Initial commit

author Pascal Spring <pascal.spring@palladium>

Wed, 15 Jun 2022 21:48:18 +0000 (23:48 +0200)

committer Pascal Spring <pascal.spring@palladium>

Wed, 15 Jun 2022 21:48:18 +0000 (23:48 +0200)
author Pascal Spring <pascal.spring@palladium>
Wed, 15 Jun 2022 21:48:18 +0000 (23:48 +0200)
committer Pascal Spring <pascal.spring@palladium>
Wed, 15 Jun 2022 21:48:18 +0000 (23:48 +0200)
diff --git a/.cproject b/.cproject

new file mode 100644 (file)

index 0000000..cf2dc67
--- /dev/null
+++ b/.cproject
@@ -0,0 +1,344 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+       
+    <storageModule moduleId="org.eclipse.cdt.core.settings">
+                       
+        <cconfiguration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1920002008">
+                               
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1920002008" moduleId="org.eclipse.cdt.core.settings" name="Release">
+                                               
+                <externalSettings/>
+                                               
+                <extensions>
+                                                       
+                    <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+                                                       
+                    <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                                                       
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                                                       
+                    <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                                                       
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                                                       
+                    <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                                               
+                </extensions>
+                                       
+            </storageModule>
+                               
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                                               
+                <configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1920002008" name="Release" optionalBuildProperties="org.eclipse.cdt.docker.launcher.containerbuild.property.selectedvolumes=,org.eclipse.cdt.docker.launcher.containerbuild.property.volumes=" parent="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release">
+                                                       
+                    <folderInfo id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1920002008." name="/" resourcePath="">
+                                                                       
+                        <toolChain id="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.release.233855040" name="ARM Cross GCC" superClass="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.release">
+                                                                               
+                            <option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash.139542648" name="Create flash image" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash" value="true" valueType="boolean"/>
+                                                                               
+                            <option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createlisting.166176329" name="Create extended listing" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createlisting"/>
+                                                                               
+                            <option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize.204458121" name="Print size" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize" value="true" valueType="boolean"/>
+                                                                               
+                            <option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.1356456702" name="Optimization Level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.size" valueType="enumerated"/>
+                                                                               
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+                                                                               
+                            <option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections.1523780790" name="Data sections (-fdata-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections" value="true" valueType="boolean"/>
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+                            <option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.438917959" name="Debug level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level"/>
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+                            <option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.1101899041" name="Debug format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format"/>
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+                            <option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family.1280345233" name="ARM family (-mcpu)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.mcpu.cortex-m0" valueType="enumerated"/>
+                                                                               
+                            <option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn.424008016" name="Enable all common warnings (-Wall)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn" value="true" valueType="boolean"/>
+                                                                               
+                            <option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.extrawarn.907715980" name="Enable extra warnings (-Wextra)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.extrawarn" value="true" valueType="boolean"/>
+                                                                               
+                            <option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.freestanding.1337145909" name="Assume freestanding environment (-ffreestanding)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.freestanding" value="true" valueType="boolean"/>
+                                                                               
+                            <option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.lto.1380214670" name="Link-time optimizer (-flto)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.lto" value="false" valueType="boolean"/>
+                                                                               
+                            <option id="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name.1497549781" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name" value="GNU MCU Eclipse ARM Embedded GCC" valueType="string"/>
+                                                                               
+                            <option id="ilg.gnuarmeclipse.managedbuild.cross.option.architecture.2102099401" name="Architecture" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.architecture" value="ilg.gnuarmeclipse.managedbuild.cross.option.architecture.arm" valueType="enumerated"/>
+                                                                               
+                            <option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset.1635599599" name="Instruction set" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset.thumb" valueType="enumerated"/>
+                                                                               
+                            <option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix.1725540197" name="Prefix" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix" value="arm-none-eabi-" valueType="string"/>
+                                                                               
+                            <option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.c.1636238479" name="C compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.c" value="gcc" valueType="string"/>
+                                                                               
+                            <option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp.950725054" name="C++ compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp" value="g++" valueType="string"/>
+                                                                               
+                            <option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.ar.1054569315" name="Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.ar" value="ar" valueType="string"/>
+                                                                               
+                            <option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy.1782929903" name="Hex/Bin converter" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy" value="objcopy" valueType="string"/>
+                                                                               
+                            <option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump.1733703649" name="Listing generator" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump" value="objdump" valueType="string"/>
+                                                                               
+                            <option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.size.187591256" name="Size command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.size" value="size" valueType="string"/>
+                                                                               
+                            <option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.make.2130031174" name="Build command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.make" value="make" valueType="string"/>
+                                                                               
+                            <option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm.799543676" name="Remove command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm" value="rm" valueType="string"/>
+                                                                               
+                            <option id="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.id.124019525" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.id" value="962691777" valueType="string"/>
+                                                                               
+                            <targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform.395447077" isAbstract="false" osList="all" superClass="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform"/>
+                                                                               
+                            <builder buildPath="${workspace_loc:/arm-electronicload}/Release" id="ilg.gnuarmeclipse.managedbuild.cross.builder.834356861" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="ilg.gnuarmeclipse.managedbuild.cross.builder"/>
+                                                                               
+                            <tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.579764077" name="GNU ARM Cross Assembler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler">
+                                                                                               
+                                <option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor.1470225809" name="Use preprocessor" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor" value="true" valueType="boolean"/>
+                                                                                               
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths.631598198" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths" valueType="includePath">
+                                                                                                       
+                                    <listOptionValue builtIn="false" value="&quot;../include&quot;"/>
+                                                                                                       
+                                    <listOptionValue builtIn="false" value="&quot;../system/include&quot;"/>
+                                                                                                       
+                                    <listOptionValue builtIn="false" value="&quot;../system/include/cmsis&quot;"/>
+                                                                                                       
+                                    <listOptionValue builtIn="false" value="&quot;../system/include/stm32f0-stdperiph&quot;"/>
+                                                                                               
+                                </option>
+                                                                                               
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs.1143866575" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs" valueType="definedSymbols">
+                                                                                                       
+                                    <listOptionValue builtIn="false" value="NDEBUG"/>
+                                                                                                       
+                                    <listOptionValue builtIn="false" value="STM32F030"/>
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+                                    <listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+                                                                                                       
+                                    <listOptionValue builtIn="false" value="HSE_VALUE=8000000"/>
+                                                                                               
+                                </option>
+                                                                                               
+                                <inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input.267595866" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input"/>
+                                                                                       
+                            </tool>
+                                                                               
+                            <tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.758732844" name="GNU ARM Cross C Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler">
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+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths.724689337" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths" useByScannerDiscovery="true" valueType="includePath">
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+                                    <listOptionValue builtIn="false" value="&quot;../system/include/cmsis&quot;"/>
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+                                    <listOptionValue builtIn="false" value="&quot;../system/include/stm32f0-stdperiph&quot;"/>
+                                                                                               
+                                </option>
+                                                                                               
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs.961771415" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs" useByScannerDiscovery="true" valueType="definedSymbols">
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+                                    <listOptionValue builtIn="false" value="NDEBUG"/>
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+                                    <listOptionValue builtIn="false" value="STM32F030"/>
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+                                    <listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
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+                                    <listOptionValue builtIn="false" value="HSE_VALUE=8000000"/>
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+                            <tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.1376600087" name="GNU ARM Cross C++ Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler">
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+                            <tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.714912098" name="GNU ARM Cross C Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker">
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+                                    <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
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+                                    <additionalInput kind="additionalinput" paths="$(LIBS)"/>
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+                            </tool>
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+                            <tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.2051990001" name="GNU ARM Cross C++ Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker">
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+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths.487316932" name="Library search path (-L)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths" valueType="libPaths">
+                                                                                                       
+                                    <listOptionValue builtIn="false" value="&quot;../ldscripts&quot;"/>
+                                                                                               
+                                </option>
+                                                                                               
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile.459973986" name="Script files (-T)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile" valueType="stringList">
+                                                                                                       
+                                    <listOptionValue builtIn="false" value="mem.ld"/>
+                                                                                                       
+                                    <listOptionValue builtIn="false" value="libs.ld"/>
+                                                                                                       
+                                    <listOptionValue builtIn="false" value="sections.ld"/>
+                                                                                               
+                                </option>
+                                                                                               
+                                <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nostart.1643796985" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nostart" value="true" valueType="boolean"/>
+                                                                                               
+                                <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.usenewlibnano.831198941" name="Use newlib-nano (--specs=nano.specs)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.usenewlibnano" value="true" valueType="boolean"/>
+                                                                                               
+                                <inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input.1477093868" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input">
+                                                                                                       
+                                    <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+                                                                                                       
+                                    <additionalInput kind="additionalinput" paths="$(LIBS)"/>
+                                                                                               
+                                </inputType>
+                                                                                       
+                            </tool>
+                                                                               
+                            <tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver.557472908" name="GNU ARM Cross Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver"/>
+                                                                               
+                            <tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash.580345143" name="GNU ARM Cross Create Flash Image" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash"/>
+                                                                               
+                            <tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting.2126002609" name="GNU ARM Cross Create Listing" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting">
+                                                                                               
+                                <option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source.1447874838" name="Display source (--source|-S)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source" value="true" valueType="boolean"/>
+                                                                                               
+                                <option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders.401519794" name="Display all headers (--all-headers|-x)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders" value="true" valueType="boolean"/>
+                                                                                               
+                                <option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle.330598880" name="Demangle names (--demangle|-C)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle" value="true" valueType="boolean"/>
+                                                                                               
+                                <option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers.203114694" name="Display line numbers (--line-numbers|-l)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers" value="true" valueType="boolean"/>
+                                                                                               
+                                <option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide.187697107" name="Wide lines (--wide|-w)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide" value="true" valueType="boolean"/>
+                                                                                       
+                            </tool>
+                                                                               
+                            <tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize.541324423" name="GNU ARM Cross Print Size" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize">
+                                                                                               
+                                <option id="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format.931879263" name="Size format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format"/>
+                                                                                       
+                            </tool>
+                                                                       
+                        </toolChain>
+                                                               
+                    </folderInfo>
+                                                       
+                    <sourceEntries>
+                                                                       
+                        <entry excluding="font32rle.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="src"/>
+                                                                       
+                        <entry excluding="src/stm32f0-stdperiph/stm32f0xx_wwdg.c|src/stm32f0-stdperiph/stm32f0xx_usart.c|src/stm32f0-stdperiph/stm32f0xx_tim.c|src/stm32f0-stdperiph/stm32f0xx_syscfg.c|src/stm32f0-stdperiph/stm32f0xx_spi.c|src/stm32f0-stdperiph/stm32f0xx_rtc.c|src/stm32f0-stdperiph/stm32f0xx_pwr.c|src/stm32f0-stdperiph/stm32f0xx_misc.c|src/stm32f0-stdperiph/stm32f0xx_iwdg.c|src/stm32f0-stdperiph/stm32f0xx_i2c.c|src/stm32f0-stdperiph/stm32f0xx_flash.c|src/stm32f0-stdperiph/stm32f0xx_exti.c|src/stm32f0-stdperiph/stm32f0xx_dma.c|src/stm32f0-stdperiph/stm32f0xx_dbgmcu.c|src/stm32f0-stdperiph/stm32f0xx_dac.c|src/stm32f0-stdperiph/stm32f0xx_crs.c|src/stm32f0-stdperiph/stm32f0xx_crc.c|src/stm32f0-stdperiph/stm32f0xx_comp.c|src/stm32f0-stdperiph/stm32f0xx_cec.c|src/stm32f0-stdperiph/stm32f0xx_can.c|src/stm32f0-stdperiph/stm32f0xx_adc.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="system"/>
+                                                               
+                    </sourceEntries>
+                                               
+                </configuration>
+                                       
+            </storageModule>
+                               
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+                       
+        </cconfiguration>
+               
+    </storageModule>
+       
+    <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                       
+        <project id="arm-electronicload.ilg.gnuarmeclipse.managedbuild.cross.target.elf.2028348947" name="Executable" projectType="ilg.gnuarmeclipse.managedbuild.cross.target.elf"/>
+               
+    </storageModule>
+       
+    <storageModule moduleId="scannerConfiguration">
+                       
+        <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+                       
+        <scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1920002008;ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1920002008.;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.758732844;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.1655308157">
+                               
+            <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+                       
+        </scannerConfigBuildInfo>
+               
+    </storageModule>
+       
+    <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+       
+    <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+       
+    <storageModule moduleId="refreshScope" versionNumber="2">
+                       
+        <configuration configurationName="Release">
+                               
+            <resource resourceType="PROJECT" workspacePath="/arm-electronicload"/>
+                       
+        </configuration>
+               
+    </storageModule>
+    
+</cproject>
diff --git a/.project b/.project

new file mode 100644 (file)

index 0000000..4172f3a
--- /dev/null
+++ b/.project
@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+       <name>arm-electronicload</name>
+       <comment></comment>
+       <projects>
+       </projects>
+       <buildSpec>
+               <buildCommand>
+                       <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+                       <triggers>clean,full,incremental,</triggers>
+                       <arguments>
+                       </arguments>
+               </buildCommand>
+               <buildCommand>
+                       <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+                       <triggers>full,incremental,</triggers>
+                       <arguments>
+                       </arguments>
+               </buildCommand>
+       </buildSpec>
+       <natures>
+               <nature>org.eclipse.cdt.core.cnature</nature>
+               <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+               <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+               <nature>org.eclipse.cdt.core.ccnature</nature>
+       </natures>
+</projectDescription>
diff --git a/.settings/language.settings.xml b/.settings/language.settings.xml

new file mode 100644 (file)

index 0000000..1a5f010
--- /dev/null
+++ b/.settings/language.settings.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+       <configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1920002008" name="Release">
+               <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+                       <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+                       <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+                       <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+                       <provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1980355196191527485" id="org.eclipse.embedcdt.managedbuild.cross.arm.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT Arm Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+                               <language-scope id="org.eclipse.cdt.core.gcc"/>
+                               <language-scope id="org.eclipse.cdt.core.g++"/>
+                       </provider>
+               </extension>
+       </configuration>
+</project>
+\ No newline at end of file
diff --git a/Release/arm-electronicload-rework.map b/Release/arm-electronicload-rework.map

new file mode 100644 (file)

index 0000000..2d554ac
--- /dev/null
+++ b/Release/arm-electronicload-rework.map
@@ -0,0 +1,2865 @@
+Archive member included to satisfy reference by file (symbol)
+
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(_thumb1_case_uqi.o)
+                              ./src/ili9341gfx.o (__gnu_thumb1_case_uqi)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(_thumb1_case_shi.o)
+                              ./src/main.o (__gnu_thumb1_case_shi)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(_udivsi3.o)
+                              ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o (__aeabi_uidiv)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(_divsi3.o)
+                              ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o (__aeabi_idiv)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(_dvmd_tls.o)
+                              /usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(_udivsi3.o) (__aeabi_idiv0)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(_arm_cmpsf2.o)
+                              ./src/main.o (__aeabi_fcmpge)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(_fixunssfsi.o)
+                              ./src/main.o (__aeabi_f2uiz)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(addsf3.o)
+                              ./src/main.o (__aeabi_fadd)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(divsf3.o)
+                              ./src/main.o (__aeabi_fdiv)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(eqsf2.o)
+                              /usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(_arm_cmpsf2.o) (__eqsf2)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(gesf2.o)
+                              /usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(_arm_cmpsf2.o) (__gesf2)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(lesf2.o)
+                              /usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(_arm_cmpsf2.o) (__lesf2)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(mulsf3.o)
+                              ./src/main.o (__aeabi_fmul)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(subsf3.o)
+                              /usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(_fixunssfsi.o) (__aeabi_fsub)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(fixsfsi.o)
+                              /usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(_fixunssfsi.o) (__aeabi_f2iz)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(floatsisf.o)
+                              ./src/main.o (__aeabi_i2f)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(floatunsisf.o)
+                              ./src/main.o (__aeabi_ui2f)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(_clzsi2.o)
+                              /usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(addsf3.o) (__clzsi2)
+/usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libg_nano.a(lib_a-errno.o)
+                              ./system/src/newlib/_sbrk.o (__errno)
+/usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libg_nano.a(lib_a-impure.o)
+                              /usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libg_nano.a(lib_a-errno.o) (_impure_ptr)
+/usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libg_nano.a(lib_a-memset.o)
+                              ./src/main.o (memset)
+
+Allocating common symbols
+Common symbol       size              file
+
+timer_delayCount    0x4               ./src/delay.o
+textbgcolour        0x2               ./src/ili9341gfx.o
+errno               0x4               ./system/src/newlib/_syscalls.o
+cursor_y            0x2               ./src/ili9341gfx.o
+iactualx            0x2               ./src/ili9341gfx.o
+iactualy            0x2               ./src/ili9341gfx.o
+vactualx            0x2               ./src/ili9341gfx.o
+isetx               0x2               ./src/ili9341gfx.o
+vsety               0x2               ./src/ili9341gfx.o
+I2C_InitStructure   0x1c              ./src/main.o
+vsetx               0x2               ./src/ili9341gfx.o
+vactualy            0x2               ./src/ili9341gfx.o
+GPIO_InitStructure  0x8               ./src/main.o
+enc_delta           0x1               ./src/main.o
+textcolour          0x2               ./src/ili9341gfx.o
+cursor_x            0x2               ./src/ili9341gfx.o
+textsize            0x1               ./src/ili9341gfx.o
+isety               0x2               ./src/ili9341gfx.o
+
+Discarded input sections
+
+ .text          0x0000000000000000        0x0 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .data          0x0000000000000000        0x0 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .bss           0x0000000000000000        0x0 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .text.GPIO_DeInit
+                0x0000000000000000       0xac ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .text.GPIO_Init
+                0x0000000000000000       0x7a ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .text.GPIO_StructInit
+                0x0000000000000000       0x18 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .text.GPIO_PinLockConfig
+                0x0000000000000000       0x24 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .text.GPIO_ReadInputDataBit
+                0x0000000000000000        0xc ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .text.GPIO_ReadInputData
+                0x0000000000000000        0x6 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .text.GPIO_ReadOutputDataBit
+                0x0000000000000000        0xc ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .text.GPIO_ReadOutputData
+                0x0000000000000000        0x6 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .text.GPIO_SetBits
+                0x0000000000000000        0x4 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .text.GPIO_ResetBits
+                0x0000000000000000        0x4 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .text.GPIO_WriteBit
+                0x0000000000000000        0xc ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .text.GPIO_Write
+                0x0000000000000000        0x4 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .text.GPIO_PinAFConfig
+                0x0000000000000000       0x22 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .debug_info    0x0000000000000000      0x688 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .debug_abbrev  0x0000000000000000      0x1f1 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .debug_loc     0x0000000000000000      0x334 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .debug_aranges
+                0x0000000000000000       0x80 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .debug_ranges  0x0000000000000000       0x70 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .debug_line    0x0000000000000000      0x265 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .debug_str     0x0000000000000000      0x511 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .comment       0x0000000000000000       0x58 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .debug_frame   0x0000000000000000      0x108 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .ARM.attributes
+                0x0000000000000000       0x31 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .text          0x0000000000000000        0x0 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .data          0x0000000000000000        0x0 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .bss           0x0000000000000000        0x0 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_DeInit
+                0x0000000000000000       0x60 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_HSEConfig
+                0x0000000000000000       0x10 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_AdjustHSICalibrationValue
+                0x0000000000000000       0x14 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_HSICmd
+                0x0000000000000000       0x1c ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_AdjustHSI14CalibrationValue
+                0x0000000000000000       0x14 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_HSI14Cmd
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+ .rodata        0x0000000000000000        0x4 /usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libg_nano.a(lib_a-impure.o)
+ .debug_info    0x0000000000000000      0x8a4 /usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libg_nano.a(lib_a-impure.o)
+ .debug_abbrev  0x0000000000000000      0x15c /usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libg_nano.a(lib_a-impure.o)
+ .debug_aranges
+                0x0000000000000000       0x18 /usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libg_nano.a(lib_a-impure.o)
+ .debug_line    0x0000000000000000       0xd4 /usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libg_nano.a(lib_a-impure.o)
+ .debug_str     0x0000000000000000      0x5c6 /usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libg_nano.a(lib_a-impure.o)
+ .comment       0x0000000000000000       0x58 /usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libg_nano.a(lib_a-impure.o)
+ .ARM.attributes
+                0x0000000000000000       0x2c /usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libg_nano.a(lib_a-impure.o)
+ .data          0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libg_nano.a(lib_a-memset.o)
+ .bss           0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libg_nano.a(lib_a-memset.o)
+
+Memory Configuration
+
+Name             Origin             Length             Attributes
+RAM              0x0000000020000000 0x0000000000002000 xrw
+CCMRAM           0x0000000000000000 0x0000000000000000 xrw
+FLASH            0x0000000008000000 0x0000000000010000 xr
+FLASHB1          0x0000000000000000 0x0000000000000000 xr
+EXTMEMB0         0x0000000000000000 0x0000000000000000 xr
+EXTMEMB1         0x0000000000000000 0x0000000000000000 xr
+EXTMEMB2         0x0000000000000000 0x0000000000000000 xr
+EXTMEMB3         0x0000000000000000 0x0000000000000000 xr
+MEMORY_ARRAY     0x0000000000000000 0x0000000000000000 xrw
+*default*        0x0000000000000000 0xffffffffffffffff
+
+Linker script and memory map
+
+LOAD ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+LOAD ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+LOAD ./system/src/newlib/_cxx.o
+LOAD ./system/src/newlib/_exit.o
+LOAD ./system/src/newlib/_sbrk.o
+LOAD ./system/src/newlib/_startup.o
+LOAD ./system/src/newlib/_syscalls.o
+LOAD ./system/src/newlib/assert.o
+LOAD ./system/src/diag/Trace.o
+LOAD ./system/src/diag/trace_impl.o
+LOAD ./system/src/cortexm/_initialize_hardware.o
+LOAD ./system/src/cortexm/_reset_hardware.o
+LOAD ./system/src/cortexm/exception_handlers.o
+LOAD ./system/src/cmsis/system_stm32f0xx.o
+LOAD ./system/src/cmsis/vectors_stm32f0xx.o
+LOAD ./src/BlinkLed.o
+LOAD ./src/_write.o
+LOAD ./src/delay.o
+LOAD ./src/font16.o
+LOAD ./src/font32.o
+LOAD ./src/font64.o
+LOAD ./src/font72.o
+LOAD ./src/font7s.o
+LOAD ./src/font8.o
+LOAD ./src/font_courier.o
+LOAD ./src/i2c.o
+LOAD ./src/ili9341.o
+LOAD ./src/ili9341gfx.o
+LOAD ./src/main.o
+LOAD ./src/mcp24aaxx.o
+LOAD /usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libstdc++_nano.a
+LOAD /usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libm.a
+START GROUP
+LOAD /usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a
+LOAD /usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libg_nano.a
+LOAD /usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libc_nano.a
+END GROUP
+START GROUP
+LOAD /usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a
+LOAD /usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libc_nano.a
+END GROUP
+                0x0000000020002000                __stack = (ORIGIN (RAM) + LENGTH (RAM))
+                0x0000000020002000                _estack = __stack
+                0x0000000000000400                __Main_Stack_Size = 0x400
+                [!provide]                        PROVIDE (_Main_Stack_Size = __Main_Stack_Size)
+                0x0000000020001c00                __Main_Stack_Limit = (__stack - __Main_Stack_Size)
+                [!provide]                        PROVIDE (_Main_Stack_Limit = __Main_Stack_Limit)
+                0x0000000000000100                _Minimum_Stack_Size = 0x100
+                0x0000000020000078                PROVIDE (_Heap_Begin = _end_noinit)
+                0x0000000020001c00                PROVIDE (_Heap_Limit = (__stack - __Main_Stack_Size))
+
+.isr_vector     0x0000000008000000      0x1ae
+ FILL mask 0xff
+                0x0000000008000000                __vectors_start = ABSOLUTE (.)
+                0x0000000008000000                __vectors_start__ = ABSOLUTE (.)
+ *(.isr_vector)
+ .isr_vector    0x0000000008000000       0xc4 ./system/src/cmsis/vectors_stm32f0xx.o
+                0x0000000008000000                g_pfnVectors
+ *(.cfmconfig)
+ *(.after_vectors .after_vectors.*)
+ .after_vectors
+                0x00000000080000c4       0xb8 ./system/src/newlib/_startup.o
+                0x00000000080000c4                _start
+ .after_vectors
+                0x000000000800017c       0x30 ./system/src/cortexm/exception_handlers.o
+                0x000000000800017c                Reset_Handler
+                0x0000000008000180                NMI_Handler
+                0x0000000008000182                HardFault_Handler
+                0x000000000800019a                HardFault_Handler_C
+                0x000000000800019c                SVC_Handler
+                0x000000000800019e                PendSV_Handler
+ .after_vectors
+                0x00000000080001ac        0x2 ./system/src/cmsis/vectors_stm32f0xx.o
+                0x00000000080001ac                TIM1_CC_IRQHandler
+                0x00000000080001ac                TSC_IRQHandler
+                0x00000000080001ac                ADC1_COMP_IRQHandler
+                0x00000000080001ac                TIM6_IRQHandler
+                0x00000000080001ac                PVD_IRQHandler
+                0x00000000080001ac                I2C1_IRQHandler
+                0x00000000080001ac                RCC_CRS_IRQHandler
+                0x00000000080001ac                SPI1_IRQHandler
+                0x00000000080001ac                TIM6_DAC_IRQHandler
+                0x00000000080001ac                USART3_4_IRQHandler
+                0x00000000080001ac                ADC1_IRQHandler
+                0x00000000080001ac                I2C2_IRQHandler
+                0x00000000080001ac                USART3_6_IRQHandler
+                0x00000000080001ac                TIM17_IRQHandler
+                0x00000000080001ac                CEC_CAN_IRQHandler
+                0x00000000080001ac                PVD_VDDIO2_IRQHandler
+                0x00000000080001ac                DMA1_Channel4_5_6_7_IRQHandler
+                0x00000000080001ac                TIM3_IRQHandler
+                0x00000000080001ac                RCC_IRQHandler
+                0x00000000080001ac                EXTI4_15_IRQHandler
+                0x00000000080001ac                USART3_8_IRQHandler
+                0x00000000080001ac                DMA1_Channel1_IRQHandler
+                0x00000000080001ac                Default_Handler
+                0x00000000080001ac                CEC_IRQHandler
+                0x00000000080001ac                DMA1_Channel4_5_IRQHandler
+                0x00000000080001ac                TIM7_IRQHandler
+                0x00000000080001ac                EXTI0_1_IRQHandler
+                0x00000000080001ac                USB_IRQHandler
+                0x00000000080001ac                SPI2_IRQHandler
+                0x00000000080001ac                DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
+                0x00000000080001ac                DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
+                0x00000000080001ac                TS_IRQHandler
+                0x00000000080001ac                WWDG_IRQHandler
+                0x00000000080001ac                TIM2_IRQHandler
+                0x00000000080001ac                DMA1_Channel2_3_IRQHandler
+                0x00000000080001ac                USART2_IRQHandler
+                0x00000000080001ac                VDDIO2_IRQHandler
+                0x00000000080001ac                FLASH_IRQHandler
+                0x00000000080001ac                USART1_IRQHandler
+                0x00000000080001ac                TIM1_BRK_UP_TRG_COM_IRQHandler
+
+.inits          0x00000000080001b0       0x28
+                0x00000000080001b0                __data_regions_array_start = .
+                0x00000000080001b0        0x4 LONG 0x80078b8 LOADADDR (.data)
+                0x00000000080001b4        0x4 LONG 0x20000000 ADDR (.data)
+                0x00000000080001b8        0x4 LONG 0x20000024 (ADDR (.data) + SIZEOF (.data))
+                0x00000000080001bc        0x4 LONG 0x80078b8 LOADADDR (.data_CCMRAM)
+                0x00000000080001c0        0x4 LONG 0x0 ADDR (.data_CCMRAM)
+                0x00000000080001c4        0x4 LONG 0x0 (ADDR (.data_CCMRAM) + SIZEOF (.data_CCMRAM))
+                0x00000000080001c8                __data_regions_array_end = .
+                0x00000000080001c8                __bss_regions_array_start = .
+                0x00000000080001c8        0x4 LONG 0x20000024 ADDR (.bss)
+                0x00000000080001cc        0x4 LONG 0x20000078 (ADDR (.bss) + SIZEOF (.bss))
+                0x00000000080001d0        0x4 LONG 0x0 ADDR (.bss_CCMRAM)
+                0x00000000080001d4        0x4 LONG 0x0 (ADDR (.bss_CCMRAM) + SIZEOF (.bss_CCMRAM))
+                0x00000000080001d8                __bss_regions_array_end = .
+ *(.init)
+ *(.fini)
+                0x00000000080001d8                . = ALIGN (0x4)
+                0x00000000080001d8                PROVIDE (__preinit_array_start = .)
+ *(.preinit_array_sysinit .preinit_array_sysinit.*)
+ *(.preinit_array_platform .preinit_array_platform.*)
+ *(.preinit_array .preinit_array.*)
+                0x00000000080001d8                PROVIDE (__preinit_array_end = .)
+                0x00000000080001d8                . = ALIGN (0x4)
+                0x00000000080001d8                PROVIDE (__init_array_start = .)
+ *(SORT_BY_NAME(.init_array.*))
+ *(.init_array)
+                0x00000000080001d8                PROVIDE (__init_array_end = .)
+                0x00000000080001d8                . = ALIGN (0x4)
+                0x00000000080001d8                PROVIDE (__fini_array_start = .)
+ *(SORT_BY_NAME(.fini_array.*))
+ *(.fini_array)
+                0x00000000080001d8                PROVIDE (__fini_array_end = .)
+
+.flashtext
+ *(.flashtext .flashtext.*)
+
+.text           0x00000000080001d8     0x76e0
+ *(.text .text.*)
+ .text._exit    0x00000000080001d8        0x6 ./system/src/newlib/_exit.o
+                0x00000000080001d8                _exit
+ *fill*         0x00000000080001de        0x2 
+ .text.__initialize_args
+                0x00000000080001e0       0x10 ./system/src/newlib/_syscalls.o
+                0x00000000080001e0                __initialize_args
+ .text.__initialize_hardware_early
+                0x00000000080001f0        0x8 ./system/src/cortexm/_initialize_hardware.o
+                0x00000000080001f0                __initialize_hardware_early
+ .text.__initialize_hardware
+                0x00000000080001f8        0x8 ./system/src/cortexm/_initialize_hardware.o
+                0x00000000080001f8                __initialize_hardware
+ .text.__reset_hardware
+                0x0000000008000200       0x1c ./system/src/cortexm/_reset_hardware.o
+                0x0000000008000200                __reset_hardware
+ .text.SystemInit
+                0x000000000800021c       0xf8 ./system/src/cmsis/system_stm32f0xx.o
+                0x000000000800021c                SystemInit
+ .text.SystemCoreClockUpdate
+                0x0000000008000314       0x64 ./system/src/cmsis/system_stm32f0xx.o
+                0x0000000008000314                SystemCoreClockUpdate
+ .text.delay_init
+                0x0000000008000378       0x44 ./src/delay.o
+                0x0000000008000378                delay_init
+ .text.timer_sleep
+                0x00000000080003bc       0x10 ./src/delay.o
+                0x00000000080003bc                timer_sleep
+ .text.timer_tick
+                0x00000000080003cc       0x14 ./src/delay.o
+                0x00000000080003cc                timer_tick
+ .text.delay_ms
+                0x00000000080003e0        0x8 ./src/delay.o
+                0x00000000080003e0                delay_ms
+ .text.SysTick_Handler
+                0x00000000080003e8        0x8 ./src/delay.o
+                0x00000000080003e8                SysTick_Handler
+ .text.i2c_init
+                0x00000000080003f0       0x44 ./src/i2c.o
+                0x00000000080003f0                i2c_init
+ .text.i2c_start
+                0x0000000008000434       0x14 ./src/i2c.o
+                0x0000000008000434                i2c_start
+ .text.i2c_stop
+                0x0000000008000448       0x14 ./src/i2c.o
+                0x0000000008000448                i2c_stop
+ .text.i2c_autoend
+                0x000000000800045c       0x10 ./src/i2c.o
+                0x000000000800045c                i2c_autoend
+ .text.i2c_set_nbytes
+                0x000000000800046c       0x1c ./src/i2c.o
+                0x000000000800046c                i2c_set_nbytes
+ .text.i2c_read_ack
+                0x0000000008000488       0x14 ./src/i2c.o
+                0x0000000008000488                i2c_read_ack
+ .text.i2c_read_nack
+                0x000000000800049c       0x20 ./src/i2c.o
+                0x000000000800049c                i2c_read_nack
+ .text.i2c_write_addr
+                0x00000000080004bc       0x24 ./src/i2c.o
+                0x00000000080004bc                i2c_write_addr
+ .text.i2c_write
+                0x00000000080004e0       0x14 ./src/i2c.o
+                0x00000000080004e0                i2c_write
+ .text.ili9341_hard_init
+                0x00000000080004f4       0x12 ./src/ili9341.o
+                0x00000000080004f4                ili9341_hard_init
+ .text.ili9341_hard_reset
+                0x0000000008000506       0x22 ./src/ili9341.o
+                0x0000000008000506                ili9341_hard_reset
+ .text.ili9341_spi_send
+                0x0000000008000528       0x34 ./src/ili9341.o
+                0x0000000008000528                ili9341_spi_send
+ .text.ili9341_writecommand8
+                0x000000000800055c       0x10 ./src/ili9341.o
+                0x000000000800055c                ili9341_writecommand8
+ .text.ili9341_writedata8
+                0x000000000800056c       0x10 ./src/ili9341.o
+                0x000000000800056c                ili9341_writedata8
+ .text.ili9341_setaddress
+                0x000000000800057c       0x50 ./src/ili9341.o
+                0x000000000800057c                ili9341_setaddress
+ .text.ili9341_init
+                0x00000000080005cc      0x206 ./src/ili9341.o
+                0x00000000080005cc                ili9341_init
+ .text.ili9341_pushcolour
+                0x00000000080007d2       0x12 ./src/ili9341.o
+                0x00000000080007d2                ili9341_pushcolour
+ .text.ili9341_clear
+                0x00000000080007e4       0x48 ./src/ili9341.o
+                0x00000000080007e4                ili9341_clear
+ .text.ili9341_drawpixel
+                0x000000000800082c       0x30 ./src/ili9341.o
+                0x000000000800082c                ili9341_drawpixel
+ .text.ili9341_drawvline
+                0x000000000800085c       0x50 ./src/ili9341.o
+                0x000000000800085c                ili9341_drawvline
+ .text.ili9341_drawhline
+                0x00000000080008ac       0x50 ./src/ili9341.o
+                0x00000000080008ac                ili9341_drawhline
+ .text.ili9341_fillrect
+                0x00000000080008fc       0x74 ./src/ili9341.o
+                0x00000000080008fc                ili9341_fillrect
+ .text.ili9341_setRotation
+                0x0000000008000970       0x50 ./src/ili9341.o
+                0x0000000008000970                ili9341_setRotation
+ .text.ili9341_setcursor
+                0x00000000080009c0       0x14 ./src/ili9341gfx.o
+                0x00000000080009c0                ili9341_setcursor
+ .text.ili9341_settextcolour
+                0x00000000080009d4       0x14 ./src/ili9341gfx.o
+                0x00000000080009d4                ili9341_settextcolour
+ .text.ili9341_settextsize
+                0x00000000080009e8       0x14 ./src/ili9341gfx.o
+                0x00000000080009e8                ili9341_settextsize
+ .text.ili9341_drawUnicode
+                0x00000000080009fc      0x1d0 ./src/ili9341gfx.o
+                0x00000000080009fc                ili9341_drawUnicode
+ .text.ili9341_write
+                0x0000000008000bcc       0xcc ./src/ili9341gfx.o
+                0x0000000008000bcc                ili9341_write
+ .text.ili9341_out
+                0x0000000008000c98       0x1a ./src/ili9341gfx.o
+                0x0000000008000c98                ili9341_out
+ .text.i_to_a   0x0000000008000cb2       0x32 ./src/main.o
+                0x0000000008000cb2                i_to_a
+ .text.encode_init
+                0x0000000008000ce4       0x30 ./src/main.o
+                0x0000000008000ce4                encode_init
+ .text.encode_read4
+                0x0000000008000d14       0x14 ./src/main.o
+                0x0000000008000d14                encode_read4
+ .text.mcp4728_set_reference
+                0x0000000008000d28       0x48 ./src/main.o
+                0x0000000008000d28                mcp4728_set_reference
+ .text.mcp4728_set_gain
+                0x0000000008000d70       0x48 ./src/main.o
+                0x0000000008000d70                mcp4728_set_gain
+ .text.mcp4728_set_pd
+                0x0000000008000db8       0x54 ./src/main.o
+                0x0000000008000db8                mcp4728_set_pd
+ .text.mcp4728_write_fast_dac
+                0x0000000008000e0c       0x68 ./src/main.o
+                0x0000000008000e0c                mcp4728_write_fast_dac
+ .text.mcp3426_config
+                0x0000000008000e74       0x40 ./src/main.o
+                0x0000000008000e74                mcp3426_config
+ .text.mcp3426_read
+                0x0000000008000eb4       0x94 ./src/main.o
+                0x0000000008000eb4                mcp3426_read
+ .text.mcp3421_config
+                0x0000000008000f48       0x40 ./src/main.o
+                0x0000000008000f48                mcp3421_config
+ .text.mcp3421_read
+                0x0000000008000f88       0x7c ./src/main.o
+                0x0000000008000f88                mcp3421_read
+ .text.mcp9808_read
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+                0x0000000008005cd8                chr_f32_7C
+ .rodata.chr_f32_7D
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+                0x0000000008005d0c                chr_f32_7D
+ .rodata.chr_f32_7E
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+                0x0000000008005d40                chr_f32_7E
+ .rodata.chr_f32_7F
+                0x0000000008005d8e       0x1a ./src/font32.o
+                0x0000000008005d8e                chr_f32_7F
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+                0x0000000008005da8                chr_f32_80
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+                0x0000000008005df6                chr_f32_81
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+                0x0000000008005e44                chrtbl_f32
+ .rodata.widtbl_f32
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+                0x0000000008005fcc                widtbl_f32
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+                0x000000000800602e                chr_f64_20
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+                0x000000000800608e                chr_f64_2D
+ .rodata.chr_f64_2E
+                0x000000000800611e       0x90 ./src/font64.o
+                0x000000000800611e                chr_f64_2E
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+                0x00000000080061ae                chr_f64_30
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+                0x000000000800626e                chr_f64_31
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+                0x000000000800632e       0xc0 ./src/font64.o
+                0x000000000800632e                chr_f64_32
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+                0x00000000080063ee                chr_f64_33
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+                0x00000000080064ae                chr_f64_34
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+                0x000000000800656e                chr_f64_35
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+                0x000000000800662e                chr_f64_36
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+                0x00000000080066ee                chr_f64_37
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+                0x00000000080067ae                chr_f64_38
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+                0x000000000800686e                chr_f64_39
+ .rodata.chr_f64_3A
+                0x000000000800692e       0x90 ./src/font64.o
+                0x000000000800692e                chr_f64_3A
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+                0x00000000080069be                chr_f64_61
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+                0x0000000008006a7e                chr_f64_6D
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+                0x0000000008006b9e                chr_f64_70
+ *fill*         0x0000000008006c5e        0x2 
+ .rodata.chrtbl_f64
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+                0x0000000008006c60                chrtbl_f64
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+                0x0000000008006de0       0x60 ./src/font64.o
+                0x0000000008006de0                widtbl_f64
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+                0x0000000008006e40                widtbl_f72
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+                0x0000000008006ea0       0x60 ./src/font7s.o
+                0x0000000008006ea0                widtbl_f7s
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+                0x0000000008006f00                chr_fc_20
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+                0x0000000008006f11                chr_fc_21
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+                0x0000000008006f22                chr_fc_22
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+                0x0000000008006f33                chr_fc_23
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+                0x0000000008006f44       0x11 ./src/font_courier.o
+                0x0000000008006f44                chr_fc_24
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+                0x0000000008006f55                chr_fc_25
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+                0x0000000008006f66                chr_fc_26
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+                0x0000000008006f88                chr_fc_28
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+                0x0000000008006f99                chr_fc_29
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+                0x0000000008006faa                chr_fc_2A
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+                0x0000000008006fbb                chr_fc_2B
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+                0x0000000008006fcc                chr_fc_2C
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+                0x0000000008006fdd                chr_fc_2D
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+                0x0000000008006fee       0x11 ./src/font_courier.o
+                0x0000000008006fee                chr_fc_2E
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+                0x0000000008006fff                chr_fc_2F
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+                0x0000000008007032                chr_fc_32
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+                0x00000000080070ba                chr_fc_3A
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+                0x00000000080070cb                chr_fc_3B
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+                0x00000000080070dc                chr_fc_3C
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+                0x00000000080070ed                chr_fc_3D
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+                0x00000000080070fe                chr_fc_3E
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+                0x000000000800710f                chr_fc_3F
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+                0x00000000080071db                chr_fc_4B
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+                0x000000000800752d                chr_fc_7D
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+                0x000000000800753e       0x11 ./src/font_courier.o
+                0x000000000800753e                chr_fc_7E
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+                0x000000000800754f                chr_fc_7F
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+                0x0000000008007560                chrtbl_fc
+ .rodata.widtbl_fc
+                0x00000000080076e0       0x60 ./src/font_courier.o
+                0x00000000080076e0                widtbl_fc
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+                0x0000000008007740       0x95 ./src/main.o
+ .rodata.show_amperes.str1.1
+                0x00000000080077d5        0x4 ./src/main.o
+ .rodata.show_cutoffvoltage.str1.1
+                0x00000000080077d9        0x4 ./src/main.o
+ .rodata.show_dacvals.str1.1
+                0x00000000080077dd        0x4 ./src/main.o
+                                          0x2 (size before relaxing)
+ .rodata.show_readbackcurrent.str1.1
+                0x00000000080077dd        0x2 ./src/main.o
+                                          0x4 (size before relaxing)
+ .rodata.show_status.str1.1
+                0x00000000080077df       0x10 ./src/main.o
+ .rodata.show_temperature.str1.1
+                0x00000000080077ef        0x4 ./src/main.o
+ .rodata.show_voltage.str1.1
+                0x00000000080077f3        0x2 ./src/main.o
+ .rodata.show_watt.str1.1
+                0x00000000080077f5        0x2 ./src/main.o
+ *fill*         0x00000000080077f7        0x1 
+ .rodata        0x00000000080077f8       0x80 /usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(divsf3.o)
+ .rodata        0x0000000008007878       0x40 /usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(mulsf3.o)
+ *(vtable)
+ *(.eh_frame*)
+ *(.glue_7)
+ .glue_7        0x00000000080078b8        0x0 linker stubs
+ *(.glue_7t)
+ .glue_7t       0x00000000080078b8        0x0 linker stubs
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+ .v4_bx         0x00000000080078b8        0x0 linker stubs
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+ .rel.iplt      0x00000000080078b8        0x0 ./system/src/newlib/_exit.o
+
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+                0x00000000080078b8                . = ALIGN (0x4)
+                0x00000000080078b8                __exidx_start = .
+
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+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+                0x00000000080078b8                __exidx_end = .
+                0x00000000080078b8                . = ALIGN (0x4)
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+                0x00000000080078b8                __etext = .
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+ FILL mask 0xff
+ *(.data.CCMRAM .data.CCMRAM.*)
+                0x0000000000000000                . = ALIGN (0x4)
+                0x00000000080078b8                _sidata = LOADADDR (.data)
+
+.data           0x0000000020000000       0x24 load address 0x00000000080078b8
+ FILL mask 0xff
+                0x0000000020000000                _sdata = .
+                0x0000000020000000                __data_start__ = .
+ *(.data_begin .data_begin.*)
+ *(.data .data.*)
+ .data.argv.4312
+                0x0000000020000000        0x8 ./system/src/newlib/_syscalls.o
+ .data.AHBPrescTable
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+                0x0000000020000008                AHBPrescTable
+ .data.SystemCoreClock
+                0x0000000020000018        0x4 ./system/src/cmsis/system_stm32f0xx.o
+                0x0000000020000018                SystemCoreClock
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+                0x000000002000001c                LCD_H
+ .data.LCD_W    0x000000002000001e        0x2 ./src/ili9341.o
+                0x000000002000001e                LCD_W
+ .data.check_temp
+                0x0000000020000020        0x1 ./src/main.o
+                0x0000000020000020                check_temp
+ .data.read_adc
+                0x0000000020000021        0x1 ./src/main.o
+                0x0000000020000021                read_adc
+ .data.set_mode
+                0x0000000020000022        0x1 ./src/main.o
+                0x0000000020000022                set_mode
+ *(.data_end .data_end.*)
+                0x0000000020000024                . = ALIGN (0x4)
+ *fill*         0x0000000020000023        0x1 ff
+                0x0000000020000024                _edata = .
+                0x0000000020000024                __data_end__ = .
+
+.igot.plt       0x0000000020000024        0x0 load address 0x00000000080078dc
+ .igot.plt      0x0000000020000024        0x0 ./system/src/newlib/_exit.o
+
+.bss_CCMRAM     0x0000000000000000        0x0
+ *(.bss.CCMRAM .bss.CCMRAM.*)
+
+.bss            0x0000000020000024       0x54
+                0x0000000020000024                __bss_start__ = .
+                0x0000000020000024                _sbss = .
+ *(.bss_begin .bss_begin.*)
+ *(.bss .bss.*)
+ .bss.name.4311
+                0x0000000020000024        0x1 ./system/src/newlib/_syscalls.o
+ *fill*         0x0000000020000025        0x1 
+ .bss.btn_hb    0x0000000020000026        0x2 ./src/main.o
+                0x0000000020000026                btn_hb
+ .bss.enc_last  0x0000000020000028        0x1 ./src/main.o
+ .bss.keyfunc   0x0000000020000029        0x1 ./src/main.o
+                0x0000000020000029                keyfunc
+ .bss.run       0x000000002000002a        0x1 ./src/main.o
+                0x000000002000002a                run
+ .bss.timeout   0x000000002000002b        0x1 ./src/main.o
+                0x000000002000002b                timeout
+ .bss.timer     0x000000002000002c        0x2 ./src/main.o
+                0x000000002000002c                timer
+ *(COMMON)
+ *fill*         0x000000002000002e        0x2 
+ COMMON         0x0000000020000030        0x4 ./src/delay.o
+                0x0000000020000030                timer_delayCount
+ COMMON         0x0000000020000034       0x1a ./src/ili9341gfx.o
+                0x0000000020000034                textbgcolour
+                0x0000000020000036                cursor_y
+                0x0000000020000038                iactualx
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+                0x0000000020000040                vsety
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+                0x0000000020000044                vactualy
+                0x0000000020000046                textcolour
+                0x0000000020000048                cursor_x
+                0x000000002000004a                textsize
+                0x000000002000004c                isety
+ *fill*         0x000000002000004e        0x2 
+ COMMON         0x0000000020000050       0x25 ./src/main.o
+                0x0000000020000050                I2C_InitStructure
+                0x000000002000006c                GPIO_InitStructure
+                0x0000000020000074                enc_delta
+ *(.bss_end .bss_end.*)
+                0x0000000020000078                . = ALIGN (0x4)
+ *fill*         0x0000000020000075        0x3 
+                0x0000000020000078                __bss_end__ = .
+                0x0000000020000078                _ebss = .
+
+.noinit_CCMRAM
+ *(.noinit.CCMRAM .noinit.CCMRAM.*)
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+                0x0000000020000078                _noinit = .
+ *(.noinit .noinit.*)
+                0x0000000020000078                . = ALIGN (0x4)
+                0x0000000020000078                _end_noinit = .
+                [!provide]                        PROVIDE (end = _end_noinit)
+                [!provide]                        PROVIDE (_end = _end_noinit)
+                [!provide]                        PROVIDE (__end = _end_noinit)
+                [!provide]                        PROVIDE (__end__ = _end_noinit)
+
+._check_stack   0x0000000020000078      0x100
+                0x0000000020000178                . = (. + _Minimum_Stack_Size)
+ *fill*         0x0000000020000078      0x100 
+
+.b1text
+ *(.b1text)
+ *(.b1rodata)
+ *(.b1rodata.*)
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+ *(.eb3text)
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+
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+ *(.stab.exclstr)
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+ *(.stab.indexstr)
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+                                         0x58 (size before relaxing)
+ .comment       0x0000000000000057       0x58 ./system/src/newlib/_startup.o
+ .comment       0x0000000000000057       0x58 ./system/src/newlib/_syscalls.o
+ .comment       0x0000000000000057       0x58 ./system/src/cortexm/_initialize_hardware.o
+ .comment       0x0000000000000057       0x58 ./system/src/cortexm/_reset_hardware.o
+ .comment       0x0000000000000057       0x58 ./system/src/cortexm/exception_handlers.o
+ .comment       0x0000000000000057       0x58 ./system/src/cmsis/system_stm32f0xx.o
+ .comment       0x0000000000000057       0x58 ./system/src/cmsis/vectors_stm32f0xx.o
+ .comment       0x0000000000000057       0x58 ./src/delay.o
+ .comment       0x0000000000000057       0x58 ./src/font16.o
+ .comment       0x0000000000000057       0x58 ./src/font32.o
+ .comment       0x0000000000000057       0x58 ./src/font64.o
+ .comment       0x0000000000000057       0x58 ./src/font72.o
+ .comment       0x0000000000000057       0x58 ./src/font7s.o
+ .comment       0x0000000000000057       0x58 ./src/font_courier.o
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+ .comment       0x0000000000000057       0x58 ./src/ili9341gfx.o
+ .comment       0x0000000000000057       0x58 ./src/main.o
+ .comment       0x0000000000000057       0x58 ./src/mcp24aaxx.o
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+ .comment       0x0000000000000057       0x58 /usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(eqsf2.o)
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+ .comment       0x0000000000000057       0x58 /usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(mulsf3.o)
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+ .comment       0x0000000000000057       0x57 /usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libg_nano.a(lib_a-memset.o)
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diff --git a/Release/arm-electronicload.map b/Release/arm-electronicload.map

new file mode 100644 (file)

index 0000000..962a321
--- /dev/null
+++ b/Release/arm-electronicload.map
@@ -0,0 +1,1578 @@
+Archive member included to satisfy reference by file (symbol)
+
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(_thumb1_case_shi.o)
+                              ./src/main.o (__gnu_thumb1_case_shi)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(_udivsi3.o)
+                              ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o (__aeabi_uidiv)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(_divsi3.o)
+                              ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o (__aeabi_idiv)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(_dvmd_tls.o)
+                              /usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(_udivsi3.o) (__aeabi_idiv0)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(_arm_cmpsf2.o)
+                              ./src/main.o (__aeabi_fcmpge)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(_fixunssfsi.o)
+                              ./src/main.o (__aeabi_f2uiz)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(addsf3.o)
+                              ./src/main.o (__aeabi_fadd)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(divsf3.o)
+                              ./src/main.o (__aeabi_fdiv)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(eqsf2.o)
+                              /usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(_arm_cmpsf2.o) (__eqsf2)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(gesf2.o)
+                              /usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(_arm_cmpsf2.o) (__gesf2)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(lesf2.o)
+                              /usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(_arm_cmpsf2.o) (__lesf2)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(mulsf3.o)
+                              ./src/main.o (__aeabi_fmul)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(subsf3.o)
+                              /usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(_fixunssfsi.o) (__aeabi_fsub)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(fixsfsi.o)
+                              /usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(_fixunssfsi.o) (__aeabi_f2iz)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(floatsisf.o)
+                              ./src/main.o (__aeabi_i2f)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(floatunsisf.o)
+                              ./src/main.o (__aeabi_ui2f)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(muldf3.o)
+                              ./src/main.o (__aeabi_dmul)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(extendsfdf2.o)
+                              ./src/main.o (__aeabi_f2d)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(truncdfsf2.o)
+                              ./src/main.o (__aeabi_d2f)
+/usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(_clzsi2.o)
+                              /usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(addsf3.o) (__clzsi2)
+/usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libg_nano.a(lib_a-errno.o)
+                              ./system/src/newlib/_sbrk.o (__errno)
+/usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libg_nano.a(lib_a-impure.o)
+                              /usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libg_nano.a(lib_a-errno.o) (_impure_ptr)
+/usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libg_nano.a(lib_a-memset.o)
+                              ./src/main.o (memset)
+
+Allocating common symbols
+Common symbol       size              file
+
+timer_delayCount    0x4               ./src/delay.o
+textbgcolour        0x2               ./src/ili9341gfx.o
+errno               0x4               ./system/src/newlib/_syscalls.o
+cursor_y            0x2               ./src/ili9341gfx.o
+iactualx            0x2               ./src/ili9341gfx.o
+iactualy            0x2               ./src/ili9341gfx.o
+vactualx            0x2               ./src/ili9341gfx.o
+isetx               0x2               ./src/ili9341gfx.o
+vsety               0x2               ./src/ili9341gfx.o
+I2C_InitStructure   0x1c              ./src/main.o
+vsetx               0x2               ./src/ili9341gfx.o
+vactualy            0x2               ./src/ili9341gfx.o
+GPIO_InitStructure  0x8               ./src/main.o
+enc_delta           0x1               ./src/main.o
+textcolour          0x2               ./src/ili9341gfx.o
+cursor_x            0x2               ./src/ili9341gfx.o
+textsize            0x1               ./src/ili9341gfx.o
+isety               0x2               ./src/ili9341gfx.o
+
+Discarded input sections
+
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+ .text.GPIO_ReadInputData
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+ .text.GPIO_ReadOutputDataBit
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+ .text.GPIO_ReadOutputData
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+ .debug_abbrev  0x0000000000000000      0x1f1 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
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+ .debug_aranges
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+ .ARM.attributes
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+ .comment       0x0000000000000000       0x58 /usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libg_nano.a(lib_a-impure.o)
+ .ARM.attributes
+                0x0000000000000000       0x2c /usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libg_nano.a(lib_a-impure.o)
+ .data          0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libg_nano.a(lib_a-memset.o)
+ .bss           0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libg_nano.a(lib_a-memset.o)
+
+Memory Configuration
+
+Name             Origin             Length             Attributes
+RAM              0x0000000020000000 0x0000000000002000 xrw
+CCMRAM           0x0000000000000000 0x0000000000000000 xrw
+FLASH            0x0000000008000000 0x0000000000010000 xr
+FLASHB1          0x0000000000000000 0x0000000000000000 xr
+EXTMEMB0         0x0000000000000000 0x0000000000000000 xr
+EXTMEMB1         0x0000000000000000 0x0000000000000000 xr
+EXTMEMB2         0x0000000000000000 0x0000000000000000 xr
+EXTMEMB3         0x0000000000000000 0x0000000000000000 xr
+MEMORY_ARRAY     0x0000000000000000 0x0000000000000000 xrw
+*default*        0x0000000000000000 0xffffffffffffffff
+
+Linker script and memory map
+
+LOAD ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+LOAD ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+LOAD ./system/src/newlib/_cxx.o
+LOAD ./system/src/newlib/_exit.o
+LOAD ./system/src/newlib/_sbrk.o
+LOAD ./system/src/newlib/_startup.o
+LOAD ./system/src/newlib/_syscalls.o
+LOAD ./system/src/newlib/assert.o
+LOAD ./system/src/diag/Trace.o
+LOAD ./system/src/diag/trace_impl.o
+LOAD ./system/src/cortexm/_initialize_hardware.o
+LOAD ./system/src/cortexm/_reset_hardware.o
+LOAD ./system/src/cortexm/exception_handlers.o
+LOAD ./system/src/cmsis/system_stm32f0xx.o
+LOAD ./system/src/cmsis/vectors_stm32f0xx.o
+LOAD ./src/BlinkLed.o
+LOAD ./src/_write.o
+LOAD ./src/delay.o
+LOAD ./src/i2c.o
+LOAD ./src/ili9341.o
+LOAD ./src/ili9341gfx.o
+LOAD ./src/main.o
+LOAD ./src/mcp24aaxx.o
+LOAD /usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libstdc++_nano.a
+LOAD /usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libm.a
+START GROUP
+LOAD /usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a
+LOAD /usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libg_nano.a
+LOAD /usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libc_nano.a
+END GROUP
+START GROUP
+LOAD /usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a
+LOAD /usr/lib/gcc/arm-none-eabi/7.3.1/../../../arm-none-eabi/lib/thumb/v6-m/libc_nano.a
+END GROUP
+                0x0000000020002000                __stack = (ORIGIN (RAM) + LENGTH (RAM))
+                0x0000000020002000                _estack = __stack
+                0x0000000000000400                __Main_Stack_Size = 0x400
+                [!provide]                        PROVIDE (_Main_Stack_Size = __Main_Stack_Size)
+                0x0000000020001c00                __Main_Stack_Limit = (__stack - __Main_Stack_Size)
+                [!provide]                        PROVIDE (_Main_Stack_Limit = __Main_Stack_Limit)
+                0x0000000000000100                _Minimum_Stack_Size = 0x100
+                0x0000000020000078                PROVIDE (_Heap_Begin = _end_noinit)
+                0x0000000020001c00                PROVIDE (_Heap_Limit = (__stack - __Main_Stack_Size))
+
+.isr_vector     0x0000000008000000      0x1ae
+ FILL mask 0xff
+                0x0000000008000000                __vectors_start = ABSOLUTE (.)
+                0x0000000008000000                __vectors_start__ = ABSOLUTE (.)
+ *(.isr_vector)
+ .isr_vector    0x0000000008000000       0xc4 ./system/src/cmsis/vectors_stm32f0xx.o
+                0x0000000008000000                g_pfnVectors
+ *(.cfmconfig)
+ *(.after_vectors .after_vectors.*)
+ .after_vectors
+                0x00000000080000c4       0xb8 ./system/src/newlib/_startup.o
+                0x00000000080000c4                _start
+ .after_vectors
+                0x000000000800017c       0x30 ./system/src/cortexm/exception_handlers.o
+                0x000000000800017c                Reset_Handler
+                0x0000000008000180                NMI_Handler
+                0x0000000008000182                HardFault_Handler
+                0x000000000800019a                HardFault_Handler_C
+                0x000000000800019c                SVC_Handler
+                0x000000000800019e                PendSV_Handler
+ .after_vectors
+                0x00000000080001ac        0x2 ./system/src/cmsis/vectors_stm32f0xx.o
+                0x00000000080001ac                TIM1_CC_IRQHandler
+                0x00000000080001ac                TSC_IRQHandler
+                0x00000000080001ac                ADC1_COMP_IRQHandler
+                0x00000000080001ac                TIM6_IRQHandler
+                0x00000000080001ac                PVD_IRQHandler
+                0x00000000080001ac                I2C1_IRQHandler
+                0x00000000080001ac                RCC_CRS_IRQHandler
+                0x00000000080001ac                SPI1_IRQHandler
+                0x00000000080001ac                TIM6_DAC_IRQHandler
+                0x00000000080001ac                USART3_4_IRQHandler
+                0x00000000080001ac                ADC1_IRQHandler
+                0x00000000080001ac                I2C2_IRQHandler
+                0x00000000080001ac                USART3_6_IRQHandler
+                0x00000000080001ac                TIM17_IRQHandler
+                0x00000000080001ac                CEC_CAN_IRQHandler
+                0x00000000080001ac                PVD_VDDIO2_IRQHandler
+                0x00000000080001ac                DMA1_Channel4_5_6_7_IRQHandler
+                0x00000000080001ac                TIM3_IRQHandler
+                0x00000000080001ac                RCC_IRQHandler
+                0x00000000080001ac                EXTI4_15_IRQHandler
+                0x00000000080001ac                USART3_8_IRQHandler
+                0x00000000080001ac                DMA1_Channel1_IRQHandler
+                0x00000000080001ac                Default_Handler
+                0x00000000080001ac                CEC_IRQHandler
+                0x00000000080001ac                DMA1_Channel4_5_IRQHandler
+                0x00000000080001ac                TIM7_IRQHandler
+                0x00000000080001ac                TIM15_IRQHandler
+                0x00000000080001ac                EXTI0_1_IRQHandler
+                0x00000000080001ac                USB_IRQHandler
+                0x00000000080001ac                SPI2_IRQHandler
+                0x00000000080001ac                DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
+                0x00000000080001ac                DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
+                0x00000000080001ac                TS_IRQHandler
+                0x00000000080001ac                WWDG_IRQHandler
+                0x00000000080001ac                TIM2_IRQHandler
+                0x00000000080001ac                DMA1_Channel2_3_IRQHandler
+                0x00000000080001ac                USART2_IRQHandler
+                0x00000000080001ac                VDDIO2_IRQHandler
+                0x00000000080001ac                FLASH_IRQHandler
+                0x00000000080001ac                USART1_IRQHandler
+                0x00000000080001ac                TIM1_BRK_UP_TRG_COM_IRQHandler
+
+.inits          0x00000000080001b0       0x28
+                0x00000000080001b0                __data_regions_array_start = .
+                0x00000000080001b0        0x4 LONG 0x8003ec0 LOADADDR (.data)
+                0x00000000080001b4        0x4 LONG 0x20000000 ADDR (.data)
+                0x00000000080001b8        0x4 LONG 0x20000024 (ADDR (.data) + SIZEOF (.data))
+                0x00000000080001bc        0x4 LONG 0x8003ec0 LOADADDR (.data_CCMRAM)
+                0x00000000080001c0        0x4 LONG 0x0 ADDR (.data_CCMRAM)
+                0x00000000080001c4        0x4 LONG 0x0 (ADDR (.data_CCMRAM) + SIZEOF (.data_CCMRAM))
+                0x00000000080001c8                __data_regions_array_end = .
+                0x00000000080001c8                __bss_regions_array_start = .
+                0x00000000080001c8        0x4 LONG 0x20000024 ADDR (.bss)
+                0x00000000080001cc        0x4 LONG 0x20000078 (ADDR (.bss) + SIZEOF (.bss))
+                0x00000000080001d0        0x4 LONG 0x0 ADDR (.bss_CCMRAM)
+                0x00000000080001d4        0x4 LONG 0x0 (ADDR (.bss_CCMRAM) + SIZEOF (.bss_CCMRAM))
+                0x00000000080001d8                __bss_regions_array_end = .
+ *(.init)
+ *(.fini)
+                0x00000000080001d8                . = ALIGN (0x4)
+                0x00000000080001d8                PROVIDE (__preinit_array_start = .)
+ *(.preinit_array_sysinit .preinit_array_sysinit.*)
+ *(.preinit_array_platform .preinit_array_platform.*)
+ *(.preinit_array .preinit_array.*)
+                0x00000000080001d8                PROVIDE (__preinit_array_end = .)
+                0x00000000080001d8                . = ALIGN (0x4)
+                0x00000000080001d8                PROVIDE (__init_array_start = .)
+ *(SORT_BY_NAME(.init_array.*))
+ *(.init_array)
+                0x00000000080001d8                PROVIDE (__init_array_end = .)
+                0x00000000080001d8                . = ALIGN (0x4)
+                0x00000000080001d8                PROVIDE (__fini_array_start = .)
+ *(SORT_BY_NAME(.fini_array.*))
+ *(.fini_array)
+                0x00000000080001d8                PROVIDE (__fini_array_end = .)
+
+.flashtext
+ *(.flashtext .flashtext.*)
+
+.text           0x00000000080001d8     0x3ce8
+ *(.text .text.*)
+ .text._exit    0x00000000080001d8        0x6 ./system/src/newlib/_exit.o
+                0x00000000080001d8                _exit
+ *fill*         0x00000000080001de        0x2 
+ .text.__initialize_args
+                0x00000000080001e0       0x10 ./system/src/newlib/_syscalls.o
+                0x00000000080001e0                __initialize_args
+ .text.__initialize_hardware_early
+                0x00000000080001f0        0x8 ./system/src/cortexm/_initialize_hardware.o
+                0x00000000080001f0                __initialize_hardware_early
+ .text.__initialize_hardware
+                0x00000000080001f8        0x8 ./system/src/cortexm/_initialize_hardware.o
+                0x00000000080001f8                __initialize_hardware
+ .text.__reset_hardware
+                0x0000000008000200       0x1c ./system/src/cortexm/_reset_hardware.o
+                0x0000000008000200                __reset_hardware
+ .text.SystemInit
+                0x000000000800021c       0xf8 ./system/src/cmsis/system_stm32f0xx.o
+                0x000000000800021c                SystemInit
+ .text.SystemCoreClockUpdate
+                0x0000000008000314       0x64 ./system/src/cmsis/system_stm32f0xx.o
+                0x0000000008000314                SystemCoreClockUpdate
+ .text.delay_init
+                0x0000000008000378       0x44 ./src/delay.o
+                0x0000000008000378                delay_init
+ .text.timer_sleep
+                0x00000000080003bc       0x10 ./src/delay.o
+                0x00000000080003bc                timer_sleep
+ .text.timer_tick
+                0x00000000080003cc       0x14 ./src/delay.o
+                0x00000000080003cc                timer_tick
+ .text.delay_ms
+                0x00000000080003e0        0x8 ./src/delay.o
+                0x00000000080003e0                delay_ms
+ .text.SysTick_Handler
+                0x00000000080003e8        0x8 ./src/delay.o
+                0x00000000080003e8                SysTick_Handler
+ .text.i2c_init
+                0x00000000080003f0       0x18 ./src/i2c.o
+                0x00000000080003f0                i2c_init
+ .text.i2c_start
+                0x0000000008000408       0x14 ./src/i2c.o
+                0x0000000008000408                i2c_start
+ .text.i2c_stop
+                0x000000000800041c       0x14 ./src/i2c.o
+                0x000000000800041c                i2c_stop
+ .text.i2c_reset
+                0x0000000008000430       0x18 ./src/i2c.o
+                0x0000000008000430                i2c_reset
+ .text.i2c_autoend
+                0x0000000008000448       0x10 ./src/i2c.o
+                0x0000000008000448                i2c_autoend
+ .text.i2c_set_nbytes
+                0x0000000008000458       0x1c ./src/i2c.o
+                0x0000000008000458                i2c_set_nbytes
+ .text.i2c_read_ack
+                0x0000000008000474       0x14 ./src/i2c.o
+                0x0000000008000474                i2c_read_ack
+ .text.i2c_write_addr
+                0x0000000008000488       0x24 ./src/i2c.o
+                0x0000000008000488                i2c_write_addr
+ .text.i2c_write
+                0x00000000080004ac       0x14 ./src/i2c.o
+                0x00000000080004ac                i2c_write
+ .text.ili9341_hard_init
+                0x00000000080004c0       0x12 ./src/ili9341.o
+                0x00000000080004c0                ili9341_hard_init
+ .text.ili9341_hard_reset
+                0x00000000080004d2       0x22 ./src/ili9341.o
+                0x00000000080004d2                ili9341_hard_reset
+ .text.ili9341_spi_send
+                0x00000000080004f4       0x34 ./src/ili9341.o
+                0x00000000080004f4                ili9341_spi_send
+ .text.ili9341_writecommand8
+                0x0000000008000528       0x10 ./src/ili9341.o
+                0x0000000008000528                ili9341_writecommand8
+ .text.ili9341_writedata8
+                0x0000000008000538       0x10 ./src/ili9341.o
+                0x0000000008000538                ili9341_writedata8
+ .text.ili9341_setaddress
+                0x0000000008000548       0x50 ./src/ili9341.o
+                0x0000000008000548                ili9341_setaddress
+ .text.ili9341_init
+                0x0000000008000598      0x206 ./src/ili9341.o
+                0x0000000008000598                ili9341_init
+ .text.ili9341_pushcolour
+                0x000000000800079e       0x12 ./src/ili9341.o
+                0x000000000800079e                ili9341_pushcolour
+ .text.ili9341_clear
+                0x00000000080007b0       0x48 ./src/ili9341.o
+                0x00000000080007b0                ili9341_clear
+ .text.ili9341_drawpixel
+                0x00000000080007f8       0x30 ./src/ili9341.o
+                0x00000000080007f8                ili9341_drawpixel
+ .text.ili9341_drawvline
+                0x0000000008000828       0x50 ./src/ili9341.o
+                0x0000000008000828                ili9341_drawvline
+ .text.ili9341_drawhline
+                0x0000000008000878       0x50 ./src/ili9341.o
+                0x0000000008000878                ili9341_drawhline
+ .text.ili9341_fillrect
+                0x00000000080008c8       0x74 ./src/ili9341.o
+                0x00000000080008c8                ili9341_fillrect
+ .text.ili9341_setRotation
+                0x000000000800093c       0x50 ./src/ili9341.o
+                0x000000000800093c                ili9341_setRotation
+ .text.ili9341_drawchar
+                0x000000000800098c       0xe8 ./src/ili9341gfx.o
+                0x000000000800098c                ili9341_drawchar
+ .text.ili9341_setcursor
+                0x0000000008000a74       0x14 ./src/ili9341gfx.o
+                0x0000000008000a74                ili9341_setcursor
+ .text.ili9341_settextcolour
+                0x0000000008000a88       0x14 ./src/ili9341gfx.o
+                0x0000000008000a88                ili9341_settextcolour
+ .text.ili9341_settextsize
+                0x0000000008000a9c       0x14 ./src/ili9341gfx.o
+                0x0000000008000a9c                ili9341_settextsize
+ .text.ili9341_write
+                0x0000000008000ab0       0x6c ./src/ili9341gfx.o
+                0x0000000008000ab0                ili9341_write
+ .text.ili9341_out
+                0x0000000008000b1c       0x1a ./src/ili9341gfx.o
+                0x0000000008000b1c                ili9341_out
+ .text.i_to_a   0x0000000008000b36       0x32 ./src/main.o
+                0x0000000008000b36                i_to_a
+ .text.encode_init
+                0x0000000008000b68       0x30 ./src/main.o
+                0x0000000008000b68                encode_init
+ .text.encode_read4
+                0x0000000008000b98       0x14 ./src/main.o
+                0x0000000008000b98                encode_read4
+ .text.mcp4728_set_reference
+                0x0000000008000bac       0x2e ./src/main.o
+                0x0000000008000bac                mcp4728_set_reference
+ .text.mcp4728_set_gain
+                0x0000000008000bda       0x2e ./src/main.o
+                0x0000000008000bda                mcp4728_set_gain
+ .text.mcp4728_set_pd
+                0x0000000008000c08       0x34 ./src/main.o
+                0x0000000008000c08                mcp4728_set_pd
+ .text.mcp4728_write_fast_dac
+                0x0000000008000c3c       0x48 ./src/main.o
+                0x0000000008000c3c                mcp4728_write_fast_dac
+ .text.mcp3421_config
+                0x0000000008000c84       0x28 ./src/main.o
+                0x0000000008000c84                mcp3421_config
+ .text.mcp3421_read
+                0x0000000008000cac       0x5c ./src/main.o
+                0x0000000008000cac                mcp3421_read
+ .text.mcp9808_read
+                0x0000000008000d08       0x70 ./src/main.o
+                0x0000000008000d08                mcp9808_read
+ .text.mcp9808_setalert
+                0x0000000008000d78       0xf0 ./src/main.o
+                0x0000000008000d78                mcp9808_setalert
+ .text.show_amperes
+                0x0000000008000e68       0x70 ./src/main.o
+                0x0000000008000e68                show_amperes
+ .text.show_voltage
+                0x0000000008000ed8       0x68 ./src/main.o
+                0x0000000008000ed8                show_voltage
+ .text.show_dec_mark
+                0x0000000008000f40       0x5c ./src/main.o
+                0x0000000008000f40                show_dec_mark
+ .text.show_status
+                0x0000000008000f9c       0x6c ./src/main.o
+                0x0000000008000f9c                show_status
+ .text.show_watt
+                0x0000000008001008       0x68 ./src/main.o
+                0x0000000008001008                show_watt
+ .text.show_resistance
+                0x0000000008001070       0x98 ./src/main.o
+                0x0000000008001070                show_resistance
+ .text.show_temperature
+                0x0000000008001108       0xb4 ./src/main.o
+                0x0000000008001108                show_temperature
+ .text.fet_pulldown
+                0x00000000080011bc       0x28 ./src/main.o
+                0x00000000080011bc                fet_pulldown
+ .text.RCC_Configuration
+                0x00000000080011e4       0xfc ./src/main.o
+                0x00000000080011e4                RCC_Configuration
+ .text.startup.main
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+ .debug_ranges  0x0000000000000b48       0x18 /usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(extendsfdf2.o)
+ .debug_ranges  0x0000000000000b60       0x38 /usr/lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/libgcc.a(truncdfsf2.o)
diff --git a/Release/arm-electronicload_rework_2022.elf b/Release/arm-electronicload_rework_2022.elf

new file mode 100755 (executable)

index 0000000..848a239

Binary files /dev/null and b/Release/arm-electronicload_rework_2022.elf differ
diff --git a/Release/arm-electronicload_rework_2022.hex b/Release/arm-electronicload_rework_2022.hex

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index 0000000..8bb778e
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+:1080D400BA3F000860400008604000082C440008D3\r
+:1080E4005E4300085E4300085C43000862430008E6\r
+:1080F400624300080A4400085C4300086243000825\r
+:108104000A440008624300085C430008064400086F\r
+:0C8114000644000806440008144400085B\r
+:10812000240000200000000000000000000000000B\r
+:108130000102030406070809006CDC02F00040019C\r
+:04814000010102FF38\r
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+:00000001FF\r
diff --git a/Release/arm-electronicload_rework_2022.map b/Release/arm-electronicload_rework_2022.map

new file mode 100644 (file)

index 0000000..8448630
--- /dev/null
+++ b/Release/arm-electronicload_rework_2022.map
@@ -0,0 +1,1845 @@
+Archive member included to satisfy reference by file (symbol)
+
+/usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_thumb1_case_uqi.o)
+                              ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o (__gnu_thumb1_case_uqi)
+/usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_thumb1_case_shi.o)
+                              ./src/main.o (__gnu_thumb1_case_shi)
+/usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+                              ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o (__aeabi_uidiv)
+/usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
+                              ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o (__aeabi_idiv)
+/usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
+                              /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o) (__aeabi_idiv0)
+/usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_arm_cmpsf2.o)
+                              ./src/main.o (__aeabi_fcmpge)
+/usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_fixunssfsi.o)
+                              ./src/main.o (__aeabi_f2uiz)
+/usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(addsf3.o)
+                              ./src/main.o (__aeabi_fadd)
+/usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(divsf3.o)
+                              ./src/main.o (__aeabi_fdiv)
+/usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(eqsf2.o)
+                              /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_arm_cmpsf2.o) (__eqsf2)
+/usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(gesf2.o)
+                              /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_arm_cmpsf2.o) (__gesf2)
+/usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(lesf2.o)
+                              /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_arm_cmpsf2.o) (__lesf2)
+/usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(mulsf3.o)
+                              ./src/main.o (__aeabi_fmul)
+/usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(subsf3.o)
+                              /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_fixunssfsi.o) (__aeabi_fsub)
+/usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(fixsfsi.o)
+                              /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_fixunssfsi.o) (__aeabi_f2iz)
+/usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(floatsisf.o)
+                              ./src/main.o (__aeabi_i2f)
+/usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(floatunsisf.o)
+                              ./src/main.o (__aeabi_ui2f)
+/usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_clzsi2.o)
+                              /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(addsf3.o) (__clzsi2)
+/usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-abs.o)
+                              ./src/ili9341.o (abs)
+/usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-errno.o)
+                              ./system/src/newlib/_sbrk.o (__errno)
+/usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-impure.o)
+                              /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-errno.o) (_impure_ptr)
+/usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-memcpy-stub.o)
+                              ./src/main.o (memcpy)
+/usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-memset.o)
+                              ./src/main.o (memset)
+
+Allocating common symbols
+Common symbol       size              file
+
+_invisible          0x1               ./src/ili9341.o
+_originx            0x2               ./src/ili9341.o
+timer_delayCount    0x4               ./src/delay.o
+_standard           0x1               ./src/ili9341.o
+errno               0x4               ./system/src/newlib/_syscalls.o
+_clipy1             0x2               ./src/ili9341.o
+font                0x1c              ./src/ili9341gfx.o
+cursor_y            0x2               ./src/ili9341gfx.o
+iactualx            0x2               ./src/ili9341gfx.o
+us_ticks            0x4               ./src/delay.o
+iactualy            0x2               ./src/ili9341gfx.o
+_displayclipx1      0x2               ./src/ili9341.o
+_clipy2             0x2               ./src/ili9341.o
+vactualx            0x2               ./src/ili9341gfx.o
+isetx               0x2               ./src/ili9341gfx.o
+vsety               0x2               ./src/ili9341gfx.o
+vsetx               0x2               ./src/ili9341gfx.o
+_clipx2             0x2               ./src/ili9341.o
+i2c                 0x25              ./src/i2c.o
+ili9341_buf         0x1               ./src/ili9341.o
+vactualy            0x2               ./src/ili9341gfx.o
+_originy            0x2               ./src/ili9341.o
+enc_delta           0x1               ./src/main.o
+ticks               0x4               ./src/delay.o
+cursor_x            0x2               ./src/ili9341gfx.o
+_displayclipy1      0x2               ./src/ili9341.o
+textsize            0x1               ./src/ili9341gfx.o
+_clipx1             0x2               ./src/ili9341.o
+_displayclipy2      0x2               ./src/ili9341.o
+isety               0x2               ./src/ili9341gfx.o
+_displayclipx2      0x2               ./src/ili9341.o
+textbgcolor         0x2               ./src/ili9341gfx.o
+textcolor           0x2               ./src/ili9341gfx.o
+
+Discarded input sections
+
+ .text          0x0000000000000000        0x0 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .data          0x0000000000000000        0x0 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .bss           0x0000000000000000        0x0 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .text.GPIO_DeInit
+                0x0000000000000000       0xac ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .text.GPIO_Init
+                0x0000000000000000       0x7a ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .text.GPIO_StructInit
+                0x0000000000000000       0x10 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .text.GPIO_PinLockConfig
+                0x0000000000000000       0x24 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .text.GPIO_ReadInputDataBit
+                0x0000000000000000        0xc ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .text.GPIO_ReadInputData
+                0x0000000000000000        0x6 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .text.GPIO_ReadOutputDataBit
+                0x0000000000000000        0xc ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .text.GPIO_ReadOutputData
+                0x0000000000000000        0x6 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .text.GPIO_SetBits
+                0x0000000000000000        0x4 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .text.GPIO_ResetBits
+                0x0000000000000000        0x4 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .text.GPIO_WriteBit
+                0x0000000000000000        0xc ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .text.GPIO_Write
+                0x0000000000000000        0x4 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .text.GPIO_PinAFConfig
+                0x0000000000000000       0x22 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .debug_info    0x0000000000000000      0x720 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .debug_abbrev  0x0000000000000000      0x22c ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .debug_loc     0x0000000000000000      0x3c8 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .debug_aranges
+                0x0000000000000000       0x80 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .debug_ranges  0x0000000000000000       0x70 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .debug_line    0x0000000000000000      0x462 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .debug_str     0x0000000000000000      0x52e ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .comment       0x0000000000000000       0x52 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .debug_frame   0x0000000000000000      0x108 ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .ARM.attributes
+                0x0000000000000000       0x2c ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+ .text          0x0000000000000000        0x0 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .data          0x0000000000000000        0x0 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .bss           0x0000000000000000        0x0 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_DeInit
+                0x0000000000000000       0x60 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_HSEConfig
+                0x0000000000000000       0x10 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_AdjustHSICalibrationValue
+                0x0000000000000000       0x14 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_HSICmd
+                0x0000000000000000       0x1c ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_AdjustHSI14CalibrationValue
+                0x0000000000000000       0x14 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_HSI14Cmd
+                0x0000000000000000       0x1c ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_HSI14ADCRequestCmd
+                0x0000000000000000       0x1c ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_LSEConfig
+                0x0000000000000000       0x20 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_LSEDriveConfig
+                0x0000000000000000       0x18 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_LSICmd
+                0x0000000000000000       0x1c ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_PLLConfig
+                0x0000000000000000       0x20 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_PLLCmd
+                0x0000000000000000       0x24 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_HSI48Cmd
+                0x0000000000000000       0x24 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_PREDIV1Config
+                0x0000000000000000       0x14 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_ClockSecuritySystemCmd
+                0x0000000000000000       0x24 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_MCOConfig
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+ .text.RCC_SYSCLKConfig
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+                0x0000000000000000       0x10 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_HCLKConfig
+                0x0000000000000000       0x14 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
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+                0x0000000000000000       0x18 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_ADCCLKConfig
+                0x0000000000000000       0x30 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_CECCLKConfig
+                0x0000000000000000       0x18 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_I2CCLKConfig
+                0x0000000000000000       0x18 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_USARTCLKConfig
+                0x0000000000000000       0x34 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_USBCLKConfig
+                0x0000000000000000       0x18 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_GetClocksFreq
+                0x0000000000000000      0x17c ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_RTCCLKConfig
+                0x0000000000000000       0x10 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_RTCCLKCmd
+                0x0000000000000000       0x24 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_BackupResetCmd
+                0x0000000000000000       0x24 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_AHBPeriphClockCmd
+                0x0000000000000000       0x18 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_APB2PeriphClockCmd
+                0x0000000000000000       0x18 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_APB1PeriphClockCmd
+                0x0000000000000000       0x18 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_AHBPeriphResetCmd
+                0x0000000000000000       0x18 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_APB2PeriphResetCmd
+                0x0000000000000000       0x18 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_APB1PeriphResetCmd
+                0x0000000000000000       0x18 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_ITConfig
+                0x0000000000000000       0x18 ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+ .text.RCC_GetFlagStatus
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+ .data.APBAHBPrescTable
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+ .ARM.attributes
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+ .bss           0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
+ .data          0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_arm_cmpsf2.o)
+ .bss           0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_arm_cmpsf2.o)
+ .data          0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_fixunssfsi.o)
+ .bss           0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_fixunssfsi.o)
+ .data          0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(addsf3.o)
+ .bss           0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(addsf3.o)
+ .data          0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(divsf3.o)
+ .bss           0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(divsf3.o)
+ .data          0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(eqsf2.o)
+ .bss           0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(eqsf2.o)
+ .data          0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(gesf2.o)
+ .bss           0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(gesf2.o)
+ .data          0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(lesf2.o)
+ .bss           0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(lesf2.o)
+ .data          0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(mulsf3.o)
+ .bss           0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(mulsf3.o)
+ .data          0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(subsf3.o)
+ .bss           0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(subsf3.o)
+ .data          0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(fixsfsi.o)
+ .bss           0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(fixsfsi.o)
+ .data          0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(floatsisf.o)
+ .bss           0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(floatsisf.o)
+ .data          0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(floatunsisf.o)
+ .bss           0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(floatunsisf.o)
+ .data          0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_clzsi2.o)
+ .bss           0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_clzsi2.o)
+ .text          0x0000000000000000        0x8 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-abs.o)
+ .data          0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-abs.o)
+ .bss           0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-abs.o)
+ .debug_info    0x0000000000000000      0x93f /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-abs.o)
+ .debug_abbrev  0x0000000000000000      0x1a7 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-abs.o)
+ .debug_loc     0x0000000000000000       0x25 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-abs.o)
+ .debug_aranges
+                0x0000000000000000       0x20 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-abs.o)
+ .debug_line    0x0000000000000000      0x13f /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-abs.o)
+ .debug_str     0x0000000000000000      0x5d8 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-abs.o)
+ .comment       0x0000000000000000       0x4f /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-abs.o)
+ .debug_frame   0x0000000000000000       0x20 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-abs.o)
+ .ARM.attributes
+                0x0000000000000000       0x2c /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-abs.o)
+ .text          0x0000000000000000        0xc /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-errno.o)
+ .data          0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-errno.o)
+ .bss           0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-errno.o)
+ .debug_info    0x0000000000000000      0x953 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-errno.o)
+ .debug_abbrev  0x0000000000000000      0x198 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-errno.o)
+ .debug_aranges
+                0x0000000000000000       0x20 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-errno.o)
+ .debug_line    0x0000000000000000      0x10e /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-errno.o)
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+ .comment       0x0000000000000000       0x4f /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-errno.o)
+ .debug_frame   0x0000000000000000       0x20 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-errno.o)
+ .ARM.attributes
+                0x0000000000000000       0x2c /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-errno.o)
+ .text          0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-impure.o)
+ .data          0x0000000000000000       0x64 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-impure.o)
+ .bss           0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-impure.o)
+ .rodata        0x0000000000000000        0x4 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-impure.o)
+ .debug_info    0x0000000000000000      0x92a /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-impure.o)
+ .debug_abbrev  0x0000000000000000      0x17a /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-impure.o)
+ .debug_aranges
+                0x0000000000000000       0x18 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-impure.o)
+ .debug_line    0x0000000000000000       0xe3 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-impure.o)
+ .debug_str     0x0000000000000000      0x5db /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-impure.o)
+ .comment       0x0000000000000000       0x4f /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-impure.o)
+ .ARM.attributes
+                0x0000000000000000       0x2c /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-impure.o)
+ .data          0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-memcpy-stub.o)
+ .bss           0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-memcpy-stub.o)
+ .data          0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-memset.o)
+ .bss           0x0000000000000000        0x0 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-memset.o)
+
+Memory Configuration
+
+Name             Origin             Length             Attributes
+RAM              0x0000000020000000 0x0000000000002000 xrw
+CCMRAM           0x0000000000000000 0x0000000000000000 xrw
+FLASH            0x0000000008000000 0x0000000000010000 xr
+FLASHB1          0x0000000000000000 0x0000000000000000 xr
+EXTMEMB0         0x0000000000000000 0x0000000000000000 xr
+EXTMEMB1         0x0000000000000000 0x0000000000000000 xr
+EXTMEMB2         0x0000000000000000 0x0000000000000000 xr
+EXTMEMB3         0x0000000000000000 0x0000000000000000 xr
+MEMORY_ARRAY     0x0000000000000000 0x0000000000000000 xrw
+*default*        0x0000000000000000 0xffffffffffffffff
+
+Linker script and memory map
+
+LOAD ./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o
+LOAD ./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o
+LOAD ./system/src/newlib/_cxx.o
+LOAD ./system/src/newlib/_exit.o
+LOAD ./system/src/newlib/_sbrk.o
+LOAD ./system/src/newlib/_startup.o
+LOAD ./system/src/newlib/_syscalls.o
+LOAD ./system/src/newlib/assert.o
+LOAD ./system/src/diag/Trace.o
+LOAD ./system/src/diag/trace_impl.o
+LOAD ./system/src/cortexm/_initialize_hardware.o
+LOAD ./system/src/cortexm/_reset_hardware.o
+LOAD ./system/src/cortexm/exception_handlers.o
+LOAD ./system/src/cmsis/system_stm32f0xx.o
+LOAD ./system/src/cmsis/vectors_stm32f0xx.o
+LOAD ./src/24aaxx.o
+LOAD ./src/BlinkLed.o
+LOAD ./src/_write.o
+LOAD ./src/delay.o
+LOAD ./src/font_Arial.o
+LOAD ./src/glcdfont.o
+LOAD ./src/i2c.o
+LOAD ./src/ili9341.o
+LOAD ./src/ili9341gfx.o
+LOAD ./src/main.o
+LOAD /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libstdc++_nano.a
+LOAD /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libm.a
+START GROUP
+LOAD /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a
+LOAD /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a
+LOAD /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a
+END GROUP
+START GROUP
+LOAD /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a
+LOAD /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a
+END GROUP
+                0x0000000020002000                __stack = (ORIGIN (RAM) + LENGTH (RAM))
+                0x0000000020002000                _estack = __stack
+                0x0000000000000400                __Main_Stack_Size = 0x400
+                [!provide]                        PROVIDE (_Main_Stack_Size = __Main_Stack_Size)
+                0x0000000020001c00                __Main_Stack_Limit = (__stack - __Main_Stack_Size)
+                [!provide]                        PROVIDE (_Main_Stack_Limit = __Main_Stack_Limit)
+                0x0000000000000100                _Minimum_Stack_Size = 0x100
+                0x00000000200000b4                PROVIDE (_Heap_Begin = _end_noinit)
+                0x0000000020001c00                PROVIDE (_Heap_Limit = (__stack - __Main_Stack_Size))
+
+.isr_vector     0x0000000008000000      0x1aa
+ FILL mask 0xff
+                0x0000000008000000                __vectors_start = ABSOLUTE (.)
+                0x0000000008000000                __vectors_start__ = ABSOLUTE (.)
+ *(.isr_vector)
+ .isr_vector    0x0000000008000000       0xc4 ./system/src/cmsis/vectors_stm32f0xx.o
+                0x0000000008000000                g_pfnVectors
+ *(.cfmconfig)
+ *(.after_vectors .after_vectors.*)
+ .after_vectors
+                0x00000000080000c4       0xb4 ./system/src/newlib/_startup.o
+                0x00000000080000c4                _start
+ .after_vectors
+                0x0000000008000178       0x30 ./system/src/cortexm/exception_handlers.o
+                0x0000000008000178                Reset_Handler
+                0x000000000800017c                NMI_Handler
+                0x000000000800017e                HardFault_Handler
+                0x0000000008000196                HardFault_Handler_C
+                0x0000000008000198                SVC_Handler
+                0x000000000800019a                PendSV_Handler
+ .after_vectors
+                0x00000000080001a8        0x2 ./system/src/cmsis/vectors_stm32f0xx.o
+                0x00000000080001a8                TIM1_CC_IRQHandler
+                0x00000000080001a8                TSC_IRQHandler
+                0x00000000080001a8                ADC1_COMP_IRQHandler
+                0x00000000080001a8                TIM6_IRQHandler
+                0x00000000080001a8                PVD_IRQHandler
+                0x00000000080001a8                RCC_CRS_IRQHandler
+                0x00000000080001a8                TIM6_DAC_IRQHandler
+                0x00000000080001a8                USART3_4_IRQHandler
+                0x00000000080001a8                ADC1_IRQHandler
+                0x00000000080001a8                I2C2_IRQHandler
+                0x00000000080001a8                USART3_6_IRQHandler
+                0x00000000080001a8                TIM17_IRQHandler
+                0x00000000080001a8                CEC_CAN_IRQHandler
+                0x00000000080001a8                PVD_VDDIO2_IRQHandler
+                0x00000000080001a8                DMA1_Channel4_5_6_7_IRQHandler
+                0x00000000080001a8                TIM3_IRQHandler
+                0x00000000080001a8                RCC_IRQHandler
+                0x00000000080001a8                EXTI4_15_IRQHandler
+                0x00000000080001a8                USART3_8_IRQHandler
+                0x00000000080001a8                DMA1_Channel1_IRQHandler
+                0x00000000080001a8                Default_Handler
+                0x00000000080001a8                CEC_IRQHandler
+                0x00000000080001a8                DMA1_Channel4_5_IRQHandler
+                0x00000000080001a8                TIM7_IRQHandler
+                0x00000000080001a8                EXTI0_1_IRQHandler
+                0x00000000080001a8                USB_IRQHandler
+                0x00000000080001a8                SPI2_IRQHandler
+                0x00000000080001a8                DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
+                0x00000000080001a8                DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
+                0x00000000080001a8                TS_IRQHandler
+                0x00000000080001a8                WWDG_IRQHandler
+                0x00000000080001a8                TIM2_IRQHandler
+                0x00000000080001a8                DMA1_Channel2_3_IRQHandler
+                0x00000000080001a8                USART2_IRQHandler
+                0x00000000080001a8                VDDIO2_IRQHandler
+                0x00000000080001a8                FLASH_IRQHandler
+                0x00000000080001a8                USART1_IRQHandler
+                0x00000000080001a8                TIM1_BRK_UP_TRG_COM_IRQHandler
+
+.inits          0x00000000080001ac       0x28
+                0x00000000080001ac                __data_regions_array_start = .
+                0x00000000080001ac        0x4 LONG 0x8008120 LOADADDR (.data)
+                0x00000000080001b0        0x4 LONG 0x20000000 ADDR (.data)
+                0x00000000080001b4        0x4 LONG 0x20000024 (ADDR (.data) + SIZEOF (.data))
+                0x00000000080001b8        0x4 LONG 0x8008120 LOADADDR (.data_CCMRAM)
+                0x00000000080001bc        0x4 LONG 0x0 ADDR (.data_CCMRAM)
+                0x00000000080001c0        0x4 LONG 0x0 (ADDR (.data_CCMRAM) + SIZEOF (.data_CCMRAM))
+                0x00000000080001c4                __data_regions_array_end = .
+                0x00000000080001c4                __bss_regions_array_start = .
+                0x00000000080001c4        0x4 LONG 0x20000024 ADDR (.bss)
+                0x00000000080001c8        0x4 LONG 0x200000b4 (ADDR (.bss) + SIZEOF (.bss))
+                0x00000000080001cc        0x4 LONG 0x0 ADDR (.bss_CCMRAM)
+                0x00000000080001d0        0x4 LONG 0x0 (ADDR (.bss_CCMRAM) + SIZEOF (.bss_CCMRAM))
+                0x00000000080001d4                __bss_regions_array_end = .
+ *(.init)
+ *(.fini)
+                0x00000000080001d4                . = ALIGN (0x4)
+                0x00000000080001d4                PROVIDE (__preinit_array_start = .)
+ *(.preinit_array_sysinit .preinit_array_sysinit.*)
+ *(.preinit_array_platform .preinit_array_platform.*)
+ *(.preinit_array .preinit_array.*)
+                0x00000000080001d4                PROVIDE (__preinit_array_end = .)
+                0x00000000080001d4                . = ALIGN (0x4)
+                0x00000000080001d4                PROVIDE (__init_array_start = .)
+ *(SORT_BY_NAME(.init_array.*))
+ *(.init_array)
+                0x00000000080001d4                PROVIDE (__init_array_end = .)
+                0x00000000080001d4                . = ALIGN (0x4)
+                0x00000000080001d4                PROVIDE (__fini_array_start = .)
+ *(SORT_BY_NAME(.fini_array.*))
+ *(.fini_array)
+                0x00000000080001d4                PROVIDE (__fini_array_end = .)
+
+.flashtext
+ *(.flashtext .flashtext.*)
+
+.text           0x00000000080001d4     0x7f4c
+ *(.text .text.*)
+ .text._exit    0x00000000080001d4        0x6 ./system/src/newlib/_exit.o
+                0x00000000080001d4                _exit
+ *fill*         0x00000000080001da        0x2 
+ .text.__initialize_args
+                0x00000000080001dc       0x10 ./system/src/newlib/_syscalls.o
+                0x00000000080001dc                __initialize_args
+ .text.__initialize_hardware_early
+                0x00000000080001ec        0x8 ./system/src/cortexm/_initialize_hardware.o
+                0x00000000080001ec                __initialize_hardware_early
+ .text.__initialize_hardware
+                0x00000000080001f4        0x8 ./system/src/cortexm/_initialize_hardware.o
+                0x00000000080001f4                __initialize_hardware
+ .text.__reset_hardware
+                0x00000000080001fc       0x1c ./system/src/cortexm/_reset_hardware.o
+                0x00000000080001fc                __reset_hardware
+ .text.SystemInit
+                0x0000000008000218       0xf8 ./system/src/cmsis/system_stm32f0xx.o
+                0x0000000008000218                SystemInit
+ .text.SystemCoreClockUpdate
+                0x0000000008000310       0x68 ./system/src/cmsis/system_stm32f0xx.o
+                0x0000000008000310                SystemCoreClockUpdate
+ .text.wordlength
+                0x0000000008000378       0x12 ./src/24aaxx.o
+                0x0000000008000378                wordlength
+ *fill*         0x000000000800038a        0x2 
+ .text.mask     0x000000000800038c       0x18 ./src/24aaxx.o
+                0x000000000800038c                mask
+ .text.shift    0x00000000080003a4       0x12 ./src/24aaxx.o
+                0x00000000080003a4                shift
+ *fill*         0x00000000080003b6        0x2 
+ .text._24aa32_write
+                0x00000000080003b8      0x10c ./src/24aaxx.o
+                0x00000000080003b8                _24aa32_write
+ .text._24aa32_read
+                0x00000000080004c4      0x160 ./src/24aaxx.o
+                0x00000000080004c4                _24aa32_read
+ .text.delay_init
+                0x0000000008000624       0x44 ./src/delay.o
+                0x0000000008000624                delay_init
+ .text.timer_tick
+                0x0000000008000668       0x14 ./src/delay.o
+                0x0000000008000668                timer_tick
+ .text.delay_ms
+                0x000000000800067c       0x2c ./src/delay.o
+                0x000000000800067c                delay_ms
+ .text.SysTick_Handler
+                0x00000000080006a8       0x14 ./src/delay.o
+                0x00000000080006a8                SysTick_Handler
+ .text.i2c_init
+                0x00000000080006bc       0x7c ./src/i2c.o
+                0x00000000080006bc                i2c_init
+ .text.i2c_start
+                0x0000000008000738        0xc ./src/i2c.o
+                0x0000000008000738                i2c_start
+ .text.i2c_autoend
+                0x0000000008000744        0xa ./src/i2c.o
+                0x0000000008000744                i2c_autoend
+ *fill*         0x000000000800074e        0x2 
+ .text.i2c_set_nbytes
+                0x0000000008000750       0x18 ./src/i2c.o
+                0x0000000008000750                i2c_set_nbytes
+ .text.i2c_write_addr
+                0x0000000008000768       0x1e ./src/i2c.o
+                0x0000000008000768                i2c_write_addr
+ *fill*         0x0000000008000786        0x2 
+ .text.i2c_read_ack
+                0x0000000008000788       0xd0 ./src/i2c.o
+                0x0000000008000788                i2c_read_ack
+ .text.i2c_write
+                0x0000000008000858       0xc8 ./src/i2c.o
+                0x0000000008000858                i2c_write
+ .text.ili9341_updatedisplayclip
+                0x0000000008000920      0x108 ./src/ili9341.o
+                0x0000000008000920                ili9341_updatedisplayclip
+ .text.ili9341_setorigin
+                0x0000000008000a28       0x1c ./src/ili9341.o
+                0x0000000008000a28                ili9341_setorigin
+ .text.ili9341_setcliprect
+                0x0000000008000a44       0x3c ./src/ili9341.o
+                0x0000000008000a44                ili9341_setcliprect
+ .text.ili9341_hard_init
+                0x0000000008000a80       0x12 ./src/ili9341.o
+                0x0000000008000a80                ili9341_hard_init
+ *fill*         0x0000000008000a92        0x2 
+ .text.ili9341_writecommand8
+                0x0000000008000a94       0x20 ./src/ili9341.o
+                0x0000000008000a94                ili9341_writecommand8
+ .text.ili9341_writedata8
+                0x0000000008000ab4       0x20 ./src/ili9341.o
+                0x0000000008000ab4                ili9341_writedata8
+ .text.ili9341_setaddress
+                0x0000000008000ad4       0x50 ./src/ili9341.o
+                0x0000000008000ad4                ili9341_setaddress
+ .text.ili9341_init
+                0x0000000008000b24      0x202 ./src/ili9341.o
+                0x0000000008000b24                ili9341_init
+ .text.ili9341_pushcolor
+                0x0000000008000d26       0x12 ./src/ili9341.o
+                0x0000000008000d26                ili9341_pushcolor
+ .text.ili9341_clear
+                0x0000000008000d38       0x48 ./src/ili9341.o
+                0x0000000008000d38                ili9341_clear
+ .text.ili9341_drawpixel
+                0x0000000008000d80       0x3c ./src/ili9341.o
+                0x0000000008000d80                ili9341_drawpixel
+ .text.ili9341_drawvline
+                0x0000000008000dbc       0x50 ./src/ili9341.o
+                0x0000000008000dbc                ili9341_drawvline
+ .text.ili9341_drawhline
+                0x0000000008000e0c       0x64 ./src/ili9341.o
+                0x0000000008000e0c                ili9341_drawhline
+ .text.ili9341_fillrect
+                0x0000000008000e70       0x74 ./src/ili9341.o
+                0x0000000008000e70                ili9341_fillrect
+ .text.ili9341_setrotation
+                0x0000000008000ee4       0x5c ./src/ili9341.o
+                0x0000000008000ee4                ili9341_setrotation
+ .text.fetchbits_unsigned
+                0x0000000008000f40       0x3c ./src/ili9341gfx.o
+ .text.ili9341_setfont
+                0x0000000008000f7c       0x2c ./src/ili9341gfx.o
+                0x0000000008000f7c                ili9341_setfont
+ .text.ili9341_setcursor
+                0x0000000008000fa8       0x14 ./src/ili9341gfx.o
+                0x0000000008000fa8                ili9341_setcursor
+ .text.ili9341_settextcolor
+                0x0000000008000fbc       0x14 ./src/ili9341gfx.o
+                0x0000000008000fbc                ili9341_settextcolor
+ .text.ili9341_drawcharbits
+                0x0000000008000fd0      0x434 ./src/ili9341gfx.o
+                0x0000000008000fd0                ili9341_drawcharbits
+ .text.ili9341_drawfontbits
+                0x0000000008001404       0xf8 ./src/ili9341gfx.o
+                0x0000000008001404                ili9341_drawfontbits
+ .text.ili9341_drawfontchar
+                0x00000000080014fc      0x4bc ./src/ili9341gfx.o
+                0x00000000080014fc                ili9341_drawfontchar
+ .text.ili9341_drawchar
+                0x00000000080019b8       0xb0 ./src/ili9341gfx.o
+                0x00000000080019b8                ili9341_drawchar
+ .text.ili9341_out
+                0x0000000008001a68       0x2c ./src/ili9341gfx.o
+                0x0000000008001a68                ili9341_out
+ .text.i_to_a   0x0000000008001a94       0x32 ./src/main.o
+                0x0000000008001a94                i_to_a
+ *fill*         0x0000000008001ac6        0x2 
+ .text.encode_init
+                0x0000000008001ac8       0x30 ./src/main.o
+                0x0000000008001ac8                encode_init
+ .text.encode_read4
+                0x0000000008001af8       0x14 ./src/main.o
+                0x0000000008001af8                encode_read4
+ .text.mcp4728_set_reference
+                0x0000000008001b0c       0x20 ./src/main.o
+                0x0000000008001b0c                mcp4728_set_reference
+ .text.mcp4728_set_gain
+                0x0000000008001b2c       0x20 ./src/main.o
+                0x0000000008001b2c                mcp4728_set_gain
+ .text.mcp4728_set_pd
+                0x0000000008001b4c       0x20 ./src/main.o
+                0x0000000008001b4c                mcp4728_set_pd
+ .text.mcp4728_write_fast_dac
+                0x0000000008001b6c       0x44 ./src/main.o
+                0x0000000008001b6c                mcp4728_write_fast_dac
+ .text.mcp3421_config
+                0x0000000008001bb0       0xc8 ./src/main.o
+                0x0000000008001bb0                mcp3421_config
+ .text.mcp3421_read
+                0x0000000008001c78       0x38 ./src/main.o
+                0x0000000008001c78                mcp3421_read
+ .text.mcp9808_read
+                0x0000000008001cb0      0x138 ./src/main.o
+                0x0000000008001cb0                mcp9808_read
+ .text.mcp9808_setalert
+                0x0000000008001de8       0x80 ./src/main.o
+                0x0000000008001de8                mcp9808_setalert
+ .text.show_amperes
+                0x0000000008001e68       0xf0 ./src/main.o
+                0x0000000008001e68                show_amperes
+ .text.show_voltage
+                0x0000000008001f58       0xa8 ./src/main.o
+                0x0000000008001f58                show_voltage
+ .text.show_status
+                0x0000000008002000       0x90 ./src/main.o
+                0x0000000008002000                show_status
+ .text.show_watt
+                0x0000000008002090       0xa4 ./src/main.o
+                0x0000000008002090                show_watt
+ .text.show_resistance
+                0x0000000008002134       0xc0 ./src/main.o
+                0x0000000008002134                show_resistance
+ .text.show_cutoffvoltage
+                0x00000000080021f4       0x84 ./src/main.o
+                0x00000000080021f4                show_cutoffvoltage
+ .text.show_readbackcurrent
+                0x0000000008002278       0x98 ./src/main.o
+                0x0000000008002278                show_readbackcurrent
+ .text.show_temperature
+                0x0000000008002310      0x108 ./src/main.o
+                0x0000000008002310                show_temperature
+ .text.show_dacvals
+                0x0000000008002418       0x94 ./src/main.o
+                0x0000000008002418                show_dacvals
+ .text.fet_pulldown
+                0x00000000080024ac       0x28 ./src/main.o
+                0x00000000080024ac                fet_pulldown
+ .text.RCC_Configuration
+                0x00000000080024d4      0x108 ./src/main.o
+                0x00000000080024d4                RCC_Configuration
+ .text.startup.main
+                0x00000000080025dc     0x1008 ./src/main.o
+                0x00000000080025dc                main
+ .text.EXTI2_3_IRQHandler
+                0x00000000080035e4       0x2c ./src/main.o
+                0x00000000080035e4                EXTI2_3_IRQHandler
+ .text.SPI1_IRQHandler
+                0x0000000008003610       0x28 ./src/main.o
+                0x0000000008003610                SPI1_IRQHandler
+ .text.I2C1_IRQHandler
+                0x0000000008003638       0xac ./src/main.o
+                0x0000000008003638                I2C1_IRQHandler
+ .text.TIM16_IRQHandler
+                0x00000000080036e4      0x104 ./src/main.o
+                0x00000000080036e4                TIM16_IRQHandler
+ .text.TIM15_IRQHandler
+                0x00000000080037e8       0x24 ./src/main.o
+                0x00000000080037e8                TIM15_IRQHandler
+ .text.TIM14_IRQHandler
+                0x000000000800380c       0x38 ./src/main.o
+                0x000000000800380c                TIM14_IRQHandler
+ .text.RTC_IRQHandler
+                0x0000000008003844       0x5c ./src/main.o
+                0x0000000008003844                RTC_IRQHandler
+ .text          0x00000000080038a0       0x14 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_thumb1_case_shi.o)
+                0x00000000080038a0                __gnu_thumb1_case_shi
+ .text          0x00000000080038b4      0x114 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+                0x00000000080038b4                __udivsi3
+                0x00000000080038b4                __aeabi_uidiv
+                0x00000000080039c0                __aeabi_uidivmod
+ .text          0x00000000080039c8      0x1d4 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
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+                0x00000000080039c8                __divsi3
+                0x0000000008003b94                __aeabi_idivmod
+ .text          0x0000000008003b9c        0x4 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
+                0x0000000008003b9c                __aeabi_ldiv0
+                0x0000000008003b9c                __aeabi_idiv0
+ .text          0x0000000008003ba0       0x74 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_arm_cmpsf2.o)
+                0x0000000008003ba0                __aeabi_cfrcmple
+                0x0000000008003ba8                __aeabi_cfcmple
+                0x0000000008003ba8                __aeabi_cfcmpeq
+                0x0000000008003bb8                __aeabi_fcmpeq
+                0x0000000008003bc4                __aeabi_fcmplt
+                0x0000000008003bd8                __aeabi_fcmple
+                0x0000000008003bec                __aeabi_fcmpgt
+                0x0000000008003c00                __aeabi_fcmpge
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+                0x0000000008003c14                __fixunssfsi
+ .text          0x0000000008003c44      0x2f0 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(addsf3.o)
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+                0x0000000008004164                __eqsf2
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+                0x00000000080041b4                __gesf2
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+ .text          0x00000000080049e4       0xa8 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-memcpy-stub.o)
+                0x00000000080049e4                memcpy
+ .text          0x0000000008004a8c       0xa8 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-memset.o)
+                0x0000000008004a8c                memset
+ *(.rodata .rodata.* .constdata .constdata.*)
+ .rodata.CSWTCH.22
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+                0x0000000008005490                Arial_13
+ .rodata.Arial_13_data
+                0x00000000080054ac      0x4c7 ./src/font_Arial.o
+ .rodata.Arial_13_index
+                0x0000000008005973       0x83 ./src/font_Arial.o
+ *fill*         0x00000000080059f6        0x2 
+ .rodata.Arial_36
+                0x00000000080059f8       0x1c ./src/font_Arial.o
+                0x00000000080059f8                Arial_36
+ .rodata.Arial_36_data
+                0x0000000008005a14     0x18f0 ./src/font_Arial.o
+ .rodata.Arial_36_index
+                0x0000000008007304       0x9c ./src/font_Arial.o
+ .rodata.Arial_8
+                0x00000000080073a0       0x1c ./src/font_Arial.o
+                0x00000000080073a0                Arial_8
+ .rodata.Arial_8_data
+                0x00000000080073bc      0x290 ./src/font_Arial.o
+ .rodata.Arial_8_index
+                0x000000000800764c       0x77 ./src/font_Arial.o
+ *fill*         0x00000000080076c3        0x1 
+ .rodata.Arial_9
+                0x00000000080076c4       0x1c ./src/font_Arial.o
+                0x00000000080076c4                Arial_9
+ .rodata.Arial_9_data
+                0x00000000080076e0      0x303 ./src/font_Arial.o
+ .rodata.Arial_9_index
+                0x00000000080079e3       0x77 ./src/font_Arial.o
+ .rodata.glcdfont
+                0x0000000008007a5a      0x4fc ./src/glcdfont.o
+                0x0000000008007a5a                glcdfont
+ .rodata        0x0000000008007f56        0x3 ./src/main.o
+ .rodata.main.str1.1
+                0x0000000008007f59       0xab ./src/main.o
+                                         0xaf (size before relaxing)
+ .rodata.show_amperes.str1.1
+                0x0000000008008004        0x7 ./src/main.o
+ .rodata.show_cutoffvoltage.str1.1
+                0x000000000800800b        0x2 ./src/main.o
+ .rodata.show_dacvals.str1.1
+                0x000000000800800d        0x2 ./src/main.o
+ .rodata.show_readbackcurrent.str1.1
+                0x000000000800800d        0x2 ./src/main.o
+ .rodata.show_resistance.str1.1
+                0x000000000800800f        0x5 ./src/main.o
+ .rodata.show_status.str1.1
+                0x0000000008008014       0x10 ./src/main.o
+ .rodata.show_temperature.str1.1
+                0x0000000008008024        0x4 ./src/main.o
+                                          0x7 (size before relaxing)
+ .rodata.show_voltage.str1.1
+                0x0000000008008028        0x5 ./src/main.o
+ .rodata.show_watt.str1.1
+                0x000000000800802d        0x5 ./src/main.o
+ *fill*         0x0000000008008032        0x2 
+ .rodata        0x0000000008008034       0xac /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(divsf3.o)
+ .rodata        0x00000000080080e0       0x40 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(mulsf3.o)
+ *(vtable)
+ *(.eh_frame*)
+ *(.glue_7)
+ .glue_7        0x0000000008008120        0x0 linker stubs
+ *(.glue_7t)
+ .glue_7t       0x0000000008008120        0x0 linker stubs
+
+.vfp11_veneer   0x0000000008008120        0x0
+ .vfp11_veneer  0x0000000008008120        0x0 linker stubs
+
+.v4_bx          0x0000000008008120        0x0
+ .v4_bx         0x0000000008008120        0x0 linker stubs
+
+.iplt           0x0000000008008120        0x0
+ .iplt          0x0000000008008120        0x0 ./system/src/newlib/_exit.o
+
+.rel.dyn        0x0000000008008120        0x0
+ .rel.iplt      0x0000000008008120        0x0 ./system/src/newlib/_exit.o
+
+.ARM.extab
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+                0x0000000008008120                . = ALIGN (0x4)
+                0x0000000008008120                __exidx_start = .
+
+.ARM.exidx
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+                0x0000000008008120                __exidx_end = .
+                0x0000000008008120                . = ALIGN (0x4)
+                0x0000000008008120                _etext = .
+                0x0000000008008120                __etext = .
+
+.data_CCMRAM    0x0000000000000000        0x0 load address 0x0000000008008120
+ FILL mask 0xff
+ *(.data.CCMRAM .data.CCMRAM.*)
+                0x0000000000000000                . = ALIGN (0x4)
+                0x0000000008008120                _sidata = LOADADDR (.data)
+
+.data           0x0000000020000000       0x24 load address 0x0000000008008120
+ FILL mask 0xff
+                0x0000000020000000                _sdata = .
+                0x0000000020000000                __data_start__ = .
+ *(.data_begin .data_begin.*)
+ *(.data .data.*)
+ .data.argv.4353
+                0x0000000020000000        0x8 ./system/src/newlib/_syscalls.o
+ .data.AHBPrescTable
+                0x0000000020000008       0x10 ./system/src/cmsis/system_stm32f0xx.o
+                0x0000000020000008                AHBPrescTable
+ .data.SystemCoreClock
+                0x0000000020000018        0x4 ./system/src/cmsis/system_stm32f0xx.o
+                0x0000000020000018                SystemCoreClock
+ .data.TFT_HEIGHT
+                0x000000002000001c        0x2 ./src/ili9341.o
+                0x000000002000001c                TFT_HEIGHT
+ .data.TFT_WIDTH
+                0x000000002000001e        0x2 ./src/ili9341.o
+                0x000000002000001e                TFT_WIDTH
+ .data.check_temp
+                0x0000000020000020        0x1 ./src/main.o
+                0x0000000020000020                check_temp
+ .data.read_adc
+                0x0000000020000021        0x1 ./src/main.o
+                0x0000000020000021                read_adc
+ .data.set_mode
+                0x0000000020000022        0x1 ./src/main.o
+                0x0000000020000022                set_mode
+ *(.data_end .data_end.*)
+                0x0000000020000024                . = ALIGN (0x4)
+ *fill*         0x0000000020000023        0x1 ff
+                0x0000000020000024                _edata = .
+                0x0000000020000024                __data_end__ = .
+
+.igot.plt       0x0000000020000024        0x0 load address 0x0000000008008144
+ .igot.plt      0x0000000020000024        0x0 ./system/src/newlib/_exit.o
+
+.bss_CCMRAM     0x0000000000000000        0x0
+ *(.bss.CCMRAM .bss.CCMRAM.*)
+
+.bss            0x0000000020000024       0x90
+                0x0000000020000024                __bss_start__ = .
+                0x0000000020000024                _sbss = .
+ *(.bss_begin .bss_begin.*)
+ *(.bss .bss.*)
+ .bss.name.4352
+                0x0000000020000024        0x1 ./system/src/newlib/_syscalls.o
+ .bss.wrap      0x0000000020000025        0x1 ./src/ili9341gfx.o
+                0x0000000020000025                wrap
+ .bss.btn_hb    0x0000000020000026        0x2 ./src/main.o
+                0x0000000020000026                btn_hb
+ .bss.enc_last  0x0000000020000028        0x1 ./src/main.o
+ .bss.keyfunc   0x0000000020000029        0x1 ./src/main.o
+                0x0000000020000029                keyfunc
+ .bss.run       0x000000002000002a        0x1 ./src/main.o
+                0x000000002000002a                run
+ .bss.timeout   0x000000002000002b        0x1 ./src/main.o
+                0x000000002000002b                timeout
+ .bss.timer     0x000000002000002c        0x2 ./src/main.o
+                0x000000002000002c                timer
+ *(COMMON)
+ *fill*         0x000000002000002e        0x2 
+ COMMON         0x0000000020000030        0xc ./src/delay.o
+                0x0000000020000030                timer_delayCount
+                0x0000000020000034                us_ticks
+                0x0000000020000038                ticks
+ COMMON         0x000000002000003c       0x25 ./src/i2c.o
+                0x000000002000003c                i2c
+ *fill*         0x0000000020000061        0x1 
+ COMMON         0x0000000020000062       0x1a ./src/ili9341.o
+                0x0000000020000062                _invisible
+                0x0000000020000064                _originx
+                0x0000000020000066                _standard
+                0x0000000020000068                _clipy1
+                0x000000002000006a                _displayclipx1
+                0x000000002000006c                _clipy2
+                0x000000002000006e                _clipx2
+                0x0000000020000070                ili9341_buf
+                0x0000000020000072                _originy
+                0x0000000020000074                _displayclipy1
+                0x0000000020000076                _clipx1
+                0x0000000020000078                _displayclipy2
+                0x000000002000007a                _displayclipx2
+ COMMON         0x000000002000007c       0x36 ./src/ili9341gfx.o
+                0x000000002000007c                font
+                0x0000000020000098                cursor_y
+                0x000000002000009a                iactualx
+                0x000000002000009c                iactualy
+                0x000000002000009e                vactualx
+                0x00000000200000a0                isetx
+                0x00000000200000a2                vsety
+                0x00000000200000a4                vsetx
+                0x00000000200000a6                vactualy
+                0x00000000200000a8                cursor_x
+                0x00000000200000aa                textsize
+                0x00000000200000ac                isety
+                0x00000000200000ae                textbgcolor
+                0x00000000200000b0                textcolor
+ COMMON         0x00000000200000b2        0x1 ./src/main.o
+                0x00000000200000b2                enc_delta
+ *(.bss_end .bss_end.*)
+                0x00000000200000b4                . = ALIGN (0x4)
+ *fill*         0x00000000200000b3        0x1 
+                0x00000000200000b4                __bss_end__ = .
+                0x00000000200000b4                _ebss = .
+
+.noinit_CCMRAM
+ *(.noinit.CCMRAM .noinit.CCMRAM.*)
+
+.noinit         0x00000000200000b4        0x0
+                0x00000000200000b4                _noinit = .
+ *(.noinit .noinit.*)
+                0x00000000200000b4                . = ALIGN (0x4)
+                0x00000000200000b4                _end_noinit = .
+                [!provide]                        PROVIDE (end = _end_noinit)
+                [!provide]                        PROVIDE (_end = _end_noinit)
+                [!provide]                        PROVIDE (__end = _end_noinit)
+                [!provide]                        PROVIDE (__end__ = _end_noinit)
+
+._check_stack   0x00000000200000b4      0x100
+                0x00000000200001b4                . = (. + _Minimum_Stack_Size)
+ *fill*         0x00000000200000b4      0x100 
+
+.b1text
+ *(.b1text)
+ *(.b1rodata)
+ *(.b1rodata.*)
+
+.eb0text
+ *(.eb0text)
+ *(.eb0rodata)
+ *(.eb0rodata.*)
+
+.eb1text
+ *(.eb1text)
+ *(.eb1rodata)
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+ *(.eb2text)
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+ *(.eb2rodata.*)
+
+.eb3text
+ *(.eb3text)
+ *(.eb3rodata)
+ *(.eb3rodata.*)
+
+.stab
+ *(.stab)
+
+.stabstr
+ *(.stabstr)
+
+.stab.excl
+ *(.stab.excl)
+
+.stab.exclstr
+ *(.stab.exclstr)
+
+.stab.index
+ *(.stab.index)
+
+.stab.indexstr
+ *(.stab.indexstr)
+
+.comment        0x0000000000000000       0x9f
+ *(.comment)
+ .comment       0x0000000000000000       0x51 ./system/src/newlib/_exit.o
+                                         0x52 (size before relaxing)
+ .comment       0x0000000000000051       0x52 ./system/src/newlib/_startup.o
+ .comment       0x0000000000000051       0x52 ./system/src/newlib/_syscalls.o
+ .comment       0x0000000000000051       0x52 ./system/src/cortexm/_initialize_hardware.o
+ .comment       0x0000000000000051       0x52 ./system/src/cortexm/_reset_hardware.o
+ .comment       0x0000000000000051       0x52 ./system/src/cortexm/exception_handlers.o
+ .comment       0x0000000000000051       0x52 ./system/src/cmsis/system_stm32f0xx.o
+ .comment       0x0000000000000051       0x52 ./system/src/cmsis/vectors_stm32f0xx.o
+ .comment       0x0000000000000051       0x52 ./src/24aaxx.o
+ .comment       0x0000000000000051       0x52 ./src/delay.o
+ .comment       0x0000000000000051       0x52 ./src/font_Arial.o
+ .comment       0x0000000000000051       0x52 ./src/glcdfont.o
+ .comment       0x0000000000000051       0x52 ./src/i2c.o
+ .comment       0x0000000000000051       0x52 ./src/ili9341.o
+ .comment       0x0000000000000051       0x52 ./src/ili9341gfx.o
+ .comment       0x0000000000000051       0x52 ./src/main.o
+ .comment       0x0000000000000051       0x52 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_fixunssfsi.o)
+ .comment       0x0000000000000051       0x52 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(addsf3.o)
+ .comment       0x0000000000000051       0x52 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(divsf3.o)
+ .comment       0x0000000000000051       0x52 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(eqsf2.o)
+ .comment       0x0000000000000051       0x52 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(gesf2.o)
+ .comment       0x0000000000000051       0x52 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(lesf2.o)
+ .comment       0x0000000000000051       0x52 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(mulsf3.o)
+ .comment       0x0000000000000051       0x52 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(subsf3.o)
+ .comment       0x0000000000000051       0x52 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(fixsfsi.o)
+ .comment       0x0000000000000051       0x52 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(floatsisf.o)
+ .comment       0x0000000000000051       0x52 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(floatunsisf.o)
+ .comment       0x0000000000000051       0x4e /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-memcpy-stub.o)
+                                         0x4f (size before relaxing)
+ .comment       0x000000000000009f       0x4f /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-memset.o)
+
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+ .ARM.attributes
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+ .ARM.attributes
+                0x0000000000000058       0x2c ./system/src/newlib/_syscalls.o
+ .ARM.attributes
+                0x0000000000000084       0x2c ./system/src/cortexm/_initialize_hardware.o
+ .ARM.attributes
+                0x00000000000000b0       0x2c ./system/src/cortexm/_reset_hardware.o
+ .ARM.attributes
+                0x00000000000000dc       0x2c ./system/src/cortexm/exception_handlers.o
+ .ARM.attributes
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+ .ARM.attributes
+                0x0000000000000134       0x2c ./system/src/cmsis/vectors_stm32f0xx.o
+ .ARM.attributes
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+ .ARM.attributes
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+ .ARM.attributes
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+ .ARM.attributes
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+ .ARM.attributes
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+ .ARM.attributes
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+ .ARM.attributes
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+ .ARM.attributes
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+ .ARM.attributes
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+ .ARM.attributes
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+ .ARM.attributes
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+ .ARM.attributes
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+ .ARM.attributes
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+ .ARM.attributes
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+ .debug_line    0x0000000000008425      0x281 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-memset.o)
+
+.debug_frame    0x0000000000000000     0x1000
+ *(.debug_frame)
+ .debug_frame   0x0000000000000000       0x40 ./system/src/newlib/_exit.o
+ .debug_frame   0x0000000000000040       0x88 ./system/src/newlib/_startup.o
+ .debug_frame   0x00000000000000c8       0x50 ./system/src/newlib/_syscalls.o
+ .debug_frame   0x0000000000000118       0x40 ./system/src/cortexm/_initialize_hardware.o
+ .debug_frame   0x0000000000000158       0x20 ./system/src/cortexm/_reset_hardware.o
+ .debug_frame   0x0000000000000178       0x80 ./system/src/cortexm/exception_handlers.o
+ .debug_frame   0x00000000000001f8       0x48 ./system/src/cmsis/system_stm32f0xx.o
+ .debug_frame   0x0000000000000240       0x20 ./system/src/cmsis/vectors_stm32f0xx.o
+ .debug_frame   0x0000000000000260       0xc8 ./src/24aaxx.o
+ .debug_frame   0x0000000000000328       0x8c ./src/delay.o
+ .debug_frame   0x00000000000003b4       0xec ./src/i2c.o
+ .debug_frame   0x00000000000004a0      0x3b4 ./src/ili9341.o
+ .debug_frame   0x0000000000000854      0x14c ./src/ili9341gfx.o
+ .debug_frame   0x00000000000009a0      0x3ac ./src/main.o
+ .debug_frame   0x0000000000000d4c       0x20 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+ .debug_frame   0x0000000000000d6c       0x20 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
+ .debug_frame   0x0000000000000d8c       0x28 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_fixunssfsi.o)
+ .debug_frame   0x0000000000000db4       0x38 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(addsf3.o)
+ .debug_frame   0x0000000000000dec       0x38 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(divsf3.o)
+ .debug_frame   0x0000000000000e24       0x2c /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(eqsf2.o)
+ .debug_frame   0x0000000000000e50       0x30 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(gesf2.o)
+ .debug_frame   0x0000000000000e80       0x30 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(lesf2.o)
+ .debug_frame   0x0000000000000eb0       0x38 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(mulsf3.o)
+ .debug_frame   0x0000000000000ee8       0x3c /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(subsf3.o)
+ .debug_frame   0x0000000000000f24       0x20 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(fixsfsi.o)
+ .debug_frame   0x0000000000000f44       0x2c /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(floatsisf.o)
+ .debug_frame   0x0000000000000f70       0x2c /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(floatunsisf.o)
+ .debug_frame   0x0000000000000f9c       0x34 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-memcpy-stub.o)
+ .debug_frame   0x0000000000000fd0       0x30 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-memset.o)
+
+.debug_str      0x0000000000000000     0x3b99
+ *(.debug_str)
+ .debug_str     0x0000000000000000      0x57b ./system/src/newlib/_exit.o
+                                        0x631 (size before relaxing)
+ .debug_str     0x000000000000057b      0x16d ./system/src/newlib/_startup.o
+                                        0x360 (size before relaxing)
+ .debug_str     0x00000000000006e8       0x8a ./system/src/newlib/_syscalls.o
+                                        0x662 (size before relaxing)
+ .debug_str     0x0000000000000772       0x6e ./system/src/cortexm/_initialize_hardware.o
+                                        0x269 (size before relaxing)
+ .debug_str     0x00000000000007e0       0x79 ./system/src/cortexm/_reset_hardware.o
+                                        0x263 (size before relaxing)
+ .debug_str     0x0000000000000859       0xb0 ./system/src/cortexm/exception_handlers.o
+                                        0x6a6 (size before relaxing)
+ .debug_str     0x0000000000000909       0xf2 ./system/src/cmsis/system_stm32f0xx.o
+                                        0x307 (size before relaxing)
+ .debug_str     0x00000000000009fb       0x56 ./system/src/cmsis/vectors_stm32f0xx.o
+                                        0x216 (size before relaxing)
+ .debug_str     0x0000000000000a51      0x1af ./src/24aaxx.o
+                                        0x3b4 (size before relaxing)
+ .debug_str     0x0000000000000c00      0x25d ./src/delay.o
+                                        0x4b2 (size before relaxing)
+ .debug_str     0x0000000000000e5d      0x3de ./src/font_Arial.o
+                                        0x548 (size before relaxing)
+ .debug_str     0x000000000000123b       0x23 ./src/glcdfont.o
+                                        0x23f (size before relaxing)
+ .debug_str     0x000000000000125e       0x6d ./src/i2c.o
+                                        0x40b (size before relaxing)
+ .debug_str     0x00000000000012cb      0x487 ./src/ili9341.o
+                                        0xaf8 (size before relaxing)
+ .debug_str     0x0000000000001752      0x2ad ./src/ili9341gfx.o
+                                        0xb01 (size before relaxing)
+ .debug_str     0x00000000000019ff      0x4f0 ./src/main.o
+                                       0x12ea (size before relaxing)
+ .debug_str     0x0000000000001eef       0xa3 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_thumb1_case_shi.o)
+ .debug_str     0x0000000000001f92       0xa3 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+ .debug_str     0x0000000000001f92       0xa3 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
+ .debug_str     0x0000000000001f92       0xa3 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
+ .debug_str     0x0000000000001f92       0x30 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_arm_cmpsf2.o)
+                                         0xa3 (size before relaxing)
+ .debug_str     0x0000000000001fc2     0x1335 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_fixunssfsi.o)
+                                       0x142f (size before relaxing)
+ .debug_str     0x00000000000032f7      0x123 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(addsf3.o)
+                                        0x2f2 (size before relaxing)
+ .debug_str     0x000000000000341a      0x10a /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(divsf3.o)
+                                        0x317 (size before relaxing)
+ .debug_str     0x0000000000003524       0x2f /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(eqsf2.o)
+                                        0x229 (size before relaxing)
+ .debug_str     0x0000000000003553       0x34 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(gesf2.o)
+                                        0x24d (size before relaxing)
+ .debug_str     0x0000000000003587       0x10 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(lesf2.o)
+                                        0x24d (size before relaxing)
+ .debug_str     0x0000000000003597       0x78 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(mulsf3.o)
+                                        0x317 (size before relaxing)
+ .debug_str     0x000000000000360f       0x16 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(subsf3.o)
+                                        0x2f2 (size before relaxing)
+ .debug_str     0x0000000000003625       0x2a /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(fixsfsi.o)
+                                        0x233 (size before relaxing)
+ .debug_str     0x000000000000364f       0x45 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(floatsisf.o)
+                                        0x2b9 (size before relaxing)
+ .debug_str     0x0000000000003694       0x1b /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(floatunsisf.o)
+                                        0x2b5 (size before relaxing)
+ .debug_str     0x00000000000036af       0xa3 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_clzsi2.o)
+ .debug_str     0x00000000000036af      0x444 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-memcpy-stub.o)
+                                        0x92d (size before relaxing)
+ .debug_str     0x0000000000003af3       0xa6 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-memset.o)
+                                        0x908 (size before relaxing)
+
+.debug_loc      0x0000000000000000     0x9a57
+ *(.debug_loc)
+ .debug_loc     0x0000000000000000       0x25 ./system/src/newlib/_exit.o
+ .debug_loc     0x0000000000000025      0x322 ./system/src/newlib/_startup.o
+ .debug_loc     0x0000000000000347       0x6f ./system/src/newlib/_syscalls.o
+ .debug_loc     0x00000000000003b6       0x2a ./system/src/cortexm/exception_handlers.o
+ .debug_loc     0x00000000000003e0      0x110 ./system/src/cmsis/system_stm32f0xx.o
+ .debug_loc     0x00000000000004f0      0x820 ./src/24aaxx.o
+ .debug_loc     0x0000000000000d10       0x9e ./src/delay.o
+ .debug_loc     0x0000000000000dae      0x43f ./src/i2c.o
+ .debug_loc     0x00000000000011ed     0x27ac ./src/ili9341.o
+ .debug_loc     0x0000000000003999     0x1814 ./src/ili9341gfx.o
+ .debug_loc     0x00000000000051ad     0x1332 ./src/main.o
+ .debug_loc     0x00000000000064df       0x41 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(_fixunssfsi.o)
+ .debug_loc     0x0000000000006520      0x88d /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(addsf3.o)
+ .debug_loc     0x0000000000006dad      0x84d /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(divsf3.o)
+ .debug_loc     0x00000000000075fa      0x143 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(eqsf2.o)
+ .debug_loc     0x000000000000773d      0x259 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(gesf2.o)
+ .debug_loc     0x0000000000007996      0x24d /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(lesf2.o)
+ .debug_loc     0x0000000000007be3      0x8bd /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(mulsf3.o)
+ .debug_loc     0x00000000000084a0      0x8b3 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(subsf3.o)
+ .debug_loc     0x0000000000008d53       0xf3 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(fixsfsi.o)
+ .debug_loc     0x0000000000008e46      0x24d /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(floatsisf.o)
+ .debug_loc     0x0000000000009093      0x264 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(floatunsisf.o)
+ .debug_loc     0x00000000000092f7      0x481 /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-memcpy-stub.o)
+ .debug_loc     0x0000000000009778      0x2df /usr/lib/gcc/arm-none-eabi/8.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libg_nano.a(lib_a-memset.o)
+
+.debug_macinfo
+ *(.debug_macinfo)
+
+.debug_weaknames
+ *(.debug_weaknames)
+
+.debug_funcnames
+ *(.debug_funcnames)
+
+.debug_typenames
+ *(.debug_typenames)
+
+.debug_varnames
+ *(.debug_varnames)
+OUTPUT(arm-electronicload_rework_2022.elf elf32-littlearm)
+LOAD linker stubs
+
+.debug_ranges   0x0000000000000000      0xea0
+ .debug_ranges  0x0000000000000000       0x18 ./system/src/newlib/_exit.o
+ .debug_ranges  0x0000000000000018       0x98 ./system/src/newlib/_startup.o
+ .debug_ranges  0x00000000000000b0       0x20 ./system/src/newlib/_syscalls.o
+ .debug_ranges  0x00000000000000d0       0x18 ./system/src/cortexm/_initialize_hardware.o
+ .debug_ranges  0x00000000000000e8       0x10 ./system/src/cortexm/_reset_hardware.o
+ .debug_ranges  0x00000000000000f8       0x40 ./system/src/cortexm/exception_handlers.o
+ .debug_ranges  0x0000000000000138       0x30 ./system/src/cmsis/system_stm32f0xx.o
+ .debug_ranges  0x0000000000000168       0x10 ./system/src/cmsis/vectors_stm32f0xx.o
+ .debug_ranges  0x0000000000000178       0xa0 ./src/24aaxx.o
+ .debug_ranges  0x0000000000000218       0x70 ./src/delay.o
+ .debug_ranges  0x0000000000000288       0xd0 ./src/i2c.o
+ .debug_ranges  0x0000000000000358      0x318 ./src/ili9341.o
+ .debug_ranges  0x0000000000000670      0x190 ./src/ili9341gfx.o
+ .debug_ranges  0x0000000000000800      0x148 ./src/main.o
+ .debug_ranges  0x0000000000000948      0x198 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(addsf3.o)
+ .debug_ranges  0x0000000000000ae0       0x80 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(divsf3.o)
+ .debug_ranges  0x0000000000000b60       0x30 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(eqsf2.o)
+ .debug_ranges  0x0000000000000b90       0x58 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(gesf2.o)
+ .debug_ranges  0x0000000000000be8       0x58 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(lesf2.o)
+ .debug_ranges  0x0000000000000c40       0x58 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(mulsf3.o)
+ .debug_ranges  0x0000000000000c98      0x198 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(subsf3.o)
+ .debug_ranges  0x0000000000000e30       0x38 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(floatsisf.o)
+ .debug_ranges  0x0000000000000e68       0x38 /usr/lib/gcc/arm-none-eabi/8.3.1/thumb/v6-m/nofp/libgcc.a(floatunsisf.o)
diff --git a/Release/makefile b/Release/makefile

new file mode 100644 (file)

index 0000000..f14aa62
--- /dev/null
+++ b/Release/makefile
@@ -0,0 +1,103 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+-include ../makefile.init
+
+RM := rm -rf
+
+# All of the sources participating in the build are defined here
+-include sources.mk
+-include system/src/stm32f0-stdperiph/subdir.mk
+-include system/src/newlib/subdir.mk
+-include system/src/diag/subdir.mk
+-include system/src/cortexm/subdir.mk
+-include system/src/cmsis/subdir.mk
+-include src/subdir.mk
+-include subdir.mk
+-include objects.mk
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(CC_DEPS)),)
+-include $(CC_DEPS)
+endif
+ifneq ($(strip $(C++_DEPS)),)
+-include $(C++_DEPS)
+endif
+ifneq ($(strip $(C_UPPER_DEPS)),)
+-include $(C_UPPER_DEPS)
+endif
+ifneq ($(strip $(CXX_DEPS)),)
+-include $(CXX_DEPS)
+endif
+ifneq ($(strip $(ASM_DEPS)),)
+-include $(ASM_DEPS)
+endif
+ifneq ($(strip $(S_UPPER_DEPS)),)
+-include $(S_UPPER_DEPS)
+endif
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+ifneq ($(strip $(CPP_DEPS)),)
+-include $(CPP_DEPS)
+endif
+endif
+
+-include ../makefile.defs
+
+OPTIONAL_TOOL_DEPS := \
+$(wildcard ../makefile.defs) \
+$(wildcard ../makefile.init) \
+$(wildcard ../makefile.targets) \
+
+
+BUILD_ARTIFACT_NAME := arm-electronicload_rework_2022
+BUILD_ARTIFACT_EXTENSION := elf
+BUILD_ARTIFACT_PREFIX :=
+BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),)
+
+# Add inputs and outputs from these tool invocations to the build variables 
+SECONDARY_FLASH += \
+arm-electronicload_rework_2022.hex \
+
+SECONDARY_SIZE += \
+arm-electronicload_rework_2022.siz \
+
+
+# All Target
+all: main-build
+
+# Main-build Target
+main-build: arm-electronicload_rework_2022.elf secondary-outputs
+
+# Tool invocations
+arm-electronicload_rework_2022.elf: $(OBJS) $(USER_OBJS) makefile objects.mk $(OPTIONAL_TOOL_DEPS)
+       @echo 'Building target: $@'
+       @echo 'Invoking: GNU ARM Cross C++ Linker'
+       arm-none-eabi-g++ -mcpu=cortex-m0 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -Wall -Wextra  -g -T mem.ld -T libs.ld -T sections.ld -nostartfiles -Xlinker --gc-sections -L"../ldscripts" -Wl,-Map,"arm-electronicload_rework_2022.map" --specs=nano.specs -o "arm-electronicload_rework_2022.elf" $(OBJS) $(USER_OBJS) $(LIBS)
+       @echo 'Finished building target: $@'
+       @echo ' '
+
+arm-electronicload_rework_2022.hex: arm-electronicload_rework_2022.elf makefile objects.mk $(OPTIONAL_TOOL_DEPS)
+       @echo 'Invoking: GNU ARM Cross Create Flash Image'
+       arm-none-eabi-objcopy -O ihex "arm-electronicload_rework_2022.elf"  "arm-electronicload_rework_2022.hex"
+       @echo 'Finished building: $@'
+       @echo ' '
+
+arm-electronicload_rework_2022.siz: arm-electronicload_rework_2022.elf makefile objects.mk $(OPTIONAL_TOOL_DEPS)
+       @echo 'Invoking: GNU ARM Cross Print Size'
+       arm-none-eabi-size --format=berkeley "arm-electronicload_rework_2022.elf"
+       @echo 'Finished building: $@'
+       @echo ' '
+
+# Other Targets
+clean:
+       -$(RM) $(CC_DEPS)$(C++_DEPS)$(OBJS)$(C_UPPER_DEPS)$(CXX_DEPS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS) arm-electronicload_rework_2022.elf
+       -@echo ' '
+
+secondary-outputs: $(SECONDARY_FLASH) $(SECONDARY_SIZE)
+
+.PHONY: all clean dependents main-build
+
+-include ../makefile.targets
diff --git a/Release/objects.mk b/Release/objects.mk

new file mode 100644 (file)

index 0000000..742c2da
--- /dev/null
+++ b/Release/objects.mk
@@ -0,0 +1,8 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+USER_OBJS :=
+
+LIBS :=
+
diff --git a/Release/openocd.cfg b/Release/openocd.cfg

new file mode 100644 (file)

index 0000000..bb383e0
--- /dev/null
+++ b/Release/openocd.cfg
@@ -0,0 +1,8 @@
+source [find interface/stlink.cfg]
+#transport select "hla_swd"
+#reset_config connect_assert_srst
+#reset_config trst_only
+#reset_config srst_only srst_nogate
+#reset_config srst_only srst_nogate connect_assert_srst
+source [find target/stm32f0x.cfg]
+#reset_config srst_only  connect_assert_srst
diff --git a/Release/sources.mk b/Release/sources.mk

new file mode 100644 (file)

index 0000000..e07daad
--- /dev/null
+++ b/Release/sources.mk
@@ -0,0 +1,36 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+ELF_SRCS := 
+C_UPPER_SRCS := 
+CXX_SRCS := 
+C++_SRCS := 
+OBJ_SRCS := 
+CC_SRCS := 
+ASM_SRCS := 
+C_SRCS := 
+CPP_SRCS := 
+S_UPPER_SRCS := 
+O_SRCS := 
+CC_DEPS := 
+C++_DEPS := 
+OBJS := 
+C_UPPER_DEPS := 
+CXX_DEPS := 
+SECONDARY_FLASH := 
+SECONDARY_SIZE := 
+ASM_DEPS := 
+S_UPPER_DEPS := 
+C_DEPS := 
+CPP_DEPS := 
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+src \
+system/src/cmsis \
+system/src/cortexm \
+system/src/diag \
+system/src/newlib \
+system/src/stm32f0-stdperiph \
+
diff --git a/Release/src/24aaxx.d b/Release/src/24aaxx.d

new file mode 100644 (file)

index 0000000..c0e9ef4
--- /dev/null
+++ b/Release/src/24aaxx.d
@@ -0,0 +1,98 @@
+src/24aaxx.o: ../src/24aaxx.c ../include/i2c.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h \
+ ../system/include/cmsis/stm32f0xx.h ../system/include/cmsis/core_cm0.h \
+ ../system/include/cmsis/core_cmInstr.h \
+ ../system/include/cmsis/cmsis_gcc.h \
+ ../system/include/cmsis/core_cmFunc.h \
+ ../system/include/cmsis/system_stm32f0xx.h ../include/stm32f0xx_conf.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_adc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_can.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_cec.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_crc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_crs.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_comp.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dac.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dma.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_exti.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_flash.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_spi.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_tim.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_usart.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_misc.h ../include/24aaxx.h \
+ ../include/i2c.h ../include/delay.h
+
+../include/i2c.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h:
+
+../system/include/cmsis/stm32f0xx.h:
+
+../system/include/cmsis/core_cm0.h:
+
+../system/include/cmsis/core_cmInstr.h:
+
+../system/include/cmsis/cmsis_gcc.h:
+
+../system/include/cmsis/core_cmFunc.h:
+
+../system/include/cmsis/system_stm32f0xx.h:
+
+../include/stm32f0xx_conf.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_adc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_can.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_cec.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_crc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_crs.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_comp.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dac.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dma.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_exti.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_flash.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_spi.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_tim.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_usart.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_misc.h:
+
+../include/24aaxx.h:
+
+../include/i2c.h:
+
+../include/delay.h:
diff --git a/Release/src/24aaxx.o b/Release/src/24aaxx.o

new file mode 100644 (file)

index 0000000..170c766

Binary files /dev/null and b/Release/src/24aaxx.o differ
diff --git a/Release/src/BlinkLed.d b/Release/src/BlinkLed.d

new file mode 100644 (file)

index 0000000..33198cf
--- /dev/null
+++ b/Release/src/BlinkLed.d
@@ -0,0 +1,91 @@
+src/BlinkLed.o: ../src/BlinkLed.c ../include/BlinkLed.h \
+ ../system/include/cmsis/stm32f0xx.h ../system/include/cmsis/core_cm0.h \
+ ../system/include/cmsis/core_cmInstr.h \
+ ../system/include/cmsis/cmsis_gcc.h \
+ ../system/include/cmsis/core_cmFunc.h \
+ ../system/include/cmsis/system_stm32f0xx.h ../include/stm32f0xx_conf.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_adc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_can.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_cec.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_crc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_crs.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_comp.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dac.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dma.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_exti.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_flash.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_spi.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_tim.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_usart.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_misc.h
+
+../include/BlinkLed.h:
+
+../system/include/cmsis/stm32f0xx.h:
+
+../system/include/cmsis/core_cm0.h:
+
+../system/include/cmsis/core_cmInstr.h:
+
+../system/include/cmsis/cmsis_gcc.h:
+
+../system/include/cmsis/core_cmFunc.h:
+
+../system/include/cmsis/system_stm32f0xx.h:
+
+../include/stm32f0xx_conf.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_adc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_can.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_cec.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_crc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_crs.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_comp.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dac.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dma.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_exti.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_flash.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_spi.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_tim.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_usart.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_misc.h:
diff --git a/Release/src/BlinkLed.o b/Release/src/BlinkLed.o

new file mode 100644 (file)

index 0000000..77f98f5

Binary files /dev/null and b/Release/src/BlinkLed.o differ
diff --git a/Release/src/_write.d b/Release/src/_write.d

new file mode 100644 (file)

index 0000000..a5ae42c
--- /dev/null
+++ b/Release/src/_write.d
@@ -0,0 +1 @@
+src/_write.o: ../src/_write.c
diff --git a/Release/src/_write.o b/Release/src/_write.o

new file mode 100644 (file)

index 0000000..7e6823d

Binary files /dev/null and b/Release/src/_write.o differ
diff --git a/Release/src/delay.d b/Release/src/delay.d

new file mode 100644 (file)

index 0000000..5966aa4
--- /dev/null
+++ b/Release/src/delay.d
@@ -0,0 +1,91 @@
+src/delay.o: ../src/delay.c ../include/delay.h \
+ ../system/include/cmsis/stm32f0xx.h ../system/include/cmsis/core_cm0.h \
+ ../system/include/cmsis/core_cmInstr.h \
+ ../system/include/cmsis/cmsis_gcc.h \
+ ../system/include/cmsis/core_cmFunc.h \
+ ../system/include/cmsis/system_stm32f0xx.h ../include/stm32f0xx_conf.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_adc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_can.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_cec.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_crc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_crs.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_comp.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dac.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dma.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_exti.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_flash.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_spi.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_tim.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_usart.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_misc.h
+
+../include/delay.h:
+
+../system/include/cmsis/stm32f0xx.h:
+
+../system/include/cmsis/core_cm0.h:
+
+../system/include/cmsis/core_cmInstr.h:
+
+../system/include/cmsis/cmsis_gcc.h:
+
+../system/include/cmsis/core_cmFunc.h:
+
+../system/include/cmsis/system_stm32f0xx.h:
+
+../include/stm32f0xx_conf.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_adc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_can.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_cec.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_crc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_crs.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_comp.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dac.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dma.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_exti.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_flash.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_spi.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_tim.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_usart.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_misc.h:
diff --git a/Release/src/delay.o b/Release/src/delay.o

new file mode 100644 (file)

index 0000000..441f2d6

Binary files /dev/null and b/Release/src/delay.o differ
diff --git a/Release/src/font_Arial.d b/Release/src/font_Arial.d

new file mode 100644 (file)

index 0000000..b7be879
--- /dev/null
+++ b/Release/src/font_Arial.d
@@ -0,0 +1,6 @@
+src/font_Arial.o: ../src/font_Arial.c ../include/font_Arial.h \
+ ../include/font_typedef.h
+
+../include/font_Arial.h:
+
+../include/font_typedef.h:
diff --git a/Release/src/font_Arial.o b/Release/src/font_Arial.o

new file mode 100644 (file)

index 0000000..af3cb1d

Binary files /dev/null and b/Release/src/font_Arial.o differ
diff --git a/Release/src/glcdfont.d b/Release/src/glcdfont.d

new file mode 100644 (file)

index 0000000..3224f8f
--- /dev/null
+++ b/Release/src/glcdfont.d
@@ -0,0 +1,6 @@
+src/glcdfont.o: ../src/glcdfont.c ../include/glcdfont.h \
+ ../include/font_typedef.h
+
+../include/glcdfont.h:
+
+../include/font_typedef.h:
diff --git a/Release/src/glcdfont.o b/Release/src/glcdfont.o

new file mode 100644 (file)

index 0000000..69d95eb

Binary files /dev/null and b/Release/src/glcdfont.o differ
diff --git a/Release/src/i2c.d b/Release/src/i2c.d

new file mode 100644 (file)

index 0000000..48e1a60
--- /dev/null
+++ b/Release/src/i2c.d
@@ -0,0 +1,91 @@
+src/i2c.o: ../src/i2c.c \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h \
+ ../system/include/cmsis/stm32f0xx.h ../system/include/cmsis/core_cm0.h \
+ ../system/include/cmsis/core_cmInstr.h \
+ ../system/include/cmsis/cmsis_gcc.h \
+ ../system/include/cmsis/core_cmFunc.h \
+ ../system/include/cmsis/system_stm32f0xx.h ../include/stm32f0xx_conf.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_adc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_can.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_cec.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_crc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_crs.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_comp.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dac.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dma.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_exti.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_flash.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_spi.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_tim.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_usart.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_misc.h ../include/i2c.h
+
+../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h:
+
+../system/include/cmsis/stm32f0xx.h:
+
+../system/include/cmsis/core_cm0.h:
+
+../system/include/cmsis/core_cmInstr.h:
+
+../system/include/cmsis/cmsis_gcc.h:
+
+../system/include/cmsis/core_cmFunc.h:
+
+../system/include/cmsis/system_stm32f0xx.h:
+
+../include/stm32f0xx_conf.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_adc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_can.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_cec.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_crc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_crs.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_comp.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dac.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dma.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_exti.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_flash.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_spi.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_tim.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_usart.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_misc.h:
+
+../include/i2c.h:
diff --git a/Release/src/i2c.o b/Release/src/i2c.o

new file mode 100644 (file)

index 0000000..8b22d3b

Binary files /dev/null and b/Release/src/i2c.o differ
diff --git a/Release/src/ili9341.d b/Release/src/ili9341.d

new file mode 100644 (file)

index 0000000..317058d
--- /dev/null
+++ b/Release/src/ili9341.d
@@ -0,0 +1,93 @@
+src/ili9341.o: ../src/ili9341.c ../include/ili9341.h \
+ ../system/include/cmsis/stm32f0xx.h ../system/include/cmsis/core_cm0.h \
+ ../system/include/cmsis/core_cmInstr.h \
+ ../system/include/cmsis/cmsis_gcc.h \
+ ../system/include/cmsis/core_cmFunc.h \
+ ../system/include/cmsis/system_stm32f0xx.h ../include/stm32f0xx_conf.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_adc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_can.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_cec.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_crc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_crs.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_comp.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dac.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dma.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_exti.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_flash.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_spi.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_tim.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_usart.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_misc.h ../include/delay.h
+
+../include/ili9341.h:
+
+../system/include/cmsis/stm32f0xx.h:
+
+../system/include/cmsis/core_cm0.h:
+
+../system/include/cmsis/core_cmInstr.h:
+
+../system/include/cmsis/cmsis_gcc.h:
+
+../system/include/cmsis/core_cmFunc.h:
+
+../system/include/cmsis/system_stm32f0xx.h:
+
+../include/stm32f0xx_conf.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_adc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_can.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_cec.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_crc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_crs.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_comp.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dac.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dma.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_exti.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_flash.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_spi.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_tim.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_usart.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_misc.h:
+
+../include/delay.h:
diff --git a/Release/src/ili9341.o b/Release/src/ili9341.o

new file mode 100644 (file)

index 0000000..b07e4be

Binary files /dev/null and b/Release/src/ili9341.o differ
diff --git a/Release/src/ili9341gfx.d b/Release/src/ili9341gfx.d

new file mode 100644 (file)

index 0000000..753401c
--- /dev/null
+++ b/Release/src/ili9341gfx.d
@@ -0,0 +1,101 @@
+src/ili9341gfx.o: ../src/ili9341gfx.c ../include/ili9341.h \
+ ../system/include/cmsis/stm32f0xx.h ../system/include/cmsis/core_cm0.h \
+ ../system/include/cmsis/core_cmInstr.h \
+ ../system/include/cmsis/cmsis_gcc.h \
+ ../system/include/cmsis/core_cmFunc.h \
+ ../system/include/cmsis/system_stm32f0xx.h ../include/stm32f0xx_conf.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_adc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_can.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_cec.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_crc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_crs.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_comp.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dac.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dma.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_exti.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_flash.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_spi.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_tim.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_usart.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_misc.h \
+ ../include/ili9341gfx.h ../include/font_typedef.h ../include/glcdfont.h \
+ ../include/font_typedef.h
+
+../include/ili9341.h:
+
+../system/include/cmsis/stm32f0xx.h:
+
+../system/include/cmsis/core_cm0.h:
+
+../system/include/cmsis/core_cmInstr.h:
+
+../system/include/cmsis/cmsis_gcc.h:
+
+../system/include/cmsis/core_cmFunc.h:
+
+../system/include/cmsis/system_stm32f0xx.h:
+
+../include/stm32f0xx_conf.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_adc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_can.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_cec.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_crc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_crs.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_comp.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dac.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dma.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_exti.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_flash.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_spi.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_tim.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_usart.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_misc.h:
+
+../include/ili9341gfx.h:
+
+../include/font_typedef.h:
+
+../include/glcdfont.h:
+
+../include/font_typedef.h:
diff --git a/Release/src/ili9341gfx.o b/Release/src/ili9341gfx.o

new file mode 100644 (file)

index 0000000..b6b0961

Binary files /dev/null and b/Release/src/ili9341gfx.o differ
diff --git a/Release/src/main.d b/Release/src/main.d

new file mode 100644 (file)

index 0000000..266a91d
--- /dev/null
+++ b/Release/src/main.d
@@ -0,0 +1,112 @@
+src/main.o: ../src/main.c ../system/include/cmsis/stm32f0xx.h \
+ ../system/include/cmsis/core_cm0.h \
+ ../system/include/cmsis/core_cmInstr.h \
+ ../system/include/cmsis/cmsis_gcc.h \
+ ../system/include/cmsis/core_cmFunc.h \
+ ../system/include/cmsis/system_stm32f0xx.h ../include/stm32f0xx_conf.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_adc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_can.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_cec.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_crc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_crs.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_comp.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dac.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dma.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_exti.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_flash.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_spi.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_tim.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_usart.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_misc.h ../include/delay.h \
+ ../include/ili9341.h ../include/ili9341gfx.h ../include/font_typedef.h \
+ ../include/font_Arial.h ../include/glcdfont.h ../include/i2c.h \
+ ../include/24aaxx.h ../include/i2c.h ../include/delay.h
+
+../system/include/cmsis/stm32f0xx.h:
+
+../system/include/cmsis/core_cm0.h:
+
+../system/include/cmsis/core_cmInstr.h:
+
+../system/include/cmsis/cmsis_gcc.h:
+
+../system/include/cmsis/core_cmFunc.h:
+
+../system/include/cmsis/system_stm32f0xx.h:
+
+../include/stm32f0xx_conf.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_adc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_can.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_cec.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_crc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_crs.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_comp.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dac.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dma.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_exti.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_flash.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_spi.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_tim.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_usart.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_misc.h:
+
+../include/delay.h:
+
+../include/ili9341.h:
+
+../include/ili9341gfx.h:
+
+../include/font_typedef.h:
+
+../include/font_Arial.h:
+
+../include/glcdfont.h:
+
+../include/i2c.h:
+
+../include/24aaxx.h:
+
+../include/i2c.h:
+
+../include/delay.h:
diff --git a/Release/src/main.o b/Release/src/main.o

new file mode 100644 (file)

index 0000000..677ae17

Binary files /dev/null and b/Release/src/main.o differ
diff --git a/Release/src/mcp24aaxx.o b/Release/src/mcp24aaxx.o

new file mode 100644 (file)

index 0000000..a689e89

Binary files /dev/null and b/Release/src/mcp24aaxx.o differ
diff --git a/Release/src/subdir.mk b/Release/src/subdir.mk

new file mode 100644 (file)

index 0000000..0eab813
--- /dev/null
+++ b/Release/src/subdir.mk
@@ -0,0 +1,51 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../src/24aaxx.c \
+../src/BlinkLed.c \
+../src/_write.c \
+../src/delay.c \
+../src/font_Arial.c \
+../src/glcdfont.c \
+../src/i2c.c \
+../src/ili9341.c \
+../src/ili9341gfx.c \
+../src/main.c 
+
+OBJS += \
+./src/24aaxx.o \
+./src/BlinkLed.o \
+./src/_write.o \
+./src/delay.o \
+./src/font_Arial.o \
+./src/glcdfont.o \
+./src/i2c.o \
+./src/ili9341.o \
+./src/ili9341gfx.o \
+./src/main.o 
+
+C_DEPS += \
+./src/24aaxx.d \
+./src/BlinkLed.d \
+./src/_write.d \
+./src/delay.d \
+./src/font_Arial.d \
+./src/glcdfont.d \
+./src/i2c.d \
+./src/ili9341.d \
+./src/ili9341gfx.d \
+./src/main.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+src/%.o: ../src/%.c src/subdir.mk
+       @echo 'Building file: $<'
+       @echo 'Invoking: GNU ARM Cross C Compiler'
+       arm-none-eabi-gcc -mcpu=cortex-m0 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -Wall -Wextra  -g -DNDEBUG -DSTM32F030 -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=8000000 -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f0-stdperiph" -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<"
+       @echo 'Finished building: $<'
+       @echo ' '
+
+
diff --git a/Release/system/src/cmsis/subdir.mk b/Release/system/src/cmsis/subdir.mk

new file mode 100644 (file)

index 0000000..b3f75c0
--- /dev/null
+++ b/Release/system/src/cmsis/subdir.mk
@@ -0,0 +1,27 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../system/src/cmsis/system_stm32f0xx.c \
+../system/src/cmsis/vectors_stm32f0xx.c 
+
+OBJS += \
+./system/src/cmsis/system_stm32f0xx.o \
+./system/src/cmsis/vectors_stm32f0xx.o 
+
+C_DEPS += \
+./system/src/cmsis/system_stm32f0xx.d \
+./system/src/cmsis/vectors_stm32f0xx.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+system/src/cmsis/%.o: ../system/src/cmsis/%.c system/src/cmsis/subdir.mk
+       @echo 'Building file: $<'
+       @echo 'Invoking: GNU ARM Cross C Compiler'
+       arm-none-eabi-gcc -mcpu=cortex-m0 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -Wall -Wextra  -g -DNDEBUG -DSTM32F030 -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=8000000 -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f0-stdperiph" -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<"
+       @echo 'Finished building: $<'
+       @echo ' '
+
+
diff --git a/Release/system/src/cmsis/system_stm32f0xx.d b/Release/system/src/cmsis/system_stm32f0xx.d

new file mode 100644 (file)

index 0000000..264a885
--- /dev/null
+++ b/Release/system/src/cmsis/system_stm32f0xx.d
@@ -0,0 +1,90 @@
+system/src/cmsis/system_stm32f0xx.o: \
+ ../system/src/cmsis/system_stm32f0xx.c \
+ ../system/include/cmsis/stm32f0xx.h ../system/include/cmsis/core_cm0.h \
+ ../system/include/cmsis/core_cmInstr.h \
+ ../system/include/cmsis/cmsis_gcc.h \
+ ../system/include/cmsis/core_cmFunc.h \
+ ../system/include/cmsis/system_stm32f0xx.h ../include/stm32f0xx_conf.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_adc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_can.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_cec.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_crc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_crs.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_comp.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dac.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dma.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_exti.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_flash.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_spi.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_tim.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_usart.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_misc.h
+
+../system/include/cmsis/stm32f0xx.h:
+
+../system/include/cmsis/core_cm0.h:
+
+../system/include/cmsis/core_cmInstr.h:
+
+../system/include/cmsis/cmsis_gcc.h:
+
+../system/include/cmsis/core_cmFunc.h:
+
+../system/include/cmsis/system_stm32f0xx.h:
+
+../include/stm32f0xx_conf.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_adc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_can.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_cec.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_crc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_crs.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_comp.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dac.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dma.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_exti.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_flash.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_spi.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_tim.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_usart.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_misc.h:
diff --git a/Release/system/src/cmsis/system_stm32f0xx.o b/Release/system/src/cmsis/system_stm32f0xx.o

new file mode 100644 (file)

index 0000000..3c22bc5

Binary files /dev/null and b/Release/system/src/cmsis/system_stm32f0xx.o differ
diff --git a/Release/system/src/cmsis/vectors_stm32f0xx.d b/Release/system/src/cmsis/vectors_stm32f0xx.d

new file mode 100644 (file)

index 0000000..e1604ae
--- /dev/null
+++ b/Release/system/src/cmsis/vectors_stm32f0xx.d
@@ -0,0 +1,5 @@
+system/src/cmsis/vectors_stm32f0xx.o: \
+ ../system/src/cmsis/vectors_stm32f0xx.c \
+ ../system/include/cortexm/ExceptionHandlers.h
+
+../system/include/cortexm/ExceptionHandlers.h:
diff --git a/Release/system/src/cmsis/vectors_stm32f0xx.o b/Release/system/src/cmsis/vectors_stm32f0xx.o

new file mode 100644 (file)

index 0000000..58225a3

Binary files /dev/null and b/Release/system/src/cmsis/vectors_stm32f0xx.o differ
diff --git a/Release/system/src/cortexm/_initialize_hardware.d b/Release/system/src/cortexm/_initialize_hardware.d

new file mode 100644 (file)

index 0000000..64c3c8f
--- /dev/null
+++ b/Release/system/src/cortexm/_initialize_hardware.d
@@ -0,0 +1,96 @@
+system/src/cortexm/_initialize_hardware.o: \
+ ../system/src/cortexm/_initialize_hardware.c \
+ ../system/include/cmsis/cmsis_device.h \
+ ../system/include/cmsis/stm32f0xx.h ../system/include/cmsis/core_cm0.h \
+ ../system/include/cmsis/core_cmInstr.h \
+ ../system/include/cmsis/cmsis_gcc.h \
+ ../system/include/cmsis/core_cmFunc.h \
+ ../system/include/cmsis/system_stm32f0xx.h ../include/stm32f0xx_conf.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_adc.h \
+ ../system/include/cmsis/stm32f0xx.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_can.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_cec.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_crc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_crs.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_comp.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dac.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dma.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_exti.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_flash.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_spi.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_tim.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_usart.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_misc.h
+
+../system/include/cmsis/cmsis_device.h:
+
+../system/include/cmsis/stm32f0xx.h:
+
+../system/include/cmsis/core_cm0.h:
+
+../system/include/cmsis/core_cmInstr.h:
+
+../system/include/cmsis/cmsis_gcc.h:
+
+../system/include/cmsis/core_cmFunc.h:
+
+../system/include/cmsis/system_stm32f0xx.h:
+
+../include/stm32f0xx_conf.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_adc.h:
+
+../system/include/cmsis/stm32f0xx.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_can.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_cec.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_crc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_crs.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_comp.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dac.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dma.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_exti.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_flash.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_spi.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_tim.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_usart.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_misc.h:
diff --git a/Release/system/src/cortexm/_initialize_hardware.o b/Release/system/src/cortexm/_initialize_hardware.o

new file mode 100644 (file)

index 0000000..ef03704

Binary files /dev/null and b/Release/system/src/cortexm/_initialize_hardware.o differ
diff --git a/Release/system/src/cortexm/_reset_hardware.d b/Release/system/src/cortexm/_reset_hardware.d

new file mode 100644 (file)

index 0000000..6f77166
--- /dev/null
+++ b/Release/system/src/cortexm/_reset_hardware.d
@@ -0,0 +1,96 @@
+system/src/cortexm/_reset_hardware.o: \
+ ../system/src/cortexm/_reset_hardware.c \
+ ../system/include/cmsis/cmsis_device.h \
+ ../system/include/cmsis/stm32f0xx.h ../system/include/cmsis/core_cm0.h \
+ ../system/include/cmsis/core_cmInstr.h \
+ ../system/include/cmsis/cmsis_gcc.h \
+ ../system/include/cmsis/core_cmFunc.h \
+ ../system/include/cmsis/system_stm32f0xx.h ../include/stm32f0xx_conf.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_adc.h \
+ ../system/include/cmsis/stm32f0xx.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_can.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_cec.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_crc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_crs.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_comp.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dac.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dma.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_exti.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_flash.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_spi.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_tim.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_usart.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_misc.h
+
+../system/include/cmsis/cmsis_device.h:
+
+../system/include/cmsis/stm32f0xx.h:
+
+../system/include/cmsis/core_cm0.h:
+
+../system/include/cmsis/core_cmInstr.h:
+
+../system/include/cmsis/cmsis_gcc.h:
+
+../system/include/cmsis/core_cmFunc.h:
+
+../system/include/cmsis/system_stm32f0xx.h:
+
+../include/stm32f0xx_conf.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_adc.h:
+
+../system/include/cmsis/stm32f0xx.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_can.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_cec.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_crc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_crs.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_comp.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dac.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dma.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_exti.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_flash.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_spi.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_tim.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_usart.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_misc.h:
diff --git a/Release/system/src/cortexm/_reset_hardware.o b/Release/system/src/cortexm/_reset_hardware.o

new file mode 100644 (file)

index 0000000..8f45c58

Binary files /dev/null and b/Release/system/src/cortexm/_reset_hardware.o differ
diff --git a/Release/system/src/cortexm/exception_handlers.d b/Release/system/src/cortexm/exception_handlers.d

new file mode 100644 (file)

index 0000000..6d7ab44
--- /dev/null
+++ b/Release/system/src/cortexm/exception_handlers.d
@@ -0,0 +1,104 @@
+system/src/cortexm/exception_handlers.o: \
+ ../system/src/cortexm/exception_handlers.c \
+ ../system/include/cortexm/ExceptionHandlers.h \
+ ../system/include/cmsis/cmsis_device.h \
+ ../system/include/cmsis/stm32f0xx.h ../system/include/cmsis/core_cm0.h \
+ ../system/include/cmsis/core_cmInstr.h \
+ ../system/include/cmsis/cmsis_gcc.h \
+ ../system/include/cmsis/core_cmFunc.h \
+ ../system/include/cmsis/system_stm32f0xx.h ../include/stm32f0xx_conf.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_adc.h \
+ ../system/include/cmsis/stm32f0xx.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_can.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_cec.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_crc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_crs.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_comp.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dac.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dma.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_exti.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_flash.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_spi.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_tim.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_usart.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_misc.h \
+ ../system/include/arm/semihosting.h ../system/include/diag/Trace.h
+
+../system/include/cortexm/ExceptionHandlers.h:
+
+../system/include/cmsis/cmsis_device.h:
+
+../system/include/cmsis/stm32f0xx.h:
+
+../system/include/cmsis/core_cm0.h:
+
+../system/include/cmsis/core_cmInstr.h:
+
+../system/include/cmsis/cmsis_gcc.h:
+
+../system/include/cmsis/core_cmFunc.h:
+
+../system/include/cmsis/system_stm32f0xx.h:
+
+../include/stm32f0xx_conf.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_adc.h:
+
+../system/include/cmsis/stm32f0xx.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_can.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_cec.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_crc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_crs.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_comp.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dac.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dma.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_exti.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_flash.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_spi.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_tim.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_usart.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_misc.h:
+
+../system/include/arm/semihosting.h:
+
+../system/include/diag/Trace.h:
diff --git a/Release/system/src/cortexm/exception_handlers.o b/Release/system/src/cortexm/exception_handlers.o

new file mode 100644 (file)

index 0000000..b64e9de

Binary files /dev/null and b/Release/system/src/cortexm/exception_handlers.o differ
diff --git a/Release/system/src/cortexm/subdir.mk b/Release/system/src/cortexm/subdir.mk

new file mode 100644 (file)

index 0000000..f6937a2
--- /dev/null
+++ b/Release/system/src/cortexm/subdir.mk
@@ -0,0 +1,30 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../system/src/cortexm/_initialize_hardware.c \
+../system/src/cortexm/_reset_hardware.c \
+../system/src/cortexm/exception_handlers.c 
+
+OBJS += \
+./system/src/cortexm/_initialize_hardware.o \
+./system/src/cortexm/_reset_hardware.o \
+./system/src/cortexm/exception_handlers.o 
+
+C_DEPS += \
+./system/src/cortexm/_initialize_hardware.d \
+./system/src/cortexm/_reset_hardware.d \
+./system/src/cortexm/exception_handlers.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+system/src/cortexm/%.o: ../system/src/cortexm/%.c system/src/cortexm/subdir.mk
+       @echo 'Building file: $<'
+       @echo 'Invoking: GNU ARM Cross C Compiler'
+       arm-none-eabi-gcc -mcpu=cortex-m0 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -Wall -Wextra  -g -DNDEBUG -DSTM32F030 -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=8000000 -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f0-stdperiph" -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<"
+       @echo 'Finished building: $<'
+       @echo ' '
+
+
diff --git a/Release/system/src/diag/Trace.d b/Release/system/src/diag/Trace.d

new file mode 100644 (file)

index 0000000..5f594d2
--- /dev/null
+++ b/Release/system/src/diag/Trace.d
@@ -0,0 +1 @@
+system/src/diag/Trace.o: ../system/src/diag/Trace.c
diff --git a/Release/system/src/diag/Trace.o b/Release/system/src/diag/Trace.o

new file mode 100644 (file)

index 0000000..c717496

Binary files /dev/null and b/Release/system/src/diag/Trace.o differ
diff --git a/Release/system/src/diag/subdir.mk b/Release/system/src/diag/subdir.mk

new file mode 100644 (file)

index 0000000..e777294
--- /dev/null
+++ b/Release/system/src/diag/subdir.mk
@@ -0,0 +1,27 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../system/src/diag/Trace.c \
+../system/src/diag/trace_impl.c 
+
+OBJS += \
+./system/src/diag/Trace.o \
+./system/src/diag/trace_impl.o 
+
+C_DEPS += \
+./system/src/diag/Trace.d \
+./system/src/diag/trace_impl.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+system/src/diag/%.o: ../system/src/diag/%.c system/src/diag/subdir.mk
+       @echo 'Building file: $<'
+       @echo 'Invoking: GNU ARM Cross C Compiler'
+       arm-none-eabi-gcc -mcpu=cortex-m0 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -Wall -Wextra  -g -DNDEBUG -DSTM32F030 -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=8000000 -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f0-stdperiph" -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<"
+       @echo 'Finished building: $<'
+       @echo ' '
+
+
diff --git a/Release/system/src/diag/trace_impl.d b/Release/system/src/diag/trace_impl.d

new file mode 100644 (file)

index 0000000..8fa4b8b
--- /dev/null
+++ b/Release/system/src/diag/trace_impl.d
@@ -0,0 +1 @@
+system/src/diag/trace_impl.o: ../system/src/diag/trace_impl.c
diff --git a/Release/system/src/diag/trace_impl.o b/Release/system/src/diag/trace_impl.o

new file mode 100644 (file)

index 0000000..60e0903

Binary files /dev/null and b/Release/system/src/diag/trace_impl.o differ
diff --git a/Release/system/src/newlib/_cxx.d b/Release/system/src/newlib/_cxx.d

new file mode 100644 (file)

index 0000000..4acf981
--- /dev/null
+++ b/Release/system/src/newlib/_cxx.d
@@ -0,0 +1,4 @@
+system/src/newlib/_cxx.o: ../system/src/newlib/_cxx.cpp \
+ ../system/include/diag/Trace.h
+
+../system/include/diag/Trace.h:
diff --git a/Release/system/src/newlib/_cxx.o b/Release/system/src/newlib/_cxx.o

new file mode 100644 (file)

index 0000000..47395ab

Binary files /dev/null and b/Release/system/src/newlib/_cxx.o differ
diff --git a/Release/system/src/newlib/_exit.d b/Release/system/src/newlib/_exit.d

new file mode 100644 (file)

index 0000000..4c9b7c7
--- /dev/null
+++ b/Release/system/src/newlib/_exit.d
@@ -0,0 +1,4 @@
+system/src/newlib/_exit.o: ../system/src/newlib/_exit.c \
+ ../system/include/diag/Trace.h
+
+../system/include/diag/Trace.h:
diff --git a/Release/system/src/newlib/_exit.o b/Release/system/src/newlib/_exit.o

new file mode 100644 (file)

index 0000000..f7fac5c

Binary files /dev/null and b/Release/system/src/newlib/_exit.o differ
diff --git a/Release/system/src/newlib/_sbrk.d b/Release/system/src/newlib/_sbrk.d

new file mode 100644 (file)

index 0000000..9172f6d
--- /dev/null
+++ b/Release/system/src/newlib/_sbrk.d
@@ -0,0 +1 @@
+system/src/newlib/_sbrk.o: ../system/src/newlib/_sbrk.c
diff --git a/Release/system/src/newlib/_sbrk.o b/Release/system/src/newlib/_sbrk.o

new file mode 100644 (file)

index 0000000..85dd1c9

Binary files /dev/null and b/Release/system/src/newlib/_sbrk.o differ
diff --git a/Release/system/src/newlib/_startup.d b/Release/system/src/newlib/_startup.d

new file mode 100644 (file)

index 0000000..d63000e
--- /dev/null
+++ b/Release/system/src/newlib/_startup.d
@@ -0,0 +1 @@
+system/src/newlib/_startup.o: ../system/src/newlib/_startup.c
diff --git a/Release/system/src/newlib/_startup.o b/Release/system/src/newlib/_startup.o

new file mode 100644 (file)

index 0000000..130ae6f

Binary files /dev/null and b/Release/system/src/newlib/_startup.o differ
diff --git a/Release/system/src/newlib/_syscalls.d b/Release/system/src/newlib/_syscalls.d

new file mode 100644 (file)

index 0000000..e90abf5
--- /dev/null
+++ b/Release/system/src/newlib/_syscalls.d
@@ -0,0 +1 @@
+system/src/newlib/_syscalls.o: ../system/src/newlib/_syscalls.c
diff --git a/Release/system/src/newlib/_syscalls.o b/Release/system/src/newlib/_syscalls.o

new file mode 100644 (file)

index 0000000..48964af

Binary files /dev/null and b/Release/system/src/newlib/_syscalls.o differ
diff --git a/Release/system/src/newlib/assert.d b/Release/system/src/newlib/assert.d

new file mode 100644 (file)

index 0000000..ae4c8be
--- /dev/null
+++ b/Release/system/src/newlib/assert.d
@@ -0,0 +1,4 @@
+system/src/newlib/assert.o: ../system/src/newlib/assert.c \
+ ../system/include/diag/Trace.h
+
+../system/include/diag/Trace.h:
diff --git a/Release/system/src/newlib/assert.o b/Release/system/src/newlib/assert.o

new file mode 100644 (file)

index 0000000..d024177

Binary files /dev/null and b/Release/system/src/newlib/assert.o differ
diff --git a/Release/system/src/newlib/subdir.mk b/Release/system/src/newlib/subdir.mk

new file mode 100644 (file)

index 0000000..76c257e
--- /dev/null
+++ b/Release/system/src/newlib/subdir.mk
@@ -0,0 +1,50 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../system/src/newlib/_exit.c \
+../system/src/newlib/_sbrk.c \
+../system/src/newlib/_startup.c \
+../system/src/newlib/_syscalls.c \
+../system/src/newlib/assert.c 
+
+CPP_SRCS += \
+../system/src/newlib/_cxx.cpp 
+
+OBJS += \
+./system/src/newlib/_cxx.o \
+./system/src/newlib/_exit.o \
+./system/src/newlib/_sbrk.o \
+./system/src/newlib/_startup.o \
+./system/src/newlib/_syscalls.o \
+./system/src/newlib/assert.o 
+
+C_DEPS += \
+./system/src/newlib/_exit.d \
+./system/src/newlib/_sbrk.d \
+./system/src/newlib/_startup.d \
+./system/src/newlib/_syscalls.d \
+./system/src/newlib/assert.d 
+
+CPP_DEPS += \
+./system/src/newlib/_cxx.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+system/src/newlib/%.o: ../system/src/newlib/%.cpp system/src/newlib/subdir.mk
+       @echo 'Building file: $<'
+       @echo 'Invoking: GNU ARM Cross C++ Compiler'
+       arm-none-eabi-g++ -mcpu=cortex-m0 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -Wall -Wextra  -g -DNDEBUG -DSTM32F030 -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=8000000 -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f0-stdperiph" -std=gnu++11 -fabi-version=0 -fno-exceptions -fno-rtti -fno-use-cxa-atexit -fno-threadsafe-statics -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<"
+       @echo 'Finished building: $<'
+       @echo ' '
+
+system/src/newlib/%.o: ../system/src/newlib/%.c system/src/newlib/subdir.mk
+       @echo 'Building file: $<'
+       @echo 'Invoking: GNU ARM Cross C Compiler'
+       arm-none-eabi-gcc -mcpu=cortex-m0 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -Wall -Wextra  -g -DNDEBUG -DSTM32F030 -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=8000000 -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f0-stdperiph" -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<"
+       @echo 'Finished building: $<'
+       @echo ' '
+
+
diff --git a/Release/system/src/stm32f0-stdperiph/stm32f0xx_gpio.d b/Release/system/src/stm32f0-stdperiph/stm32f0xx_gpio.d

new file mode 100644 (file)

index 0000000..a39dbc3
--- /dev/null
+++ b/Release/system/src/stm32f0-stdperiph/stm32f0xx_gpio.d
@@ -0,0 +1,90 @@
+system/src/stm32f0-stdperiph/stm32f0xx_gpio.o: \
+ ../system/src/stm32f0-stdperiph/stm32f0xx_gpio.c \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h \
+ ../system/include/cmsis/stm32f0xx.h ../system/include/cmsis/core_cm0.h \
+ ../system/include/cmsis/core_cmInstr.h \
+ ../system/include/cmsis/cmsis_gcc.h \
+ ../system/include/cmsis/core_cmFunc.h \
+ ../system/include/cmsis/system_stm32f0xx.h ../include/stm32f0xx_conf.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_adc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_can.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_cec.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_crc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_crs.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_comp.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dac.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dma.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_exti.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_flash.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_spi.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_tim.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_usart.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_misc.h
+
+../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h:
+
+../system/include/cmsis/stm32f0xx.h:
+
+../system/include/cmsis/core_cm0.h:
+
+../system/include/cmsis/core_cmInstr.h:
+
+../system/include/cmsis/cmsis_gcc.h:
+
+../system/include/cmsis/core_cmFunc.h:
+
+../system/include/cmsis/system_stm32f0xx.h:
+
+../include/stm32f0xx_conf.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_adc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_can.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_cec.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_crc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_crs.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_comp.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dac.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dma.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_exti.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_flash.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_spi.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_tim.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_usart.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_misc.h:
diff --git a/Release/system/src/stm32f0-stdperiph/stm32f0xx_gpio.o b/Release/system/src/stm32f0-stdperiph/stm32f0xx_gpio.o

new file mode 100644 (file)

index 0000000..3accf16

Binary files /dev/null and b/Release/system/src/stm32f0-stdperiph/stm32f0xx_gpio.o differ
diff --git a/Release/system/src/stm32f0-stdperiph/stm32f0xx_rcc.d b/Release/system/src/stm32f0-stdperiph/stm32f0xx_rcc.d

new file mode 100644 (file)

index 0000000..b6493c9
--- /dev/null
+++ b/Release/system/src/stm32f0-stdperiph/stm32f0xx_rcc.d
@@ -0,0 +1,90 @@
+system/src/stm32f0-stdperiph/stm32f0xx_rcc.o: \
+ ../system/src/stm32f0-stdperiph/stm32f0xx_rcc.c \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h \
+ ../system/include/cmsis/stm32f0xx.h ../system/include/cmsis/core_cm0.h \
+ ../system/include/cmsis/core_cmInstr.h \
+ ../system/include/cmsis/cmsis_gcc.h \
+ ../system/include/cmsis/core_cmFunc.h \
+ ../system/include/cmsis/system_stm32f0xx.h ../include/stm32f0xx_conf.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_adc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_can.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_cec.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_crc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_crs.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_comp.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dac.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_dma.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_exti.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_flash.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_spi.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_tim.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_usart.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h \
+ ../system/include/stm32f0-stdperiph/stm32f0xx_misc.h
+
+../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h:
+
+../system/include/cmsis/stm32f0xx.h:
+
+../system/include/cmsis/core_cm0.h:
+
+../system/include/cmsis/core_cmInstr.h:
+
+../system/include/cmsis/cmsis_gcc.h:
+
+../system/include/cmsis/core_cmFunc.h:
+
+../system/include/cmsis/system_stm32f0xx.h:
+
+../include/stm32f0xx_conf.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_adc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_can.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_cec.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_crc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_crs.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_comp.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dac.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_dma.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_exti.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_flash.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_spi.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_tim.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_usart.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h:
+
+../system/include/stm32f0-stdperiph/stm32f0xx_misc.h:
diff --git a/Release/system/src/stm32f0-stdperiph/stm32f0xx_rcc.o b/Release/system/src/stm32f0-stdperiph/stm32f0xx_rcc.o

new file mode 100644 (file)

index 0000000..5d09ed5

Binary files /dev/null and b/Release/system/src/stm32f0-stdperiph/stm32f0xx_rcc.o differ
diff --git a/Release/system/src/stm32f0-stdperiph/subdir.mk b/Release/system/src/stm32f0-stdperiph/subdir.mk

new file mode 100644 (file)

index 0000000..3fe6a68
--- /dev/null
+++ b/Release/system/src/stm32f0-stdperiph/subdir.mk
@@ -0,0 +1,27 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../system/src/stm32f0-stdperiph/stm32f0xx_gpio.c \
+../system/src/stm32f0-stdperiph/stm32f0xx_rcc.c 
+
+OBJS += \
+./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o \
+./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o 
+
+C_DEPS += \
+./system/src/stm32f0-stdperiph/stm32f0xx_gpio.d \
+./system/src/stm32f0-stdperiph/stm32f0xx_rcc.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+system/src/stm32f0-stdperiph/%.o: ../system/src/stm32f0-stdperiph/%.c system/src/stm32f0-stdperiph/subdir.mk
+       @echo 'Building file: $<'
+       @echo 'Invoking: GNU ARM Cross C Compiler'
+       arm-none-eabi-gcc -mcpu=cortex-m0 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -Wall -Wextra  -g -DNDEBUG -DSTM32F030 -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=8000000 -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f0-stdperiph" -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<"
+       @echo 'Finished building: $<'
+       @echo ' '
+
+
diff --git a/include/24aaxx.h b/include/24aaxx.h

new file mode 100644 (file)

index 0000000..8e10880
--- /dev/null
+++ b/include/24aaxx.h
@@ -0,0 +1,23 @@
+/*
+ * mcp24aaxx.h
+ *
+ *  Created on: Oct 8, 2017
+ *      Author: pascal.spring
+ */
+
+#ifndef _24AAXX_H_
+#define _24AAXX_H_
+
+#define _24AAXX 0x50
+
+#include "i2c.h"
+#include "delay.h"
+
+extern struct i2c_struct_type i2c;
+
+void _24aa02_write(I2C_TypeDef * I2Cx, uint8_t addr, uint32_t data, uint8_t word);
+uint32_t _24aa02_read(I2C_TypeDef * I2Cx, uint8_t addr, uint8_t word);
+void _24aa32_write(I2C_TypeDef * I2Cx, uint16_t addr, uint32_t data, uint8_t word);
+uint32_t _24aa32_read(I2C_TypeDef * I2Cx, uint16_t addr, uint8_t word);
+
+#endif /* _24AAXX_H_ */
diff --git a/include/BlinkLed.h b/include/BlinkLed.h

new file mode 100644 (file)

index 0000000..2189efe
--- /dev/null
+++ b/include/BlinkLed.h
@@ -0,0 +1,92 @@
+/*
+ * This file is part of the ??OS++ distribution.
+ *   (https://github.com/micro-os-plus)
+ * Copyright (c) 2014 Liviu Ionescu.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef BLINKLED_H_
+#define BLINKLED_H_
+
+#include "stm32f0xx.h"
+
+// ----- LED definitions ------------------------------------------------------
+
+// Adjust these definitions for your own board.
+
+// STM32F0DISCOVERY definitions (GREEN led, C9, active high)
+// (SEGGER J-Link device name: STM32F051R8).
+
+// Port numbers: 0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, ...
+#define BLINK_PORT_NUMBER               (2)
+#define BLINK_PIN_NUMBER                (9)
+#define BLINK_ACTIVE_LOW                (0)
+
+#define BLINK_GPIOx(_N)                 ((GPIO_TypeDef *)(GPIOA_BASE + (GPIOB_BASE-GPIOA_BASE)*(_N)))
+#define BLINK_PIN_MASK(_N)              (1 << (_N))
+#define BLINK_RCC_MASKx(_N)             (RCC_AHBPeriph_GPIOA << (_N))
+// ----------------------------------------------------------------------------
+
+extern
+void
+blink_led_init(void);
+
+// ----------------------------------------------------------------------------
+
+inline void
+blink_led_on(void);
+
+inline void
+blink_led_off(void);
+
+// ----------------------------------------------------------------------------
+
+inline void
+__attribute__((always_inline))
+blink_led_on(void)
+{
+#if (BLINK_ACTIVE_LOW)
+  GPIO_ResetBits(BLINK_GPIOx(BLINK_PORT_NUMBER),
+      BLINK_PIN_MASK(BLINK_PIN_NUMBER));
+#else
+  GPIO_SetBits(BLINK_GPIOx(BLINK_PORT_NUMBER),
+      BLINK_PIN_MASK(BLINK_PIN_NUMBER));
+#endif
+}
+
+inline void
+__attribute__((always_inline))
+blink_led_off(void)
+{
+#if (BLINK_ACTIVE_LOW)
+  GPIO_SetBits(BLINK_GPIOx(BLINK_PORT_NUMBER),
+      BLINK_PIN_MASK(BLINK_PIN_NUMBER));
+#else
+  GPIO_ResetBits(BLINK_GPIOx(BLINK_PORT_NUMBER),
+      BLINK_PIN_MASK(BLINK_PIN_NUMBER));
+#endif
+}
+
+// ----------------------------------------------------------------------------
+
+#endif // BLINKLED_H_
diff --git a/include/Timer.h b/include/Timer.h

new file mode 100644 (file)

index 0000000..57a817a
--- /dev/null
+++ b/include/Timer.h
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the ??OS++ distribution.
+ *   (https://github.com/micro-os-plus)
+ * Copyright (c) 2014 Liviu Ionescu.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef TIMER_H_
+#define TIMER_H_
+
+#include "cmsis_device.h"
+
+// ----------------------------------------------------------------------------
+
+#define TIMER_FREQUENCY_HZ (1000u)
+
+typedef uint32_t timer_ticks_t;
+
+extern volatile timer_ticks_t timer_delayCount;
+
+extern void
+timer_start (void);
+
+extern void
+timer_sleep (timer_ticks_t ticks);
+
+// ----------------------------------------------------------------------------
+
+#endif // TIMER_H_
diff --git a/include/delay.h b/include/delay.h

new file mode 100644 (file)

index 0000000..d922845
--- /dev/null
+++ b/include/delay.h
@@ -0,0 +1,28 @@
+#ifndef DELAY_H
+#define DELAY_H
+
+#include <stdint.h>
+#include <stm32f0xx.h>
+
+#define TIMER_FREQUENCY_HZ (1000u)
+
+typedef uint32_t timer_ticks_t;
+
+extern volatile timer_ticks_t timer_delayCount;
+
+extern void
+delay_init (void);
+
+extern void
+timer_sleep (timer_ticks_t ticks);
+
+extern void
+delay_ms(timer_ticks_t ticks);
+
+extern void
+delay_us(timer_ticks_t ticks);
+/*
+extern void
+delay_us(timer_ticks_t ticks);
+*/
+#endif
diff --git a/include/font_Arial.h b/include/font_Arial.h

new file mode 100644 (file)

index 0000000..7e1bb75
--- /dev/null
+++ b/include/font_Arial.h
@@ -0,0 +1,31 @@
+#ifndef _font_Arial_
+#define _font_Arial_
+
+//#include "ILI9341_t3.h"
+#include "font_typedef.h"
+
+
+extern const ILI9341_t3_font_t Arial_8;
+extern const ILI9341_t3_font_t Arial_9;
+extern const ILI9341_t3_font_t Arial_10;
+extern const ILI9341_t3_font_t Arial_11;
+extern const ILI9341_t3_font_t Arial_12;
+extern const ILI9341_t3_font_t Arial_13;
+extern const ILI9341_t3_font_t Arial_14;
+extern const ILI9341_t3_font_t Arial_16;
+extern const ILI9341_t3_font_t Arial_18;
+extern const ILI9341_t3_font_t Arial_20;
+extern const ILI9341_t3_font_t Arial_24;
+extern const ILI9341_t3_font_t Arial_28;
+extern const ILI9341_t3_font_t Arial_32;
+extern const ILI9341_t3_font_t Arial_36;
+extern const ILI9341_t3_font_t Arial_37;
+extern const ILI9341_t3_font_t Arial_38;
+extern const ILI9341_t3_font_t Arial_40;
+extern const ILI9341_t3_font_t Arial_48;
+extern const ILI9341_t3_font_t Arial_60;
+extern const ILI9341_t3_font_t Arial_72;
+extern const ILI9341_t3_font_t Arial_96;
+
+
+#endif
diff --git a/include/font_typedef.h b/include/font_typedef.h

new file mode 100644 (file)

index 0000000..289e716
--- /dev/null
+++ b/include/font_typedef.h
@@ -0,0 +1,24 @@
+#ifndef INC_FONT_TYPEDEF_H_
+#define INC_FONT_TYPEDEF_H_
+
+typedef struct {
+        const unsigned char *index;
+        const unsigned char *unicode;
+        const unsigned char *data;
+        unsigned char version;
+        unsigned char reserved;
+        unsigned char index1_first;
+        unsigned char index1_last;
+        unsigned char index2_first;
+        unsigned char index2_last;
+        unsigned char bits_index;
+        unsigned char bits_width;
+        unsigned char bits_height;
+        unsigned char bits_xoffset;
+        unsigned char bits_yoffset;
+        unsigned char bits_delta;
+        unsigned char line_space;
+        unsigned char cap_height;
+} ILI9341_t3_font_t;
+
+#endif /* INC_FONT_TYPEDEF_H_ */
diff --git a/include/glcdfont.h b/include/glcdfont.h

new file mode 100644 (file)

index 0000000..767728e
--- /dev/null
+++ b/include/glcdfont.h
@@ -0,0 +1,9 @@
+#ifndef _ILI9341_t3_font_5x7_
+#define _ILI9341_t3_font_5x7_
+
+#include "font_typedef.h"
+
+const unsigned char glcdfont[1276];
+const ILI9341_t3_font_t Font5x7;
+
+#endif  /* INC_GLCDFONT_H_ */
diff --git a/include/i2c.h b/include/i2c.h

new file mode 100644 (file)

index 0000000..5fd6b05
--- /dev/null
+++ b/include/i2c.h
@@ -0,0 +1,65 @@
+/*
+ * i2c.h
+ *
+ *  Created on: Sep 30, 2017
+ *      Author: pascal.spring
+ */
+
+#ifndef I2C_H_
+#define I2C_H_
+
+#ifndef __STM32F10X_I2C_H
+#include <stm32f0xx_i2c.h>
+#endif
+
+#define READ 1
+#define WRITE 0
+#define I2C_SPEED 100000UL
+#define I2C__SLAVE_SUPPORT
+
+struct i2c_struct_type
+{
+       volatile uint8_t rx_buf[16];
+       volatile uint8_t tx_buf[16];
+       volatile uint8_t rx_idx;
+       volatile uint8_t tx_idx;
+       volatile uint8_t state;
+       volatile uint8_t device;
+       volatile uint8_t buf_cnt;
+};
+
+
+typedef enum
+{
+    I2C_IDLE = 0,
+    I2C_SENDING_START = 1,
+    I2C_SENDING_ADDRESS = 2,
+    I2C_SENDING_DATA = 3,
+    I2C_RECEIVING_DATA = 4,
+    I2C_SENDING_RESTART = 5,
+    I2C_ERROR = 6,
+#ifdef I2C__SLAVE_SUPPORT
+    I2C_SL_TX,
+    I2C_SL_RX,
+#endif
+}
+i2c_state_t;
+
+void i2c_init(I2C_TypeDef * I2Cx);
+uint8_t i2c_status(uint8_t stat);
+void i2c_start(I2C_TypeDef * I2Cx);
+void i2c_restart(void);
+void i2c_stop(I2C_TypeDef * I2Cx);
+void i2c_reset(I2C_TypeDef * I2Cx);
+void i2c_autoend(I2C_TypeDef * I2Cx, uint8_t autoend);
+void i2c_set_nbytes(I2C_TypeDef * I2Cx, uint8_t nbytes);
+uint8_t i2c_read_nack(void);
+//uint8_t i2c_read_ack(void);
+uint8_t i2c_read_ack(I2C_TypeDef * I2Cx, uint8_t * data, uint8_t count, uint8_t device);
+void i2c_write_addr(I2C_TypeDef * I2Cx, uint8_t addr, uint8_t dir);
+uint8_t i2c_write(I2C_TypeDef * I2Cx, uint8_t * data, uint8_t count, uint8_t device );
+//void i2c_write(uint8_t data);
+
+
+
+#endif /* I2C_H_ */
diff --git a/include/ili9341.h b/include/ili9341.h

new file mode 100644 (file)

index 0000000..97781f7
--- /dev/null
+++ b/include/ili9341.h
@@ -0,0 +1,112 @@
+#ifndef __ILI9341_H
+#define __ILI9341_H
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <inttypes.h>
+#include <stdarg.h>
+#include <limits.h>
+#include <stm32f0xx.h>
+
+#define ILI9341_TFTWIDTH 320UL
+#define ILI9341_TFTHEIGHT 240UL
+
+#define CS ((uint32_t)0x10)
+#define RST ((uint32_t)0x8)
+#define DC ((uint32_t)0x4)
+
+
+#define VIRIDIAN       0x440D
+#define EMERALD                0x54CA
+#define GREEN          0x6586
+#define DARKGREEN      0x0320
+#define GREENYELLOW 0xDFE1
+#define FAINTGREEN     0x32C6
+#define LIME           0x27E1
+
+#define ULTRAPURPLE 0x381F
+#define DARKPURPLE  0x981F
+#define NPURPLE                0x89D2
+#define PURPLE         0xD01F
+#define LILAS          0xF81B
+#define RED                    0xF804
+
+#define BLACK       0x0000
+#define NAVY        0x000F
+//#define DARKGREEN   0x03E0
+#define DARKCYAN    0x03EF
+#define MAROON      0x7800
+//#define PURPLE      0x780F
+#define OLIVE       0x7BE0
+#define LIGHTGREY   0xC618
+#define DARKGREY    0x7BEF
+#define BLUE        0x001F
+//#define GREEN       0x07E0
+#define CYAN        0x07FF
+//#define RED         0xF800
+#define MAGENTA     0xF81F
+#define YELLOW      0xFFE0
+#define MARINE                 0x041F
+#define NBLUE          0x41DF
+#define WHITE       0xFFFF
+#define ORANGE      0xFD20
+#define DARKORANGE  0xFAE0
+//#define GREENYELLOW 0xAFE5
+#define PINK        0xF81F
+#define LIGHTBLUE      0x031F
+#define GOLD           0xFE80
+#define NGOLD          0xFD88
+
+#define AMPERE      0xF802
+#define VOLT        0xFD80
+#define WATT        0x36A0
+#define OHM         0x3117
+
+
+volatile uint8_t ili9341_buf;
+
+int16_t _originx, _originy;
+int16_t _displayclipx1, _displayclipy1, _displayclipx2, _displayclipy2;
+int16_t _clipx1, _clipy1, _clipx2, _clipy2;
+uint8_t _invisible;
+uint8_t _standard;
+
+int16_t width(void);
+int16_t height(void);
+
+void ili9341_updatedisplayclip();
+void ili9341_setorigin(void);
+//void getOrigin(int16_t *x, int16_t *y);
+void ili9341_setcliprect();
+void ili9341_hard_init(void);
+void ili9341_hard_reset(void);
+void ili9341_spi_init(void);
+void ili9341_spi_send(SPI_TypeDef * SPIx, uint16_t spi_data);
+void ili9341_writecommand8(uint8_t com);
+void ili9341_writedata8(uint8_t data);
+void ili9341_writedata16(uint16_t data);
+void ili9341_setaddress(uint16_t x1,uint16_t y1,uint16_t x2,uint16_t y2);
+void ili9341_init(void);
+void ili9341_pushcolor(uint16_t color);
+void ili9341_clear(uint16_t color);
+void ili9341_drawpixel(int16_t x3,int16_t y3,uint16_t color1);
+void ili9341_drawvline(uint16_t x,uint16_t y,uint16_t h,uint16_t color);
+void ili9341_drawhline(int16_t x,int16_t y,uint16_t w,uint16_t color);
+void ili9341_drawline(int16_t x0, int16_t y0, int16_t x1, int16_t y1, uint16_t color);
+void ili9341_drawcirclehelper(int16_t x0, int16_t y0, int16_t r,uint8_t cornername, uint16_t color);
+void ili9341_fillcirclehelper(int16_t x0, int16_t y0, int16_t r,uint8_t cornername, int16_t delta,uint16_t color);
+void ili9341_drawrect(uint16_t x, uint16_t y, uint16_t w, uint16_t h,uint16_t color);
+void ili9341_fillrect(uint16_t x,uint16_t y,uint16_t w,uint16_t h,uint16_t color);
+void ili9341_drawroundrect(int16_t x, int16_t y, int16_t w, int16_t h,int16_t r, uint16_t color);
+void ili9341_fillroundrect(int16_t x, int16_t y, int16_t w, int16_t h,int16_t r, uint16_t color);
+void ili9341_drawhollowcircle(uint16_t X, uint16_t Y, uint16_t radius, uint16_t color);
+void ili9341_drawfilledcircle(uint16_t X, uint16_t Y, uint16_t radius, uint16_t color);
+void ili9341_drawtriangle(int16_t x0, int16_t y0, int16_t x1, int16_t y1, int16_t x2, int16_t y2, uint16_t color);
+void ili9341_filltriangle(int16_t x0, int16_t y0,int16_t x1, int16_t y1,int16_t x2, int16_t y2, uint16_t color);
+void ili9341_fillrecthgradient(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color1, uint16_t color2);
+void ili9341_fillrectvgradient(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color1, uint16_t color2);
+void ili9341_setrotation(uint8_t x);
+
+#endif
diff --git a/include/ili9341gfx.h b/include/ili9341gfx.h

new file mode 100644 (file)

index 0000000..dc638fe
--- /dev/null
+++ b/include/ili9341gfx.h
@@ -0,0 +1,29 @@
+#ifndef ILI9341GFX_H
+#define ILI9341GFX_H
+#endif
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <inttypes.h>
+#include <stdarg.h>
+#include <limits.h>
+#include "font_typedef.h"
+
+
+void ili9341_setfont(const ILI9341_t3_font_t f);
+void ili9341_setcursor(uint16_t x,uint16_t y);
+void ili9341_settextcolor(uint16_t x,uint16_t y);
+void ili9341_settextsize(uint8_t s);
+void ili9341_drawcharbits(int16_t x, int16_t y, char c,uint16_t fgcolor, uint16_t bgcolor, uint8_t size_x,uint8_t size_y);
+void ili9341_drawfontbits(uint8_t opaque, uint32_t bits, uint32_t numbits, int32_t x, int32_t y, uint32_t repeat);
+void ili9341_drawfontchar(unsigned char c);
+void ili9341_drawchar(char c);
+void backuplocationvset(void);
+void backuplocationvactual(void);
+void backuplocationiset(void);
+void backuplocationiactual(void);
+void ili9341_out(char *strn);
+//void display_init(void);
+
diff --git a/include/stm32f0xx_conf.h b/include/stm32f0xx_conf.h

new file mode 100644 (file)

index 0000000..35dcdd7
--- /dev/null
+++ b/include/stm32f0xx_conf.h
@@ -0,0 +1,83 @@
+/**
+  ******************************************************************************
+  * @file    Project/STM32F0xx_StdPeriph_Templates/stm32f0xx_conf.h 
+  * @author  MCD Application Team
+  * @version V1.3.1
+  * @date    17-January-2014
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_CONF_H
+#define __STM32F0XX_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Comment the line below to disable peripheral header file inclusion */
+#include "stm32f0xx_adc.h"
+#include "stm32f0xx_can.h"
+#include "stm32f0xx_cec.h"
+#include "stm32f0xx_crc.h"
+#include "stm32f0xx_crs.h"
+#include "stm32f0xx_comp.h"
+#include "stm32f0xx_dac.h"
+#include "stm32f0xx_dbgmcu.h"
+#include "stm32f0xx_dma.h"
+#include "stm32f0xx_exti.h"
+#include "stm32f0xx_flash.h"
+#include "stm32f0xx_gpio.h"
+#include "stm32f0xx_syscfg.h"
+#include "stm32f0xx_i2c.h"
+#include "stm32f0xx_iwdg.h"
+#include "stm32f0xx_pwr.h"
+#include "stm32f0xx_rcc.h"
+#include "stm32f0xx_rtc.h"
+#include "stm32f0xx_spi.h"
+#include "stm32f0xx_tim.h"
+#include "stm32f0xx_usart.h"
+#include "stm32f0xx_wwdg.h"
+#include "stm32f0xx_misc.h"  /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function which reports 
+  *         the name of the source file and the source line number of the call 
+  *         that failed. If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F0XX_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ldscripts/libs.ld b/ldscripts/libs.ld

new file mode 100644 (file)

index 0000000..70fea89
--- /dev/null
+++ b/ldscripts/libs.ld
@@ -0,0 +1,8 @@
+
+/*
+ * Placeholder to list other libraries required by the application.
+ 
+GROUP(
+)
+
+ */
diff --git a/ldscripts/mem.ld b/ldscripts/mem.ld

new file mode 100644 (file)

index 0000000..74a3e9a
--- /dev/null
+++ b/ldscripts/mem.ld
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the ??OS++ distribution.
+ *   (https://github.com/micro-os-plus)
+ * Copyright (c) 2014 Liviu Ionescu.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Memory Spaces Definitions.
+ *
+ * Need modifying for a specific board. 
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ *
+ * The values below can be addressed in further linker scripts
+ * using functions like 'ORIGIN(RAM)' or 'LENGTH(RAM)'.
+ */
+
+MEMORY
+{
+  RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 8K
+  CCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 0
+  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 64K
+  FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0
+  EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0
+  EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0
+  EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0
+  EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0
+  MEMORY_ARRAY (xrw)  : ORIGIN = 0x00000000, LENGTH = 0
+}
+
+/*
+ * For external ram use something like:
+
+  RAM (xrw) : ORIGIN = 0x68000000, LENGTH = 8K
+
+ */
diff --git a/ldscripts/sections.ld b/ldscripts/sections.ld

new file mode 100644 (file)

index 0000000..a6432cb
--- /dev/null
+++ b/ldscripts/sections.ld
@@ -0,0 +1,473 @@
+/*
+ * This file is part of the ??OS++ distribution.
+ *   (https://github.com/micro-os-plus)
+ * Copyright (c) 2014 Liviu Ionescu.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Default linker script for Cortex-M (it includes specifics for 
+ * STM32F[34]xx).
+ * 
+ * To make use of the multi-region initialisations, define
+ * OS_INCLUDE_STARTUP_INIT_MULTIPLE_RAM_SECTIONS for the _startup.c file.
+ */
+
+/*
+ * The '__stack' definition is required by crt0, do not remove it.
+ */
+__stack = ORIGIN(RAM) + LENGTH(RAM);
+
+_estack = __stack;     /* STM specific definition */
+
+/*
+ * Default stack sizes.
+ * These are used by the startup in order to allocate stacks 
+ * for the different modes.
+ */
+
+__Main_Stack_Size = 1024 ;
+
+PROVIDE ( _Main_Stack_Size = __Main_Stack_Size ) ;
+
+__Main_Stack_Limit = __stack  - __Main_Stack_Size ;
+
+/* "PROVIDE" allows to easily override these values from an 
+ * object file or the command line. */
+PROVIDE ( _Main_Stack_Limit = __Main_Stack_Limit ) ;
+
+/*
+ * There will be a link error if there is not this amount of 
+ * RAM free at the end. 
+ */
+_Minimum_Stack_Size = 256 ;
+
+/*
+ * Default heap definitions.
+ * The heap start immediately after the last statically allocated 
+ * .sbss/.noinit section, and extends up to the main stack limit.
+ */
+PROVIDE ( _Heap_Begin = _end_noinit ) ;
+PROVIDE ( _Heap_Limit = __stack - __Main_Stack_Size ) ;
+
+/* 
+ * The entry point is informative, for debuggers and simulators,
+ * since the Cortex-M vector points to it anyway.
+ */
+ENTRY(_start)
+
+
+/* Sections Definitions */
+
+SECTIONS
+{
+    /*
+     * For Cortex-M devices, the beginning of the startup code is stored in
+     * the .isr_vector section, which goes to FLASH. 
+     */
+    .isr_vector : ALIGN(4)
+    {
+        FILL(0xFF)
+        
+        __vectors_start = ABSOLUTE(.) ;
+        __vectors_start__ = ABSOLUTE(.) ; /* STM specific definition */
+        KEEP(*(.isr_vector))           /* Interrupt vectors */
+        
+               KEEP(*(.cfmconfig))                     /* Freescale configuration words */   
+                    
+        /* 
+         * This section is here for convenience, to store the
+         * startup code at the beginning of the flash area, hoping that
+         * this will increase the readability of the listing.
+         */
+        *(.after_vectors .after_vectors.*)     /* Startup code and ISR */
+
+    } >FLASH
+
+    .inits : ALIGN(4)
+    {
+        /* 
+         * Memory regions initialisation arrays.
+         *
+         * Thee are two kinds of arrays for each RAM region, one for 
+         * data and one for bss. Each is iterrated at startup and the   
+         * region initialisation is performed.
+         * 
+         * The data array includes:
+         * - from (LOADADDR())
+         * - region_begin (ADDR())
+         * - region_end (ADDR()+SIZEOF())
+         *
+         * The bss array includes:
+         * - region_begin (ADDR())
+         * - region_end (ADDR()+SIZEOF())
+         *
+         * WARNING: It is mandatory that the regions are word aligned, 
+         * since the initialisation code works only on words.
+         */
+         
+        __data_regions_array_start = .;
+        
+        LONG(LOADADDR(.data));
+        LONG(ADDR(.data));
+        LONG(ADDR(.data)+SIZEOF(.data));
+        
+        LONG(LOADADDR(.data_CCMRAM));
+        LONG(ADDR(.data_CCMRAM));
+        LONG(ADDR(.data_CCMRAM)+SIZEOF(.data_CCMRAM));
+        
+        __data_regions_array_end = .;
+        
+        __bss_regions_array_start = .;
+        
+        LONG(ADDR(.bss));
+        LONG(ADDR(.bss)+SIZEOF(.bss));
+        
+        LONG(ADDR(.bss_CCMRAM));
+        LONG(ADDR(.bss_CCMRAM)+SIZEOF(.bss_CCMRAM));
+        
+        __bss_regions_array_end = .;
+
+        /* End of memory regions initialisation arrays. */
+    
+        /*
+         * These are the old initialisation sections, intended to contain
+         * naked code, with the prologue/epilogue added by crti.o/crtn.o
+         * when linking with startup files. The standalone startup code
+         * currently does not run these, better use the init arrays below.
+         */
+               KEEP(*(.init))
+               KEEP(*(.fini))
+
+               . = ALIGN(4);
+
+               /*
+         * The preinit code, i.e. an array of pointers to initialisation 
+         * functions to be performed before constructors.
+         */
+               PROVIDE_HIDDEN (__preinit_array_start = .);
+        
+        /*
+         * Used to run the SystemInit() before anything else.
+         */
+               KEEP(*(.preinit_array_sysinit .preinit_array_sysinit.*))
+        
+        /* 
+         * Used for other platform inits.
+         */
+               KEEP(*(.preinit_array_platform .preinit_array_platform.*))
+        
+        /*
+         * The application inits. If you need to enforce some order in 
+         * execution, create new sections, as before.
+         */
+               KEEP(*(.preinit_array .preinit_array.*))
+
+               PROVIDE_HIDDEN (__preinit_array_end = .);
+
+               . = ALIGN(4);
+
+               /*
+         * The init code, i.e. an array of pointers to static constructors.
+         */
+               PROVIDE_HIDDEN (__init_array_start = .);
+               KEEP(*(SORT(.init_array.*)))
+               KEEP(*(.init_array))
+               PROVIDE_HIDDEN (__init_array_end = .);
+
+               . = ALIGN(4);
+
+               /*
+         * The fini code, i.e. an array of pointers to static destructors.
+         */
+               PROVIDE_HIDDEN (__fini_array_start = .);
+               KEEP(*(SORT(.fini_array.*)))
+               KEEP(*(.fini_array))
+               PROVIDE_HIDDEN (__fini_array_end = .);
+
+    } >FLASH
+
+    /*
+     * For some STRx devices, the beginning of the startup code
+     * is stored in the .flashtext section, which goes to FLASH.
+     */
+    .flashtext : ALIGN(4)
+    {
+        *(.flashtext .flashtext.*)     /* Startup code */
+    } >FLASH
+ 
+    
+    /*
+     * The program code is stored in the .text section, 
+     * which goes to FLASH.
+     */
+    .text : ALIGN(4)
+    {
+        *(.text .text.*)                       /* all remaining code */
+ 
+               /* read-only data (constants) */
+        *(.rodata .rodata.* .constdata .constdata.*)           
+
+        *(vtable)                                      /* C++ virtual tables */
+
+               KEEP(*(.eh_frame*))
+
+               /*
+                * Stub sections generated by the linker, to glue together 
+                * ARM and Thumb code. .glue_7 is used for ARM code calling 
+                * Thumb code, and .glue_7t is used for Thumb code calling 
+                * ARM code. Apparently always generated by the linker, for some
+                * architectures, so better leave them here.
+                */
+        *(.glue_7)
+        *(.glue_7t)
+
+    } >FLASH
+
+       /* ARM magic sections */
+       .ARM.extab : ALIGN(4)
+       {
+       *(.ARM.extab* .gnu.linkonce.armextab.*)
+       } > FLASH
+       
+    . = ALIGN(4);
+       __exidx_start = .;      
+       .ARM.exidx : ALIGN(4)
+       {
+       *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+       } > FLASH
+       __exidx_end = .;
+       
+    . = ALIGN(4);
+    _etext = .;
+    __etext = .;
+    
+    /* MEMORY_ARRAY */
+    /*
+    .ROarraySection :
+    {
+       *(.ROarraySection .ROarraySection.*)                          
+    } >MEMORY_ARRAY
+    */
+
+       /*
+        * The secondary initialised data section.
+        */
+    .data_CCMRAM : ALIGN(4)
+    {
+       FILL(0xFF)
+       *(.data.CCMRAM .data.CCMRAM.*)
+       . = ALIGN(4) ;
+    } > CCMRAM AT>FLASH
+
+       /* 
+     * This address is used by the startup code to 
+     * initialise the .data section.
+     */
+    _sidata = LOADADDR(.data);
+
+    /*
+     * The initialised data section.
+     *
+     * The program executes knowing that the data is in the RAM
+     * but the loader puts the initial values in the FLASH (inidata).
+     * It is one task of the startup to copy the initial values from 
+     * FLASH to RAM.
+     */
+    .data : ALIGN(4)
+    {
+       FILL(0xFF)
+        /* This is used by the startup code to initialise the .data section */
+        _sdata = . ;           /* STM specific definition */
+        __data_start__ = . ;
+               *(.data_begin .data_begin.*)
+
+               *(.data .data.*)
+               
+               *(.data_end .data_end.*)
+           . = ALIGN(4);
+
+           /* This is used by the startup code to initialise the .data section */
+        _edata = . ;           /* STM specific definition */
+        __data_end__ = . ;
+
+    } >RAM AT>FLASH
+    
+    /*
+     * The uninitialised data sections. NOLOAD is used to avoid
+     * the "section `.bss' type changed to PROGBITS" warning
+     */
+     
+    /* The secondary uninitialised data section. */
+       .bss_CCMRAM (NOLOAD) : ALIGN(4)
+       {
+               *(.bss.CCMRAM .bss.CCMRAM.*)
+       } > CCMRAM
+
+    /* The primary uninitialised data section. */
+    .bss (NOLOAD) : ALIGN(4)
+    {
+        __bss_start__ = .;             /* standard newlib definition */
+        _sbss = .;              /* STM specific definition */
+        *(.bss_begin .bss_begin.*)
+
+        *(.bss .bss.*)
+        *(COMMON)
+        
+        *(.bss_end .bss_end.*)
+           . = ALIGN(4);
+        __bss_end__ = .;        /* standard newlib definition */
+        _ebss = . ;             /* STM specific definition */
+    } >RAM
+
+    .noinit_CCMRAM (NOLOAD) : ALIGN(4)
+    {
+        *(.noinit.CCMRAM .noinit.CCMRAM.*)         
+    } > CCMRAM
+    
+    .noinit (NOLOAD) : ALIGN(4)
+    {
+        _noinit = .;
+        
+        *(.noinit .noinit.*) 
+        
+         . = ALIGN(4) ;
+        _end_noinit = .;   
+    } > RAM
+    
+    /* Mandatory to be word aligned, _sbrk assumes this */
+    PROVIDE ( end = _end_noinit ); /* was _ebss */
+    PROVIDE ( _end = _end_noinit );
+    PROVIDE ( __end = _end_noinit );
+    PROVIDE ( __end__ = _end_noinit );
+    
+    /*
+     * Used for validation only, do not allocate anything here!
+     *
+     * This is just to check that there is enough RAM left for the Main
+     * stack. It should generate an error if it's full.
+     */
+    ._check_stack : ALIGN(4)
+    {
+        . = . + _Minimum_Stack_Size ;
+    } >RAM
+    
+    /*
+     * The FLASH Bank1.
+     * The C or assembly source must explicitly place the code 
+     * or data there using the "section" attribute.
+     */
+    .b1text : ALIGN(4)
+    {
+        *(.b1text)                   /* remaining code */
+        *(.b1rodata)                 /* read-only data (constants) */
+        *(.b1rodata.*)
+    } >FLASHB1
+    
+    /*
+     * The EXTMEM.
+     * The C or assembly source must explicitly place the code or data there
+     * using the "section" attribute.
+     */
+
+    /* EXTMEM Bank0 */
+    .eb0text : ALIGN(4)
+    {
+        *(.eb0text)                   /* remaining code */
+        *(.eb0rodata)                 /* read-only data (constants) */
+        *(.eb0rodata.*)
+    } >EXTMEMB0
+    
+    /* EXTMEM Bank1 */
+    .eb1text : ALIGN(4)
+    {
+        *(.eb1text)                   /* remaining code */
+        *(.eb1rodata)                 /* read-only data (constants) */
+        *(.eb1rodata.*)
+    } >EXTMEMB1
+    
+    /* EXTMEM Bank2 */
+    .eb2text : ALIGN(4)
+    {
+        *(.eb2text)                   /* remaining code */
+        *(.eb2rodata)                 /* read-only data (constants) */
+        *(.eb2rodata.*)
+    } >EXTMEMB2
+    
+    /* EXTMEM Bank0 */
+    .eb3text : ALIGN(4)
+    {
+        *(.eb3text)                   /* remaining code */
+        *(.eb3rodata)                 /* read-only data (constants) */
+        *(.eb3rodata.*)
+    } >EXTMEMB3
+   
+
+    /* After that there are only debugging sections. */
+    
+    /* This can remove the debugging information from the standard libraries */    
+    /* 
+    DISCARD :
+    {
+     libc.a ( * )
+     libm.a ( * )
+     libgcc.a ( * )
+     }
+     */
+  
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /*
+     * DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  
+     */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }    
+}
diff --git a/src/.main.c.swo b/src/.main.c.swo

new file mode 100644 (file)

index 0000000..ec1263b

Binary files /dev/null and b/src/.main.c.swo differ
diff --git a/src/24aaxx.c b/src/24aaxx.c

new file mode 100644 (file)

index 0000000..ad82449
--- /dev/null
+++ b/src/24aaxx.c
@@ -0,0 +1,320 @@
+/*
+ * mcp24aaxx.c
+ *
+ *  Created on: Oct 8, 2017
+ *      Author: pascal.spring
+ */
+
+#include "i2c.h"
+#include "24aaxx.h"
+
+
+uint8_t wordlength(uint8_t wl)
+{
+       if(wl & 0x4)            // dword
+       {
+               wl=4;
+       }
+       else if(wl & 0x2)
+       {
+               wl=2;                                   // word
+       }
+       else if(wl & 0x1)
+       {
+               wl=1;
+       }
+       else
+       {
+               wl=1;
+       }
+       return wl;
+}
+
+uint32_t mask(uint8_t wl)
+{
+       uint32_t mask=0;
+
+       switch(wl)
+       {
+       case 4:
+               mask=0xff000000;
+               break;
+       case 2:
+               mask=0xff00;
+               break;
+       case 1:
+               mask=0xff;
+               break;
+       }
+
+       return mask;
+}
+
+uint8_t shift(uint8_t wl)
+{
+       uint8_t shift=0;
+
+       switch(wl)
+       {
+       case 4:
+               shift=24;
+               break;
+       case 2:
+               shift=8;
+               break;
+       case 1:
+               shift=0;
+               break;
+       }
+
+       return shift;
+}
+
+/* suitable for all EEPROMs 24AA01 to 24AA16; 24AA04 no A0, 24AA08 no A0 & A1, 24AA16 no A0,A1 & A2, pages are addressed by I2C address  */
+
+void _24aa02_write(I2C_TypeDef * I2Cx, uint8_t addr, uint32_t data, uint8_t word) {                                                    // attention: internal write cycle is 6ms, otherwise NACK is sent
+
+       uint32_t msk;
+       uint16_t cycle;
+       uint8_t shft;
+       uint8_t wl;
+
+       wl=wordlength(word);
+       msk=mask(wl);
+       shft=shift(wl);
+
+    if(i2c.state==I2C_IDLE && i2c.device==0)
+    {
+       i2c_autoend(I2Cx,1);
+       i2c_set_nbytes(I2Cx,1+wl);
+       i2c_write_addr(I2Cx,_24AAXX,0);
+       i2c.device=_24AAXX;
+       i2c.rx_idx=0;
+       i2c.tx_idx=1+wl;
+       i2c.buf_cnt=0;
+       i2c.tx_buf[0]=((uint8_t)(addr & 0xff));
+       for(uint8_t i=0;i<wl;i++)
+       {
+               i2c.tx_buf[1+i]=((uint8_t)((data & msk)>>shft));
+               msk=msk>>8;
+               shft-=8;
+       }
+       I2Cx->CR1 |= I2C_CR1_TXIE | I2C_CR1_TCIE;
+       i2c_start(I2Cx);
+
+       cycle=(uint16_t)(SystemCoreClock/(100000/i2c.tx_idx));
+
+       while(cycle--)
+       {
+               asm("NOP");
+       }
+       (void)I2Cx->ICR;
+
+    }
+
+    if(i2c.state==I2C_SENDING_DATA && i2c.device==_24AAXX)
+    {
+               i2c.state=0;
+               i2c.device=0;
+               I2Cx->ICR=0;
+
+    }
+}
+
+uint32_t _24aa02_read(I2C_TypeDef * I2Cx, uint8_t addr, uint8_t word) {
+
+       uint32_t tmp=0;
+       uint16_t cycle;
+       uint8_t shft;
+       uint8_t wl;
+
+       wl=wordlength(word);
+       shft=shift(wl);
+
+    if(i2c.state==I2C_IDLE && i2c.device==0)
+    {
+
+       i2c_autoend(I2Cx,0);
+       i2c_set_nbytes(I2Cx,1);
+       i2c_write_addr(I2Cx,_24AAXX,0);
+       i2c.device=_24AAXX;
+       i2c.rx_idx=0;
+       i2c.tx_idx=1;
+       i2c.buf_cnt=0;
+       i2c.tx_buf[0]=addr & 0xff;
+       I2Cx->CR1 |= I2C_CR1_TXIE | I2C_CR1_TCIE;
+       i2c_start(I2Cx);
+    }
+
+       cycle=(uint16_t)(SystemCoreClock/(100000/i2c.tx_idx));
+
+       while(cycle--)
+       {
+               asm("NOP");
+       }
+       (void)I2Cx->ICR;
+
+
+       if(i2c.state==I2C_SENDING_DATA && i2c.device==_24AAXX)
+       {
+               i2c.state=0;
+               I2Cx->ICR=0;
+
+               i2c_autoend(I2Cx,0);
+               i2c_set_nbytes(I2Cx,wl);
+               i2c_write_addr(I2Cx,_24AAXX,READ);
+               i2c.rx_idx=wl;
+               i2c.tx_idx=0;
+               i2c.buf_cnt=0;
+               I2Cx->CR1 |= I2C_CR1_RXIE;
+               i2c_start(I2Cx);
+
+               cycle=(uint16_t)(SystemCoreClock/(100000/i2c.rx_idx));
+
+               while(cycle--)
+               {
+                       asm("NOP");
+               }
+               (void)I2Cx->ICR;
+
+
+       }
+    if(i2c.state==I2C_RECEIVING_DATA && i2c.device==_24AAXX)
+    {
+       for(uint8_t i=0;i<wl;i++)
+       {
+               tmp+=i2c.rx_buf[i]<<shft;
+               shft-=8;
+       }
+               i2c.state=0;
+               i2c.device=0;
+    }
+
+       return tmp;
+}
+
+
+/* suitable for all EEPROMs 24AA32 to 23AA512 */
+
+void _24aa32_write(I2C_TypeDef * I2Cx, uint16_t addr, uint32_t data, uint8_t word) {                                                   // attention: internal write cycle is 6ms, otherwise NACK is sent
+
+       uint32_t msk;
+       uint16_t cycle;
+       uint8_t shft;
+       uint8_t wl;
+
+       wl=wordlength(word);
+       msk=mask(wl);
+       shft=shift(wl);
+
+    if(i2c.state==I2C_IDLE && i2c.device==0)
+    {
+       i2c_autoend(I2Cx,1);
+       i2c_set_nbytes(I2Cx,2+wl);
+       i2c_write_addr(I2Cx,_24AAXX,0);
+       i2c.device=_24AAXX;
+       i2c.rx_idx=0;
+       i2c.tx_idx=2+wl;
+       i2c.buf_cnt=0;
+       i2c.tx_buf[0]=((uint8_t)((addr & 0xff00)>>8));
+       i2c.tx_buf[1]=((uint8_t)(addr & 0xff));
+       for(uint8_t i=0;i<wl;i++)
+       {
+               i2c.tx_buf[2+i]=((uint8_t)((data & msk)>>shft));
+               msk=msk>>8;
+               shft-=8;
+       }
+       I2Cx->CR1 |= I2C_CR1_TXIE | I2C_CR1_TCIE;
+       i2c_start(I2Cx);
+
+       cycle=(uint16_t)(SystemCoreClock/(100000/i2c.tx_idx));
+
+       while(cycle--)
+       {
+               asm("NOP");
+       }
+       (void)I2Cx->ICR;
+
+    }
+
+    if(i2c.state==I2C_SENDING_DATA && i2c.device==_24AAXX)
+    {
+               i2c.state=0;
+               i2c.device=0;
+               I2Cx->ICR=0;
+
+    }
+}
+
+uint32_t _24aa32_read(I2C_TypeDef * I2Cx, uint16_t addr, uint8_t word) {
+
+       uint32_t tmp=0;
+       uint16_t cycle;
+       uint8_t shft;
+       uint8_t wl;
+
+       wl=wordlength(word);
+       shft=shift(wl);
+
+    if(i2c.state==I2C_IDLE && i2c.device==0)
+    {
+
+       i2c_autoend(I2Cx,0);
+       i2c_set_nbytes(I2Cx,2);
+       i2c_write_addr(I2Cx,_24AAXX,0);
+       i2c.device=_24AAXX;
+       i2c.rx_idx=0;
+       i2c.tx_idx=2;
+       i2c.buf_cnt=0;
+       i2c.tx_buf[0]=(addr & 0xff00)>>8;
+       i2c.tx_buf[1]=addr & 0xff;
+       I2Cx->CR1 |= I2C_CR1_TXIE | I2C_CR1_TCIE;
+       i2c_start(I2Cx);
+    }
+
+       cycle=(uint16_t)(SystemCoreClock/(100000/i2c.tx_idx));
+
+       while(cycle--)
+       {
+               asm("NOP");
+       }
+       (void)I2Cx->ICR;
+
+
+       if(i2c.state==I2C_SENDING_DATA && i2c.device==_24AAXX)
+       {
+               i2c.state=0;
+               I2Cx->ICR=0;
+
+               i2c_autoend(I2Cx,0);
+               i2c_set_nbytes(I2Cx,wl);
+               i2c_write_addr(I2Cx,_24AAXX,READ);
+               i2c.rx_idx=wl;
+               i2c.tx_idx=0;
+               i2c.buf_cnt=0;
+               I2Cx->CR1 |= I2C_CR1_RXIE;
+               i2c_start(I2Cx);
+
+               cycle=(uint16_t)(SystemCoreClock/(100000/i2c.rx_idx));
+
+               while(cycle--)
+               {
+                       asm("NOP");
+               }
+               (void)I2Cx->ICR;
+
+
+       }
+    if(i2c.state==I2C_RECEIVING_DATA && i2c.device==_24AAXX)
+    {
+       for(uint8_t i=0;i<wl;i++)
+       {
+               tmp+=i2c.rx_buf[i]<<shft;
+               shft-=8;
+       }
+               i2c.state=0;
+               i2c.device=0;
+    }
+
+       return tmp;
+}
diff --git a/src/BlinkLed.c b/src/BlinkLed.c

new file mode 100644 (file)

index 0000000..3df0739
--- /dev/null
+++ b/src/BlinkLed.c
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the ??OS++ distribution.
+ *   (https://github.com/micro-os-plus)
+ * Copyright (c) 2014 Liviu Ionescu.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "BlinkLed.h"
+
+// ----------------------------------------------------------------------------
+
+void
+blink_led_init()
+{
+  // Enable GPIO Peripheral clock
+  RCC_AHBPeriphClockCmd(BLINK_RCC_MASKx(BLINK_PORT_NUMBER), ENABLE);
+
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+  // Configure pin in output push/pull mode
+  GPIO_InitStructure.GPIO_Pin = BLINK_PIN_MASK(BLINK_PIN_NUMBER);
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(BLINK_GPIOx(BLINK_PORT_NUMBER), &GPIO_InitStructure);
+
+  // Start with led turned off
+  blink_led_off();
+}
+
+// ----------------------------------------------------------------------------
diff --git a/src/_write.c b/src/_write.c

new file mode 100644 (file)

index 0000000..ba31407
--- /dev/null
+++ b/src/_write.c
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the ??OS++ distribution.
+ *   (https://github.com/micro-os-plus)
+ * Copyright (c) 2014 Liviu Ionescu.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+// Do not include on semihosting and when freestanding
+#if !defined(OS_USE_SEMIHOSTING) && !(__STDC_HOSTED__ == 0)
+
+// ----------------------------------------------------------------------------
+
+#include <errno.h>
+#include "diag/Trace.h"
+
+// ----------------------------------------------------------------------------
+
+// When using retargetted configurations, the standard write() system call,
+// after a long way inside newlib, finally calls this implementation function.
+
+// Based on the file descriptor, it can send arrays of characters to
+// different physical devices.
+
+// Currently only the output and error file descriptors are tested,
+// and the characters are forwarded to the trace device, mainly
+// for demonstration purposes. Adjust it for your specific needs.
+
+// For freestanding applications this file is not used and can be safely
+// ignored.
+
+ssize_t
+_write (int fd, const char* buf, size_t nbyte);
+
+ssize_t
+_write (int fd __attribute__((unused)), const char* buf __attribute__((unused)),
+       size_t nbyte __attribute__((unused)))
+{
+#if defined(TRACE)
+  // STDOUT and STDERR are routed to the trace device
+  if (fd == 1 || fd == 2)
+    {
+      return trace_write (buf, nbyte);
+    }
+#endif // TRACE
+
+  errno = ENOSYS;
+  return -1;
+}
+
+// ----------------------------------------------------------------------------
+
+#endif // !defined(OS_USE_SEMIHOSTING) && !(__STDC_HOSTED__ == 0)
diff --git a/src/delay.c b/src/delay.c

new file mode 100644 (file)

index 0000000..7158b6f
--- /dev/null
+++ b/src/delay.c
@@ -0,0 +1,93 @@
+
+#include "delay.h"
+
+void
+timer_tick (void);
+
+volatile timer_ticks_t timer_delayCount;
+volatile uint32_t ticks;
+volatile uint32_t us_ticks;
+
+void
+delay_init (void)
+{
+  // Use SysTick as reference for the delay loops.
+  SysTick_Config (SystemCoreClock / TIMER_FREQUENCY_HZ);
+}
+
+void
+timer_sleep (timer_ticks_t ticks)
+{
+  timer_delayCount = ticks;
+
+  // Busy wait until the SysTick decrements the counter to zero.
+  while (timer_delayCount != 0u)
+    ;
+}
+
+void
+timer_tick (void)
+{
+  // Decrement to zero the counter used by the delay routine.
+  if (timer_delayCount != 0u)
+    {
+      --timer_delayCount;
+    }
+}
+
+inline uint32_t millis (void)
+{
+   return ticks;
+}
+
+uint32_t micros(void)
+{
+
+    us_ticks = ticks*1000 + 1000 - SysTick->VAL/(SystemCoreClock/1000000);
+
+    // = Millis*1000+(SystemCoreClock/1000-SysTick->VAL)/72;
+return us_ticks;
+
+}
+
+void delay_ms (uint32_t t)
+{
+       //t*=1000;
+  uint32_t start, end;
+  start = millis();
+  end = start + t;
+  if (start < end) {
+       while ((millis() >= start) && (millis() < end)) {
+         // do nothing
+       }
+  } else {
+    while ((millis() >= start) || (millis() < end)) {
+      // do nothing
+    };
+  }
+}
+
+
+/*
+void delay_ms(timer_ticks_t ticks)
+{
+       timer_delayCount = ticks;
+
+       while (timer_delayCount != 0);
+}
+*/
+/*
+void delay_us(timer_ticks_t ticks)
+{
+       timer_delayCount = ticks;
+
+       while (timer_delayCount != 0);
+}
+*/
+// ----- SysTick_Handler() ----------------------------------------------------
+
+extern void SysTick_Handler (void)
+{
+  timer_tick ();
+  ticks++;
+}
diff --git a/src/font_Arial.c b/src/font_Arial.c

new file mode 100644 (file)

index 0000000..3b4eac5
--- /dev/null
+++ b/src/font_Arial.c
@@ -0,0 +1,16903 @@
+#include "font_Arial.h"
+
+static const unsigned char Arial_8_data[] = {
+0x00,0x00,0x18,0x03,0x00,0x16,0x44,0x06,0x62,0xA4,
+0xD0,0x0B,0x00,0x34,0x15,0xF8,0x53,0xF1,0x40,0x0B,
+0x27,0xB1,0xCA,0xA8,0x74,0x15,0x53,0x84,0x13,0x00,
+0x51,0x89,0x12,0x83,0x40,0x16,0x81,0x48,0x8C,0x0D,
+0x00,0x38,0xC8,0x48,0x61,0x44,0x68,0x8E,0x80,0x02,
+0x62,0x94,0xC0,0x07,0x47,0x20,0x96,0x42,0x10,0x07,
+0x47,0x22,0x16,0x12,0x40,0x06,0x82,0x21,0x39,0x28,
+0x0A,0xA0,0xB4,0x11,0xF8,0x20,0x02,0x6F,0x1C,0xC0,
+0x06,0x21,0x23,0x80,0x02,0x28,0x1A,0x07,0x00,0x1C,
+0x1A,0x51,0x00,0x0B,0x00,0x31,0xD9,0x13,0x80,0x07,
+0x00,0x30,0x9A,0xD9,0x0B,0x00,0x31,0xC8,0xC0,0x42,
+0x10,0x87,0xC0,0x0B,0x00,0x31,0xC8,0x82,0x34,0x05,
+0x13,0x80,0x0B,0x00,0x30,0x43,0x42,0x92,0x7E,0x04,
+0x0B,0x00,0x31,0xE4,0x20,0xF4,0x05,0x13,0x80,0x0B,
+0x00,0x31,0xC8,0xA0,0xF4,0xC4,0xE0,0x0B,0x00,0x33,
+0xF0,0x28,0x24,0xA0,0x0B,0x00,0x31,0xD1,0x13,0xA6,
+0x27,0x00,0x0B,0x00,0x31,0xD3,0x13,0xC1,0x44,0xE0,
+0x02,0xC0,0x1B,0x44,0x03,0x07,0x1B,0x49,0x80,0x0A,
+0xA0,0xB0,0x27,0x20,0x70,0x20,0x0A,0x61,0x33,0xE0,
+0x3E,0x0A,0xA0,0xB2,0x07,0x02,0x72,0x00,0x0B,0x00,
+0x31,0xC8,0x82,0x14,0x10,0x01,0x00,0x15,0x47,0x58,
+0x7C,0x30,0x44,0xD5,0x26,0xC5,0x12,0xA6,0x93,0x61,
+0x01,0x1F,0xC0,0x0F,0x00,0x40,0x44,0x94,0x22,0x3E,
+0x88,0x20,0x0D,0x00,0x3B,0xE8,0x85,0xFC,0xC2,0xF8,
+0x0D,0x00,0x38,0xE2,0x35,0x01,0x11,0xC0,0x0D,0x00,
+0x3B,0xC4,0x55,0x0A,0x27,0x80,0x0B,0x00,0x33,0xF1,
+0x07,0xE6,0x0F,0x80,0x0B,0x00,0x33,0xF1,0x07,0xAA,
+0x00,0x0F,0x00,0x40,0xE1,0x12,0x0A,0x02,0x3A,0x09,
+0x10,0xE0,0x0D,0x00,0x3C,0xC2,0xFE,0xA1,0x03,0x00,
+0x16,0xD0,0x09,0x00,0x2D,0x8C,0x49,0x80,0x0D,0x00,
+0x3A,0x14,0x49,0x16,0x34,0x88,0x90,0x80,0x0B,0x00,
+0x36,0xC1,0xF0,0x0F,0x00,0x42,0x0C,0x63,0x9A,0xB1,
+0x24,0x0D,0x00,0x3A,0x16,0x31,0x4C,0x4A,0x8D,0x08,
+0x0F,0x00,0x40,0xE1,0x15,0x41,0x22,0x1C,0x0B,0x00,
+0x33,0xD3,0x17,0xA6,0x00,0x0F,0x00,0x40,0xE1,0x14,
+0xC1,0x4D,0x22,0x1F,0x0D,0x00,0x3B,0xE8,0x85,0xF2,
+0x48,0x89,0x08,0x0D,0x00,0x39,0xE4,0x28,0x0C,0x06,
+0x02,0x84,0xF0,0x0B,0x00,0x33,0xFA,0x40,0x0D,0x00,
+0x3E,0xC2,0x78,0x0F,0x00,0x44,0x41,0x84,0x50,0x52,
+0x04,0x00,0x17,0x18,0x52,0x10,0xA2,0x8C,0x25,0x28,
+0x51,0x50,0x41,0x00,0x0D,0x00,0x3A,0x18,0x4A,0x0C,
+0x84,0x90,0x80,0x0F,0x00,0x42,0x0C,0x22,0x14,0xA1,
+0x00,0x0D,0x00,0x39,0xF0,0x50,0x24,0x10,0x41,0xF8,
+0x05,0x47,0x1B,0xD9,0x30,0x07,0x00,0x1C,0x4A,0x50,
+0x40,0x05,0x47,0x1B,0xD4,0xB0,0x0A,0x82,0x28,0x90,
+0xA4,0x40,0x0C,0x27,0x33,0xF0,0x04,0x43,0x22,0x20,
+0x0A,0xC0,0x31,0xC8,0x9E,0x8A,0x6E,0x80,0x0B,0x00,
+0x34,0x41,0x66,0x62,0x2C,0xAC,0x0A,0xC0,0x31,0xC8,
+0xC4,0x11,0x38,0x0B,0x00,0x34,0x04,0xD4,0xE2,0x29,
+0x9A,0x0A,0xC0,0x31,0xC8,0xBE,0x82,0x27,0x00,0x07,
+0x00,0x20,0x93,0xDA,0x0B,0x07,0x31,0xA9,0xC4,0x53,
+0x34,0x17,0x80,0x0B,0x00,0x34,0x41,0x66,0x6A,0x20,
+0x03,0x00,0x12,0x64,0x05,0x5F,0x11,0x1A,0xA0,0x09,
+0x00,0x2C,0x42,0x54,0xC7,0x29,0x20,0x03,0x00,0x16,
+0xD0,0x0E,0xC0,0x42,0xF3,0x4D,0x49,0x0A,0xC0,0x33,
+0xD7,0x10,0x0A,0xC0,0x31,0xD5,0x13,0x80,0x0B,0x07,
+0x32,0xCC,0xC4,0x59,0x5A,0x20,0x0B,0x07,0x31,0xA9,
+0xC4,0x53,0x36,0x02,0x06,0xC0,0x22,0xB5,0x40,0x0A,
+0xC0,0x31,0xC8,0x98,0x12,0x27,0x00,0x07,0x18,0x1C,
+0x27,0xA4,0x60,0x0A,0xC0,0x35,0x45,0x33,0x40,0x0A,
+0xC0,0x34,0x46,0x15,0x04,0x12,0xC0,0x52,0x22,0x94,
+0xC2,0xAA,0x08,0x80,0x0A,0xC0,0x32,0x25,0x41,0x0A,
+0x44,0x0B,0x07,0x34,0x46,0x15,0x24,0x20,0x0A,0xC0,
+0x33,0xE1,0x41,0x08,0x7C,0x07,0x47,0x20,0xCA,0x4A,
+0x42,0x03,0x47,0x16,0xE6,0x07,0x4F,0x22,0x4A,0x1A,
+0x48,0x0A,0x42,0x33,0xAB,0x00,};
+/* font data size: 656 bytes */
+
+static const unsigned char Arial_8_index[] = {
+0x00,0x00,0x30,0x1C,
+0x0B,0x04,0xC1,0xC0,0x9C,0x31,0x0D,0x43,0xB1,0x04,
+0x46,0x13,0x05,0x01,0x50,0x57,0x17,0x46,0x31,0xA0,
+0x71,0x1E,0x88,0x22,0x2C,0x93,0x26,0x8A,0x22,0xA8,
+0xAE,0x2C,0xCB,0xA2,0xFC,0xC6,0x33,0xCD,0xF3,0xA0,
+0xF0,0x3E,0x10,0x04,0x21,0x0F,0x46,0x92,0x04,0x91,
+0x2A,0x4D,0x13,0x95,0x05,0x4A,0x54,0x95,0x95,0x89,
+0x6B,0x5D,0x57,0xA5,0xFD,0x88,0x65,0x19,0xD6,0x95,
+0xAE,0x6C,0xDB,0x96,0xF9,0xC4,0x72,0x1C,0xC7,0x51,
+0xDC,0x78,0xDE,0xB7,0xCD,0xF8,0x80,0x60,0x88,0x32,
+0x11,0x86,0x61,0xD8,0x8E,0x28,0x8B,0xA3,0x68,0xFA,
+0x43,0x92,0xE5,0x19,0x5E,0x5D,0x99,0xA6,0xD9,0xD2,
+0x7B,0xA0,0x68,0x5A,0x2C,
+};
+/* font index size: 119 bytes */
+
+const ILI9341_t3_font_t Arial_8 = {
+       Arial_8_index,
+       0,
+       Arial_8_data,
+       1,
+       0,
+       32,
+       126,
+       0,
+       0,
+       10,
+       4,
+       4,
+       2,
+       4,
+       4,
+       11,
+       8
+};
+
+
+
+static const unsigned char Arial_9_data[] = {
+0x00,0x00,0x08,0x03,0x44,0x07,0xB4,0x40,0x06,0x64,
+0xEB,0x34,0x11,0x40,0x0F,0x02,0x42,0x27,0xFC,0x12,
+0x3F,0xE5,0x20,0x0B,0x67,0xEE,0x72,0xB1,0x47,0x07,
+0x16,0x2A,0x70,0x80,0x15,0x44,0x18,0x61,0x22,0x48,
+0x4A,0x06,0x40,0x13,0x02,0x98,0x12,0x44,0x30,0x11,
+0x44,0x12,0x30,0x94,0x81,0x81,0x81,0x24,0x8A,0x46,
+0x1C,0xC0,0x02,0x64,0xE5,0x30,0x07,0xA7,0xA8,0x30,
+0xB6,0x42,0x10,0x07,0xA3,0xA8,0x90,0xB4,0xC2,0x40,
+0x0A,0x80,0xCA,0x23,0xE2,0x14,0x0E,0xE4,0x31,0x22,
+0x1F,0xE4,0x40,0x02,0x6B,0xC9,0x30,0x06,0x20,0x68,
+0xE0,0x02,0x24,0x08,0x80,0x09,0x40,0x09,0x03,0x25,
+0x29,0x10,0x0D,0x40,0x0E,0x7B,0x61,0x42,0x78,0x07,
+0x44,0x0E,0x26,0xBA,0x40,0x0D,0x40,0x0E,0x79,0x0C,
+0x82,0x08,0x20,0x82,0x0F,0xC0,0x0D,0x40,0x0E,0x79,
+0x0C,0x02,0x3A,0x41,0x42,0x78,0x0D,0x40,0x0E,0x0A,
+0x06,0x82,0xA1,0x27,0xF0,0x10,0x0D,0x40,0x0E,0x7E,
+0x10,0x40,0xF9,0x0C,0x02,0x84,0xF0,0x0D,0x40,0x0E,
+0x79,0x0C,0x40,0xB9,0x8C,0xC2,0x78,0x0D,0x40,0x0E,
+0xFE,0x02,0x81,0x20,0x89,0x40,0x0D,0x40,0x0E,0x7A,
+0x61,0x3D,0x50,0x9E,0x0D,0x40,0x0E,0x7A,0x61,0x46,
+0x76,0x01,0x44,0x70,0x02,0xE4,0x08,0xD9,0x03,0x27,
+0xC8,0xDA,0x60,0x0C,0xE4,0x30,0x04,0x31,0x84,0x06,
+0x03,0x01,0x0E,0x80,0x70,0xFF,0x00,0x1F,0xC0,0x0C,
+0xE4,0x30,0x80,0xC0,0x60,0x21,0x8C,0x20,0x0B,0x44,
+0x0E,0x74,0x44,0x10,0x84,0x84,0x00,0x40,0x19,0xA3,
+0xBA,0x0F,0x81,0x82,0x10,0x08,0x9D,0x29,0x19,0x50,
+0x4A,0x84,0x54,0x24,0xA3,0x24,0xEE,0x10,0x04,0x40,
+0xC1,0xF8,0x13,0x40,0x12,0x08,0x48,0xA2,0x08,0x87,
+0xF1,0x05,0x10,0x10,0x0F,0x44,0x12,0xFD,0x30,0x5F,
+0xAA,0x0B,0xF0,0x0F,0x44,0x12,0x38,0x44,0x83,0x50,
+0x10,0x48,0x87,0x00,0x0F,0x44,0x12,0xF8,0x85,0x90,
+0x50,0x9F,0x00,0x0F,0x44,0x12,0xFF,0x30,0x1F,0xEA,
+0x03,0xF8,0x0D,0x44,0x10,0xFE,0x60,0x7D,0x70,0x00,
+0x11,0x44,0x14,0x3C,0x21,0x20,0x62,0x01,0x1F,0x10,
+0x24,0x21,0xE0,0x0F,0x44,0x13,0x50,0x5F,0xEE,0x08,
+0x03,0x44,0x07,0xB9,0x80,0x0B,0x40,0x0D,0xA1,0x88,
+0x9C,0x11,0x44,0x12,0x81,0x41,0x21,0x11,0x09,0x05,
+0x83,0x21,0x08,0x82,0x40,0x80,0x0D,0x44,0x0F,0xB0,
+0x44,0x0F,0xC0,0x13,0x44,0x16,0x80,0xC6,0x0E,0x28,
+0xB3,0x29,0x88,0x88,0x0F,0x44,0x12,0x82,0xC3,0x14,
+0x62,0x4C,0x45,0x43,0x41,0x11,0x44,0x14,0x3C,0x21,
+0x64,0x09,0x08,0x78,0x0F,0x44,0x12,0xFD,0x50,0x5F,
+0xAA,0x00,0x11,0x47,0xF4,0x3C,0x21,0x5C,0x0A,0x34,
+0x84,0x3D,0x0F,0x44,0x12,0xFD,0x50,0x5F,0x91,0x22,
+0x12,0x08,0x0F,0x44,0x12,0x7D,0x10,0x50,0x0E,0x01,
+0x80,0x62,0x09,0xF0,0x0F,0x40,0x0E,0xFF,0xA2,0x20,
+0x40,0x0F,0x44,0x13,0xB0,0x50,0x48,0x87,0x00,0x13,
+0x40,0x13,0x10,0x18,0x41,0x41,0x12,0x05,0x10,0x10,
+0x1B,0x40,0x1A,0x82,0x0A,0x14,0x32,0x8A,0x29,0x28,
+0xA4,0x08,0x20,0x0F,0x40,0x0E,0x83,0x08,0x85,0x20,
+0x40,0xA4,0x22,0x41,0x0F,0x44,0x12,0x83,0x08,0xA0,
+0xA5,0x88,0x0F,0x40,0x0E,0x7E,0x05,0x01,0x20,0x44,
+0x10,0x20,0x7F,0x05,0xA7,0xA8,0xF6,0xA9,0x80,0x09,
+0x40,0x09,0x11,0x29,0x25,0x02,0x05,0xA7,0xA8,0xF5,
+0xA5,0x80,0x0A,0xA0,0x8A,0x24,0xA9,0x10,0x0E,0x23,
+0xAE,0xFE,0x04,0x45,0x08,0x88,0x0A,0xE4,0x0E,0x72,
+0x20,0x9E,0x8A,0x66,0x80,0x0B,0x44,0x0F,0x30,0x59,
+0x9A,0x8B,0xC0,0x0A,0xE4,0x0E,0x72,0x33,0x04,0x4E,
+0x0B,0x44,0x0F,0x21,0x35,0x39,0x8A,0x66,0x80,0x0A,
+0xE4,0x0E,0x74,0x45,0xF4,0x11,0x38,0x09,0x40,0x06,
+0x38,0x47,0x62,0x00,0x0B,0x47,0xAE,0x6A,0x73,0x14,
+0xCD,0x05,0x13,0x80,0x0B,0x44,0x0F,0x30,0x59,0x9B,
+0x88,0x03,0x44,0x06,0xC3,0x60,0x07,0xBF,0xA6,0x30,
+0x34,0xC1,0x60,0x0B,0x44,0x0F,0x30,0x45,0x25,0x1C,
+0x89,0x22,0x03,0x44,0x07,0xB9,0x80,0x12,0xE4,0x16,
+0xB3,0x33,0x37,0x11,0x0A,0xE4,0x0E,0xB3,0x37,0x10,
+0x0A,0xE4,0x0E,0x75,0xC4,0xE0,0x0B,0x47,0xAE,0xB3,
+0x33,0x16,0x56,0x98,0x00,0x0B,0x47,0xAE,0x6A,0x73,
+0x14,0xCD,0x90,0x80,0x06,0xE4,0x08,0xAD,0x70,0x0A,
+0xE4,0x0E,0x72,0x28,0x1C,0x0A,0x27,0x00,0x07,0x20,
+0x09,0x09,0xED,0x18,0x0A,0xE4,0x0F,0x91,0x3C,0x0A,
+0xE0,0x0B,0x11,0x95,0x41,0x00,0x12,0xE0,0x13,0x11,
+0x19,0x55,0x41,0x10,0x0A,0xE4,0x0E,0x8C,0x28,0x48,
+0x52,0x20,0x0B,0x47,0xAF,0x11,0x95,0x51,0x18,0x0A,
+0xE4,0x0E,0xFC,0x08,0x48,0x43,0xE0,0x07,0xA3,0xA8,
+0x36,0x92,0xD0,0x80,0x03,0x87,0xC7,0xBB,0x80,0x07,
+0xA7,0xA8,0x96,0x86,0xD2,0x00,0x0E,0x40,0x90,0x72,
+0x9E,};
+/* font data size: 771 bytes */
+
+static const unsigned char Arial_9_index[] = {
+0x00,0x00,0x30,0x20,0x0C,0x05,0xC2,0x20,0xC4,
+0x3E,0x10,0x84,0x91,0x40,0x56,0x17,0x46,0x11,0x94,
+0x69,0x1C,0x07,0x71,0xF4,0x88,0x24,0x89,0xC2,0x9C,
+0xB1,0x2E,0x8C,0x23,0x30,0xD0,0x35,0x4D,0xE3,0x94,
+0xEE,0x3E,0x11,0x04,0x71,0x25,0x4C,0x13,0x95,0x09,
+0x4A,0x55,0xD5,0xE5,0x8D,0x69,0x5E,0x17,0xF6,0x29,
+0x95,0x67,0x9A,0x66,0xC1,0xBA,0x71,0x9C,0xD7,0x55,
+0xE0,0x7B,0x5F,0x88,0x02,0x0B,0x84,0x61,0x88,0x7A,
+0x24,0x8A,0x22,0xC8,0xD6,0x3D,0x91,0x24,0xD9,0x56,
+0x5C,0x99,0xA6,0xD9,0xCA,0x79,0xA0,0xA8,0x7A,0x3A,
+0x94,0xA6,0xAA,0x3A,0xB2,0xB1,0xAE,0xAC,0x0B,0x16,
+0xCC,0xB5,0x2D,0xCB,0x8E,0xEB,0xBC,0xAF,0x7B,0xF8,
+};
+/* font index size: 119 bytes */
+
+const ILI9341_t3_font_t Arial_9 = {
+       Arial_9_index,
+       0,
+       Arial_9_data,
+       1,
+       0,
+       32,
+       126,
+       0,
+       0,
+       10,
+       4,
+       4,
+       3,
+       5,
+       4,
+       13,
+       10
+};
+
+
+static const unsigned char Arial_10_data[] = {
+0x00,0x00,0x08,0x05,0x44,0x09,0x9C,0x41,0x80,0x06,
+0x84,0xCB,0x54,0x11,0x40,0x10,0x12,0x19,0x09,0x1F,
+0xF0,0x48,0xFF,0x94,0x80,0x0D,0x87,0xF0,0x20,0xF2,
+0xB8,0xA0,0xE0,0xB8,0x25,0x5B,0xE1,0x00,0x17,0x44,
+0x18,0x61,0x09,0x11,0x12,0x40,0xC8,0x01,0x38,0x16,
+0x82,0x44,0x26,0x84,0x38,0x11,0x44,0x12,0x38,0x84,
+0xC3,0x41,0xC1,0xB0,0x8A,0x43,0x33,0x8F,0x60,0x02,
+0x84,0xC7,0x50,0x07,0xA7,0xAA,0x30,0x9A,0xE3,0x42,
+0x10,0x07,0xA7,0xAA,0x90,0x8E,0xC9,0xC2,0x40,0x08,
+0x84,0xCA,0x47,0x91,0x40,0x0C,0xE4,0x31,0x26,0x3F,
+0x93,0x00,0x04,0x67,0xC8,0xCA,0x08,0x20,0x6A,0xF0,
+0x04,0x24,0x08,0xC0,0x09,0x40,0x08,0x1A,0x29,0x48,
+0x80,0x0D,0x44,0x10,0x79,0x96,0x42,0xC8,0xF0,0x07,
+0x48,0x10,0x26,0xFA,0x40,0x0F,0x40,0x10,0x3C,0x46,
+0x42,0x02,0x06,0x0C,0x18,0x30,0x40,0xFE,0x0D,0x44,
+0x10,0x79,0x92,0x30,0x43,0x81,0x81,0x42,0xCC,0xF0,
+0x0F,0x40,0x11,0x01,0x82,0x86,0x84,0x88,0x98,0x9F,
+0xE0,0x10,0x0D,0x44,0x10,0x7D,0x82,0x07,0xC8,0xE0,
+0x14,0x2C,0xCF,0x00,0x0D,0x44,0x10,0x79,0x9C,0x40,
+0xB9,0x9C,0x42,0xCC,0xF0,0x0D,0x44,0x10,0xFC,0x18,
+0x60,0x83,0x20,0x88,0x60,0x80,0x0D,0x44,0x10,0x79,
+0x9A,0x36,0x67,0x11,0xC4,0x28,0xCF,0x00,0x0D,0x44,
+0x10,0x71,0x94,0x42,0x8C,0xE8,0x10,0x68,0x8E,0x00,
+0x05,0x04,0x08,0xF0,0x60,0x05,0x47,0xC8,0xF0,0x65,
+0x00,0x0C,0xE4,0x30,0x04,0x31,0x84,0x06,0x03,0x01,
+0x0C,0x84,0x70,0xFE,0x00,0x7E,0x0C,0xE4,0x30,0x80,
+0xC0,0x60,0x21,0x8C,0x20,0x0D,0x44,0x10,0x79,0x9A,
+0x10,0x20,0x82,0x0C,0x10,0x00,0x60,0x19,0xA7,0xBC,
+0x0F,0x81,0x83,0x18,0x0C,0x9D,0x29,0x99,0x48,0x4A,
+0xC2,0x56,0x22,0x93,0x24,0xEE,0x10,0x04,0x60,0xC0,
+0xFC,0x13,0x40,0x12,0x08,0x40,0xA0,0x6C,0x11,0x04,
+0x63,0xF8,0x82,0x20,0xD8,0x10,0x11,0x44,0x12,0xFC,
+0x43,0x20,0x90,0xCF,0xE4,0x14,0x41,0xA0,0x9F,0x80,
+0x11,0x44,0x14,0x3E,0x31,0xB0,0x6A,0x01,0x82,0x63,
+0x1F,0x00,0x11,0x44,0x14,0xFC,0x41,0x64,0x0A,0x09,
+0xF8,0x11,0x44,0x12,0xFE,0x98,0x07,0xF5,0x40,0x3F,
+0xC0,0x0F,0x44,0x12,0xFF,0x30,0x1F,0xAE,0x00,0x13,
+0x44,0x16,0x3E,0x18,0x4C,0x1C,0x40,0x10,0xF4,0x05,
+0x81,0x30,0xC7,0xC0,0x11,0x44,0x15,0x50,0x2F,0xFB,
+0x81,0x05,0x44,0x09,0xBC,0xE0,0x0D,0x40,0x0F,0xA0,
+0xB1,0x26,0x78,0x11,0x44,0x12,0x83,0x43,0x23,0x13,
+0x0B,0x07,0xC3,0x31,0x08,0x86,0x41,0x80,0x0D,0x44,
+0x11,0xB0,0x44,0x0F,0xC0,0x15,0x44,0x18,0xC0,0xDC,
+0x3C,0x50,0xEB,0x2E,0x24,0xB4,0xE7,0x11,0x98,0x11,
+0x44,0x15,0x18,0x2A,0x18,0x91,0x88,0x94,0x2C,0x41,
+0x80,0x13,0x44,0x16,0x3E,0x18,0xCC,0x1D,0x40,0x58,
+0x33,0x18,0x7C,0x11,0x44,0x12,0xFE,0x41,0x44,0x1A,
+0x09,0xF9,0x50,0x00,0x13,0x47,0xF6,0x3E,0x18,0xCC,
+0x1D,0x40,0x58,0xB3,0x38,0x7F,0x13,0x44,0x14,0xFE,
+0x20,0xD1,0x02,0x41,0x9F,0xC4,0x21,0x0C,0x41,0x90,
+0x30,0x11,0x44,0x12,0x7C,0x63,0x20,0x98,0x07,0x80,
+0x70,0x0D,0x06,0xC2,0x3E,0x00,0x11,0x40,0x12,0xFF,
+0xD0,0x88,0x08,0x11,0x44,0x15,0xB0,0x2C,0x32,0x10,
+0xF0,0x13,0x40,0x12,0xC0,0x90,0x64,0x11,0x84,0x22,
+0x0C,0x81,0x60,0x50,0x1C,0x03,0x00,0x1B,0x40,0x1A,
+0xC3,0x09,0x1C,0x70,0x8A,0x23,0x24,0x85,0x16,0x82,
+0x8A,0x0A,0x18,0x10,0x40,0x13,0x40,0x12,0x41,0x88,
+0xC3,0x20,0x70,0x0C,0x07,0x01,0x60,0x88,0x61,0x30,
+0x60,0x13,0x40,0x12,0xC1,0x98,0x42,0x30,0xD8,0x1C,
+0x58,0x40,0x11,0x40,0x12,0x7F,0x01,0x81,0x80,0x80,
+0x80,0xC0,0xC0,0xC0,0x40,0x7F,0x80,0x07,0xA7,0xA8,
+0xFB,0x2A,0x38,0x09,0x40,0x09,0x11,0x29,0x44,0x10,
+0x07,0xA3,0xA8,0xFA,0x68,0xB8,0x0A,0xA4,0xAE,0x21,
+0xC5,0x24,0x88,0x10,0x23,0xB0,0xFF,0x04,0x45,0x0A,
+0x88,0x0D,0x04,0x10,0x79,0x18,0x11,0xEC,0x62,0x37,
+0xA0,0x0D,0x44,0x11,0x10,0x2E,0x67,0x50,0xB3,0x5C,
+0x0D,0x04,0x0E,0x79,0x9D,0x40,0xCC,0xF0,0x0D,0x44,
+0x11,0x00,0x9D,0x88,0xE2,0x14,0x6C,0xCE,0x80,0x0D,
+0x04,0x10,0x79,0x9A,0x17,0xF1,0x03,0x13,0xC0,0x09,
+0x40,0x08,0x32,0x3F,0x50,0x0F,0x63,0xB0,0x3A,0x66,
+0x47,0x18,0x48,0x48,0xC7,0x40,0x48,0x8F,0x00,0x0D,
+0x44,0x11,0x10,0x2E,0x67,0x90,0x80,0x03,0x44,0x06,
+0x9B,0x40,0x07,0xBF,0xA6,0x21,0xA6,0x4B,0x80,0x0D,
+0x44,0x0F,0x10,0x22,0x48,0xA1,0xC2,0xC4,0x88,0x91,
+0x80,0x03,0x44,0x07,0xB9,0x80,0x15,0x04,0x18,0xBB,
+0x99,0x9A,0x31,0xB8,0x84,0x0D,0x04,0x10,0xB9,0x9E,
+0x42,0x0F,0x00,0x10,0x3C,0x66,0x43,0x18,0x48,0x4C,
+0xC7,0x80,0x0D,0x67,0xB0,0xB9,0x9D,0x42,0xCD,0x74,
+0xC0,0x0D,0x67,0xB0,0x75,0x9A,0x38,0x85,0x1B,0x33,
+0xB2,0x08,0x09,0x04,0x0A,0xF6,0x64,0x00,0x0B,0x04,
+0x0E,0x72,0x28,0x38,0x38,0x28,0xBC,0x09,0x40,0x29,
+0x08,0xFC,0x41,0x80,0x0D,0x04,0x11,0x70,0xC4,0x67,
+0x40,0x0F,0x00,0x0E,0xC7,0x08,0x8D,0xA0,0xA0,0xE0,
+0x40,0x15,0x00,0x14,0x8C,0x59,0x9C,0x26,0x45,0x2A,
+0x4C,0xC0,0x0F,0x00,0x0E,0x44,0x6C,0x28,0x10,0x38,
+0x28,0x6C,0xC6,0x0F,0x63,0xAE,0xC7,0x08,0x8C,0xA0,
+0xA0,0xE4,0x08,0x18,0x30,0x0F,0x00,0x0E,0x7C,0x04,
+0x08,0x10,0x30,0x60,0x40,0xFE,0x09,0xA3,0xAA,0x3A,
+0x23,0x30,0xD4,0x43,0x03,0xA7,0xA9,0xBC,0x80,0x09,
+0xA3,0xAA,0xCB,0x20,0xD9,0x30,0x0E,0x44,0x70,0xE2,
+0x9C,0x00,0x00,0x00,
+
+};
+/* font data size: 904 bytes */
+
+static const unsigned char Arial_10_index[] = {
+0x00,0x00,0x30,0x24,0x0D,0x06,0x42,0x60,0xDC,0x45,
+0x12,0x45,0x11,0x64,0x5F,0x19,0x86,0xA1,0xB8,0x72,
+0x1E,0x48,0x12,0x1C,0x94,0x28,0x0A,0xC2,0xE0,0xC3,
+0x33,0x8D,0xA3,0x98,0xEB,0x3C,0x4F,0xA4,0x01,0x09,
+0x45,0x52,0xD4,0xF1,0x4A,0x55,0x95,0xF5,0xA5,0x71,
+0x60,0x18,0x76,0x31,0x93,0x68,0x9A,0x96,0xDD,0xC3,
+0x73,0xDD,0xA7,0x99,0xF5,0x81,0x20,0xB8,0x4E,0x23,
+0x8D,0x64,0x59,0x42,0x5F,0x99,0x66,0xC9,0xCA,0x79,
+0x9F,0x68,0x1A,0x2E,0x94,0xA7,0x2A,0x7A,0xC6,0xB7,
+0xB1,0x6C,0xDB,0x4A,0xD9,0xB9,0x6E,0xAB,0xCE,0xF9,
+0xC1,0x30,0xDC,0x63,0x1E,0xC9,0xF2,0xEC,0xD7,0x3F,
+0xD2,0xB5,0x5D,0x87,0x6C,0xDD,0x37,0x9E,0x03,0x85,
+};
+/* font index size: 120 bytes */
+
+const ILI9341_t3_font_t Arial_10 = {
+        Arial_10_index,
+        0,
+        Arial_10_data,
+        1,
+        0,
+        32,
+        126,
+        0,
+        0,
+        10,
+        4,
+        4,
+        3,
+        5,
+        4,
+        14,
+        10
+};
+
+
+
+
+static const unsigned char Arial_11_data[] = {
+0x00,0x00,0x08,0x03,0x68,0x0B,0xB8,0x88,0x06,0x84,
+0xEB,0x54,0x11,0x60,0x11,0x22,0x4F,0xF9,0x24,0x7F,
+0xCA,0x40,0x0F,0xA3,0xF0,0x10,0x3C,0x56,0x92,0x90,
+0x50,0x38,0x14,0x12,0x92,0x54,0x38,0x10,0x17,0x64,
+0x1A,0x60,0x91,0x22,0x22,0x48,0x19,0x34,0x04,0x98,
+0x11,0x22,0x0C,0x13,0x64,0x14,0x38,0x4A,0x20,0x50,
+0x38,0x22,0x24,0x86,0x21,0x47,0x98,0x02,0x84,0xE7,
+0x50,0x07,0xC7,0xAA,0x30,0xB6,0x34,0x21,0x07,0xC7,
+0xAA,0x90,0xB4,0xCA,0x40,0x0A,0xA0,0xCC,0x23,0xE2,
+0x42,0x80,0x0E,0xE4,0x53,0x22,0x1F,0xE4,0x40,0x02,
+0x6B,0xA9,0x30,0x08,0x20,0x6A,0xF0,0x02,0x28,0x08,
+0x80,0x09,0x60,0x09,0x03,0x25,0x49,0x10,0x0D,0x64,
+0x10,0x7B,0x61,0x88,0x4F,0x00,0x07,0x68,0x10,0x26,
+0xBA,0x44,0x0D,0x64,0x10,0x7A,0x21,0x80,0x60,0x20,
+0x82,0x08,0x3F,0x0D,0x64,0x10,0x7A,0x21,0x80,0x47,
+0x40,0x31,0x09,0xE0,0x0F,0x60,0x10,0x04,0x0C,0x15,
+0x04,0x88,0x90,0x9F,0xE4,0x10,0x0D,0x64,0x10,0x7E,
+0x10,0x40,0xF9,0x0C,0x02,0x85,0x11,0xE0,0x0D,0x64,
+0x10,0x7A,0x21,0x40,0xB9,0x8D,0x42,0x78,0x0D,0x64,
+0x10,0xFC,0x0C,0x05,0x22,0x51,0x00,0x0D,0x64,0x10,
+0x7A,0xA1,0x3D,0x50,0x9E,0x0D,0x64,0x10,0x7A,0xA1,
+0x46,0x74,0x0C,0x42,0x78,0x03,0x04,0x08,0xE1,0x03,
+0x47,0xA8,0xE2,0x60,0x0E,0xE4,0x52,0x02,0x1C,0x60,
+0x80,0x60,0x1C,0x02,0x0E,0xA4,0x72,0xFF,0x20,0x1F,
+0xC0,0x0E,0xE4,0x52,0x80,0x70,0x0C,0x02,0x0C,0x70,
+0x80,0x0D,0x64,0x10,0x7A,0x21,0x02,0x08,0x24,0x90,
+0x00,0x40,0x1D,0xC3,0xBE,0x07,0xC0,0x30,0x60,0x80,
+0x22,0x1D,0x64,0xC6,0x51,0x04,0xC4,0x82,0x29,0x04,
+0x91,0x19,0x13,0xDC,0x20,0x02,0x30,0x18,0x1F,0xC0,
+0x13,0x60,0x12,0x08,0x48,0xA2,0x08,0x84,0x11,0xFC,
+0x41,0x44,0x04,0x11,0x64,0x14,0xFE,0x98,0x14,0x13,
+0xFA,0xA0,0x5F,0xC0,0x13,0x64,0x16,0x1E,0x18,0x44,
+0x0D,0xC0,0x08,0x13,0x08,0x3C,0x13,0x64,0x16,0xFE,
+0x20,0x5B,0x01,0x40,0x9F,0xC0,0x11,0x64,0x14,0xFF,
+0xA8,0x07,0xFD,0x40,0x3F,0xC0,0x0F,0x64,0x12,0xFF,
+0x50,0x1F,0xAE,0x00,0x13,0x64,0x16,0x3E,0x10,0x48,
+0x0C,0x40,0x10,0xF9,0x80,0x90,0x43,0xE0,0x11,0x64,
+0x15,0x70,0x2F,0xFB,0x81,0x03,0x64,0x07,0xBA,0x80,
+0x0D,0x60,0x0F,0xA0,0x81,0x88,0x4F,0x00,0x13,0x64,
+0x14,0x81,0x20,0x88,0x42,0x20,0x90,0x2A,0x0C,0x42,
+0x10,0x82,0x20,0x48,0x08,0x0F,0x64,0x11,0xB0,0x26,
+0x03,0xF8,0x13,0x64,0x16,0x80,0xC6,0x0E,0x68,0xB3,
+0x29,0x88,0x88,0x11,0x64,0x14,0x81,0x60,0xC5,0x0C,
+0x48,0xA2,0x62,0x15,0x06,0x81,0x15,0x64,0x18,0x1E,
+0x0C,0x31,0x02,0xB8,0x04,0x81,0x18,0x60,0xF0,0x11,
+0x64,0x14,0xFE,0xA8,0x17,0xF5,0xC0,0x00,0x15,0x67,
+0xF8,0x1E,0x0C,0x31,0x02,0xB8,0x04,0x8D,0x18,0x60,
+0xF2,0x13,0x64,0x16,0xFF,0x54,0x05,0xFE,0x42,0x22,
+0x08,0x81,0x20,0x20,0x11,0x64,0x14,0x3C,0x21,0x20,
+0x50,0x0F,0x00,0x74,0x00,0xA0,0x58,0x43,0xC0,0x13,
+0x60,0x12,0xFF,0xE8,0x42,0x42,0x00,0x11,0x64,0x15,
+0xB0,0x31,0x02,0x42,0x1E,0x00,0x13,0x60,0x13,0x10,
+0x18,0x41,0x49,0x12,0x05,0x10,0x10,0x1F,0x60,0x1E,
+0x81,0x02,0x82,0x83,0x08,0x50,0xA1,0x11,0x10,0x91,
+0x24,0x14,0x14,0x81,0x01,0x00,0x13,0x60,0x12,0x80,
+0x90,0x50,0x44,0x0A,0x01,0x80,0xA2,0x08,0x84,0x12,
+0x02,0x13,0x60,0x12,0x80,0x90,0x50,0x44,0x0A,0x30,
+0x20,0x11,0x60,0x10,0x7F,0x01,0x40,0x20,0x22,0x04,
+0x20,0x80,0x80,0xFF,0x07,0xC7,0xA8,0xFB,0x2E,0x38,
+0x09,0x60,0x09,0x11,0x29,0x45,0x02,0x07,0xC3,0xA8,
+0xFA,0x6C,0xB8,0x0A,0xC0,0xAA,0x24,0xAA,0x22,0x10,
+0x23,0xB0,0xFF,0x04,0x45,0x2A,0x88,0x0D,0x04,0x10,
+0x79,0x08,0x11,0xE4,0x50,0xA3,0x3A,0x0D,0x64,0x11,
+0x30,0x2E,0x63,0x50,0xB1,0x5C,0x0D,0x04,0x10,0x79,
+0x0D,0x40,0x84,0xF0,0x0D,0x64,0x11,0x20,0x9D,0x47,
+0x50,0xA3,0x3A,0x0D,0x04,0x10,0x7A,0x21,0x7F,0x10,
+0x21,0x3C,0x09,0x60,0x08,0x38,0x47,0xEA,0x00,0x0D,
+0x67,0xB0,0x75,0x1D,0x42,0x8C,0xE8,0x14,0x27,0x80,
+0x0D,0x64,0x11,0x30,0x2E,0x63,0x90,0x80,0x03,0x64,
+0x06,0xC3,0x68,0x07,0xDF,0xA6,0x30,0x34,0xC9,0x60,
+0x0D,0x64,0x0F,0x30,0x21,0x44,0x91,0x43,0x48,0x89,
+0x08,0x03,0x64,0x07,0xBA,0x80,0x17,0x04,0x1A,0xB9,
+0xCC,0x63,0x90,0x84,0x0D,0x04,0x10,0xB9,0x8E,0x42,
+0x0D,0x04,0x10,0x7B,0x21,0x3C,0x0D,0x67,0xB0,0xB9,
+0x8D,0x42,0xC5,0x74,0xC0,0x0D,0x67,0xB0,0x75,0x1D,
+0x42,0x8C,0xEC,0x82,0x09,0x04,0x0A,0xB6,0x64,0x00,
+0x0D,0x04,0x10,0x79,0x0A,0x03,0x01,0x80,0xA1,0x3C,
+0x09,0x40,0x29,0x08,0xFC,0x43,0x80,0x0D,0x04,0x11,
+0x90,0xA3,0x3A,0x0F,0x00,0x0F,0x10,0x61,0x14,0x14,
+0x81,0x00,0x17,0x00,0x16,0x84,0x28,0xA3,0x09,0x4A,
+0x14,0x54,0x10,0x40,0x0F,0x00,0x0E,0x82,0x44,0x29,
+0x02,0x05,0x08,0x90,0x40,0x0F,0x63,0xAF,0x10,0x61,
+0x14,0x94,0x91,0x06,0x00,0x0D,0x04,0x10,0xFC,0x14,
+0x09,0x04,0x10,0x7E,0x0B,0xC3,0xAA,0x1E,0x11,0x8B,
+0x20,0x60,0x03,0xC7,0xA7,0xBD,0x80,0x0B,0xC3,0xAA,
+0xC6,0x10,0x3B,0x23,0x00,0x10,0x40,0x92,0x71,0x47,
+0x00,};
+/* font data size: 861 bytes */
+
+static const unsigned char Arial_11_index[] = {
+0x00,0x00,0x30,0x20,0x0C,0x05,0x82,0x60,0xD4,
+0x43,0x11,0xC4,0xE1,0x54,0x5C,0x18,0xC6,0x71,0xAC,
+0x6F,0x1D,0x87,0xE2,0x10,0x8F,0x26,0x8A,0x62,0xC8,
+0xBC,0x31,0x4C,0xD3,0x5C,0xDB,0x38,0x0E,0xA3,0xC4,
+0xFB,0x41,0x92,0x24,0xBD,0x3A,0x51,0x95,0x05,0x69,
+0x62,0x5C,0x17,0x75,0xF1,0x84,0x65,0x59,0xC6,0x9D,
+0xB4,0x70,0x5C,0xA7,0x5D,0xE4,0x7C,0xDF,0xB8,0x12,
+0x0F,0x88,0xA3,0x18,0xEE,0x48,0x93,0xA5,0x59,0x6E,
+0x61,0x99,0x66,0x99,0xCE,0x7C,0xA1,0x28,0xDA,0x5A,
+0x9D,0xAA,0x2B,0x0A,0xD6,0xBC,0xB1,0xEC,0xCB,0x52,
+0xDA,0xB8,0x2E,0x9B,0xCA,0xF8,0xC0,0xB0,0x9C,0x3F,
+0x18,0xC9,0x32,0xFC,0xE7,0x42,0xD2,0xB4,0xFD,0x5C,
+};
+/* font index size: 119 bytes */
+
+const ILI9341_t3_font_t Arial_11 = {
+       Arial_11_index,
+       0,
+       Arial_11_data,
+       1,
+       0,
+       32,
+       126,
+       0,
+       0,
+       10,
+       4,
+       4,
+       3,
+       5,
+       4,
+       16,
+       11
+};
+
+/*
+static const unsigned char Arial_12_data[] = {
+0x00,0x00,0x01,0x40,0x02,0x61,0x01,0x67,0xD4,0x10,
+0x04,0x21,0x41,0xAA,0x40,0x09,0x60,0x02,0x43,0x29,
+0x11,0x3F,0xF2,0x44,0x7F,0xCC,0x88,0x44,0x00,0x08,
+0x79,0xF2,0x42,0x07,0xC6,0xB2,0x49,0x20,0xD0,0x3C,
+0x07,0x82,0x51,0x26,0xD6,0x1E,0x40,0x80,0x0D,0x61,
+0x03,0xCE,0x08,0x6C,0x61,0x11,0x04,0x4C,0x11,0x20,
+0x6D,0x38,0xE5,0xB8,0x04,0x88,0x22,0x21,0x8D,0x84,
+0x1C,0x09,0x61,0x02,0xC7,0x81,0x30,0xC4,0x33,0x07,
+0x81,0xC0,0xD8,0x62,0xD0,0xF6,0x19,0x8F,0x1E,0x40,
+0x01,0x21,0x40,0xEA,0x04,0x79,0xE9,0x82,0x23,0x13,
+0x70,0x86,0x10,0x40,0x04,0x79,0xE9,0x90,0x43,0x0A,
+0x4C,0x32,0x62,0x31,0x10,0x05,0x29,0x39,0xC4,0x5C,
+0xC3,0x92,0x08,0x39,0x1A,0xA4,0x61,0xFF,0x23,0x00,
+0x02,0x21,0xE9,0x65,0x40,0x04,0x09,0x21,0x9E,0x01,
+0x0A,0x01,0x50,0x05,0x60,0x01,0x43,0x91,0x49,0x0C,
+0x84,0x30,0x80,0x08,0x61,0x02,0x47,0x84,0x66,0x12,
+0x0A,0xA0,0xD0,0x4C,0x22,0x30,0xF0,0x04,0x62,0x02,
+0x42,0x33,0xB7,0x44,0x20,0x08,0x61,0x02,0x4F,0x8C,
+0x64,0x10,0x0C,0x04,0x06,0x06,0x06,0x06,0x06,0x06,
+0x03,0xFC,0x08,0x61,0x02,0x47,0x8C,0x64,0x14,0x03,
+0x07,0x00,0xD0,0x06,0x82,0x63,0x1F,0x00,0x09,0x60,
+0x02,0x60,0x18,0x0E,0x07,0x81,0x60,0x98,0x66,0x11,
+0x8F,0xFC,0x83,0x00,0x08,0x61,0x02,0x4F,0xD0,0x80,
+0xC0,0x7E,0x31,0xA4,0x0D,0x04,0xC6,0x3E,0x00,0x08,
+0x61,0x02,0x47,0x86,0x66,0x12,0x01,0x78,0xC6,0x61,
+0x44,0x1B,0x08,0x8C,0x3C,0x08,0x61,0x02,0x5F,0xE0,
+0x60,0x20,0x30,0x10,0x18,0x08,0x41,0x84,0x90,0x00,
+0x08,0x61,0x02,0x47,0x84,0x68,0xC2,0x23,0x0F,0x18,
+0xD3,0x06,0xC6,0x1E,0x00,0x08,0x61,0x02,0x47,0x8C,
+0x66,0x14,0xC1,0xB1,0xCF,0x60,0x24,0x13,0x18,0xF0,
+0x01,0x4A,0x01,0x5D,0x20,0x02,0x61,0xE9,0x4E,0x92,
+0xA0,0x08,0x49,0x12,0x80,0x20,0x70,0xF1,0xC1,0x80,
+0x70,0x0F,0x01,0xC0,0x20,0x08,0x29,0x1A,0x9F,0xF2,
+0x00,0xFF,0x08,0x49,0x12,0x90,0x0E,0x03,0xC0,0x38,
+0x06,0x0E,0x3C,0x38,0x10,0x00,0x08,0x61,0x02,0x47,
+0x84,0x66,0x12,0x0C,0x04,0x06,0x06,0x40,0xC0,0x40,
+0x00,0x18,0x0F,0x81,0xE4,0x40,0xFC,0x03,0x03,0x06,
+0x01,0x8C,0x76,0xC8,0x8C,0x59,0x0C,0x66,0x61,0x8A,
+0x61,0x12,0x23,0x23,0x1D,0xC1,0x00,0x08,0x80,0x18,
+0x60,0x60,0x1F,0xC0,0x0B,0x60,0x02,0xC1,0xC2,0x02,
+0x80,0x6C,0x04,0x40,0x46,0x0C,0x60,0xFE,0x18,0x31,
+0x81,0x10,0x1B,0x01,0x80,0x09,0x61,0x02,0xDF,0xC6,
+0x0A,0x30,0x6C,0x13,0xFC,0xC1,0xCE,0x05,0x83,0x7F,
+0x80,0x0B,0x61,0x03,0x03,0xE0,0x43,0x08,0x1A,0xF0,
+0x03,0x01,0x90,0x31,0xC6,0x07,0xC0,0x0A,0x61,0x03,
+0x1F,0xE3,0x06,0x8C,0x0E,0xB0,0x18,0xC0,0xD8,0x33,
+0xFC,0x09,0x61,0x02,0xDF,0xFA,0xC0,0x3F,0xF7,0x80,
+0x7F,0xC0,0x09,0x61,0x02,0x9F,0xFA,0xC0,0x3F,0xD9,
+0x80,0x0B,0x61,0x03,0x43,0xF0,0x61,0x8C,0x0D,0x80,
+0xA3,0x00,0x30,0xFC,0x60,0x13,0x01,0x18,0x70,0xFC,
+0x0A,0x61,0x03,0x2F,0x03,0x7F,0xF9,0x81,0x80,0x01,
+0x62,0x01,0x77,0x70,0x07,0x60,0x02,0x74,0x08,0x0B,
+0x09,0x09,0x98,0xF0,0x0A,0x61,0x02,0xD8,0x3B,0x0E,
+0x63,0x0C,0xC1,0xB0,0x3E,0x07,0x60,0xC6,0x23,0x0C,
+0x60,0xCC,0x0C,0x08,0x61,0x02,0x77,0x02,0xB0,0x1F,
+0xE0,0x0C,0x61,0x03,0x9C,0x06,0xE0,0x77,0x83,0xB4,
+0x3D,0xA1,0x6D,0x8B,0x64,0xDB,0x24,0xD9,0xA6,0xC7,
+0x38,0xC6,0x30,0x0A,0x61,0x03,0x18,0x1C,0x70,0x6D,
+0x0E,0x32,0x38,0xC4,0xD8,0x5C,0x60,0xEC,0x0C,0x0B,
+0x61,0x03,0x43,0xE0,0x61,0x88,0x0D,0x80,0xE3,0x00,
+0xA0,0x0B,0x00,0xB0,0x19,0x01,0x8C,0x30,0x7C,0x00,
+0x0A,0x61,0x02,0xDF,0xE3,0x06,0x60,0x4C,0x0D,0x81,
+0x30,0x67,0xF9,0x78,0x00,0x0B,0x69,0xFB,0x43,0xE0,
+0xE1,0x88,0x09,0x80,0xD8,0x06,0x20,0x0B,0x00,0xB0,
+0x19,0x0D,0x8C,0x70,0x7F,0x80,0x08,0x0B,0x61,0x03,
+0x1F,0xF2,0xB0,0x33,0x02,0x3F,0xC3,0x08,0x30,0x43,
+0x06,0x30,0x33,0x01,0x80,0x09,0x61,0x02,0xC7,0xC3,
+0x0D,0x83,0x60,0x0C,0x01,0xF0,0x1F,0x00,0xD0,0x16,
+0x04,0xC3,0x1F,0x00,0x0A,0x60,0x02,0x9F,0xFE,0x86,
+0x14,0x18,0x00,0x0A,0x61,0x03,0x37,0x03,0x8C,0x0C,
+0x81,0x98,0x60,0xF8,0x0B,0x60,0x02,0xD8,0x0C,0x80,
+0xCC,0x08,0xC1,0x84,0x10,0x63,0x02,0x30,0x32,0x03,
+0x60,0x14,0x01,0xC0,0x0C,0x00,0x10,0x60,0x04,0x18,
+0x30,0x64,0x18,0x22,0x1E,0x14,0x31,0x23,0x08,0x99,
+0x04,0xCC,0x83,0x42,0xC1,0xA1,0x40,0x70,0xE2,0x06,
+0x06,0x00,0x0B,0x60,0x02,0xCC,0x0C,0x61,0x86,0x30,
+0x36,0x01,0xE0,0x0C,0x01,0xC0,0x36,0x03,0x30,0x63,
+0x0C,0x19,0x80,0xC0,0x0B,0x60,0x02,0xD8,0x0C,0xC1,
+0x86,0x10,0x63,0x03,0x62,0x03,0x85,0x82,0x00,0x0A,
+0x60,0x02,0x8F,0xFC,0x00,0xC0,0x30,0x0C,0x40,0x60,
+0x18,0x06,0x04,0x30,0x0F,0xFC,0x03,0x79,0xE9,0x5F,
+0x76,0x67,0x05,0x60,0x01,0x50,0x62,0x10,0x64,0x92,
+0x44,0x18,0x04,0x78,0xE9,0x5F,0xA7,0x86,0xF0,0x06,
+0x39,0x2A,0x20,0xC2,0xC4,0x99,0x44,0x20,0x0A,0x08,
+0xEA,0x5F,0xF8,0x03,0x11,0x51,0x98,0xC0,0x08,0x49,
+0x02,0x47,0x8C,0x64,0x10,0x79,0xE4,0x82,0x43,0x31,
+0x8F,0x60,0x08,0x61,0x02,0x67,0x01,0xF8,0xE6,0x61,
+0x30,0xD0,0x6C,0x36,0x13,0x19,0xF8,0x07,0x49,0x02,
+0x47,0x98,0xD8,0x66,0x03,0x0B,0x18,0xF0,0x07,0x61,
+0x02,0x64,0x09,0xEB,0x1D,0xC1,0x63,0x1D,0x08,0x49,
+0x02,0x47,0x84,0x66,0x12,0x0D,0xFE,0x80,0x61,0xB1,
+0x87,0x80,0x05,0x60,0x01,0x47,0x10,0xC7,0xF5,0x86,
+0x00,0x07,0x61,0xEA,0x4F,0x58,0xEE,0x0B,0x19,0xE8,
+0x0B,0x19,0xF0,0x07,0x61,0x02,0x67,0x03,0xF3,0x1E,
+0xE1,0x02,0x61,0x01,0x1C,0x1B,0xC6,0x04,0x7F,0xE9,
+0x07,0x01,0xA7,0x26,0x27,0x00,0x07,0x61,0x02,0x67,
+0x03,0x1B,0x33,0x64,0x78,0x6C,0x66,0x62,0x63,0x02,
+0x61,0x01,0x37,0xBC,0x0C,0x49,0x03,0x97,0xBC,0xC7,
+0x3D,0xC6,0x10,0x07,0x49,0x02,0x57,0x98,0xF7,0x08,
+0x08,0x49,0x02,0x47,0x8C,0x6B,0x83,0x63,0x0F,0x00,
+0x08,0x61,0xEA,0x57,0x8E,0x66,0x13,0x0D,0x06,0xC3,
+0x61,0x31,0x9F,0x93,0x80,0x07,0x61,0xEA,0x4F,0x58,
+0xEE,0x0B,0x18,0xEC,0x81,0x05,0x49,0x01,0x97,0xDC,
+0x30,0x07,0x49,0x02,0x4F,0x18,0x90,0x1C,0x0F,0xA0,
+0x1A,0x19,0xE0,0x05,0x60,0x01,0x44,0x86,0x3D,0xAC,
+0x1C,0x07,0x49,0x02,0x77,0x0B,0x19,0xE8,0x08,0x48,
+0x02,0x58,0x24,0x33,0x10,0x88,0x4C,0x34,0x81,0xC0,
+0xC0,0x0C,0x48,0x03,0x18,0xC2,0xC6,0x32,0x39,0x1B,
+0xC8,0xD2,0xC2,0x94,0x14,0xE0,0xE7,0x02,0x18,0x08,
+0x48,0x02,0x4C,0x66,0x61,0xA0,0x70,0x30,0x1C,0x1B,
+0x18,0x98,0x60,0x08,0x60,0xEA,0x58,0x24,0x33,0x10,
+0x88,0x6C,0x34,0x0A,0x07,0x20,0x60,0x20,0x70,0x08,
+0x48,0x02,0x4F,0xE0,0x20,0x30,0x30,0x30,0x30,0x10,
+0x18,0x1F,0xE0,0x05,0x78,0xE9,0x83,0xA3,0x41,0x18,
+0x82,0x51,0x83,0x01,0x82,0xE1,0x37,0xB8,0x80,0x05,
+0x78,0xE9,0x9C,0xA2,0x0C,0x10,0x21,0x0D,0x44,0x70,
+0x08,0x11,0x2A,0x9E,0x28,0xF0,0x00,0x00,0x00,0x00,
+};
+
+static const unsigned char Arial_12_index[] = {
+0x00,0x00,0x10,0x05,0x00,0xF0,0x3A,0x0C,0x02,0x38,
+0x5A,0x0B,0xC1,0xA0,0x39,0x87,0xA1,0x04,0x21,0xC4,
+0x58,0x8F,0x13,0x22,0x9C,0x57,0x8C,0x01,0xA0,0x38,
+0x07,0x78,0xFF,0x21,0xC4,0x74,0x96,0x13,0x12,0x6E,
+0x51,0x4A,0x61,0x5A,0x2D,0x46,0x28,0xCF,0x9A,0xF3,
+0x7E,0x73,0x4E,0xC1,0xE1,0x3E,0x87,0xF5,0x01,0x20,
+0xC4,0x3E,0x89,0xD1,0xEA,0x4D,0x4C,0x49,0xC5,0x43,
+0xA9,0x95,0x58,0xAD,0x56,0x02,0xD6,0x5E,0x0C,0x19,
+0x8A,0xB2,0x66,0x58,0xCD,0x99,0xEB,0x46,0x69,0x6D,
+0x41,0xAF,0x36,0xD6,0xF0,0xE0,0x9C,0x83,0x99,0x74,
+0xAE,0xB5,0xD9,0xBB,0xC7,0x92,0xF3,0x9E,0xBB,0xDE,
+0x7D,0x0F,0xDE,0x00,0xC0,0x78,0x27,0x06,0xE1,0x14,
+0x2F,0x88,0x31,0x3E,0x2F,0xC6,0xD8,0xEF,0x1F,0x64,
+0x44,0x8E,
+};
+
+const ILI9341_t3_font_t Arial_12 = {
+        Arial_12_index,
+        0,
+        Arial_12_data,
+        1,
+        0,
+        32,
+        127,
+        0,
+        0,
+        11,
+        5,
+        5,
+        3,
+        5,
+        5,
+        18,
+        12
+};
+*/
+
+static const unsigned char Arial_12_data[] = {
+0x00,0x00,0x01,0x40,0x02,0x61,0x01,0x67,0xD4,0x10,
+0x04,0x21,0x41,0xAA,0x40,0x09,0x60,0x02,0x43,0x29,
+0x11,0x3F,0xF2,0x44,0x7F,0xCC,0x88,0x44,0x00,0x08,
+0x79,0xF2,0x42,0x07,0xC6,0xB2,0x49,0x20,0xD0,0x3C,
+0x07,0x82,0x51,0x26,0xD6,0x1E,0x40,0x80,0x0D,0x61,
+0x03,0xCE,0x08,0x6C,0x61,0x11,0x04,0x4C,0x11,0x20,
+0x6D,0x38,0xE5,0xB8,0x04,0x88,0x22,0x21,0x8D,0x84,
+0x1C,0x09,0x61,0x02,0xC7,0x81,0x30,0xC4,0x33,0x07,
+0x81,0xC0,0xD8,0x62,0xD0,0xF6,0x19,0x8F,0x1E,0x40,
+0x01,0x21,0x40,0xEA,0x04,0x79,0xE9,0x82,0x23,0x13,
+0x70,0x86,0x10,0x40,0x04,0x79,0xE9,0x90,0x43,0x0A,
+0x4C,0x32,0x62,0x31,0x10,0x05,0x29,0x39,0xC4,0x5C,
+0xC3,0x92,0x08,0x39,0x1A,0xA4,0x61,0xFF,0x23,0x00,
+0x02,0x21,0xE9,0x65,0x40,0x04,0x09,0x21,0x9E,0x01,
+0x0A,0x01,0x50,0x05,0x60,0x01,0x43,0x91,0x49,0x0C,
+0x84,0x30,0x80,0x08,0x61,0x02,0x47,0x84,0x66,0x12,
+0x0A,0xA0,0xD0,0x4C,0x22,0x30,0xF0,0x04,0x62,0x02,
+0x42,0x33,0xB7,0x44,0x20,0x08,0x61,0x02,0x4F,0x8C,
+0x64,0x10,0x0C,0x04,0x06,0x06,0x06,0x06,0x06,0x06,
+0x03,0xFC,0x08,0x61,0x02,0x47,0x8C,0x64,0x14,0x03,
+0x07,0x00,0xD0,0x06,0x82,0x63,0x1F,0x00,0x09,0x60,
+0x02,0x60,0x18,0x0E,0x07,0x81,0x60,0x98,0x66,0x11,
+0x8F,0xFC,0x83,0x00,0x08,0x61,0x02,0x4F,0xD0,0x80,
+0xC0,0x7E,0x31,0xA4,0x0D,0x04,0xC6,0x3E,0x00,0x08,
+0x61,0x02,0x47,0x86,0x66,0x12,0x01,0x78,0xC6,0x61,
+0x44,0x1B,0x08,0x8C,0x3C,0x08,0x61,0x02,0x5F,0xE0,
+0x60,0x20,0x30,0x10,0x18,0x08,0x41,0x84,0x90,0x00,
+0x08,0x61,0x02,0x47,0x84,0x68,0xC2,0x23,0x0F,0x18,
+0xD3,0x06,0xC6,0x1E,0x00,0x08,0x61,0x02,0x47,0x8C,
+0x66,0x14,0xC1,0xB1,0xCF,0x60,0x24,0x13,0x18,0xF0,
+0x01,0x4A,0x01,0x5D,0x20,0x02,0x61,0xE9,0x4E,0x92,
+0xA0,0x08,0x49,0x12,0x80,0x20,0x70,0xF1,0xC1,0x80,
+0x70,0x0F,0x01,0xC0,0x20,0x08,0x29,0x1A,0x9F,0xF2,
+0x00,0xFF,0x08,0x49,0x12,0x90,0x0E,0x03,0xC0,0x38,
+0x06,0x0E,0x3C,0x38,0x10,0x00,0x08,0x61,0x02,0x47,
+0x84,0x66,0x12,0x0C,0x04,0x06,0x06,0x40,0xC0,0x40,
+0x00,0x18,0x0F,0x81,0xE4,0x40,0xFC,0x03,0x03,0x06,
+0x01,0x8C,0x76,0xC8,0x8C,0x59,0x0C,0x66,0x61,0x8A,
+0x61,0x12,0x23,0x23,0x1D,0xC1,0x00,0x08,0x80,0x18,
+0x60,0x60,0x1F,0xC0,0x0B,0x60,0x02,0xC1,0xC2,0x02,
+0x80,0x6C,0x04,0x40,0x46,0x0C,0x60,0xFE,0x18,0x31,
+0x81,0x10,0x1B,0x01,0x80,0x09,0x61,0x02,0xDF,0xC6,
+0x0A,0x30,0x6C,0x13,0xFC,0xC1,0xCE,0x05,0x83,0x7F,
+0x80,0x0B,0x61,0x03,0x03,0xE0,0x43,0x08,0x1A,0xF0,
+0x03,0x01,0x90,0x31,0xC6,0x07,0xC0,0x0A,0x61,0x03,
+0x1F,0xE3,0x06,0x8C,0x0E,0xB0,0x18,0xC0,0xD8,0x33,
+0xFC,0x09,0x61,0x02,0xDF,0xFA,0xC0,0x3F,0xF7,0x80,
+0x7F,0xC0,0x09,0x61,0x02,0x9F,0xFA,0xC0,0x3F,0xD9,
+0x80,0x0B,0x61,0x03,0x43,0xF0,0x61,0x8C,0x0D,0x80,
+0xA3,0x00,0x30,0xFC,0x60,0x13,0x01,0x18,0x70,0xFC,
+0x0A,0x61,0x03,0x2F,0x03,0x7F,0xF9,0x81,0x80,0x01,
+0x62,0x01,0x77,0x70,0x07,0x60,0x02,0x74,0x08,0x0B,
+0x09,0x09,0x98,0xF0,0x0A,0x61,0x02,0xD8,0x3B,0x0E,
+0x63,0x0C,0xC1,0xB0,0x3E,0x07,0x60,0xC6,0x23,0x0C,
+0x60,0xCC,0x0C,0x08,0x61,0x02,0x77,0x02,0xB0,0x1F,
+0xE0,0x0C,0x61,0x03,0x9C,0x06,0xE0,0x77,0x83,0xB4,
+0x3D,0xA1,0x6D,0x8B,0x64,0xDB,0x24,0xD9,0xA6,0xC7,
+0x38,0xC6,0x30,0x0A,0x61,0x03,0x18,0x1C,0x70,0x6D,
+0x0E,0x32,0x38,0xC4,0xD8,0x5C,0x60,0xEC,0x0C,0x0B,
+0x61,0x03,0x43,0xE0,0x61,0x88,0x0D,0x80,0xE3,0x00,
+0xA0,0x0B,0x00,0xB0,0x19,0x01,0x8C,0x30,0x7C,0x00,
+0x0A,0x61,0x02,0xDF,0xE3,0x06,0x60,0x4C,0x0D,0x81,
+0x30,0x67,0xF9,0x78,0x00,0x0B,0x69,0xFB,0x43,0xE0,
+0xE1,0x88,0x09,0x80,0xD8,0x06,0x20,0x0B,0x00,0xB0,
+0x19,0x0D,0x8C,0x70,0x7F,0x80,0x08,0x0B,0x61,0x03,
+0x1F,0xF2,0xB0,0x33,0x02,0x3F,0xC3,0x08,0x30,0x43,
+0x06,0x30,0x33,0x01,0x80,0x09,0x61,0x02,0xC7,0xC3,
+0x0D,0x83,0x60,0x0C,0x01,0xF0,0x1F,0x00,0xD0,0x16,
+0x04,0xC3,0x1F,0x00,0x0A,0x60,0x02,0x9F,0xFE,0x86,
+0x14,0x18,0x00,0x0A,0x61,0x03,0x37,0x03,0x8C,0x0C,
+0x81,0x98,0x60,0xF8,0x0B,0x60,0x02,0xD8,0x0C,0x80,
+0xCC,0x08,0xC1,0x84,0x10,0x63,0x02,0x30,0x32,0x03,
+0x60,0x14,0x01,0xC0,0x0C,0x00,0x10,0x60,0x04,0x18,
+0x30,0x64,0x18,0x22,0x1E,0x14,0x31,0x23,0x08,0x99,
+0x04,0xCC,0x83,0x42,0xC1,0xA1,0x40,0x70,0xE2,0x06,
+0x06,0x00,0x0B,0x60,0x02,0xCC,0x0C,0x61,0x86,0x30,
+0x36,0x01,0xE0,0x0C,0x01,0xC0,0x36,0x03,0x30,0x63,
+0x0C,0x19,0x80,0xC0,0x0B,0x60,0x02,0xD8,0x0C,0xC1,
+0x86,0x10,0x63,0x03,0x62,0x03,0x85,0x82,0x00,0x0A,
+0x60,0x02,0x8F,0xFC,0x00,0xC0,0x30,0x0C,0x40,0x60,
+0x18,0x06,0x04,0x30,0x0F,0xFC,0x03,0x79,0xE9,0x5F,
+0x76,0x67,0x05,0x60,0x01,0x50,0x62,0x10,0x64,0x92,
+0x44,0x18,0x04,0x78,0xE9,0x5F,0xA7,0x86,0xF0,0x06,
+0x39,0x2A,0x20,0xC2,0xC4,0x99,0x44,0x20,0x0A,0x08,
+0xEA,0x5F,0xF8,0x03,0x11,0x51,0x98,0xC0,0x08,0x49,
+0x02,0x47,0x8C,0x64,0x10,0x79,0xE4,0x82,0x43,0x31,
+0x8F,0x60,0x08,0x61,0x02,0x67,0x01,0xF8,0xE6,0x61,
+0x30,0xD0,0x6C,0x36,0x13,0x19,0xF8,0x07,0x49,0x02,
+0x47,0x98,0xD8,0x66,0x03,0x0B,0x18,0xF0,0x07,0x61,
+0x02,0x64,0x09,0xEB,0x1D,0xC1,0x63,0x1D,0x08,0x49,
+0x02,0x47,0x84,0x66,0x12,0x0D,0xFE,0x80,0x61,0xB1,
+0x87,0x80,0x05,0x60,0x01,0x47,0x10,0xC7,0xF5,0x86,
+0x00,0x07,0x61,0xEA,0x4F,0x58,0xEE,0x0B,0x19,0xE8,
+0x0B,0x19,0xF0,0x07,0x61,0x02,0x67,0x03,0xF3,0x1E,
+0xE1,0x02,0x61,0x01,0x1C,0x1B,0xC6,0x04,0x7F,0xE9,
+0x07,0x01,0xA7,0x26,0x27,0x00,0x07,0x61,0x02,0x67,
+0x03,0x1B,0x33,0x64,0x78,0x6C,0x66,0x62,0x63,0x02,
+0x61,0x01,0x37,0xBC,0x0C,0x49,0x03,0x97,0xBC,0xC7,
+0x3D,0xC6,0x10,0x07,0x49,0x02,0x57,0x98,0xF7,0x08,
+0x08,0x49,0x02,0x47,0x8C,0x6B,0x83,0x63,0x0F,0x00,
+0x08,0x61,0xEA,0x57,0x8E,0x66,0x13,0x0D,0x06,0xC3,
+0x61,0x31,0x9F,0x93,0x80,0x07,0x61,0xEA,0x4F,0x58,
+0xEE,0x0B,0x18,0xEC,0x81,0x05,0x49,0x01,0x97,0xDC,
+0x30,0x07,0x49,0x02,0x4F,0x18,0x90,0x1C,0x0F,0xA0,
+0x1A,0x19,0xE0,0x05,0x60,0x01,0x44,0x86,0x3D,0xAC,
+0x1C,0x07,0x49,0x02,0x77,0x0B,0x19,0xE8,0x08,0x48,
+0x02,0x58,0x24,0x33,0x10,0x88,0x4C,0x34,0x81,0xC0,
+0xC0,0x0C,0x48,0x03,0x18,0xC2,0xC6,0x32,0x39,0x1B,
+0xC8,0xD2,0xC2,0x94,0x14,0xE0,0xE7,0x02,0x18,0x08,
+0x48,0x02,0x4C,0x66,0x61,0xA0,0x70,0x30,0x1C,0x1B,
+0x18,0x98,0x60,0x08,0x60,0xEA,0x58,0x24,0x33,0x10,
+0x88,0x6C,0x34,0x0A,0x07,0x20,0x60,0x20,0x70,0x08,
+0x48,0x02,0x4F,0xE0,0x20,0x30,0x30,0x30,0x30,0x10,
+0x18,0x1F,0xE0,0x05,0x78,0xE9,0x83,0xA3,0x41,0x18,
+0x82,0x51,0x83,0x01,0x82,0xE1,0x37,0xB8,0x80,0x05,
+0x78,0xE9,0x9C,0xA2,0x0C,0x10,0x21,0x0D,0x44,0x70,
+0x08,0x11,0x2A,0x9E,0x28,0xF0,
+};
+/* font data size: 1166 bytes */
+
+static const unsigned char Arial_12_index[] = {
+0x00,0x00,0x10,0x05,0x00,0xF0,0x3A,0x0C,0x02,0x38,
+0x5A,0x0B,0xC1,0xA0,0x39,0x87,0xA1,0x04,0x21,0xC4,
+0x58,0x8F,0x13,0x22,0x9C,0x57,0x8C,0x01,0xA0,0x38,
+0x07,0x78,0xFF,0x21,0xC4,0x74,0x96,0x13,0x12,0x6E,
+0x51,0x4A,0x61,0x5A,0x2D,0x46,0x28,0xCF,0x9A,0xF3,
+0x7E,0x73,0x4E,0xC1,0xE1,0x3E,0x87,0xF5,0x01,0x20,
+0xC4,0x3E,0x89,0xD1,0xEA,0x4D,0x4C,0x49,0xC5,0x43,
+0xA9,0x95,0x58,0xAD,0x56,0x02,0xD6,0x5E,0x0C,0x19,
+0x8A,0xB2,0x66,0x58,0xCD,0x99,0xEB,0x46,0x69,0x6D,
+0x41,0xAF,0x36,0xD6,0xF0,0xE0,0x9C,0x83,0x99,0x74,
+0xAE,0xB5,0xD9,0xBB,0xC7,0x92,0xF3,0x9E,0xBB,0xDE,
+0x7D,0x0F,0xDE,0x00,0xC0,0x78,0x27,0x06,0xE1,0x14,
+0x2F,0x88,0x31,0x3E,0x2F,0xC6,0xD8,0xEF,0x1F,0x64,
+0x40,
+};
+/* font index size: 131 bytes */
+
+const ILI9341_t3_font_t Arial_12 = {
+        Arial_12_index,
+        0,
+        Arial_12_data,
+        1,
+        0,
+        32,
+        126,
+        0,
+        0,
+        11,
+        5,
+        5,
+        3,
+        5,
+        5,
+        18,
+        12
+};
+
+
+
+static const unsigned char Arial_13_data[] = {
+0x00,0x00,0x01,0x40,0x02,0x6A,0x01,0xB7,0x9C,0x46,
+0x05,0x29,0x41,0xAF,0x60,0x0B,0x68,0x02,0xA0,0x33,
+0x06,0x64,0x7F,0xF0,0xCC,0x1D,0xC1,0x98,0x8F,0xFE,
+0x33,0x10,0xCC,0x00,0x09,0x81,0xF2,0x81,0x01,0xF0,
+0xFE,0x64,0xD9,0x07,0x40,0xF8,0x0F,0x81,0xF0,0x4D,
+0x93,0x75,0xCF,0xE1,0xF2,0x02,0x00,0x0E,0x69,0x04,
+0x0F,0x0C,0x46,0x66,0x11,0x9B,0x03,0x3E,0x03,0xDB,
+0xC0,0x3C,0xE0,0x1B,0x38,0x0C,0xCC,0x30,0xF0,0x0B,
+0x69,0x03,0x03,0xC0,0x7E,0x20,0xCC,0x0D,0x80,0x70,
+0x1F,0x01,0xB3,0x31,0xB3,0x0E,0x38,0xE1,0xFF,0x0F,
+0x18,0x02,0x28,0x40,0xEF,0x05,0x89,0xE1,0x81,0x08,
+0x48,0x66,0xE2,0x18,0x20,0x40,0x80,0x05,0x88,0xE1,
+0x90,0x20,0x48,0x36,0x8E,0x0C,0x21,0x08,0x00,0x05,
+0x29,0x41,0xC4,0x7C,0x48,0x50,0x0A,0x51,0x0A,0xE8,
+0x30,0x8F,0xFE,0x83,0x00,0x02,0x22,0xF1,0x63,0x28,
+0x05,0x10,0x21,0xA3,0xE0,0x02,0x12,0x01,0x63,0x06,
+0x68,0x01,0x60,0x39,0x1A,0x4C,0x96,0x23,0x00,0x08,
+0x69,0x02,0x87,0x87,0xE7,0x3E,0xE1,0xB9,0xCF,0xC3,
+0xC0,0x05,0x6A,0x02,0x83,0x1C,0xF6,0xD3,0xD1,0x86,
+0x08,0x69,0x02,0x87,0x87,0xE7,0x3B,0x0E,0x00,0xC0,
+0xC0,0xC0,0xC1,0xC0,0xC1,0x1F,0xE0,0x08,0x69,0x02,
+0x87,0x07,0xC6,0x34,0x03,0x07,0x03,0xD0,0x07,0x18,
+0x67,0xE1,0xE0,0x09,0x68,0x02,0x80,0xC8,0x0E,0x07,
+0x90,0x6C,0x33,0x18,0xC8,0xFF,0xC8,0x30,0x08,0x69,
+0x02,0xA1,0xF8,0xC0,0xC0,0x6E,0x3F,0x98,0x70,0x07,
+0x18,0x67,0xE1,0xE0,0x08,0x69,0x02,0x87,0x87,0xE3,
+0x1C,0x60,0x37,0x1F,0xCE,0x38,0xC3,0x31,0x9F,0x87,
+0x80,0x08,0x69,0x02,0xA3,0xFC,0x04,0x06,0x80,0xC9,
+0x18,0x1C,0x49,0x80,0x08,0x69,0x02,0x87,0x87,0xE9,
+0xC3,0x87,0xEA,0xC3,0x3F,0x0F,0x00,0x08,0x69,0x02,
+0x87,0x87,0xE9,0xC3,0x63,0x9F,0xC7,0x70,0x06,0xC6,
+0x3F,0x0F,0x00,0x02,0x52,0x01,0x63,0xC2,0x30,0x02,
+0x62,0xF1,0x63,0xC2,0x32,0x80,0x09,0x49,0x12,0xC0,
+0x10,0x1C,0x3E,0x3C,0x18,0x03,0xC0,0x3E,0x01,0xC0,
+0x10,0x09,0x31,0x22,0xE3,0xFF,0x00,0x08,0xFF,0x80,
+0x09,0x49,0x12,0xD0,0x07,0x00,0xF8,0x07,0x80,0x30,
+0x78,0xF8,0x70,0x10,0x00,0x08,0x69,0x02,0x87,0x87,
+0xE7,0x3B,0x0C,0x06,0x06,0x06,0x06,0x20,0xC0,0x01,
+0x06,0x00,0x11,0x89,0xE4,0x80,0x7E,0x00,0x7F,0xE0,
+0x38,0x1C,0x18,0xEF,0x8C,0x7F,0x73,0x33,0x8D,0x9C,
+0x63,0x66,0x18,0xD9,0x84,0x36,0x63,0x19,0x9C,0xCE,
+0x63,0xFF,0x0C,0xEF,0x03,0x80,0x1C,0x78,0x0E,0x0F,
+0xFF,0x00,0xFF,0x00,0x0B,0x68,0x02,0xE0,0x38,0x48,
+0xD8,0x83,0x18,0x3F,0x87,0xFD,0x0C,0x1A,0x30,0x18,
+0x0A,0x69,0x03,0x1F,0xE3,0xFE,0x9C,0x0E,0x3F,0xE9,
+0xC0,0xD8,0x3B,0xFE,0x7F,0x80,0x0B,0x69,0x03,0x43,
+0xE0,0x7F,0x8E,0x1C,0xC0,0xEF,0x00,0x18,0x19,0xC3,
+0x0F,0xF0,0x3C,0x00,0x0B,0x69,0x03,0x5F,0xE1,0xFF,
+0x18,0x39,0x81,0xEF,0x01,0xB0,0x33,0x07,0x3F,0xE3,
+0xFC,0x00,0x0A,0x69,0x03,0x23,0xFF,0x9C,0x02,0x3F,
+0xEA,0xC0,0x23,0xFF,0x09,0x69,0x02,0xE3,0xFF,0x38,
+0x08,0xFF,0x66,0x00,0x0C,0x69,0x03,0x81,0xF0,0x3F,
+0xE3,0x83,0x18,0x0E,0x30,0x02,0x30,0xFD,0x80,0x66,
+0x03,0x38,0x38,0xFF,0x81,0xF0,0x0B,0x69,0x03,0x6F,
+0x01,0xC7,0xFF,0xCC,0x06,0x02,0x69,0x01,0x37,0xCC,
+0x07,0x69,0x02,0x74,0x1C,0x03,0x8C,0x6F,0xC7,0x80,
+0x0B,0x69,0x03,0x18,0x39,0x87,0x18,0xE1,0x9C,0x1B,
+0x81,0xF0,0x1F,0x81,0xDC,0x18,0xE1,0x86,0x18,0x71,
+0x83,0x98,0x1C,0x08,0x69,0x02,0xB7,0x02,0xB0,0x23,
+0xFC,0x0D,0x69,0x03,0xDC,0x07,0x9F,0x07,0xCE,0xC6,
+0xD9,0x13,0x9C,0xD9,0xC6,0x38,0xC0,0x0B,0x69,0x03,
+0x58,0x0D,0xC0,0xE3,0xC1,0xB6,0x1B,0x31,0xB3,0x9B,
+0x19,0xB0,0xDC,0x60,0xF6,0x07,0x60,0x30,0x0C,0x69,
+0x03,0x81,0xF0,0x3F,0xC3,0x87,0x18,0x1A,0xF0,0x0C,
+0xC0,0xC7,0x0E,0x1F,0xE0,0x3C,0x00,0x0A,0x69,0x03,
+0x1F,0xE3,0xFE,0x60,0xF1,0x81,0xB0,0x77,0xFC,0xFF,
+0x2F,0x00,0x0C,0x69,0x03,0x83,0xF0,0x3F,0xC3,0x87,
+0x18,0x1E,0xF0,0x0C,0xC6,0xC7,0x1C,0x1F,0xE0,0x7D,
+0xC0,0x0C,0x69,0x03,0x5F,0xF0,0xFF,0xC6,0x07,0x30,
+0x19,0x81,0xCF,0xFC,0x7F,0xC3,0x0C,0x18,0x70,0xC1,
+0xC6,0x06,0x30,0x39,0x80,0xE0,0x0A,0x69,0x03,0x03,
+0xE1,0xFE,0x70,0xEC,0x0D,0x80,0x1E,0x01,0xF8,0x07,
+0x80,0x1B,0x03,0x70,0xE7,0xF8,0x7E,0x00,0x0A,0x69,
+0x03,0x23,0xFF,0xD0,0xC2,0x83,0x00,0x0B,0x69,0x03,
+0x77,0x01,0xCE,0x03,0x70,0x63,0xFE,0x0F,0x80,0x0B,
+0x68,0x02,0xE3,0x01,0xCB,0x06,0x93,0x19,0x23,0x62,
+0x03,0x80,0x11,0x68,0x04,0x63,0x07,0x07,0x4C,0x6C,
+0x63,0x11,0x1A,0x8D,0x8D,0x90,0x38,0x38,0x0B,0x68,
+0x02,0xCE,0x38,0x63,0x20,0x6C,0x48,0x70,0x81,0xB0,
+0x3B,0x83,0x18,0x60,0xCE,0x0E,0x0C,0x68,0x03,0x1C,
+0x0E,0x60,0x61,0x86,0x0E,0x70,0x33,0x10,0x1E,0x18,
+0x0C,0x00,0x0A,0x68,0x02,0xE1,0xFF,0x00,0xC0,0x30,
+0x0E,0x01,0x80,0x60,0x18,0x07,0x00,0xC0,0x30,0x11,
+0xFF,0x80,0x04,0x89,0xE1,0x63,0xF7,0x33,0x23,0xC0,
+0x06,0x68,0x01,0x63,0x09,0x62,0x4C,0x91,0xA0,0x30,
+0x04,0x88,0xE1,0x63,0xF4,0xF0,0xE3,0xC0,0x07,0x38,
+0x31,0xC2,0x07,0x05,0x21,0xB1,0x13,0x18,0x0A,0x10,
+0xE2,0xA3,0xFF,0x03,0x11,0x59,0x98,0xC0,0x08,0x51,
+0x02,0x87,0xC7,0xF6,0x18,0x3C,0xFE,0xF3,0x61,0xB1,
+0xDF,0xE7,0xB0,0x08,0x69,0x02,0xA7,0x01,0xB8,0xFE,
+0x73,0xD6,0x1B,0x9D,0xFC,0xDC,0x07,0x51,0x02,0x47,
+0x8F,0xDC,0xEB,0x03,0x99,0xF8,0xF0,0x08,0x69,0x02,
+0xA4,0x0C,0x76,0x7F,0x73,0xD6,0x1B,0x9C,0xFE,0x3B,
+0x08,0x51,0x02,0x87,0x87,0xE7,0x33,0x0E,0x3F,0xD8,
+0x0E,0x33,0xF0,0xF0,0x06,0x68,0x01,0x47,0x9F,0x31,
+0x1F,0x6B,0x06,0x00,0x08,0x71,0xE2,0x87,0x67,0xF7,
+0x3D,0x61,0xB9,0xCF,0xE3,0xB0,0x1B,0x1D,0xFC,0x7C,
+0x08,0x69,0x02,0xA7,0x01,0xBC,0xFF,0x71,0xEE,0x18,
+0x02,0x69,0x01,0x23,0x1B,0xCE,0x04,0x8F,0xE1,0x20,
+0xC1,0xA7,0x66,0xF7,0x00,0x08,0x69,0x02,0x67,0x01,
+0x8E,0xCE,0x6E,0x3C,0x1F,0x0D,0x88,0xCC,0x63,0x31,
+0xC0,0x02,0x69,0x01,0x37,0xCC,0x0C,0x51,0x03,0x9B,
+0x9C,0xFD,0xF7,0x39,0xEE,0x31,0x80,0x08,0x51,0x02,
+0x9B,0xCF,0xF7,0x1E,0xE1,0x80,0x08,0x51,0x02,0x87,
+0x87,0xE7,0x3D,0x61,0xB9,0xCF,0xC3,0xC0,0x08,0x71,
+0xE2,0x9B,0x8F,0xE7,0x3D,0x61,0xB9,0xDF,0xCD,0xCA,
+0xC0,0x08,0x71,0xE2,0x87,0x67,0xF7,0x3D,0x61,0xB9,
+0xCF,0xE3,0xBA,0x03,0x05,0x51,0x01,0x9B,0x7D,0xCD,
+0xC0,0x07,0x51,0x02,0x4F,0x9F,0xD8,0xDC,0x0F,0x03,
+0x81,0xD8,0xDF,0xCF,0x80,0x04,0x68,0x01,0x65,0xA3,
+0xF1,0xA1,0xC0,0x08,0x51,0x02,0xB7,0x0D,0x8E,0xFF,
+0x3D,0x80,0x09,0x50,0x02,0x63,0x07,0x2C,0x68,0x36,
+0x40,0xE0,0x10,0x0D,0x50,0x03,0x58,0x43,0x8C,0x71,
+0x99,0x4D,0x0D,0xB6,0x14,0x52,0x0E,0x38,0x18,0xC0,
+0x08,0x50,0x02,0x18,0x70,0xCC,0x3C,0x81,0x81,0xE4,
+0x33,0x30,0xC0,0x09,0x70,0xE2,0x63,0x07,0x0C,0x61,
+0x98,0x6C,0x81,0xE4,0x86,0x03,0x03,0xC0,0xE0,0x08,
+0x50,0x02,0x23,0xFC,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,
+0x08,0xFF,0x06,0x88,0xE1,0x83,0x8F,0xA3,0x0E,0x47,
+0x07,0x2C,0xC1,0xE1,0xC0,0x02,0x8A,0xE1,0xB7,0xDE,
+0x70,0x06,0x88,0xE1,0x9C,0x3C,0xA3,0x07,0x40,0xE3,
+0xAC,0xC7,0x8E,0x00,0x0A,0x20,0x22,0xCE,0x03,0xF1,
+0x47,0xE0,0x38,};
+
+static const unsigned char Arial_13_index[] = {
+0x00,0x00,0x10,0x05,0x00,0xF0,0x44,
+0x0E,0x42,0x78,0x65,0x0D,0x21,0xD4,0x40,0x88,0x81,
+0x22,0x25,0x84,0xD8,0x9F,0x15,0x22,0xD4,0x5F,0x0C,
+0xF1,0xBE,0x3B,0x87,0xF1,0x0F,0x23,0x84,0xA4,0x9C,
+0x93,0xF2,0x8C,0x55,0x4A,0xF1,0x6D,0x2F,0xC6,0xA0,
+0xDC,0x1C,0x83,0xB4,0x7B,0x0F,0xC2,0x02,0x43,0x08,
+0x85,0x13,0x23,0x04,0x8E,0x93,0xD2,0xFA,0x74,0x50,
+0xEA,0x59,0x54,0xAC,0x25,0xB0,0xB8,0x57,0x6A,0xFA,
+0x61,0x4C,0x71,0x96,0x34,0x06,0x90,0xD4,0x9A,0xD3,
+0x64,0x6D,0x2D,0xB9,0xBE,0xB8,0xA7,0x2A,0xE8,0x9D,
+0x83,0xBA,0x79,0x4F,0x51,0xED,0x3E,0x37,0xE6,0xFE,
+0x20,0x1C,0x0C,0x83,0x10,0x96,0x19,0x43,0x98,0x8F,
+0x13,0xE2,0xC4,0x63,0x8E,0x92,0x06,0x48,0xC9,0xE9,
+0x57,0x2C,0x65,0xF0,
+};
+
+const ILI9341_t3_font_t Arial_13 = {
+       Arial_13_index,
+       0,
+       Arial_13_data,
+       1,
+       0,
+       32,
+       126,
+       0,
+       0,
+       11,
+       5,
+       5,
+       3,
+       5,
+       5,
+       19,
+       13
+};
+
+
+
+static const unsigned char Arial_14_data[] = {
+0x00,0x00,0x01,0x40,0x02,0x72,0x01,0xB7,0xAC,0x46,
+0x05,0x29,0x49,0xEF,0x60,0x0B,0x70,0x02,0xE0,0x33,
+0x06,0x64,0x7F,0xF8,0x19,0x83,0x31,0x1F,0xFE,0x0C,
+0xC4,0x33,0x00,0x09,0x89,0xF2,0xC1,0x01,0xF0,0xFE,
+0x74,0xE3,0x20,0x78,0x0F,0x80,0xF0,0x2E,0x09,0xB2,
+0x6E,0xB9,0xFC,0x3E,0x40,0x40,0x0F,0x71,0x04,0x4F,
+0x03,0x23,0x30,0xC3,0x31,0x84,0x66,0x60,0x3C,0xC0,
+0x00,0xDE,0x80,0x36,0x60,0x66,0x70,0x18,0xCC,0x30,
+0x78,0x0C,0x71,0x03,0x43,0xC0,0x3F,0x08,0x63,0x03,
+0x98,0x0F,0x80,0x78,0x07,0xC0,0x73,0x33,0x0D,0x98,
+0x38,0xE3,0xC3,0xFB,0x0F,0x8C,0x02,0x29,0x49,0x2F,
+0x05,0x91,0xE1,0x81,0x08,0x68,0x61,0x19,0x82,0x21,
+0x83,0x04,0x08,0x05,0x90,0xE1,0x90,0x20,0xC8,0x30,
+0x58,0x30,0xA0,0xC6,0x10,0x80,0x05,0x31,0x41,0xE0,
+0x8F,0x89,0x0A,0x0A,0x51,0x0A,0xE8,0x30,0x8F,0xFE,
+0x83,0x00,0x02,0x29,0xE9,0x63,0x85,0x00,0x05,0x10,
+0x21,0xA3,0xE0,0x02,0x12,0x01,0x63,0x06,0x70,0x01,
+0x60,0x39,0x1A,0x8C,0x96,0x23,0x00,0x09,0x71,0x02,
+0xC7,0xC3,0xF8,0xC6,0xDC,0x1B,0x06,0x63,0x1F,0xC3,
+0xE0,0x05,0x72,0x02,0xE0,0x63,0xBE,0xDE,0x8E,0x06,
+0x09,0x71,0x02,0xC7,0xC3,0xF9,0xC7,0x60,0xE0,0x06,
+0x03,0x01,0x80,0xC0,0x60,0x30,0x18,0x11,0xFF,0x09,
+0x71,0x02,0xC7,0x83,0xF1,0xC6,0x61,0x80,0x60,0xF0,
+0x3E,0x01,0xE0,0x06,0xC1,0xB8,0xE7,0xF0,0xF8,0x0A,
+0x70,0x02,0xC0,0x20,0x0C,0x03,0x80,0xF2,0x06,0xC1,
+0x98,0x63,0x18,0x64,0x7F,0xF2,0x06,0x00,0x09,0x71,
+0x02,0xE1,0xFD,0x0C,0x06,0x01,0xBC,0x7F,0x98,0x38,
+0x01,0xB0,0x6E,0x39,0xFC,0x3E,0x00,0x09,0x71,0x02,
+0xC3,0xC1,0xF8,0xC7,0x70,0xD8,0x06,0xF1,0xFE,0x71,
+0xE7,0x06,0x63,0x9F,0xC1,0xE0,0x09,0x71,0x02,0xE3,
+0xFE,0x01,0x00,0xC0,0x60,0x11,0x01,0x89,0x18,0x49,
+0x80,0x09,0x71,0x02,0xC7,0xC3,0xF9,0xC7,0x8C,0x1B,
+0x8F,0x0F,0xE7,0x1E,0x30,0x6C,0x39,0xFC,0x3E,0x00,
+0x09,0x71,0x02,0xC7,0x83,0xF9,0xC6,0x9C,0x1B,0x8E,
+0x7F,0x8F,0x60,0x1B,0x06,0xE3,0x1F,0xC3,0xC0,0x02,
+0x52,0x01,0x63,0xC2,0x30,0x02,0x6A,0xE9,0x63,0xC2,
+0x38,0x50,0x09,0x49,0x12,0xC0,0x10,0x1C,0x3E,0x3C,
+0x18,0x03,0xC0,0x3E,0x01,0xC0,0x10,0x09,0x31,0x22,
+0xE3,0xFF,0x00,0x08,0xFF,0x80,0x09,0x49,0x12,0xD0,
+0x07,0x00,0xF8,0x07,0x80,0x30,0x78,0xF8,0x70,0x10,
+0x00,0x09,0x71,0x02,0xC7,0xC3,0xF9,0xC7,0x60,0xC0,
+0x30,0x18,0x0E,0x07,0x03,0x88,0x18,0x00,0x10,0x30,
+0x12,0x91,0xE4,0xC0,0x7F,0x00,0x3F,0xF8,0x0F,0x07,
+0x83,0x80,0x38,0xE3,0xDB,0x18,0xFF,0x37,0x39,0xC6,
+0xCE,0x18,0xD9,0x83,0x1B,0x30,0x47,0x66,0x18,0xCC,
+0xE7,0x31,0xCF,0xFE,0x18,0xEF,0x03,0x80,0x0E,0x3C,
+0x07,0x81,0xFF,0xE0,0x0F,0xE0,0x0D,0x70,0x03,0x60,
+0x1C,0x12,0x1B,0x08,0x18,0xC0,0xC1,0x90,0x7F,0xC8,
+0x60,0x34,0x60,0x0C,0x0A,0x72,0x03,0x5F,0xC3,0xFC,
+0x61,0xD1,0x83,0x30,0xE8,0xFF,0x18,0x34,0x60,0x6C,
+0x1D,0xFF,0x3F,0xC0,0x0C,0x71,0x03,0x81,0xE0,0x3F,
+0xC3,0x83,0x18,0x0E,0xF0,0x01,0x80,0x66,0x06,0x38,
+0x70,0xFF,0x01,0xE0,0x0B,0x72,0x03,0x9F,0xE1,0xFF,
+0x18,0x39,0x81,0xB3,0x01,0xB0,0x33,0x07,0x3F,0xE3,
+0xFC,0x00,0x0A,0x72,0x03,0x63,0xFF,0xAC,0x02,0x3F,
+0xEA,0xC0,0x23,0xFF,0x09,0x72,0x03,0x23,0xFF,0x58,
+0x08,0xFF,0x66,0x00,0x0D,0x71,0x03,0xC1,0xF8,0x1F,
+0xF0,0xE0,0xE3,0x01,0xDC,0x02,0x8C,0x00,0x46,0x0F,
+0xD8,0x03,0x30,0x0C,0xF0,0x71,0xFF,0x81,0xF8,0x0B,
+0x71,0x03,0x73,0x01,0xC7,0xFF,0xCC,0x06,0x02,0x72,
+0x01,0xB7,0xDC,0x07,0x71,0x02,0xB4,0x1C,0x83,0x8C,
+0x6F,0xC7,0x80,0x0B,0x72,0x03,0x58,0x39,0x87,0x18,
+0xE1,0x9C,0x1B,0x81,0xB0,0x1F,0x01,0xF8,0x19,0xC1,
+0x8C,0x18,0x61,0x87,0x18,0x39,0x81,0xC0,0x08,0x72,
+0x02,0xF7,0x02,0xF0,0x23,0xFC,0x0D,0x71,0x03,0xDC,
+0x07,0x9F,0x07,0xD6,0xC6,0xE7,0x36,0x6C,0x51,0xC6,
+0x38,0xC0,0x0B,0x71,0x03,0x58,0x0D,0xC0,0xE3,0xC1,
+0xB6,0x1C,0x66,0x38,0xC6,0x6C,0x37,0x18,0x3D,0x81,
+0xD8,0x0C,0x0D,0x71,0x03,0xC1,0xF0,0x1F,0xF0,0xE0,
+0xE3,0x01,0xB3,0x00,0x66,0x03,0x1C,0x1C,0x3F,0xE0,
+0x3E,0x00,0x0A,0x72,0x03,0x5F,0xE3,0xFE,0x60,0xF3,
+0x81,0xB0,0x77,0xFC,0xFF,0x2F,0x00,0x0D,0x71,0x03,
+0xC1,0xF0,0x1F,0xF0,0xE0,0xE3,0x01,0xB3,0x00,0x66,
+0x1B,0x1C,0x38,0x3F,0xE0,0x3E,0xE0,0x0B,0x72,0x03,
+0x9F,0xE1,0xFF,0x18,0x3A,0x30,0x33,0x07,0x3F,0xE3,
+0xFC,0x31,0x83,0x0C,0x30,0xE3,0x07,0x30,0x33,0x03,
+0x80,0x0B,0x71,0x03,0x43,0xF0,0x7F,0x8E,0x1C,0xC0,
+0xCC,0x00,0x70,0x03,0xE0,0x07,0x80,0x0E,0x30,0x19,
+0xC3,0x9F,0xF0,0x7E,0x00,0x0A,0x71,0x03,0x23,0xFF,
+0xD0,0xC2,0xC3,0x00,0x0B,0x71,0x03,0x77,0x01,0xD6,
+0x03,0x30,0x63,0xFE,0x0F,0x80,0x0D,0x70,0x03,0x63,
+0x00,0x72,0xC0,0x68,0x30,0x64,0x8C,0x62,0x03,0x61,
+0x00,0xE0,0x13,0x70,0x04,0xE3,0x03,0x81,0xCB,0x0D,
+0x86,0x86,0x31,0x8D,0x06,0x63,0x32,0x4D,0x83,0x64,
+0x0E,0x03,0x80,0x0D,0x70,0x03,0x4E,0x0E,0x1C,0x70,
+0x31,0x80,0xEE,0x01,0xB0,0x90,0x70,0x03,0x60,0x1D,
+0xC0,0xE3,0x83,0x06,0x1C,0x1C,0xE0,0x38,0x0C,0x70,
+0x03,0x1C,0x0E,0x60,0x61,0x86,0x0E,0x70,0x33,0x01,
+0xD8,0x07,0x86,0x83,0x00,0x0B,0x70,0x03,0x21,0xFF,
+0x80,0x30,0x06,0x40,0x18,0x03,0x00,0x60,0x81,0x80,
+0x30,0x06,0x01,0x1F,0xFC,0x04,0x91,0xE1,0x63,0xF7,
+0x37,0x23,0xC0,0x06,0x70,0x01,0x63,0x09,0x62,0x8C,
+0x91,0xA0,0x30,0x04,0x90,0xE1,0x63,0xF4,0xF4,0xE3,
+0xC0,0x07,0x38,0x39,0xC2,0x07,0x05,0x21,0xB1,0x13,
+0x18,0x0B,0x10,0xE2,0xE3,0xFF,0x80,0x03,0x19,0x59,
+0x98,0xC4,0x09,0x51,0x02,0x87,0xC7,0xF9,0x86,0x07,
+0x8F,0xE7,0x99,0x86,0x63,0x9F,0xE3,0xCC,0x09,0x71,
+0x02,0xEB,0x00,0xDE,0x3F,0xCE,0x3D,0x60,0xDC,0x77,
+0xF9,0xBC,0x08,0x51,0x02,0x87,0x87,0xE7,0x3D,0x60,
+0x39,0xCF,0xC3,0xC0,0x09,0x71,0x02,0xE8,0x06,0x3D,
+0x9F,0xEE,0x3D,0x60,0xDC,0x73,0xFC,0x7B,0x09,0x51,
+0x02,0xC7,0xC3,0xF9,0xC6,0x60,0xE3,0xFE,0xC0,0x38,
+0x67,0xF0,0xF8,0x06,0x71,0x01,0x87,0x9F,0x86,0x23,
+0xED,0x60,0xC0,0x09,0x71,0xE2,0xC7,0xB3,0xFD,0xC7,
+0xAC,0x1B,0x8E,0x7F,0x8F,0x60,0x1B,0x0E,0xFF,0x0F,
+0x80,0x08,0x71,0x02,0xAB,0x01,0xBC,0xFF,0x71,0xEE,
+0x18,0x02,0x71,0x01,0x23,0x83,0x79,0xC0,0x04,0x97,
+0xE1,0x20,0xE0,0x34,0xEC,0xDE,0xE0,0x08,0x71,0x02,
+0x6B,0x01,0x8E,0xCE,0x6E,0x47,0xC3,0x71,0x98,0xCE,
+0x63,0x31,0xC0,0x02,0x71,0x01,0x37,0xDC,0x0E,0x51,
+0x04,0x1B,0xCF,0x3F,0xBF,0x71,0xC7,0xB8,0x61,0x80,
+0x08,0x51,0x02,0x9B,0xCF,0xF7,0x1E,0xE1,0x80,0x09,
+0x51,0x02,0xC7,0xC3,0xF9,0xC7,0xAC,0x1B,0x8E,0x7F,
+0x0F,0x80,0x09,0x71,0xE2,0xDB,0xC7,0xF9,0xC7,0xAC,
+0x1B,0x8C,0xFF,0x37,0x95,0x80,0x09,0x71,0xE2,0xC7,
+0xB3,0xFD,0xC7,0xAC,0x19,0x8E,0x7F,0x8F,0x74,0x03,
+0x05,0x51,0x01,0x9B,0x7D,0xCD,0xC0,0x08,0x51,0x02,
+0x8F,0x8F,0xE6,0x1B,0x80,0xF0,0x1E,0x03,0xB0,0xCF,
+0xE3,0xE0,0x05,0x68,0x01,0x65,0x91,0xFC,0x61,0xE3,
+0x80,0x08,0x51,0x02,0xB7,0x0D,0x8E,0xFF,0x3D,0x80,
+0x09,0x50,0x02,0x63,0x07,0x2C,0x68,0x36,0x40,0xE0,
+0x10,0x0D,0x50,0x03,0x58,0x43,0x8C,0x71,0x99,0x4D,
+0x0D,0xB6,0x14,0x52,0x0E,0x38,0x18,0xC0,0x09,0x50,
+0x02,0x58,0x33,0x1A,0x0D,0x90,0x38,0x83,0x61,0x8C,
+0xC1,0x80,0x09,0x70,0xE2,0x63,0x07,0x0C,0x61,0x98,
+0x6C,0x81,0xE4,0x86,0x03,0x03,0xC0,0xE0,0x09,0x50,
+0x02,0x61,0xFE,0x03,0x81,0xC1,0xE0,0xE0,0x70,0x38,
+0x11,0xFF,0x06,0x90,0xE1,0x83,0x8F,0xB3,0x0E,0x47,
+0x07,0x2C,0xC1,0xE1,0xC0,0x02,0x92,0xE1,0xB7,0xDE,
+0xB0,0x06,0x90,0xE1,0x9C,0x3C,0xB3,0x07,0x40,0xE3,
+0xAC,0xC7,0x8E,0x00,0x09,0x21,0x22,0xCE,0x07,0xC5,
+0x1F,0x03,0x80,};
+/* font data size: 1313 bytes */
+
+static const unsigned char Arial_14_index[] = {
+0x00,0x00,0x10,0x05,0x00,0xF0,0x42,
+0x0E,0x02,0x88,0x6A,0x0D,0xC1,0xEC,0x44,0x08,0xF1,
+0x30,0x27,0x85,0x18,0xA7,0x16,0x22,0xFC,0x64,0x0D,
+0xB1,0xDE,0x40,0x88,0xA9,0x28,0x26,0xE5,0x28,0xAE,
+0x96,0x32,0xD4,0x5E,0x4C,0x11,0x91,0x34,0x87,0x48,
+0xF2,0x1F,0x84,0x18,0x87,0x91,0x52,0x34,0x49,0xA9,
+0x59,0x2D,0xA6,0x54,0xFC,0xA1,0x94,0xB2,0xAA,0x57,
+0xCB,0x35,0x70,0xAF,0x96,0x22,0xC6,0x99,0x33,0x36,
+0x69,0x6D,0x91,0xBA,0xB8,0x97,0x22,0xE6,0xDD,0x1B,
+0xAD,0x76,0x6E,0xE1,0xE4,0x3D,0x67,0xC4,0xFC,0x1F,
+0xFC,0x09,0x83,0x70,0x96,0x16,0x43,0x58,0x8B,0x12,
+0xA2,0xB4,0x5F,0x8D,0x91,0xEA,0x44,0x48,0xF9,0x3D,
+0x29,0xE5,0x84,0xBB,0x99,0x93,0x6A,0x75,0x4F,0x8A,
+0x0B,0x42,0xE8,0xC0,
+};
+/* font index size: 131 bytes */
+
+const ILI9341_t3_font_t Arial_14 = {
+       Arial_14_index,
+       0,
+       Arial_14_data,
+       1,
+       0,
+       32,
+       126,
+       0,
+       0,
+       11,
+       5,
+       5,
+       3,
+       5,
+       5,
+       21,
+       14
+};
+
+
+
+static const unsigned char Arial_16_data[] = {
+0x00,0x00,0x01,0x80,0x02,0x82,0x01,0xB7,0xBE,0x08,
+0xC0,0x06,0x31,0x52,0x33,0x30,0x0C,0x80,0x03,0x24,
+0x31,0x83,0x19,0x1F,0xFF,0x03,0x19,0x06,0x31,0x1F,
+0xFE,0x31,0x89,0x63,0x00,0x0A,0x99,0xF3,0x01,0x00,
+0xF8,0x3F,0xCE,0x9D,0x91,0xB2,0x07,0x40,0x78,0x07,
+0xE0,0x3E,0x04,0xE0,0x8E,0x32,0x33,0x4C,0x7F,0x87,
+0xC4,0x04,0x00,0x12,0x81,0x05,0x07,0x00,0xC1,0xB0,
+0x30,0x63,0x06,0x0C,0x61,0x82,0x31,0x8C,0x06,0x33,
+0x00,0x6C,0x67,0x07,0x19,0xB4,0x00,0xCC,0x70,0x06,
+0x31,0x81,0x86,0x30,0x60,0x6C,0x0C,0x07,0x00,0x0D,
+0x81,0x03,0xC1,0xC0,0x0F,0x82,0x4C,0x60,0x1B,0x00,
+0x7C,0x01,0xC0,0x1D,0x80,0x63,0x33,0x06,0xCC,0x1E,
+0x30,0x38,0x61,0xA1,0xFE,0x61,0xE1,0x00,0x02,0x31,
+0x51,0x33,0x05,0xA1,0xE1,0xC1,0x08,0x61,0x21,0x9B,
+0x86,0x21,0x82,0x0C,0x10,0x20,0x05,0xA1,0xE1,0xD0,
+0x20,0xC1,0x20,0xDA,0x30,0xE0,0xC2,0x18,0x42,0x00,
+0x08,0x39,0x4A,0x60,0x61,0xFF,0x07,0x86,0x61,0x20,
+0x0A,0x51,0x1B,0x68,0x30,0x8F,0xFE,0x83,0x00,0x02,
+0x2A,0xE9,0xA3,0x85,0x00,0x06,0x10,0x29,0xE3,0xF0,
+0x02,0x12,0x01,0xA3,0x07,0x80,0x01,0xA0,0x1C,0x86,
+0x91,0x92,0x62,0x58,0x38,0x30,0x00,0x0A,0x81,0x03,
+0x03,0xC0,0xFE,0x86,0x1B,0x70,0x36,0x07,0x0C,0x30,
+0xFC,0x0F,0x00,0x06,0x82,0x03,0x20,0x30,0xE7,0xDD,
+0xA3,0xD0,0xE4,0x30,0x0A,0x81,0x03,0x07,0xE1,0xFE,
+0x70,0xEC,0x0E,0x40,0x30,0x0C,0x03,0x00,0xC0,0x30,
+0x0C,0x03,0x00,0xC0,0x47,0xFE,0x0A,0x81,0x03,0x07,
+0xC1,0xFC,0x71,0xCC,0x18,0x03,0x00,0xC0,0x70,0x0F,
+0x00,0x34,0x80,0x6C,0x0D,0xC3,0x1F,0xE1,0xF0,0x0A,
+0x81,0x03,0x00,0x60,0x1C,0x80,0xF2,0x06,0xC1,0x98,
+0x73,0x0C,0x63,0x0C,0x8F,0xFE,0x80,0xC0,0x0A,0x81,
+0x03,0x20,0xFE,0x96,0x00,0xFC,0x3F,0xE6,0x0D,0x40,
+0x1B,0x03,0x70,0xC7,0xF8,0x7C,0x00,0x0A,0x81,0x03,
+0x03,0xE0,0xFE,0x30,0xE6,0x0E,0x30,0x06,0x78,0xFF,
+0x9C,0x3D,0x60,0x66,0x18,0xFF,0x07,0x80,0x0A,0x81,
+0x03,0x23,0xFF,0x00,0x40,0x18,0x06,0x40,0x31,0x01,
+0x84,0x8C,0x01,0x02,0x4C,0x00,0x0A,0x81,0x03,0x03,
+0xC0,0xFC,0xA6,0x1A,0x0F,0xC3,0x0D,0x58,0x19,0x86,
+0x3F,0xC1,0xE0,0x0A,0x81,0x03,0x03,0xC1,0xFC,0x30,
+0xCC,0x0A,0x70,0x37,0x0E,0x7F,0xC7,0x9C,0x00,0x6C,
+0x19,0xC7,0x1F,0xC1,0xF0,0x02,0x62,0x01,0xA3,0xD0,
+0x46,0x02,0x7A,0xE9,0xA3,0xD0,0x47,0x0A,0x0B,0x59,
+0x13,0x40,0x04,0x01,0xC0,0xF8,0x3C,0x0F,0x01,0x80,
+0x0F,0x00,0x3C,0x00,0xF8,0x01,0xC0,0x04,0x0B,0x39,
+0x23,0x63,0xFF,0xC8,0x00,0x8F,0xFE,0x0B,0x59,0x13,
+0x50,0x01,0xC0,0x0F,0x80,0x1E,0x00,0x78,0x00,0xC0,
+0x78,0x1E,0x0F,0x81,0xC0,0x10,0x00,0x0A,0x81,0x03,
+0x07,0xE1,0xFE,0x70,0xEC,0x0C,0x01,0x80,0x70,0x1C,
+0x07,0x00,0xC4,0x86,0x10,0x00,0x40,0x60,0x14,0xA9,
+0xDD,0x80,0x3F,0x00,0x07,0xFE,0x00,0xF0,0x3C,0x06,
+0x00,0x60,0x63,0x99,0x87,0x7E,0xCE,0x37,0x1C,0x31,
+0xB0,0x61,0x9B,0x83,0x0D,0x1B,0x03,0x0C,0xD8,0x30,
+0xC6,0xC1,0x8E,0x37,0x1C,0xE1,0xDF,0xFE,0x06,0x71,
+0xC0,0x38,0x00,0x18,0xE0,0x03,0x83,0xC0,0x78,0x0F,
+0xFF,0x80,0x0F,0xE0,0x00,0x0F,0x80,0x03,0xE0,0x0E,
+0x04,0x03,0x60,0x07,0x70,0x80,0xC6,0x10,0x30,0x62,
+0x0F,0xFE,0x0C,0x06,0x43,0x00,0x68,0xC0,0x06,0x0C,
+0x82,0x03,0xDF,0xF0,0xFF,0xC6,0x07,0x4E,0x03,0x30,
+0x32,0x3F,0xF1,0x80,0xD3,0x80,0x6C,0x07,0x7F,0xF3,
+0xFE,0x00,0x0E,0x81,0x04,0x00,0xF8,0x07,0xFC,0x1C,
+0x1C,0x60,0x18,0xC0,0x1E,0x60,0x00,0x60,0x0C,0xC0,
+0x30,0xE0,0xE0,0xFF,0x80,0xFC,0x00,0x0D,0x82,0x04,
+0x1F,0xF0,0x7F,0xF1,0x80,0xE6,0x01,0x98,0x07,0xCC,
+0x01,0xC6,0x01,0x98,0x1C,0x7F,0xF1,0xFF,0x00,0x0C,
+0x82,0x03,0xE3,0xFF,0xEF,0x00,0x23,0xFF,0xAF,0x00,
+0x23,0xFF,0xC0,0x0A,0x82,0x03,0x63,0xFF,0xBC,0x02,
+0x3F,0xED,0xC0,0x00,0x0F,0x81,0x04,0x40,0xFC,0x03,
+0xFF,0x07,0x03,0x8E,0x01,0x8C,0x00,0xE7,0x00,0x04,
+0x60,0x7F,0x60,0x03,0x30,0x03,0x38,0x03,0x1C,0x0F,
+0x0F,0xFE,0x03,0xF0,0x0C,0x82,0x04,0x37,0x00,0xE3,
+0xFF,0xF7,0x00,0xC0,0x02,0x82,0x01,0xB7,0xDE,0x30,
+0x08,0x81,0x02,0xF4,0x0E,0x80,0xE3,0x0D,0xCE,0x7E,
+0x1E,0x00,0x0D,0x82,0x03,0xD8,0x0E,0x60,0x71,0x83,
+0x86,0x1C,0x18,0xE0,0x67,0x01,0xB8,0x07,0xE0,0x1F,
+0xC0,0x73,0x81,0x87,0x06,0x0E,0x18,0x18,0x60,0x71,
+0x80,0xE6,0x01,0xC0,0x09,0x82,0x03,0x37,0x01,0xB8,
+0x08,0xFF,0x80,0x0F,0x82,0x04,0xDC,0x01,0xE7,0xC0,
+0x7C,0xEC,0x1B,0x9C,0xC6,0x73,0x8D,0x8E,0x70,0xE1,
+0x80,0x0C,0x82,0x04,0x18,0x06,0xE0,0x38,0xF0,0x38,
+0xD8,0x36,0x61,0xC6,0x31,0xB0,0xCE,0x30,0x6E,0x30,
+0x3D,0x80,0xEC,0x03,0x0F,0x81,0x04,0x40,0xF8,0x03,
+0xFE,0x07,0x07,0x0E,0x03,0x8C,0x01,0xB3,0x00,0x19,
+0x80,0x31,0xC0,0x70,0xE0,0xE0,0x7F,0xC0,0x1F,0x00,
+0x0C,0x82,0x03,0xDF,0xF0,0xFF,0xE6,0x03,0x56,0x01,
+0xB0,0x19,0xFF,0xCF,0xF8,0xCC,0x00,0x0F,0x89,0xFC,
+0x40,0xF8,0x03,0xFE,0x07,0x07,0x0E,0x03,0x8C,0x01,
+0xB3,0x00,0x19,0x80,0x31,0xC3,0xB0,0xE0,0xE0,0x7F,
+0xE0,0x1F,0xB8,0x00,0x08,0x0C,0x82,0x04,0x1F,0xF8,
+0xFF,0xE6,0x03,0xCE,0x01,0xB0,0x1D,0xFF,0xCF,0xFC,
+0x61,0x83,0x06,0x18,0x38,0xC0,0xE6,0x03,0x30,0x1D,
+0x80,0x60,0x0D,0x81,0x03,0xC1,0xF8,0x1F,0xF0,0xE0,
+0xE8,0x60,0x19,0xC0,0x03,0xC0,0x07,0xF0,0x03,0xF0,
+0x00,0xF1,0x80,0x33,0x00,0xCE,0x0E,0x1F,0xF8,0x1F,
+0x80,0x0C,0x81,0x03,0xA3,0xFF,0xF4,0x18,0x34,0x18,
+0x00,0x0C,0x82,0x04,0x37,0x00,0xEF,0x00,0xDC,0x0E,
+0x70,0xE1,0xFE,0x07,0xE0,0x0F,0x80,0x03,0xD8,0x00,
+0xDC,0x01,0xE1,0x80,0x34,0x18,0x0C,0x1C,0x1C,0x81,
+0x83,0x12,0x18,0xC2,0x01,0xB0,0x01,0xF0,0x00,0xE0,
+0x00,0x15,0x80,0x05,0x63,0x01,0xC0,0x74,0xC1,0xB0,
+0x6A,0x31,0x8C,0x65,0x0D,0x83,0x62,0x03,0x80,0xE0,
+0x0F,0x80,0x03,0xCE,0x03,0x87,0x07,0x03,0x06,0x01,
+0x8C,0x01,0xDC,0x00,0xD8,0x24,0x0E,0x00,0x1B,0x00,
+0x31,0x80,0x71,0xC0,0x60,0xC0,0xC0,0x61,0xC0,0x73,
+0x80,0x38,0x0E,0x80,0x03,0x9C,0x03,0x98,0x06,0x18,
+0x18,0x38,0x70,0x30,0xC0,0x33,0x00,0x7E,0x00,0x78,
+0x34,0x0C,0x00,0x18,0x00,0x0C,0x80,0x03,0x61,0xFF,
+0xC0,0x0D,0x00,0x18,0x01,0x80,0x18,0x40,0x30,0x03,
+0x00,0x30,0x10,0x60,0x06,0x00,0x8F,0xFF,0x04,0xA1,
+0xE1,0xA3,0xF7,0x37,0x23,0x23,0xC0,0x07,0x80,0x01,
+0xA3,0x04,0xB0,0x93,0x12,0x32,0x43,0x03,0x81,0x80,
+0x04,0xA1,0xE1,0xA3,0xF4,0xF4,0xE0,0xE3,0xC0,0x0A,
+0x48,0x3A,0xC1,0x84,0x0F,0x12,0x66,0x43,0x0C,0xC0,
+0xC0,0x0C,0x10,0xE3,0x23,0xFF,0xC0,0x03,0x19,0x69,
+0xD8,0xC4,0x0A,0x61,0x03,0x07,0xC1,0xFC,0x8C,0x18,
+0x0F,0x1F,0xE3,0xCD,0x18,0x33,0x0E,0x3F,0xC7,0xCC,
+0x0A,0x81,0x03,0x2B,0x00,0x6F,0x0F,0xF9,0xC3,0x66,
+0x06,0xE1,0x9F,0xF3,0x78,0x09,0x61,0x02,0xC3,0xC3,
+0xF8,0xC7,0x60,0xEB,0x00,0xC1,0x98,0xE7,0xF0,0x78,
+0x0A,0x81,0x03,0x28,0x03,0x0F,0x67,0xFC,0xC3,0xE6,
+0x06,0xE1,0xCF,0xF8,0x7B,0x0A,0x61,0x03,0x03,0xC1,
+0xFE,0x30,0xCC,0x0E,0x3F,0xF8,0xC0,0x1C,0x19,0xC6,
+0x1F,0xC1,0xE0,0x07,0x80,0x01,0xC3,0xC7,0xE0,0xC4,
+0x7E,0xD3,0x12,0x60,0x0A,0x81,0xE3,0x03,0xD9,0xFF,
+0x30,0xEE,0x0E,0xB0,0x36,0x0E,0x61,0xCF,0xF8,0x7B,
+0x00,0x6C,0x19,0xFF,0x0F,0x80,0x09,0x81,0x02,0xEB,
+0x00,0xDE,0x3F,0xCE,0x3E,0xE0,0xE3,0x06,0x02,0x81,
+0x01,0x63,0x83,0x7B,0xC0,0x04,0xA7,0xE1,0x20,0xE0,
+0x34,0xF4,0xDE,0xE0,0x09,0x81,0x02,0xAB,0x00,0xC3,
+0xB1,0xCC,0xE3,0x70,0xF8,0x3F,0x0E,0xC3,0x38,0xC6,
+0x31,0xCC,0x33,0x0E,0x02,0x81,0x01,0x37,0xDE,0x30,
+0x10,0x61,0x04,0x9B,0xC7,0x8F,0xF7,0xE7,0x1E,0x3E,
+0xE0,0xC1,0xC6,0x0C,0x18,0x09,0x61,0x02,0xDB,0xC7,
+0xF9,0xC7,0xDC,0x1C,0x60,0xC0,0x0B,0x61,0x03,0x43,
+0xE0,0x7F,0x0E,0x39,0xC1,0xEB,0x01,0xB8,0x39,0xC7,
+0x0F,0xE0,0x7C,0x00,0x0A,0x81,0xE3,0x1B,0xC3,0xFE,
+0x70,0xD9,0x81,0xB8,0x67,0xF8,0xDE,0x2B,0x00,0x0A,
+0x81,0xE3,0x03,0xD9,0xFF,0x30,0xF9,0x81,0x98,0x73,
+0xFE,0x1E,0xE8,0x03,0x06,0x61,0x01,0xDB,0xBF,0x71,
+0xB8,0x46,0x00,0x09,0x61,0x02,0xC7,0xC3,0xF9,0x83,
+0x60,0x1E,0x03,0xF0,0x3F,0x01,0xC0,0x36,0x1C,0xFE,
+0x1F,0x00,0x05,0x80,0x01,0x84,0x96,0x47,0xF5,0x86,
+0x1E,0x38,0x09,0x61,0x02,0xF7,0x07,0x18,0x37,0x1C,
+0xFF,0x1E,0xC0,0x0B,0x60,0x02,0xE3,0x01,0xC3,0x06,
+0x93,0x19,0x03,0x62,0x03,0x80,0x10,0x00,0x0F,0x60,
+0x03,0xD8,0x20,0xE3,0x0E,0x19,0x8A,0x31,0x9B,0x30,
+0x9B,0x24,0x1B,0x6C,0x0A,0x28,0x81,0xC7,0x00,0xC6,
+0x00,0x0A,0x60,0x02,0x9C,0x39,0x86,0x83,0x30,0x3C,
+0x40,0x60,0x1E,0x20,0xCC,0x30,0xCE,0x1C,0x0B,0x80,
+0xE2,0xE3,0x01,0xC3,0x06,0x18,0x61,0x8C,0x81,0x99,
+0x01,0xE0,0x0E,0x00,0xC0,0x1C,0x01,0x80,0xF8,0x0F,
+0x00,0x0A,0x60,0x02,0xE1,0xFF,0x00,0xE0,0x38,0x0E,
+0x03,0x80,0xE0,0x38,0x0E,0x03,0x80,0x8F,0xFC,0x06,
+0xA0,0xE1,0xC3,0x8F,0xC3,0x0C,0x47,0x06,0x30,0xC1,
+0xE1,0xC0,0x02,0xAA,0xD9,0xB7,0xDF,0x70,0x06,0xA1,
+0xE1,0xDC,0x3C,0xC3,0x07,0x40,0xE3,0xB0,0xC7,0x8E,
+0x00,0x0B,0x21,0x33,0x4F,0x01,0xFC,0x51,0xFC,0x07,
+0x80,};
+/* font data size: 1551 bytes */
+
+static const unsigned char Arial_16_index[] = {
+0x00,0x00,0x10,0x05,0x81,0x00,0x46,0x0F,0xC3,
+0x18,0x80,0x10,0x82,0x48,0x50,0x0A,0xA1,0x66,0x2E,
+0x45,0xF0,0xC2,0x19,0xE3,0x7C,0x75,0x10,0x02,0x2E,
+0x4A,0x89,0xE9,0x52,0x2C,0x85,0xD4,0xC5,0x99,0x13,
+0x30,0x6B,0x0D,0xA9,0xC9,0x3B,0xC8,0x5D,0x17,0xA4,
+0x64,0xBE,0x9D,0x54,0x1A,0x8E,0x55,0x8A,0xD9,0x5E,
+0x2C,0x85,0xD0,0xBC,0x58,0x1B,0x1A,0x66,0x8D,0x15,
+0xB0,0xB7,0xC7,0x32,0xE8,0xDD,0x8B,0xCB,0x7B,0xCF,
+0xFA,0x0A,0xC2,0xC8,0x6B,0x10,0xA2,0x5C,0x57,0x8B,
+0xB1,0x8A,0x3A,0x48,0x39,0x25,0x28,0x65,0x9C,0xBE,
+0x9A,0x93,0x82,0x73,0xCF,0x0A,0x09,0x42,0xA8,0xCD,
+0x24,0xA6,0xD5,0x16,0xAA,0x55,0xDA,0xE1,0x5E,0xAC,
+0x2D,0x94,0xB5,0x76,0xF2,0xE9,0xDE,0x5B,0xE5,0x7E,
+0x30,0x28,
+};
+/* font index size: 131 bytes */
+
+const ILI9341_t3_font_t Arial_16 = {
+       Arial_16_index,
+       0,
+       Arial_16_data,
+       1,
+       0,
+       32,
+       126,
+       0,
+       0,
+       11,
+       5,
+       5,
+       3,
+       5,
+       5,
+       23,
+       16
+};
+
+
+
+static const unsigned char Arial_18_data[] = {
+0x00,0x00,0x01,0xC0,0x02,0x93,0x02,0x37,0xDE,0x08,
+0xC0,0x07,0x31,0x62,0x73,0x18,0x0E,0x90,0x03,0xA0,
+0x18,0x60,0x71,0x90,0x18,0x64,0x7F,0xFF,0x43,0x0C,
+0x47,0xFF,0xF0,0x61,0x80,0xC7,0x08,0x61,0x80,0x0B,
+0xA9,0xF3,0x80,0x80,0x3E,0x0F,0xF8,0xC9,0x98,0x8E,
+0x31,0x03,0x90,0x1F,0x00,0xFC,0x01,0xF0,0x13,0x40,
+0x23,0x62,0x37,0x27,0x32,0xE3,0xFE,0x0F,0x88,0x04,
+0x00,0x13,0x91,0x05,0x87,0x80,0xC0,0xFC,0x1C,0x1C,
+0xE1,0x81,0x86,0x38,0x18,0x63,0x01,0x86,0x70,0x18,
+0x66,0x01,0xCE,0xE0,0x0F,0xCC,0xF0,0x79,0x9F,0x80,
+0x1B,0x9E,0x00,0x66,0x1C,0x01,0x8C,0x30,0x30,0xE7,
+0x03,0x07,0xE0,0x60,0x3C,0x0F,0x91,0x04,0x41,0xF0,
+0x03,0xF8,0x07,0x1C,0x20,0xC1,0x80,0xE3,0x80,0x77,
+0x00,0x3E,0x00,0x78,0x00,0xEC,0x01,0x86,0x33,0x07,
+0x73,0x03,0xE3,0x01,0xC3,0x81,0xE1,0xC3,0xF0,0xFF,
+0x78,0x7C,0x30,0x02,0x31,0x61,0x73,0x06,0xBA,0xDA,
+0x01,0x86,0x83,0x25,0x8D,0xC2,0x30,0x96,0x20,0xC0,
+0xC0,0xC0,0x06,0xB8,0xDA,0x18,0x18,0x83,0x24,0x6D,
+0x0C,0x18,0x78,0x18,0x74,0x18,0x61,0x80,0x08,0x41,
+0x52,0xA0,0x61,0x36,0xFF,0x83,0xC3,0x30,0x90,0x0C,
+0x61,0x1B,0xEC,0x18,0x23,0xFF,0xEC,0x18,0x00,0x02,
+0x32,0xE1,0xE3,0x85,0xA0,0x06,0x11,0x2A,0x23,0xF0,
+0x02,0x12,0x01,0xE3,0x07,0x90,0x01,0xE0,0x1C,0x86,
+0x0E,0x91,0x94,0x62,0x58,0x46,0x00,0x0C,0x91,0x03,
+0x83,0xF0,0x3F,0xC3,0x87,0x18,0x1B,0x70,0x0E,0x70,
+0x0C,0xC0,0xC7,0x0E,0x1F,0xE0,0x7E,0x00,0x07,0x92,
+0x03,0xA0,0x18,0x78,0xFB,0xDB,0x9E,0x83,0xB0,0x60,
+0x0C,0x91,0x03,0x83,0xF0,0x3F,0xC3,0x87,0x30,0x1D,
+0x80,0x70,0x00,0x70,0x00,0xC0,0x0C,0x00,0xC0,0x0C,
+0x01,0xC0,0x1C,0x01,0x80,0x18,0x02,0x3F,0xFC,0x0C,
+0x91,0x03,0x83,0xE0,0x3F,0xC3,0x86,0x38,0x19,0x80,
+0xC0,0x06,0x00,0xE0,0x3E,0x01,0xF8,0x00,0x60,0x03,
+0xC0,0x01,0xB0,0x0D,0xC0,0xE6,0x0E,0x1F,0xE0,0x7C,
+0x00,0x0C,0x91,0x03,0x80,0x18,0x01,0xC8,0x03,0xC0,
+0x36,0x03,0xB0,0x19,0x81,0x8C,0x1C,0x60,0xC3,0x0C,
+0x18,0xE0,0xC8,0xFF,0xFA,0x00,0xC0,0x0C,0x91,0x03,
+0xA0,0xFF,0x8E,0x01,0x2C,0x00,0x6F,0x87,0xFE,0x38,
+0x38,0x00,0xF2,0x00,0x6C,0x03,0x60,0x31,0x83,0x87,
+0xF8,0x1F,0x00,0x0C,0x91,0x03,0x81,0xF0,0x3F,0xC1,
+0x87,0x18,0x1C,0xC0,0x6C,0x00,0x67,0xC3,0x7F,0x1E,
+0x1C,0xE0,0x7A,0xC0,0x33,0x03,0x1C,0x38,0x7F,0x80,
+0xF8,0x0C,0x91,0x03,0xA3,0xFF,0xC0,0x0D,0x00,0x19,
+0x00,0x31,0x00,0x61,0x00,0xC1,0x21,0x81,0x43,0x00,
+0x0C,0x91,0x03,0x81,0xE0,0x3F,0xC3,0x86,0x4B,0x03,
+0x0C,0x30,0x3F,0x03,0xFC,0x38,0x73,0x81,0xE7,0x00,
+0xD8,0x0E,0x70,0x61,0xFE,0x07,0xE0,0x0C,0x91,0x03,
+0x83,0xE0,0x3F,0xC3,0x87,0x38,0x1A,0xB0,0x0D,0xC0,
+0xE7,0x0F,0x1F,0xD8,0x7C,0xC0,0x07,0x18,0x0C,0x60,
+0xC3,0xFC,0x07,0xC0,0x02,0x6A,0x01,0xE3,0xD2,0x08,
+0xC0,0x02,0x8A,0xE1,0xE3,0xD2,0x08,0xE1,0x68,0x0C,
+0x59,0x1B,0xC0,0x02,0x00,0xF0,0x1F,0x03,0xC0,0xF0,
+0x0C,0x00,0x3C,0x00,0x3C,0x00,0x7C,0x00,0xF0,0x00,
+0x80,0x0C,0x41,0x2B,0xE3,0xFF,0xE8,0x00,0x23,0xFF,
+0xC0,0x0C,0x59,0x1B,0xD0,0x00,0xF0,0x03,0xE0,0x03,
+0xC0,0x03,0xC0,0x03,0x00,0xF0,0x3C,0x0F,0x80,0xF0,
+0x04,0x00,0x00,0x0C,0x91,0x03,0x83,0xF0,0x3F,0xC3,
+0x87,0x38,0x1D,0x80,0x60,0x03,0x00,0x38,0x03,0x80,
+0x38,0x03,0x80,0x18,0x48,0x30,0x40,0x00,0x40,0x30,
+0x00,0x17,0xB9,0xDE,0x40,0x1F,0xC0,0x00,0x7F,0xF8,
+0x01,0xF0,0x3C,0x03,0x80,0x0E,0x07,0x00,0x07,0x06,
+0x0F,0x33,0x0C,0x3F,0xB3,0x8C,0x70,0xF1,0x8C,0xE0,
+0x61,0x98,0xC0,0x61,0xA3,0x30,0x0C,0x33,0x30,0x0C,
+0x63,0x30,0x18,0x63,0x30,0x38,0xE3,0x98,0x79,0xC1,
+0x9F,0xFF,0x81,0xC7,0x8E,0x18,0xE0,0x00,0x30,0x70,
+0x00,0xE0,0x3C,0x03,0xC0,0x1F,0xFF,0x80,0x03,0xFC,
+0x00,0x0F,0x91,0x04,0x60,0x0E,0x04,0x83,0x60,0x80,
+0xC6,0x01,0xC7,0x10,0x30,0x62,0x0F,0xFE,0x0C,0x06,
+0x1C,0x03,0x43,0x00,0x68,0xC0,0x06,0x0E,0x92,0x04,
+0x5F,0xF8,0x3F,0xFC,0x60,0x19,0x58,0x03,0x30,0x0C,
+0x7F,0xF0,0xFF,0xF1,0x80,0x73,0x00,0x79,0xC0,0x0D,
+0x80,0x73,0xFF,0xE7,0xFF,0x00,0x10,0x91,0x04,0x80,
+0x7E,0x01,0xFF,0xC1,0xE0,0x71,0xC0,0x18,0xC0,0x0E,
+0xE0,0x00,0xCC,0x00,0x03,0x00,0x19,0x80,0x1C,0xE0,
+0x1C,0x3C,0x1C,0x0F,0xFC,0x01,0xF8,0x00,0x0F,0x92,
+0x04,0x9F,0xF8,0x1F,0xFE,0x18,0x07,0x18,0x03,0x98,
+0x01,0x98,0x01,0xF3,0x00,0x1B,0x00,0x3B,0x00,0x33,
+0x00,0x73,0x00,0xE3,0xFF,0xC3,0xFF,0x00,0x0E,0x92,
+0x04,0x63,0xFF,0xFC,0xC0,0x02,0x3F,0xFE,0xCC,0x00,
+0x23,0xFF,0xF0,0x0C,0x92,0x03,0xE3,0xFF,0xF3,0x00,
+0x23,0xFF,0xB7,0x00,0x18,0x00,0x10,0x91,0x04,0xC0,
+0x7E,0x01,0xFF,0xC1,0xE0,0xF0,0xC0,0x18,0xC0,0x0E,
+0x60,0x02,0x9C,0x00,0x08,0xC0,0x7F,0x60,0x01,0xC3,
+0x00,0x18,0xC0,0x0C,0x78,0x3E,0x1F,0xFC,0x01,0xF8,
+0x00,0x0E,0x92,0x04,0xB7,0x00,0x36,0x00,0x71,0xFF,
+0xFE,0xE0,0x06,0xC0,0x0C,0x02,0x92,0x01,0xB7,0xDE,
+0xB0,0x0A,0x91,0x03,0x74,0x03,0xB0,0x0E,0x70,0x33,
+0x0C,0x7F,0x87,0xC0,0x0F,0x92,0x04,0x58,0x03,0x98,
+0x07,0x18,0x0E,0x18,0x1C,0x18,0x38,0x18,0x70,0x18,
+0xE0,0x19,0xC0,0x1B,0xE0,0x1F,0xE0,0x1E,0x70,0x1C,
+0x38,0x18,0x1C,0x23,0x01,0xC3,0x00,0xE3,0x00,0x73,
+0x00,0x38,0x0B,0x92,0x03,0xB7,0x00,0x6E,0x00,0x8C,
+0x01,0x1F,0xFC,0x11,0x92,0x05,0x5C,0x00,0x78,0xF0,
+0x07,0xCE,0xC0,0x6E,0x73,0x06,0x73,0x8C,0x63,0x9C,
+0x36,0x1C,0xE0,0xE0,0xC0,0x0E,0x92,0x04,0xA3,0x80,
+0x38,0xF0,0x0D,0xB0,0x1C,0x66,0x06,0xC6,0x0E,0x30,
+0xC3,0x60,0xC7,0x18,0x19,0xB0,0x1B,0x8C,0x03,0xE3,
+0x00,0x70,0x11,0x91,0x04,0xC0,0x7C,0x00,0xFF,0xC0,
+0x78,0x3C,0x18,0x03,0x21,0x80,0x0D,0x98,0x00,0x38,
+0x60,0x03,0x0C,0x01,0x83,0xC1,0xE0,0x7F,0xF0,0x03,
+0xE0,0x00,0x0E,0x92,0x04,0x5F,0xFC,0x3F,0xFC,0x60,
+0x1C,0xC0,0x1E,0x70,0x03,0x60,0x0E,0xC0,0x39,0xFF,
+0xE3,0xFF,0x8D,0xC0,0x00,0x11,0x99,0xFC,0xC0,0x7C,
+0x00,0xFF,0xC0,0x78,0x3C,0x18,0x03,0x21,0x80,0x0D,
+0x98,0x00,0x33,0x00,0x1C,0xC0,0xC6,0x18,0x3F,0x87,
+0x83,0xC0,0x7F,0xF8,0x07,0xEF,0x00,0x00,0xC0,0x0F,
+0x92,0x04,0x9F,0xFC,0x1F,0xFF,0x18,0x07,0x27,0x00,
+0x33,0x00,0x73,0x00,0xE3,0xFF,0xE3,0xFF,0x83,0x07,
+0x03,0x03,0x03,0x03,0x83,0x01,0xC4,0x60,0x1C,0x60,
+0x0E,0x60,0x07,0x0F,0x91,0x04,0x40,0xFC,0x03,0xFF,
+0x07,0x03,0x8C,0x01,0xCC,0x00,0xCC,0x00,0x0E,0x00,
+0x07,0xE0,0x03,0xFE,0x00,0x7F,0x80,0x03,0x80,0x00,
+0xE3,0x00,0x19,0x80,0x39,0xE0,0x70,0xFF,0xE0,0x3F,
+0x80,0x0E,0x90,0x03,0xA3,0xFF,0xFD,0x03,0x03,0x40,
+0xC0,0x80,0x30,0x00,0x0E,0x92,0x04,0xB7,0x00,0x3D,
+0xC0,0x0C,0xC0,0x31,0xC0,0xE1,0xFF,0x80,0xFC,0x00,
+0x0F,0x91,0x04,0x58,0x00,0xDC,0x01,0xE1,0x80,0x31,
+0xC0,0x74,0x18,0x0C,0x91,0x83,0x10,0x18,0xC0,0x1D,
+0xC2,0x01,0xB0,0x01,0xF0,0x40,0x1C,0x00,0x19,0x90,
+0x06,0x98,0x03,0x80,0x36,0x00,0xE0,0x1E,0x58,0x0D,
+0x80,0xC3,0x07,0x70,0x64,0x18,0x31,0x83,0x06,0x0C,
+0x61,0xC9,0x18,0xC1,0x8C,0x48,0x6C,0x06,0xC0,0x1F,
+0x01,0xF0,0x80,0x70,0x07,0x00,0x11,0x90,0x04,0x4E,
+0x00,0xE1,0xC0,0x70,0x38,0x38,0x06,0x0C,0x01,0xC7,
+0x00,0x3B,0x80,0x06,0xC0,0x80,0x1C,0x00,0x0F,0x80,
+0x03,0x60,0x01,0xDC,0x00,0xE3,0x80,0x70,0x70,0x18,
+0x0C,0x0E,0x03,0x87,0x00,0x73,0x80,0x0E,0x10,0x90,
+0x04,0x18,0x00,0xE6,0x00,0xE1,0x80,0x60,0xE0,0x70,
+0x38,0x70,0x0C,0x30,0x07,0x38,0x01,0x98,0x20,0x0F,
+0x03,0x40,0x60,0x00,0x30,0x00,0x0E,0x90,0x03,0xE1,
+0xFF,0xF0,0x00,0xC0,0x03,0x80,0x0E,0x00,0x38,0x00,
+0x60,0x01,0xC0,0x07,0x00,0x1C,0x00,0x30,0x00,0xE0,
+0x03,0x80,0x0E,0x00,0x18,0x00,0x60,0x02,0x3F,0xFF,
+0x05,0xBA,0xD9,0xE3,0xFB,0x8D,0xC5,0xE2,0x3E,0x07,
+0x90,0x01,0xE3,0x04,0xB0,0x38,0x93,0x14,0x32,0x43,
+0x40,0x30,0x05,0xB8,0xD9,0xE3,0xFA,0x3D,0x1D,0x8E,
+0x3E,0x0A,0x51,0x43,0x01,0x84,0x0F,0x12,0x66,0x4B,
+0x0C,0xC0,0xC0,0x0F,0x17,0xDB,0xA3,0xFF,0xF8,0x04,
+0x19,0x7A,0x1C,0x61,0x80,0x0C,0x69,0x03,0x83,0xF0,
+0x7F,0xC7,0x07,0x30,0x18,0x00,0xC0,0x3E,0x1F,0xF1,
+0xF1,0x98,0x0C,0xC0,0xE7,0x0F,0x1F,0xD8,0x7C,0x60,
+0x0B,0x92,0x03,0xAF,0x00,0x33,0xC3,0x7E,0x3C,0x73,
+0x83,0x5E,0x03,0x70,0x67,0x8E,0x6F,0xC6,0x78,0x0B,
+0x69,0x03,0x43,0xF0,0x7F,0x8E,0x1D,0xC0,0xEB,0x00,
+0x30,0x1B,0x83,0x9C,0x30,0xFE,0x07,0xC0,0x0B,0x91,
+0x03,0xAC,0x01,0x87,0x98,0xFD,0x9C,0x79,0x83,0xDE,
+0x03,0x30,0x73,0x8F,0x1F,0xB0,0xF3,0x0C,0x69,0x03,
+0x83,0xF0,0x3F,0xC3,0x87,0x18,0x19,0x80,0x71,0xFF,
+0xF1,0x80,0x0E,0x03,0x38,0x30,0xFF,0x03,0xF0,0x07,
+0x90,0x01,0xC3,0xC7,0xE4,0xC4,0x7F,0xD3,0x14,0x60,
+0x0B,0x91,0xDB,0x83,0xCC,0x7E,0xCE,0x3C,0xC1,0xEF,
+0x01,0x98,0x39,0xC7,0x8F,0xD8,0x79,0x80,0x1B,0x03,
+0xB8,0x71,0xFF,0x0F,0xC0,0x0A,0x92,0x03,0xAF,0x00,
+0x67,0x8D,0xF9,0xE3,0xB8,0x3D,0xC0,0xE3,0x03,0x02,
+0x92,0x01,0xA3,0x93,0x7C,0xC0,0x05,0xBF,0xD9,0xA0,
+0x72,0x0D,0x1E,0x8E,0x06,0xFB,0xC0,0x0B,0x92,0x03,
+0x6F,0x00,0x30,0x73,0x0E,0x31,0xC3,0x38,0x37,0x03,
+0xE0,0x3F,0x03,0x38,0x31,0xC3,0x0C,0x30,0x63,0x07,
+0x30,0x38,0x02,0x92,0x01,0xB7,0xDE,0xB0,0x12,0x6A,
+0x05,0x99,0xE1,0xE3,0x7E,0xFE,0x78,0xF8,0xEE,0x0E,
+0x0F,0x70,0x30,0x38,0xC0,0xC0,0xC0,0x0A,0x6A,0x03,
+0x99,0xE3,0x7E,0x78,0xEE,0x0F,0x70,0x38,0xC0,0xC0,
+0x0C,0x69,0x03,0x83,0xF0,0x3F,0xC3,0x87,0x38,0x1E,
+0xF0,0x0D,0xC0,0xE7,0x0E,0x1F,0xE0,0x7E,0x00,0x0B,
+0x92,0xDB,0x99,0xE1,0xBF,0x1E,0x39,0xC1,0xAF,0x01,
+0xB8,0x33,0xC7,0x37,0xE3,0x3C,0x5E,0x00,0x0B,0x91,
+0xDB,0x83,0xCC,0x7E,0xCE,0x3D,0xC1,0xEF,0x01,0x98,
+0x39,0xC7,0x8F,0xF8,0x79,0xD8,0x03,0x06,0x6A,0x02,
+0x1B,0xBF,0x71,0xB8,0x4E,0x00,0x0B,0x69,0x03,0x47,
+0xE0,0xFF,0x9C,0x19,0x80,0x1C,0x00,0xFC,0x07,0xF8,
+0x0F,0xC0,0x1D,0x80,0xDC,0x1C,0xFF,0x83,0xE0,0x07,
+0x88,0x09,0xE8,0xC4,0x7F,0xD3,0x10,0x60,0x7C,0x3C,
+0x0A,0x6A,0x03,0xB7,0x03,0x8C,0x0D,0x83,0xB8,0xF3,
+0xF6,0x3C,0xC0,0x0B,0x68,0x02,0xE3,0x01,0xCB,0x06,
+0x83,0x19,0x23,0x62,0x03,0x80,0x10,0x00,0x13,0x68,
+0x04,0xD8,0x08,0x0D,0x81,0xC0,0xCC,0x1C,0x1E,0x18,
+0x6C,0x30,0xC6,0xC6,0x0C,0xC6,0x60,0x6C,0x6E,0x06,
+0xC6,0xC0,0x68,0x2C,0x40,0x70,0x70,0x03,0x03,0x00,
+0x0B,0x68,0x02,0xDC,0x0C,0xC1,0x86,0x38,0x73,0x03,
+0x62,0x43,0x80,0x6C,0x0E,0xE0,0xC6,0x18,0x33,0x83,
+0x80,0x0B,0x91,0xDB,0x23,0x01,0xC3,0x06,0x30,0xC8,
+0x31,0x83,0x30,0x1B,0x10,0x3C,0x01,0xC2,0x43,0x00,
+0x60,0x1E,0x01,0xC0,0x00,0x0B,0x68,0x03,0x21,0xFF,
+0x80,0x30,0x06,0x00,0xC0,0x1C,0x03,0x80,0x70,0x0E,
+0x01,0xC0,0x18,0x04,0x7F,0xF0,0x08,0xB9,0xDA,0x00,
+0xE1,0xFD,0x18,0x18,0x47,0x00,0xC3,0x46,0x03,0x00,
+0xF0,0x38,0x02,0xBA,0xD9,0xB7,0xDF,0x78,0xC0,0x08,
+0xBF,0xDA,0x1C,0x0F,0x0D,0x18,0x06,0x40,0x38,0x33,
+0x46,0x03,0x0F,0x07,0x00,0x0D,0x21,0x3B,0xC7,0x80,
+0x7F,0x8D,0x8F,0xF0,0x0F,0x00,};
+/* font data size: 1886 bytes */
+
+static const unsigned char Arial_18_index[] = {
+0x00,0x00,0x10,0x05,
+0x81,0x00,0x4E,0x11,0xC3,0x98,0x99,0x13,0xA2,0xB0,
+0x5E,0x0C,0x71,0xA2,0x35,0xC6,0xE0,0xE0,0x1D,0xA4,
+0x08,0x87,0x12,0xB2,0x96,0x59,0x4B,0xF9,0x9B,0x35,
+0xC7,0x24,0xF2,0x1E,0xB3,0xE6,0x82,0x50,0x9A,0x29,
+0x48,0xAA,0x2D,0x52,0xAC,0x25,0xC4,0xC0,0x18,0x7B,
+0x1C,0x67,0xED,0x35,0xA9,0xB6,0x07,0x0C,0xE4,0x5D,
+0x3B,0xC2,0x7C,0x0F,0xDE,0x0C,0xC3,0xB8,0xC3,0x1B,
+0xA3,0xF4,0x9A,0x98,0x13,0xAA,0x83,0x52,0x8A,0x63,
+0x4F,0xAA,0x3D,0x53,0xAB,0x35,0x7E,0xBC,0x58,0xBB,
+0x3D,0x6C,0x6E,0x3D,0xD2,0xBD,0x77,0xE7,0x00,0x60,
+0xBC,0x49,0x8A,0xB1,0xEE,0x4A,0xCB,0xB9,0xC3,0x41,
+0xE8,0xCD,0x47,0xAB,0xB5,0xDE,0xCA,0xDD,0x5B,0xFF,
+0x8B,0xF2,0xCE,0x79,0xD0,0xFA,0x98,
+};
+/* font index size: 131 bytes */
+
+const ILI9341_t3_font_t Arial_18 = {
+       Arial_18_index,
+       0,
+       Arial_18_data,
+       1,
+       0,
+       32,
+       126,
+       0,
+       0,
+       11,
+       5,
+       5,
+       3,
+       5,
+       5,
+       27,
+       18
+};
+
+
+
+static const unsigned char Arial_20_data[] = {
+0x00,0x00,0x01,0x00,0x02,0xA3,0x01,0x1B,0xEF,0x1C,
+0x11,0x80,0x08,0x39,0x35,0x5B,0x86,0x0F,0xA0,0x02,
+0x10,0x0C,0x18,0x1C,0x3A,0x43,0x06,0x47,0xFF,0xFA,
+0x18,0x30,0x38,0x31,0x1F,0xFF,0xE0,0xC1,0x81,0xC3,
+0x84,0x30,0x60,0x0D,0xB9,0xFA,0x00,0x20,0x03,0xE0,
+0x3F,0xC1,0xCB,0x8E,0x27,0x30,0x8D,0x18,0x40,0x31,
+0x00,0xFC,0x00,0xFE,0x00,0x7C,0x01,0x3A,0x00,0x87,
+0x18,0x43,0x31,0x1C,0xE4,0xE1,0xFF,0x01,0xF0,0x80,
+0x20,0x00,0x15,0xA2,0x03,0x23,0xC0,0x18,0x1F,0x80,
+0xC0,0x66,0x03,0x04,0x61,0x83,0x02,0x30,0xC3,0x00,
+0xC3,0x18,0x03,0x98,0xE0,0x07,0xE3,0x1E,0x0F,0x18,
+0xFC,0x00,0x63,0x34,0x00,0x63,0x0C,0x03,0x0C,0x30,
+0x1C,0x30,0xC0,0x60,0xC3,0x03,0x83,0x98,0x0C,0x07,
+0xE0,0x60,0x0F,0x00,0x11,0xA1,0x02,0x60,0x78,0x00,
+0x7F,0x80,0x38,0x70,0x49,0x81,0x80,0x30,0xC0,0x06,
+0xF0,0x00,0xF0,0x00,0xF8,0x00,0x73,0x00,0x38,0xE1,
+0x9C,0x1C,0xE6,0x03,0x71,0x80,0x7C,0x60,0x0E,0x1C,
+0x07,0xC3,0x87,0xF8,0x7F,0xCF,0x07,0xC1,0x80,0x02,
+0x39,0x34,0xBB,0x80,0x06,0xD2,0xE9,0x20,0xE0,0x68,
+0x32,0x58,0xDC,0x27,0x09,0x62,0x0C,0x81,0x81,0x80,
+0x06,0xD1,0xE9,0x2C,0x21,0x88,0x32,0x46,0xD0,0xE0,
+0x30,0xF2,0x34,0x19,0x0C,0x30,0x0A,0x49,0x2D,0x70,
+0x18,0x13,0x27,0xFE,0x3F,0x03,0xC0,0xFC,0x39,0xC2,
+0x10,0x0E,0x71,0x0A,0x18,0x06,0x04,0x7F,0xFF,0x80,
+0x60,0x00,0x02,0x3A,0xED,0x11,0xCA,0xD0,0x07,0x11,
+0x19,0x31,0xFC,0x02,0x12,0x01,0x11,0x80,0x08,0xA0,
+0x01,0x10,0x07,0x20,0xD2,0x18,0x1C,0x91,0x89,0x30,
+0x96,0x07,0x03,0x00,0x0D,0xA1,0x02,0x00,0xF8,0x0F,
+0xF8,0x70,0x74,0x30,0x1B,0x70,0x07,0x38,0x03,0x86,
+0x03,0x1C,0x1C,0x3F,0xE0,0x3E,0x00,0x08,0xA2,0x02,
+0x10,0x06,0x0F,0x0F,0x9F,0xDE,0x6C,0x3D,0x03,0xC0,
+0x30,0x0D,0xA1,0x02,0x00,0xF8,0x0F,0xF8,0x70,0x71,
+0x80,0xF1,0x80,0x38,0x00,0x18,0x00,0xC0,0x07,0x00,
+0x18,0x00,0xC0,0x06,0x00,0x30,0x03,0x80,0x1C,0x00,
+0xE0,0x06,0x00,0x47,0xFF,0xC0,0x0D,0xA1,0x02,0x01,
+0xF8,0x0F,0xF0,0x70,0xE3,0x80,0xCC,0x03,0x00,0x0C,
+0x00,0x70,0x03,0x80,0x7C,0x01,0xF8,0x00,0x70,0x00,
+0xF0,0x00,0x38,0xC0,0x19,0x80,0xC7,0x07,0x0F,0xF8,
+0x0F,0x80,0x0E,0xA1,0x02,0x00,0x03,0x00,0x0E,0x00,
+0x3C,0x00,0xF8,0x01,0xB0,0x06,0x60,0x18,0xC0,0x71,
+0x81,0xC3,0x03,0x06,0x0C,0x0C,0x30,0x18,0xE0,0x32,
+0x3F,0xFF,0xB0,0x03,0x00,0x0D,0xA1,0x02,0x10,0x7F,
+0xE3,0x80,0x25,0x80,0x04,0xF8,0x3F,0xF8,0xF0,0x73,
+0x00,0xD4,0x00,0x38,0xC0,0x19,0x80,0xC7,0x06,0x0F,
+0xF8,0x0F,0x80,0x0D,0xA1,0x02,0x00,0x7C,0x07,0xF8,
+0x38,0x71,0xC0,0xE6,0x01,0x98,0x00,0xC0,0x03,0x1E,
+0x0D,0xFE,0x3C,0x1C,0xE0,0x35,0x60,0x0C,0xC0,0x33,
+0x01,0x86,0x0E,0x0F,0xF0,0x1F,0x00,0x0D,0xA1,0x02,
+0x11,0xFF,0xF0,0x00,0x80,0x04,0x00,0x30,0x01,0x80,
+0x04,0x00,0x30,0x80,0x30,0x48,0x30,0x24,0x30,0x14,
+0x30,0x00,0x0D,0xA1,0x02,0x00,0xF8,0x0F,0xF8,0x30,
+0x65,0x30,0x18,0x60,0xC0,0xFE,0x07,0xFC,0x38,0x38,
+0xC0,0x6A,0xC0,0x19,0x80,0xC7,0x07,0x0F,0xF8,0x0F,
+0x80,0x0D,0xA1,0x02,0x00,0xF8,0x0F,0xF8,0x70,0x71,
+0x80,0xCC,0x01,0x56,0x00,0xCC,0x07,0x38,0x3C,0x7F,
+0xB0,0x78,0xC0,0x03,0x00,0x19,0x80,0x67,0x01,0x8E,
+0x1C,0x1F,0xE0,0x3E,0x00,0x02,0x7B,0x01,0x11,0xE9,
+0x44,0x60,0x02,0xA3,0xED,0x11,0xE9,0x44,0x72,0xB4,
+0x0C,0x6A,0x0E,0x00,0x01,0x00,0x78,0x0F,0x81,0xF0,
+0x7C,0x07,0x80,0x30,0x01,0xE0,0x07,0xC0,0x07,0xC0,
+0x0F,0x80,0x1E,0x00,0x10,0x0D,0x41,0x1A,0x11,0xFF,
+0xFA,0x00,0x04,0x7F,0xFC,0x0C,0x6A,0x0E,0x08,0x00,
+0x78,0x01,0xF0,0x03,0xE0,0x03,0xE0,0x07,0x80,0x0C,
+0x01,0xE0,0x3E,0x0F,0x81,0xF0,0x1E,0x00,0x80,0x00,
+0x0E,0xA1,0x02,0x00,0xFC,0x07,0xFE,0x1E,0x0E,0x30,
+0x0E,0xE0,0x0D,0x80,0x18,0x00,0x30,0x00,0xE0,0x03,
+0x80,0x0E,0x00,0x38,0x00,0xE0,0x03,0x82,0x40,0xC0,
+0x80,0x00,0x20,0x0C,0x00,0x1A,0xD2,0xEB,0x80,0x07,
+0xF8,0x00,0x03,0xFF,0xE0,0x01,0xF0,0x1E,0x00,0x78,
+0x00,0xE0,0x1C,0x00,0x0E,0x07,0x07,0x8C,0xE0,0xC3,
+0xFD,0x8C,0x38,0xE1,0xF1,0xC6,0x18,0x1C,0x18,0xC6,
+0x01,0x83,0x30,0xC0,0x30,0x68,0xC6,0x00,0xC1,0x98,
+0xC0,0x18,0x73,0x18,0x06,0x0C,0x63,0x00,0xC3,0x8C,
+0x70,0x38,0x61,0xC7,0x1F,0x38,0x18,0x7F,0x7E,0x03,
+0x87,0xC7,0x80,0x30,0x00,0x00,0xC7,0x00,0x00,0x70,
+0x78,0x00,0x1C,0x03,0xE0,0x1F,0x00,0x3F,0xFF,0x80,
+0x00,0xFF,0x80,0x00,0x11,0xA1,0x02,0x70,0x03,0x80,
+0x80,0x36,0x00,0x1D,0xC1,0x00,0xC6,0x00,0x71,0xC2,
+0x03,0x06,0x10,0x30,0x18,0x0F,0xFE,0x07,0xFF,0xC1,
+0x80,0x30,0xE0,0x0E,0x86,0x00,0x34,0x60,0x00,0xC0,
+0x10,0xA2,0x02,0x6F,0xFE,0x07,0xFF,0xC3,0x00,0x71,
+0x80,0x1D,0x38,0x00,0xCC,0x00,0xE6,0x00,0xE3,0xFF,
+0xE1,0xFF,0xF8,0xC0,0x0E,0x60,0x03,0xCE,0x00,0x1B,
+0x00,0x1D,0x80,0x1C,0xFF,0xFC,0x7F,0xF8,0x00,0x12,
+0xA1,0x02,0x80,0x3F,0x80,0x1F,0xFC,0x07,0x81,0xC1,
+0xC0,0x1C,0x70,0x01,0xCC,0x00,0x1B,0x80,0x00,0xCC,
+0x00,0x01,0xC0,0x01,0x98,0x00,0x73,0x80,0x0C,0x38,
+0x03,0x83,0x81,0xE0,0x3F,0xF8,0x01,0xFC,0x00,0x11,
+0xA2,0x02,0x8F,0xFE,0x03,0xFF,0xE0,0xC0,0x1E,0x30,
+0x01,0x91,0x80,0x06,0xDC,0x00,0x1B,0x00,0x0F,0x18,
+0x00,0x66,0x00,0x31,0x80,0x3C,0x7F,0xFC,0x1F,0xFC,
+0x00,0x0F,0xA2,0x02,0x71,0xFF,0xFF,0x70,0x00,0x47,
+0xFF,0xED,0xC0,0x01,0x1F,0xFF,0xC0,0x0E,0xA2,0x02,
+0x31,0xFF,0xFE,0xE0,0x01,0x1F,0xFE,0x6E,0x00,0x11,
+0x80,0x00,0x13,0xA1,0x02,0xC0,0x1F,0xC0,0x0F,0xFF,
+0x01,0xE0,0x78,0x38,0x01,0xC7,0x00,0x0C,0x60,0x00,
+0x66,0x00,0x01,0x38,0x00,0x02,0x30,0x07,0xFB,0x00,
+0x01,0xB8,0x00,0x19,0x80,0x01,0x9C,0x00,0x18,0xE0,
+0x03,0x87,0x80,0xF0,0x3F,0xFE,0x00,0x7F,0x00,0x10,
+0xA2,0x02,0x9B,0x80,0x07,0x18,0x00,0x71,0xFF,0xFF,
+0xB8,0x00,0x71,0x80,0x06,0x02,0xA3,0x01,0x1B,0xEF,
+0x98,0x0B,0xA1,0x01,0xDA,0x00,0xF4,0x01,0xC6,0x03,
+0x70,0x33,0x06,0x3F,0xE0,0xF8,0x10,0xA2,0x02,0x6C,
+0x00,0xE6,0x00,0xE3,0x00,0xE1,0x80,0xE0,0xC0,0xE0,
+0x60,0xE0,0x30,0xE0,0x18,0xE0,0x0C,0xF0,0x06,0xFC,
+0x03,0xEE,0x01,0xE3,0x80,0xE0,0xE0,0x8C,0x07,0x06,
+0x01,0xC4,0x60,0x0E,0x30,0x03,0x98,0x00,0xE0,0x0D,
+0xA2,0x02,0x1B,0x80,0x0D,0xC0,0x05,0x60,0x02,0x3F,
+0xFE,0x11,0xA3,0x02,0xEE,0x00,0x3C,0xF8,0x03,0xE7,
+0x60,0x37,0x39,0x83,0x36,0x61,0xCE,0x71,0x8C,0x73,
+0x86,0xC3,0x60,0xF0,0xE3,0x07,0x06,0x10,0xA2,0x02,
+0x91,0xC0,0x06,0xF0,0x03,0x7C,0x01,0xB6,0x00,0xD9,
+0x80,0x71,0x8C,0x06,0xC3,0x03,0x8C,0x18,0x36,0x06,
+0x1C,0x60,0x31,0xB0,0x0C,0xD8,0x03,0x6C,0x01,0xF6,
+0x00,0x7C,0x60,0x03,0x80,0x14,0xA1,0x02,0xC0,0x1F,
+0x80,0x07,0xFF,0x80,0x78,0x1E,0x07,0x00,0x38,0x70,
+0x00,0xE3,0x00,0x03,0x38,0x00,0x1B,0x30,0x00,0x0E,
+0x18,0x00,0x18,0xE0,0x01,0xC3,0x80,0x1C,0x0F,0x03,
+0xC0,0x3F,0xFC,0x00,0x3F,0x00,0x10,0xA2,0x02,0x6F,
+0xFF,0x07,0xFF,0xE3,0x00,0x39,0x80,0x0F,0x58,0x00,
+0x6C,0x00,0x66,0x00,0x73,0xFF,0xF1,0xFF,0xE1,0xB8,
+0x00,0x0C,0x00,0x00,0x14,0xA9,0xFE,0xC0,0x1F,0x80,
+0x07,0xFF,0x80,0x78,0x1E,0x07,0x00,0x38,0x70,0x00,
+0xE8,0x60,0x00,0x6C,0xC0,0x00,0x33,0x00,0x03,0x98,
+0x00,0x18,0xE0,0x79,0xC3,0x81,0xFC,0x0F,0x03,0xE0,
+0x1F,0xFF,0x80,0x3F,0x8E,0x00,0x00,0x30,0x10,0xA2,
+0x02,0x8F,0xFF,0x87,0xFF,0xE3,0x00,0x39,0x80,0x0F,
+0x38,0x00,0x6C,0x00,0x76,0x00,0x73,0xFF,0xF1,0xFF,
+0xE0,0xC0,0xE0,0x60,0x30,0x30,0x0C,0x18,0x07,0x0C,
+0x01,0xC6,0x00,0x63,0x00,0x19,0x80,0x0E,0xC0,0x03,
+0x10,0xA1,0x02,0x60,0x7F,0x00,0xFF,0xE0,0xE0,0x78,
+0xE0,0x0D,0x0C,0x00,0x67,0x00,0x03,0xE0,0x00,0xFF,
+0x00,0x3F,0xF0,0x03,0xFE,0x00,0x0F,0x00,0x01,0xE3,
+0x00,0x0D,0xC0,0x06,0x70,0x06,0x1E,0x0F,0x07,0xFF,
+0x00,0xFE,0x00,0x10,0xA0,0x02,0x11,0xFF,0xFF,0xA0,
+0x30,0x1A,0x03,0x01,0x40,0x30,0x00,0x10,0xA2,0x02,
+0x9B,0x80,0x07,0xB8,0x00,0x6C,0x00,0x37,0x00,0x39,
+0x80,0x18,0xF0,0x38,0x3F,0xF8,0x03,0xF0,0x00,0x11,
+0xA1,0x02,0x6C,0x00,0x1B,0x80,0x0F,0x0C,0x00,0x69,
+0x30,0x06,0x40,0xC0,0x60,0x38,0x38,0x80,0xC1,0x84,
+0x03,0x18,0x00,0xCE,0x08,0x03,0x60,0x00,0xF8,0x10,
+0x03,0x80,0x1B,0xA0,0x03,0x91,0x80,0x1C,0x00,0xE5,
+0x80,0x6C,0x03,0x18,0x0C,0x60,0x34,0x18,0x18,0xC0,
+0xC1,0x83,0x86,0x0C,0x1C,0x30,0x61,0xC0,0xC3,0x06,
+0x18,0x0C,0x70,0x31,0x80,0xC6,0x03,0x18,0x0E,0x60,
+0x33,0x80,0x6E,0x03,0xB0,0x80,0xD8,0x03,0x60,0x07,
+0x80,0x3C,0x10,0x0E,0x00,0x38,0x00,0x13,0xA0,0x02,
+0x67,0x00,0x1C,0x38,0x03,0x81,0xC0,0x70,0x0C,0x06,
+0x00,0x60,0xC0,0x07,0x1C,0x00,0x3B,0x80,0x01,0xB0,
+0x10,0x01,0xC0,0x00,0x1E,0x00,0x03,0x60,0x00,0x63,
+0x00,0x0E,0x38,0x01,0xC1,0xC0,0x18,0x0C,0x03,0x00,
+0x60,0x70,0x07,0x0E,0x00,0x39,0xC0,0x01,0xC0,0x12,
+0xA0,0x02,0x4C,0x00,0x1C,0xC0,0x07,0x0C,0x00,0xC1,
+0xC0,0x38,0x1C,0x0E,0x01,0x83,0x80,0x18,0x70,0x03,
+0x9C,0x00,0x33,0x02,0x00,0x78,0x0D,0x00,0xC0,0x20,
+0x03,0x00,0x10,0xA0,0x02,0x30,0xFF,0xFC,0x00,0x0C,
+0x00,0x0C,0x00,0x0E,0x00,0x06,0x00,0x06,0x00,0x06,
+0x00,0x07,0x00,0x03,0x00,0x03,0x00,0x03,0x80,0x01,
+0x80,0x01,0x80,0x01,0x80,0x01,0xC0,0x00,0xC0,0x00,
+0xC0,0x01,0x1F,0xFF,0xE0,0x05,0xD2,0xE9,0x11,0xFD,
+0xC6,0xE3,0x70,0xC4,0x7C,0x08,0xA0,0x01,0x11,0x81,
+0x2C,0x12,0x60,0x38,0x91,0x89,0x0C,0x90,0x60,0x38,
+0x0C,0x05,0xD1,0xE9,0x11,0xFD,0x1E,0x8F,0x46,0x1C,
+0x7C,0x0C,0x59,0x25,0xC0,0x60,0x80,0xF0,0x81,0x98,
+0x93,0x0C,0x86,0x06,0x60,0x18,0x11,0x17,0xEA,0x11,
+0xFF,0xFF,0x05,0x21,0x41,0x2E,0x1C,0x30,0x60,0x0D,
+0x79,0x01,0xE1,0xFC,0x1F,0xF8,0x70,0x73,0x00,0xC0,
+0x03,0x00,0x3C,0x1F,0xF1,0xFC,0xC6,0x03,0x46,0x01,
+0x98,0x0E,0x70,0xF8,0xFF,0x61,0xF8,0xC0,0x0D,0xA2,
+0x02,0x17,0x80,0x06,0x7C,0x1B,0xFC,0x78,0x39,0xC0,
+0x66,0x01,0xEF,0x00,0x6C,0x03,0xB8,0x0C,0xF0,0xE3,
+0x7F,0x0C,0xF8,0x00,0x0C,0x79,0x01,0xC0,0xF8,0x1F,
+0xE1,0xC3,0x8C,0x0E,0xE0,0x3A,0xC0,0x08,0xC0,0x33,
+0x03,0x1C,0x38,0x7F,0x80,0xF8,0x0D,0xA1,0x02,0x16,
+0x00,0x30,0x7C,0xC7,0xFB,0x38,0x3C,0xC0,0x77,0x00,
+0xEF,0x00,0x6E,0x01,0x98,0x0E,0x70,0x78,0xFF,0x60,
+0xF9,0x80,0x0D,0x79,0x01,0xE0,0xF8,0x0F,0xF8,0x70,
+0x71,0x80,0xD1,0x80,0x38,0xFF,0xFC,0x60,0x01,0xC0,
+0x03,0x00,0xCF,0x0E,0x1F,0xF0,0x1F,0x80,0x08,0xA0,
+0x00,0xE1,0xF1,0xFC,0x98,0x47,0xF6,0x98,0x61,0x80,
+0x0D,0xA9,0xEA,0x00,0xF9,0x8F,0xFE,0x70,0x79,0x80,
+0xEE,0x01,0xDE,0x00,0xDC,0x03,0x30,0x1C,0xE0,0xF1,
+0xFF,0xC1,0xF3,0x00,0x0D,0x80,0x36,0x01,0x8E,0x0E,
+0x3F,0xF0,0x3F,0x00,0x0C,0xA2,0x02,0x17,0x80,0x0C,
+0xF8,0x7F,0xF3,0xC1,0x9C,0x07,0xB8,0x07,0x58,0x06,
+0x02,0xA2,0x00,0xD1,0xC9,0xBE,0xEC,0x05,0xD7,0xE8,
+0xD0,0x39,0x06,0x8F,0x47,0x63,0x79,0xC0,0x0C,0xA2,
+0x01,0xD7,0x80,0x0C,0x07,0x60,0x73,0x07,0x18,0x70,
+0xC7,0x06,0x70,0x47,0xF0,0x39,0xC2,0x30,0xE1,0x83,
+0x8C,0x0C,0x60,0x73,0x01,0xC0,0x02,0xA2,0x00,0xDB,
+0xEF,0x98,0x14,0x7A,0x03,0x0C,0xF8,0x7C,0x6F,0xEF,
+0xF3,0xC3,0xE1,0xDC,0x0E,0x07,0xB8,0x0C,0x07,0x58,
+0x0C,0x06,0x0C,0x7A,0x02,0x0C,0xF8,0x6F,0xF3,0xC1,
+0x9C,0x07,0xB8,0x07,0x58,0x06,0x0D,0x79,0x01,0xE0,
+0xF8,0x0F,0xF8,0x70,0x71,0x80,0xCE,0x03,0xDE,0x00,
+0xDC,0x07,0x30,0x18,0xE0,0xE1,0xFF,0x01,0xF0,0x0D,
+0xAA,0xEA,0x0C,0xF8,0x37,0xF8,0xF0,0x73,0x80,0xCC,
+0x03,0xDE,0x00,0xD8,0x07,0x70,0x19,0xE1,0xC6,0xFE,
+0x19,0xF0,0xCC,0x00,0x00,0x0D,0xA9,0xEA,0x00,0xF9,
+0x8F,0xF6,0x70,0x79,0x80,0xEE,0x01,0xDE,0x00,0xDC,
+0x03,0x30,0x1C,0x70,0xF0,0xFE,0xC1,0xF3,0xC0,0x01,
+0x80,0x07,0x7A,0x01,0x2D,0xEF,0xF1,0xC3,0x70,0x56,
+0x00,0x0C,0x79,0x01,0xC1,0xF0,0x3F,0xE3,0x83,0x98,
+0x0C,0xC0,0x07,0x80,0x1F,0xC0,0x7F,0x80,0x7E,0x00,
+0x3B,0x00,0xDC,0x06,0x70,0x61,0xFF,0x07,0xE0,0x07,
+0xA0,0x01,0x01,0x14,0x62,0x3F,0xE9,0x8A,0x30,0x3E,
+0x1E,0x0C,0x7A,0x02,0x1B,0x80,0x75,0x80,0x6C,0x07,
+0x30,0x79,0xFE,0xC3,0xE6,0x0D,0x78,0x01,0xB1,0x80,
+0x38,0x60,0x31,0xC1,0xC3,0x06,0x0E,0x39,0x03,0x18,
+0x0E,0xC2,0x03,0x61,0x00,0xE0,0x01,0x00,0x13,0x78,
+0x02,0x6C,0x06,0x07,0x18,0x1C,0x0C,0xC1,0x41,0x8C,
+0x36,0x18,0xC3,0x63,0x86,0x36,0x30,0x62,0x23,0x07,
+0x63,0x72,0x06,0xC6,0xC0,0x28,0x2C,0x40,0x70,0x70,
+0x02,0x02,0x00,0x0D,0x78,0x01,0xAE,0x01,0x98,0x0C,
+0x30,0x70,0xE3,0x81,0x8C,0x03,0x60,0x0F,0x80,0x1C,
+0x00,0xF8,0x03,0x60,0x1C,0xC0,0xE3,0x83,0x06,0x18,
+0x0C,0xE0,0x38,0x0D,0xA8,0xE9,0xAC,0x01,0xB0,0x0F,
+0x0C,0x06,0x30,0x30,0x60,0xC1,0x87,0x06,0x18,0x0C,
+0x62,0x06,0x60,0x0F,0x84,0x07,0x82,0x41,0x81,0x01,
+0x80,0x1E,0x00,0x70,0x00,0x0D,0x78,0x01,0xD0,0xFF,
+0xF0,0x01,0x80,0x0E,0x00,0x70,0x03,0x80,0x1C,0x00,
+0xE0,0x07,0x00,0x38,0x01,0xC0,0x0E,0x00,0x30,0x02,
+0x3F,0xFE,0x08,0xD1,0xE9,0x20,0x70,0x78,0x73,0x46,
+0x03,0x03,0x08,0xE0,0x18,0x68,0xC4,0x0C,0x03,0xC0,
+0xE0,0x02,0xD2,0xE8,0xDB,0xEF,0xBD,0xE0,0x08,0xD0,
+0xE9,0x2E,0x07,0x86,0x8C,0x40,0xC0,0x32,0x01,0xC1,
+0x9A,0x30,0x18,0x1C,0x3C,0x1C,0x00,0x0E,0x21,0x22,
+0x03,0xC0,0x1F,0xF1,0xB0,0xFF,0x40,0x78,};
+/* font data size: 2278 bytes */
+
+static const unsigned char Arial_20_index[] = {
+0x00,0x00,
+0x04,0x00,0xC0,0x11,0x02,0xB0,0x52,0x08,0x60,0xB3,
+0x0B,0x80,0xC8,0x0D,0x80,0xE7,0x0F,0x20,0xF8,0x0F,
+0xD1,0x02,0x11,0x21,0x29,0x13,0x71,0x5A,0x17,0xE1,
+0x9F,0x1B,0xB1,0xDD,0x1F,0x62,0x13,0x23,0x52,0x3C,
+0x24,0x42,0x5D,0x26,0x72,0x80,0x2A,0x32,0xFC,0x32,
+0x03,0x47,0x36,0xF3,0x8F,0x39,0xF3,0xAE,0x3D,0xD3,
+0xED,0x3F,0x34,0x02,0x42,0xD4,0x39,0x45,0x34,0x79,
+0x4A,0x24,0xBE,0x4E,0xA5,0x14,0x53,0xF5,0x4D,0x56,
+0x35,0x84,0x5B,0xB5,0xEF,0x61,0x06,0x3B,0x64,0x56,
+0x55,0x65,0xF6,0x6E,0x67,0x46,0x7B,0x69,0x86,0xB2,
+0x6C,0x86,0xE2,0x6F,0xC7,0x08,0x72,0xA7,0x3A,0x74,
+0x17,0x4C,0x76,0x87,0x6E,0x78,0x27,0x90,0x7A,0x77,
+0xC1,0x7D,0xB7,0xE5,0x80,0x18,0x0D,0x81,0xB8,0x32,
+0x85,0x58,0x73,0x89,0x38,0xAE,0x8C,0x18,0xC8,0x8D,
+0xB0,
+};
+/* font index size: 143 bytes */
+
+const ILI9341_t3_font_t Arial_20 = {
+       Arial_20_index,
+       0,
+       Arial_20_data,
+       1,
+       0,
+       32,
+       126,
+       0,
+       0,
+       12,
+       5,
+       5,
+       3,
+       6,
+       5,
+       30,
+       20
+};
+
+
+
+static const unsigned char Arial_24_data[] = {
+0x00,0x00,0x00,0x24,0x01,0xE1,0x00,0x2F,0x7D,0xF3,
+0xC5,0x02,0x78,0x04,0xA0,0x50,0x33,0x78,0xE4,0x10,
+0x08,0xE0,0x00,0x4A,0x00,0xE1,0xC0,0x78,0xE4,0x83,
+0x87,0x27,0xFF,0xFF,0x21,0xC3,0x88,0x1C,0x38,0x4F,
+0xFF,0xFE,0x8E,0x1C,0x03,0x8F,0x04,0x38,0x70,0x00,
+0x08,0x70,0x7D,0x48,0x03,0x00,0x07,0xE0,0x0F,0xFC,
+0x0F,0xFF,0x07,0x33,0x90,0xE3,0x1D,0x0E,0x30,0x07,
+0x98,0x01,0xFC,0x00,0x7F,0x80,0x1F,0xF0,0x01,0xFC,
+0x00,0xDF,0x00,0x63,0xE0,0x06,0x1E,0x38,0x61,0xDE,
+0x31,0xE7,0x99,0xE1,0xFF,0xE0,0x7F,0xE0,0x0F,0xE1,
+0x20,0x30,0x00,0x0C,0xE0,0x80,0x74,0x3E,0x00,0xE0,
+0x1F,0xC0,0x70,0x0E,0x38,0x1C,0x08,0xE0,0xE1,0xC0,
+0x38,0x38,0xF0,0x11,0xC1,0xC7,0x00,0x8E,0x0E,0x70,
+0x01,0xC7,0x38,0x00,0x3F,0x8E,0x7C,0x07,0xC7,0x3F,
+0x80,0x01,0xDC,0x74,0x00,0x1D,0xC1,0xE0,0x01,0xCE,
+0x0F,0x00,0x1C,0x70,0x70,0x0E,0x1C,0x1C,0x03,0x83,
+0x8E,0x01,0xC0,0x7F,0x00,0x70,0x0F,0x80,0x0A,0x60,
+0x40,0x58,0x03,0xE0,0x00,0x7F,0x80,0x07,0xFE,0x00,
+0x78,0x78,0x24,0x70,0x38,0x01,0xC3,0x80,0x0F,0x3C,
+0x00,0x3F,0xC0,0x00,0xF8,0x00,0x1F,0x80,0x03,0xEE,
+0x00,0x3C,0x38,0x41,0xC1,0xC7,0x9C,0x07,0x38,0xE0,
+0x1F,0xC7,0x00,0x7C,0x38,0x03,0xC1,0xE0,0x1F,0x07,
+0x83,0xFC,0x1F,0xFE,0xF0,0x7F,0xE3,0xC0,0xFC,0x08,
+0x01,0xA0,0x50,0x1B,0x79,0x00,0x04,0x7C,0xB9,0x2C,
+0x06,0x06,0x07,0x03,0x03,0x10,0x70,0x30,0x87,0x03,
+0x06,0xF0,0x47,0x04,0xB8,0x0C,0x20,0xE0,0x31,0x01,
+0x80,0x60,0x18,0x04,0x7C,0x79,0x2D,0x80,0x60,0x38,
+0x0C,0x03,0x10,0x38,0x0C,0x90,0xED,0x07,0x80,0x79,
+0x0E,0x06,0x40,0xE0,0xE0,0x60,0x70,0x30,0x30,0x00,
+0x05,0x28,0x4E,0x36,0x43,0x07,0x6E,0xFF,0xC7,0xE0,
+0x78,0x1F,0x87,0x38,0x42,0x00,0x07,0xBC,0x84,0x4F,
+0x00,0xE0,0x4F,0xFF,0xFC,0x03,0x80,0x01,0xA0,0xFB,
+0x26,0x7C,0xB2,0x60,0x04,0x8C,0x47,0x2E,0x7F,0xE0,
+0x01,0x8C,0xC0,0x26,0x78,0x04,0xE0,0x00,0x26,0x00,
+0x72,0x06,0xA0,0x64,0x86,0x24,0x60,0x38,0x49,0x82,
+0x58,0x0E,0x03,0x00,0x08,0x60,0x40,0x48,0x0F,0xC0,
+0x1F,0xF8,0x1F,0xFE,0x1F,0x0F,0x0E,0x03,0xC7,0x00,
+0xE7,0x80,0x76,0xF0,0x03,0xCF,0x00,0x39,0x80,0x38,
+0xE0,0x1C,0x70,0x1E,0x3E,0x1E,0x0F,0xFF,0x03,0xFF,
+0x00,0x7E,0x00,0x04,0x60,0xC0,0x48,0x06,0x07,0x07,
+0x87,0xC7,0xE7,0xF7,0xBB,0x1D,0x0F,0xA0,0xFA,0x0E,
+0x07,0x08,0x60,0x40,0x48,0x0F,0xC0,0x1F,0xF8,0x1F,
+0xFE,0x1E,0x07,0x8E,0x01,0xF1,0xC0,0x0F,0x00,0x00,
+0xF0,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,
+0x1C,0x00,0x1C,0x00,0x1C,0x00,0x3C,0x00,0x3C,0x00,
+0x38,0x00,0x38,0x00,0x1F,0xFF,0xE3,0xFF,0xFC,0x08,
+0x60,0x40,0x48,0x0F,0xC0,0x1F,0xF8,0x1F,0xFE,0x1E,
+0x0F,0x1E,0x03,0xCE,0x00,0xE0,0x00,0x70,0x00,0x78,
+0x00,0x79,0x00,0x7F,0x00,0x3F,0xC0,0x00,0xF0,0x00,
+0x3E,0x40,0x01,0xDC,0x00,0xEE,0x00,0xF3,0x80,0x71,
+0xE0,0xF8,0x7F,0xF8,0x1F,0xF8,0x03,0xF0,0x00,0x08,
+0xE0,0x40,0x48,0x00,0x18,0x00,0x0E,0x00,0x07,0x80,
+0x03,0xE2,0x00,0x3F,0x00,0x1D,0xC0,0x0E,0x70,0x07,
+0x1C,0x40,0x70,0xE0,0x38,0x38,0x1C,0x0E,0x0E,0x03,
+0x87,0x00,0xE2,0x7F,0xFF,0xF8,0x00,0x38,0x08,0x60,
+0x40,0x4A,0x4F,0xFF,0xAD,0xC0,0x00,0xEF,0xC0,0xEF,
+0xF8,0x7F,0xFE,0x3C,0x07,0x80,0x01,0xD4,0x00,0x0E,
+0xE0,0x07,0x70,0x07,0x9C,0x03,0x8F,0x03,0xC3,0xFF,
+0xC0,0xFF,0xC0,0x1F,0x80,0x08,0x60,0x40,0x48,0x07,
+0xE0,0x0F,0xFC,0x0F,0xFF,0x0F,0x07,0x8F,0x01,0xE7,
+0x00,0x73,0x80,0x03,0x80,0x01,0xC7,0xC0,0xE7,0xF8,
+0x7F,0xFE,0x3F,0x07,0x9E,0x01,0xCF,0x00,0x7A,0xE0,
+0x07,0x38,0x03,0x9C,0x03,0x87,0x83,0xC3,0xFF,0xC0,
+0x7F,0xC0,0x0F,0x80,0x08,0x60,0x40,0x4A,0x7F,0xFF,
+0xC0,0x00,0xC0,0x00,0xC0,0x00,0xE0,0x00,0xE0,0x00,
+0x60,0x00,0x70,0x80,0x0E,0x08,0x01,0xC0,0x90,0x38,
+0x0A,0x07,0x00,0xA0,0xE0,0x00,0x08,0x60,0x40,0x48,
+0x0F,0xC0,0x1F,0xF8,0x1F,0xFE,0x1E,0x07,0x29,0xC0,
+0x38,0x70,0x38,0x1F,0xF8,0x07,0xF8,0x0F,0xFF,0x0F,
+0x03,0xC7,0x00,0xEB,0xE0,0x07,0x38,0x07,0x1E,0x07,
+0x87,0xFF,0x81,0xFF,0x80,0x3F,0x00,0x08,0x60,0x40,
+0x48,0x0F,0x80,0x1F,0xF0,0x1F,0xFC,0x1F,0x07,0x0E,
+0x01,0xCF,0x00,0x6A,0xE0,0x07,0x70,0x07,0x9C,0x03,
+0xCF,0x07,0xE3,0xFF,0xF0,0xFF,0xB8,0x1F,0x1C,0x00,
+0x0E,0x00,0x0E,0x70,0x07,0x3C,0x07,0x8F,0x07,0x87,
+0xFF,0x81,0xFF,0x80,0x3F,0x00,0x01,0xC8,0xC0,0x26,
+0x7E,0x8B,0x13,0xC0,0x01,0xDC,0xFB,0x26,0x7E,0x8B,
+0x13,0xE5,0x93,0x00,0x07,0xBC,0x84,0x4C,0x00,0x04,
+0x00,0x3C,0x00,0xFC,0x07,0xF8,0x1F,0xC0,0xFE,0x01,
+0xF8,0x01,0xC0,0x01,0xF8,0x00,0xFE,0x00,0x1F,0xC0,
+0x07,0xF8,0x00,0xFC,0x00,0x3C,0x00,0x04,0x07,0xA8,
+0x87,0x4E,0x7F,0xFF,0xD0,0x00,0x09,0xFF,0xFE,0x07,
+0xBC,0x84,0x4D,0x00,0x01,0xE0,0x01,0xF8,0x00,0xFF,
+0x00,0x1F,0xC0,0x03,0xF8,0x00,0xFC,0x00,0x1C,0x00,
+0xFC,0x03,0xF8,0x1F,0xC0,0xFF,0x01,0xF8,0x01,0xE0,
+0x01,0x00,0x00,0x08,0x60,0x40,0x48,0x0F,0xC0,0x1F,
+0xF8,0x1F,0xFE,0x1F,0x0F,0x8E,0x01,0xEF,0x00,0x77,
+0x00,0x38,0x00,0x1C,0x00,0x1E,0x00,0x0E,0x00,0x0F,
+0x00,0x0F,0x00,0x0F,0x00,0x0F,0x00,0x07,0x05,0x00,
+0xE0,0x40,0x00,0x04,0x80,0xE0,0x00,0x0F,0x7C,0xB9,
+0x88,0x00,0x3F,0xE0,0x00,0x03,0xFF,0xF0,0x00,0x0F,
+0xFF,0xF8,0x00,0x7F,0x01,0xF8,0x01,0xF0,0x00,0xF8,
+0x03,0xC0,0x00,0x78,0x0F,0x0F,0x0E,0x70,0x3C,0x7F,
+0x9C,0xF0,0x71,0xFF,0xF0,0xE1,0xE7,0xC7,0xE1,0xE3,
+0x8E,0x07,0xC1,0xC7,0x3C,0x07,0x83,0x9C,0x70,0x0F,
+0x07,0x39,0xE0,0x1C,0x0E,0x73,0x80,0x38,0x1C,0xE7,
+0x00,0x70,0x79,0xCE,0x01,0xE0,0xE3,0x9C,0x03,0x81,
+0xC7,0x38,0x0F,0x07,0x0E,0x78,0x3E,0x1E,0x1E,0x78,
+0xFC,0x78,0x1C,0xFF,0xFF,0xE0,0x38,0xFF,0x7F,0x80,
+0x38,0x78,0x7C,0x00,0x78,0x00,0x00,0x38,0x78,0x00,
+0x01,0xE0,0x7C,0x00,0x07,0x80,0x7F,0x00,0x7E,0x00,
+0x7F,0xFF,0xF8,0x00,0x3F,0xFF,0xC0,0x00,0x0F,0xFC,
+0x00,0x0A,0xE0,0x00,0x5A,0x40,0x3E,0x01,0x20,0x3B,
+0x80,0x80,0x38,0xE0,0x01,0xE3,0x81,0x00,0xE0,0xE0,
+0x90,0xE0,0x38,0x48,0xFF,0xFE,0x24,0xE0,0x03,0x90,
+0xE0,0x00,0xE7,0x80,0x03,0x9C,0x00,0x07,0x08,0xE0,
+0xC0,0x59,0xFF,0xE0,0x7F,0xFE,0x1F,0xFF,0xC7,0x00,
+0xF1,0xC0,0x1E,0x9E,0x00,0x73,0x80,0x38,0xE0,0x1E,
+0x47,0xFF,0xE1,0xFF,0xFC,0x70,0x07,0x9C,0x00,0xFA,
+0xE0,0x03,0xB8,0x01,0xEE,0x00,0xF3,0xFF,0xFC,0xFF,
+0xFE,0x3F,0xFE,0x00,0x0A,0x60,0x80,0x60,0x03,0xF0,
+0x00,0x7F,0xE0,0x07,0xFF,0xC0,0x78,0x1E,0x07,0x80,
+0x78,0x78,0x01,0xE3,0x80,0x07,0x1C,0x00,0x23,0x78,
+0x00,0x01,0xC0,0x00,0x87,0x00,0x07,0x38,0x00,0x79,
+0xE0,0x03,0x87,0x80,0x3C,0x1F,0x07,0xC0,0xFF,0xFC,
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+0x9A,0x38,0x0E,0x07,0x87,0xE1,0xF0,0x78,0x00,0x08,
+0x18,0x48,0x4C,0x7C,0x00,0x7F,0x01,0x7F,0xE1,0xB0,
+0xFF,0xD0,0x1F,0xC0,0x07,0xC0,};
+/* font data size: 2966 bytes */
+
+static const unsigned char Arial_24_index[] = {
+0x00,0x00,0x04,0x00,
+0xD0,0x14,0x03,0x20,0x67,0x0A,0x80,0xE6,0x0E,0xC1,
+0x07,0x12,0x21,0x32,0x13,0xD1,0x44,0x14,0xA1,0x4F,
+0x16,0x21,0x89,0x19,0xB1,0xCB,0x1F,0xD2,0x24,0x24,
+0x92,0x7A,0x29,0xA2,0xC3,0x2F,0x42,0xFC,0x30,0x63,
+0x28,0x33,0x33,0x55,0x38,0x13,0xFD,0x42,0x24,0x50,
+0x48,0x44,0xB1,0x4C,0x54,0xD5,0x51,0x15,0x23,0x52,
+0xB5,0x40,0x58,0x35,0x90,0x5B,0x85,0xE1,0x61,0x46,
+0x37,0x67,0x06,0xAC,0x6E,0x56,0xF5,0x71,0x07,0x40,
+0x77,0x67,0xB7,0x7E,0x38,0x1A,0x82,0x68,0x39,0x84,
+0x58,0x5A,0x86,0x18,0x6A,0x89,0x18,0xB2,0x8D,0x38,
+0xF4,0x91,0x59,0x26,0x95,0x39,0x67,0x97,0x09,0x7E,
+0x9A,0x69,0xAE,0x9C,0x89,0xDA,0x9F,0x9A,0x18,0xA3,
+0x7A,0x45,0xA6,0xDA,0x7B,0xA8,0xDA,0xAB,0xAD,0x5A,
+0xFC,0xB2,0x3B,0x44,0xB6,0x0B,0x68,0xB8,0x50,
+};
+/* font index size: 143 bytes */
+
+const ILI9341_t3_font_t Arial_24 = {
+       Arial_24_index,
+       0,
+       Arial_24_data,
+       1,
+       0,
+       32,
+       126,
+       0,
+       0,
+       12,
+       6,
+       5,
+       4,
+       6,
+       6,
+       35,
+       24
+};
+
+static const unsigned char Arial_28_data[] = {
+0x00,0x00,0x00,0x16,0x02,0xB8,0x60,0x17,0xBF,0x7F,
+0x5D,0x8E,0x90,0x57,0x80,0x05,0x14,0x49,0x1D,0x9E,
+0x7B,0x8F,0x70,0xEE,0x18,0xC3,0x00,0x0A,0xB8,0x00,
+0x2C,0x00,0xE0,0x60,0x03,0x03,0x92,0x03,0x81,0xC0,
+0x0E,0x06,0x20,0x0E,0x07,0x13,0xFF,0xFF,0xF9,0x07,
+0x03,0x80,0x1C,0x0C,0x00,0x60,0x70,0x03,0x81,0xC1,
+0x3F,0xFF,0xFF,0xA1,0xC0,0xE0,0x07,0x07,0x01,0x27,
+0x03,0x80,0x09,0xC2,0x3E,0xAD,0x00,0x0C,0x00,0x07,
+0xF0,0x01,0xFF,0xC0,0x3F,0xFE,0x07,0xCC,0xF0,0x70,
+0xC7,0x8F,0x0C,0x78,0xE0,0xC7,0x8E,0x0C,0x02,0x1E,
+0x18,0x00,0xF1,0x80,0x0F,0x98,0x00,0x7F,0x80,0x01,
+0xFF,0x00,0x07,0xFC,0x00,0x1F,0xE0,0x01,0x9F,0x00,
+0x18,0xF0,0x01,0x87,0x9C,0x18,0x7B,0xC1,0x87,0x9C,
+0x18,0x79,0xE1,0x87,0x1F,0x18,0xF0,0xF9,0x9F,0x07,
+0xFF,0xE0,0x3F,0xFC,0x00,0xFE,0x04,0x80,0x30,0x00,
+0x0F,0x38,0x40,0x46,0x0F,0x80,0x07,0x00,0x7F,0x80,
+0x0E,0x00,0xF7,0x80,0x38,0x03,0x87,0x00,0x60,0x07,
+0x07,0x01,0xC0,0x23,0x81,0xC0,0xE0,0x08,0xE0,0x70,
+0x70,0x01,0xC0,0xE1,0xC0,0x01,0xC1,0xC3,0x80,0x03,
+0x87,0x0E,0x00,0x07,0xDE,0x1C,0x00,0x07,0xF8,0x70,
+0x7C,0x03,0xE0,0xC3,0xFC,0x00,0x03,0x87,0xBC,0x00,
+0x0E,0x1C,0x3C,0x00,0x1C,0x38,0x3C,0x00,0x0E,0x1C,
+0x0F,0x00,0x07,0x07,0x03,0x80,0x1C,0x0E,0x07,0x00,
+0x38,0x0E,0x0E,0x00,0xE0,0x1C,0x3C,0x01,0x80,0x1E,
+0xF0,0x07,0x00,0x3F,0xC0,0x0C,0x00,0x1F,0x00,0x0B,
+0xB8,0x40,0x34,0x01,0xF8,0x00,0x03,0xFE,0x00,0x0F,
+0xFF,0x00,0x0F,0x0F,0x00,0x1E,0x07,0x01,0x03,0xC0,
+0xF0,0x03,0xC0,0xE0,0x01,0xE1,0xE0,0x01,0xF3,0xC0,
+0x00,0xFF,0x80,0x00,0x7F,0x00,0x00,0xFC,0x00,0x01,
+0xFE,0x00,0x07,0xFF,0x06,0x0F,0x8F,0x8F,0x0F,0x07,
+0xCF,0x1E,0x03,0xEE,0x1E,0x01,0xFE,0x1C,0x00,0xFE,
+0x1C,0x00,0xFC,0x1E,0x00,0x7C,0x1E,0x00,0x7E,0x1F,
+0x00,0xFF,0x0F,0x83,0xEF,0x87,0xFF,0xC7,0xC3,0xFF,
+0x83,0x80,0xFE,0x01,0x00,0x02,0x14,0x49,0x0F,0x7F,
+0x5C,0x60,0x04,0xC8,0x5C,0x1A,0x01,0x80,0xF0,0x0E,
+0x80,0xE4,0x0E,0x20,0xE1,0x0F,0x09,0x70,0x67,0x82,
+0x5C,0x10,0xF0,0x83,0x84,0x0E,0x20,0x39,0x00,0xE0,
+0x1C,0x03,0x04,0xC8,0x7C,0x1A,0xC0,0x38,0x10,0xE0,
+0x83,0x84,0x0E,0x24,0x38,0x0F,0x50,0x3A,0x81,0xF2,
+0x0E,0x80,0xF4,0x07,0x03,0xC8,0x1C,0x41,0xC2,0x1C,
+0x0E,0x03,0x00,0x06,0x98,0x28,0x1F,0x00,0xE0,0x23,
+0x88,0xEE,0xE7,0xF7,0xCF,0xFE,0x80,0xF8,0x07,0x70,
+0x3D,0xE0,0xE3,0x81,0x04,0x00,0x09,0xA6,0x42,0x2F,
+0xA0,0x1C,0x00,0x01,0xC0,0x27,0xFF,0xFF,0xE8,0x07,
+0x00,0x00,0x70,0x00,0x02,0x14,0x7D,0x17,0x5F,0x46,
+0x62,0x00,0x05,0x86,0x24,0x9B,0x3F,0xFC,0x01,0x88,
+0x80,0x17,0x5C,0x05,0xB8,0x00,0x16,0x00,0xE0,0x0D,
+0x20,0x3A,0x40,0xE0,0x0C,0x48,0x38,0x90,0xE0,0x0C,
+0x12,0x38,0x24,0xE0,0x0C,0x04,0xB8,0x08,0xE0,0x00,
+0x09,0x38,0x40,0x2C,0x03,0xF0,0x01,0xFF,0x80,0x7F,
+0xF8,0x1E,0x0F,0x07,0x80,0xF2,0x1C,0x01,0xE8,0xF0,
+0x03,0xB7,0x80,0x0F,0x9E,0x00,0x3E,0x3C,0x00,0xE8,
+0x70,0x07,0x8F,0x01,0xE0,0xF0,0x7C,0x0F,0xFF,0x00,
+0xFF,0xC0,0x07,0xE0,0x00,0x05,0xB8,0x80,0x2C,0x00,
+0xF0,0x03,0xC0,0x7C,0x1F,0xC3,0xFC,0xFF,0xDF,0x3D,
+0xE3,0xD8,0x3F,0x40,0x7E,0x80,0xFA,0x01,0xE0,0x09,
+0xB8,0x20,0x2C,0x03,0xF8,0x00,0xFF,0xE0,0x1F,0xFF,
+0x83,0xE0,0x78,0x3C,0x03,0xD0,0xF0,0x03,0x8E,0x00,
+0x3C,0x00,0x03,0xC0,0x00,0x3A,0x00,0x00,0xF0,0x00,
+0x1E,0x00,0x03,0xC0,0x00,0x7C,0x00,0x0F,0x80,0x01,
+0xF0,0x00,0x3C,0x00,0x0F,0x80,0x01,0xF0,0x00,0x3E,
+0x00,0x07,0xC0,0x00,0xF8,0x00,0x0F,0x00,0x01,0xE0,
+0x00,0x1F,0xFF,0xFC,0x7F,0xFF,0xF0,0x09,0x38,0x40,
+0x2C,0x07,0xE0,0x03,0xFF,0x00,0xFF,0xF8,0x3E,0x0F,
+0x07,0x80,0xF2,0x3C,0x01,0xC7,0x80,0x3C,0x00,0x07,
+0x20,0x00,0x3C,0x00,0x1F,0x10,0x03,0xF8,0x00,0xFF,
+0xC0,0x00,0x7C,0x00,0x07,0xA4,0x00,0x0F,0x8E,0x00,
+0x3D,0xE0,0x07,0x3E,0x01,0xE3,0xE0,0xF8,0x3F,0xFE,
+0x03,0xFF,0x80,0x1F,0xC0,0x0A,0x38,0x00,0x2C,0x00,
+0x07,0x00,0x00,0x78,0x40,0x00,0xF8,0x00,0x0F,0xC0,
+0x00,0xFE,0x00,0x07,0x70,0x00,0x73,0x80,0x07,0x9C,
+0x00,0x38,0xE0,0x03,0x87,0x00,0x38,0x38,0x03,0xC1,
+0xC0,0x1C,0x0E,0x01,0xC0,0x70,0x1E,0x03,0x80,0xE0,
+0x1C,0x0E,0x00,0xE1,0x3F,0xFF,0xFF,0xA0,0x00,0xE0,
+0x09,0x38,0x40,0x2D,0x03,0xFF,0xF0,0xFF,0xFE,0x1E,
+0x00,0x14,0x70,0x00,0x1E,0x00,0x03,0x8F,0x80,0x77,
+0xFC,0x0F,0xFF,0xE1,0xF0,0x3C,0x7C,0x03,0xCF,0x00,
+0x3E,0xC0,0x00,0xF7,0x00,0x1E,0xF0,0x03,0xDE,0x00,
+0xF1,0xE0,0x1E,0x3E,0x0F,0x83,0xFF,0xE0,0x3F,0xF8,
+0x01,0xFC,0x00,0x09,0xB8,0x20,0x2C,0x01,0xFC,0x00,
+0x7F,0xF0,0x0F,0xFF,0x81,0xF0,0x78,0x1C,0x03,0xC3,
+0xC0,0x1C,0x38,0x01,0xC7,0x80,0x01,0x0E,0x00,0x00,
+0xE1,0xF8,0x0E,0x7F,0xC1,0xEF,0xFF,0x1F,0xC0,0xF1,
+0xF8,0x07,0x9F,0x00,0x3A,0x1E,0x00,0x7C,0x38,0x00,
+0xF8,0x78,0x01,0xE3,0x80,0x1C,0x3C,0x03,0xC1,0xE0,
+0x78,0x0F,0xFF,0x00,0x7F,0xE0,0x01,0xF8,0x00,0x09,
+0x38,0x40,0x2D,0x3F,0xFF,0xF8,0x00,0x1E,0x80,0x00,
+0xF0,0x00,0x3C,0x40,0x01,0xE1,0x00,0x0F,0x04,0x00,
+0x78,0x10,0x03,0xC0,0x40,0x1E,0x00,0x03,0x80,0x24,
+0x1E,0x00,0x03,0x80,0x14,0x1E,0x00,0x40,0x70,0x00,
+0x09,0x38,0x40,0x2C,0x07,0xF0,0x03,0xFF,0x80,0xFF,
+0xF8,0x1E,0x0F,0x87,0x80,0xF2,0x5C,0x01,0xE3,0xC0,
+0x3C,0x78,0x0F,0x07,0xC3,0xE0,0x7F,0xF0,0x07,0xFC,
+0x03,0xFF,0xE0,0xF8,0x1E,0x3E,0x01,0xE7,0x80,0x1D,
+0x7C,0x00,0x7B,0xC0,0x0E,0x3C,0x03,0xC7,0xC0,0xF0,
+0x7F,0xFC,0x07,0xFF,0x00,0x3F,0x80,0x09,0x38,0x40,
+0x2C,0x07,0xE0,0x03,0xFF,0x00,0xFF,0xF8,0x3E,0x0F,
+0x87,0x80,0x71,0xE0,0x0F,0x3C,0x00,0xE7,0x00,0x1D,
+0x5C,0x00,0x7B,0xC0,0x1F,0x3C,0x03,0xE7,0xC0,0xFC,
+0x7F,0xFB,0x87,0xFE,0xF0,0x3F,0x1E,0x00,0x03,0xE0,
+0x00,0x0E,0x78,0x03,0xCF,0x00,0x70,0xE0,0x1E,0x1E,
+0x07,0x81,0xFF,0xE0,0x1F,0xF8,0x00,0xFC,0x00,0x01,
+0xA8,0x80,0x17,0x5F,0x45,0x8A,0xE0,0x02,0x34,0x7D,
+0x17,0x5F,0xA1,0x61,0x5F,0x46,0x62,0x00,0x09,0xA6,
+0x42,0x2E,0x00,0x00,0x60,0x00,0x1E,0x00,0x07,0xE0,
+0x01,0xFC,0x00,0xFE,0x00,0x3F,0x80,0x0F,0xE0,0x07,
+0xF8,0x00,0xFC,0x00,0x0F,0x00,0x00,0xFC,0x00,0x07,
+0xF0,0x00,0x0F,0xE0,0x00,0x3F,0x80,0x00,0xFE,0x00,
+0x03,0xFC,0x00,0x07,0xE0,0x00,0x1E,0x00,0x00,0x60,
+0x09,0x96,0x44,0xAF,0x3F,0xFF,0xFE,0xC0,0x00,0x04,
+0xFF,0xFF,0xF0,0x09,0xA6,0x42,0x2E,0x80,0x00,0x0F,
+0x00,0x00,0xFC,0x00,0x07,0xF0,0x00,0x1F,0xE0,0x00,
+0x3F,0x80,0x00,0xFE,0x00,0x03,0xFC,0x00,0x07,0xE0,
+0x00,0x1E,0x00,0x07,0xE0,0x03,0xF8,0x00,0xFE,0x00,
+0x3F,0x80,0x0F,0xE0,0x07,0xF0,0x00,0xFC,0x00,0x0F,
+0x00,0x00,0x80,0x00,0x00,0x09,0x38,0x40,0x2C,0x07,
+0xF0,0x03,0xFF,0x80,0xFF,0xFC,0x3E,0x07,0x87,0x80,
+0x79,0xE0,0x07,0x3C,0x00,0xF7,0x00,0x1E,0x00,0x03,
+0xC0,0x00,0x70,0x00,0x1E,0x00,0x07,0x80,0x01,0xE0,
+0x00,0x78,0x00,0x1E,0x00,0x07,0x80,0x00,0xE0,0x00,
+0x3C,0x04,0x80,0xE0,0x12,0x00,0x00,0x50,0x0F,0x00,
+0x12,0x48,0x5C,0x50,0x00,0x03,0xFF,0x00,0x00,0x00,
+0xFF,0xFF,0x00,0x00,0x1F,0xFF,0xFE,0x00,0x03,0xF8,
+0x01,0xF8,0x00,0x3E,0x00,0x03,0xE0,0x03,0xE0,0x00,
+0x07,0x80,0x3C,0x00,0x00,0x1E,0x01,0xC0,0x00,0x00,
+0x70,0x1C,0x01,0xF0,0x01,0xC1,0xE0,0x3F,0xC7,0x0E,
+0x0E,0x07,0xFF,0x78,0x38,0x70,0x7C,0x1F,0xC1,0xC7,
+0x03,0xC0,0x7C,0x0E,0x38,0x3C,0x03,0xE0,0x71,0x81,
+0xC0,0x0F,0x03,0x9C,0x1E,0x00,0x78,0x1C,0xE0,0xF0,
+0x03,0x80,0xE7,0x07,0x00,0x1C,0x07,0x38,0x78,0x00,
+0xE0,0x39,0xC3,0xC0,0x0F,0x03,0x8E,0x1E,0x00,0x70,
+0x1C,0x70,0x70,0x07,0x81,0xC3,0x83,0x80,0x3C,0x1E,
+0x0E,0x1E,0x03,0xE1,0xE0,0x70,0x78,0x7F,0x3E,0x03,
+0x83,0xFF,0x7F,0xE0,0x0E,0x0F,0xF3,0xFE,0x00,0x70,
+0x1F,0x0F,0xC0,0x01,0xC0,0x00,0x00,0x0F,0x0F,0x00,
+0x00,0x00,0xF0,0x3E,0x00,0x00,0x0F,0x00,0xFC,0x00,
+0x01,0xF0,0x03,0xFC,0x00,0x7F,0x00,0x07,0xFF,0xFF,
+0xE0,0x00,0x0F,0xFF,0xFC,0x00,0x00,0x07,0xFF,0x00,
+0x00,0x0D,0x38,0x00,0x35,0x00,0x07,0xC0,0x00,0x00,
+0xFC,0x00,0x80,0x07,0x70,0x00,0x00,0xEF,0x00,0x00,
+0x3C,0xE0,0x00,0x07,0x1E,0x00,0x01,0xE1,0xC0,0x00,
+0x3C,0x3C,0x00,0x07,0x07,0x80,0x01,0xE0,0x70,0x00,
+0x38,0x0F,0x00,0x0F,0x01,0xE0,0x01,0xE0,0x1E,0x00,
+0x38,0x03,0xC0,0x0F,0xFF,0xF8,0x20,0x3F,0xFF,0xF0,
+0x0F,0x00,0x0F,0x01,0xC0,0x01,0xE0,0x78,0x00,0x1C,
+0x0F,0x00,0x03,0xC1,0xC0,0x00,0x79,0x0F,0x00,0x00,
+0xF3,0xC0,0x00,0x1E,0x78,0x00,0x01,0xE0,0x0A,0xB8,
+0x60,0x34,0xFF,0xFC,0x03,0xFF,0xFE,0x0F,0xFF,0xFC,
+0x3C,0x03,0xF1,0x1E,0x00,0x3C,0x8F,0x00,0x0F,0x47,
+0x80,0x07,0x1E,0x00,0x3C,0x78,0x01,0xE1,0xFF,0xFF,
+0x07,0xFF,0xF8,0x1F,0xFF,0xF8,0x78,0x07,0xF2,0x3C,
+0x00,0x3D,0x5E,0x00,0x0F,0x78,0x00,0x7D,0xE0,0x01,
+0xE7,0x80,0x3F,0x9F,0xFF,0xFC,0x7F,0xFF,0xE1,0xFF,
+0xFC,0x00,0x0C,0x38,0x40,0x38,0x00,0x7F,0x80,0x00,
+0xFF,0xF0,0x01,0xFF,0xFE,0x01,0xFC,0x3F,0x81,0xF0,
+0x07,0xC1,0xF0,0x00,0xF0,0xF0,0x00,0x7C,0xF0,0x00,
+0x1E,0x78,0x00,0x0E,0xDF,0x00,0x00,0x08,0xF0,0x00,
+0x00,0x38,0x00,0x03,0x43,0xC0,0x00,0x78,0xF0,0x00,
+0x7C,0x7C,0x00,0x3C,0x1F,0x00,0x7E,0x07,0xF1,0xFE,
+0x01,0xFF,0xFE,0x00,0x7F,0xFC,0x00,0x07,0xF8,0x00,
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+0xE7,0xE7,0xF3,0xE0,0x08,0x38,0x60,0x29,0xBC,0x00,
+0x0E,0x01,0xE7,0x01,0xE3,0x81,0xE1,0xC1,0xE0,0xE1,
+0xE0,0x71,0xE0,0x39,0xE0,0x1D,0xE0,0x0F,0xF0,0x07,
+0xFC,0x03,0xEF,0x01,0xE7,0x80,0xE1,0xE0,0x70,0xF8,
+0x38,0x3C,0x23,0x81,0xE1,0xC0,0x79,0x1C,0x03,0xCE,
+0x00,0xF0,0x02,0x38,0x40,0x13,0xBF,0xBF,0xBF,0xBE,
+0x0D,0xAA,0x60,0x40,0xE3,0xF0,0x3F,0x0E,0xFF,0x8F,
+0xF8,0xFF,0xFD,0xFF,0xCF,0x83,0xF8,0x3D,0x1E,0x03,
+0xE0,0x3F,0x78,0x03,0x80,0x3E,0xF0,0x07,0x00,0x77,
+0x00,0x70,0x07,0x08,0x2A,0x60,0x2C,0xE3,0xF0,0x77,
+0xFE,0x3F,0xFF,0x9F,0x83,0xD1,0xE0,0x1E,0xE0,0x0F,
+0xDE,0x00,0x7D,0xE0,0x07,0x09,0xAA,0x20,0x2C,0x01,
+0xF8,0x00,0xFF,0xE0,0x1F,0xFF,0x03,0xE0,0x78,0x3C,
+0x03,0xC7,0x80,0x1D,0x0E,0x00,0x3E,0xFC,0x00,0x3C,
+0x38,0x00,0xF3,0xC0,0x0E,0x1E,0x01,0xE1,0xF0,0x3C,
+0x0F,0xFF,0x80,0x7F,0xF0,0x01,0xFC,0x00,0x08,0xBA,
+0x7C,0x2C,0xE3,0xE0,0x3B,0xFE,0x0F,0xFF,0xC3,0xF0,
+0x78,0xF8,0x0F,0x3C,0x01,0xD3,0xC0,0x0F,0x9E,0x00,
+0x3C,0xF0,0x03,0xDE,0x00,0xE7,0x80,0x79,0xF0,0x3C,
+0x7F,0xFE,0x1D,0xFF,0x07,0x1F,0x03,0x78,0x00,0x0E,
+0x00,0x00,0x09,0x3A,0x3C,0x2C,0x03,0xF1,0xC1,0xFF,
+0x38,0x7F,0xF7,0x1F,0x07,0xE3,0xC0,0x7C,0xF0,0x07,
+0xC3,0x80,0x1F,0x5E,0x00,0x3C,0x38,0x00,0xE7,0x00,
+0x3C,0xF0,0x07,0x8F,0x01,0xF1,0xF0,0x7E,0x1F,0xFF,
+0xC1,0xFF,0x78,0x0F,0xCF,0xD0,0x00,0x3C,0x00,0x07,
+0x80,0x05,0x2A,0x60,0x1A,0xE7,0xDD,0xFB,0xFF,0x7C,
+0x11,0xE0,0x6F,0x01,0xBC,0x03,0x80,0x08,0xAA,0x20,
+0x28,0x07,0xF0,0x07,0xFF,0x03,0xFF,0xE1,0xE0,0x7C,
+0x70,0x0F,0x1C,0x01,0xC7,0x00,0x01,0xF0,0x00,0x3F,
+0x80,0x0F,0xFE,0x00,0xFF,0xE0,0x07,0xFC,0x00,0x1F,
+0x80,0x01,0xF1,0xE0,0x0F,0x3C,0x03,0xCF,0x81,0xE1,
+0xFF,0xF8,0x3F,0xF8,0x03,0xF8,0x00,0x04,0xB8,0x20,
+0x16,0x04,0x07,0x16,0x78,0x9F,0xFE,0x9E,0x34,0xF0,
+0x3C,0x0F,0xE1,0xF8,0x3E,0x08,0xAA,0x40,0x2D,0xBE,
+0x00,0xFD,0xF0,0x07,0xC3,0x80,0x3C,0xF0,0x1F,0x3E,
+0x0F,0xC7,0xFF,0x70,0xFF,0x9C,0x1F,0x87,0x09,0x2A,
+0x20,0x28,0xE0,0x03,0xDE,0x00,0x7B,0xC0,0x0E,0x38,
+0x03,0xC7,0x80,0x70,0x70,0x0E,0x0E,0x03,0xC1,0xE0,
+0x70,0x1C,0x0E,0x03,0x83,0xC0,0x78,0x70,0x07,0x0E,
+0x00,0xE3,0x80,0x1E,0x70,0x01,0xDE,0x00,0x3B,0x81,
+0x00,0x7E,0x00,0x0F,0x80,0x80,0x1E,0x00,0x0E,0x2A,
+0x00,0x38,0xF0,0x0F,0x00,0xF8,0x70,0x0F,0x00,0xE3,
+0xC0,0xFC,0x07,0x1E,0x07,0xE0,0x7A,0x0E,0x07,0xE0,
+0x70,0x78,0x73,0x87,0x92,0x38,0x73,0x87,0x00,0xE7,
+0x1E,0x70,0x80,0xE7,0x0E,0x70,0x07,0x38,0x77,0x04,
+0x83,0xF0,0x3F,0x00,0x0F,0x81,0xF0,0x20,0x0F,0x00,
+0xF0,0x00,0x09,0x2A,0x20,0x28,0xF0,0x07,0x8F,0x00,
+0xF0,0xF0,0x3C,0x1E,0x0F,0x01,0xE3,0xE0,0x1E,0x78,
+0x03,0xDE,0x00,0x3F,0x80,0x03,0xF0,0x20,0x0F,0x80,
+0x01,0xF8,0x00,0x7F,0x00,0x1E,0xF0,0x03,0xCF,0x00,
+0xF1,0xE0,0x3C,0x1E,0x07,0x81,0xE1,0xE0,0x3E,0x78,
+0x03,0xCF,0x00,0x3C,0x09,0x3A,0x3C,0x28,0xF0,0x01,
+0xDE,0x00,0x79,0xC0,0x0E,0x87,0x80,0x78,0x70,0x0E,
+0x0F,0x03,0xC1,0xE0,0x70,0x1C,0x0E,0x03,0xC3,0xC0,
+0x78,0x70,0x07,0x0E,0x00,0xF3,0xC2,0x01,0xCE,0x00,
+0x3F,0x81,0x00,0x7E,0x00,0x0F,0x80,0x80,0x1E,0x02,
+0x00,0x70,0x08,0x03,0x80,0x01,0xF0,0x01,0xFC,0x00,
+0x3F,0x00,0x07,0xC0,0x00,0x09,0x2A,0x20,0x29,0x2F,
+0xFF,0xF0,0x00,0x3C,0x00,0x0F,0x00,0x03,0xC0,0x00,
+0xF8,0x00,0x1E,0x00,0x07,0x80,0x01,0xE0,0x00,0x78,
+0x00,0x1F,0x00,0x03,0xC0,0x00,0xF0,0x00,0x3C,0x00,
+0x0F,0x00,0x03,0xE0,0x00,0x78,0x00,0x27,0xFF,0xFF,
+0x05,0xC8,0x3C,0x1A,0x01,0xF0,0x0F,0xC1,0xE3,0x43,
+0x84,0x87,0x00,0xF0,0x1E,0x07,0xC0,0x70,0x07,0xC0,
+0x1E,0x00,0xE0,0xD0,0xE1,0x41,0xC0,0x1E,0x00,0xFC,
+0x07,0xC0,0x3C,0x01,0xC8,0x9C,0x15,0xBF,0x7E,0xFD,
+0xFB,0xDC,0x05,0xC8,0x3C,0x1A,0xF0,0x11,0xF8,0x03,
+0xC3,0x43,0x84,0x87,0x00,0x78,0x03,0xC0,0x1F,0x00,
+0x70,0x1F,0x03,0xC0,0x38,0xD0,0xE1,0x21,0xC2,0x07,
+0x83,0xF0,0x3E,0x03,0xC0,0x00,0x09,0x8E,0x45,0x2E,
+0x3F,0x00,0x0F,0xFC,0x02,0xFF,0xF0,0xEF,0xFF,0xFE,
+0xC1,0xFF,0xE8,0x07,0xFC,0x00,0x1F,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x16,0x02,0xB8,0x9C,0x1B,0x4F,0x90,
+0x6B,0xAD,0xC7,0xEF,0xDF,0x09,0x48,0x5C,0x2D,0x00,
+0x00,0xC0,0x00,0x38,0x80,0x00,0xC0,0x00,0x38,0x00,
+0x06,0x00,0x1F,0xC0,0x0F,0xFC,0x03,0xFF,0xE0,0xF0,
+0xFC,0x3C,0x1B,0xC7,0x87,0x78,0xE0,0xC7,0x3C,0x18,
+0x07,0x87,0x01,0x3E,0x18,0x03,0xC7,0x00,0x78,0xC1,
+0xE7,0x18,0x38,0xF7,0x07,0x1E,0xC1,0xE1,0xF8,0x78,
+0x1F,0xFE,0x01,0xFF,0x80,0x1F,0xC0,0x03,0x00,0x00,
+0xE0,0x02,0x43,0x00,0x00,0xE0,0x01,0x03,0x00,0x00,
+0x0A,0x38,0x20,0x2C,0x01,0xFC,0x00,0x3F,0xF8,0x03,
+0xFF,0xE0,0x3E,0x0F,0x03,0xC0,0x3C,0x1E,0x00,0xE0,
+0xF0,0x07,0x87,0x00,0x3D,0x47,0x80,0x00,0x1C,0x00,
+0x09,0xFF,0xF8,0x00,0x70,0x00,0x03,0xC0,0x02,0x03,
+0x80,0x00,0x3C,0x00,0x01,0xC0,0x00,0x1E,0x00,0x00,
+0xE0,0x00,0x1F,0xFE,0x1C,0xFF,0xFF,0xE7,0xFF,0xFF,
+0x90,0x07,0xF0,0x09,0x24,0x42,0xAC,0x40,0x01,0x1C,
+0x7E,0x7B,0xFF,0xFF,0x3F,0xFF,0xC3,0xE1,0xF0,0x70,
+0x1E,0x1E,0x01,0xC3,0x80,0x3D,0x0E,0x00,0x71,0xC0,
+0x1E,0x38,0x03,0x87,0x80,0xF0,0x7C,0x3E,0x1F,0xFF,
+0xE7,0xFF,0xFE,0xE3,0xF3,0xC8,0x00,0x20,0x0A,0xB8,
+0x00,0x2C,0xF0,0x00,0x79,0xE0,0x01,0xE7,0x80,0x0F,
+0x0F,0x00,0x3C,0x3C,0x01,0xE0,0x78,0x07,0x80,0xE0,
+0x3C,0x03,0xC0,0xE0,0x07,0x07,0x80,0x1E,0x1C,0x00,
+0x38,0xF0,0x00,0xF7,0x80,0x01,0xDE,0x00,0x07,0xF0,
+0x12,0xFF,0xFF,0xE8,0x00,0x78,0x04,0xBF,0xFF,0xFB,
+0x00,0x1E,0x00,0x01,0xC8,0x9C,0x15,0xBF,0x7B,0xE0,
+0xDF,0xBD,0xC0,0x09,0x48,0x5C,0x2C,0x07,0xF0,0x01,
+0xFF,0x80,0x7F,0xF8,0x1E,0x0F,0x03,0x80,0xF0,0xF0,
+0x1E,0x1E,0x01,0xC1,0xC0,0x00,0x3C,0x00,0x03,0xE0,
+0x00,0x3E,0x00,0x1F,0xF0,0x07,0xBF,0x81,0xC1,0xF8,
+0x38,0x1F,0x87,0x00,0xF8,0xE0,0x0F,0x9C,0x00,0x7B,
+0xC0,0x0F,0x3E,0x00,0xE3,0xE0,0x1C,0x3F,0x07,0x03,
+0xF9,0xE0,0x1F,0xF8,0x01,0xFC,0x00,0x0F,0xC0,0x00,
+0xF8,0x00,0x07,0x80,0x00,0x70,0xE0,0x0F,0x1E,0x01,
+0xE3,0xC0,0x38,0x3C,0x0F,0x07,0xFF,0xC0,0x3F,0xF0,
+0x03,0xF8,0x00,0x05,0x88,0x2C,0x1B,0x5E,0x3C,0x0E,
+0xB8,0x00,0x3A,0x00,0x1F,0xC0,0x00,0x03,0xFF,0xE0,
+0x00,0x3F,0x9F,0xE0,0x01,0xE0,0x07,0xC0,0x0F,0x00,
+0x07,0x80,0x70,0x00,0x07,0x03,0x80,0xF8,0x0E,0x0C,
+0x0F,0xF8,0x38,0x70,0x78,0xF0,0x71,0x83,0x80,0xE1,
+0xCE,0x1C,0x01,0x83,0x47,0x0E,0x00,0x01,0xE3,0x07,
+0x00,0x00,0xEE,0x1C,0x00,0x03,0xB8,0x70,0x06,0x0E,
+0x61,0xC0,0x38,0x31,0x83,0x80,0xE1,0xC7,0x07,0x8F,
+0x07,0x0C,0x0F,0xF8,0x38,0x38,0x1F,0x80,0xE0,0x70,
+0x00,0x07,0x00,0xF0,0x00,0x78,0x01,0xE0,0x03,0xC0,
+0x03,0xF9,0xFE,0x00,0x03,0xFF,0xE0,0x00,0x01,0xFC,
+0x00,0x00,0x06,0x1C,0x27,0x1C,0x1F,0x81,0xFF,0x1E,
+0x3C,0xE0,0xE6,0x07,0x00,0xF8,0xFF,0xCF,0xEE,0xF0,
+0x77,0x03,0xB8,0x3D,0xE3,0xE7,0xFF,0x1F,0x18,0x08,
+0x22,0x60,0xAC,0x07,0x07,0x03,0x87,0x03,0x87,0x03,
+0x83,0x83,0xC3,0x81,0xC3,0xC1,0xE3,0xC1,0xE1,0xC0,
+0xE1,0xE0,0x78,0x70,0x1E,0x3C,0x07,0x0F,0x03,0xC3,
+0x80,0xE0,0xE0,0x38,0x70,0x0E,0x1C,0x07,0x07,0x09,
+0x98,0x44,0x2F,0x3F,0xFF,0xFF,0x40,0x00,0x7C,0x00,
+0x00,0xF0,0x05,0x86,0x24,0x9B,0x3F,0xFC,0x0E,0xB8,
+0x00,0x3A,0x00,0x1F,0xC0,0x00,0x03,0xFF,0xE0,0x00,
+0x3F,0x9F,0xE0,0x01,0xE0,0x07,0xC0,0x0F,0x00,0x07,
+0x80,0x70,0x00,0x07,0x03,0x80,0x00,0x0E,0x0C,0x3F,
+0xF0,0x38,0x70,0xFF,0xE0,0x71,0x83,0x83,0xC1,0xCE,
+0x0E,0x07,0x03,0x47,0x07,0x03,0x81,0xD8,0x1F,0xFC,
+0x07,0x60,0x7F,0xC0,0x1D,0xC1,0xC7,0x00,0x77,0x07,
+0x0E,0x01,0xCC,0x1C,0x18,0x06,0x30,0x70,0x70,0x38,
+0xE1,0xC0,0xE0,0xE1,0x87,0x03,0x87,0x07,0x1C,0x07,
+0x1C,0x0E,0x00,0x00,0xE0,0x1E,0x00,0x0F,0x00,0x3C,
+0x00,0x78,0x00,0x7F,0x3F,0xC0,0x00,0x7F,0xFC,0x00,
+0x00,0x3F,0x80,0x00,0x0B,0x85,0xEF,0x2D,0x1F,0xFF,
+0xFF,0xC0,0x05,0x96,0x48,0xA0,0x1F,0x03,0xF8,0x71,
+0xC6,0x0F,0x1C,0x0C,0xC0,0xCC,0x1C,0xE3,0x87,0xF0,
+0x3E,0x00,0x09,0xB0,0x20,0x2B,0xA0,0x1C,0x00,0x01,
+0xC0,0x27,0xFF,0xFF,0xE8,0x07,0x00,0x00,0x70,0x08,
+0x00,0x00,0x13,0xFF,0xFF,0xC0,0x05,0x9C,0x27,0x1A,
+0x1F,0x87,0xFC,0xF1,0xEE,0x0F,0x00,0x1C,0x03,0x80,
+0xF0,0x1E,0x03,0xC0,0x70,0x0E,0x02,0x3F,0xF8,0x05,
+0x9C,0x27,0x1A,0x3F,0x87,0xFC,0xF1,0xEE,0x0E,0x01,
+0xC0,0x78,0x0F,0xC0,0x1F,0x00,0x1D,0xC1,0xDE,0x3C,
+0xFF,0x87,0xF0,0x03,0x8A,0x8B,0x9A,0x3E,0x3C,0x78,
+0x70,0xE0,0x08,0x3A,0x7C,0x2D,0xBC,0x00,0xF7,0xC0,
+0x0F,0x3E,0x00,0xEF,0x00,0xF7,0xC0,0xFB,0xF8,0xFD,
+0xDF,0xFE,0xEF,0xF7,0x71,0xF3,0xEF,0x00,0x03,0x80,
+0x00,0x0A,0xC8,0x1C,0x2A,0x07,0xFF,0xF8,0x7F,0xFF,
+0xE3,0xFF,0xFF,0xC3,0xFF,0x0E,0x33,0xFF,0x87,0x10,
+0xFF,0xC3,0x81,0xFF,0x0E,0x03,0xFC,0x38,0x03,0xF0,
+0xE3,0x40,0x38,0x71,0xA0,0x1C,0x38,0xC0,0x0E,0x1C,
+0x00,
+};
+/* font data size: 5071 bytes */
+
+static const unsigned char Arial_28_index[] = {
+0x00,0x00,0x01,0x00,0x1E,0x01,0xB0,0x24,0x02,0x58,
+0x1F,0x21,0x4F,0x0A,0xB0,0x5D,0x03,0x26,0x1A,0xA0,
+0xDE,0x07,0x10,0x39,0x41,0xCF,0x0F,0x50,0x85,0xC4,
+0x5E,0x27,0x31,0x56,0x8B,0x90,0x63,0x23,0x5B,0x1C,
+0x20,0xEF,0x47,0xF6,0x40,0x32,0x07,0x11,0x08,0x89,
+0xE4,0x83,0x25,0xD1,0x59,0x4B,0x78,0x5F,0xC3,0x20,
+0x19,0xF0,0xD2,0xC6,0xAC,0x37,0xC1,0xC3,0x4E,0x2A,
+0x73,0x13,0xC4,0x9E,0x68,0xFC,0xE8,0x25,0x43,0xDA,
+0x29,0x11,0xEE,0x94,0xB4,0xCC,0x26,0xB5,0x39,0xAA,
+0x24,0x54,0x72,0xB9,0xD6,0x46,0xB6,0xD5,0xBD,0xAE,
+0x65,0x74,0xEB,0xC9,0x5E,0x8A,0xF6,0x98,0x22,0xC3,
+0x96,0x2F,0x32,0x31,0x97,0x8C,0xD0,0x68,0x73,0x49,
+0xDA,0x60,0xD4,0x26,0xB9,0x35,0xE9,0xB3,0x6D,0xB1,
+0x6E,0xE3,0x82,0x1C,0x72,0xE4,0x97,0x3D,0xBA,0x35,
+0xD4,0x8E,0xD6,0x78,0x63,0xD0,0x1E,0xFA,0xFA,0xA7,
+0xE5,0xBF,0x51,0xFE,0xD0,0x0C,0x80,0x84,0x05,0x20,
+0x31,0x01,0xC8,0x10,0x40,0x92,0x05,0x10,0x2C,0x81,
+0x84,0x0D,0x20,0x71,0x03,0xC8,0x20,0x41,0x12,0x09,
+0x10,0x4C,0x82,0x84,0x15,0x20,0xB1,0x05,0xC8,0x30,
+0x41,0x92,0x0D,0x10,0x6C,0x83,0x84,0x1D,0x20,0xF1,
+0x07,0xC8,0x40,0x42,0x12,0x11,0x10,0x8C,0x84,0x84,
+0x25,0x21,0x3F,0x0E,0xA8,0x94,0xC5,0x5A,0x31,0xB1,
+0x97,0x8F,0x8C,0x7D,0xE4,0xBD,0x27,0x99,0x50,0xCA,
+0xBA,0x56,0x93,0x1E,0x99,0x34,0xCE,0xA6,0xA5,0x36,
+0x99,0xC0,0xCE,0x2A,0x74,0xE0,
+};
+/* font index size: 246 bytes */
+
+const ILI9341_t3_font_t Arial_28 = {
+        Arial_28_index,
+        0,
+        Arial_28_data,
+        1,
+        0,
+        32,
+        182,
+        0,
+        0,
+        13,
+        6,
+        6,
+        4,
+        6,
+        6,
+        43,
+        28
+};
+
+
+/*
+static const unsigned char Arial_28_data[] = {
+0x00,0x00,0x00,0x16,0x01,0xB8,0x80,0x17,0xBF,0x79,
+0xEA,0x91,0x3C,0x05,0x94,0x29,0x1D,0xBC,0x1D,0xC1,
+0xC8,0x0C,0x80,0x80,0x0B,0x38,0x00,0x2D,0x00,0x1C,
+0x0E,0x00,0x78,0x38,0xA0,0x1C,0x0E,0x00,0x70,0x38,
+0x4F,0xFF,0xFF,0xE0,0x38,0x3C,0x28,0x1C,0x0E,0x00,
+0x78,0x38,0x13,0xFF,0xFF,0xF8,0x38,0x1C,0x0A,0x1C,
+0x0E,0x00,0x38,0x3C,0x04,0x1C,0x0E,0x00,0x09,0x40,
+0x3E,0xAC,0x00,0xC0,0x00,0x7E,0x00,0x3F,0xF0,0x0F,
+0xFF,0x03,0xCC,0xF0,0xF1,0x8E,0x43,0x86,0x1D,0x0E,
+0x18,0x01,0xE3,0x00,0x1E,0x60,0x03,0xFC,0x00,0x3F,
+0xE0,0x01,0xFF,0x00,0x0F,0xF8,0x00,0xCF,0x80,0x18,
+0x74,0x80,0x60,0xF1,0xC1,0x83,0xBC,0x30,0xF3,0xC6,
+0x3C,0x7C,0xCF,0x87,0xFF,0xE0,0x7F,0xF8,0x01,0xFC,
+0x12,0x01,0x80,0x00,0x0F,0xB8,0x40,0x46,0x1F,0x00,
+0x03,0x80,0x3F,0xC0,0x07,0x80,0x79,0xE0,0x07,0x00,
+0x70,0xE0,0x0F,0x00,0xE0,0x70,0x0E,0x00,0xE0,0x70,
+0x1C,0x00,0xE0,0x70,0x3C,0x00,0xE0,0x70,0x38,0x00,
+0xE0,0x70,0x78,0x00,0xE0,0x70,0x70,0x00,0xE0,0x70,
+0xE0,0x00,0x70,0xE0,0xE0,0x00,0x79,0xE1,0xC0,0x00,
+0x3F,0xC3,0xC3,0xE0,0x0F,0x03,0x87,0xF8,0x00,0x07,
+0x8F,0x3C,0x00,0x07,0x0E,0x1D,0x00,0x01,0xC3,0x81,
+0xC0,0x03,0x83,0x81,0xC0,0x07,0x83,0x81,0xC0,0x07,
+0x03,0x81,0xC0,0x0F,0x03,0x81,0xC0,0x0E,0x03,0x81,
+0xC0,0x1C,0x01,0xC3,0x80,0x3C,0x01,0xE7,0x80,0x38,
+0x00,0xFF,0x00,0x78,0x00,0x3C,0x00,0x0B,0xB8,0x40,
+0x34,0x01,0xF8,0x00,0x07,0xFE,0x00,0x0F,0xFF,0x00,
+0x0F,0x0F,0x00,0x1E,0x07,0x81,0x23,0x80,0x70,0x01,
+0xC0,0xE0,0x01,0xE3,0xE0,0x00,0xFF,0xC0,0x00,0x7F,
+0x00,0x00,0xFE,0x00,0x01,0xFC,0x00,0x03,0xFE,0x00,
+0x07,0x8F,0x04,0x0F,0x07,0x8F,0x1E,0x03,0x8F,0x1C,
+0x01,0xDE,0x1C,0x01,0xFE,0x1C,0x00,0xFE,0x1C,0x00,
+0x7C,0x1E,0x00,0x7C,0x0F,0x00,0xFE,0x0F,0x83,0xFF,
+0x07,0xFF,0xE7,0xC1,0xFF,0x83,0x80,0x7E,0x01,0x00,
+0x01,0x94,0x49,0x0F,0xBE,0x39,0x00,0x04,0x48,0x5C,
+0x1A,0x03,0x03,0x03,0x81,0x81,0xC0,0xC4,0x1C,0x0C,
+0x25,0xC3,0x78,0x2B,0x80,0xC1,0x2E,0x03,0x08,0x38,
+0x0C,0x07,0x01,0x80,0xE0,0x30,0x0C,0x04,0x48,0x7C,
+0x1A,0xC0,0x30,0x1C,0x06,0x03,0x80,0xC4,0x0E,0x03,
+0x24,0x38,0x0D,0xA0,0xF2,0x0E,0x06,0x90,0xE0,0x64,
+0x0E,0x06,0x07,0x03,0x03,0x81,0x81,0x80,0x06,0x98,
+0x28,0x1F,0x20,0xE0,0x23,0x89,0xEE,0xF7,0xFF,0xC7,
+0xFC,0x07,0xC0,0x3B,0x81,0xEF,0x07,0x1C,0x08,0x20,
+0x09,0xA6,0x42,0x2F,0xA0,0x1C,0x00,0x01,0xC0,0x27,
+0xFF,0xFF,0xE8,0x07,0x00,0x00,0x70,0x00,0x01,0x92,
+0x7D,0x17,0x3E,0x9B,0x20,0x05,0x86,0x24,0x1B,0x3F,
+0xFC,0x01,0x86,0x60,0x17,0x3C,0x05,0xB8,0x00,0x17,
+0x00,0x1E,0x40,0x75,0x01,0xC9,0x07,0x14,0x1C,0x24,
+0x70,0x51,0xC0,0x97,0x01,0x1C,0x00,0x09,0x38,0x40,
+0x2C,0x03,0xF0,0x01,0xFF,0x80,0x7F,0xF8,0x1F,0x0F,
+0x83,0x80,0x72,0x5C,0x00,0xED,0xE0,0x01,0xEF,0x80,
+0x07,0x97,0x00,0x38,0x70,0x0E,0x0F,0x87,0xC0,0xFF,
+0xF0,0x0F,0xFC,0x00,0x7E,0x00,0x05,0xB8,0x80,0x2C,
+0x00,0x60,0x0E,0x01,0xE0,0x3E,0x07,0xE1,0xFE,0x7F,
+0xEF,0xCE,0xF0,0xEC,0x0F,0xA0,0x1F,0x40,0x3D,0x00,
+0x70,0x09,0xB8,0x20,0x2C,0x03,0xF8,0x00,0xFF,0xE0,
+0x3F,0xFF,0x83,0xE0,0xFC,0x78,0x03,0xC7,0x00,0x1F,
+0x1C,0x00,0x1E,0x00,0x00,0x38,0x00,0x07,0x80,0x00,
+0x70,0x00,0x0F,0x00,0x01,0xE0,0x00,0x3C,0x00,0x07,
+0x80,0x00,0xF0,0x00,0x1E,0x00,0x03,0xC0,0x00,0x78,
+0x00,0x1F,0x00,0x03,0xC0,0x00,0x78,0x00,0x0F,0x00,
+0x01,0xC0,0x00,0x1F,0xFF,0xFC,0x7F,0xFF,0xF0,0x09,
+0x38,0x40,0x2C,0x07,0xF0,0x03,0xFF,0x80,0xFF,0xF8,
+0x3E,0x0F,0x87,0x00,0x71,0xE0,0x07,0x38,0x00,0xE8,
+0x00,0x03,0x80,0x00,0xF0,0x00,0x1C,0x00,0x0F,0x10,
+0x03,0xF8,0x00,0x7F,0xC0,0x00,0x3C,0x00,0x03,0x80,
+0x00,0x7C,0x00,0x00,0xF1,0xC0,0x03,0x9C,0x00,0xF3,
+0xC0,0x3C,0x3C,0x0F,0x07,0xFF,0xC0,0x3F,0xF0,0x01,
+0xF8,0x00,0x09,0xB8,0x20,0x2C,0x00,0x07,0x00,0x00,
+0xF0,0x00,0x1F,0x10,0x00,0x7E,0x00,0x0F,0xE0,0x01,
+0xEE,0x00,0x1C,0xE0,0x03,0x8E,0x00,0x78,0xE0,0x0F,
+0x0E,0x00,0xE0,0xE0,0x1C,0x0E,0x03,0xC0,0xE0,0x38,
+0x0E,0x07,0x00,0xE0,0xF0,0x0E,0x1E,0x00,0xE2,0x7F,
+0xFF,0xFE,0x80,0x03,0x80,0x09,0x38,0x40,0x2D,0x03,
+0xFF,0xF0,0xFF,0xFE,0xA3,0x80,0x02,0x1C,0x00,0x03,
+0x9F,0x80,0x7F,0xFC,0x0F,0xFF,0xC3,0xE0,0x3C,0x78,
+0x03,0xC0,0x00,0x3A,0xC0,0x00,0x77,0x00,0x0E,0xE0,
+0x03,0x8E,0x00,0x71,0xC0,0x1E,0x1E,0x07,0x83,0xFF,
+0xE0,0x3F,0xF8,0x00,0xFC,0x00,0x09,0xB8,0x20,0x2C,
+0x01,0xFC,0x00,0x7F,0xF0,0x0F,0xFF,0x81,0xF0,0x7C,
+0x3C,0x01,0xC3,0x80,0x1E,0x78,0x00,0xF0,0xE0,0x00,
+0x1C,0x00,0x01,0xC3,0xF0,0x1C,0xFF,0xC1,0xDF,0xFE,
+0x1F,0xC0,0xF1,0xF0,0x07,0x9E,0x00,0x3A,0xB8,0x00,
+0x39,0x80,0x03,0x9C,0x00,0x39,0xC0,0x07,0x0E,0x00,
+0xF0,0xF8,0x1E,0x07,0xFF,0xC0,0x1F,0xF8,0x00,0x7E,
+0x00,0x09,0x38,0x40,0x2D,0x3F,0xFF,0xF8,0x00,0x06,
+0x00,0x01,0x80,0x00,0x60,0x00,0x1C,0x00,0x07,0x00,
+0x00,0xC0,0x00,0x38,0x20,0x01,0xC0,0x80,0x0E,0x02,
+0x40,0x70,0x09,0x03,0x80,0x28,0x1C,0x00,0xA0,0xE0,
+0x00,0x09,0x38,0x40,0x2C,0x03,0xF0,0x01,0xFF,0x80,
+0x7F,0xF8,0x1E,0x07,0x87,0x80,0x7A,0x9C,0x00,0xE3,
+0xC0,0x3C,0x3C,0x0F,0x03,0xFF,0xC0,0x3F,0xE0,0x0F,
+0xFF,0x03,0xC0,0xF0,0xF0,0x0F,0x3C,0x00,0xEB,0xE0,
+0x01,0xDE,0x00,0x79,0xC0,0x0E,0x1E,0x07,0x83,0xFF,
+0xF0,0x1F,0xF8,0x00,0xFC,0x00,0x09,0x38,0x40,0x2C,
+0x03,0xF0,0x01,0xFF,0x80,0xFF,0xF8,0x1E,0x07,0x87,
+0x80,0x70,0xE0,0x07,0x3C,0x00,0x67,0x00,0x0D,0x5C,
+0x00,0x39,0xC0,0x0F,0x3C,0x03,0xE7,0xC0,0xFC,0x7F,
+0xFB,0x87,0xFE,0x70,0x3F,0x0E,0x00,0x01,0xE0,0x00,
+0x0E,0x70,0x01,0xCE,0x00,0x70,0xE0,0x1E,0x1E,0x07,
+0x81,0xFF,0xE0,0x1F,0xF8,0x00,0xFC,0x00,0x01,0xAA,
+0x60,0x17,0x3F,0x46,0x80,0x9E,0x01,0xB6,0x7D,0x17,
+0x3F,0x46,0x80,0x9F,0x4D,0x90,0x09,0xA6,0x42,0x2E,
+0x00,0x00,0x20,0x00,0x1E,0x00,0x07,0xE0,0x01,0xFC,
+0x00,0xFE,0x00,0x3F,0x80,0x0F,0xC0,0x07,0xF0,0x00,
+0xF8,0x00,0x0E,0x00,0x00,0xF8,0x00,0x07,0xF0,0x00,
+0x0F,0xC0,0x00,0x3F,0x80,0x00,0xFE,0x00,0x01,0xFC,
+0x00,0x07,0xE0,0x00,0x1E,0x00,0x00,0x20,0x09,0x98,
+0x44,0x2F,0x3F,0xFF,0xFF,0x00,0x00,0x04,0xFF,0xFF,
+0xF0,0x09,0xA6,0x42,0x2E,0x80,0x00,0x0F,0x00,0x00,
+0xFC,0x00,0x07,0xF0,0x00,0x0F,0xE0,0x00,0x3F,0x80,
+0x00,0x7E,0x00,0x01,0xFC,0x00,0x03,0xE0,0x00,0x0E,
+0x00,0x03,0xE0,0x01,0xFC,0x00,0x7E,0x00,0x3F,0x80,
+0x0F,0xE0,0x07,0xF0,0x00,0xFC,0x00,0x0F,0x00,0x00,
+0x80,0x00,0x00,0x09,0x38,0x40,0x2C,0x03,0xF0,0x01,
+0xFF,0xC0,0xFF,0xFC,0x1E,0x07,0xC7,0x80,0x78,0xE0,
+0x07,0xC7,0x00,0x0E,0x00,0x01,0xC0,0x00,0x78,0x00,
+0x0E,0x00,0x03,0xC0,0x01,0xF0,0x00,0x7C,0x00,0x1F,
+0x00,0x03,0xC0,0x00,0xF0,0x00,0x3C,0x05,0x00,0xE0,
+0x12,0x00,0x00,0x48,0x0E,0x00,0x12,0x48,0x5C,0x50,
+0x00,0x03,0xFE,0x00,0x00,0x00,0xFF,0xFE,0x00,0x00,
+0x1F,0xFF,0xFC,0x00,0x03,0xFC,0x03,0xF8,0x00,0x3F,
+0x00,0x07,0xE0,0x03,0xE0,0x00,0x0F,0x80,0x3C,0x00,
+0x00,0x3C,0x01,0xC0,0x3E,0x1C,0xF0,0x1E,0x07,0xFC,
+0xE3,0xC1,0xE0,0x7F,0xF7,0x0E,0x0E,0x07,0x83,0xF0,
+0x70,0xF0,0x78,0x07,0x81,0xC7,0x07,0x80,0x3C,0x0E,
+0x38,0x78,0x00,0xE0,0x73,0xC3,0x80,0x07,0x03,0x9C,
+0x1C,0x00,0x30,0x1C,0xE1,0xE0,0x01,0x80,0xE7,0x0E,
+0x00,0x0C,0x07,0x47,0x0E,0x00,0x1C,0x0E,0x38,0x70,
+0x00,0xE0,0xF1,0xC3,0x80,0x0E,0x07,0x0E,0x1E,0x00,
+0xF0,0x78,0x78,0x70,0x0F,0x87,0x81,0xC3,0xE1,0xFC,
+0x78,0x0E,0x0F,0xFE,0xFF,0x80,0x78,0x3F,0xE7,0xF8,
+0x01,0xE0,0x7C,0x1F,0x03,0x8F,0x00,0x00,0x00,0x38,
+0x3E,0x00,0x00,0x03,0x80,0xF8,0x00,0x00,0x78,0x03,
+0xF0,0x00,0x0F,0x80,0x0F,0xF0,0x03,0xF8,0x00,0x1F,
+0xFF,0xFF,0x80,0x00,0x3F,0xFF,0xF0,0x00,0x00,0x1F,
+0xF8,0x00,0x00,0x0C,0xB8,0x20,0x35,0x20,0x07,0xC0,
+0x08,0x00,0x77,0x00,0x00,0x3D,0xE0,0x10,0x01,0xC7,
+0x00,0x80,0x1C,0x1C,0x00,0x0F,0x07,0x81,0x00,0x70,
+0x1C,0x00,0x3C,0x07,0x82,0x01,0xC0,0x1C,0x10,0x1F,
+0xFF,0xF0,0x0F,0xFF,0xFE,0x20,0x70,0x00,0x71,0x27,
+0x00,0x01,0xC8,0x70,0x00,0x07,0x3C,0x00,0x01,0xEE,
+0x00,0x00,0x38,0x0A,0xB8,0x60,0x34,0xFF,0xFE,0x03,
+0xFF,0xFE,0x0F,0xFF,0xFC,0x38,0x00,0xF8,0xE0,0x00,
+0xE5,0xF0,0x00,0x39,0xC0,0x01,0xC7,0x00,0x1F,0x1F,
+0xFF,0xF0,0x7F,0xFF,0xE1,0xFF,0xFF,0xC7,0x00,0x0F,
+0x9C,0x00,0x0E,0x70,0x00,0x3E,0xB8,0x00,0x0E,0xE0,
+0x00,0x7B,0x80,0x01,0xCE,0x00,0x1F,0x3F,0xFF,0xF8,
+0xFF,0xFF,0xC3,0xFF,0xF8,0x00,0x0C,0x38,0x40,0x38,
+0x00,0x7F,0x00,0x01,0xFF,0xE0,0x01,0xFF,0xFC,0x01,
+0xF0,0x3F,0x01,0xE0,0x07,0x81,0xE0,0x01,0xE0,0xE0,
+0x00,0x78,0xE0,0x00,0x1C,0x70,0x00,0x08,0x78,0x00,
+0x00,0x6F,0x00,0x00,0x03,0x80,0x00,0x00,0xE0,0x00,
+0x08,0x70,0x00,0x07,0x38,0x00,0x07,0x8E,0x00,0x03,
+0x87,0x80,0x03,0xC1,0xE0,0x03,0xC0,0x7C,0x07,0xC0,
+0x1F,0xFF,0xC0,0x07,0xFF,0xC0,0x00,0x7F,0x00,0x0B,
+0xB8,0x60,0x38,0xFF,0xFE,0x00,0xFF,0xFF,0x80,0xFF,
+0xFF,0xE0,0xE0,0x03,0xF0,0xE0,0x00,0xF0,0xE0,0x00,
+0x78,0xE0,0x00,0x3D,0x1C,0x00,0x03,0xB7,0x80,0x00,
+0x3C,0x70,0x00,0x07,0x70,0x00,0x0F,0x8E,0x00,0x01,
+0xCE,0x00,0x03,0xCE,0x00,0x07,0x8E,0x00,0x0F,0x0E,
+0x00,0x3F,0x0F,0xFF,0xFE,0x0F,0xFF,0xF8,0x0F,0xFF,
+0xE0,0x00,0x0A,0xB8,0x60,0x35,0x3F,0xFF,0xFE,0xDE,
+0x00,0x00,0x47,0x00,0x00,0x27,0xFF,0xFF,0x9B,0xC0,
+0x00,0x09,0xE0,0x00,0x04,0xFF,0xFF,0xFC,0x09,0xB8,
+0x60,0x31,0x3F,0xFF,0xFF,0x78,0x00,0x04,0x70,0x00,
+0x09,0xFF,0xFF,0x9B,0xC0,0x00,0x33,0x80,0x00,0x00,
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+0x00,0xED,0xE0,0x01,0xE3,0xC0,0x0E,0x7C,0x03,0xCF,
+0xC1,0xF1,0xFF,0xFC,0x3B,0xFF,0x07,0x1F,0x81,0xBC,
+0x00,0x03,0x80,0x00,0x09,0x3A,0x3C,0x2C,0x03,0xF1,
+0xC1,0xFF,0x38,0x7F,0xF7,0x1F,0x0F,0xE7,0x80,0x7C,
+0xE0,0x07,0xBC,0x00,0xFD,0xE0,0x01,0xE1,0xC0,0x0F,
+0x3C,0x03,0xE3,0xE1,0xFC,0x3F,0xFF,0x83,0xFF,0x70,
+0x1F,0x8F,0xA0,0x00,0x38,0x00,0x07,0x05,0x2A,0x60,
+0x1A,0xE7,0xDD,0xFB,0xFE,0x7C,0x11,0xE0,0x6F,0x01,
+0xBC,0x03,0x80,0x08,0xAA,0x20,0x26,0x0F,0xE0,0x0F,
+0xFE,0x07,0xFF,0xE1,0xE0,0x78,0xE0,0x0F,0x38,0x01,
+0xCE,0x00,0x03,0xE0,0x00,0x7F,0x80,0x1F,0xFE,0x01,
+0xFF,0xE0,0x0F,0xFC,0x00,0x3F,0x80,0x01,0xF1,0xC0,
+0x07,0x38,0x03,0xCF,0x81,0xE1,0xFF,0xF0,0x3F,0xF8,
+0x03,0xF8,0x00,0x05,0x38,0x00,0x16,0x04,0x01,0x85,
+0x8E,0x13,0xFF,0xE8,0xE1,0xA3,0x80,0x78,0x0F,0xE0,
+0xFC,0x0F,0x80,0x08,0x2A,0x60,0x2D,0xBC,0x00,0xFB,
+0xC0,0x0E,0xE0,0x07,0x70,0x07,0xBC,0x07,0xCF,0x07,
+0xE7,0xFF,0x71,0xFF,0x38,0x3F,0x1C,0x09,0xAA,0x00,
+0x26,0xE0,0x00,0xF0,0xE0,0x03,0x8F,0x00,0x7A,0x0E,
+0x00,0xE0,0x70,0x1E,0x07,0x01,0xC0,0x78,0x3C,0x40,
+0x70,0x70,0x07,0x8F,0x08,0x07,0x1C,0x12,0x07,0x70,
+0x20,0x07,0xC0,0x00,0x3C,0x00,0x03,0x80,0x00,0x0E,
+0xAA,0x00,0x3B,0x1C,0x00,0xE0,0x07,0x78,0x07,0xC0,
+0x3E,0x1C,0x03,0xE0,0x1C,0x38,0x0D,0x80,0xE4,0x1C,
+0x0E,0xE0,0x70,0x38,0x31,0x83,0x80,0xE1,0xC7,0x0E,
+0x01,0x87,0x1C,0x70,0x07,0x1C,0x31,0xC0,0x1C,0xE0,
+0xE7,0x00,0x33,0x83,0xB8,0x00,0xEE,0x0E,0xE0,0x03,
+0xB8,0x1B,0x02,0x00,0xF8,0x0F,0x80,0x01,0xE0,0x3C,
+0x00,0x07,0x00,0x70,0x00,0x1C,0x01,0x80,0x00,0x09,
+0x2A,0x00,0x24,0xF0,0x01,0xCF,0x00,0x70,0xE0,0x1E,
+0x1E,0x07,0x81,0xE0,0xE0,0x1C,0x3C,0x03,0xCF,0x00,
+0x3D,0xC0,0x03,0xF0,0x00,0x3E,0x04,0x00,0xF0,0x00,
+0x3F,0x00,0x0F,0xF0,0x01,0xCF,0x00,0x70,0xE0,0x1E,
+0x1E,0x07,0x81,0xE0,0xE0,0x1C,0x3C,0x03,0xCF,0x00,
+0x3C,0x08,0xBA,0x3C,0x26,0xE0,0x03,0x9C,0x01,0xF0,
+0xE0,0x0E,0x1C,0x07,0xA0,0xE0,0x38,0x1C,0x1E,0x40,
+0xE0,0xE0,0x1C,0x78,0x80,0xE3,0x80,0x1D,0xE1,0x00,
+0xEE,0x00,0x1F,0x82,0x00,0xF8,0x00,0x1E,0x04,0x80,
+0xE0,0x20,0x0E,0x00,0x07,0x00,0x0F,0xC0,0x03,0xE0,
+0x00,0xF0,0x00,0x09,0x2A,0x00,0x27,0x2F,0xFF,0xF8,
+0x00,0x1E,0x00,0x07,0x80,0x01,0xE0,0x00,0x38,0x00,
+0x0F,0x00,0x03,0xC0,0x00,0xF0,0x00,0x3C,0x00,0x0F,
+0x00,0x03,0xC0,0x00,0xF0,0x00,0x3C,0x00,0x0F,0x00,
+0x03,0xC0,0x00,0x70,0x00,0x27,0xFF,0xFF,0x05,0xC8,
+0x3C,0x1A,0x01,0xF0,0x0F,0xC1,0xE3,0x43,0x85,0x07,
+0x00,0xE0,0x1E,0x07,0xC0,0x70,0x07,0xC0,0x1E,0x00,
+0xE0,0xD0,0xE1,0x21,0xC0,0x1E,0x20,0x1F,0x80,0x78,
+0x01,0xCA,0x7B,0x93,0xBF,0x7E,0xFD,0xFB,0xE3,0x80,
+0x05,0xC8,0x3C,0x1A,0xF0,0x0F,0x80,0xFC,0x01,0xE1,
+0xA1,0xC2,0x83,0x80,0x1C,0x01,0xE0,0x0F,0x80,0x38,
+0x0F,0x81,0xE0,0x1C,0x68,0x70,0x90,0xE0,0x1E,0x11,
+0xF8,0x1E,0x00,0x0A,0x0C,0x25,0xAE,0x1F,0x00,0x03,
+0xFF,0x01,0xBF,0xFE,0x1D,0xC3,0xFF,0xEC,0x03,0xFE,
+0x00,0x07,0xC0,};
+*/
+/* font data size: 3983 bytes */
+/*
+static const unsigned char Arial_28_index[] = {
+0x00,0x00,0x04,0x00,0xD0,0x18,0x04,
+0x40,0x86,0x0F,0x71,0x4A,0x15,0x11,0x6F,0x18,0xE1,
+0xA4,0x1B,0x61,0xBD,0x1C,0x31,0xC8,0x1D,0xD2,0x04,
+0x21,0xD2,0x61,0x2A,0x02,0xD5,0x30,0x83,0x49,0x37,
+0x13,0xA8,0x3E,0x63,0xEE,0x3F,0x84,0x2C,0x43,0x94,
+0x6D,0x4A,0x25,0x49,0x58,0x55,0xC4,0x60,0xD6,0x4C,
+0x66,0x66,0x7C,0x6C,0xC6,0xE1,0x6E,0x97,0x04,0x75,
+0xC7,0x6E,0x7A,0x37,0xEE,0x83,0x78,0x66,0x8B,0x99,
+0x03,0x95,0x39,0x67,0x98,0xA9,0xD2,0xA2,0xEA,0x8D,
+0xAC,0x9B,0x13,0xB2,0x1B,0x36,0xB4,0x4B,0x5C,0xB6,
+0x4B,0x6D,0xBA,0x1B,0xC8,0xBF,0x1C,0x18,0xC4,0x5C,
+0x59,0xC9,0x0C,0xAB,0xCB,0x4C,0xC6,0xCF,0xCD,0x04,
+0xD2,0x9D,0x41,0xD6,0x9D,0x92,0xDB,0xDD,0xCD,0xDF,
+0xFE,0x13,0xE2,0xBE,0x55,0xE9,0xBE,0xCF,0xF0,0x3F,
+0x30,0xF5,0x0F,0x5A,0xF7,0xB0,
+};
+*/
+/* font index size: 143 bytes */
+/*
+const ILI9341_t3_font_t Arial_28 = {
+       Arial_28_index,
+       0,
+       Arial_28_data,
+       1,
+       0,
+       32,
+       126,
+       0,
+       0,
+       12,
+       6,
+       6,
+       4,
+       6,
+       6,
+       43,
+       28
+};
+*/
+
+/*
+static const unsigned char Arial_28_data[] = {
+0x00,0x00,0x00,0x16,0x02,0xB8,0x60,0x17,0xBF,0x7F,
+0x5D,0x8E,0x90,0x57,0x80,0x05,0x14,0x49,0x1D,0x9E,
+0x7B,0x8F,0x70,0xEE,0x18,0xC3,0x00,0x0A,0xB8,0x00,
+0x2C,0x00,0xE0,0x60,0x03,0x03,0x92,0x03,0x81,0xC0,
+0x0E,0x06,0x20,0x0E,0x07,0x13,0xFF,0xFF,0xF9,0x07,
+0x03,0x80,0x1C,0x0C,0x00,0x60,0x70,0x03,0x81,0xC1,
+0x3F,0xFF,0xFF,0xA1,0xC0,0xE0,0x07,0x07,0x01,0x27,
+0x03,0x80,0x09,0xC2,0x3E,0xAD,0x00,0x0C,0x00,0x07,
+0xF0,0x01,0xFF,0xC0,0x3F,0xFE,0x07,0xCC,0xF0,0x70,
+0xC7,0x8F,0x0C,0x78,0xE0,0xC7,0x8E,0x0C,0x02,0x1E,
+0x18,0x00,0xF1,0x80,0x0F,0x98,0x00,0x7F,0x80,0x01,
+0xFF,0x00,0x07,0xFC,0x00,0x1F,0xE0,0x01,0x9F,0x00,
+0x18,0xF0,0x01,0x87,0x9C,0x18,0x7B,0xC1,0x87,0x9C,
+0x18,0x79,0xE1,0x87,0x1F,0x18,0xF0,0xF9,0x9F,0x07,
+0xFF,0xE0,0x3F,0xFC,0x00,0xFE,0x04,0x80,0x30,0x00,
+0x0F,0x38,0x40,0x46,0x0F,0x80,0x07,0x00,0x7F,0x80,
+0x0E,0x00,0xF7,0x80,0x38,0x03,0x87,0x00,0x60,0x07,
+0x07,0x01,0xC0,0x23,0x81,0xC0,0xE0,0x08,0xE0,0x70,
+0x70,0x01,0xC0,0xE1,0xC0,0x01,0xC1,0xC3,0x80,0x03,
+0x87,0x0E,0x00,0x07,0xDE,0x1C,0x00,0x07,0xF8,0x70,
+0x7C,0x03,0xE0,0xC3,0xFC,0x00,0x03,0x87,0xBC,0x00,
+0x0E,0x1C,0x3C,0x00,0x1C,0x38,0x3C,0x00,0x0E,0x1C,
+0x0F,0x00,0x07,0x07,0x03,0x80,0x1C,0x0E,0x07,0x00,
+0x38,0x0E,0x0E,0x00,0xE0,0x1C,0x3C,0x01,0x80,0x1E,
+0xF0,0x07,0x00,0x3F,0xC0,0x0C,0x00,0x1F,0x00,0x0B,
+0xB8,0x40,0x34,0x01,0xF8,0x00,0x03,0xFE,0x00,0x0F,
+0xFF,0x00,0x0F,0x0F,0x00,0x1E,0x07,0x01,0x03,0xC0,
+0xF0,0x03,0xC0,0xE0,0x01,0xE1,0xE0,0x01,0xF3,0xC0,
+0x00,0xFF,0x80,0x00,0x7F,0x00,0x00,0xFC,0x00,0x01,
+0xFE,0x00,0x07,0xFF,0x06,0x0F,0x8F,0x8F,0x0F,0x07,
+0xCF,0x1E,0x03,0xEE,0x1E,0x01,0xFE,0x1C,0x00,0xFE,
+0x1C,0x00,0xFC,0x1E,0x00,0x7C,0x1E,0x00,0x7E,0x1F,
+0x00,0xFF,0x0F,0x83,0xEF,0x87,0xFF,0xC7,0xC3,0xFF,
+0x83,0x80,0xFE,0x01,0x00,0x02,0x14,0x49,0x0F,0x7F,
+0x5C,0x60,0x04,0xC8,0x5C,0x1A,0x01,0x80,0xF0,0x0E,
+0x80,0xE4,0x0E,0x20,0xE1,0x0F,0x09,0x70,0x67,0x82,
+0x5C,0x10,0xF0,0x83,0x84,0x0E,0x20,0x39,0x00,0xE0,
+0x1C,0x03,0x04,0xC8,0x7C,0x1A,0xC0,0x38,0x10,0xE0,
+0x83,0x84,0x0E,0x24,0x38,0x0F,0x50,0x3A,0x81,0xF2,
+0x0E,0x80,0xF4,0x07,0x03,0xC8,0x1C,0x41,0xC2,0x1C,
+0x0E,0x03,0x00,0x06,0x98,0x28,0x1F,0x00,0xE0,0x23,
+0x88,0xEE,0xE7,0xF7,0xCF,0xFE,0x80,0xF8,0x07,0x70,
+0x3D,0xE0,0xE3,0x81,0x04,0x00,0x09,0xA6,0x42,0x2F,
+0xA0,0x1C,0x00,0x01,0xC0,0x27,0xFF,0xFF,0xE8,0x07,
+0x00,0x00,0x70,0x00,0x02,0x14,0x7D,0x17,0x5F,0x46,
+0x62,0x00,0x05,0x86,0x24,0x9B,0x3F,0xFC,0x01,0x88,
+0x80,0x17,0x5C,0x05,0xB8,0x00,0x16,0x00,0xE0,0x0D,
+0x20,0x3A,0x40,0xE0,0x0C,0x48,0x38,0x90,0xE0,0x0C,
+0x12,0x38,0x24,0xE0,0x0C,0x04,0xB8,0x08,0xE0,0x00,
+0x09,0x38,0x40,0x2C,0x03,0xF0,0x01,0xFF,0x80,0x7F,
+0xF8,0x1E,0x0F,0x07,0x80,0xF2,0x1C,0x01,0xE8,0xF0,
+0x03,0xB7,0x80,0x0F,0x9E,0x00,0x3E,0x3C,0x00,0xE8,
+0x70,0x07,0x8F,0x01,0xE0,0xF0,0x7C,0x0F,0xFF,0x00,
+0xFF,0xC0,0x07,0xE0,0x00,0x05,0xB8,0x80,0x2C,0x00,
+0xF0,0x03,0xC0,0x7C,0x1F,0xC3,0xFC,0xFF,0xDF,0x3D,
+0xE3,0xD8,0x3F,0x40,0x7E,0x80,0xFA,0x01,0xE0,0x09,
+0xB8,0x20,0x2C,0x03,0xF8,0x00,0xFF,0xE0,0x1F,0xFF,
+0x83,0xE0,0x78,0x3C,0x03,0xD0,0xF0,0x03,0x8E,0x00,
+0x3C,0x00,0x03,0xC0,0x00,0x3A,0x00,0x00,0xF0,0x00,
+0x1E,0x00,0x03,0xC0,0x00,0x7C,0x00,0x0F,0x80,0x01,
+0xF0,0x00,0x3C,0x00,0x0F,0x80,0x01,0xF0,0x00,0x3E,
+0x00,0x07,0xC0,0x00,0xF8,0x00,0x0F,0x00,0x01,0xE0,
+0x00,0x1F,0xFF,0xFC,0x7F,0xFF,0xF0,0x09,0x38,0x40,
+0x2C,0x07,0xE0,0x03,0xFF,0x00,0xFF,0xF8,0x3E,0x0F,
+0x07,0x80,0xF2,0x3C,0x01,0xC7,0x80,0x3C,0x00,0x07,
+0x20,0x00,0x3C,0x00,0x1F,0x10,0x03,0xF8,0x00,0xFF,
+0xC0,0x00,0x7C,0x00,0x07,0xA4,0x00,0x0F,0x8E,0x00,
+0x3D,0xE0,0x07,0x3E,0x01,0xE3,0xE0,0xF8,0x3F,0xFE,
+0x03,0xFF,0x80,0x1F,0xC0,0x0A,0x38,0x00,0x2C,0x00,
+0x07,0x00,0x00,0x78,0x40,0x00,0xF8,0x00,0x0F,0xC0,
+0x00,0xFE,0x00,0x07,0x70,0x00,0x73,0x80,0x07,0x9C,
+0x00,0x38,0xE0,0x03,0x87,0x00,0x38,0x38,0x03,0xC1,
+0xC0,0x1C,0x0E,0x01,0xC0,0x70,0x1E,0x03,0x80,0xE0,
+0x1C,0x0E,0x00,0xE1,0x3F,0xFF,0xFF,0xA0,0x00,0xE0,
+0x09,0x38,0x40,0x2D,0x03,0xFF,0xF0,0xFF,0xFE,0x1E,
+0x00,0x14,0x70,0x00,0x1E,0x00,0x03,0x8F,0x80,0x77,
+0xFC,0x0F,0xFF,0xE1,0xF0,0x3C,0x7C,0x03,0xCF,0x00,
+0x3E,0xC0,0x00,0xF7,0x00,0x1E,0xF0,0x03,0xDE,0x00,
+0xF1,0xE0,0x1E,0x3E,0x0F,0x83,0xFF,0xE0,0x3F,0xF8,
+0x01,0xFC,0x00,0x09,0xB8,0x20,0x2C,0x01,0xFC,0x00,
+0x7F,0xF0,0x0F,0xFF,0x81,0xF0,0x78,0x1C,0x03,0xC3,
+0xC0,0x1C,0x38,0x01,0xC7,0x80,0x01,0x0E,0x00,0x00,
+0xE1,0xF8,0x0E,0x7F,0xC1,0xEF,0xFF,0x1F,0xC0,0xF1,
+0xF8,0x07,0x9F,0x00,0x3A,0x1E,0x00,0x7C,0x38,0x00,
+0xF8,0x78,0x01,0xE3,0x80,0x1C,0x3C,0x03,0xC1,0xE0,
+0x78,0x0F,0xFF,0x00,0x7F,0xE0,0x01,0xF8,0x00,0x09,
+0x38,0x40,0x2D,0x3F,0xFF,0xF8,0x00,0x1E,0x80,0x00,
+0xF0,0x00,0x3C,0x40,0x01,0xE1,0x00,0x0F,0x04,0x00,
+0x78,0x10,0x03,0xC0,0x40,0x1E,0x00,0x03,0x80,0x24,
+0x1E,0x00,0x03,0x80,0x14,0x1E,0x00,0x40,0x70,0x00,
+0x09,0x38,0x40,0x2C,0x07,0xF0,0x03,0xFF,0x80,0xFF,
+0xF8,0x1E,0x0F,0x87,0x80,0xF2,0x5C,0x01,0xE3,0xC0,
+0x3C,0x78,0x0F,0x07,0xC3,0xE0,0x7F,0xF0,0x07,0xFC,
+0x03,0xFF,0xE0,0xF8,0x1E,0x3E,0x01,0xE7,0x80,0x1D,
+0x7C,0x00,0x7B,0xC0,0x0E,0x3C,0x03,0xC7,0xC0,0xF0,
+0x7F,0xFC,0x07,0xFF,0x00,0x3F,0x80,0x09,0x38,0x40,
+0x2C,0x07,0xE0,0x03,0xFF,0x00,0xFF,0xF8,0x3E,0x0F,
+0x87,0x80,0x71,0xE0,0x0F,0x3C,0x00,0xE7,0x00,0x1D,
+0x5C,0x00,0x7B,0xC0,0x1F,0x3C,0x03,0xE7,0xC0,0xFC,
+0x7F,0xFB,0x87,0xFE,0xF0,0x3F,0x1E,0x00,0x03,0xE0,
+0x00,0x0E,0x78,0x03,0xCF,0x00,0x70,0xE0,0x1E,0x1E,
+0x07,0x81,0xFF,0xE0,0x1F,0xF8,0x00,0xFC,0x00,0x01,
+0xA8,0x80,0x17,0x5F,0x45,0x8A,0xE0,0x02,0x34,0x7D,
+0x17,0x5F,0xA1,0x61,0x5F,0x46,0x62,0x00,0x09,0xA6,
+0x42,0x2E,0x00,0x00,0x60,0x00,0x1E,0x00,0x07,0xE0,
+0x01,0xFC,0x00,0xFE,0x00,0x3F,0x80,0x0F,0xE0,0x07,
+0xF8,0x00,0xFC,0x00,0x0F,0x00,0x00,0xFC,0x00,0x07,
+0xF0,0x00,0x0F,0xE0,0x00,0x3F,0x80,0x00,0xFE,0x00,
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+0x00,0x3F,0x00,0x0F,0xFC,0x03,0xFF,0xE0,0x7C,0x0F,
+0x07,0x80,0x78,0xF0,0x03,0xA1,0xC0,0x07,0x9F,0xFF,
+0xFC,0x7F,0xFF,0xF7,0x80,0x00,0x87,0x00,0x01,0x0F,
+0x00,0x3C,0x78,0x07,0x87,0xC0,0xF8,0x3F,0xFF,0x01,
+0xFF,0xE0,0x03,0xF8,0x00,0x09,0xB8,0x20,0x2D,0x00,
+0x07,0x80,0x00,0xF0,0x00,0x0E,0x00,0x01,0xC0,0x20,
+0x00,0x00,0x00,0x7E,0x00,0x1F,0xF8,0x07,0xFF,0xC0,
+0xF8,0x1E,0x0F,0x00,0xF1,0xE0,0x07,0x43,0x80,0x0F,
+0x3F,0xFF,0xF8,0xFF,0xFF,0xEF,0x00,0x01,0x0E,0x00,
+0x02,0x1E,0x00,0x78,0xF0,0x0F,0x0F,0x81,0xF0,0x7F,
+0xFE,0x03,0xFF,0xC0,0x07,0xF0,0x00,0x09,0xB8,0x20,
+0x2C,0x01,0xF0,0x00,0x1F,0x80,0x03,0xBC,0x00,0x79,
+0xE0,0x0F,0x0E,0x10,0x00,0x00,0x00,0x3F,0x00,0x0F,
+0xFC,0x03,0xFF,0xE0,0x7C,0x0F,0x07,0x80,0x78,0xF0,
+0x03,0xA1,0xC0,0x07,0x9F,0xFF,0xFC,0x7F,0xFF,0xF7,
+0x80,0x00,0x87,0x00,0x01,0x0F,0x00,0x3C,0x78,0x07,
+0x87,0xC0,0xF8,0x3F,0xFF,0x01,0xFF,0xE0,0x03,0xF8,
+0x00,0x09,0xB6,0x20,0x2D,0x41,0xE1,0xC2,0x00,0x00,
+0x00,0x07,0xE0,0x01,0xFF,0x80,0x7F,0xFC,0x0F,0x81,
+0xE0,0xF0,0x0F,0x1E,0x00,0x74,0x38,0x00,0xF3,0xFF,
+0xFF,0x8F,0xFF,0xFE,0xF0,0x00,0x10,0xE0,0x00,0x21,
+0xE0,0x07,0x8F,0x00,0xF0,0xF8,0x1F,0x07,0xFF,0xE0,
+0x3F,0xFC,0x00,0x7F,0x00,0x03,0xB8,0x20,0x16,0xF8,
+0x78,0x3C,0x1C,0x0F,0x00,0x34,0x76,0x8E,0xD1,0xC0,
+0x03,0x38,0x80,0x16,0x3E,0x1E,0x78,0xE2,0x00,0xDE,
+0x37,0x8D,0xE0,0x05,0xB8,0x00,0x16,0x1F,0x01,0xF8,
+0x3B,0xC7,0x9C,0xF1,0xF0,0x00,0x34,0x38,0x68,0x70,
+0xD0,0xE0,0x05,0xB6,0x00,0x17,0x5E,0x3E,0x00,0x06,
+0x87,0x0D,0x0E,0x1A,0x1C,0x00,0x09,0xB8,0x20,0x2C,
+0x03,0xC3,0x00,0x1E,0xF0,0x00,0xFE,0x00,0x0F,0x80,
+0x07,0xFC,0x00,0xF9,0xE0,0x04,0x0E,0x00,0x3F,0x70,
+0x0F,0xFF,0x81,0xFF,0xF8,0x3E,0x0F,0xC3,0xC0,0x3C,
+0x78,0x03,0xC7,0x80,0x1E,0x70,0x01,0xEF,0x00,0x1F,
+0x1E,0x00,0x1E,0x3C,0x00,0x7C,0x38,0x00,0xF3,0xC0,
+0x1E,0x1E,0x01,0xE1,0xF0,0x7C,0x0F,0xFF,0x80,0x7F,
+0xF0,0x01,0xFC,0x00,0x08,0x36,0x60,0x2C,0x0F,0x0E,
+0x0F,0xFF,0x0F,0xFF,0x07,0x0F,0x10,0x00,0x00,0xE3,
+0xF0,0x77,0xFE,0x3F,0xFF,0x9F,0x83,0xD1,0xE0,0x1E,
+0xE0,0x0F,0xDE,0x00,0x7D,0xE0,0x07,0x09,0xB8,0x20,
+0x2C,0x07,0xC0,0x00,0x3C,0x00,0x01,0xE0,0x00,0x0E,
+0x00,0x00,0x70,0x10,0x00,0x00,0x00,0x3F,0x00,0x1F,
+0xFC,0x03,0xFF,0xE0,0x7C,0x0F,0x07,0x80,0x78,0xF0,
+0x03,0xA1,0xC0,0x07,0xDF,0x80,0x07,0x87,0x00,0x1E,
+0x78,0x01,0xC3,0xC0,0x3C,0x3E,0x07,0x81,0xFF,0xF0,
+0x0F,0xFE,0x00,0x3F,0x80,0x09,0xB8,0x20,0x2D,0x00,
+0x07,0x80,0x00,0xF0,0x00,0x0E,0x00,0x01,0xC0,0x20,
+0x00,0x00,0x00,0x7E,0x00,0x3F,0xF8,0x07,0xFF,0xC0,
+0xF8,0x1E,0x0F,0x00,0xF1,0xE0,0x07,0x43,0x80,0x0F,
+0xBF,0x00,0x0F,0x0E,0x00,0x3C,0xF0,0x03,0x87,0x80,
+0x78,0x7C,0x0F,0x03,0xFF,0xE0,0x1F,0xFC,0x00,0x7F,
+0x00,0x09,0xB8,0x20,0x2C,0x01,0xF0,0x00,0x1F,0x80,
+0x03,0xBC,0x00,0x79,0xE0,0x0F,0x0E,0x10,0x00,0x00,
+0x00,0x3F,0x00,0x1F,0xFC,0x03,0xFF,0xE0,0x7C,0x0F,
+0x07,0x80,0x78,0xF0,0x03,0xA1,0xC0,0x07,0xDF,0x80,
+0x07,0x87,0x00,0x1E,0x78,0x01,0xC3,0xC0,0x3C,0x3E,
+0x07,0x81,0xFF,0xF0,0x0F,0xFE,0x00,0x3F,0x80,0x09,
+0xB6,0x20,0x2C,0x07,0x83,0x00,0xFF,0xF0,0x0E,0xFE,
+0x01,0xC3,0xC1,0x00,0x00,0x00,0x03,0xF0,0x01,0xFF,
+0xC0,0x3F,0xFE,0x07,0xC0,0xF0,0x78,0x07,0x8F,0x00,
+0x3A,0x1C,0x00,0x7D,0xF8,0x00,0x78,0x70,0x01,0xE7,
+0x80,0x1C,0x3C,0x03,0xC3,0xE0,0x78,0x1F,0xFF,0x00,
+0xFF,0xE0,0x03,0xF8,0x00,0x09,0xB6,0x20,0x2D,0x41,
+0xE1,0xC2,0x00,0x00,0x00,0x07,0xE0,0x03,0xFF,0x80,
+0x7F,0xFC,0x0F,0x81,0xE0,0xF0,0x0F,0x1E,0x00,0x74,
+0x38,0x00,0xFB,0xF0,0x00,0xF0,0xE0,0x03,0xCF,0x00,
+0x38,0x78,0x07,0x87,0xC0,0xF0,0x3F,0xFE,0x01,0xFF,
+0xC0,0x07,0xF0,0x00,0x09,0x9E,0x23,0x2B,0x40,0x1E,
+0x02,0x00,0x00,0x04,0xFF,0xFF,0xF8,0x00,0x00,0x14,
+0x01,0xE0,0x00,0x09,0xAE,0x5F,0xB0,0x00,0x00,0x40,
+0x1F,0x8E,0x07,0xFE,0xC1,0xFF,0xFC,0x3E,0x07,0x83,
+0xC0,0x7D,0x0F,0x01,0xFC,0xE0,0x39,0xCE,0x07,0x1E,
+0x3C,0x1C,0x3B,0xC3,0x83,0x9C,0x70,0x39,0xCE,0x03,
+0x9E,0xC0,0x79,0xFC,0x07,0x8F,0x80,0xF0,0xF8,0x1E,
+0x0F,0xFF,0xE0,0xFF,0xF8,0x1C,0x7E,0x00,0x80,0x00,
+0x00,0x08,0xB8,0x40,0x2C,0x07,0xC0,0x00,0xF0,0x00,
+0x1E,0x00,0x03,0x80,0x00,0x70,0x40,0x00,0x03,0x7C,
+0x01,0xFB,0xE0,0x0F,0x87,0x00,0x79,0xE0,0x3E,0x7C,
+0x1F,0x8F,0xFE,0xE1,0xFF,0x38,0x3F,0x0E,0x08,0xB8,
+0x40,0x2C,0x00,0x78,0x40,0x07,0x80,0x03,0xC0,0x00,
+0xE0,0x20,0x00,0x01,0xBE,0x00,0xFD,0xF0,0x07,0xC3,
+0x80,0x3C,0xF0,0x1F,0x3E,0x0F,0xC7,0xFF,0x70,0xFF,
+0x9C,0x1F,0x87,0x08,0xB8,0x40,0x2C,0x03,0xE0,0x00,
+0xFC,0x00,0x77,0x80,0x3C,0xE0,0x1E,0x3C,0x40,0x00,
+0x03,0x7C,0x01,0xFB,0xE0,0x0F,0x87,0x00,0x79,0xE0,
+0x3E,0x7C,0x1F,0x8F,0xFE,0xE1,0xFF,0x38,0x3F,0x0E,
+0x08,0xB6,0x40,0x2D,0x43,0xC7,0x88,0x00,0x00,0x6F,
+0x80,0x3F,0x7C,0x01,0xF0,0xE0,0x0F,0x3C,0x07,0xCF,
+0x83,0xF1,0xFF,0xDC,0x3F,0xE7,0x07,0xE1,0xC0,0x09,
+0x48,0x3C,0x28,0x00,0x7C,0x00,0x0F,0x00,0x03,0xC0,
+0x00,0x70,0x00,0x1C,0x02,0x00,0x00,0x07,0x80,0x0E,
+0xF0,0x03,0xCE,0x00,0x74,0x3C,0x03,0xC3,0x80,0x70,
+0x78,0x1E,0x0F,0x03,0x80,0xE0,0x70,0x1E,0x1E,0x03,
+0xC3,0x80,0x38,0x70,0x07,0x9E,0x10,0x0E,0x70,0x01,
+0xFC,0x08,0x03,0xF0,0x00,0x7C,0x04,0x00,0xF0,0x10,
+0x03,0x80,0x40,0x1C,0x00,0x0F,0x80,0x0F,0xE0,0x01,
+0xF8,0x00,0x3E,0x00,0x00,0x08,0xC8,0x7C,0x2D,0xBC,
+0x00,0x07,0x1F,0x01,0xDF,0xF0,0x7F,0xFE,0x1F,0x83,
+0xC7,0xC0,0x79,0xE0,0x0E,0x9E,0x00,0x7C,0xF0,0x01,
+0xE7,0x80,0x1E,0xF0,0x07,0x3C,0x03,0xCF,0x81,0xE3,
+0xFF,0xF0,0xEF,0xF8,0x38,0xF8,0x1B,0xC0,0x00,0x70,
+0x00,0x00,0x09,0x46,0x3C,0x29,0x41,0xC3,0x84,0x00,
+0x00,0x0F,0x00,0x1D,0xE0,0x07,0x9C,0x00,0xE8,0x78,
+0x07,0x87,0x00,0xE0,0xF0,0x3C,0x1E,0x07,0x01,0xC0,
+0xE0,0x3C,0x3C,0x07,0x87,0x00,0x70,0xE0,0x0F,0x3C,
+0x20,0x1C,0xE0,0x03,0xF8,0x10,0x07,0xE0,0x00,0xF8,
+0x08,0x01,0xE0,0x20,0x07,0x00,0x80,0x38,0x00,0x1F,
+0x00,0x1F,0xC0,0x03,0xF0,0x00,0x7C,0x00,0x00,
+};
+*/
+/* font data size: 9389 bytes */
+/*
+static const unsigned char Arial_28_index[] = {
+0x00,0x00,0x00,0x40,0x03,0xC0,0x1B,0x01,0x20,0x09,
+0x60,0x3E,0x41,0x4F,0x05,0x58,0x17,0x40,0x64,0xC1,
+0xAA,0x06,0xF0,0x1C,0x40,0x72,0x81,0xCF,0x07,0xA8,
+0x21,0x70,0x8B,0xC2,0x73,0x0A,0xB4,0x2E,0x40,0xC6,
+0x43,0x5B,0x0E,0x10,0x3B,0xD0,0xFE,0xC4,0x03,0x10,
+0x38,0x44,0x21,0x13,0xC4,0x83,0x12,0xE8,0x56,0x51,
+0x6F,0x05,0xFC,0x19,0x00,0x67,0xC1,0xA5,0x86,0xAC,
+0x1B,0xE0,0x70,0xD1,0xC5,0x47,0x31,0x1E,0x24,0x79,
+0xA1,0xF9,0xC8,0x25,0x21,0xEC,0x8A,0x42,0x3D,0xC9,
+0x4B,0x26,0x60,0x9A,0xD2,0x73,0x4A,0x24,0x2A,0x38,
+0xAE,0x72,0xC8,0xCB,0x6D,0x2D,0xEC,0xB9,0x92,0xE9,
+0xCB,0xC9,0x2F,0x44,0xBD,0xA3,0x04,0x4C,0x39,0x31,
+0x78,0xC8,0xC3,0x2F,0x0C,0xD0,0x34,0x38,0xD2,0x73,
+0x4C,0x0D,0x42,0x35,0xC8,0xD7,0xA3,0x66,0xCD,0xB1,
+0x37,0x70,0xE0,0x83,0x8E,0x4E,0x49,0x39,0xEC,0xE8,
+0xD3,0xA9,0x0E,0xD6,0x3C,0x30,0xF4,0x03,0xDF,0x4F,
+0xAA,0x3F,0x2C,0xFD,0x43,0xFD,0x90,0x0C,0x40,0x41,
+0x01,0x44,0x06,0x10,0x1C,0x40,0x81,0x02,0x44,0x0A,
+0x10,0x2C,0x40,0xC1,0x03,0x44,0x0E,0x10,0x3C,0x41,
+0x01,0x04,0x44,0x12,0x10,0x4C,0x41,0x41,0x05,0x44,
+0x16,0x10,0x5C,0x41,0x81,0x06,0x44,0x1A,0x10,0x6C,
+0x41,0xC1,0x07,0x44,0x1E,0x10,0x7C,0x42,0x01,0x08,
+0x44,0x22,0x10,0x8C,0x42,0x41,0x09,0x44,0x27,0xD0,
+0xEA,0x44,0xA5,0x15,0x64,0x63,0x51,0x97,0x47,0xC5,
+0x1F,0x74,0x97,0x92,0x79,0x4A,0x85,0x2A,0xE4,0xAD,
+0x13,0x1E,0x4C,0x99,0x33,0xA4,0xD4,0x93,0x69,0x4E,
+0x05,0x38,0xA4,0xE9,0xD3,0xCF,0x4F,0x51,0x3E,0x14,
+0xFB,0x94,0x05,0x50,0xB5,0x49,0x35,0x3E,0x55,0x66,
+0x56,0x6D,0x60,0x35,0x9A,0xD6,0xD6,0x5C,0xF9,0x79,
+0xC6,0x01,0x18,0x62,0x62,0xFD,0x8E,0xA6,0x44,0xD9,
+0x3E,0x65,0x79,0x96,0xE6,0x5F,0x19,0x91,0x66,0x85,
+0x9E,0x76,0x8D,0x1A,0x9D,0x6C,0x25,0xB7,0x56,0xF7,
+0x5C,0x3B,0x71,0x8D,0xCD,0x07,0x3F,0xDD,0x2E,0x75,
+0x7D,0xD8,0x57,0x74,0x9D,0xFB,0x79,0x11,0xE8,0x87,
+0xB3,0x1F,0x12,0x7D,0x59,0xF9,0x27,0xF6,0xE0,0x36,
+0x81,0xB6,0x0A,0xD8,0x3A,0xE1,0x2B,0x85,0x86,0x17,
+0x08,0x5F,0x61,0x90,0x86,0x7A,0x1E,0x28,0x80,0xE2,
+0x3D,0x89,0xD6,0x2A,0xF8,0xB9,0xE3,0x18,0x8C,0xAE,
+0x36,0x58,0xE2,0xA3,0xAD,0x8F,0x4A,0x3E,0xF9,0x0E,
+0xE4,0x6A,
+};
+*/
+/* font index size: 392 bytes */
+/*
+const ILI9341_t3_font_t Arial_28 = {
+       Arial_28_index,
+       0,
+       Arial_28_data,
+       1,
+       0,
+       32,
+       255,
+       0,
+       0,
+       14,
+       6,
+       6,
+       4,
+       6,
+       6,
+       43,
+       28
+};
+*/
+
+
+static const unsigned char Arial_32_data[] = {
+0x00,0x00,0x00,0x18,0x02,0x40,0xA0,0x1D,0xBF,0xBF,
+0x1E,0x7D,0x63,0x48,0x57,0x80,0x06,0x16,0x4A,0xA1,
+0xBE,0x1E,0xF0,0xF3,0x83,0x43,0x03,0x00,0x0C,0x40,
+0x00,0x31,0x00,0x0F,0x07,0x80,0x0F,0x87,0x8A,0x00,
+0xF0,0x78,0x00,0xF0,0x78,0x57,0xFF,0xFF,0xFD,0x01,
+0xE0,0xF0,0x48,0x3C,0x1E,0x05,0x7F,0xFF,0xFF,0xC0,
+0x78,0x3C,0x05,0x0F,0x07,0x80,0x07,0x87,0xC0,0x20,
+0xF0,0x78,0x00,0x0A,0x4C,0x5E,0x31,0x00,0x0C,0x00,
+0x01,0xF8,0x00,0x7F,0xF0,0x07,0xFF,0xE0,0x7F,0xFF,
+0x03,0xE6,0xFC,0x3E,0x31,0xE1,0xE1,0x8F,0x8F,0x0C,
+0x3C,0x78,0x61,0x88,0x78,0x60,0x01,0xE3,0x00,0x0F,
+0xD8,0x00,0x3F,0xE0,0x00,0xFF,0xE0,0x01,0xFF,0x80,
+0x03,0xFF,0x00,0x0D,0xF8,0x00,0x63,0xE0,0x03,0x0F,
+0x40,0x03,0x07,0x8C,0x18,0x3D,0xE0,0xC1,0xEF,0x86,
+0x0F,0x7C,0x30,0xF9,0xF1,0x8F,0x8F,0xCC,0xFC,0x3F,
+0xFF,0xC0,0xFF,0xFC,0x03,0xFF,0xC0,0x07,0xF8,0x14,
+0x00,0xC0,0x00,0x11,0x40,0x40,0x4E,0x0F,0x80,0x00,
+0xE0,0x07,0xF8,0x00,0x3C,0x00,0xFF,0x80,0x07,0x00,
+0x3C,0x78,0x01,0xE0,0x07,0x07,0x00,0x38,0x01,0xC0,
+0x70,0x0F,0x00,0x38,0x0E,0x01,0xC0,0x08,0xE0,0x38,
+0x0E,0x00,0x1C,0x07,0x03,0x80,0x03,0x80,0xE0,0xF0,
+0x00,0x70,0x1C,0x1C,0x00,0x07,0x07,0x07,0x80,0x00,
+0xF1,0xE0,0xE0,0x00,0x0F,0xF8,0x3C,0x00,0x01,0xFE,
+0x07,0x03,0xE0,0x0F,0x81,0xC1,0xFE,0x00,0x00,0x38,
+0x3F,0xE0,0x00,0x0E,0x0F,0x1E,0x00,0x03,0xC1,0xC1,
+0xC0,0x00,0x70,0x70,0x1C,0x00,0x1E,0x0E,0x03,0x80,
+0x03,0x81,0xC0,0x70,0x00,0xF0,0x38,0x0E,0x00,0x1C,
+0x07,0x01,0xE0,0x00,0xE0,0x1C,0x07,0x00,0x38,0x01,
+0xC1,0xC0,0x0F,0x00,0x3C,0x78,0x01,0xC0,0x03,0xFE,
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+0x01,0xF1,0xE0,0x07,0x8E,0x00,0x1C,0xF0,0x00,0xFA,
+0xFF,0xFF,0xF9,0xF0,0x00,0x07,0xC0,0x06,0x1E,0x00,
+0x7C,0xF8,0x07,0xC3,0xF0,0x7E,0x1F,0xFF,0xE0,0x7F,
+0xFE,0x00,0xFF,0xE0,0x01,0xFC,0x00,0x06,0xC0,0x20,
+0x1A,0x03,0xF8,0x1F,0xE0,0xFF,0x87,0xFE,0x1F,0x05,
+0x0F,0x02,0xBF,0xF9,0xA3,0xC0,0xD1,0xE0,0x58,0xF0,
+0x00,0x0A,0x42,0x5B,0xB2,0x03,0xF0,0x00,0x3F,0xE7,
+0x87,0xFF,0xFC,0x7F,0xFF,0xE3,0xF0,0xFF,0x3E,0x01,
+0xFC,0x3C,0x00,0xFE,0xF8,0x00,0x7B,0xC0,0x03,0xE1,
+0xE0,0x07,0xCF,0x80,0x7E,0x3F,0x0F,0xF8,0x1F,0xFF,
+0xF0,0x7F,0xE7,0x80,0xFE,0x3C,0x00,0x01,0xE6,0x00,
+0x0F,0x3C,0x00,0xF1,0xF0,0x0F,0x87,0xC0,0xFC,0x3F,
+0xFF,0xC0,0xFF,0xFC,0x03,0xFF,0xC0,0x07,0xF8,0x00,
+0x09,0x40,0x60,0x31,0xBE,0x00,0x03,0xC0,0x00,0x78,
+0x7C,0x0F,0x3F,0xE1,0xEF,0xFE,0x3F,0xFF,0xE7,0xF0,
+0x7C,0xFC,0x07,0xE3,0xE0,0x0F,0xDF,0x00,0x3F,0x7C,
+0x00,0xF8,0xF0,0x03,0xC0,0x02,0x40,0x60,0x15,0x5F,
+0x61,0xBF,0xBF,0xBF,0x1E,0x04,0xD3,0xDB,0x95,0x40,
+0xFB,0x00,0x68,0x3F,0x41,0xFA,0x0F,0xC0,0x78,0x3E,
+0x7F,0x3F,0xCF,0xE3,0xF0,0x09,0xC0,0x60,0x2D,0xBE,
+0x00,0x02,0x3C,0x00,0x03,0xC0,0x3E,0x3C,0x07,0xC3,
+0xC0,0xF8,0x3C,0x1F,0x03,0xC3,0xE0,0x3C,0x7C,0x03,
+0xCF,0x80,0x3D,0xF0,0x03,0xFE,0x00,0x3F,0xF0,0x03,
+0xFF,0x80,0x3F,0x78,0x03,0xE7,0xC0,0x3C,0x3E,0x03,
+0xC1,0xE0,0x3C,0x1F,0x03,0xC0,0xF8,0x3C,0x07,0x83,
+0xC0,0x7C,0x3C,0x03,0xE3,0xC0,0x1E,0x3C,0x01,0xF3,
+0xC0,0x0F,0x80,0x02,0x40,0x60,0x15,0xBF,0xBF,0xBF,
+0xBF,0x5E,0x10,0x30,0x60,0x4C,0x00,0xFC,0x03,0xF0,
+0x79,0xFF,0x07,0xFE,0x3D,0xFF,0xC7,0xFF,0x9E,0xFF,
+0xF7,0xFF,0xCF,0xE0,0xFF,0x83,0xF7,0xE0,0x3F,0x80,
+0xFB,0xE0,0x0F,0x80,0x3D,0xF0,0x07,0x80,0x1F,0xBE,
+0x00,0x78,0x01,0xFB,0xE0,0x07,0x80,0x1F,0x1E,0x00,
+0x78,0x01,0xE0,0x09,0x30,0x60,0x30,0x00,0xFC,0x1E,
+0x7F,0xC3,0xDF,0xFC,0x7F,0xFF,0xCF,0xE0,0xF9,0xF8,
+0x0F,0xC7,0xC0,0x1F,0xBE,0x00,0x7E,0xF8,0x01,0xF1,
+0xE0,0x07,0x80,0x0A,0x30,0x40,0x30,0x01,0xF8,0x00,
+0x3F,0xF0,0x07,0xFF,0xE0,0x7F,0xFF,0x83,0xF0,0xFC,
+0x3E,0x01,0xF1,0xE0,0x07,0x9F,0x00,0x3D,0xBE,0x00,
+0x1E,0xF0,0x00,0xF7,0xC0,0x0F,0x9E,0x00,0x78,0xF8,
+0x07,0xC3,0xF0,0xFC,0x1F,0xFF,0xE0,0x7F,0xFE,0x00,
+0xFF,0xC0,0x01,0xF8,0x00,0x0A,0x42,0x7B,0xB2,0x00,
+0xF8,0x07,0x9F,0xF8,0x3D,0xFF,0xE1,0xEF,0xFF,0x8F,
+0xF0,0xFC,0x7E,0x01,0xF3,0xF0,0x07,0x9F,0x00,0x3C,
+0xF8,0x00,0xFD,0xF0,0x00,0xF8,0xF8,0x01,0xE7,0xE0,
+0x1F,0x3F,0xC3,0xF1,0xFF,0xFF,0x0F,0x7F,0xF0,0x79,
+0xFF,0x03,0xC7,0xE0,0x37,0xC0,0x00,0x23,0xC0,0x00,
+0x00,0x0A,0x42,0x5B,0xB2,0x01,0xF0,0x00,0x7F,0xE7,
+0x87,0xFF,0xBC,0x7F,0xFD,0xE3,0xF0,0xFF,0x3E,0x01,
+0xF9,0xE0,0x0F,0xCF,0x00,0x3E,0xF0,0x01,0xFD,0xF0,
+0x00,0xF8,0x78,0x01,0xF3,0xE0,0x1F,0x8F,0xC3,0xFC,
+0x3F,0xFF,0xE0,0xFF,0xEF,0x03,0xFE,0x78,0x07,0xC3,
+0xF4,0x00,0x03,0xE0,0x00,0x03,0xC0,0x06,0xB0,0x60,
+0x1E,0x03,0xE3,0x9F,0xEE,0xFF,0xBF,0xFC,0xFE,0x34,
+0x7C,0x03,0x7C,0x01,0xBE,0x00,0x9F,0x00,0x00,0x09,
+0x30,0x40,0x2C,0x03,0xF0,0x01,0xFF,0x80,0x7F,0xFC,
+0x1F,0xFF,0x87,0xC1,0xF8,0xF0,0x1F,0x1E,0x01,0x83,
+0xC0,0x00,0x7E,0x00,0x07,0xF8,0x00,0xFF,0xE0,0x0F,
+0xFF,0x00,0x7F,0xF0,0x03,0xFF,0x00,0x07,0xF0,0x00,
+0x3E,0x30,0x03,0xDE,0x00,0x7B,0xE0,0x1F,0x3E,0x07,
+0xC7,0xFF,0xF8,0x7F,0xFE,0x07,0xFF,0x80,0x3F,0xC0,
+0x05,0xBE,0x20,0x18,0x02,0x00,0xE1,0x83,0xC2,0xBF,
+0xF6,0x8F,0x0D,0x1E,0x01,0xE1,0x03,0xF8,0x1F,0xC0,
+0xFC,0x09,0x2E,0x60,0x31,0xBE,0x00,0x7E,0xF8,0x01,
+0xF1,0xE0,0x07,0xBC,0x01,0xF7,0xC0,0x7E,0xFC,0x1F,
+0xE1,0xFF,0xEF,0x1F,0xF9,0xE0,0xFC,0x3C,0x0A,0xAE,
+0x20,0x2E,0xF0,0x00,0x7C,0xBC,0x00,0x7A,0x4F,0x00,
+0x79,0x03,0xC0,0x78,0x90,0xF0,0x78,0x48,0x3C,0x78,
+0x24,0x0F,0x78,0x10,0x03,0xF8,0x09,0x00,0xF8,0x00,
+0x10,0xAE,0x00,0x43,0x1E,0x00,0x7C,0x00,0xF7,0x80,
+0x1F,0x00,0x7E,0x1E,0x01,0xFC,0x03,0xC7,0x80,0x77,
+0x01,0xF0,0xF0,0x1D,0xE0,0x78,0x3C,0x0F,0x78,0x1E,
+0x07,0x83,0xDE,0x0F,0x81,0xE0,0xE3,0x83,0xC0,0x78,
+0x78,0xF0,0xF1,0x01,0xE3,0xC7,0x8F,0x00,0x78,0xE0,
+0xE3,0xC0,0x0E,0x78,0x3D,0xE0,0x03,0xDE,0x0F,0x78,
+0x00,0xF7,0x03,0xDE,0x00,0x1D,0xC0,0x77,0x02,0x00,
+0xFE,0x03,0xF8,0x12,0x03,0xE0,0x0F,0x80,0x0B,0x2E,
+0x00,0x2C,0x7C,0x00,0x78,0x7C,0x01,0xF0,0x7C,0x07,
+0xC0,0xF8,0x1F,0x00,0xF8,0x3C,0x00,0xF8,0xF8,0x00,
+0xF3,0xE0,0x01,0xFF,0x80,0x01,0xFE,0x00,0x01,0xFC,
+0x04,0x00,0x7E,0x00,0x00,0xFE,0x00,0x03,0xFC,0x00,
+0x0F,0xFC,0x00,0x1E,0x7C,0x00,0x7C,0x78,0x01,0xF0,
+0xF8,0x07,0xC0,0xF8,0x0F,0x00,0xF8,0x3E,0x00,0xF0,
+0xF8,0x01,0xF3,0xE0,0x01,0xF0,0x0A,0xC0,0x1B,0xAA,
+0xF0,0x00,0x79,0xE0,0x03,0xE7,0x80,0x0F,0x1F,0x00,
+0x3C,0x3C,0x01,0xF0,0xF0,0x07,0x81,0xE0,0x1E,0x07,
+0x80,0xF8,0x1F,0x03,0xC0,0x3C,0x0F,0x00,0xF0,0x7C,
+0x40,0x3C,0x3C,0x00,0xF9,0xF0,0x01,0xE7,0x80,0x07,
+0xDE,0x00,0x0F,0x70,0x20,0x07,0xF8,0x10,0x01,0xF8,
+0x00,0x03,0xE0,0x20,0x01,0xE0,0x00,0x0F,0x80,0x00,
+0x3C,0x00,0x01,0xF0,0x00,0x0F,0x80,0x03,0xFE,0x00,
+0x0F,0xF0,0x00,0x1F,0x80,0x00,0x7C,0x00,0x00,0x0A,
+0x2E,0x20,0x2D,0x4F,0xFF,0xFC,0x00,0x07,0xC0,0x00,
+0x7C,0x00,0x07,0xC0,0x00,0x7C,0x00,0x07,0xE0,0x00,
+0x3E,0x00,0x03,0xE0,0x00,0x3E,0x00,0x03,0xE0,0x00,
+0x3E,0x00,0x03,0xE0,0x00,0x3E,0x00,0x03,0xF0,0x00,
+0x1F,0x00,0x01,0xF0,0x00,0x2B,0xFF,0xFF,0xC0,0x06,
+0x52,0x3B,0x9E,0x01,0xF0,0x1F,0x81,0xFC,0x1F,0xE0,
+0xF8,0xD0,0xF0,0xA0,0xF0,0x0F,0x00,0xF8,0x1F,0x81,
+0x1E,0x00,0xFC,0x01,0xF0,0x40,0xF0,0x68,0x78,0x50,
+0x78,0x03,0xE2,0x01,0xFC,0x07,0xE0,0x1F,0x01,0xD2,
+0x9B,0x97,0xBF,0x7E,0xFD,0xFB,0xF3,0x80,0x06,0x52,
+0x5B,0x9E,0xF8,0x07,0xE0,0x47,0xF0,0x07,0xC3,0x43,
+0xC2,0x83,0xC0,0x0F,0x00,0x7C,0x01,0xFC,0x00,0x78,
+0x0F,0xC0,0xF8,0x07,0x80,0x7C,0x68,0x78,0x50,0x78,
+0x07,0xC2,0x3F,0x81,0xF8,0x0F,0x80,0x0B,0x10,0x45,
+0xB4,0x0F,0x80,0x00,0x7F,0xC0,0x09,0xFF,0xE0,0x37,
+0xFF,0xE1,0xEF,0x0F,0xFF,0xD8,0x07,0xFF,0x20,0x07,
+0xFC,0x00,0x03,0xE0,};
+/* font data size: 4974 bytes */
+
+static const unsigned char Arial_32_index[] = {
+0x00,0x00,0x01,0x00,0x20,0x01,
+0xC0,0x24,0x82,0x8C,0x25,0x61,0x95,0x0C,0xE0,0x71,
+0xC3,0xE4,0x20,0xB1,0x10,0x08,0xA4,0x45,0xE2,0x34,
+0x12,0x90,0xA2,0x05,0x46,0x2F,0x21,0xA3,0x0E,0x18,
+0x78,0x64,0x15,0x22,0x09,0x21,0x49,0xA8,0x4D,0xD2,
+0x74,0x94,0x9C,0xA6,0xA5,0x73,0x2D,0xB9,0xA4,0xCD,
+0xE2,0x73,0x63,0xCC,0x9F,0xA5,0x00,0xA8,0x1F,0x43,
+0xFA,0x26,0x11,0x42,0x8C,0x24,0x97,0xA5,0x09,0x2F,
+0x49,0xD2,0x51,0xA2,0x9B,0x15,0xAC,0xB3,0xA5,0xD0,
+0xAE,0xDD,0x7C,0xAC,0x43,0x66,0x23,0x4F,0x5B,0x0E,
+0xDD,0xB6,0xF5,0x38,0x21,0xC2,0xEE,0x36,0x71,0xF3,
+0x92,0x5D,0x18,0xEC,0x17,0x7A,0xBC,0xA9,0xEC,0x2F,
+0x79,0x7D,0xF3,0xF8,0x5F,0xD6,0xFF,0xF8,0x21,0xC1,
+0x32,0x0F,0xF0,0x9D,0x86,0x8C,0x42,0x62,0x83,0x15,
+0x78,0xCA,0x46,0xA6,0x38,0x91,0xE4,0x91,0x94,0x9D,
+0xA5,0x93,0x2F,0xB9,0x91,0x4C,0xB2,0x6A,0x60,
+};
+/* font index size: 155 bytes */
+
+const ILI9341_t3_font_t Arial_32 = {
+       Arial_32_index,
+       0,
+       Arial_32_data,
+       1,
+       0,
+       32,
+       126,
+       0,
+       0,
+       13,
+       6,
+       6,
+       4,
+       6,
+       6,
+       48,
+       32
+};
+
+static const unsigned char Arial_36_data[] = {
+0x00,0x00,0x00,0x1C,0x03,0x48,0x80,0x1D,0xBF,0xD7,
+0xE7,0xF5,0xEC,0x7A,0x0E,0xA0,0x2F,0xF0,0x06,0x9A,
+0x4B,0xA5,0xBF,0x1F,0xA7,0x87,0x9C,0x1E,0x70,0x30,
+0x0D,0x48,0x20,0x38,0x00,0x78,0x0F,0x00,0x0E,0x01,
+0xE0,0x03,0xC0,0x3C,0x00,0x78,0x07,0x10,0x01,0xE0,
+0x3C,0x00,0x38,0x07,0x88,0x01,0xE0,0x1C,0x00,0x3C,
+0x07,0x85,0x7F,0xFF,0xFF,0xE0,0x3C,0x07,0x82,0x00,
+0xE0,0x1E,0x00,0x3C,0x03,0x81,0x00,0xF0,0x1E,0x00,
+0x1C,0x03,0xC0,0x07,0x80,0x78,0x15,0xFF,0xFF,0xFF,
+0x87,0x80,0x78,0x00,0xF0,0x0E,0x01,0x03,0xC0,0x78,
+0x00,0x70,0x0F,0x00,0x83,0xC0,0x38,0x00,0x78,0x0F,
+0x00,0x41,0xC0,0x3C,0x00,0x0B,0xD4,0x5E,0x39,0x00,
+0x07,0x00,0x00,0x1F,0xE0,0x00,0xFF,0xF8,0x01,0xFF,
+0xFC,0x03,0xFF,0xFE,0x07,0xE7,0x3F,0x0F,0xC7,0x1F,
+0x0F,0x87,0x0F,0x8F,0x07,0x0F,0x8F,0x07,0x07,0x8F,
+0x07,0x07,0x21,0xE0,0xE0,0x01,0xF0,0xE0,0x01,0xF8,
+0xE0,0x00,0xFE,0xE0,0x00,0x7F,0xE0,0x00,0x3F,0xFE,
+0x00,0x0F,0xFF,0x80,0x03,0xFF,0xC0,0x00,0xFF,0xE0,
+0x00,0xE7,0xF0,0x00,0xE1,0xF8,0x00,0xE0,0xF8,0x00,
+0xE0,0x78,0xC0,0xE0,0x7B,0xC0,0xE0,0x7C,0x7C,0x1C,
+0x0F,0x7C,0x1C,0x1F,0x3E,0x1C,0x1F,0x3F,0x1C,0x3E,
+0x1F,0x9C,0x7E,0x0F,0xFF,0xFC,0x07,0xFF,0xF8,0x03,
+0xFF,0xF0,0x00,0x7F,0x80,0xA0,0x03,0x80,0x00,0x13,
+0x48,0x60,0x58,0x07,0xC0,0x00,0x1C,0x00,0x3F,0xE0,
+0x00,0x78,0x00,0xFF,0xE0,0x00,0xE0,0x03,0xE3,0xE0,
+0x03,0xC0,0x07,0x83,0xC0,0x07,0x00,0x1E,0x03,0xC0,
+0x1E,0x00,0x3C,0x07,0x80,0x38,0x00,0x78,0x0F,0x00,
+0xF0,0x00,0xF0,0x1E,0x01,0xC0,0x01,0xE0,0x3C,0x07,
+0x80,0x04,0x78,0x0F,0x03,0xC0,0x00,0xF0,0x1E,0x0F,
+0x00,0x01,0xE0,0x3C,0x1C,0x00,0x01,0xE0,0xF0,0x78,
+0x00,0x03,0xE3,0xE0,0xE0,0x00,0x03,0xFF,0x83,0xC0,
+0x00,0x03,0xFE,0x07,0x01,0xF0,0x01,0xF0,0x1E,0x0F,
+0xF8,0x00,0x00,0x38,0x3F,0xF8,0x00,0x00,0xF0,0xF8,
+0xF8,0x00,0x03,0xC1,0xE0,0xF0,0x00,0x07,0x83,0x80,
+0xF0,0x00,0x1E,0x0F,0x01,0xE0,0x00,0x38,0x1E,0x03,
+0xC0,0x00,0xF0,0x3C,0x03,0x80,0x01,0xC0,0x78,0x07,
+0x00,0x07,0x80,0xF0,0x1E,0x00,0x0E,0x01,0xE0,0x3C,
+0x00,0x3C,0x03,0xC0,0x78,0x00,0x70,0x03,0x80,0xF0,
+0x01,0xE0,0x07,0x83,0xC0,0x07,0x80,0x0F,0x8F,0x80,
+0x0F,0x00,0x0F,0xFE,0x00,0x3C,0x00,0x0F,0xF8,0x00,
+0x70,0x00,0x07,0xC0,0x0F,0x48,0x40,0x42,0x00,0x3F,
+0x80,0x00,0x01,0xFF,0xC0,0x00,0x07,0xFF,0xC0,0x00,
+0x1F,0xFF,0xC0,0x00,0x7E,0x0F,0x80,0x00,0xF8,0x0F,
+0x80,0x48,0x3C,0x03,0xE0,0x00,0x7C,0x07,0xC0,0x00,
+0xF8,0x1F,0x00,0x00,0xF8,0x7C,0x00,0x01,0xF9,0xF8,
+0x00,0x01,0xFF,0xE0,0x00,0x01,0xFF,0x00,0x00,0x01,
+0xFC,0x00,0x00,0x0F,0xF8,0x00,0x00,0x7F,0xF0,0x00,
+0x01,0xFB,0xF0,0x00,0x07,0xE3,0xF0,0x70,0x1F,0x03,
+0xF0,0xF8,0x7C,0x03,0xF1,0xE0,0xF8,0x03,0xE7,0xC3,
+0xE0,0x07,0xEF,0x87,0xC0,0x07,0xFE,0x0F,0x80,0x07,
+0xFC,0x1F,0x00,0x07,0xF0,0x3E,0x00,0x07,0xE0,0x7E,
+0x00,0x1F,0xC0,0x7C,0x00,0x7F,0xC0,0xFC,0x01,0xFF,
+0xC0,0xFE,0x0F,0xFF,0xC0,0xFF,0xFF,0xCF,0xE0,0xFF,
+0xFE,0x0F,0xC0,0xFF,0xF8,0x0F,0x00,0x3F,0x80,0x0C,
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+0x03,0xFC,0x03,0xF8,0x08,0x01,0xFC,0x03,0xF8,0x00,
+0x0F,0xC0,0x1F,0x80,0x40,0x07,0xC0,0x0F,0x80,0x00,
+0x0B,0xB4,0x20,0x32,0xFC,0x00,0x7E,0x7E,0x00,0x7C,
+0x3E,0x00,0xF8,0x1F,0x01,0xF0,0x1F,0x83,0xF0,0x0F,
+0x83,0xE0,0x07,0xC7,0xC0,0x07,0xCF,0x80,0x03,0xEF,
+0x80,0x01,0xFF,0x00,0x01,0xFE,0x00,0x00,0xFE,0x00,
+0x00,0x7C,0x00,0x00,0xFE,0x01,0x00,0x3F,0xE0,0x00,
+0x7D,0xF0,0x20,0x1F,0x1F,0x00,0x3E,0x0F,0x80,0x7C,
+0x07,0xC0,0xFC,0x07,0xC0,0xF8,0x03,0xE1,0xF0,0x01,
+0xF3,0xF0,0x01,0xFB,0xE0,0x00,0xF8,0x0B,0xC8,0x3B,
+0x33,0x1F,0x00,0x03,0xCF,0x00,0x07,0xCF,0x80,0x07,
+0x87,0x80,0x07,0xA0,0xF8,0x01,0xE0,0x78,0x03,0xE4,
+0x0F,0x80,0x78,0x07,0x80,0xF8,0x07,0xC0,0xF0,0x03,
+0xC0,0xF0,0x03,0xC1,0xE0,0x03,0xE1,0xE0,0x01,0xE3,
+0xE0,0x01,0xE3,0xC0,0x01,0xF3,0xC0,0x00,0xF7,0xC0,
+0x00,0xF7,0x80,0x00,0x7F,0x80,0x80,0x0F,0xE0,0x00,
+0x07,0xE0,0x12,0x00,0xF8,0x02,0x00,0x1E,0x00,0x40,
+0x07,0x80,0x01,0x3F,0x00,0x01,0xFF,0x00,0x01,0xFE,
+0x00,0x01,0xFC,0x00,0x01,0xF8,0x00,0x00,0x0B,0xB4,
+0x20,0x33,0x4F,0xFF,0xFF,0x80,0x00,0x1F,0x00,0x00,
+0x3E,0x00,0x00,0x7C,0x00,0x00,0xF8,0x00,0x01,0xF0,
+0x00,0x03,0xF0,0x00,0x07,0xE0,0x00,0x07,0xC0,0x00,
+0x0F,0x80,0x00,0x1F,0x00,0x00,0x3E,0x00,0x00,0x7C,
+0x00,0x00,0xFC,0x00,0x01,0xF8,0x00,0x03,0xF0,0x00,
+0x03,0xE0,0x00,0x07,0xC0,0x00,0x0F,0x80,0x00,0x2B,
+0xFF,0xFF,0xF8,0x07,0xDC,0x3B,0x22,0x00,0x7E,0x00,
+0xFE,0x01,0xFE,0x03,0xFE,0x03,0xE1,0x20,0x78,0x30,
+0x1F,0x05,0x83,0xC0,0x07,0x80,0x0F,0x80,0x7F,0x00,
+0x8F,0x80,0x0F,0xE0,0x01,0xF0,0x00,0xF0,0x14,0x0F,
+0x03,0x41,0xF0,0x48,0x1E,0x00,0x1F,0x00,0x1F,0xF0,
+0x0F,0xF0,0x07,0xF0,0x03,0xF0,0x01,0xDC,0xBB,0x1B,
+0xBF,0x7E,0xFD,0xFB,0xF7,0xD7,0x07,0x5C,0x3B,0x22,
+0xF8,0x01,0xFC,0x04,0x7F,0x80,0x0F,0x83,0x41,0xE0,
+0xB0,0x78,0x20,0x0F,0x00,0x1F,0x00,0x1F,0x00,0x1F,
+0xC0,0x03,0xE0,0x0F,0xC0,0x3E,0x00,0xF8,0x80,0x3C,
+0x34,0x1E,0x0B,0x07,0x80,0x1F,0x04,0x7F,0x80,0xFE,
+0x01,0xF0,0x00,0x0C,0x90,0x47,0x3A,0x0F,0xC0,0x00,
+0x8F,0xFE,0x00,0x67,0xFF,0xF0,0x7C,0x7F,0xFF,0xFF,
+0xDE,0x0F,0xFF,0xF6,0x00,0x7F,0xF1,0x00,0x03,0xF0,
+0x00,0x00,0x00,0x00,
+};
+/* font data size: 6384 bytes */
+
+static const unsigned char Arial_36_index[] = {
+0x00,0x00,0x01,0x00,0x24,0x01,0xE0,0x39,0x83,0x94,
+0x32,0x82,0x1C,0x11,0x20,0x95,0x45,0x14,0x2A,0xA1,
+0x5F,0x8B,0x24,0x59,0xE2,0xD4,0x18,0x28,0xD4,0x06,
+0xEC,0x3D,0xA2,0x23,0x92,0x54,0x9D,0x25,0x50,0x2C,
+0xC1,0x81,0x0C,0xCE,0x67,0x13,0x3F,0x9B,0x24,0xDA,
+0xE7,0x21,0x3B,0xAA,0x20,0x92,0x10,0x97,0x34,0xF8,
+0x29,0x31,0x4D,0x6A,0x88,0x57,0xE2,0xC7,0x16,0x4C,
+0xB5,0x15,0xEB,0x2F,0xB9,0x8C,0x0C,0xDA,0x6A,0x8B,
+0x65,0x5C,0x4C,0xE9,0x97,0x8D,0x3C,0xDD,0xED,0x2F,
+0xEB,0x84,0x9C,0x4A,0x23,0x1F,0x1F,0xE9,0x08,0x49,
+0x06,0x4A,0x72,0x8A,0x94,0x94,0xA7,0x65,0xCF,0x32,
+0xC9,0xB7,0x4E,0xCE,0x7E,0xF4,0x13,0xA3,0x5D,0x24,
+0xA9,0x3B,0x4B,0x5A,0x81,0x54,0x36,0xA8,0x95,0x65,
+0xAD,0x5D,0x7C,0xEC,0x6D,0x64,0xDB,0x4A,0x5A,0xB6,
+0xD9,0xD7,0x0E,0xBB,0xD5,0xF1,0xF0,0x45,0x86,0x3C,
+0x4C,0x62,0x8B,0x1A,0x38,0xEC,
+};
+/* font index size: 156 bytes */
+
+const ILI9341_t3_font_t Arial_36 = {
+        Arial_36_index,
+        0,
+        Arial_36_data,
+        1,
+        0,
+        32,
+        127,
+        0,
+        0,
+        13,
+        6,
+        6,
+        4,
+        6,
+        6,
+        55,
+        43
+};
+
+static const unsigned char Arial_37_data[] = {
+0x00,0x00,0x00,0x1C,0x03,0x4A,0x80,0x1D,0xBF,0xCF,
+0xF6,0xFE,0xBD,0x0F,0x51,0xD4,0x05,0xBE,0x07,0x1A,
+0x4C,0x25,0xBF,0x0F,0xD3,0xC3,0xC7,0x83,0x8E,0x07,
+0x00,0x0D,0xCA,0x20,0x38,0x00,0x78,0x07,0x00,0x07,
+0x80,0xF0,0x00,0x70,0x0F,0x10,0x01,0xE0,0x1E,0x00,
+0x1E,0x01,0xC0,0x01,0xE0,0x3C,0x00,0x1C,0x03,0xC2,
+0x00,0x78,0x07,0x85,0x7F,0xFF,0xFF,0xF0,0x1E,0x01,
+0xE0,0x01,0xE0,0x1C,0x00,0x1E,0x03,0xC0,0x01,0xC0,
+0x3C,0x08,0x07,0x80,0x78,0x00,0x78,0x07,0x00,0x07,
+0x80,0xF0,0x00,0x70,0x0F,0x01,0x5F,0xFF,0xFF,0xFC,
+0x1C,0x03,0xC0,0x03,0xC0,0x3C,0x00,0x3C,0x03,0x80,
+0x03,0xC0,0x78,0x02,0x07,0x00,0xF0,0x00,0xF0,0x0F,
+0x00,0x0F,0x00,0xE0,0x00,0xF0,0x1E,0x00,0x0E,0x01,
+0xE0,0x00,0x0C,0x58,0x5D,0xB9,0x00,0x03,0x00,0x00,
+0x0F,0xF0,0x00,0x3F,0xFE,0x00,0x3F,0xFF,0xC0,0x3F,
+0xFF,0xF0,0x3F,0x19,0xF8,0x1F,0x0C,0x3E,0x1F,0x06,
+0x1F,0x0F,0x83,0x07,0xC7,0x81,0x83,0xE3,0xC0,0xC1,
+0xE4,0x3C,0x0C,0x00,0x43,0xE0,0xC0,0x00,0xF8,0x60,
+0x00,0x7F,0x30,0x00,0x1F,0xF8,0x00,0x07,0xFF,0xC0,
+0x00,0xFF,0xF8,0x00,0x0F,0xFF,0x00,0x01,0xFF,0xC0,
+0x00,0xC7,0xF0,0x00,0x61,0xF8,0x00,0x30,0x7C,0x00,
+0x18,0x1F,0x18,0x0C,0x0F,0xCF,0xC0,0xC0,0xFB,0xF0,
+0x60,0x7C,0xF8,0x30,0x7C,0x7E,0x18,0x7E,0x1F,0x8C,
+0x7E,0x07,0xFF,0xFE,0x01,0xFF,0xFE,0x00,0x7F,0xFE,
+0x00,0x07,0xF8,0x05,0x80,0x0C,0x00,0x00,0x13,0xCA,
+0x60,0x5A,0x07,0xC0,0x00,0x1E,0x00,0x1F,0xF0,0x00,
+0x1E,0x00,0x3F,0xF8,0x00,0x3C,0x00,0x7C,0x7C,0x00,
+0x3C,0x00,0x78,0x3E,0x00,0x78,0x00,0x78,0x1E,0x00,
+0x70,0x00,0xF0,0x1E,0x00,0xF0,0x00,0xF0,0x0E,0x00,
+0xE0,0x00,0xF0,0x0E,0x01,0xE0,0x00,0xF0,0x0F,0x01,
+0xC0,0x00,0xF0,0x0F,0x03,0xC0,0x00,0xF0,0x0F,0x03,
+0x80,0x00,0xF0,0x1E,0x07,0x80,0x00,0xF0,0x1E,0x0F,
+0x00,0x00,0x70,0x1E,0x0F,0x00,0x00,0x78,0x3E,0x1E,
+0x00,0x00,0x7C,0x7C,0x1E,0x00,0x00,0x3F,0xF8,0x3C,
+0x0F,0xC0,0x1F,0xF0,0x38,0x1F,0xF0,0x07,0xC0,0x78,
+0x3F,0xF8,0x00,0x00,0x70,0x7C,0x7C,0x00,0x00,0xF0,
+0x78,0x3C,0x00,0x00,0xE0,0xF0,0x1E,0x00,0x01,0xE0,
+0xF0,0x1E,0x00,0x01,0xC0,0xF0,0x1E,0x00,0x03,0xC0,
+0xF0,0x1E,0x00,0x07,0x80,0xF0,0x1E,0x00,0x07,0x80,
+0xE0,0x1F,0x00,0x01,0xE0,0x1E,0x03,0xC0,0x03,0xC0,
+0x1E,0x03,0xC0,0x03,0x80,0x1E,0x03,0xC0,0x07,0x80,
+0x0F,0x07,0x80,0x07,0x00,0x0F,0x8F,0x80,0x0F,0x00,
+0x07,0xFF,0x00,0x0E,0x00,0x03,0xFE,0x00,0x1E,0x00,
+0x00,0xF8,0x00,0x0F,0x4A,0x40,0x44,0x00,0x1F,0x80,
+0x00,0x01,0xFF,0xC0,0x00,0x07,0xFF,0xC0,0x00,0x1F,
+0xFF,0xC0,0x00,0x3E,0x0F,0xC0,0x00,0xF8,0x0F,0x80,
+0x01,0xF0,0x0F,0x00,0x80,0x78,0x03,0xC0,0x20,0x1F,
+0x01,0xF0,0x00,0x1F,0x07,0xC0,0x00,0x3F,0x1F,0x00,
+0x00,0x3F,0xFC,0x00,0x00,0x3F,0xF0,0x00,0x00,0x7F,
+0xC0,0x00,0x00,0xFF,0x00,0x00,0x07,0xFE,0x00,0x00,
+0x1F,0xFE,0x00,0x00,0xFE,0x7E,0x06,0x03,0xF8,0x7E,
+0x1F,0x07,0xC0,0x7E,0x3E,0x1F,0x00,0xFE,0x7C,0x3E,
+0x00,0xFF,0xF0,0xF8,0x00,0xFF,0xE1,0xF0,0x00,0xFF,
+0x83,0xE0,0x00,0xFF,0x07,0xC0,0x00,0xFC,0x0F,0xC0,
+0x01,0xFC,0x0F,0x80,0x03,0xFC,0x1F,0x80,0x0F,0xFC,
+0x1F,0x80,0x7F,0xFC,0x3F,0x83,0xFD,0xFC,0x3F,0xFF,
+0xF3,0xF8,0x3F,0xFF,0xC3,0xF0,0x1F,0xFE,0x01,0xC0,
+0x0F,0xE0,0x01,0x00,0x02,0x9A,0x4C,0x15,0xBF,0x7E,
+0x5F,0x0E,0x06,0x5E,0x7B,0x22,0x00,0x70,0x07,0x00,
+0x7A,0x00,0xF2,0x01,0xE2,0x03,0xC2,0x07,0x80,0x7C,
+0x10,0x78,0x10,0xF8,0x10,0xF0,0x1B,0xF0,0x15,0xF0,
+0x10,0xF0,0x10,0xF8,0x10,0x78,0x03,0xE0,0x81,0xE0,
+0x80,0xF0,0x80,0x78,0x80,0x3C,0x00,0xF0,0x03,0x80,
+0x0E,0x06,0x5E,0x7B,0x22,0xF0,0x03,0x80,0x0E,0x00,
+0x78,0x01,0xC0,0x0F,0x04,0x07,0x84,0x83,0xC4,0x01,
+0xE4,0x01,0xF4,0x00,0xF6,0x00,0xF8,0x03,0xF0,0x07,
+0xE0,0x07,0xA0,0x0F,0xA0,0x0F,0x20,0x1E,0x01,0xF1,
+0x01,0xE0,0x1E,0x00,0xE0,0x0F,0x00,0x70,0x07,0x00,
+0x78,0x00,0x08,0x20,0x4A,0xA9,0x00,0x78,0x10,0x07,
+0x00,0x43,0x86,0x7D,0xCF,0x47,0xFF,0xF8,0xFF,0xF0,
+0x0F,0x80,0x0F,0xE0,0x0F,0x78,0x07,0x9E,0x07,0x8F,
+0x83,0xC3,0x80,0x40,0x80,0x0C,0x30,0x63,0x3D,0xA0,
+0x07,0x80,0x12,0x00,0x78,0x01,0x5F,0xFF,0xFF,0xFA,
+0x00,0x78,0x01,0x20,0x07,0x80,0x00,0x02,0x98,0xBC,
+0x9D,0x7F,0x83,0x8C,0x73,0xCE,0x30,0x06,0x8A,0x45,
+0x23,0x7F,0xFF,0x02,0x8A,0xA0,0x1D,0x7F,0x07,0x4A,
+0x00,0x1D,0x00,0x07,0xC0,0x01,0xD0,0x00,0xF0,0x01,
+0xC8,0x00,0xF2,0x00,0x38,0x80,0x1E,0x00,0x38,0x40,
+0x1E,0x10,0x07,0x04,0x03,0xC0,0x07,0x02,0x03,0xC0,
+0x80,0xE0,0x20,0x78,0x00,0xE0,0x10,0x78,0x04,0x1C,
+0x01,0x0F,0x00,0x1C,0x00,0x8F,0x00,0x00,0x0C,0x4A,
+0x40,0x38,0x00,0xFF,0x00,0x01,0xFF,0xE0,0x01,0xFF,
+0xF8,0x01,0xFF,0xFE,0x01,0xF8,0x1F,0x80,0xF8,0x07,
+0xC0,0xF8,0x01,0xF0,0x78,0x00,0x79,0x0F,0x80,0x07,
+0xD0,0xF0,0x00,0x3D,0xBF,0x00,0x03,0xF9,0xF0,0x00,
+0x3F,0x0F,0x00,0x03,0xD0,0xF8,0x00,0x7C,0x3C,0x00,
+0x3C,0x1F,0x00,0x3E,0x07,0xC0,0x3E,0x03,0xF0,0x3F,
+0x00,0xFF,0xFF,0x00,0x3F,0xFF,0x00,0x0F,0xFF,0x00,
+0x01,0xFC,0x00,0x06,0xCA,0xC0,0x38,0x00,0x3C,0x00,
+0x3C,0x01,0xF0,0x0F,0xC0,0x7F,0x03,0xFC,0x1F,0xF1,
+0xFB,0xDF,0xCF,0x7E,0x3D,0xE0,0xF7,0x03,0xD0,0x0F,
+0xD0,0x07,0xE8,0x03,0xF4,0x01,0xF0,0x00,0xF0,0x0C,
+0x4A,0x40,0x38,0x00,0xFF,0x00,0x01,0xFF,0xF0,0x03,
+0xFF,0xFC,0x03,0xFF,0xFF,0x03,0xF8,0x0F,0xC1,0xF0,
+0x03,0xF4,0x3E,0x00,0x1F,0x1E,0x00,0x07,0xA3,0xE0,
+0x00,0x7C,0x00,0x00,0x3E,0x00,0x00,0x1E,0x80,0x00,
+0x03,0xE0,0x00,0x03,0xE0,0x00,0x03,0xF0,0x00,0x03,
+0xF0,0x00,0x03,0xF0,0x00,0x03,0xF0,0x00,0x03,0xF0,
+0x00,0x03,0xF0,0x00,0x03,0xF0,0x00,0x03,0xF0,0x00,
+0x03,0xF0,0x00,0x07,0xF0,0x00,0x07,0xF0,0x00,0x07,
+0xF0,0x00,0x07,0xF0,0x00,0x03,0xE0,0x00,0x03,0xE0,
+0x00,0x03,0xF0,0x00,0x01,0xF0,0x00,0x02,0xBF,0xFF,
+0xFF,0xC0,0x0C,0x4A,0x40,0x38,0x00,0xFE,0x00,0x01,
+0xFF,0xE0,0x03,0xFF,0xF8,0x03,0xFF,0xFE,0x03,0xF8,
+0x1F,0x81,0xF0,0x07,0xC4,0x3E,0x00,0x3E,0x1E,0x00,
+0x0F,0x07,0x00,0x07,0x92,0x00,0x00,0xF8,0x00,0x01,
+0xF8,0x00,0x03,0xF8,0x00,0x1F,0xF8,0x00,0x0F,0xF0,
+0x00,0x07,0xFF,0x00,0x03,0xFF,0xC0,0x00,0x03,0xF0,
+0x00,0x00,0xFC,0x00,0x00,0x3E,0xA0,0x00,0x01,0xF3,
+0xC0,0x00,0xFC,0x7C,0x00,0x0F,0xC3,0xE0,0x01,0xF0,
+0xF8,0x01,0xF0,0x7F,0x03,0xF8,0x1F,0xFF,0xF8,0x07,
+0xFF,0xF8,0x00,0xFF,0xF0,0x00,0x1F,0xE0,0x00,0x0C,
+0xCA,0x20,0x38,0x00,0x00,0xF0,0x40,0x00,0x0F,0x80,
+0x00,0x07,0xE0,0x00,0x03,0xF8,0x20,0x00,0x3F,0xC0,
+0x00,0x1F,0xF0,0x00,0x0F,0xFC,0x00,0x03,0xDF,0x00,
+0x01,0xE7,0xC0,0x00,0xF9,0xF0,0x00,0x3C,0x7C,0x00,
+0x1E,0x1F,0x00,0x0F,0x87,0xC0,0x03,0xC1,0xF0,0x01,
+0xE0,0x7C,0x00,0xF8,0x1F,0x00,0x7C,0x07,0xC0,0x1E,
+0x01,0xF0,0x0F,0x00,0x7C,0x07,0xC0,0x1F,0x01,0xE0,
+0x07,0xC0,0xF0,0x01,0xF0,0x57,0xFF,0xFF,0xFF,0x40,
+0x00,0x7C,0x10,0x00,0x03,0xE0,0x0C,0x4A,0x40,0x39,
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+0xF0,0x40,0x3E,0x0D,0x07,0x81,0x20,0xF0,0x01,0xF0,
+0x23,0xFC,0x03,0xF8,0x03,0xE0,0x00,0x0D,0x10,0x47,
+0x3C,0x0F,0xE0,0x00,0x47,0xFF,0x80,0x19,0xFF,0xFC,
+0x0F,0x8F,0xFF,0xFF,0xFD,0xE0,0x7F,0xFF,0x30,0x03,
+0xFF,0xC4,0x00,0x0F,0xE0,0x00,0x00,0x00,0x00,
+};
+/* font data size: 6699 bytes */
+
+static const unsigned char Arial_37_index[] = {
+0x00,0x00,0x01,0x00,0x24,0x01,0xF0,0x42,0x03,0xE0,
+0x36,0x22,0x3E,0x12,0x30,0x9D,0xC5,0x54,0x2C,0xB1,
+0x70,0x8B,0xAC,0x5E,0x22,0xF6,0x19,0x40,0xDC,0xC7,
+0x2E,0x3F,0xE2,0x2F,0x92,0xD8,0xA1,0xC5,0x75,0x2D,
+0xB1,0x88,0x0D,0x06,0x68,0xD3,0x4E,0x1B,0xA4,0xDF,
+0x07,0x45,0x3C,0xCA,0x2B,0x12,0x7C,0x9A,0x65,0x0B,
+0xA9,0xE9,0x53,0x2A,0xB7,0x59,0xA2,0xD5,0x56,0xC0,
+0xB8,0xD6,0x0E,0xB0,0xD9,0x9B,0x2D,0x54,0x6E,0x7B,
+0x89,0x1D,0x72,0xF2,0xF7,0xDA,0x3F,0x46,0x01,0xF0,
+0x8D,0x8A,0x7C,0x79,0x24,0x97,0x2B,0xE9,0x68,0x4C,
+0x0A,0x62,0x93,0x42,0x9A,0x5C,0xD5,0xE7,0x4F,0x3F,
+0x2A,0x1B,0x51,0xFE,0x98,0xD4,0xE2,0xAA,0x15,0x5A,
+0xEA,0xED,0x58,0xCA,0xF1,0x57,0xB6,0xC4,0xB6,0x48,
+0xB4,0x7D,0xB6,0x2E,0x41,0x73,0x8B,0xC3,0xDE,0x7E,
+0xF8,0x98,0x17,0xC4,0x3E,0x38,0x32,0x8F,0x98,0xEC,
+0xE4,0x67,0x4F,0x41,0x7A,0x27,
+};
+/* font index size: 156 bytes */
+
+const ILI9341_t3_font_t Arial_37 = {
+        Arial_37_index,
+        0,
+        Arial_37_data,
+        1,
+        0,
+        32,
+        127,
+        0,
+        0,
+        13,
+        6,
+        6,
+        4,
+        6,
+        6,
+        56,
+        42
+};
+
+
+static const unsigned char Arial_38_data[] = {
+0x00,0x00,0x00,0x1E,0x02,0xCC,0xA0,0x1F,0xBF,0xDF,
+0xEF,0xDE,0xD7,0x50,0x2F,0xE0,0x07,0x1A,0x4C,0xA7,
+0x9F,0x8F,0xC3,0xE3,0xE7,0x87,0xE1,0xE0,0xF3,0xC1,
+0xC3,0x83,0x80,0x0E,0x4C,0x20,0x3A,0x00,0x38,0x03,
+0x8A,0x00,0x78,0x07,0x80,0x03,0x80,0x38,0x50,0x07,
+0x80,0x78,0x00,0x78,0x03,0x82,0xBF,0xFF,0xFF,0xFC,
+0x07,0x80,0x38,0x14,0x07,0x80,0x78,0x14,0x0F,0x00,
+0xF0,0x15,0xFF,0xFF,0xFF,0xE0,0xF0,0x0F,0x00,0x07,
+0x00,0x78,0x05,0x0F,0x00,0xF0,0x05,0x1E,0x01,0xE0,
+0x00,0x0C,0xDA,0x5D,0xBB,0x00,0x03,0x80,0x00,0x07,
+0xFC,0x00,0x07,0xFF,0xC0,0x07,0xFF,0xFC,0x03,0xFF,
+0xFF,0x81,0xFC,0xEF,0xE0,0x7C,0x38,0xFC,0x3F,0x0E,
+0x1F,0x21,0xF0,0x70,0x7C,0x78,0x1C,0x1E,0x1E,0x07,
+0x00,0x10,0xF8,0x38,0x00,0x3F,0x0E,0x00,0x07,0xE3,
+0x80,0x01,0xFE,0xE0,0x00,0x3F,0xF8,0x00,0x03,0xFF,
+0xC0,0x00,0x3F,0xFE,0x00,0x03,0xFF,0xC0,0x00,0x3F,
+0xFC,0x00,0x0E,0x7F,0x00,0x03,0x87,0xE0,0x00,0xE0,
+0xFA,0x00,0x07,0x03,0xE3,0x81,0xC0,0xFC,0xFC,0x0E,
+0x07,0xCF,0x83,0x83,0xE3,0xF0,0xE0,0xF8,0xFE,0x38,
+0x7E,0x1F,0xCE,0x7F,0x03,0xFF,0xFF,0x80,0x7F,0xFF,
+0xC0,0x07,0xFF,0xE0,0x00,0x7F,0xC0,0x2C,0x00,0x70,
+0x00,0x14,0xCC,0x60,0x5E,0x07,0xE0,0x00,0x07,0x00,
+0x07,0xFE,0x00,0x03,0xC0,0x03,0xFF,0xC0,0x00,0xE0,
+0x00,0xF9,0xF8,0x00,0x78,0x00,0x78,0x1E,0x00,0x3C,
+0x00,0x1E,0x03,0xC0,0x0F,0x00,0x11,0xE0,0x1E,0x00,
+0xF0,0x00,0x8F,0x00,0xF0,0x0F,0x00,0x04,0x78,0x07,
+0x80,0xF0,0x00,0x1E,0x01,0xE0,0x78,0x00,0x07,0x80,
+0x78,0x1C,0x00,0x00,0xF0,0x1E,0x0F,0x00,0x00,0x3C,
+0x0F,0x07,0x80,0x00,0x07,0xCF,0xC1,0xE0,0x00,0x01,
+0xFF,0xE0,0xF0,0x00,0x00,0x3F,0xF0,0x3C,0x07,0xE0,
+0x03,0xF0,0x1E,0x07,0xFC,0x00,0x00,0x07,0x83,0xFF,
+0x80,0x00,0x03,0xC1,0xF1,0xF0,0x00,0x00,0xF0,0x78,
+0x3E,0x00,0x00,0x78,0x3C,0x07,0x80,0x00,0x1C,0x0F,
+0x01,0xE0,0x00,0x0F,0x03,0xC0,0x3E,0x00,0x00,0xF0,
+0x1E,0x01,0xF0,0x00,0x0F,0x00,0xF0,0x0F,0x00,0x07,
+0x80,0x3C,0x03,0xC0,0x01,0xE0,0x0F,0x01,0xE0,0x00,
+0xF0,0x03,0xC0,0x78,0x00,0x3C,0x00,0x78,0x3E,0x00,
+0x1E,0x00,0x1F,0x1F,0x00,0x07,0x00,0x03,0xFF,0x80,
+0x03,0xC0,0x00,0x7F,0xC0,0x01,0xE0,0x00,0x07,0xC0,
+0x10,0x4C,0x40,0x46,0x00,0x1F,0xC0,0x00,0x00,0x3F,
+0xF8,0x00,0x00,0x3F,0xFE,0x00,0x00,0x3F,0xFF,0x80,
+0x00,0x3F,0x0F,0xE0,0x00,0x1F,0x01,0xF0,0x05,0x03,
+0xE0,0x1F,0x00,0x01,0xF8,0x0F,0x80,0x00,0x7C,0x0F,
+0x80,0x00,0x3F,0x0F,0xC0,0x00,0x0F,0xCF,0xC0,0x00,
+0x03,0xFF,0xC0,0x00,0x01,0xFF,0x80,0x00,0x00,0x7F,
+0x00,0x00,0x00,0xFF,0xC0,0x00,0x00,0xFF,0xF0,0x00,
+0x01,0xFD,0xFC,0x00,0x01,0xFC,0x7E,0x06,0x01,0xF8,
+0x1F,0x87,0xC0,0xF8,0x0F,0xE3,0xE0,0xF8,0x03,0xFB,
+0xF0,0x7C,0x00,0xFF,0xF0,0x7C,0x00,0x3F,0xF8,0x3E,
+0x00,0x0F,0xF8,0x1F,0x00,0x03,0xFC,0x0F,0xC0,0x00,
+0xFC,0x03,0xE0,0x00,0x7F,0x01,0xF8,0x00,0x7F,0xC0,
+0xFC,0x00,0x7F,0xF0,0x3F,0x00,0x7F,0xFC,0x1F,0xE1,
+0xFF,0x7F,0x07,0xFF,0xFF,0x1F,0xC1,0xFF,0xFE,0x07,
+0xC0,0x3F,0xFE,0x01,0xC0,0x07,0xF8,0x00,0x40,0x03,
+0x1A,0x4C,0x95,0xBF,0xE3,0xC0,0x06,0x62,0x7A,0xA4,
+0x00,0x70,0x07,0x80,0x38,0x03,0xD0,0x07,0x90,0x0F,
+0x10,0x1E,0x10,0x3C,0x03,0xE0,0x83,0xC0,0x97,0xC0,
+0x87,0x80,0xDF,0x80,0x8F,0x80,0x87,0x80,0x97,0xC0,
+0x1E,0x04,0x1F,0x00,0x78,0x03,0xE1,0x01,0xE1,0x00,
+0xF1,0x00,0x78,0x01,0xE0,0x07,0x00,0x3C,0x00,0xE0,
+0x06,0xE2,0x7A,0xA4,0xF0,0x01,0xE0,0x03,0x80,0x0F,
+0x01,0x03,0xC0,0x80,0xF0,0x40,0x3C,0x00,0xF8,0x01,
+0xE2,0x00,0xF8,0x01,0xE5,0x00,0xF8,0x01,0xED,0x00,
+0xF8,0x03,0xF0,0x01,0xEA,0x01,0xF0,0x07,0x90,0x07,
+0xC0,0x1E,0x00,0xF8,0x80,0x78,0x40,0x78,0x20,0x78,
+0x03,0xC0,0x0E,0x00,0x78,0x01,0xC0,0x00,0x08,0xA0,
+0x4B,0x2B,0x20,0x78,0x02,0x0E,0x19,0xE3,0x9E,0x7E,
+0xEF,0x9F,0xFF,0xF3,0xFF,0xF8,0x1F,0xE0,0x03,0xF0,
+0x01,0xFE,0x00,0x7B,0xC0,0x3C,0xF8,0x1E,0x1F,0x03,
+0x83,0x80,0x40,0x80,0x0C,0xB2,0x63,0x3F,0xA0,0x07,
+0xC0,0x09,0x00,0x3E,0x00,0x5F,0xFF,0xFF,0xFF,0x40,
+0x0F,0x80,0x12,0x00,0x7C,0x00,0x02,0x9A,0xBC,0x1F,
+0x7F,0xA3,0x9C,0xF3,0x8C,0x00,0x07,0x0A,0x45,0xA5,
+0x7F,0xFF,0x80,0x02,0x8A,0xA0,0x1F,0x7F,0x07,0xCC,
+0x00,0x1E,0x00,0x1E,0x00,0x1D,0x00,0x07,0x80,0x07,
+0x24,0x01,0xE0,0x01,0xC4,0x00,0x78,0x00,0x70,0x90,
+0x1E,0x12,0x07,0x80,0x07,0x02,0x41,0xE0,0x48,0x78,
+0x00,0x70,0x09,0x1E,0x01,0x27,0x80,0x07,0x00,0x21,
+0xE0,0x01,0xC0,0x04,0x78,0x00,0x0C,0xCC,0x40,0x3A,
+0x00,0x7F,0x00,0x00,0x7F,0xF0,0x00,0x7F,0xFF,0x00,
+0x3F,0xFF,0xE0,0x0F,0xC1,0xFC,0x07,0xC0,0x1F,0x10,
+0x7C,0x00,0x7C,0x1E,0x00,0x0F,0xA1,0xF0,0x00,0x7C,
+0x7C,0x00,0x0F,0x1E,0x00,0x03,0xFB,0xF0,0x00,0x1F,
+0xBF,0x80,0x00,0xF9,0xE0,0x00,0x3E,0x7C,0x00,0x0F,
+0x43,0xE0,0x00,0xF8,0x78,0x00,0x3E,0x1F,0x00,0x1F,
+0x07,0xE0,0x07,0xC0,0xFC,0x03,0xE0,0x3F,0x83,0xF8,
+0x07,0xFF,0xFC,0x00,0xFF,0xFE,0x00,0x0F,0xFE,0x00,
+0x00,0xFE,0x00,0x07,0x4C,0xC0,0x3B,0x00,0x07,0x80,
+0x1F,0x00,0x7E,0x01,0xFC,0x07,0xF8,0x3F,0xF0,0xFF,
+0xE7,0xFF,0xDF,0xEF,0xBF,0x1F,0x7C,0x3E,0xE0,0x7D,
+0x00,0xFE,0x80,0x3F,0xA0,0x0F,0xE8,0x03,0xF2,0x00,
+0xF8,0x0C,0xCC,0x40,0x3A,0x00,0x7F,0x80,0x00,0xFF,
+0xF8,0x00,0x7F,0xFF,0x80,0x3F,0xFF,0xF0,0x1F,0xC0,
+0xFE,0x0F,0xC0,0x1F,0x83,0xE0,0x03,0xF1,0xF0,0x00,
+0x7C,0x7C,0x00,0x0F,0x1F,0x00,0x03,0xE7,0x80,0x00,
+0xFB,0xE0,0x00,0x3E,0x00,0x00,0x0F,0x40,0x00,0x00,
+0xF8,0x00,0x00,0x7C,0x00,0x00,0x3F,0x20,0x00,0x03,
+0xF0,0x00,0x01,0xF8,0x00,0x01,0xFC,0x00,0x00,0xFE,
+0x00,0x00,0x7F,0x00,0x00,0x3F,0x80,0x00,0x1F,0x80,
+0x00,0x0F,0xC0,0x00,0x0F,0xE0,0x00,0x07,0xF0,0x00,
+0x03,0xF8,0x00,0x01,0xFC,0x00,0x00,0x7E,0x00,0x00,
+0x3F,0x00,0x00,0x1F,0x80,0x00,0x07,0xFF,0xFF,0xFD,
+0x7F,0xFF,0xFF,0xC0,0x0C,0xCC,0x40,0x3A,0x00,0x7F,
+0x00,0x00,0xFF,0xF0,0x00,0x7F,0xFF,0x00,0x3F,0xFF,
+0xE0,0x1F,0xC1,0xF8,0x0F,0xC0,0x3F,0x03,0xE0,0x07,
+0xE4,0xBE,0x00,0x1F,0x07,0x00,0x07,0xC8,0x00,0x00,
+0x3E,0x00,0x00,0x1F,0x00,0x00,0x0F,0xC0,0x00,0x0F,
+0xE0,0x00,0x3F,0xF0,0x00,0x0F,0xF0,0x00,0x03,0xFF,
+0x00,0x00,0xFF,0xF0,0x00,0x40,0xFE,0x00,0x00,0x0F,
+0xC0,0x00,0x01,0xF0,0x00,0x00,0x7F,0x20,0x00,0x01,
+0xF3,0xC0,0x00,0x7D,0xF0,0x00,0x1F,0x3E,0x00,0x07,
+0xCF,0x80,0x03,0xE3,0xF0,0x01,0xF8,0x7E,0x00,0xFC,
+0x1F,0xE0,0xFF,0x03,0xFF,0xFF,0x80,0x7F,0xFF,0x80,
+0x07,0xFF,0xC0,0x00,0x7F,0x80,0x00,0x0D,0x4C,0x20,
+0x3A,0x00,0x00,0x78,0x00,0x00,0x1F,0x04,0x00,0x00,
+0xFC,0x00,0x00,0x3F,0x80,0x00,0x0F,0xF0,0x40,0x00,
+0x7F,0xC0,0x00,0x1F,0xF8,0x00,0x07,0xDF,0x00,0x00,
+0xF3,0xE0,0x00,0x3C,0x7C,0x00,0x0F,0x8F,0x80,0x01,
+0xE1,0xF0,0x00,0x78,0x3E,0x00,0x1F,0x07,0xC0,0x03,
+0xC0,0xF8,0x00,0xF0,0x1F,0x00,0x3E,0x03,0xE0,0x0F,
+0x80,0x7C,0x01,0xE0,0x0F,0x80,0x7C,0x01,0xF0,0x1F,
+0x00,0x3E,0x03,0xC0,0x07,0xC0,0xF8,0x00,0xF8,0x2B,
+0xFF,0xFF,0xFF,0xD0,0x00,0x0F,0x82,0x00,0x00,0x3E,
+0x00,0x0C,0xCC,0x40,0x3A,0x07,0xFF,0xFF,0x50,0x7F,
+0xFF,0xF8,0x1E,0x00,0x00,0x91,0xF0,0x00,0x04,0x8F,
+0x00,0x00,0x07,0xC7,0xF0,0x01,0xF7,0xFF,0x00,0x7F,
+0xFF,0xF0,0x1F,0xFF,0xFE,0x07,0xF8,0x3F,0xC3,0xF8,
+0x03,0xF8,0xFC,0x00,0x7E,0x1E,0x00,0x0F,0xF4,0x00,
+0x00,0x3E,0xF8,0x00,0x0F,0xBF,0x00,0x03,0xE7,0xC0,
+0x01,0xF9,0xF0,0x00,0x7C,0x7E,0x00,0x3F,0x0F,0xC0,
+0x1F,0x81,0xFC,0x1F,0xC0,0x7F,0xFF,0xE0,0x07,0xFF,
+0xF0,0x00,0xFF,0xF8,0x00,0x07,0xF0,0x00,0x0C,0xCC,
+0x40,0x3A,0x00,0x3F,0x80,0x00,0x7F,0xF8,0x00,0x3F,
+0xFF,0x80,0x1F,0xFF,0xF0,0x0F,0xE0,0xFE,0x07,0xE0,
+0x1F,0x81,0xF0,0x03,0xF0,0xF8,0x00,0x7C,0x3C,0x00,
+0x1F,0x1F,0x00,0x03,0xC7,0xC0,0x00,0x04,0x3C,0x00,
+0x00,0x1F,0x03,0xF0,0x07,0xC7,0xFF,0x01,0xF3,0xFF,
+0xF0,0x7D,0xFF,0xFE,0x1F,0xF8,0x1F,0xC7,0xF8,0x03,
+0xF1,0xFC,0x00,0x7E,0x7F,0x00,0x0F,0xA3,0xF0,0x00,
+0x3F,0x3F,0x00,0x01,0xF9,0x7C,0x00,0x0F,0x9F,0x00,
+0x03,0xC3,0xE0,0x01,0xF0,0xFC,0x00,0xFC,0x1F,0x80,
+0x7E,0x07,0xF8,0x3F,0x00,0xFF,0xFF,0xC0,0x1F,0xFF,
+0xE0,0x01,0xFF,0xE0,0x00,0x1F,0xE0,0x00,0x0C,0x4C,
+0x60,0x3B,0x5F,0xFF,0xFF,0xEF,0xFF,0xFF,0xE0,0x00,
+0x03,0xE0,0x00,0x03,0xF0,0x00,0x01,0xF0,0x00,0x01,
+0xF0,0x00,0x01,0xF8,0x00,0x00,0xF8,0x20,0x00,0x1F,
+0x00,0x00,0x1F,0x00,0x00,0x1F,0x80,0x00,0x0F,0x80,
+0x00,0x0F,0xC0,0x00,0x07,0xC0,0x00,0x07,0xE0,0x08,
+0x00,0x7C,0x00,0x90,0x0F,0x80,0x09,0x01,0xF0,0x00,
+0xA0,0x3E,0x00,0x00,0x1E,0x00,0x06,0x03,0xE0,0x00,
+0x00,0x0C,0xCC,0x40,0x3A,0x00,0x7F,0x00,0x00,0xFF,
+0xF8,0x00,0x7F,0xFF,0x00,0x3F,0xFF,0xE0,0x1F,0xC1,
+0xFC,0x07,0xC0,0x1F,0x90,0x7C,0x00,0x7C,0x1F,0x00,
+0x0F,0x87,0x80,0x03,0xE1,0xF0,0x00,0xFA,0x0F,0x80,
+0x0F,0x81,0xF0,0x07,0xE0,0x7F,0x07,0xF0,0x07,0xFF,
+0xF8,0x00,0xFF,0xF8,0x00,0x3F,0xFF,0x00,0x3F,0xFF,
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+0xFC,0x00,0xFE,0x00,0xFF,0x00,0xFF,0x80,0x0F,0x80,
+0x07,0x81,0xA0,0xF8,0x20,0x1F,0x05,0x01,0xE0,0x01,
+0xF0,0x00,0xF0,0x00,0xFC,0x00,0x7F,0x80,0x03,0xE0,
+0x0F,0xE0,0x0F,0x80,0x1F,0x00,0x3E,0x16,0x07,0x83,
+0x41,0xF0,0x40,0x3E,0x00,0x3C,0x00,0x7C,0x07,0xFC,
+0x07,0xF8,0x07,0xF0,0x07,0xC0,0x00,0x0D,0x90,0x47,
+0xBE,0x0F,0xE0,0x00,0x23,0xFF,0xC0,0x06,0x7F,0xFF,
+0x81,0xF1,0xFF,0xFF,0xFF,0xDE,0x07,0xFF,0xF9,0x80,
+0x0F,0xFF,0x10,0x00,0x1F,0xC0,0x00,0x00,0x00,0x00,
+};
+/* font data size: 7100 bytes */
+
+static const unsigned char Arial_38_index[] = {
+0x00,0x00,0x01,0x00,0x20,0x02,0x10,0x2D,0x83,0x4C,
+0x30,0xC2,0x1B,0x11,0x10,0x96,0x05,0x24,0x2B,0x61,
+0x66,0x0B,0x58,0x5B,0xA2,0xE2,0x18,0x90,0xDA,0x47,
+0x1E,0x40,0x02,0x38,0x93,0x3C,0xA4,0xC5,0x94,0x2E,
+0xE9,0x91,0xCD,0x68,0x6B,0xE3,0x66,0x1C,0x88,0xE6,
+0x27,0x8A,0x3F,0x0A,0x44,0x93,0x48,0xA1,0xB5,0x4D,
+0xAC,0x21,0x65,0x2B,0x48,0x5E,0x42,0xFA,0x97,0xEA,
+0xC1,0xE6,0x5D,0x33,0x4D,0xAB,0x0D,0xC2,0x72,0xBB,
+0xAB,0x1E,0x9C,0xFE,0x48,0x3C,0xC2,0x5E,0x1A,0xF1,
+0x61,0x92,0x14,0xBB,0x66,0xC7,0x3D,0x99,0xF5,0xD0,
+0x7E,0x86,0x34,0x66,0xA3,0x7D,0x1F,0x29,0xAD,0x52,
+0x4A,0xB6,0xD6,0xE2,0xBF,0xF6,0x21,0xB4,0x2D,0xAC,
+0xED,0x7B,0x6D,0x3B,0x97,0x5C,0xE6,0xEF,0x37,0xA0,
+0xBF,0xA6,0x10,0xB1,0x1B,0x8A,0x7C,0x7E,0x64,0x63,
+0x28,0x39,0x9B,0xD0,0x46,0x99,0x35,0x9B,0xB1,0xAD,
+0xA9,0xED,0x7B,0x73,0x7B,0xB8,
+};
+/* font index size: 156 bytes */
+
+const ILI9341_t3_font_t Arial_38 = {
+        Arial_38_index,
+        0,
+        Arial_38_data,
+        1,
+        0,
+        32,
+        127,
+        0,
+        0,
+        13,
+        6,
+        6,
+        4,
+        6,
+        6,
+        58,
+        45
+};
+
+
+
+static const unsigned char Arial_40_data[] = {
+0x00,0x00,0x00,0x10,0x02,0xD0,0xC0,0x11,0xDF,0xEF,
+0xF3,0xFA,0xEA,0x75,0x02,0xFE,0x07,0x9C,0x46,0x94,
+0xDF,0x83,0xF3,0xF0,0x7E,0x9C,0x07,0x00,0x0E,0xD0,
+0x20,0x1F,0x80,0x03,0xE0,0x3E,0x00,0x1F,0x81,0xF9,
+0x40,0x0F,0x80,0xF8,0x00,0x7E,0x07,0xE2,0x40,0x3E,
+0x03,0xE1,0x7F,0xFF,0xFF,0xFF,0x00,0xF8,0x0F,0x80,
+0x07,0xE0,0x7E,0x0A,0x03,0xE0,0x3E,0x00,0x1F,0x81,
+0xF8,0x10,0x0F,0x80,0xF8,0x0B,0xFF,0xFF,0xFF,0xFC,
+0x07,0xC0,0x7C,0x00,0x3F,0x03,0xF0,0x0A,0x1F,0x01,
+0xF0,0x00,0xFC,0x0F,0xC0,0x10,0x7C,0x07,0xC0,0x00,
+0x0D,0xDC,0x5E,0xDF,0x80,0x00,0xE0,0x00,0x00,0x7F,
+0xC0,0x00,0x3F,0xFF,0x00,0x07,0xFF,0xFC,0x01,0xFF,
+0xFF,0xE0,0x1F,0xFF,0xFF,0x03,0xFC,0xE7,0xF0,0x3F,
+0x0E,0x1F,0x87,0xE0,0xE0,0xF8,0x7C,0x0E,0x0F,0xC7,
+0xC0,0xE0,0x7C,0x7C,0x0E,0x07,0x07,0xC0,0xE0,0x00,
+0x7E,0x0E,0x00,0x03,0xF0,0xE0,0x00,0x3F,0xCE,0x00,
+0x01,0xFF,0xE0,0x00,0x0F,0xFF,0x00,0x00,0x7F,0xFF,
+0x00,0x01,0xFF,0xFC,0x00,0x07,0xFF,0xE0,0x00,0x0F,
+0xFF,0x00,0x00,0xEF,0xF8,0x00,0x0E,0x3F,0xC0,0x00,
+0xE0,0xFC,0x00,0x0E,0x07,0xE0,0x00,0xE0,0x3E,0x38,
+0x0E,0x03,0xEF,0x80,0xE0,0x3F,0x1F,0x81,0xC0,0x7C,
+0xF8,0x1C,0x0F,0xCF,0xC1,0xC1,0xF8,0xFE,0x1C,0x3F,
+0x87,0xF9,0xCF,0xF0,0x3F,0xFF,0xFF,0x01,0xFF,0xFF,
+0xE0,0x0F,0xFF,0xFC,0x00,0x7F,0xFF,0x00,0x00,0xFF,
+0x80,0x2C,0x00,0x38,0x00,0x00,0x16,0x50,0x60,0x32,
+0x03,0xF0,0x00,0x00,0xF0,0x00,0x3F,0xE0,0x00,0x0F,
+0x80,0x03,0xFF,0x80,0x00,0x78,0x00,0x3E,0x3E,0x00,
+0x07,0xC0,0x03,0xE0,0xF8,0x00,0x3C,0x00,0x1E,0x03,
+0xC0,0x03,0xE0,0x00,0xE0,0x1E,0x00,0x1E,0x00,0x0F,
+0x00,0x78,0x01,0xE0,0x00,0x78,0x03,0xC0,0x1F,0x00,
+0x03,0xC0,0x1E,0x00,0xF0,0x00,0x1E,0x00,0xF0,0x0F,
+0x80,0x00,0xF0,0x07,0x80,0x78,0x00,0x07,0x80,0x3C,
+0x07,0xC0,0x00,0x3C,0x01,0xE0,0x3C,0x00,0x01,0xE0,
+0x0F,0x03,0xE0,0x00,0x07,0x00,0xF0,0x3E,0x00,0x00,
+0x3C,0x07,0x81,0xE0,0x00,0x01,0xE0,0x7C,0x1F,0x00,
+0x00,0x07,0xC7,0xC0,0xF0,0x1F,0x80,0x1F,0xFC,0x0F,
+0x81,0xFF,0x00,0x7F,0xC0,0x78,0x1F,0xFC,0x00,0xF8,
+0x07,0xC1,0xF1,0xF0,0x00,0x00,0x7C,0x1E,0x07,0xC0,
+0x00,0x03,0xC0,0xF0,0x1E,0x00,0x00,0x3E,0x07,0x00,
+0xF0,0x00,0x01,0xE0,0x78,0x03,0xC0,0x00,0x1F,0x03,
+0xC0,0x1E,0x00,0x00,0xF0,0x1E,0x00,0xF0,0x00,0x0F,
+0x80,0xF0,0x07,0x80,0x00,0xF8,0x07,0x80,0x3C,0x00,
+0x07,0x80,0x3C,0x01,0xE0,0x00,0x7C,0x01,0xE0,0x0F,
+0x00,0x03,0xC0,0x0F,0x00,0x78,0x00,0x3E,0x00,0x38,
+0x07,0x80,0x01,0xE0,0x01,0xE0,0x3C,0x00,0x1F,0x00,
+0x0F,0x03,0xE0,0x01,0xF0,0x00,0x3E,0x3E,0x00,0x0F,
+0x00,0x00,0xFF,0xE0,0x00,0xF8,0x00,0x03,0xFE,0x00,
+0x07,0x80,0x00,0x07,0xC0,0x10,0xD0,0x60,0x25,0x00,
+0x0F,0xE0,0x00,0x00,0x0F,0xFE,0x00,0x00,0x07,0xFF,
+0xC0,0x00,0x03,0xFF,0xF8,0x00,0x01,0xFF,0xFF,0x00,
+0x00,0x7E,0x0F,0xC0,0x00,0x3F,0x01,0xF8,0x02,0x81,
+0xF0,0x07,0xC0,0x00,0x3E,0x03,0xE0,0x00,0x0F,0xC1,
+0xF8,0x00,0x03,0xF0,0xFC,0x00,0x00,0x7E,0xFE,0x00,
+0x00,0x0F,0xFF,0x00,0x00,0x01,0xFF,0x00,0x00,0x00,
+0xFF,0x00,0x00,0x00,0xFF,0xC0,0x00,0x00,0x7F,0xF8,
+0x00,0x00,0x3F,0xBF,0x00,0x00,0x1F,0x87,0xE0,0x20,
+0x0F,0xC1,0xFC,0x0F,0x87,0xE0,0x3F,0x07,0xE1,0xF0,
+0x07,0xE1,0xF0,0xFC,0x00,0xFC,0xFC,0x3E,0x00,0x1F,
+0xFF,0x0F,0x80,0x07,0xFF,0x83,0xE0,0x00,0xFF,0xE0,
+0xF8,0x00,0x1F,0xF0,0x47,0xE0,0x00,0x7F,0x00,0xFC,
+0x00,0x3F,0xE0,0x3F,0x80,0x1F,0xFC,0x07,0xF8,0x3F,
+0xFF,0x81,0xFF,0xFF,0xF7,0xF8,0x3F,0xFF,0xF8,0xFF,
+0x03,0xFF,0xFC,0x1F,0x80,0x7F,0xFC,0x03,0xC0,0x03,
+0xF8,0x00,0x60,0x02,0x9C,0x66,0x8B,0xDF,0xCF,0xE9,
+0xC0,0x07,0x66,0x7D,0x53,0x00,0x1E,0x00,0x78,0x01,
+0xE0,0x07,0xC0,0x0F,0x00,0x3E,0x00,0xF8,0x01,0xE0,
+0x07,0xC0,0x0F,0x02,0x07,0xC0,0x93,0xE0,0x29,0xF0,
+0x0D,0xF8,0x02,0xFE,0x00,0x3C,0x01,0x4F,0x80,0x41,
+0xF0,0x01,0xE0,0x20,0x7C,0x08,0x0F,0x80,0x0F,0x00,
+0x1F,0x00,0x1F,0x00,0x1E,0x00,0x3E,0x00,0x3C,0x00,
+0x3C,0x00,0x3C,0x07,0x66,0x5D,0x53,0x78,0x00,0x78,
+0x00,0x78,0x00,0xF8,0x00,0xF0,0x01,0xF0,0x01,0xE0,
+0x01,0xE0,0x03,0xE0,0x03,0xC2,0x00,0xF8,0x00,0xF1,
+0x00,0x3E,0x58,0x07,0xDA,0x00,0xFD,0x00,0x3F,0x60,
+0x1F,0x40,0x0F,0x80,0x1E,0x20,0x0F,0x88,0x07,0xC0,
+0x1F,0x00,0x3C,0x00,0xF8,0x01,0xE0,0x07,0xC0,0x0F,
+0x00,0x3C,0x00,0xF0,0x00,0x09,0x22,0x45,0xD6,0xA0,
+0x1E,0x00,0x83,0xC1,0x1E,0x79,0xE7,0xFE,0xFE,0xFF,
+0xFF,0xC7,0xFF,0xE0,0x07,0xC0,0x01,0xF8,0x00,0x7F,
+0x80,0x1E,0x78,0x07,0xCF,0x81,0xF0,0xF8,0x1C,0x0E,
+0x00,0x81,0x00,0x0D,0xB6,0x61,0xA1,0xD0,0x01,0xF0,
+0x01,0x40,0x03,0xE0,0x02,0xFF,0xFF,0xFF,0xFE,0x80,
+0x0F,0x80,0x0A,0x00,0x1F,0x00,0x00,0x02,0x9A,0xBE,
+0x10,0xBF,0xD1,0xC6,0x39,0xC2,0x00,0x08,0x0A,0x23,
+0x13,0xBF,0xFF,0xF0,0x02,0x8A,0xA0,0x10,0xBF,0x80,
+0x08,0x50,0x00,0x10,0x80,0x00,0xF9,0x00,0x1E,0x90,
+0x03,0xC0,0x03,0xE4,0x80,0x3C,0x48,0x07,0x84,0x80,
+0xF0,0x00,0xF8,0x24,0x0F,0x02,0x41,0xE0,0x24,0x3C,
+0x00,0x3E,0x01,0x23,0xC0,0x12,0x78,0x01,0x2F,0x00,
+0x0F,0x80,0x07,0x80,0x00,0x0C,0xCE,0x60,0x1F,0x00,
+0x3F,0x80,0x00,0x7F,0xFC,0x00,0x3F,0xFF,0x80,0x1F,
+0xFF,0xF0,0x0F,0xFF,0xFE,0x03,0xF8,0x3F,0x81,0xF8,
+0x03,0xF0,0x7C,0x00,0x7C,0x3F,0x00,0x1F,0xA5,0xF0,
+0x00,0x7D,0xBF,0x00,0x01,0xFD,0xF8,0x00,0x0F,0xBE,
+0x00,0x03,0xF2,0xF8,0x00,0x3E,0x3F,0x00,0x1F,0x87,
+0xC0,0x07,0xC1,0xF8,0x03,0xF0,0x3F,0x83,0xF8,0x0F,
+0xFF,0xFE,0x01,0xFF,0xFF,0x00,0x3F,0xFF,0x80,0x07,
+0xFF,0xC0,0x00,0x3F,0x80,0x00,0x07,0xCE,0xC0,0x1F,
+0x80,0x01,0xE0,0x03,0xE0,0x07,0xE0,0x0F,0xE0,0x1F,
+0xE0,0x3F,0xE0,0xFF,0xE3,0xFF,0xE7,0xFB,0xEF,0xF3,
+0xEF,0xC3,0xEF,0x03,0xEC,0x03,0xFA,0x00,0x7F,0x40,
+0x0F,0xE8,0x01,0xFA,0x00,0x3E,0x0D,0x4E,0x40,0x1F,
+0x00,0x3F,0xE0,0x00,0x1F,0xFF,0x00,0x0F,0xFF,0xF8,
+0x03,0xFF,0xFF,0x80,0xFF,0xFF,0xF8,0x1F,0xC0,0x7F,
+0x87,0xF0,0x03,0xF0,0xFC,0x00,0x3E,0x3F,0x00,0x07,
+0xF0,0xF8,0x00,0x0F,0x87,0x00,0x01,0xF8,0x00,0x00,
+0x07,0xE0,0x00,0x00,0x3E,0x00,0x00,0x0F,0xC0,0x00,
+0x03,0xF0,0x00,0x00,0xFC,0x00,0x00,0x3F,0x00,0x00,
+0x0F,0xE0,0x00,0x03,0xF8,0x00,0x00,0xFE,0x00,0x00,
+0x7F,0x80,0x00,0x1F,0xC0,0x00,0x07,0xF0,0x00,0x01,
+0xFC,0x00,0x00,0xFF,0x00,0x00,0x3F,0xC0,0x00,0x0F,
+0xE0,0x00,0x03,0xF8,0x00,0x00,0x7E,0x00,0x00,0x1F,
+0x80,0x00,0x07,0xE0,0x00,0x02,0x1F,0xFF,0xFF,0xF9,
+0xFF,0xFF,0xFF,0xC0,0x0C,0xCE,0x60,0x1F,0x00,0x7F,
+0x00,0x00,0x7F,0xF8,0x00,0x7F,0xFF,0x00,0x3F,0xFF,
+0xF0,0x1F,0xFF,0xFC,0x07,0xF0,0x3F,0x83,0xF0,0x07,
+0xE0,0xF8,0x00,0xFC,0x7E,0x00,0x1F,0x1F,0x00,0x07,
+0xC1,0xC0,0x01,0xF0,0x00,0x00,0x7C,0x00,0x00,0x3E,
+0x00,0x00,0x1F,0x80,0x00,0x1F,0xC0,0x00,0x7F,0xE0,
+0x00,0x1F,0xE0,0x00,0x07,0xFC,0x00,0x01,0xFF,0xC0,
+0x00,0xEF,0xF8,0x00,0x00,0x3F,0x00,0x00,0x07,0xE0,
+0x00,0x00,0xF8,0x00,0x00,0x3F,0x90,0x00,0x00,0xF8,
+0xE0,0x00,0x3E,0xF8,0x00,0x0F,0xBF,0x00,0x07,0xEF,
+0xC0,0x01,0xF1,0xF8,0x00,0xFC,0x7F,0x00,0x7F,0x0F,
+0xE0,0x7F,0x83,0xFF,0xFF,0xC0,0x7F,0xFF,0xE0,0x0F,
+0xFF,0xF0,0x00,0xFF,0xF8,0x00,0x0F,0xF0,0x00,0x0D,
+0xCE,0x20,0x1F,0x00,0x00,0x1E,0x00,0x00,0x03,0xE0,
+0x00,0x00,0x7E,0x08,0x00,0x01,0xFC,0x00,0x00,0x3F,
+0xC0,0x00,0x07,0xFC,0x10,0x00,0x1F,0xF8,0x00,0x03,
+0xFF,0x80,0x00,0x7E,0xF8,0x20,0x01,0xF9,0xF0,0x00,
+0x3F,0x1F,0x00,0x07,0xE1,0xF0,0x40,0x1F,0x83,0xE0,
+0x03,0xF0,0x3E,0x00,0x7E,0x03,0xE0,0x81,0xF8,0x07,
+0xC0,0x3F,0x00,0x7C,0x07,0xE0,0x07,0xC0,0xFC,0x00,
+0x7C,0x17,0xFF,0xFF,0xFF,0xF4,0x00,0x01,0xF0,0x48,
+0x00,0x03,0xE0,0x0C,0xCE,0x60,0x1F,0x80,0x7F,0xFF,
+0xE4,0x87,0xFF,0xFF,0x20,0x3E,0x00,0x01,0x03,0xF0,
+0x00,0x09,0x1F,0x00,0x00,0x0F,0xC0,0x00,0x03,0xF1,
+0xF8,0x00,0xFD,0xFF,0x80,0x3E,0xFF,0xF8,0x0F,0xFF,
+0xFF,0x07,0xFF,0xFF,0xE1,0xFE,0x03,0xF8,0x7E,0x00,
+0x3F,0x07,0x00,0x07,0xC0,0x00,0x01,0xFE,0x00,0x00,
+0x07,0xDF,0x00,0x01,0xF7,0xC0,0x00,0xF9,0xF8,0x00,
+0x3E,0x3E,0x00,0x1F,0x8F,0xC0,0x0F,0xC1,0xFC,0x0F,
+0xF0,0x7F,0xFF,0xF8,0x0F,0xFF,0xFC,0x01,0xFF,0xFE,
+0x00,0x1F,0xFE,0x00,0x01,0xFE,0x00,0x0D,0x4E,0x40,
+0x1F,0x00,0x1F,0xE0,0x00,0x0F,0xFF,0x00,0x07,0xFF,
+0xF0,0x01,0xFF,0xFF,0x00,0x7F,0xFF,0xF0,0x1F,0xE0,
+0xFF,0x03,0xF0,0x07,0xE0,0xFC,0x00,0x7C,0x1F,0x00,
+0x0F,0xC7,0xE0,0x00,0xFA,0x5F,0x00,0x00,0x07,0xC0,
+0x00,0x00,0xF8,0x1F,0xC0,0x1F,0x0F,0xFE,0x03,0xE7,
+0xFF,0xF0,0x7D,0xFF,0xFF,0x0F,0xBF,0xFF,0xF1,0xFF,
+0x80,0xFE,0x3F,0xC0,0x0F,0xE7,0xF0,0x00,0xFC,0xFC,
+0x00,0x0F,0xEB,0xE0,0x00,0x1F,0x87,0x80,0x00,0x7C,
+0xF8,0x00,0x1F,0x9F,0x00,0x03,0xE1,0xF0,0x00,0xFC,
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+0xF8,0xFC,0x00,0x1F,0x83,0xF0,0x01,0xF9,0x01,0xF8,
+0x03,0xF0,0x07,0xE0,0x3F,0x00,0x1F,0x83,0xF0,0x00,
+0xFC,0x3F,0x00,0x03,0xF1,0xF8,0x00,0x0F,0xDF,0x80,
+0x00,0x3F,0xF8,0x00,0x01,0xFF,0x80,0x00,0x07,0xFC,
+0x01,0x00,0x03,0xF8,0x00,0x00,0x3F,0xC0,0x00,0x03,
+0xFF,0x00,0x00,0x1F,0xFC,0x00,0x01,0xFF,0xE0,0x00,
+0x1F,0x9F,0x80,0x01,0xF8,0x7E,0x00,0x0F,0xC1,0xF8,
+0x00,0xFC,0x0F,0xC0,0x0F,0xC0,0x3F,0x08,0x1F,0x80,
+0x1F,0x81,0xF8,0x00,0x7E,0x1F,0x80,0x01,0xF9,0xF8,
+0x00,0x07,0xE0,0x0C,0xD0,0x3D,0x5B,0x7C,0x00,0x07,
+0xCF,0x80,0x03,0xF8,0x7C,0x00,0x1F,0x0F,0x80,0x0F,
+0xC3,0xE0,0x03,0xE0,0xFC,0x00,0xF8,0x1F,0x00,0x7E,
+0x07,0xC0,0x1F,0x01,0xF8,0x07,0xC0,0x3E,0x03,0xF0,
+0x0F,0x80,0xF8,0x03,0xF0,0x3E,0x00,0x7C,0x1F,0x80,
+0x1F,0x07,0xC0,0x07,0xE1,0xF0,0x00,0xF8,0xFC,0x00,
+0x3E,0x3E,0x00,0x07,0xCF,0x80,0x01,0xF7,0xE0,0x00,
+0x7D,0xF0,0x00,0x0F,0xFC,0x04,0x00,0x7F,0xC0,0x00,
+0x0F,0xF0,0x08,0x00,0x7F,0x00,0x00,0x0F,0xC0,0x10,
+0x00,0x7C,0x00,0x00,0x3F,0x00,0x00,0x0F,0x80,0x08,
+0x00,0xFC,0x00,0x00,0x7E,0x00,0x03,0xFF,0x80,0x00,
+0xFF,0xC0,0x00,0x1F,0xE0,0x00,0x07,0xF0,0x00,0x01,
+0xF8,0x00,0x00,0x0C,0xBA,0x20,0x1B,0xB3,0xFF,0xFF,
+0xF0,0x00,0x01,0xF8,0x00,0x00,0xFC,0x00,0x00,0x7E,
+0x00,0x00,0x3F,0x00,0x00,0x1F,0x80,0x00,0x0F,0xE0,
+0x00,0x07,0xF0,0x00,0x03,0xF8,0x00,0x00,0xFC,0x00,
+0x00,0x7E,0x00,0x00,0x3F,0x00,0x00,0x1F,0x80,0x00,
+0x0F,0xC0,0x00,0x07,0xE0,0x00,0x03,0xF8,0x00,0x01,
+0xFC,0x00,0x00,0xFE,0x00,0x00,0x3F,0x00,0x00,0x1F,
+0x80,0x00,0x17,0xFF,0xFF,0xFF,0x08,0xE6,0x3D,0x53,
+0x00,0x0F,0xC0,0x0F,0xF0,0x07,0xFE,0x00,0x7F,0xE0,
+0x3F,0x80,0x0F,0xC1,0xA0,0x7C,0x0B,0x03,0xE0,0x40,
+0x3E,0x00,0x1F,0x80,0x0F,0xC0,0x1F,0xE0,0x07,0xF0,
+0x01,0xF0,0x00,0x7F,0x00,0x1F,0xE0,0x01,0xFC,0x00,
+0x1F,0x80,0x80,0x7C,0x06,0x81,0xF0,0x30,0x0F,0x80,
+0x03,0xF8,0x40,0x0F,0xFC,0x01,0xFF,0x00,0x3F,0xC0,
+0x03,0xF0,0x02,0x6A,0xBC,0xCE,0xDF,0xDF,0xDF,0xDF,
+0xDF,0xDF,0xDF,0xAF,0x08,0xE6,0x3D,0x53,0x7E,0x00,
+0x1F,0xE0,0x07,0xFC,0x02,0x3F,0xF0,0x00,0xFE,0x00,
+0x1F,0x81,0xA0,0x7C,0x0B,0x03,0xE0,0x00,0xFC,0x00,
+0x1F,0x00,0x07,0xE0,0x00,0xFC,0x00,0x1F,0xE0,0x03,
+0xF8,0x00,0x3E,0x00,0x3F,0x80,0x1F,0xE0,0x0F,0xC0,
+0x07,0xE0,0x01,0xF0,0x00,0xFC,0x1A,0x07,0xC0,0xB0,
+0x3E,0x00,0x1F,0x80,0x0F,0xE0,0x47,0xFE,0x01,0xFF,
+0x00,0x7F,0x80,0x1F,0x80,0x00,0x0E,0x14,0x43,0xA1,
+0x03,0xE0,0x00,0x00,0x7F,0xE0,0x00,0x47,0xFF,0xC0,
+0x06,0x7F,0xFF,0x80,0x77,0xFF,0xFF,0x0F,0xBE,0x0F,
+0xFF,0xFD,0xC0,0x1F,0xFF,0xCC,0x00,0x7F,0xFC,0x40,
+0x00,0xFF,0xC0,0x00,0x01,0xF8,0x00,};
+/* font data size: 7477 bytes */
+
+static const unsigned char Arial_40_index[] = {
+0x00,0x00,0x01,
+0x00,0x20,0x01,0xC0,0x32,0x03,0xD8,0x3B,0x62,0x79,
+0x14,0x08,0xAF,0xC5,0xFA,0x32,0x31,0x9D,0x8D,0x14,
+0x69,0x83,0x52,0x1B,0xF8,0xF4,0x07,0xF0,0x46,0xE2,
+0x75,0x94,0xFC,0xB3,0xA6,0x12,0x32,0xD1,0xB1,0x0E,
+0x64,0x73,0xC3,0xA5,0x1E,0xB4,0xF7,0xA8,0x20,0x44,
+0x3A,0x79,0x14,0xDA,0xAE,0x75,0xBE,0xAF,0xBD,0x82,
+0x0C,0x2F,0x66,0x43,0x3A,0x99,0xEA,0xD2,0x26,0xE2,
+0xB7,0x79,0xC7,0x0E,0xB8,0x7A,0x83,0xEA,0x20,0x95,
+0x0E,0x08,0xC0,0xC6,0x82,0x3C,0x92,0x5F,0x99,0xCC,
+0xF7,0x28,0x8D,0x4C,0xBA,0x6F,0x54,0x2E,0xA3,0xD5,
+0x48,0xAA,0x8D,0x57,0xEB,0x8D,0x62,0x0B,0x3B,0x5B,
+0x36,0xE4,0xD7,0x46,0xBD,0xBD,0xFA,0x2F,0xE9,0x80,
+0xCC,0x32,0x61,0xBF,0x16,0x38,0xDB,0xC9,0x76,0x60,
+0xB3,0xB3,0x9F,0x6D,0x2A,0xE9,0xDB,0x54,0x1A,0xEA,
+0xDA,0x8E,0xED,0x78,0x5B,0xC7,0x6E,0x5C,0x73,0x13,
+0xA1,0x80,
+};
+/* font index size: 155 bytes */
+
+const ILI9341_t3_font_t Arial_40 = {
+       Arial_40_index,
+       0,
+       Arial_40_data,
+       1,
+       0,
+       32,
+       126,
+       0,
+       0,
+       13,
+       6,
+       6,
+       4,
+       7,
+       6,
+       61,
+       48
+};
+
+
+
+static const unsigned char Arial_48_data[] = {
+0x00,0x00,0x00,0x02,0x60,0x01,0xB0,0x40,0x02,0xDB,
+0xFE,0xFF,0x3F,0x9F,0xD7,0xAD,0xE1,0xD8,0x65,0x81,
+0x9F,0x80,0x04,0x91,0x19,0xF3,0x1B,0xF8,0x1F,0xD7,
+0xE0,0x7F,0x8F,0x00,0xF0,0x09,0x30,0x00,0x04,0xB0,
+0x00,0x0F,0xC0,0x3F,0x00,0x00,0xFE,0x03,0xF0,0xA0,
+0x00,0xFC,0x03,0xF0,0x00,0x0F,0xE0,0x3F,0x05,0x00,
+0x0F,0xC0,0x3F,0x00,0x00,0xFE,0x03,0xF0,0x33,0xFF,
+0xFF,0xFF,0xFF,0xE0,0x01,0xF8,0x07,0xE0,0x00,0x0F,
+0xC0,0x7F,0x01,0x40,0x1F,0x80,0x7E,0x00,0x01,0xFC,
+0x07,0xE0,0x08,0x01,0xF8,0x07,0xE0,0x0C,0xFF,0xFF,
+0xFF,0xFF,0xF0,0x1F,0x80,0xFE,0x00,0x50,0x3F,0x00,
+0xFC,0x00,0x01,0xF8,0x0F,0xE0,0x02,0x83,0xF0,0x0F,
+0xC0,0x00,0x1F,0x80,0xFE,0x00,0x10,0x3F,0x00,0xFC,
+0x00,0x00,0x07,0xFA,0x1F,0x94,0xB2,0x00,0x07,0x00,
+0x00,0x00,0x3F,0xE0,0x00,0x01,0xFF,0xFC,0x00,0x07,
+0xFF,0xFF,0x00,0x0F,0xFF,0xFF,0x80,0x1F,0xFF,0xFF,
+0xC0,0x3F,0xFF,0xFF,0xE0,0x7F,0xE7,0x3F,0xE0,0x7F,
+0x87,0x0F,0xF0,0x7F,0x07,0x07,0xF0,0xFE,0x07,0x03,
+0xF0,0xFC,0x07,0x03,0xF8,0xFC,0x07,0x01,0xF8,0xFC,
+0x07,0x01,0xC2,0x1F,0x80,0xE0,0x00,0x1F,0xC0,0xE0,
+0x00,0x0F,0xC0,0xE0,0x00,0x0F,0xE0,0xE0,0x00,0x0F,
+0xF8,0xE0,0x00,0x07,0xFE,0xE0,0x00,0x03,0xFF,0xE0,
+0x00,0x01,0xFF,0xFC,0x00,0x00,0xFF,0xFF,0x80,0x00,
+0x3F,0xFF,0xE0,0x00,0x0F,0xFF,0xF0,0x00,0x01,0xFF,
+0xFC,0x00,0x00,0xFF,0xFC,0x00,0x00,0xE3,0xFE,0x00,
+0x00,0xE0,0xFF,0x00,0x00,0xE0,0x7F,0x00,0x00,0xE0,
+0x3F,0x00,0x00,0xE0,0x3F,0xC0,0x00,0x1C,0x03,0xF0,
+0xE0,0x1C,0x03,0xF7,0xE0,0x1C,0x03,0xF7,0xF0,0x1C,
+0x03,0xF7,0xF0,0x1C,0x07,0xF3,0xF0,0x1C,0x07,0xF3,
+0xF8,0x1C,0x0F,0xE3,0xFC,0x1C,0x1F,0xE1,0xFE,0x1C,
+0x3F,0xC1,0xFF,0x9C,0xFF,0xC0,0xFF,0xFF,0xFF,0x80,
+0x7F,0xFF,0xFF,0x00,0x3F,0xFF,0xFE,0x00,0x1F,0xFF,
+0xFC,0x00,0x07,0xFF,0xF0,0x00,0x00,0xFF,0x80,0x0C,
+0x00,0x03,0x80,0x00,0x0D,0x32,0x27,0xF7,0x80,0x1F,
+0x80,0x00,0x00,0x7E,0x00,0x03,0xFF,0x00,0x00,0x03,
+0xE0,0x00,0x7F,0xFC,0x00,0x00,0x3F,0x00,0x03,0xFF,
+0xF0,0x00,0x03,0xF0,0x00,0x3F,0x0F,0xC0,0x00,0x1F,
+0x00,0x03,0xF0,0x3F,0x00,0x01,0xF8,0x00,0x1F,0x00,
+0xF8,0x00,0x0F,0x80,0x00,0xF8,0x07,0xC0,0x00,0xFC,
+0x00,0x0F,0x80,0x1F,0x00,0x07,0xC0,0x00,0x7C,0x00,
+0xF8,0x00,0x7E,0x00,0x03,0xE0,0x07,0xC0,0x03,0xE0,
+0x00,0x1F,0x00,0x3E,0x00,0x3F,0x00,0x01,0x1F,0x00,
+0x3E,0x00,0x7E,0x00,0x00,0xF8,0x01,0xF0,0x07,0xE0,
+0x00,0x07,0xC0,0x0F,0x80,0x3E,0x00,0x00,0x3E,0x00,
+0x7C,0x03,0xF0,0x00,0x01,0xF0,0x03,0xE0,0x1F,0x00,
+0x00,0x07,0xC0,0x3E,0x01,0xF8,0x00,0x00,0x3E,0x01,
+0xF0,0x0F,0x80,0x00,0x01,0xF8,0x1F,0x00,0xFC,0x00,
+0x00,0x07,0xE1,0xF8,0x07,0xC0,0x00,0x00,0x1F,0xFF,
+0x80,0x7E,0x00,0x00,0x00,0x7F,0xF8,0x07,0xE0,0x00,
+0x00,0x01,0xFF,0x80,0x3F,0x00,0x7E,0x00,0x03,0xF0,
+0x03,0xF0,0x0F,0xFC,0x00,0x00,0x00,0x1F,0x01,0xFF,
+0xF0,0x00,0x00,0x01,0xF8,0x0F,0xFF,0xC0,0x00,0x00,
+0x0F,0x80,0xFC,0x3F,0x00,0x00,0x00,0xFC,0x0F,0xC0,
+0xFC,0x00,0x00,0x07,0xC0,0x7C,0x03,0xE0,0x00,0x00,
+0x7E,0x03,0xE0,0x1F,0x00,0x00,0x03,0xE0,0x3E,0x00,
+0x7C,0x00,0x00,0x3F,0x01,0xF0,0x03,0xF0,0x00,0x00,
+0x7E,0x01,0xF0,0x03,0xE0,0x00,0x07,0xE0,0x0F,0x80,
+0x1F,0x00,0x00,0x3E,0x00,0x7C,0x00,0xF8,0x00,0x03,
+0xF0,0x03,0xE0,0x07,0xC0,0x00,0x1F,0x00,0x1F,0x00,
+0x3E,0x00,0x01,0xF8,0x00,0xF8,0x01,0xF0,0x00,0x0F,
+0x80,0x07,0xC0,0x0F,0x80,0x00,0xFC,0x00,0x1F,0x00,
+0xF8,0x00,0x07,0xC0,0x00,0xF8,0x07,0xC0,0x00,0x7E,
+0x00,0x07,0xE0,0x7C,0x00,0x07,0xE0,0x00,0x1F,0x87,
+0xE0,0x00,0x3E,0x00,0x00,0x7F,0xFE,0x00,0x03,0xF0,
+0x00,0x01,0xFF,0xE0,0x00,0x1F,0x00,0x00,0x07,0xFE,
+0x00,0x01,0xF8,0x00,0x00,0x0F,0xC0,0x00,0x0A,0x32,
+0x1F,0xF5,0xA0,0x00,0x3F,0x80,0x00,0x00,0x00,0x7F,
+0xF8,0x00,0x00,0x00,0xFF,0xFE,0x00,0x00,0x00,0xFF,
+0xFF,0x80,0x00,0x00,0xFF,0xFF,0xE0,0x00,0x00,0xFF,
+0xFF,0xF8,0x00,0x00,0x7F,0x83,0xFC,0x00,0x00,0x3F,
+0x80,0xFF,0x00,0x00,0x3F,0x80,0x3F,0x80,0x0A,0x03,
+0xF0,0x01,0xF8,0x00,0x01,0xFC,0x00,0xFC,0x00,0x00,
+0x7E,0x00,0xFC,0x00,0x00,0x3F,0x80,0xFE,0x00,0x00,
+0x0F,0xE0,0xFE,0x00,0x00,0x07,0xF0,0xFE,0x00,0x00,
+0x01,0xFD,0xFE,0x00,0x00,0x00,0x7F,0xFE,0x00,0x00,
+0x00,0x3F,0xFE,0x00,0x00,0x00,0x0F,0xFC,0x00,0x00,
+0x00,0x1F,0xFC,0x00,0x00,0x00,0x1F,0xFE,0x00,0x00,
+0x00,0x3F,0xFF,0x80,0x00,0x00,0x3F,0xEF,0xE0,0x00,
+0x00,0x3F,0xC7,0xF8,0x00,0x00,0x3F,0xC1,0xFE,0x03,
+0xC0,0x3F,0xC0,0x7F,0x03,0xF8,0x1F,0xC0,0x1F,0xC1,
+0xFC,0x1F,0xC0,0x07,0xF0,0xFC,0x0F,0xC0,0x03,0xFC,
+0xFE,0x0F,0xE0,0x00,0xFF,0x7E,0x07,0xE0,0x00,0x3F,
+0xFF,0x03,0xF0,0x00,0x0F,0xFF,0x01,0xF8,0x00,0x03,
+0xFF,0x80,0xFC,0x00,0x01,0xFF,0x80,0x7E,0x00,0x00,
+0x7F,0xC0,0x3F,0x80,0x00,0x1F,0xE0,0x1F,0xC0,0x00,
+0x1F,0xF8,0x07,0xF0,0x00,0x1F,0xFE,0x03,0xFC,0x00,
+0x1F,0xFF,0x80,0xFF,0x00,0x1F,0xFF,0xE0,0x7F,0xE0,
+0x7F,0xF7,0xF8,0x1F,0xFF,0xFF,0xF3,0xFE,0x07,0xFF,
+0xFF,0xF0,0xFF,0x81,0xFF,0xFF,0xF0,0x3F,0x80,0x7F,
+0xFF,0xE0,0x0F,0x80,0x0F,0xFF,0xC0,0x03,0x80,0x00,
+0xFF,0x00,0x00,0x80,0x01,0x91,0x19,0xF1,0xBB,0xFD,
+0x7F,0x8F,0x00,0x04,0x3D,0x27,0x32,0xC0,0x00,0xF0,
+0x00,0xF0,0x00,0xF8,0x00,0xF8,0x00,0x78,0x00,0x7C,
+0x40,0x0F,0x84,0x01,0xF0,0x40,0x3E,0x04,0x07,0xC0,
+0x07,0xE0,0x03,0xE0,0x10,0x7E,0x00,0x3E,0x00,0xA7,
+0xE0,0x03,0xE0,0x06,0xFE,0x00,0x67,0xE0,0x05,0xBF,
+0x00,0x49,0xF8,0x00,0x7C,0x00,0x3F,0x01,0x01,0xF0,
+0x10,0x0F,0x81,0x00,0x7C,0x10,0x03,0xE0,0x00,0xF8,
+0x00,0x3C,0x00,0x1F,0x00,0x07,0x80,0x01,0xE0,0x00,
+0x78,0x04,0x3D,0x17,0x32,0xCF,0x00,0x03,0xC0,0x01,
+0xF0,0x00,0x7C,0x00,0x1E,0x00,0x0F,0x80,0x40,0x7C,
+0x04,0x03,0xE0,0x40,0x1F,0x04,0x00,0xF8,0x00,0x7E,
+0x00,0x1F,0x10,0x01,0xF8,0x00,0x7C,0xB0,0x07,0xED,
+0x00,0x3F,0xC0,0x03,0xFA,0x00,0x7E,0x00,0x3E,0x48,
+0x07,0xE0,0x03,0xE0,0x03,0xF1,0x00,0x3E,0x10,0x07,
+0xC1,0x00,0xF8,0x10,0x1F,0x00,0x1F,0x00,0x0F,0x00,
+0x0F,0x80,0x07,0x80,0x07,0x80,0x07,0x80,0x00,0x05,
+0xD4,0x11,0xC3,0x56,0x00,0xF8,0x00,0xE0,0xF8,0x38,
+0xFC,0x71,0xF8,0xFF,0x7F,0xF9,0xFF,0xFF,0xFC,0x7F,
+0xFF,0xF0,0x03,0xFF,0x00,0x01,0xFC,0x00,0x03,0xFE,
+0x00,0x07,0xDF,0x00,0x0F,0x9F,0x80,0x1F,0x8F,0xC2,
+0x07,0xE0,0xFC,0x01,0xC0,0x70,0x00,0x80,0x20,0x00,
+0x08,0x20,0x18,0x74,0xFA,0x00,0x0F,0xC0,0x01,0x80,
+0x00,0xFC,0x00,0x19,0xFF,0xFF,0xFF,0xFF,0xA0,0x00,
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+0x3F,0xFF,0xFF,0xFF,0x05,0x3F,0x0F,0x22,0xC0,0x00,
+0x7F,0x00,0x0F,0xF8,0x00,0xFF,0xC0,0x0F,0xFF,0x00,
+0x1F,0xFE,0x01,0xFE,0x00,0x0F,0xE0,0x68,0x0F,0xC0,
+0x68,0x0F,0xC0,0x00,0x7E,0x02,0x00,0xFC,0x00,0x0F,
+0xE0,0x00,0xFE,0x00,0x0F,0xF0,0x03,0xFF,0x00,0x1F,
+0xF0,0x01,0x1F,0xC0,0x00,0xFF,0x00,0x07,0xFE,0x00,
+0x07,0xF8,0x00,0x1F,0xC0,0x00,0x7F,0x00,0x80,0x3F,
+0x00,0xD0,0x1F,0x80,0xD0,0x1F,0x80,0x80,0x1F,0x80,
+0x00,0xFE,0x00,0x03,0xF8,0x20,0x03,0xFF,0xC0,0x0F,
+0xFE,0x00,0x3F,0xF0,0x00,0xFF,0x80,0x01,0xFC,0x01,
+0x7F,0x37,0x12,0x3B,0xFD,0xFE,0xFF,0x7F,0xBF,0xDF,
+0xEF,0xF7,0xFB,0xF0,0x05,0x3F,0x0F,0x22,0xCF,0xE0,
+0x00,0x7F,0xC0,0x03,0xFF,0x00,0x1F,0xFC,0x01,0x1F,
+0xFE,0x00,0x07,0xF0,0x00,0x1F,0xC0,0x68,0x0F,0xC0,
+0x68,0x0F,0xC0,0x00,0x7E,0x02,0x00,0x3F,0x00,0x01,
+0xFC,0x00,0x07,0xF0,0x00,0x3F,0xC0,0x00,0xFF,0xC0,
+0x01,0xFF,0x00,0x00,0xFE,0x00,0x1F,0xF0,0x01,0xFF,
+0x80,0x1F,0xE0,0x00,0xFE,0x00,0x0F,0xE0,0x00,0x7E,
+0x00,0x07,0xF0,0x34,0x07,0xE0,0x34,0x07,0xE0,0x20,
+0x07,0xE0,0x00,0x7F,0x00,0x07,0xF8,0x08,0xFF,0xF0,
+0x07,0xFF,0x00,0x3F,0xF0,0x01,0xFF,0x00,0x0F,0xE0,
+0x00,0x08,0x8D,0x11,0x04,0xE0,0x3F,0x00,0x00,0x00,
+0x1F,0xFC,0x00,0x00,0x87,0xFF,0xE0,0x00,0x31,0xFF,
+0xFF,0x00,0x0E,0x7F,0xFF,0xF8,0x03,0xDF,0xFF,0xFF,
+0xC1,0xFB,0xFF,0xFF,0xFF,0xFF,0x7E,0x0F,0xFF,0xFF,
+0xEF,0x00,0x3F,0xFF,0xF9,0xC0,0x03,0xFF,0xFE,0x30,
+0x00,0x1F,0xFF,0x84,0x00,0x00,0xFF,0xE0,0x00,0x00,
+0x07,0xF0,0x00,};
+/* font data size: 10693 bytes */
+
+static const unsigned char Arial_48_index[] = {
+0x00,0x00,0x00,0x50,0x05,0x80,0x23,
+0x02,0x10,0x14,0xE0,0xA4,0x83,0x88,0x0E,0x44,0x3D,
+0xF1,0x0B,0x44,0x60,0x11,0xEC,0x48,0x71,0x23,0xC4,
+0x95,0x13,0x64,0x55,0x81,0x63,0x86,0x2D,0x1B,0x7C,
+0x76,0x61,0xFC,0x48,0x9C,0x24,0x04,0x9A,0x72,0x93,
+0x4A,0x59,0x29,0xB0,0xAF,0x52,0xC2,0xCB,0x94,0x30,
+0x8C,0xE1,0x83,0xB3,0xCF,0x89,0x41,0x59,0x0F,0x74,
+0x49,0x11,0x4D,0x48,0x89,0x25,0x14,0x97,0xD2,0xA5,
+0x4E,0x6D,0x3B,0xE5,0x10,0x15,0x0B,0x57,0xC5,0x66,
+0xA5,0xD8,0x58,0x30,0x64,0x59,0x94,0x06,0x67,0xDA,
+0x51,0x6D,0xED,0xC7,0x87,0x41,0x1D,0xBA,0x77,0x49,
+0xE1,0x67,0x8B,0x9E,0x6E,0x79,0xE1,0xE8,0xB7,0xC7,
+0x5F,0x98,0x80,0x4A,0x08,0xA8,0x42,0x21,0x34,0x87,
+0x1E,0x20,0x78,0x85,0x62,0x37,0x8A,0xEA,0x2C,0x88,
+0xCC,0x63,0x69,0x8F,0x62,0x45,0x09,0x32,0xE4,0xF3,
+0x96,0x0E,0x5A,0xF9,0x79,0xE6,0x5E,0x9C,0x36,0x79,
+0xBA,0x14,0xA8,0xB8,0xA4,0x5E,0x92,0x6A,0x61,0xC0,
+};
+/* font index size: 167 bytes */
+
+const ILI9341_t3_font_t Arial_48 = {
+       Arial_48_index,
+       0,
+       Arial_48_data,
+       1,
+       0,
+       32,
+       126,
+       0,
+       0,
+       14,
+       7,
+       6,
+       5,
+       7,
+       7,
+       74,
+       48
+};
+
+
+
+static const unsigned char Arial_60_data[] = {
+0x00,0x00,0x00,0x01,0x70,0x01,0xDE,0x24,0x01,0x9D,
+0xFF,0xBF,0xF7,0xFB,0xF9,0xFE,0xBE,0xD7,0xD0,0xFB,
+0x4E,0x0E,0x60,0x0D,0xFE,0x05,0x8A,0x8D,0x39,0xDD,
+0xFE,0x01,0xFF,0x3F,0x80,0x7F,0xD7,0xC0,0x0F,0x87,
+0x80,0x0E,0x00,0x0B,0x5E,0x00,0x02,0xE8,0x00,0x00,
+0x7F,0x00,0x3F,0x80,0x00,0x03,0xFC,0x01,0xFC,0x12,
+0x00,0x01,0xFC,0x00,0xFE,0x00,0x00,0x07,0xF0,0x07,
+0xF8,0x00,0x00,0x3F,0xC0,0x1F,0xC0,0x90,0x00,0x1F,
+0xC0,0x0F,0xE0,0x00,0x00,0xFF,0x00,0x7F,0x81,0x40,
+0x00,0x7F,0x00,0x3F,0x80,0xDF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xC0,0x00,0x7F,0x00,0x3F,0x80,0x00,0x03,0xFC,
+0x01,0xFC,0x00,0x90,0x01,0xFC,0x00,0xFE,0x00,0x00,
+0x07,0xF0,0x07,0xF8,0x00,0x00,0x3F,0xC0,0x1F,0xC0,
+0x04,0x80,0x1F,0xC0,0x0F,0xE0,0x00,0x00,0x7F,0x00,
+0x7F,0x80,0x08,0x00,0x7F,0x00,0x3F,0x80,0x06,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFE,0x80,0x7F,0x00,0x3F,0x80,
+0x00,0x03,0xFC,0x01,0xFE,0x00,0x04,0x81,0xFC,0x00,
+0xFE,0x00,0x00,0x07,0xF0,0x07,0xF8,0x00,0x00,0x3F,
+0xC0,0x1F,0xC0,0x00,0x24,0x1F,0xC0,0x0F,0xE0,0x00,
+0x00,0x7F,0x00,0x7F,0x80,0x00,0x40,0x7F,0x00,0x3F,
+0x80,0x00,0x00,0x09,0xE3,0x8F,0xC2,0xE9,0x00,0x00,
+0x3C,0x00,0x00,0x00,0x03,0xFF,0x80,0x00,0x00,0x1F,
+0xFF,0xF0,0x00,0x00,0x7F,0xFF,0xFC,0x00,0x01,0xFF,
+0xFF,0xFE,0x00,0x03,0xFF,0xFF,0xFF,0x00,0x07,0xFF,
+0xFF,0xFF,0x80,0x0F,0xFF,0xFF,0xFF,0xC0,0x1F,0xFE,
+0x3F,0xFF,0xE0,0x1F,0xF8,0x3C,0xFF,0xE0,0x3F,0xE0,
+0x3C,0x3F,0xF0,0x3F,0xC0,0x3C,0x1F,0xF0,0x7F,0x80,
+0x3C,0x0F,0xF0,0x7F,0x80,0x3C,0x07,0xF8,0x7F,0x00,
+0x3C,0x07,0xF8,0x7F,0x00,0x3C,0x03,0xF8,0x7F,0x00,
+0x3C,0x03,0xC1,0x0F,0xE0,0x07,0x80,0x00,0x21,0xFE,
+0x00,0xF0,0x00,0x00,0xFF,0x00,0xF0,0x00,0x00,0xFF,
+0x80,0xF0,0x00,0x00,0x7F,0xE0,0xF0,0x00,0x00,0x7F,
+0xF8,0xF0,0x00,0x00,0x3F,0xFF,0xF0,0x00,0x00,0x1F,
+0xFF,0xF0,0x00,0x00,0x0F,0xFF,0xFF,0x00,0x00,0x03,
+0xFF,0xFF,0xE0,0x00,0x01,0xFF,0xFF,0xF8,0x00,0x00,
+0x3F,0xFF,0xFE,0x00,0x00,0x0F,0xFF,0xFF,0x00,0x00,
+0x00,0xFF,0xFF,0x80,0x00,0x00,0xFF,0xFF,0xC0,0x00,
+0x00,0xF1,0xFF,0xE0,0x00,0x00,0xF0,0x7F,0xE0,0x00,
+0x00,0xF0,0x1F,0xF0,0x00,0x00,0xF0,0x0F,0xF0,0x00,
+0x00,0xF0,0x07,0xF0,0x00,0x00,0xF0,0x07,0xFC,0x80,
+0x00,0x1E,0x00,0x7F,0x0F,0x00,0x1E,0x00,0x7F,0x7F,
+0x00,0x1E,0x00,0x7F,0x8F,0xF0,0x03,0xC0,0x0F,0xEF,
+0xF0,0x03,0xC0,0x1F,0xE7,0xF8,0x03,0xC0,0x1F,0xC7,
+0xF8,0x03,0xC0,0x3F,0xC7,0xFC,0x03,0xC0,0x7F,0xC3,
+0xFE,0x03,0xC0,0xFF,0x83,0xFF,0x83,0xC1,0xFF,0x81,
+0xFF,0xE3,0xCF,0xFF,0x01,0xFF,0xFF,0xFF,0xFE,0x00,
+0xFF,0xFF,0xFF,0xFC,0x00,0x7F,0xFF,0xFF,0xF8,0x00,
+0x3F,0xFF,0xFF,0xF0,0x00,0x1F,0xFF,0xFF,0xE0,0x00,
+0x07,0xFF,0xFF,0x80,0x00,0x01,0xFF,0xFC,0x00,0x00,
+0x00,0x1F,0xC0,0x00,0x1A,0x00,0x00,0x78,0x00,0x00,
+0x10,0x1F,0x17,0xFC,0xA0,0x03,0xF8,0x00,0x00,0x00,
+0x3F,0x80,0x00,0x0F,0xFF,0x00,0x00,0x00,0x1F,0x80,
+0x00,0x0F,0xFF,0xE0,0x00,0x00,0x1F,0xC0,0x00,0x0F,
+0xFF,0xF8,0x00,0x00,0x0F,0xC0,0x00,0x0F,0xFF,0xFE,
+0x00,0x00,0x0F,0xE0,0x00,0x07,0xF0,0x7F,0x00,0x00,
+0x07,0xE0,0x00,0x07,0xF0,0x1F,0xC0,0x00,0x07,0xF0,
+0x00,0x07,0xF0,0x07,0xE0,0x00,0x07,0xF0,0x00,0x03,
+0xF0,0x01,0xF8,0x00,0x03,0xF8,0x00,0x04,0x3F,0x00,
+0x1F,0x80,0x00,0x7F,0x00,0x00,0x3F,0x00,0x07,0xE0,
+0x00,0x7F,0x00,0x00,0x1F,0x80,0x03,0xF0,0x00,0x3F,
+0x00,0x00,0x0F,0xC0,0x01,0xF8,0x00,0x3F,0x80,0x00,
+0x07,0xE0,0x00,0xFC,0x00,0x1F,0x80,0x00,0x03,0xF0,
+0x00,0x7E,0x00,0x1F,0xC0,0x00,0x01,0xF8,0x00,0x3F,
+0x00,0x0F,0xC0,0x00,0x00,0xFC,0x00,0x1F,0x80,0x0F,
+0xE0,0x00,0x00,0x7E,0x00,0x0F,0xC0,0x07,0xE0,0x00,
+0x00,0x3F,0x00,0x07,0xE0,0x07,0xF0,0x00,0x00,0x1F,
+0x80,0x03,0xF0,0x03,0xF0,0x00,0x00,0x07,0xC0,0x03,
+0xF0,0x03,0xF8,0x00,0x00,0x08,0x7E,0x00,0x3F,0x00,
+0x7F,0x00,0x00,0x00,0x3F,0x80,0x3F,0x00,0x7F,0x00,
+0x00,0x00,0x0F,0xE0,0x3F,0x80,0x3F,0x80,0x00,0x00,
+0x07,0xF8,0x3F,0x80,0x3F,0x80,0x00,0x00,0x01,0xFF,
+0xFF,0xC0,0x1F,0x80,0x00,0x00,0x00,0x7F,0xFF,0xC0,
+0x1F,0xC0,0x00,0x00,0x00,0x1F,0xFF,0xC0,0x0F,0xC0,
+0x00,0x00,0x00,0x03,0xFF,0x80,0x0F,0xE0,0x01,0xFC,
+0x00,0x00,0x7F,0x00,0x07,0xE0,0x07,0xFF,0x80,0x00,
+0x00,0x00,0x07,0xF0,0x07,0xFF,0xF0,0x00,0x00,0x00,
+0x03,0xF0,0x07,0xFF,0xFC,0x00,0x00,0x00,0x03,0xF8,
+0x07,0xFF,0xFF,0x00,0x00,0x00,0x01,0xF8,0x03,0xF8,
+0x3F,0x80,0x00,0x00,0x01,0xFC,0x03,0xF8,0x0F,0xE0,
+0x00,0x00,0x00,0xFC,0x03,0xF8,0x03,0xF0,0x00,0x00,
+0x00,0xFE,0x01,0xF8,0x00,0xFD,0x00,0x00,0x00,0x1F,
+0xC0,0x1F,0x80,0x0F,0xD0,0x00,0x00,0x03,0xF8,0x03,
+0xF0,0x00,0x7E,0x00,0x00,0x03,0xF8,0x01,0xF8,0x00,
+0x3F,0x00,0x00,0x01,0xF8,0x00,0xFC,0x00,0x1F,0x80,
+0x00,0x01,0xFC,0x00,0x7E,0x00,0x0F,0xC0,0x00,0x00,
+0xFC,0x00,0x3F,0x00,0x07,0xE0,0x00,0x00,0xFE,0x00,
+0x1F,0x80,0x03,0xF0,0x00,0x00,0x7E,0x00,0x0F,0xC0,
+0x01,0xF8,0x00,0x00,0x7F,0x00,0x07,0xE0,0x00,0xFC,
+0x00,0x00,0x3F,0x00,0x03,0xF0,0x00,0x7E,0x00,0x00,
+0x3F,0x80,0x00,0xF8,0x00,0x7E,0x00,0x00,0x1F,0x80,
+0x00,0x7E,0x00,0x3F,0x00,0x00,0x1F,0xC0,0x00,0x3F,
+0x00,0x1F,0x80,0x00,0x1F,0xC0,0x00,0x1F,0xC0,0x1F,
+0x80,0x00,0x0F,0xE0,0x00,0x07,0xF0,0x1F,0xC0,0x00,
+0x0F,0xE0,0x00,0x03,0xFC,0x1F,0xC0,0x00,0x07,0xF0,
+0x00,0x00,0xFF,0xFF,0xE0,0x00,0x07,0xF0,0x00,0x00,
+0x3F,0xFF,0xE0,0x00,0x03,0xF0,0x00,0x00,0x0F,0xFF,
+0xE0,0x00,0x03,0xF8,0x00,0x00,0x01,0xFF,0xC0,0x00,
+0x01,0xF8,0x00,0x00,0x00,0x3F,0x80,0x00,0x0C,0x5F,
+0x13,0xFB,0x70,0x00,0x03,0xFC,0x00,0x00,0x00,0x00,
+0x03,0xFF,0xE0,0x00,0x00,0x00,0x03,0xFF,0xFE,0x00,
+0x00,0x00,0x01,0xFF,0xFF,0xC0,0x00,0x00,0x00,0xFF,
+0xFF,0xF8,0x00,0x00,0x00,0x7F,0xFF,0xFF,0x00,0x00,
+0x00,0x3F,0xFF,0xFF,0xC0,0x00,0x00,0x1F,0xF8,0x1F,
+0xF8,0x00,0x00,0x07,0xFC,0x03,0xFE,0x00,0x00,0x01,
+0xFE,0x00,0x7F,0x80,0x00,0x00,0xFF,0x00,0x0F,0xF0,
+0x00,0x2C,0x07,0xF0,0x00,0x3F,0x80,0x00,0x01,0xFE,
+0x00,0x0F,0xE0,0x00,0x00,0x3F,0x80,0x07,0xF0,0x00,
+0x00,0x0F,0xF0,0x01,0xFC,0x00,0x00,0x03,0xFC,0x00,
+0xFE,0x00,0x00,0x00,0x7F,0x80,0x7F,0x80,0x00,0x00,
+0x0F,0xF0,0x7F,0xC0,0x00,0x00,0x03,0xFE,0x3F,0xE0,
+0x00,0x00,0x00,0x7F,0xFF,0xF0,0x00,0x00,0x00,0x0F,
+0xFF,0xF8,0x00,0x00,0x00,0x01,0xFF,0xFC,0x00,0x00,
+0x00,0x00,0x7F,0xFE,0x00,0x00,0x00,0x00,0x3F,0xFE,
+0x00,0x00,0x00,0x00,0x1F,0xFF,0x00,0x00,0x00,0x00,
+0x1F,0xFF,0xC0,0x00,0x00,0x00,0x0F,0xFF,0xF8,0x00,
+0x00,0x00,0x0F,0xFF,0xFF,0x00,0x00,0x00,0x07,0xFF,
+0x3F,0xE0,0x00,0x00,0x03,0xFF,0x07,0xFC,0x00,0x00,
+0x00,0xFF,0x80,0xFF,0x00,0x3C,0x00,0x7F,0xC0,0x1F,
+0xE0,0x1F,0xE0,0x3F,0xE0,0x07,0xFC,0x07,0xF8,0x0F,
+0xF0,0x00,0xFF,0x81,0xFC,0x07,0xF8,0x00,0x1F,0xF0,
+0xFF,0x01,0xFC,0x00,0x03,0xFC,0x3F,0xC0,0x7F,0x00,
+0x00,0x7F,0x9F,0xE0,0x3F,0x80,0x00,0x1F,0xF7,0xF8,
+0x0F,0xE0,0x00,0x03,0xFF,0xFE,0x03,0xF8,0x00,0x00,
+0x7F,0xFF,0x00,0xFE,0x00,0x00,0x0F,0xFF,0xC0,0x47,
+0xF0,0x00,0x00,0x3F,0xFC,0x01,0xFE,0x00,0x00,0x07,
+0xFE,0x00,0x7F,0x80,0x00,0x00,0xFF,0xC0,0x0F,0xF0,
+0x00,0x00,0x7F,0xF8,0x03,0xFC,0x00,0x00,0x3F,0xFE,
+0x00,0xFF,0x80,0x00,0x1F,0xFF,0xC0,0x1F,0xF0,0x00,
+0x1F,0xFF,0xF8,0x03,0xFE,0x00,0x1F,0xFF,0xFF,0x00,
+0xFF,0xF0,0x1F,0xFF,0x3F,0xF0,0x1F,0xFF,0xFF,0xFF,
+0x8F,0xFE,0x03,0xFF,0xFF,0xFF,0xC1,0xFF,0xC0,0x7F,
+0xFF,0xFF,0xE0,0x3F,0xE0,0x0F,0xFF,0xFF,0xE0,0x07,
+0xF0,0x00,0xFF,0xFF,0xF0,0x00,0xF8,0x00,0x0F,0xFF,
+0xF0,0x00,0x1C,0x00,0x00,0x7F,0xE0,0x00,0x02,0x00,
+0x01,0xCA,0x91,0x39,0x0D,0xFF,0x9F,0xF5,0xF1,0xE0,
+0x04,0xE6,0x97,0x79,0xC0,0x00,0x1F,0x00,0x03,0xE0,
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+0x3F,0xC3,0xFE,0x00,0x03,0xFE,0x1F,0xFE,0x00,0xFF,
+0xE0,0x7F,0xFF,0xFF,0xFF,0x01,0xFF,0xFF,0xFF,0xF0,
+0x07,0xFF,0xFF,0xFF,0x00,0x1F,0xFF,0xFF,0xF0,0x00,
+0x7F,0xFF,0xFE,0x00,0x00,0xFF,0xFF,0xC0,0x00,0x00,
+0x7F,0xF0,0x00,0x05,0x5E,0x0B,0xF9,0x70,0x00,0x80,
+0x00,0x06,0x00,0x00,0x78,0x00,0x07,0xE0,0x0D,0x07,
+0xF0,0x05,0x03,0xF8,0x03,0x7F,0xFF,0xFD,0xA0,0xFE,
+0x00,0xD0,0x7F,0x00,0x68,0x3F,0x80,0x34,0x1F,0xC0,
+0x00,0x7F,0x00,0x01,0xFE,0x00,0x07,0xFC,0x00,0x1F,
+0xFF,0xD0,0x07,0xFF,0xE0,0x1F,0xFF,0xC0,0x3F,0xFF,
+0x00,0x3F,0xFC,0x00,0x3F,0xE0,0x08,0x96,0x9B,0xFA,
+0xED,0xFE,0x00,0x00,0x1F,0xF7,0xF8,0x00,0x00,0x7F,
+0xDF,0xE0,0x00,0x01,0xFF,0x7F,0x80,0x00,0x07,0xF7,
+0xF0,0x00,0x00,0xFF,0x3F,0xC0,0x00,0x07,0xFC,0x7F,
+0x80,0x00,0x3F,0xEF,0xF8,0x00,0x0F,0xFC,0xFF,0x00,
+0x03,0xFF,0x9F,0xF8,0x01,0xFF,0xF3,0xFF,0x80,0xFF,
+0xFE,0x3F,0xFF,0xFF,0xDF,0xC7,0xFF,0xFF,0xF3,0xF8,
+0x7F,0xFF,0xFC,0x7F,0x07,0xFF,0xFF,0x0F,0xE0,0x7F,
+0xFF,0xC1,0xFC,0x03,0xFF,0xE0,0x3F,0x80,0x0F,0xF0,
+0x00,0x00,0x09,0xD6,0x04,0x02,0x97,0xF8,0x00,0x00,
+0x0F,0xF8,0x7F,0x00,0x00,0x01,0xFC,0x7F,0x80,0x00,
+0x03,0xFD,0x07,0xF0,0x00,0x00,0x7F,0x07,0xF8,0x00,
+0x00,0xFF,0x20,0x7F,0x00,0x00,0x1F,0xC0,0x7F,0x80,
+0x00,0x3F,0xC4,0x07,0xF0,0x00,0x07,0xF0,0x07,0xF8,
+0x00,0x0F,0xF0,0x03,0xF8,0x00,0x0F,0xE0,0x03,0xFC,
+0x00,0x0F,0xE0,0x03,0xFC,0x00,0x1F,0xE0,0x01,0xFC,
+0x00,0x1F,0xC0,0x80,0x3F,0xC0,0x07,0xF8,0x00,0x1F,
+0xC0,0x07,0xF0,0x00,0x1F,0xE0,0x0F,0xF0,0x00,0x0F,
+0xE0,0x0F,0xF0,0x00,0x0F,0xE0,0x0F,0xE0,0x00,0x0F,
+0xF0,0x1F,0xE0,0x00,0x07,0xF0,0x1F,0xE0,0x00,0x07,
+0xF0,0x1F,0xC0,0x00,0x07,0xF8,0x3F,0xC0,0x10,0x00,
+0x7F,0x07,0xF0,0x00,0x00,0x7F,0x8F,0xF0,0x02,0x00,
+0x07,0xF1,0xFC,0x00,0x00,0x07,0xFB,0xFC,0x00,0x40,
+0x00,0x7F,0x7F,0x00,0x00,0x00,0x7F,0xFF,0x00,0x09,
+0x00,0x07,0xFF,0xC0,0x01,0x00,0x00,0x7F,0xF0,0x00,
+0x00,0x00,0x3F,0xF0,0x00,0x20,0x00,0x07,0xFC,0x00,
+0x00,0x0E,0xD6,0x00,0x03,0xB8,0xFE,0x00,0x00,0x7F,
+0xC0,0x00,0x0F,0xEF,0xF0,0x00,0x07,0xFC,0x00,0x01,
+0xFE,0x7F,0x00,0x00,0x7F,0xC0,0x00,0x1F,0xC7,0xF0,
+0x00,0x0F,0xFE,0x00,0x01,0xFC,0x7F,0x80,0x00,0xFF,
+0xE0,0x00,0x3F,0xD0,0x7F,0x00,0x01,0xFF,0xC0,0x00,
+0x7F,0x07,0xF0,0x00,0x1F,0xFE,0x00,0x0F,0xF0,0x3F,
+0x80,0x03,0xFF,0xE0,0x00,0xFE,0x20,0x7F,0x00,0x07,
+0xEF,0xC0,0x01,0xFC,0x03,0xF8,0x00,0x7E,0xFE,0x00,
+0x3F,0x84,0x07,0xF0,0x01,0xFD,0xFC,0x00,0x7F,0x08,
+0x07,0xF0,0x03,0xF1,0xF8,0x01,0xFC,0x00,0x7F,0x00,
+0x7F,0x1F,0xC0,0x1F,0xC0,0x03,0xF8,0x07,0xF1,0xFC,
+0x03,0xF8,0x10,0x07,0xF0,0x0F,0xC1,0xF8,0x07,0xF0,
+0x20,0x07,0xF0,0x3F,0x83,0xF8,0x1F,0xC0,0x00,0x7F,
+0x03,0xF0,0x3F,0x81,0xFC,0x00,0x07,0xF8,0x3F,0x01,
+0xF8,0x3F,0x80,0x40,0x07,0xF0,0xFE,0x03,0xF8,0x7F,
+0x00,0x00,0x7F,0x0F,0xE0,0x3F,0x8F,0xE0,0x00,0x03,
+0xF8,0xFC,0x01,0xF8,0xFE,0x00,0x00,0x3F,0x9F,0xC0,
+0x1F,0xCF,0xE0,0x00,0x03,0xF9,0xFC,0x01,0xFC,0xFC,
+0x00,0x00,0x1F,0x9F,0xC0,0x1F,0xDF,0xC0,0x00,0x01,
+0xFD,0xF8,0x00,0xFD,0xFC,0x00,0x00,0x1F,0xDF,0x80,
+0x0F,0xDF,0x80,0x08,0x00,0x1F,0xFF,0x00,0x1F,0xFF,
+0x00,0x00,0x01,0xFF,0xF0,0x00,0xFF,0xF0,0x01,0x20,
+0x01,0xFF,0xC0,0x01,0xFF,0xC0,0x00,0x00,0x0F,0xFC,
+0x00,0x1F,0xF8,0x00,0x20,0x00,0x1F,0xF0,0x00,0x1F,
+0xF0,0x00,0x00,0x00,0xFF,0x00,0x01,0xFE,0x00,0x00,
+0x0A,0x16,0x04,0x02,0xA3,0xFE,0x00,0x00,0x07,0xF8,
+0xFF,0x00,0x00,0x07,0xF8,0x3F,0xC0,0x00,0x07,0xFC,
+0x1F,0xF0,0x00,0x07,0xFC,0x07,0xFC,0x00,0x03,0xFC,
+0x01,0xFE,0x00,0x03,0xFC,0x00,0x7F,0x80,0x03,0xFE,
+0x00,0x3F,0xE0,0x01,0xFE,0x00,0x0F,0xF0,0x01,0xFE,
+0x00,0x03,0xFC,0x01,0xFF,0x00,0x01,0xFF,0x01,0xFF,
+0x00,0x00,0x7F,0x80,0xFF,0x00,0x00,0x1F,0xE0,0xFF,
+0x00,0x00,0x0F,0xF8,0xFF,0x80,0x00,0x03,0xFC,0xFF,
+0x80,0x00,0x00,0xFF,0x7F,0x80,0x00,0x00,0x7F,0xFF,
+0x80,0x00,0x00,0x1F,0xFF,0xC0,0x00,0x00,0x07,0xFF,
+0xC0,0x01,0x00,0x00,0x3F,0xF8,0x00,0x10,0x00,0x01,
+0xFF,0x00,0x00,0x00,0x01,0xFF,0xC0,0x00,0x00,0x01,
+0xFF,0xE0,0x00,0x00,0x01,0xFF,0xF8,0x00,0x00,0x00,
+0xFF,0xFE,0x00,0x00,0x00,0xFF,0xFF,0x80,0x00,0x00,
+0xFF,0xBF,0xC0,0x00,0x00,0x7F,0x8F,0xF0,0x00,0x00,
+0x7F,0x87,0xFC,0x00,0x00,0x7F,0xC1,0xFE,0x00,0x00,
+0x7F,0xC0,0x7F,0x80,0x00,0x3F,0xC0,0x3F,0xE0,0x00,
+0x3F,0xC0,0x0F,0xF0,0x00,0x3F,0xE0,0x03,0xFC,0x00,
+0x3F,0xE0,0x01,0xFF,0x00,0x1F,0xE0,0x00,0x7F,0x80,
+0x1F,0xE0,0x00,0x1F,0xE0,0x1F,0xF0,0x00,0x0F,0xF8,
+0x0F,0xF0,0x00,0x03,0xFE,0x0F,0xF0,0x00,0x00,0xFF,
+0x0F,0xF8,0x00,0x00,0x3F,0xCF,0xF8,0x00,0x00,0x1F,
+0xF0,0x09,0x5F,0x07,0x72,0x77,0xF0,0x00,0x00,0x1F,
+0xCF,0xE0,0x00,0x00,0xFF,0x87,0xF0,0x00,0x00,0x7F,
+0x0F,0xE0,0x00,0x03,0xFD,0x07,0xF0,0x00,0x01,0xFC,
+0x0F,0xE0,0x00,0x0F,0xF2,0x07,0xF0,0x00,0x07,0xF0,
+0x0F,0xE0,0x00,0x3F,0xC4,0x07,0xF0,0x00,0x1F,0xC0,
+0x0F,0xE0,0x00,0xFF,0x08,0x07,0xF0,0x00,0x7F,0x00,
+0x0F,0xE0,0x03,0xFC,0x10,0x07,0xF0,0x01,0xFC,0x00,
+0x0F,0xE0,0x0F,0xF0,0x20,0x07,0xF0,0x07,0xF0,0x00,
+0x0F,0xE0,0x3F,0xC0,0x40,0x07,0xF0,0x1F,0xC0,0x00,
+0x0F,0xE0,0xFF,0x00,0x80,0x07,0xF0,0x7F,0x00,0x00,
+0x0F,0xC3,0xFC,0x01,0x00,0x07,0xF1,0xFC,0x00,0x00,
+0x0F,0xCF,0xF0,0x02,0x00,0x07,0xF7,0xF0,0x00,0x00,
+0x0F,0xFF,0xC0,0x04,0x00,0x07,0xFF,0xC0,0x00,0x00,
+0x0F,0xFF,0x00,0x08,0x00,0x07,0xFF,0x00,0x00,0x00,
+0x0F,0xFC,0x00,0x10,0x00,0x07,0xFC,0x00,0x00,0x00,
+0x0F,0xF0,0x00,0x20,0x00,0x07,0xF0,0x00,0x00,0x00,
+0x3F,0xC0,0x00,0x40,0x00,0x1F,0xC0,0x00,0x24,0x00,
+0x1F,0xC0,0x00,0x00,0x00,0xFE,0x00,0x00,0x00,0x07,
+0xF8,0x00,0x00,0x10,0x3F,0xC0,0x00,0x00,0x7F,0xFF,
+0x00,0x00,0x10,0x3F,0xFF,0x00,0x00,0x00,0x7F,0xF8,
+0x00,0x00,0x01,0xFF,0xC0,0x00,0x00,0x07,0xFE,0x00,
+0x00,0x00,0x0F,0xE0,0x00,0x00,0x00,0x09,0x56,0x04,
+0x02,0x8D,0x3F,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x00,
+0xFF,0x80,0x00,0x00,0x07,0xFC,0x00,0x00,0x00,0x3F,
+0xE0,0x00,0x00,0x01,0xFF,0x00,0x00,0x00,0x0F,0xF8,
+0x10,0x00,0x00,0x0F,0xF8,0x00,0x00,0x00,0x7F,0xC0,
+0x00,0x00,0x03,0xFE,0x00,0x00,0x00,0x1F,0xF0,0x00,
+0x00,0x00,0xFF,0x80,0x00,0x00,0x07,0xFC,0x00,0x00,
+0x00,0x3F,0xE0,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,
+0x07,0xFC,0x00,0x00,0x00,0x3F,0xE0,0x00,0x00,0x01,
+0xFF,0x00,0x00,0x00,0x0F,0xF8,0x00,0x00,0x00,0x7F,
+0xC0,0x00,0x00,0x03,0xFE,0x00,0x00,0x00,0x0F,0xF0,
+0x00,0x00,0x00,0x7F,0xC0,0x00,0x00,0x03,0xFE,0x00,
+0x00,0x00,0x1F,0xF0,0x00,0x00,0x00,0xFF,0x80,0x00,
+0x00,0x07,0xFC,0x00,0x00,0x00,0x3F,0xE0,0x00,0x00,
+0x08,0x3F,0xE0,0x00,0x00,0x01,0xFF,0x00,0x00,0x00,
+0x1B,0xFF,0xFF,0xFF,0xFF,0xF0,0x05,0xE7,0x8B,0x71,
+0xC0,0x00,0x0F,0xF0,0x00,0x3F,0xF0,0x00,0x7F,0xF0,
+0x00,0xFF,0xF0,0x01,0xFF,0xF8,0x00,0x7F,0xFE,0x00,
+0x7F,0xC1,0x00,0x1F,0xE0,0x34,0x03,0xF8,0x06,0x80,
+0x7F,0x00,0xB0,0x0F,0xE0,0x12,0x03,0xF8,0x00,0x07,
+0xF8,0x00,0x07,0xF0,0x00,0x0F,0xF0,0x00,0x3F,0xE0,
+0x01,0xFF,0xC0,0x01,0xFF,0x80,0x01,0xFE,0x00,0x01,
+0xFC,0x00,0x01,0xFE,0x00,0x01,0xFF,0x80,0x01,0xFF,
+0xC0,0x00,0x3F,0xE0,0x00,0x0F,0xF0,0x00,0x07,0xF0,
+0x00,0x07,0xF8,0x02,0x40,0x7F,0x00,0x68,0x07,0xF0,
+0x0D,0x00,0xFE,0x01,0x60,0x1F,0xC0,0x00,0x1F,0xE0,
+0x00,0x0F,0xE0,0x00,0x0F,0xF8,0x00,0x0F,0xFF,0xE0,
+0x00,0xFF,0xF8,0x00,0x7F,0xF8,0x00,0x3F,0xF8,0x00,
+0x1F,0xF8,0x00,0x03,0xF8,0x01,0xA7,0x1F,0x71,0x4D,
+0xFF,0x7F,0xDF,0xF7,0xFD,0xFF,0x7F,0xDF,0xF7,0xFD,
+0xFF,0x7F,0xDF,0xDF,0x80,0x05,0xE7,0x8F,0x71,0xC7,
+0xF0,0x00,0x07,0xFE,0x00,0x07,0xFF,0x00,0x07,0xFF,
+0x80,0x08,0xFF,0xF8,0x00,0xFF,0xFC,0x00,0x07,0xFC,
+0x00,0x01,0xFC,0x00,0x01,0xFE,0x01,0xA0,0x1F,0xC0,
+0x34,0x03,0xF8,0x05,0x80,0x7F,0x00,0x90,0x07,0xF0,
+0x00,0x07,0xF8,0x00,0x03,0xF8,0x00,0x03,0xFC,0x00,
+0x01,0xFF,0x00,0x00,0xFF,0xE0,0x00,0x7F,0xE0,0x00,
+0x1F,0xE0,0x00,0x0F,0xE0,0x00,0x3F,0xE0,0x00,0x7F,
+0xE0,0x00,0xFF,0xE0,0x01,0xFF,0x00,0x03,0xFC,0x00,
+0x03,0xF8,0x00,0x07,0xF8,0x00,0x07,0xF0,0x10,0x01,
+0xFE,0x03,0x40,0x3F,0x80,0x68,0x07,0xF0,0x0B,0x00,
+0xFE,0x01,0x00,0x3F,0xC0,0x00,0xFF,0x80,0x23,0xFF,
+0xF0,0x03,0xFF,0xE0,0x03,0xFF,0xC0,0x03,0xFF,0x80,
+0x03,0xFF,0x00,0x03,0xFC,0x00,0x00,0x0A,0x47,0x90,
+0xAB,0x00,0x07,0xF0,0x00,0x00,0x00,0x0F,0xFF,0x80,
+0x00,0x01,0x07,0xFF,0xF8,0x00,0x00,0xC3,0xFF,0xFF,
+0x80,0x00,0x71,0xFF,0xFF,0xF8,0x00,0x3C,0xFF,0xFF,
+0xFF,0x00,0x3F,0x7F,0xFF,0xFF,0xF8,0x3F,0xDF,0xFF,
+0xFF,0xFF,0xFF,0xF7,0xF8,0x3F,0xFF,0xFF,0xFD,0xF8,
+0x01,0xFF,0xFF,0xFE,0x78,0x00,0x1F,0xFF,0xFF,0x1C,
+0x00,0x01,0xFF,0xFF,0x86,0x00,0x00,0x3F,0xFF,0xC1,
+0x00,0x00,0x03,0xFF,0xE0,0x00,0x00,0x00,0x1F,0xC0,
+0x00,};
+/* font data size: 16081 bytes */
+
+static const unsigned char Arial_60_index[] = {
+0x00,0x00,0x00,0x50,0x06,0x40,0x2B,0x03,0x2C,
+0x1F,0x40,0xF4,0x85,0x3C,0x15,0x18,0x5C,0x11,0x8D,
+0xC6,0x85,0x1A,0xC0,0x6B,0xE1,0xB1,0x86,0xCC,0x1C,
+0xD0,0x7E,0x62,0x0E,0xC9,0x41,0x29,0x28,0xB1,0x92,
+0xF9,0x0C,0xF5,0x36,0x58,0xE8,0xB3,0xE1,0x8F,0x95,
+0x3E,0xAD,0x06,0xE4,0x22,0x11,0x4B,0x48,0x59,0x4F,
+0x75,0x81,0x97,0x10,0x61,0x05,0x94,0x86,0x60,0xD9,
+0xB9,0x6C,0x21,0xB4,0x56,0xD5,0xDB,0xB9,0x74,0xD5,
+0xD6,0x77,0x9C,0x1F,0x9E,0x83,0xAE,0x1A,0x18,0xC2,
+0xE4,0x4B,0x96,0x9E,0x5E,0x69,0x9D,0x67,0xC7,0xA6,
+0xCA,0xB4,0x0B,0x0F,0xED,0x3D,0xB5,0x72,0xDB,0xEB,
+0x77,0x6E,0x42,0xB9,0x36,0xE6,0x5B,0xD1,0xEF,0xF9,
+0xC2,0xAB,0x15,0xCC,0x83,0x32,0x44,0xCC,0x9B,0x38,
+0xAC,0xE7,0x73,0xD2,0xD2,0xB7,0x4B,0xED,0x56,0xF5,
+0xB1,0xD9,0x87,0x71,0xDD,0xF5,0x38,0x0E,0xE3,0x8F,
+0x92,0x2E,0x5E,0x3A,0x21,0xEC,0x6B,0xBF,0x7F,0x33,
+0xFD,0x64,0xF7,0x97,0xDF,0x9F,0x9F,0x40,
+};
+/* font index size: 167 bytes */
+
+const ILI9341_t3_font_t Arial_60 = {
+       Arial_60_index,
+       0,
+       Arial_60_data,
+       1,
+       0,
+       32,
+       126,
+       0,
+       0,
+       14,
+       7,
+       7,
+       5,
+       7,
+       7,
+       92,
+       60
+};
+
+
+
+static const unsigned char Arial_72_data[] = {
+0x00,0x00,0x00,0x01,0xC0,0x02,0x64,0x2C,0x01,0xCD,
+0xFF,0xEF,0xFF,0x7F,0xF9,0xFF,0xD7,0xF6,0xBF,0xAD,
+0xFD,0xA7,0xC9,0x3E,0x68,0x03,0x7F,0xF1,0xFF,0x06,
+0xCD,0x11,0x72,0x4D,0xFF,0x80,0x3F,0xFB,0xFF,0x00,
+0x7F,0xDF,0xF0,0x07,0xFC,0xFF,0x00,0x3F,0xB1,0xFC,
+0x00,0x7F,0x0F,0xC0,0x03,0xE4,0x9F,0x00,0x07,0xC0,
+0x0D,0x64,0x04,0x03,0x88,0x00,0x00,0x1F,0xF0,0x00,
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+0x00,0x1F,0xFF,0xFF,0xE1,0xC0,0x00,0x00,0xFF,0xFF,
+0xF8,0x30,0x00,0x00,0x07,0xFF,0xFE,0x04,0x00,0x00,
+0x00,0x3F,0xFF,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,
+0x00,};
+/* font data size: 23001 bytes */
+
+static const unsigned char Arial_72_index[] = {
+0x00,0x00,0x00,0x14,0x00,0xE8,0x03,0xC0,0x28,
+0xE0,0xB9,0xC2,0xB9,0x07,0x85,0x0F,0x26,0x21,0x00,
+0x47,0x30,0x95,0x11,0x31,0x42,0x67,0x84,0xD5,0x09,
+0xB2,0x14,0xC0,0x2D,0x20,0x5E,0x00,0xD3,0x01,0xD5,
+0xE3,0xF1,0x48,0x73,0x92,0x5E,0x26,0x78,0x52,0x74,
+0xB0,0x81,0x62,0x42,0xC8,0x85,0xD7,0x4B,0xC4,0x18,
+0xA1,0x33,0x92,0x77,0xF0,0xFB,0xC2,0x0F,0x34,0x52,
+0x89,0x02,0xD2,0x3A,0x24,0xCD,0x4D,0x0C,0x9B,0x95,
+0x37,0xEA,0x78,0x75,0x34,0x2A,0x7B,0xD5,0xCB,0x2D,
+0x0E,0x5D,0xAC,0xBF,0x91,0x8D,0xAB,0x39,0xC6,0xB0,
+0x4D,0x78,0xDB,0x56,0x38,0xA9,0x76,0xDC,0xF6,0x19,
+0xF7,0xB4,0x0A,0xF8,0x1B,0xD0,0x63,0x20,0xDD,0xC2,
+0x38,0x84,0x8B,0x09,0x9E,0x1C,0xFC,0x49,0xE8,0xB2,
+0x11,0xA2,0x63,0xCB,0x47,0xF3,0x92,0x9B,0x27,0x5E,
+0x4F,0x7C,0xA3,0x59,0x6B,0xF2,0xDD,0xA6,0x21,0xCC,
+0xBB,0x9B,0x87,0x3B,0x0A,0x7E,0x65,0x01,0x3A,0x27,
+0x94,0x63,0xE9,0x01,0x52,0xF6,0xA8,0xCD,0x56,0x4A,
+0xB7,0x9D,0x7D,0xFB,0x13,0x36,0x2C,0xEC,0xB3,0x80,
+};
+/* font index size: 179 bytes */
+
+const ILI9341_t3_font_t Arial_72 = {
+       Arial_72_index,
+       0,
+       Arial_72_data,
+       1,
+       0,
+       32,
+       126,
+       0,
+       0,
+       15,
+       7,
+       7,
+       5,
+       7,
+       7,
+       111,
+       72
+};
+
+
+
+static const unsigned char Arial_96_data[] = {
+0x00,0x00,0x00,0x00,0x94,0x03,0x2F,0xAC,0x00,0x8B,
+0x7F,0xFF,0x7F,0xFF,0x7F,0xFF,0x7F,0xFE,0x3F,0xFF,
+0x5F,0xFB,0x5F,0xFA,0x5F,0xFB,0x4F,0xF3,0x4F,0xF2,
+0x4F,0xF0,0x3F,0x9A,0x3F,0x01,0xF8,0xD0,0x00,0x90,
+0x00,0xDF,0xFF,0xBF,0xFF,0x09,0x11,0x18,0xF4,0xBF,
+0x7F,0xFC,0x00,0x3F,0xFF,0x7F,0xFC,0x00,0x3F,0xFE,
+0xFF,0xFC,0x00,0x3F,0xFF,0x1F,0xF8,0x00,0x1F,0xF8,
+0x7F,0xC0,0x00,0x7F,0xD6,0x7F,0x80,0x00,0x7F,0x81,
+0xFC,0x00,0x03,0xFC,0x0F,0xE0,0x00,0x0F,0xC0,0x7E,
+0x00,0x00,0x7E,0x00,0x12,0x6F,0x80,0x01,0x28,0x00,
+0x00,0x00,0x7F,0xF8,0x00,0x03,0xFF,0xC0,0x00,0x00,
+0x00,0x1F,0xFE,0x00,0x01,0xFF,0xF0,0x00,0x00,0x00,
+0x0F,0xFF,0x80,0x00,0x7F,0xF8,0x09,0x00,0x00,0x00,
+0x7F,0xF8,0x00,0x03,0xFF,0xC0,0x00,0x00,0x00,0x1F,
+0xFE,0x00,0x01,0xFF,0xF0,0x00,0x00,0x00,0x0F,0xFF,
+0x80,0x00,0x7F,0xF8,0x04,0x80,0x00,0x00,0x7F,0xF8,
+0x00,0x03,0xFF,0xC0,0x00,0x00,0x00,0x1F,0xFE,0x00,
+0x01,0xFF,0xF0,0x00,0x00,0x00,0x0F,0xFF,0x80,0x00,
+0x7F,0xF8,0x02,0x40,0x00,0x00,0x7F,0xF8,0x00,0x03,
+0xFF,0xC0,0x00,0x00,0x00,0x1F,0xFE,0x00,0x01,0xFF,
+0xF0,0x00,0x00,0x00,0x0F,0xFF,0x80,0x00,0x7F,0xF8,
+0x01,0x00,0x00,0x00,0x7F,0xF8,0x00,0x03,0xFF,0xC0,
+0x00,0x00,0x00,0x1F,0xFE,0x00,0x01,0xFF,0xF0,0x00,
+0x00,0x00,0x0F,0xFF,0x80,0x00,0x7F,0xF8,0x00,0x90,
+0x00,0x00,0x7F,0xF8,0x00,0x03,0xFF,0xC0,0x00,0x00,
+0x00,0x1F,0xFE,0x00,0x01,0xFF,0xF0,0x01,0xBF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFB,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x0F,
+0xFF,0x00,0x00,0x7F,0xF8,0x00,0x00,0x00,0x03,0xFF,
+0xC0,0x00,0x3F,0xFE,0x00,0x00,0x00,0x01,0xFF,0xF0,
+0x00,0x0F,0xFF,0x00,0x01,0x20,0x00,0x0F,0xFF,0x00,
+0x00,0x7F,0xF8,0x00,0x00,0x00,0x03,0xFF,0xC0,0x00,
+0x3F,0xFE,0x00,0x00,0x00,0x01,0xFF,0xF0,0x00,0x0F,
+0xFF,0x00,0x00,0x90,0x00,0x0F,0xFF,0x00,0x00,0x7F,
+0xF8,0x00,0x00,0x00,0x03,0xFF,0xC0,0x00,0x3F,0xFE,
+0x00,0x00,0x00,0x01,0xFF,0xF0,0x00,0x0F,0xFF,0x00,
+0x00,0x48,0x00,0x0F,0xFF,0x00,0x00,0x7F,0xF8,0x00,
+0x00,0x00,0x03,0xFF,0xC0,0x00,0x3F,0xFE,0x00,0x00,
+0x00,0x01,0xFF,0xF0,0x00,0x0F,0xFF,0x00,0x00,0x20,
+0x00,0x0F,0xFF,0x00,0x00,0x7F,0xF8,0x00,0x01,0xBF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFB,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xC8,0x00,
+0xFF,0xF0,0x00,0x07,0xFF,0x80,0x00,0x00,0x00,0x3F,
+0xFC,0x00,0x03,0xFF,0xE0,0x00,0x00,0x00,0x1F,0xFF,
+0x00,0x00,0xFF,0xF0,0x00,0x00,0x20,0x00,0xFF,0xF0,
+0x00,0x07,0xFF,0x80,0x00,0x00,0x00,0x3F,0xFC,0x00,
+0x03,0xFF,0xE0,0x00,0x00,0x00,0x1F,0xFF,0x00,0x00,
+0xFF,0xF0,0x00,0x00,0x12,0x00,0xFF,0xF0,0x00,0x07,
+0xFF,0x80,0x00,0x00,0x00,0x3F,0xFC,0x00,0x03,0xFF,
+0xE0,0x00,0x00,0x00,0x1F,0xFF,0x00,0x00,0xFF,0xF0,
+0x00,0x00,0x09,0x00,0xFF,0xF0,0x00,0x07,0xFF,0x80,
+0x00,0x00,0x00,0x3F,0xFC,0x00,0x03,0xFF,0xE0,0x00,
+0x00,0x00,0x1F,0xFF,0x00,0x00,0xFF,0xF0,0x00,0x00,
+0x04,0x80,0xFF,0xF0,0x00,0x07,0xFF,0x80,0x00,0x00,
+0x00,0x3F,0xFC,0x00,0x03,0xFF,0xE0,0x00,0x00,0x00,
+0x1F,0xFF,0x00,0x00,0xFF,0xF0,0x00,0x00,0x00,0x07,
+0xFF,0x80,0x00,0x3F,0xFC,0x00,0x00,0x00,0x0F,0xFA,
+0x1B,0xCD,0x2A,0xC0,0x00,0x00,0x03,0xF8,0x00,0x00,
+0x00,0x00,0x00,0x00,0x3F,0xFF,0x00,0x00,0x00,0x00,
+0x00,0x03,0xFF,0xFF,0xF8,0x00,0x00,0x00,0x00,0x1F,
+0xFF,0xFF,0xFE,0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF,
+0xFF,0xC0,0x00,0x00,0x01,0xFF,0xFF,0xFF,0xFF,0xE0,
+0x00,0x00,0x07,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x00,
+0x0F,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x1F,0xFF,
+0xFF,0xFF,0xFF,0xFE,0x00,0x00,0x3F,0xFF,0xFF,0xFF,
+0xFF,0xFF,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,
+0x80,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xC0,0x00,
+0xFF,0xFF,0xF3,0xFF,0xFF,0xFF,0xC0,0x01,0xFF,0xFF,
+0x83,0xF9,0xFF,0xFF,0xE0,0x01,0xFF,0xFE,0x03,0xF8,
+0x3F,0xFF,0xF0,0x03,0xFF,0xF8,0x03,0xF8,0x0F,0xFF,
+0xF0,0x03,0xFF,0xF0,0x03,0xF8,0x07,0xFF,0xF8,0x07,
+0xFF,0xE0,0x03,0xF8,0x01,0xFF,0xF8,0x07,0xFF,0xC0,
+0x03,0xF8,0x01,0xFF,0xF8,0x07,0xFF,0xC0,0x03,0xF8,
+0x00,0xFF,0xFC,0x07,0xFF,0x80,0x03,0xF8,0x00,0x7F,
+0xFC,0x0F,0xFF,0x80,0x03,0xF8,0x00,0x7F,0xFC,0x49,
+0xFF,0xE0,0x00,0x7F,0x00,0x07,0xFF,0xC1,0xFF,0xE0,
+0x00,0x7F,0x00,0x03,0xFE,0x01,0xFF,0xE0,0x00,0x7F,
+0x00,0x03,0x80,0x09,0x3F,0xFC,0x00,0x0F,0xE0,0x00,
+0x00,0x01,0x07,0xFF,0xC0,0x01,0xFC,0x00,0x00,0x00,
+0x03,0xFF,0xC0,0x01,0xFC,0x00,0x00,0x00,0x20,0x7F,
+0xFC,0x00,0x3F,0x80,0x00,0x00,0x00,0x7F,0xFE,0x00,
+0x3F,0x80,0x00,0x00,0x00,0x3F,0xFF,0x00,0x3F,0x80,
+0x00,0x00,0x00,0x3F,0xFF,0xC0,0x3F,0x80,0x00,0x00,
+0x00,0x1F,0xFF,0xE0,0x3F,0x80,0x00,0x00,0x00,0x1F,
+0xFF,0xFC,0x3F,0x80,0x00,0x00,0x00,0x0F,0xFF,0xFF,
+0xBF,0x80,0x00,0x00,0x04,0x00,0xFF,0xFF,0xFF,0xF0,
+0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF,0xFE,0x00,0x00,
+0x00,0x00,0x3F,0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x00,
+0x0F,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x00,0x07,0xFF,
+0xFF,0xFF,0xFF,0x00,0x00,0x00,0x01,0xFF,0xFF,0xFF,
+0xFF,0xC0,0x00,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xF0,
+0x00,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xFC,0x00,0x00,
+0x00,0x07,0xFF,0xFF,0xFF,0xFE,0x00,0x00,0x00,0x00,
+0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x1F,0xFF,
+0xFF,0xFF,0x80,0x00,0x00,0x00,0x07,0xFF,0xFF,0xFF,
+0xC0,0x00,0x00,0x00,0x07,0xFF,0xFF,0xFF,0xE0,0x00,
+0x00,0x00,0x07,0xF7,0xFF,0xFF,0xF0,0x00,0x00,0x00,
+0x07,0xF0,0xFF,0xFF,0xF0,0x00,0x00,0x00,0x07,0xF0,
+0x1F,0xFF,0xF8,0x00,0x00,0x00,0x07,0xF0,0x0F,0xFF,
+0xF8,0x00,0x00,0x00,0x07,0xF0,0x03,0xFF,0xFC,0x00,
+0x00,0x00,0x07,0xF0,0x01,0xFF,0xFC,0x80,0x00,0x00,
+0x00,0xFE,0x00,0x0F,0xFF,0xC0,0x00,0x00,0x00,0xFE,
+0x00,0x07,0xFF,0xC0,0x00,0x00,0x00,0xFE,0x00,0x03,
+0xFF,0xD0,0x00,0x00,0x00,0x1F,0xC0,0x00,0x7F,0xFE,
+0x40,0x00,0x00,0x03,0xF8,0x00,0x07,0xFF,0x80,0x1C,
+0x00,0x03,0xF8,0x00,0x07,0xFF,0x87,0xFC,0x00,0x03,
+0xF8,0x00,0x07,0xFF,0xBF,0xFC,0x00,0x03,0xF8,0x00,
+0x07,0xFF,0xC7,0xFF,0xC0,0x00,0x7F,0x00,0x00,0xFF,
+0xF7,0xFF,0xC0,0x00,0x7F,0x00,0x01,0xFF,0xF8,0x7F,
+0xFC,0x00,0x0F,0xE0,0x00,0x3F,0xFC,0x7F,0xFC,0x00,
+0x0F,0xE0,0x00,0x7F,0xFC,0x7F,0xFE,0x00,0x0F,0xE0,
+0x00,0x7F,0xFC,0x3F,0xFE,0x00,0x0F,0xE0,0x00,0xFF,
+0xF8,0x3F,0xFF,0x00,0x0F,0xE0,0x01,0xFF,0xF8,0x3F,
+0xFF,0x80,0x0F,0xE0,0x03,0xFF,0xF8,0x1F,0xFF,0xC0,
+0x0F,0xE0,0x07,0xFF,0xF0,0x1F,0xFF,0xE0,0x0F,0xE0,
+0x0F,0xFF,0xF0,0x0F,0xFF,0xF8,0x0F,0xE0,0x1F,0xFF,
+0xE0,0x0F,0xFF,0xFC,0x0F,0xE0,0x7F,0xFF,0xC0,0x07,
+0xFF,0xFF,0x8F,0xE3,0xFF,0xFF,0xC0,0x07,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0x80,0x03,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0x00,0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE,
+0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x00,
+0x7F,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x3F,0xFF,
+0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x1F,0xFF,0xFF,0xFF,
+0xFF,0xC0,0x00,0x00,0x07,0xFF,0xFF,0xFF,0xFF,0x00,
+0x00,0x00,0x01,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x00,
+0x00,0x7F,0xFF,0xFF,0xF0,0x00,0x00,0x00,0x00,0x0F,
+0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xE0,
+0x00,0x00,0x01,0xA0,0x00,0x00,0x01,0xFC,0x00,0x00,
+0x00,0x2C,0x00,0x00,0x00,0x3F,0x80,0x00,0x00,0x00,
+0x19,0xF0,0x9F,0xFD,0xD8,0x00,0x03,0xFF,0x00,0x00,
+0x00,0x00,0x00,0x01,0xFF,0xE0,0x00,0x00,0x00,0x1F,
+0xFF,0xE0,0x00,0x00,0x00,0x00,0x01,0xFF,0xC0,0x00,
+0x00,0x00,0x7F,0xFF,0xF8,0x00,0x00,0x00,0x00,0x03,
+0xFF,0xC0,0x00,0x00,0x00,0xFF,0xFF,0xFE,0x00,0x00,
+0x00,0x00,0x03,0xFF,0x80,0x00,0x00,0x01,0xFF,0xFF,
+0xFF,0x00,0x00,0x00,0x00,0x07,0xFF,0x80,0x00,0x00,
+0x03,0xFF,0xFF,0xFF,0x80,0x00,0x00,0x00,0x07,0xFF,
+0x00,0x00,0x00,0x07,0xFF,0xFF,0xFF,0xC0,0x00,0x00,
+0x00,0x0F,0xFE,0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFF,
+0xE0,0x00,0x00,0x00,0x0F,0xFE,0x00,0x00,0x00,0x1F,
+0xFF,0x83,0xFF,0xF0,0x00,0x00,0x00,0x1F,0xFC,0x00,
+0x00,0x00,0x1F,0xFC,0x00,0xFF,0xF0,0x00,0x00,0x00,
+0x1F,0xFC,0x00,0x00,0x00,0x3F,0xF8,0x00,0x3F,0xF8,
+0x00,0x00,0x00,0x3F,0xF8,0x00,0x00,0x00,0x3F,0xF0,
+0x00,0x1F,0xF8,0x00,0x00,0x00,0x3F,0xF8,0x00,0x00,
+0x00,0x7F,0xF0,0x00,0x1F,0xFC,0x00,0x00,0x00,0x7F,
+0xF0,0x00,0x00,0x00,0x7F,0xE0,0x00,0x0F,0xFC,0x00,
+0x00,0x00,0xFF,0xF0,0x00,0x00,0x00,0xFF,0xE0,0x00,
+0x0F,0xFE,0x00,0x00,0x00,0xFF,0xE0,0x00,0x00,0x00,
+0xFF,0xC0,0x00,0x07,0xFE,0x00,0x00,0x01,0xFF,0xE0,
+0x00,0x00,0x00,0xFF,0xC0,0x00,0x07,0xFE,0x00,0x00,
+0x01,0xFF,0xC0,0x00,0x00,0x00,0xFF,0xC0,0x00,0x07,
+0xFE,0x00,0x00,0x03,0xFF,0xC0,0x00,0x00,0x00,0xFF,
+0xC0,0x00,0x07,0xFE,0x00,0x00,0x03,0xFF,0x80,0x00,
+0x00,0x02,0x3F,0xF0,0x00,0x00,0x7F,0xE0,0x00,0x00,
+0xFF,0xE0,0x00,0x00,0x00,0x47,0xFE,0x00,0x00,0x0F,
+0xFC,0x00,0x00,0x3F,0xF8,0x00,0x00,0x00,0x08,0xFF,
+0xC0,0x00,0x01,0xFF,0x80,0x00,0x0F,0xFE,0x00,0x00,
+0x00,0x00,0xFF,0xC0,0x00,0x01,0xFF,0x80,0x00,0x1F,
+0xFC,0x00,0x00,0x00,0x00,0xFF,0xC0,0x00,0x01,0xFF,
+0x80,0x00,0x3F,0xFC,0x00,0x00,0x00,0x00,0xFF,0xC0,
+0x00,0x01,0xFF,0x80,0x00,0x3F,0xF8,0x00,0x00,0x00,
+0x00,0xFF,0xC0,0x00,0x01,0xFF,0x80,0x00,0x7F,0xF8,
+0x00,0x00,0x00,0x00,0xFF,0xC0,0x00,0x01,0xFF,0x80,
+0x00,0x7F,0xF0,0x00,0x00,0x00,0x00,0xFF,0xC0,0x00,
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+0x03,0xFF,0xC0,0x00,0x00,0x03,0xFF,0xE0,0x1F,0xFF,
+0x00,0x00,0x00,0x07,0xFF,0x80,0x7F,0xFC,0x00,0x00,
+0x00,0x1F,0xFE,0x01,0xFF,0xE0,0x00,0x00,0x00,0x7F,
+0xFC,0x0F,0xFF,0x80,0x00,0x00,0x00,0xFF,0xF0,0x3F,
+0xFE,0x00,0x00,0x00,0x03,0xFF,0xC0,0xFF,0xF0,0x00,
+0x00,0x00,0x07,0xFF,0x87,0xFF,0xC0,0x00,0x00,0x00,
+0x1F,0xFE,0x1F,0xFE,0x00,0x00,0x00,0x00,0x7F,0xF8,
+0xFF,0xF8,0x00,0x00,0x00,0x00,0xFF,0xF3,0xFF,0xE0,
+0x00,0x00,0x00,0x03,0xFF,0xCF,0xFF,0x00,0x00,0x00,
+0x00,0x0F,0xFF,0x7F,0xFC,0x00,0x00,0x00,0x00,0x1F,
+0xFD,0xFF,0xF0,0x00,0x04,0x00,0x00,0x0F,0xFF,0xFF,
+0xF0,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF,0xC0,0x00,
+0x00,0x00,0x00,0x7F,0xFF,0xFE,0x00,0x00,0x20,0x00,
+0x00,0x1F,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x7F,
+0xFF,0xF8,0x00,0x00,0x40,0x00,0x00,0x1F,0xFF,0xFC,
+0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0xE0,0x00,0x00,
+0x80,0x00,0x00,0x1F,0xFF,0xF0,0x00,0x00,0x00,0x00,
+0x00,0x7F,0xFF,0x80,0x00,0x01,0x00,0x00,0x00,0x1F,
+0xFF,0xC0,0x00,0x00,0x90,0x00,0x00,0x07,0xFF,0xC0,
+0x00,0x00,0x40,0x00,0x00,0x07,0xFF,0xC0,0x00,0x00,
+0x00,0x00,0x00,0x1F,0xFE,0x00,0x00,0x00,0x80,0x00,
+0x00,0x1F,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,
+0xF8,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xE0,0x00,
+0x00,0x00,0x00,0x00,0x0F,0xFF,0x00,0x00,0x00,0x10,
+0x00,0x00,0x0F,0xFF,0x80,0x00,0x00,0x08,0x00,0x00,
+0x0F,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x7F,0xFC,
+0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xF0,0x00,0x00,
+0x00,0x01,0x80,0x7F,0xFF,0x80,0x00,0x00,0x00,0x07,
+0xFF,0xFF,0xFE,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF,
+0xF0,0x00,0x00,0x00,0x10,0x07,0xFF,0xFF,0xF0,0x00,
+0x00,0x00,0x00,0x1F,0xFF,0xFF,0x80,0x00,0x00,0x00,
+0x00,0x7F,0xFF,0xFC,0x00,0x00,0x00,0x00,0x01,0xFF,
+0xFF,0xE0,0x00,0x00,0x00,0x00,0x03,0xFF,0xFF,0x00,
+0x00,0x00,0x00,0x00,0x0F,0xFF,0xF8,0x00,0x00,0x00,
+0x00,0x00,0x3F,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,
+0x1F,0xF0,0x00,0x00,0x00,0x00,0x00,0x0F,0x22,0x94,
+0x01,0x0F,0x43,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF2,
+0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0x1F,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0xFF,0xFF,0xFF,0xFF,
+0x8F,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,
+0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xF0,0x00,0x00,
+0x00,0x00,0x00,0x7F,0xFF,0x00,0x00,0x00,0x00,0x00,
+0x07,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,
+0x80,0x00,0x00,0x00,0x00,0x07,0xFF,0xF8,0x00,0x00,
+0x00,0x00,0x00,0x7F,0xFF,0x80,0x00,0x00,0x00,0x00,
+0x03,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,
+0x80,0x00,0x00,0x00,0x00,0x03,0xFF,0xF8,0x00,0x00,
+0x00,0x00,0x00,0x3F,0xFF,0xC0,0x00,0x00,0x00,0x00,
+0x03,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,
+0xC0,0x00,0x00,0x00,0x00,0x01,0xFF,0xFC,0x00,0x00,
+0x00,0x00,0x00,0x1F,0xFF,0xC0,0x00,0x00,0x00,0x00,
+0x01,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,
+0xE0,0x00,0x00,0x00,0x00,0x01,0xFF,0xFE,0x00,0x00,
+0x00,0x00,0x00,0x1F,0xFF,0xE0,0x00,0x00,0x00,0x00,
+0x01,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,
+0xE0,0x00,0x00,0x00,0x00,0x00,0xFF,0xFE,0x00,0x00,
+0x00,0x00,0x00,0x0F,0xFF,0xE0,0x00,0x00,0x00,0x00,
+0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,
+0xF0,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,
+0x00,0x00,0x00,0x0F,0xFF,0xF0,0x00,0x00,0x00,0x00,
+0x00,0x7F,0xFF,0x00,0x00,0x00,0x00,0x00,0x07,0xFF,
+0xF0,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0x80,0x00,
+0x00,0x00,0x00,0x07,0xFF,0xF8,0x00,0x00,0x00,0x00,
+0x00,0x7F,0xFF,0x80,0x00,0x00,0x00,0x00,0x07,0xFF,
+0xF8,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0x80,0x00,
+0x00,0x00,0x00,0x03,0xFF,0xF8,0x00,0x00,0x00,0x00,
+0x00,0x3F,0xFF,0x80,0x00,0x00,0x00,0x00,0x03,0xFF,
+0xFC,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xC0,0x00,
+0x00,0x00,0x00,0x03,0xFF,0xFC,0x00,0x00,0x00,0x00,
+0x00,0x3F,0xFF,0xC0,0x00,0x00,0x00,0x00,0x01,0xFF,
+0xFC,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xC0,0x00,
+0x00,0x00,0x00,0x01,0xFF,0xFC,0x00,0x00,0x00,0x00,
+0x00,0x1F,0xFF,0xE0,0x00,0x00,0x00,0x00,0x01,0xFF,
+0xFE,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xE0,0x00,
+0x00,0x00,0x00,0x00,0xFF,0xFE,0x00,0x00,0x00,0x00,
+0x00,0x0F,0xFF,0xE1,0xFF,0xFF,0xFF,0xFF,0xFF,0xDF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x9F,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0x09,0xBD,0x8F,0x94,0xB0,
+0x00,0x00,0x00,0x3F,0xF8,0x00,0x00,0x07,0xFF,0xF0,
+0x00,0x00,0x3F,0xFF,0xE0,0x00,0x00,0xFF,0xFF,0xC0,
+0x00,0x07,0xFF,0xFF,0xC0,0x00,0x03,0xFF,0xFF,0xE0,
+0x00,0x0F,0xFF,0xFF,0xE4,0x00,0x07,0xFF,0xFF,0xF0,
+0x00,0x1F,0xFF,0xFF,0xE0,0x00,0x3F,0xFF,0xE0,0x00,
+0x00,0x7F,0xFE,0x00,0x00,0x01,0xFF,0xF8,0x00,0x90,
+0x00,0x7F,0xFC,0x00,0x34,0x00,0x1F,0xFE,0x00,0x0D,
+0x00,0x07,0xFF,0x80,0x03,0x40,0x01,0xFF,0xE0,0x00,
+0xA0,0x00,0x7F,0xF8,0x00,0x2C,0x00,0x3F,0xFC,0x00,
+0x08,0x00,0x1F,0xFE,0x00,0x00,0x00,0x7F,0xFC,0x00,
+0x00,0x00,0xFF,0xF0,0x00,0x00,0x03,0xFF,0xE0,0x00,
+0x00,0x0F,0xFF,0x80,0x00,0x00,0x7F,0xFF,0x00,0x00,
+0x03,0xFF,0xFC,0x00,0x00,0x7F,0xFF,0xF0,0x00,0x00,
+0xFF,0xFF,0xC0,0x00,0x01,0xFF,0xFE,0x00,0x00,0x03,
+0xFF,0xF8,0x00,0x00,0x07,0xFF,0xC0,0x00,0x00,0x0F,
+0xFE,0x00,0x00,0x00,0x1F,0xFF,0x00,0x00,0x00,0x3F,
+0xFF,0x80,0x00,0x00,0x7F,0xFF,0x80,0x00,0x00,0xFF,
+0xFF,0xC0,0x00,0x01,0xFF,0xFF,0xC0,0x00,0x00,0x3F,
+0xFF,0xC0,0x00,0x00,0x1F,0xFF,0x80,0x00,0x00,0x0F,
+0xFF,0x80,0x00,0x00,0x0F,0xFF,0x80,0x00,0x00,0x0F,
+0xFF,0x00,0x00,0x00,0x1F,0xFF,0x00,0x01,0x00,0x03,
+0xFF,0xC0,0x00,0x58,0x00,0x7F,0xF8,0x00,0x1A,0x00,
+0x0F,0xFF,0x00,0x06,0x80,0x03,0xFF,0xC0,0x01,0xA0,
+0x00,0xFF,0xF0,0x00,0x58,0x00,0x3F,0xFC,0x00,0x10,
+0x00,0x07,0xFF,0x80,0x00,0x00,0x0F,0xFF,0x80,0x00,
+0x00,0x1F,0xFF,0x80,0x00,0x00,0x3F,0xFF,0xC0,0x00,
+0x00,0x7F,0xFF,0xFF,0xC0,0x00,0x0F,0xFF,0xFF,0xF0,
+0x00,0x01,0xFF,0xFF,0xF8,0x00,0x01,0xFF,0xFF,0xF0,
+0x00,0x01,0xFF,0xFF,0xE0,0x00,0x01,0xFF,0xFF,0xC0,
+0x00,0x01,0xFF,0xFF,0x80,0x00,0x01,0xFF,0xFF,0x00,
+0x00,0x00,0xFF,0xFE,0x00,0x00,0x00,0x1F,0xFC,0x02,
+0xBE,0xB3,0x88,0x8B,0x7F,0xFD,0xFF,0xF7,0xFF,0xDF,
+0xFF,0x7F,0xFD,0xFF,0xF7,0xFF,0xDF,0xFF,0x7F,0xFD,
+0xFF,0xF7,0xFF,0xDF,0xFF,0x7F,0xFD,0xFF,0xF7,0xFF,
+0xDF,0xFF,0x7F,0xFC,0xFF,0xC0,0x09,0xBD,0x8F,0x94,
+0xB1,0xFF,0xC0,0x00,0x00,0x03,0xFF,0xF8,0x00,0x00,
+0x07,0xFF,0xFC,0x00,0x00,0x0F,0xFF,0xFC,0x00,0x00,
+0x1F,0xFF,0xFC,0x00,0x00,0x3F,0xFF,0xFC,0x00,0x00,
+0x7F,0xFF,0xFC,0x00,0x01,0x1F,0xFF,0xFF,0x80,0x00,
+0x47,0xFF,0xFF,0xF0,0x00,0x0F,0xFF,0xFF,0xF0,0x00,
+0x00,0x1F,0xFF,0xE0,0x00,0x00,0x0F,0xFF,0xC0,0x00,
+0x00,0x0F,0xFF,0x80,0x01,0x00,0x01,0xFF,0xE0,0x00,
+0x68,0x00,0x3F,0xFC,0x00,0x1A,0x00,0x0F,0xFF,0x00,
+0x06,0x80,0x03,0xFF,0xC0,0x01,0x60,0x00,0xFF,0xF0,
+0x00,0x58,0x00,0x1F,0xFE,0x00,0x10,0x00,0x03,0xFF,
+0xC0,0x00,0x00,0x07,0xFF,0xC0,0x00,0x00,0x07,0xFF,
+0x80,0x00,0x00,0x0F,0xFF,0x80,0x00,0x00,0x0F,0xFF,
+0x80,0x00,0x00,0x0F,0xFF,0xC0,0x00,0x00,0x1F,0xFF,
+0xE0,0x00,0x00,0x1F,0xFF,0xFC,0x00,0x00,0x0F,0xFF,
+0xF8,0x00,0x00,0x0F,0xFF,0xF0,0x00,0x00,0x0F,0xFF,
+0xE0,0x00,0x00,0x07,0xFF,0xC0,0x00,0x00,0x03,0xFF,
+0x80,0x00,0x00,0x1F,0xFF,0x00,0x00,0x00,0xFF,0xFE,
+0x00,0x00,0x07,0xFF,0xFC,0x00,0x00,0x1F,0xFF,0xF8,
+0x00,0x00,0x7F,0xFF,0xF0,0x00,0x01,0xFF,0xFE,0x00,
+0x00,0x07,0xFF,0xF0,0x00,0x00,0x1F,0xFF,0x80,0x00,
+0x00,0x3F,0xFE,0x00,0x80,0x00,0x1F,0xFF,0x00,0x20,
+0x00,0x0F,0xFF,0x80,0x00,0x00,0x1F,0xFE,0x00,0x14,
+0x00,0x0F,0xFF,0x80,0x06,0x80,0x03,0xFF,0xC0,0x01,
+0xA0,0x00,0xFF,0xF0,0x00,0x68,0x00,0x3F,0xFC,0x00,
+0x14,0x00,0x0F,0xFF,0x00,0x04,0x80,0x07,0xFF,0xC0,
+0x00,0x00,0x1F,0xFF,0x80,0x00,0x00,0x7F,0xFE,0x00,
+0x00,0x07,0xFF,0xFC,0x00,0x07,0xFF,0xFF,0xF8,0x00,
+0x13,0xFF,0xFF,0xFC,0x00,0x03,0xFF,0xFF,0xF0,0x00,
+0x07,0xFF,0xFF,0xC0,0x00,0x11,0xFF,0xFF,0xE0,0x00,
+0x03,0xFF,0xFF,0x00,0x00,0x07,0xFF,0xFC,0x00,0x00,
+0x0F,0xFF,0xE0,0x00,0x00,0x1F,0xFC,0x00,0x00,0x00,
+0x00,0x10,0xCC,0x18,0x85,0x38,0x00,0x07,0xFC,0x00,
+0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xFC,0x00,0x00,
+0x00,0x00,0x04,0x01,0xFF,0xFF,0xF0,0x00,0x00,0x00,
+0x00,0xC0,0x3F,0xFF,0xFF,0xC0,0x00,0x00,0x00,0x1C,
+0x07,0xFF,0xFF,0xFF,0x80,0x00,0x00,0x03,0xC1,0xFF,
+0xFF,0xFF,0xFE,0x00,0x00,0x00,0x7C,0x3F,0xFF,0xFF,
+0xFF,0xF8,0x00,0x00,0x0F,0xC3,0xFF,0xFF,0xFF,0xFF,
+0xC0,0x00,0x03,0xFC,0x7F,0xFF,0xFF,0xFF,0xFF,0x00,
+0x00,0x7F,0xCF,0xFF,0xFF,0xFF,0xFF,0xFE,0x00,0x1F,
+0xFD,0xFF,0xFF,0xFF,0xFF,0xFF,0xF8,0x07,0xFF,0xE3,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xBF,0xFE,
+0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xFB,0xFF,0x80,0x03,
+0xFF,0xFF,0xFF,0xFF,0xFF,0x3F,0xE0,0x00,0x0F,0xFF,
+0xFF,0xFF,0xFF,0xE3,0xF8,0x00,0x00,0x3F,0xFF,0xFF,
+0xFF,0xFC,0x3F,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,
+0x83,0xE0,0x00,0x00,0x03,0xFF,0xFF,0xFF,0xF0,0x3C,
+0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFE,0x03,0x80,0x00,
+0x00,0x00,0x3F,0xFF,0xFF,0xC0,0x30,0x00,0x00,0x00,
+0x00,0xFF,0xFF,0xF0,0x02,0x00,0x00,0x00,0x00,0x03,
+0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xFE,
+0x00,0x00,};
+/* font data size: 40352 bytes */
+
+static const unsigned char Arial_96_index[] = {
+0x00,0x00,0x00,0x05,0x00,0x2D,0x00,0x5E,
+0x02,0x38,0x05,0x0A,0x09,0x97,0x0D,0x36,0x0D,0x48,
+0x0E,0x68,0x0F,0xA0,0x10,0x5A,0x10,0xB3,0x10,0xD3,
+0x10,0xE2,0x10,0xEB,0x12,0x10,0x13,0xD3,0x14,0x99,
+0x17,0x08,0x19,0xB5,0x1B,0x9D,0x1D,0x98,0x20,0x42,
+0x21,0xE3,0x24,0x4A,0x26,0xC8,0x26,0xE3,0x27,0x15,
+0x29,0x12,0x29,0x52,0x2B,0x4F,0x2D,0x49,0x34,0xA3,
+0x37,0x86,0x3A,0x2A,0x3D,0x44,0x3F,0xBA,0x40,0x55,
+0x40,0xE2,0x44,0x0A,0x44,0xA1,0x44,0xC4,0x45,0xB6,
+0x49,0x5E,0x49,0xD1,0x4C,0xB4,0x4F,0xA4,0x52,0xE8,
+0x54,0xB1,0x58,0x3A,0x5B,0x77,0x5E,0xCE,0x5F,0x5D,
+0x60,0xCB,0x64,0x35,0x69,0x13,0x6C,0xE2,0x6F,0x7D,
+0x72,0x5F,0x72,0xA9,0x73,0xCC,0x74,0x16,0x74,0xFA,
+0x75,0x13,0x75,0x4B,0x77,0x62,0x79,0x24,0x7A,0xBF,
+0x7C,0x7A,0x7E,0x39,0x7E,0xC9,0x80,0xFE,0x81,0xEC,
+0x82,0x0D,0x82,0x7C,0x84,0x7F,0x84,0xA0,0x86,0x18,
+0x86,0xE8,0x88,0x8F,0x8A,0x52,0x8C,0x00,0x8C,0x80,
+0x8E,0x73,0x8F,0x01,0x8F,0xD1,0x91,0x65,0x93,0xF7,
+0x96,0x1D,0x98,0x9B,0x9A,0x3D,0x9B,0x77,0x9B,0x9C,
+0x9C,0xD7,
+};
+/* font index size: 190 bytes */
+
+const ILI9341_t3_font_t Arial_96 = {
+       Arial_96_index,
+       0,
+       Arial_96_data,
+       1,
+       0,
+       32,
+       126,
+       0,
+       0,
+       16,
+       7,
+       7,
+       5,
+       8,
+       8,
+       148,
+       95
+};
+
+
+
diff --git a/src/glcdfont.c b/src/glcdfont.c

new file mode 100644 (file)

index 0000000..32885a5
--- /dev/null
+++ b/src/glcdfont.c
@@ -0,0 +1,286 @@
+#ifndef FONT5X7_H
+#define FONT5X7_H
+
+#include "glcdfont.h"
+
+// Standard ASCII 5x7 font
+
+const unsigned char glcdfont[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00,
+       0x3E, 0x5B, 0x4F, 0x5B, 0x3E,
+       0x3E, 0x6B, 0x4F, 0x6B, 0x3E,
+       0x1C, 0x3E, 0x7C, 0x3E, 0x1C,
+       0x18, 0x3C, 0x7E, 0x3C, 0x18,
+       0x1C, 0x57, 0x7D, 0x57, 0x1C,
+       0x1C, 0x5E, 0x7F, 0x5E, 0x1C,
+       0x00, 0x18, 0x3C, 0x18, 0x00,
+       0xFF, 0xE7, 0xC3, 0xE7, 0xFF,
+       0x00, 0x18, 0x24, 0x18, 0x00,
+       0xFF, 0xE7, 0xDB, 0xE7, 0xFF,
+       0x30, 0x48, 0x3A, 0x06, 0x0E,
+       0x26, 0x29, 0x79, 0x29, 0x26,
+       0x40, 0x7F, 0x05, 0x05, 0x07,
+       0x40, 0x7F, 0x05, 0x25, 0x3F,
+       0x5A, 0x3C, 0xE7, 0x3C, 0x5A,
+       0x7F, 0x3E, 0x1C, 0x1C, 0x08,
+       0x08, 0x1C, 0x1C, 0x3E, 0x7F,
+       0x14, 0x22, 0x7F, 0x22, 0x14,
+       0x5F, 0x5F, 0x00, 0x5F, 0x5F,
+       0x06, 0x09, 0x7F, 0x01, 0x7F,
+       0x00, 0x66, 0x89, 0x95, 0x6A,
+       0x60, 0x60, 0x60, 0x60, 0x60,
+       0x94, 0xA2, 0xFF, 0xA2, 0x94,
+       0x08, 0x04, 0x7E, 0x04, 0x08,
+       0x10, 0x20, 0x7E, 0x20, 0x10,
+       0x08, 0x08, 0x2A, 0x1C, 0x08,
+       0x08, 0x1C, 0x2A, 0x08, 0x08,
+       0x1E, 0x10, 0x10, 0x10, 0x10,
+       0x0C, 0x1E, 0x0C, 0x1E, 0x0C,
+       0x30, 0x38, 0x3E, 0x38, 0x30,
+       0x06, 0x0E, 0x3E, 0x0E, 0x06,
+       0x00, 0x00, 0x00, 0x00, 0x00,
+       0x00, 0x00, 0x5F, 0x00, 0x00,
+       0x00, 0x07, 0x00, 0x07, 0x00,
+       0x14, 0x7F, 0x14, 0x7F, 0x14,
+       0x24, 0x2A, 0x7F, 0x2A, 0x12,
+       0x23, 0x13, 0x08, 0x64, 0x62,
+       0x36, 0x49, 0x56, 0x20, 0x50,
+       0x00, 0x08, 0x07, 0x03, 0x00,
+       0x00, 0x1C, 0x22, 0x41, 0x00,
+       0x00, 0x41, 0x22, 0x1C, 0x00,
+       0x2A, 0x1C, 0x7F, 0x1C, 0x2A,
+       0x08, 0x08, 0x3E, 0x08, 0x08,
+       0x00, 0x80, 0x70, 0x30, 0x00,
+       0x08, 0x08, 0x08, 0x08, 0x08,
+       0x00, 0x00, 0x60, 0x60, 0x00,
+       0x20, 0x10, 0x08, 0x04, 0x02,
+       0x3E, 0x51, 0x49, 0x45, 0x3E,
+       0x00, 0x42, 0x7F, 0x40, 0x00,
+       0x72, 0x49, 0x49, 0x49, 0x46,
+       0x21, 0x41, 0x49, 0x4D, 0x33,
+       0x18, 0x14, 0x12, 0x7F, 0x10,
+       0x27, 0x45, 0x45, 0x45, 0x39,
+       0x3C, 0x4A, 0x49, 0x49, 0x31,
+       0x41, 0x21, 0x11, 0x09, 0x07,
+       0x36, 0x49, 0x49, 0x49, 0x36,
+       0x46, 0x49, 0x49, 0x29, 0x1E,
+       0x00, 0x00, 0x14, 0x00, 0x00,
+       0x00, 0x40, 0x34, 0x00, 0x00,
+       0x00, 0x08, 0x14, 0x22, 0x41,
+       0x14, 0x14, 0x14, 0x14, 0x14,
+       0x00, 0x41, 0x22, 0x14, 0x08,
+       0x02, 0x01, 0x59, 0x09, 0x06,
+       0x3E, 0x41, 0x5D, 0x59, 0x4E,
+       0x7C, 0x12, 0x11, 0x12, 0x7C,
+       0x7F, 0x49, 0x49, 0x49, 0x36,
+       0x3E, 0x41, 0x41, 0x41, 0x22,
+       0x7F, 0x41, 0x41, 0x41, 0x3E,
+       0x7F, 0x49, 0x49, 0x49, 0x41,
+       0x7F, 0x09, 0x09, 0x09, 0x01,
+       0x3E, 0x41, 0x41, 0x51, 0x73,
+       0x7F, 0x08, 0x08, 0x08, 0x7F,
+       0x00, 0x41, 0x7F, 0x41, 0x00,
+       0x20, 0x40, 0x41, 0x3F, 0x01,
+       0x7F, 0x08, 0x14, 0x22, 0x41,
+       0x7F, 0x40, 0x40, 0x40, 0x40,
+       0x7F, 0x02, 0x1C, 0x02, 0x7F,
+       0x7F, 0x04, 0x08, 0x10, 0x7F,
+       0x3E, 0x41, 0x41, 0x41, 0x3E,
+       0x7F, 0x09, 0x09, 0x09, 0x06,
+       0x3E, 0x41, 0x51, 0x21, 0x5E,
+       0x7F, 0x09, 0x19, 0x29, 0x46,
+       0x26, 0x49, 0x49, 0x49, 0x32,
+       0x03, 0x01, 0x7F, 0x01, 0x03,
+       0x3F, 0x40, 0x40, 0x40, 0x3F,
+       0x1F, 0x20, 0x40, 0x20, 0x1F,
+       0x3F, 0x40, 0x38, 0x40, 0x3F,
+       0x63, 0x14, 0x08, 0x14, 0x63,
+       0x03, 0x04, 0x78, 0x04, 0x03,
+       0x61, 0x59, 0x49, 0x4D, 0x43,
+       0x00, 0x7F, 0x41, 0x41, 0x41,
+       0x02, 0x04, 0x08, 0x10, 0x20,
+       0x00, 0x41, 0x41, 0x41, 0x7F,
+       0x04, 0x02, 0x01, 0x02, 0x04,
+       0x40, 0x40, 0x40, 0x40, 0x40,
+       0x00, 0x03, 0x07, 0x08, 0x00,
+       0x20, 0x54, 0x54, 0x78, 0x40,
+       0x7F, 0x28, 0x44, 0x44, 0x38,
+       0x38, 0x44, 0x44, 0x44, 0x28,
+       0x38, 0x44, 0x44, 0x28, 0x7F,
+       0x38, 0x54, 0x54, 0x54, 0x18,
+       0x00, 0x08, 0x7E, 0x09, 0x02,
+       0x18, 0xA4, 0xA4, 0x9C, 0x78,
+       0x7F, 0x08, 0x04, 0x04, 0x78,
+       0x00, 0x44, 0x7D, 0x40, 0x00,
+       0x20, 0x40, 0x40, 0x3D, 0x00,
+       0x7F, 0x10, 0x28, 0x44, 0x00,
+       0x00, 0x41, 0x7F, 0x40, 0x00,
+       0x7C, 0x04, 0x78, 0x04, 0x78,
+       0x7C, 0x08, 0x04, 0x04, 0x78,
+       0x38, 0x44, 0x44, 0x44, 0x38,
+       0xFC, 0x18, 0x24, 0x24, 0x18,
+       0x18, 0x24, 0x24, 0x18, 0xFC,
+       0x7C, 0x08, 0x04, 0x04, 0x08,
+       0x48, 0x54, 0x54, 0x54, 0x24,
+       0x04, 0x04, 0x3F, 0x44, 0x24,
+       0x3C, 0x40, 0x40, 0x20, 0x7C,
+       0x1C, 0x20, 0x40, 0x20, 0x1C,
+       0x3C, 0x40, 0x30, 0x40, 0x3C,
+       0x44, 0x28, 0x10, 0x28, 0x44,
+       0x4C, 0x90, 0x90, 0x90, 0x7C,
+       0x44, 0x64, 0x54, 0x4C, 0x44,
+       0x00, 0x08, 0x36, 0x41, 0x00,
+       0x00, 0x00, 0x77, 0x00, 0x00,
+       0x00, 0x41, 0x36, 0x08, 0x00,
+       0x02, 0x01, 0x02, 0x04, 0x02,
+       0x3C, 0x26, 0x23, 0x26, 0x3C,
+       0x1E, 0xA1, 0xA1, 0x61, 0x12,
+       0x3A, 0x40, 0x40, 0x20, 0x7A,
+       0x38, 0x54, 0x54, 0x55, 0x59,
+       0x21, 0x55, 0x55, 0x79, 0x41,
+       0x21, 0x54, 0x54, 0x78, 0x41,
+       0x21, 0x55, 0x54, 0x78, 0x40,
+       0x20, 0x54, 0x55, 0x79, 0x40,
+       0x0C, 0x1E, 0x52, 0x72, 0x12,
+       0x39, 0x55, 0x55, 0x55, 0x59,
+       0x39, 0x54, 0x54, 0x54, 0x59,
+       0x39, 0x55, 0x54, 0x54, 0x58,
+       0x00, 0x00, 0x45, 0x7C, 0x41,
+       0x00, 0x02, 0x45, 0x7D, 0x42,
+       0x00, 0x01, 0x45, 0x7C, 0x40,
+       0xF0, 0x29, 0x24, 0x29, 0xF0,
+       0xF0, 0x28, 0x25, 0x28, 0xF0,
+       0x7C, 0x54, 0x55, 0x45, 0x00,
+       0x20, 0x54, 0x54, 0x7C, 0x54,
+       0x7C, 0x0A, 0x09, 0x7F, 0x49,
+       0x32, 0x49, 0x49, 0x49, 0x32,
+       0x32, 0x48, 0x48, 0x48, 0x32,
+       0x32, 0x4A, 0x48, 0x48, 0x30,
+       0x3A, 0x41, 0x41, 0x21, 0x7A,
+       0x3A, 0x42, 0x40, 0x20, 0x78,
+       0x00, 0x9D, 0xA0, 0xA0, 0x7D,
+       0x39, 0x44, 0x44, 0x44, 0x39,
+       0x3D, 0x40, 0x40, 0x40, 0x3D,
+       0x3C, 0x24, 0xFF, 0x24, 0x24,
+       0x48, 0x7E, 0x49, 0x43, 0x66,
+       0x2B, 0x2F, 0xFC, 0x2F, 0x2B,
+       0xFF, 0x09, 0x29, 0xF6, 0x20,
+       0xC0, 0x88, 0x7E, 0x09, 0x03,
+       0x20, 0x54, 0x54, 0x79, 0x41,
+       0x00, 0x00, 0x44, 0x7D, 0x41,
+       0x30, 0x48, 0x48, 0x4A, 0x32,
+       0x38, 0x40, 0x40, 0x22, 0x7A,
+       0x00, 0x7A, 0x0A, 0x0A, 0x72,
+       0x7D, 0x0D, 0x19, 0x31, 0x7D,
+       0x26, 0x29, 0x29, 0x2F, 0x28,
+       0x26, 0x29, 0x29, 0x29, 0x26,
+       0x30, 0x48, 0x4D, 0x40, 0x20,
+       0x38, 0x08, 0x08, 0x08, 0x08,
+       0x08, 0x08, 0x08, 0x08, 0x38,
+       0x2F, 0x10, 0xC8, 0xAC, 0xBA,
+       0x2F, 0x10, 0x28, 0x34, 0xFA,
+       0x00, 0x00, 0x7B, 0x00, 0x00,
+       0x08, 0x14, 0x2A, 0x14, 0x22,
+       0x22, 0x14, 0x2A, 0x14, 0x08,
+       0xAA, 0x00, 0x55, 0x00, 0xAA,
+       0xAA, 0x55, 0xAA, 0x55, 0xAA,
+       0x00, 0x00, 0x00, 0xFF, 0x00,
+       0x10, 0x10, 0x10, 0xFF, 0x00,
+       0x14, 0x14, 0x14, 0xFF, 0x00,
+       0x10, 0x10, 0xFF, 0x00, 0xFF,
+       0x10, 0x10, 0xF0, 0x10, 0xF0,
+       0x14, 0x14, 0x14, 0xFC, 0x00,
+       0x14, 0x14, 0xF7, 0x00, 0xFF,
+       0x00, 0x00, 0xFF, 0x00, 0xFF,
+       0x14, 0x14, 0xF4, 0x04, 0xFC,
+       0x14, 0x14, 0x17, 0x10, 0x1F,
+       0x10, 0x10, 0x1F, 0x10, 0x1F,
+       0x14, 0x14, 0x14, 0x1F, 0x00,
+       0x10, 0x10, 0x10, 0xF0, 0x00,
+       0x00, 0x00, 0x00, 0x1F, 0x10,
+       0x10, 0x10, 0x10, 0x1F, 0x10,
+       0x10, 0x10, 0x10, 0xF0, 0x10,
+       0x00, 0x00, 0x00, 0xFF, 0x10,
+       0x10, 0x10, 0x10, 0x10, 0x10,
+       0x10, 0x10, 0x10, 0xFF, 0x10,
+       0x00, 0x00, 0x00, 0xFF, 0x14,
+       0x00, 0x00, 0xFF, 0x00, 0xFF,
+       0x00, 0x00, 0x1F, 0x10, 0x17,
+       0x00, 0x00, 0xFC, 0x04, 0xF4,
+       0x14, 0x14, 0x17, 0x10, 0x17,
+       0x14, 0x14, 0xF4, 0x04, 0xF4,
+       0x00, 0x00, 0xFF, 0x00, 0xF7,
+       0x14, 0x14, 0x14, 0x14, 0x14,
+       0x14, 0x14, 0xF7, 0x00, 0xF7,
+       0x14, 0x14, 0x14, 0x17, 0x14,
+       0x10, 0x10, 0x1F, 0x10, 0x1F,
+       0x14, 0x14, 0x14, 0xF4, 0x14,
+       0x10, 0x10, 0xF0, 0x10, 0xF0,
+       0x00, 0x00, 0x1F, 0x10, 0x1F,
+       0x00, 0x00, 0x00, 0x1F, 0x14,
+       0x00, 0x00, 0x00, 0xFC, 0x14,
+       0x00, 0x00, 0xF0, 0x10, 0xF0,
+       0x10, 0x10, 0xFF, 0x10, 0xFF,
+       0x14, 0x14, 0x14, 0xFF, 0x14,
+       0x10, 0x10, 0x10, 0x1F, 0x00,
+       0x00, 0x00, 0x00, 0xF0, 0x10,
+       0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+       0xF0, 0xF0, 0xF0, 0xF0, 0xF0,
+       0xFF, 0xFF, 0xFF, 0x00, 0x00,
+       0x00, 0x00, 0x00, 0xFF, 0xFF,
+       0x0F, 0x0F, 0x0F, 0x0F, 0x0F,
+       0x38, 0x44, 0x44, 0x38, 0x44,
+       0x7C, 0x2A, 0x2A, 0x3E, 0x14,
+       0x7E, 0x02, 0x02, 0x06, 0x06,
+       0x02, 0x7E, 0x02, 0x7E, 0x02,
+       0x63, 0x55, 0x49, 0x41, 0x63,
+       0x38, 0x44, 0x44, 0x3C, 0x04,
+       0x40, 0x7E, 0x20, 0x1E, 0x20,
+       0x06, 0x02, 0x7E, 0x02, 0x02,
+       0x99, 0xA5, 0xE7, 0xA5, 0x99,
+       0x1C, 0x2A, 0x49, 0x2A, 0x1C,
+       0x4C, 0x72, 0x01, 0x72, 0x4C,
+       0x30, 0x4A, 0x4D, 0x4D, 0x30,
+       0x30, 0x48, 0x78, 0x48, 0x30,
+       0xBC, 0x62, 0x5A, 0x46, 0x3D,
+       0x3E, 0x49, 0x49, 0x49, 0x00,
+       0x7E, 0x01, 0x01, 0x01, 0x7E,
+       0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
+       0x44, 0x44, 0x5F, 0x44, 0x44,
+       0x40, 0x51, 0x4A, 0x44, 0x40,
+       0x40, 0x44, 0x4A, 0x51, 0x40,
+       0x00, 0x00, 0xFF, 0x01, 0x03,
+       0xE0, 0x80, 0xFF, 0x00, 0x00,
+       0x08, 0x08, 0x6B, 0x6B, 0x08,
+       0x36, 0x12, 0x36, 0x24, 0x36,
+       0x06, 0x0F, 0x09, 0x0F, 0x06,
+       0x00, 0x00, 0x18, 0x18, 0x00,
+       0x00, 0x00, 0x10, 0x10, 0x00,
+       0x30, 0x40, 0xFF, 0x01, 0x01,
+       0x00, 0x1F, 0x01, 0x01, 0x1E,
+       0x00, 0x19, 0x1D, 0x17, 0x12,
+       0x00, 0x3C, 0x3C, 0x3C, 0x3C,
+       0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+const ILI9341_t3_font_t Font5x7 = {
+       0,
+       0,
+       0,
+       0,
+       0,
+       0,
+       0,
+       0,
+       0,
+       0,
+       0,
+       0,
+       0,
+       0,
+       0,
+       0,
+       0
+};
+
+#endif // FONT5X7_H
diff --git a/src/i2c.c b/src/i2c.c

new file mode 100644 (file)

index 0000000..6ca5ee6
--- /dev/null
+++ b/src/i2c.c
@@ -0,0 +1,227 @@
+/*
+ * i2c.c
+ *
+ *  Created on: Sep 30, 2017
+ *      Author: pascal.spring
+ */
+
+
+#include <stm32f0xx_i2c.h>
+
+#include "i2c.h"
+
+struct i2c_struct_type i2c;
+
+void i2c_init(I2C_TypeDef * I2Cx)
+{
+
+    if(I2Cx==I2C1)
+    {
+        RCC->APB1RSTR |=  RCC_APB1RSTR_I2C1RST;
+        RCC->APB1RSTR &= ~RCC_APB1RSTR_I2C1RST;
+        RCC->CFGR3 |= RCC_CFGR3_I2C1SW;
+
+    }
+    else
+    {
+        RCC->APB1RSTR |=  RCC_APB1RSTR_I2C2RST;
+        RCC->APB1RSTR &= ~RCC_APB1RSTR_I2C2RST;
+    }
+
+
+       I2Cx->CR1 = 0x0;
+       I2Cx->CR2 = 0x0;
+       I2Cx->TIMINGR = 0x0;
+
+       RCC->CFGR3 |= RCC_CFGR3_I2C1SW;
+       //RCC->APB1ENR |= RCC_APB1ENR_I2C1EN;
+
+       I2Cx->TIMINGR |= (5<<28);                               // prescaler 1:4 == 12MHz
+       //I2C1->TIMINGR |= (176<<20);
+       I2Cx->TIMINGR |= (37<<8);                               // SCL high time == 15 cycles == 1,25uS
+       I2Cx->TIMINGR |= (37<<0);                               // SCL low time == 15 cycles == 1,25uS, 37 = 100kHz, 9 = 400kHz
+
+       I2Cx->CR1 |= I2C_CR1_PE;
+
+}
+
+uint8_t i2c_status(uint8_t stat) {
+       uint32_t flags1,last_ev;
+       uint32_t status[6] = { 0x8004,
+                                                       0x8001,
+                                                       0x8000,
+                                                       0x8009,
+                                                       0x8008,
+       };
+       /*
+       uint32_t status[6] = { 0x30040,                         // 0 - master byte received - BUSY MSL RXNE
+                                                 0x70084,                      // 1 - master byte transmitted - BUSY MSL TXE TRA BTF
+                                                 0x30001,                      // 2 - master mode select - BUSY MSL SB
+                                                 0x70082,                      // 3 - master transmitter mode selected - BUSY MSL ADDR TXE TRA
+                                                 0x30002,                      // 4 - master receiver mode selected - BUSY MSL ADDR
+                                                 };
+       */
+       flags1 = I2C1->ISR;
+       //flags2 = I2C1->SR2;
+       //flags2<<=16;
+
+       last_ev =(flags1) & 0xffff;
+
+       if((last_ev & status[stat])!=status[stat]) {
+               return 0;
+       }
+       else {
+               return 1;
+       }
+}
+
+
+void i2c_start(I2C_TypeDef * I2Cx) {
+       //while(I2C1->ISR & I2C_ISR_BUSY);
+       I2Cx->CR2 |= I2C_CR2_START;                             // set start condition
+       }
+
+/*
+void i2c_restart(void) {
+       I2C1->CR2 |= 0x2000;
+       while(!(i2c_status(2)));
+       }
+*/
+void i2c_stop(I2C_TypeDef * I2Cx)
+{
+       I2Cx->CR2 |= I2C_CR2_STOP;                      }
+
+void i2c_reset(I2C_TypeDef * I2Cx)
+{
+       while(!(I2C1->ISR & I2C_ISR_STOPF));
+       I2Cx->ICR &= ~(I2C_ICR_STOPCF);
+}
+
+void i2c_autoend(I2C_TypeDef * I2Cx, uint8_t autoend) {
+       autoend = autoend & 0x1;
+       I2Cx->CR2 = ((uint32_t)(autoend) << 25);
+}
+
+void i2c_set_nbytes(I2C_TypeDef * I2Cx, uint8_t nbytes) {
+       uint32_t tmp=0;
+       tmp |= I2C_CR2_NBYTES;
+       I2Cx->CR2 &= ~(tmp);
+       I2Cx->CR2 |= ((uint32_t)(nbytes)<<16);
+}
+
+uint8_t i2c_read_ack(I2C_TypeDef * I2Cx, uint8_t * data, uint8_t count, uint8_t device)
+{
+       uint16_t cycle;
+       uint8_t state=0;
+
+    if(i2c.state==I2C_IDLE && i2c.device==0)
+    {
+       i2c_autoend(I2Cx,0);
+       i2c_set_nbytes(I2Cx,count);
+       i2c_write_addr(I2Cx,device,READ);
+       i2c.device=device;
+       i2c.rx_idx=count;
+       i2c.tx_idx=0;
+       i2c.buf_cnt=0;
+       I2C1->CR1 |= I2C_CR1_RXIE;
+
+       i2c_start(I2Cx);
+
+       cycle=(uint16_t)(SystemCoreClock/(I2C_SPEED/i2c.rx_idx));
+
+       while(cycle--)
+       {
+               if(i2c.state==I2C_RECEIVING_DATA)
+               {
+                       cycle=0;
+               }
+               //asm("NOP");
+       }
+
+       I2Cx->ICR=0;
+    }
+    if(i2c.state==I2C_RECEIVING_DATA && i2c.device==device)
+    {
+
+       state=i2c.state;
+       for(uint8_t i=0;i<count;i++)
+       {
+               data[i]=i2c.rx_buf[i];
+       }
+               i2c.state=0;
+               i2c.device=0;
+    }
+    return state;
+}
+
+uint8_t i2c_read_nack(void) {
+       //uint8_t tmp=0;
+
+       //tmp = I2C1->RXDR;
+       I2C1->CR2 |= (I2C_CR2_NACK);                    // disable ACK flag
+       //I2C1->CR2 |= (I2C_CR2_START);
+       while(!(I2C1->ISR & I2C_ISR_RXNE));
+       //while(!(i2c_status(0)));
+       return I2C1->RXDR;
+}
+
+void i2c_write_addr(I2C_TypeDef * I2Cx, uint8_t addr, uint8_t dir) {
+       //while(I2C1->ISR & I2C_ISR_BUSY);
+       uint32_t tmp=0;
+       dir = dir & 0x1;
+       tmp |= I2C_CR2_SADD | I2C_CR2_RD_WRN;
+       I2Cx->CR2 &= ~(tmp);
+       I2Cx->CR2 |= ((uint32_t)(addr)<<1);
+       I2Cx->CR2 |= ((uint32_t)(dir)<<10);
+}
+
+
+
+uint8_t i2c_write(I2C_TypeDef * I2Cx, uint8_t * data, uint8_t count, uint8_t device )
+{
+       uint16_t cycle;
+       uint8_t state=0;
+
+    if(i2c.state==I2C_IDLE && i2c.device==0)
+    {
+       i2c_autoend(I2Cx,0);
+       i2c_set_nbytes(I2Cx, count);
+       i2c_write_addr(I2Cx, device,0);
+       i2c.device=device;
+       i2c.rx_idx=0;
+       i2c.tx_idx=count;
+       i2c.buf_cnt=0;
+       for(uint8_t i=0;i<count;i++)
+       {
+               i2c.tx_buf[i]=data[i];
+       }
+       I2Cx->CR1 |= I2C_CR1_TXIE | I2C_CR1_TCIE;
+       i2c_start(I2Cx);
+    }
+
+
+
+       cycle=(uint16_t)(SystemCoreClock/(I2C_SPEED/i2c.tx_idx));
+
+       while(cycle--)
+       {
+               if(i2c.state==I2C_SENDING_DATA)
+               {
+                       cycle=0;
+               }
+       }
+       (void)I2Cx->ICR;
+
+    if(i2c.state==I2C_SENDING_DATA && i2c.device==device)
+    {
+       state=i2c.state;
+               i2c.state=0;
+               i2c.device=0;
+
+    }
+
+    I2Cx->ICR=0;
+
+    return state;
+}
+
diff --git a/src/ili9341.c b/src/ili9341.c

new file mode 100644 (file)

index 0000000..4a7cb9f
--- /dev/null
+++ b/src/ili9341.c
@@ -0,0 +1,935 @@
+//#ifndef __ILI9341_H
+#include "ili9341.h"
+//#endif
+
+#ifndef __DELAY_H
+#include "delay.h"
+#endif
+
+volatile uint16_t TFT_WIDTH=ILI9341_TFTWIDTH;
+volatile uint16_t TFT_HEIGHT=ILI9341_TFTHEIGHT;
+
+#define swap(a,b) do { __typeof__ (a) _a = (a); __typeof__(b) _b = (b); a = _b; b = _a; } while(0)
+#define min(a,b) ({ __typeof__ (a) _a = (a); __typeof__ (b) _b = (b); _a < _b ? _a : _b; })
+#define max(a,b) ({ __typeof__ (a) _a = (a); __typeof__ (b) _b = (b); _a > _b ? _a : _b; })
+
+int16_t width(void) { return TFT_WIDTH; }
+int16_t height(void) { return TFT_HEIGHT; }
+
+void ili9341_updatedisplayclip() {
+       _displayclipx1 = max(0, min(_clipx1 + _originx, width()));
+       _displayclipx2 = max(0, min(_clipx2 + _originx, width()));
+       _displayclipy1 = max(0, min(_clipy1 + _originy, height()));
+       _displayclipy2 = max(0, min(_clipy2 + _originy, height()));
+       _invisible = (_displayclipx1 == _displayclipx2 || _displayclipy1 == _displayclipy2);
+       _standard = (_displayclipx1 == 0) && (_displayclipx2 == TFT_WIDTH) && (_displayclipy1 == 0) && (_displayclipy2 == TFT_HEIGHT);
+}
+
+void ili9341_setorigin(void) {
+       _originx = 0;
+       _originy = 0;
+       ili9341_updatedisplayclip();
+ }
+
+/*
+void getOrigin(int16_t *x, int16_t *y) {
+   *x = _originx;
+   *y = _originy;
+ }
+*/
+
+void ili9341_setcliprect() {
+       _clipx1 = 0;
+       _clipy1 = 0;
+       _clipx2 = TFT_WIDTH;
+       _clipy2 = TFT_HEIGHT;
+       ili9341_updatedisplayclip();
+}
+
+void ili9341_hard_init(void)//init hardware
+{
+    GPIOA->BSRR = RST;
+    GPIOA->BSRR = DC;
+    GPIOA->BRR = CS;
+
+
+
+}
+
+void ili9341_hard_reset(void)//hard reset display
+{
+       /*
+    GPIOA->BSRR = RST;
+    delay_ms(200);
+    GPIOA->BRR = RST;
+    delay_ms(200);
+    GPIOA->BSRR = RST;
+    delay_ms(200);
+       */
+}
+
+void ili9341_spi_init(void)//set spi speed and settings
+{
+       //GPIOB->CRL=0x03433330;        // set port for sw spi
+       //GPIOB->CRL |= 0x6;    // set port for hw spi
+       GPIOA->BSRR=CS;
+}
+
+void ili9341_spi_send(SPI_TypeDef * SPIx, uint16_t spi_data)//send spi data to display
+{
+       //GPIOA->BRR = CS;
+       //spi_buf=spi_data;
+       ili9341_buf=spi_data;
+       SPIx->CR2 |= SPI_CR2_TXEIE;
+}
+
+
+void ili9341_writecommand8(uint8_t com)//command write
+{
+       //SPI1->CR2 &= ~SPI_CR2_DS_3;
+       //SPI1->CR1 &= ~SPI_CR1_SPE;
+       //SPI1->CR1 = (SPI1->CR1 & 0xf7bf);
+       GPIOA->BRR = DC;
+
+       //SPI1->CR1 &= ~(SPI_CR1_DFF);
+       //SPI1->CR1 |= SPI_CR1_SPE;
+    ili9341_spi_send(SPI1, com);
+}
+
+
+void ili9341_writedata8(uint8_t data)//data write
+{
+       //SPI1->CR1 &= ~SPI_CR1_SPE;
+       //SPI1->CR1 = (SPI1->CR1 & 0xf7bf);
+       GPIOA->BSRR = DC;
+
+       //SPI1->CR1 &= ~(SPI_CR1_DFF);
+       //SPI1->CR1 |= SPI_CR1_SPE;
+    ili9341_spi_send(SPI1, data);
+}
+
+
+void ili9341_writedata16(uint16_t data)
+{
+       //SPI1->CR2 |= SPI_CR2_DS_3;
+       SPI1->CR1 &= ~SPI_CR1_SPE;
+       //SPI1->CR1 = (SPI1->CR1 & 0xf7bf);
+       GPIOB->BSRR = DC;
+
+       //SPI1->CR1 |= SPI_CR1_DFF;
+       SPI1->CR1 |= SPI_CR1_SPE;
+       data = (((data & 0x00ff) << 8) | ((data & 0xff00) >> 8));
+       ili9341_spi_send(SPI1, data);
+
+}
+
+
+void color565toRGB14(uint16_t color, int16_t *r, int16_t *g, int16_t *b)
+{
+       *r = (color>>2)&0x3E00;
+       *g = (color<<3)&0x3F00;
+       *b = (color<<9)&0x3E00;
+}
+
+uint16_t RGB14tocolor565(int16_t r, int16_t g, int16_t b)
+{
+       return (((r & 0x3E00) << 2) | ((g & 0x3F00) >>3) | ((b & 0x3E00) >> 9));
+}
+
+
+void ili9341_setaddress(uint16_t x1,uint16_t y1,uint16_t x2,uint16_t y2)//set coordinate for print or other function
+{
+    ili9341_writecommand8(0x2A);
+
+    ili9341_writedata8(x1>>8);
+    ili9341_writedata8(x1);
+    ili9341_writedata8(x2>>8);
+    ili9341_writedata8(x2);
+
+    ili9341_writecommand8(0x2B);
+
+    ili9341_writedata8(y1>>8);
+    ili9341_writedata8(y1);
+    ili9341_writedata8(y2);
+    ili9341_writedata8(y2);
+
+    ili9341_writecommand8(0x2C);//meory write
+}
+
+
+/*void ili9341_hard_reset(void)//hard reset display
+{
+    rstport |=(1<<rst);//pull high if low previously
+    _delay_ms(200);
+    rstport &=~(1<<rst);//low for reset
+    _delay_ms(200);
+    rstport |=(1<<rst);//again pull high for normal operation
+    _delay_ms(200);
+    }
+*/
+
+void ili9341_init(void)//set up display using predefined command sequence
+{
+
+       ili9341_hard_init();
+       ili9341_spi_init();
+       ili9341_hard_reset();
+
+       ili9341_writecommand8(0x01);//soft reset
+       //delay_ms(1000);
+       //power control A
+       ili9341_writecommand8(0xCB);
+       ili9341_writedata8(0x39);
+       ili9341_writedata8(0x2C);
+       ili9341_writedata8(0x00);
+       ili9341_writedata8(0x34);
+       ili9341_writedata8(0x02);
+
+       //power control B
+       ili9341_writecommand8(0xCF);
+       ili9341_writedata8(0x00);
+       ili9341_writedata8(0xC1);
+       ili9341_writedata8(0x30);
+
+       //driver timing control A
+       ili9341_writecommand8(0xE8);
+       ili9341_writedata8(0x85);
+       ili9341_writedata8(0x00);
+       ili9341_writedata8(0x78);
+
+       //driver timing control B
+       ili9341_writecommand8(0xEA);
+       ili9341_writedata8(0x00);
+       ili9341_writedata8(0x00);
+
+       //power on sequence control
+       ili9341_writecommand8(0xED);
+       ili9341_writedata8(0x64);
+       ili9341_writedata8(0x03);
+       ili9341_writedata8(0x12);
+       ili9341_writedata8(0x81);
+
+       //pump ratio control
+       ili9341_writecommand8(0xF7);
+       ili9341_writedata8(0x20);
+
+       //power control,VRH[5:0]
+       ili9341_writecommand8(0xC0);
+       ili9341_writedata8(0x23);
+
+       //Power control,SAP[2:0];BT[3:0]
+       ili9341_writecommand8(0xC1);
+       ili9341_writedata8(0x10);
+
+       //vcm control
+       ili9341_writecommand8(0xC5);
+       ili9341_writedata8(0x3E);
+       ili9341_writedata8(0x28);
+
+       //vcm control 2
+       ili9341_writecommand8(0xC7);
+       ili9341_writedata8(0x86);
+
+       //memory access control
+       ili9341_writecommand8(0x36);
+       ili9341_writedata8(0x48);
+
+       //pixel format
+       ili9341_writecommand8(0x3A);
+       ili9341_writedata8(0x55);
+
+       //frameration control,normal mode full colors
+       ili9341_writecommand8(0xB1);
+       ili9341_writedata8(0x00);
+       ili9341_writedata8(0x18);
+
+       //display function control
+       ili9341_writecommand8(0xB6);
+       ili9341_writedata8(0x08);
+       ili9341_writedata8(0x82);
+       ili9341_writedata8(0x27);
+
+       //3gamma function disable
+       ili9341_writecommand8(0xF2);
+       ili9341_writedata8(0x00);
+
+       //gamma curve selected
+       ili9341_writecommand8(0x26);
+       ili9341_writedata8(0x01);
+
+       //set positive gamma correction
+       ili9341_writecommand8(0xE0);
+       ili9341_writedata8(0x0F);
+       ili9341_writedata8(0x31);
+       ili9341_writedata8(0x2B);
+       ili9341_writedata8(0x0C);
+       ili9341_writedata8(0x0E);
+       ili9341_writedata8(0x08);
+       ili9341_writedata8(0x4E);
+       ili9341_writedata8(0xF1);
+       ili9341_writedata8(0x37);
+       ili9341_writedata8(0x07);
+       ili9341_writedata8(0x10);
+       ili9341_writedata8(0x03);
+       ili9341_writedata8(0x0E);
+       ili9341_writedata8(0x09);
+       ili9341_writedata8(0x00);
+
+       //set negative gamma correction
+       ili9341_writecommand8(0xE1);
+       ili9341_writedata8(0x00);
+       ili9341_writedata8(0x0E);
+       ili9341_writedata8(0x14);
+       ili9341_writedata8(0x03);
+       ili9341_writedata8(0x11);
+       ili9341_writedata8(0x07);
+       ili9341_writedata8(0x31);
+       ili9341_writedata8(0xC1);
+       ili9341_writedata8(0x48);
+       ili9341_writedata8(0x08);
+       ili9341_writedata8(0x0F);
+       ili9341_writedata8(0x0C);
+       ili9341_writedata8(0x31);
+       ili9341_writedata8(0x36);
+       ili9341_writedata8(0x0F);
+
+       //exit sleep
+       ili9341_writecommand8(0x11);
+       //delay_ms(120);
+       //display on
+       ili9341_writecommand8(0x29);
+
+}
+
+//set color for drawing
+void ili9341_pushcolor(uint16_t color)
+{
+    ili9341_writedata8((uint8_t)(color>>8));
+    ili9341_writedata8((uint8_t)color);
+}
+
+
+//clear lcd and fill with color
+void ili9341_clear(uint16_t color)
+{
+    uint16_t i,j;
+    ili9341_setaddress(0,0,TFT_WIDTH-1,TFT_HEIGHT-1);
+
+    for(i=0;i<TFT_WIDTH;i++)
+    {
+        for(j=0;j<TFT_HEIGHT;j++)
+        {
+            ili9341_pushcolor(color);
+        }
+    }
+}
+
+
+
+// draw pixel
+void ili9341_drawpixel(int16_t x3, int16_t y3,uint16_t color) //pixels will always be counted from right side.x is representing LCD width which will always be less tha 240.Y is representing LCD height which will always be less than 320
+{
+    if((x3 < 0) ||(x3 >=TFT_WIDTH) || (y3 < 0) || (y3 >=TFT_HEIGHT)) return;
+       //if((x3 >= TFT_WIDTH) || (y3 >=TFT_HEIGHT)) return;
+    ili9341_setaddress(x3,y3,x3+1,y3+1);
+
+    ili9341_pushcolor(color);
+}
+
+
+//draw vertical line
+void ili9341_drawvline(uint16_t x,uint16_t y,uint16_t h,uint16_t color)//basically we will see this line horizental if we see the display 320*240
+{
+    if((x >=TFT_WIDTH) || (y >=TFT_HEIGHT)) return;
+    if((y+h-1)>=TFT_HEIGHT)
+    {
+       h=TFT_HEIGHT-y;
+    }
+    ili9341_setaddress(x,y,x,y+h-1);
+    while(h--)
+    {
+        ili9341_pushcolor(color);
+    }
+}
+
+
+//draw horizental line
+
+void ili9341_drawhline(int16_t x,int16_t y,uint16_t w,uint16_t color)
+{
+    if((x >=TFT_WIDTH) || (y >=TFT_HEIGHT || y < 0)) return;
+    if(x < 0)
+    {
+       w += x;
+       x=0;
+    }
+    if((x+w-1)>=TFT_WIDTH)
+    {
+        w=((uint16_t)(TFT_WIDTH-x));
+    }
+       ili9341_setaddress(x,y,((uint16_t)(x+w-1)),y);
+    while(w--)
+    {
+        ili9341_pushcolor(color);
+    }
+}
+
+void ili9341_drawline(int16_t x0, int16_t y0, int16_t x1, int16_t y1, uint16_t color)
+{
+       if (y0 == y1) {
+               if (x1 > x0)
+               {
+                       ili9341_drawhline(x0, y0, x1 - x0 + 1, color);
+               }
+               else if (x1 < x0)
+               {
+                       ili9341_drawhline(x1, y0, x0 - x1 + 1, color);
+               }
+               else {
+                       ili9341_setaddress(x0, y0, x0, y0);
+                       ili9341_pushcolor(color);
+               }
+               return;
+       }
+       else if (x0 == x1)
+       {
+               if (y1 > y0)
+               {
+                       ili9341_drawvline(x0, y0, y1 - y0 + 1, color);
+               }
+               else
+               {
+                       ili9341_drawvline(x0, y1, y0 - y1 + 1, color);
+               }
+               return;
+       }
+
+       uint8_t steep = abs(y1 - y0) > abs(x1 - x0);
+       if (steep)
+       {
+               swap(x0, y0);
+               swap(x1, y1);
+       }
+       if (x0 > x1)
+       {
+               swap(x0, x1);
+               swap(y0, y1);
+       }
+
+       int16_t dx, dy;
+       dx = x1 - x0;
+       dy = abs(y1 - y0);
+
+       int16_t err = dx / 2;
+       int16_t ystep;
+
+       if (y0 < y1) {
+               ystep = 1;
+       } else {
+               ystep = -1;
+       }
+
+       int16_t xbegin = x0;
+       if (steep)
+       {
+               for (; x0<=x1; x0++)
+               {
+                       err -= dy;
+                       if (err < 0)
+                       {
+                               int16_t len = x0 - xbegin;
+                               if (len)
+                               {
+                                       ili9341_drawvline(y0, xbegin, len + 1, color);
+                               }
+                               else
+                               {
+                                       ili9341_setaddress(y0, x0, y0, x0);
+                                       ili9341_pushcolor(color);
+                               }
+                               xbegin = x0 + 1;
+                               y0 += ystep;
+                               err += dx;
+                       }
+               }
+               if (x0 > xbegin + 1)
+               {
+                       ili9341_drawvline(y0, xbegin, x0 - xbegin, color);
+               }
+       }
+       else
+       {
+               for (; x0<=x1; x0++)
+               {
+                       err -= dy;
+                       if (err < 0)
+                       {
+                               int16_t len = x0 - xbegin;
+                               if (len)
+                               {
+                                       ili9341_drawhline(xbegin, y0, len + 1, color);
+                               }
+                               else
+                               {
+                                       ili9341_setaddress(x0, y0, x0, y0);
+                                       ili9341_pushcolor(color);
+                       }
+                               xbegin = x0 + 1;
+                               y0 += ystep;
+                               err += dx;
+                       }
+               }
+               if (x0 > xbegin + 1)
+               {
+                       ili9341_drawhline(xbegin, y0, x0 - xbegin, color);
+               }
+       }
+}
+
+void ili9341_drawcirclehelper(int16_t x0, int16_t y0, int16_t r,uint8_t cornername, uint16_t color)
+{
+       int16_t f = 1 - r;
+       int16_t ddF_x = 1;
+       int16_t ddF_y = -2 * r;
+       int16_t x = 0;
+       int16_t y = r;
+
+       while (x < y)
+       {
+               if (f >= 0)
+               {
+                       y--;
+                       ddF_y += 2;
+                       f += ddF_y;
+               }
+               x++;
+               ddF_x += 2;
+               f += ddF_x;
+               if (cornername & 0x4)
+               {
+                       ili9341_drawpixel(x0 + x, y0 + y, color);
+                       ili9341_drawpixel(x0 + y, y0 + x, color);
+               }
+               if (cornername & 0x2)
+               {
+                       ili9341_drawpixel(x0 + x, y0 - y, color);
+                       ili9341_drawpixel(x0 + y, y0 - x, color);
+               }
+               if (cornername & 0x8)
+               {
+                       ili9341_drawpixel(x0 - y, y0 + x, color);
+                       ili9341_drawpixel(x0 - x, y0 + y, color);
+               }
+               if (cornername & 0x1)
+               {
+                       ili9341_drawpixel(x0 - y, y0 - x, color);
+                       ili9341_drawpixel(x0 - x, y0 - y, color);
+               }
+       }
+}
+
+void ili9341_fillcirclehelper(int16_t x0, int16_t y0, int16_t r,uint8_t cornername, int16_t delta,uint16_t color)
+{
+       int16_t f = 1 - r;
+       int16_t ddF_x = 1;
+       int16_t ddF_y = -2 * r;
+       int16_t x = 0;
+       int16_t y = r;
+
+       while (x < y)
+       {
+               if (f >= 0)
+               {
+                       y--;
+                       ddF_y += 2;
+                       f += ddF_y;
+               }
+               x++;
+               ddF_x += 2;
+               f += ddF_x;
+
+               if (cornername & 0x1)
+               {
+                       ili9341_drawvline(x0 + x, y0 - y, 2 * y + 1 + delta, color);
+                       ili9341_drawvline(x0 + y, y0 - x, 2 * x + 1 + delta, color);
+               }
+               if (cornername & 0x2)
+               {
+                       ili9341_drawvline(x0 - x, y0 - y, 2 * y + 1 + delta, color);
+                       ili9341_drawvline(x0 - y, y0 - x, 2 * x + 1 + delta, color);
+               }
+       }
+}
+
+void ili9341_drawrect(uint16_t x, uint16_t y, uint16_t w, uint16_t h,uint16_t color)
+{
+    ili9341_drawhline(x,y,w,color);
+    ili9341_drawhline(x,y+h-1,w,color);
+    ili9341_drawvline(x,y,h,color);
+    ili9341_drawvline(x+w-1,y,h,color);
+    /*
+    HLine(x, y, w, color);
+    HLine(x, y + h - 1, w, color);
+    VLine(x, y, h, color);
+    VLine(x + w - 1, y, h, color);
+    writecommand_last(ILI9341_NOP);
+    endSPITransaction();
+       */
+}
+
+void ili9341_fillrect(uint16_t x,uint16_t y,uint16_t w,uint16_t h,uint16_t color)
+{
+    if((x >=TFT_WIDTH) || (y >=TFT_HEIGHT))
+    {
+       return;
+       }
+    if((x+w-1)>=TFT_WIDTH)
+    {
+        w=TFT_WIDTH-x;
+    }
+       if((y+h-1)>=TFT_HEIGHT)
+       {
+               h=TFT_HEIGHT-y;
+       }
+
+    ili9341_setaddress(x, y, x+w-1, y+h-1);
+
+    for(y=h; y>0; y--)
+    {
+        for(x=w; x>0; x--)
+        {
+            ili9341_pushcolor(color);
+        }
+    }
+}
+
+void ili9341_drawroundrect(int16_t x, int16_t y, int16_t w, int16_t h,int16_t r, uint16_t color)
+{
+  // smarter version
+       ili9341_drawhline(x + r, y, w - 2 * r, color);         // Top
+       ili9341_drawhline(x + r, y + h - 1, w - 2 * r, color); // Bottom
+       ili9341_drawvline(x, y + r, h - 2 * r, color);         // Left
+       ili9341_drawvline(x + w - 1, y + r, h - 2 * r, color); // Right
+  // draw four corners
+       ili9341_drawcirclehelper(x + r, y + r, r, 1, color);
+       ili9341_drawcirclehelper(x + w - r - 1, y + r, r, 2, color);
+       ili9341_drawcirclehelper(x + w - r - 1, y + h - r - 1, r, 4, color);
+       ili9341_drawcirclehelper(x + r, y + h - r - 1, r, 8, color);
+}
+
+// Fill a rounded rectangle
+void ili9341_fillroundrect(int16_t x, int16_t y, int16_t w, int16_t h,int16_t r, uint16_t color)
+{
+       // smarter version
+       ili9341_fillrect(x + r, y, w - 2 * r, h, color);
+
+       // draw four corners
+       ili9341_fillcirclehelper(x + w - r - 1, y + r, r, 1, h - 2 * r - 1, color);
+       ili9341_fillcirclehelper(x + r, y + r, r, 2, h - 2 * r - 1, color);
+}
+
+void ili9341_drawhollowcircle(uint16_t X, uint16_t Y, uint16_t radius, uint16_t color)
+{
+       int16_t x = radius-1;
+       int16_t y = 0;
+       int16_t dx = 1;
+       int16_t dy = 1;
+       int16_t err = dx - (radius << 1);
+
+       while (x >= y)
+       {
+               ili9341_drawpixel(X + x, Y + y, color);
+               ili9341_drawpixel(X + y, Y + x, color);
+               ili9341_drawpixel(X - y, Y + x, color);
+               ili9341_drawpixel(X - x, Y + y, color);
+               ili9341_drawpixel(X - x, Y - y, color);
+               ili9341_drawpixel(X - y, Y - x, color);
+               ili9341_drawpixel(X + y, Y - x, color);
+               ili9341_drawpixel(X + x, Y - y, color);
+
+               if (err <= 0)
+               {
+                       y++;
+                       err += dy;
+                       dy += 2;
+               }
+
+               if (err > 0)
+               {
+                       x--;
+                       dx += 2;
+                       err += (-radius << 1) + dx;
+               }
+       }
+}
+
+
+void ili9341_drawfilledcircle(uint16_t X, uint16_t Y, uint16_t radius, uint16_t color)
+{
+
+       int16_t x = radius;
+       int16_t y = 0;
+       int16_t xChange = 1 - (radius << 1);
+       int16_t yChange = 0;
+       int16_t radiusError = 0;
+
+       while (x >= y)
+       {
+               for (uint16_t i = X - x; i <= X + x; i++)
+               {
+                       ili9341_drawpixel(i, Y + y,color);
+                       ili9341_drawpixel(i, Y - y,color);
+               }
+
+               for (int i = X - y; i <= X + y; i++)
+               {
+                       ili9341_drawpixel(i, Y + x,color);
+                       ili9341_drawpixel(i, Y - x,color);
+               }
+
+               y++;
+               radiusError += yChange;
+               yChange += 2;
+
+               if (((radiusError << 1) + xChange) > 0)
+               {
+                       x--;
+                       radiusError += xChange;
+                       xChange += 2;
+               }
+       }
+}
+
+void ili9341_drawtriangle(int16_t x0, int16_t y0, int16_t x1, int16_t y1, int16_t x2, int16_t y2, uint16_t color)
+{
+       ili9341_drawline(x0, y0, x1, y1, color);
+       ili9341_drawline(x1, y1, x2, y2, color);
+       ili9341_drawline(x2, y2, x0, y0, color);
+}
+
+void ili9341_filltriangle(int16_t x0, int16_t y0,int16_t x1, int16_t y1,int16_t x2, int16_t y2, uint16_t color)
+{
+       int16_t a, b, y, last;
+
+       // Sort coordinates by Y order (y2 >= y1 >= y0)
+       if (y0 > y1) {
+               swap(y0, y1); swap(x0, x1);
+       }
+       if (y1 > y2) {
+               swap(y2, y1); swap(x2, x1);
+       }
+       if (y0 > y1) {
+               swap(y0, y1); swap(x0, x1);
+       }
+
+       if(y0 == y2) { // Handle awkward all-on-same-line case as its own thing
+               a = b = x0;
+               if(x1 < a)      a = x1;
+               else if(x1 > b) b = x1;
+               if(x2 < a)      a = x2;
+               else if(x2 > b) b = x2;
+               ili9341_drawhline(a, y0, b-a+1, color);
+               return;
+       }
+
+       int32_t
+       dx01 = x1 - x0,
+               dy01 = y1 - y0,
+               dx02 = x2 - x0,
+               dy02 = y2 - y0,
+               dx12 = x2 - x1,
+               dy12 = y2 - y1,
+               sa   = 0,
+               sb   = 0;
+
+       // For upper part of triangle, find scanline crossings for segments
+       // 0-1 and 0-2.  If y1=y2 (flat-bottomed triangle), the scanline y1
+       // is included here (and second loop will be skipped, avoiding a /0
+       // error there), otherwise scanline y1 is skipped here and handled
+       // in the second loop...which also avoids a /0 error here if y0=y1
+       // (flat-topped triangle).
+       if(y1 == y2) last = y1;   // Include y1 scanline
+       else         last = y1-1; // Skip it
+
+       for(y=y0; y<=last; y++)
+       {
+               a   = x0 + sa / dy01;
+               b   = x0 + sb / dy02;
+               sa += dx01;
+               sb += dx02;
+               /* longhand:
+       a = x0 + (x1 - x0) * (y - y0) / (y1 - y0);
+       b = x0 + (x2 - x0) * (y - y0) / (y2 - y0);
+                */
+               if(a > b) swap(a,b);
+               ili9341_drawhline(a, y, b-a+1, color);
+       }
+
+       // For lower part of triangle, find scanline crossings for segments
+       // 0-2 and 1-2.  This loop is skipped if y1=y2.
+       sa = dx12 * (y - y1);
+       sb = dx02 * (y - y0);
+       for(; y<=y2; y++)
+       {
+               a   = x1 + sa / dy12;
+               b   = x0 + sb / dy02;
+               sa += dx12;
+               sb += dx02;
+               /* longhand:
+       a = x1 + (x2 - x1) * (y - y1) / (y2 - y1);
+       b = x0 + (x2 - x0) * (y - y0) / (y2 - y0);
+                */
+               if(a > b) swap(a,b);
+               ili9341_drawhline(a, y, b-a+1, color);
+       }
+}
+
+void ili9341_fillrecthgradient(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color1, uint16_t color2)
+{
+       x += _originx;
+       y += _originy;
+
+       // Rectangular clipping
+       if ((x >= _displayclipx2) || (y >= _displayclipy2))
+    {
+               return;
+    }
+       if (x < _displayclipx1)
+       {
+               w -= (_displayclipx1 - x);
+               x = _displayclipx1;
+       }
+       if (y < _displayclipy1)
+       {
+               h -= (_displayclipy1 - y);
+               y = _displayclipy1;
+       }
+       if ((x + w - 1) >= _displayclipx2)
+       {
+               w = _displayclipx2 - x;
+       }
+       if ((y + h - 1) >= _displayclipy2)
+    {
+               h = _displayclipy2 - y;
+    }
+
+       int16_t r1, g1, b1, r2, g2, b2, dr, dg, db, r, g, b;
+       uint16_t color;
+       color565toRGB14(color1, &r1, &g1, &b1);
+       color565toRGB14(color2, &r2, &g2, &b2);
+       dr = (r2 - r1) / w;
+       dg = (g2 - g1) / w;
+       db = (b2 - b1) / w;
+       r = r1;
+       g = g1;
+       b = b1;
+       ili9341_setaddress(x, y, x + w - 1, y + h - 1);
+       for (y = h; y > 0; y--)
+       {
+               for (x = w; x > 1; x--)
+               {
+                       color = RGB14tocolor565(r, g, b);
+                       ili9341_pushcolor(color);
+                       r += dr;
+                       g += dg;
+                       b += db;
+               }
+               color = RGB14tocolor565(r, g, b);
+               ili9341_pushcolor(color);
+               r = r1;
+               g = g1;
+               b = b1;
+    }
+}
+
+
+
+void ili9341_fillrectvgradient(int16_t x, int16_t y, int16_t w, int16_t h,uint16_t color1, uint16_t color2)
+{
+       x += _originx;
+       y += _originy;
+
+       // Rectangular clipping
+       if ((x >= _displayclipx2) || (y >= _displayclipy2))
+    {
+               return;
+    }
+       if (x < _displayclipx1)
+       {
+               w -= (_displayclipx1 - x);
+               x = _displayclipx1;
+       }
+       if (y < _displayclipy1)
+       {
+               h -= (_displayclipy1 - y);
+               y = _displayclipy1;
+       }
+       if ((x + w - 1) >= _displayclipx2)
+    {
+               w = _displayclipx2 - x;
+    }
+       if ((y + h - 1) >= _displayclipy2)
+    {
+               h = _displayclipy2 - y;
+    }
+
+       int16_t r1, g1, b1, r2, g2, b2, dr, dg, db, r, g, b;
+       color565toRGB14(color1, &r1, &g1, &b1);
+       color565toRGB14(color2, &r2, &g2, &b2);
+       dr = (r2 - r1) / h;
+       dg = (g2 - g1) / h;
+       db = (b2 - b1) / h;
+       r = r1;
+       g = g1;
+       b = b1;
+
+       ili9341_setaddress(x, y, x + w - 1, y + h - 1);
+       for (y = h; y > 0; y--)
+       {
+               uint16_t color = RGB14tocolor565(r, g, b);
+
+               for (x = w; x > 1; x--)
+               {
+                       ili9341_pushcolor(color);
+               }
+               ili9341_pushcolor(color);
+               r += dr;
+               g += dg;
+               b += db;
+       }
+}
+
+
+void ili9341_setrotation(uint8_t m)
+{
+       uint8_t rotation;
+    ili9341_writecommand8(0x36);
+    rotation=m%4;
+    switch (rotation)
+    {
+        case 0:
+            ili9341_writedata8(0x40|0x08);
+            TFT_WIDTH = 240;
+            TFT_HEIGHT = 320;
+            break;
+        case 1:
+            ili9341_writedata8(0x20|0x08);
+            TFT_WIDTH  = 320;
+            TFT_HEIGHT = 240;
+            break;
+        case 2:
+            ili9341_writedata8(0x80|0x08);
+            TFT_WIDTH  = 240;
+            TFT_HEIGHT = 320;
+            break;
+        case 3:
+            ili9341_writedata8(0x40|0x80|0x20|0x08);
+            TFT_WIDTH  = 320;
+            TFT_HEIGHT = 240;
+            break;
+    }
+    ili9341_updatedisplayclip();
+    ili9341_setorigin();
+    ili9341_setcliprect();
+}
+
diff --git a/src/ili9341gfx.c b/src/ili9341gfx.c

new file mode 100644 (file)

index 0000000..3230580
--- /dev/null
+++ b/src/ili9341gfx.c
@@ -0,0 +1,676 @@
+#ifndef __ILI9341_H
+#include "ili9341.h"
+#endif
+
+#ifndef __ILI9341_GFX_H
+#include "ili9341gfx.h"
+#endif
+
+#include "glcdfont.h"
+#include "font_typedef.h"
+
+extern volatile uint16_t TFT_WIDTH;
+extern volatile uint16_t TFT_HEIGHT;
+
+volatile int16_t cursor_x;
+volatile uint16_t cursor_y;
+volatile uint16_t textcolor;
+volatile uint16_t textbgcolor;
+volatile uint8_t textsize;
+uint16_t vsetx,vsety,vactualx,vactualy,isetx,isety,iactualx,iactualy;
+uint8_t wrap=0;
+ILI9341_t3_font_t font;
+
+void backuplocationvset(void)//backing up vset data start location to print next vset data in exact location
+{
+       vsetx=cursor_x;
+       vsety=cursor_y;
+}
+
+
+void backuplocationvactual(void)//backing up vactual data start location to print next vactual data in exact location
+{
+       vactualx=cursor_x;
+       vactualy=cursor_y;
+}
+
+void backuplocationiset(void)//backing up iset data start location to print next iset data in exact location
+{
+       isetx=cursor_x;
+       isety=cursor_y;
+}
+
+
+void backuplocationiactual(void)//backing up iactual data start location to print next iactual data in exact location
+{
+       iactualx=cursor_x;
+       iactualy=cursor_y;
+}
+
+static inline uint32_t fetchbit(const uint8_t *p, uint32_t index)
+{
+       return (p[index >> 3] & (0x80 >> (index & 7)));
+}
+
+static uint32_t fetchbits_unsigned(const uint8_t *p, uint32_t index, uint32_t required)
+{
+       uint32_t val;
+       uint8_t *s = (uint8_t *)&p[index>>3];
+
+#ifdef UNALIGNED_IS_SAFE
+       val = *(uint32_t *)s; // read 4 bytes - unaligned is ok
+       val = __builtin_bswap32(val); // change to big-endian order
+#else
+       val = s[0] << 24;
+       val |= (s[1] << 16);
+       val |= (s[2] << 8);
+       val |= s[3];
+#endif
+       val <<= (index & 7); // shift out used bits
+       if (32 - (index & 7) < required) { // need to get more bits
+               val |= (s[4] >> (8 - (index & 7)));
+       }
+       val >>= (32-required); // right align the bits
+       return val;
+}
+
+static uint32_t fetchbits_signed(const uint8_t *p, uint32_t index, uint32_t required)
+{
+        uint32_t val = fetchbits_unsigned(p, index, required);
+        if (val & (1 << (required - 1))) {
+                return (int32_t)val - (1 << required);
+        }
+        return (int32_t)val;
+}
+
+void ili9341_setfont(const ILI9341_t3_font_t f)
+{
+       font = f;
+}
+
+
+void ili9341_setcursor(uint16_t x,uint16_t y)//set cursor at desired location to print data
+{
+       cursor_x=x;
+       cursor_y=y;
+}
+
+void ili9341_settextcolor(uint16_t x,uint16_t y)//set text colour and text background colour
+{
+       textcolor=x;
+       textbgcolor=y;
+}
+
+void ili9341_settextsize(uint8_t s)
+{
+       if(s>8) return;
+       textsize=(s>0) ? s: 1;//this operation means if s0 greater than 0,then s=s,else s=1
+}
+
+
+void ili9341_drawcharbits(int16_t x, int16_t y, char c,uint16_t fgcolor, uint16_t bgcolor, uint8_t size_x,uint8_t size_y)
+{
+       if ((x >= TFT_WIDTH) || (y >= TFT_HEIGHT) || ((x + 6 * size_x - 1) < 0) || ((y + 8 * size_y - 1) < 0))
+       {
+               return;
+       }
+
+       if (fgcolor == bgcolor)
+       {
+               // This transparent approach is only about 20% faster
+               if ((size_x == 1) && (size_y == 1))
+               {
+                       uint8_t mask = 0x01;
+                       int16_t xoff, yoff;
+                       for (yoff = 0; yoff < 8; yoff++)
+                       {
+                               uint8_t line = 0;
+                               for (xoff = 0; xoff < 5; xoff++)
+                               {
+                                       if (glcdfont[c * 5 + xoff] & mask)
+                                       {
+                                               line |= 1;
+                                       }
+                                       line <<= 1;
+                               }
+                               line >>= 1;
+                               xoff = 0;
+                               while (line)
+                               {
+                                       if (line == 0x1F)
+                                       {
+                                               ili9341_drawhline(x + xoff, y + yoff, 5, fgcolor);
+                                               break;
+                                       }
+                                       else if (line == 0x1E)
+                                       {
+                                               ili9341_drawhline(x + xoff, y + yoff, 4, fgcolor);
+                                               break;
+                                       }
+                                       else if ((line & 0x1C) == 0x1C)
+                                       {
+                                               ili9341_drawhline(x + xoff, y + yoff, 3, fgcolor);
+                                               line <<= 4;
+                                               xoff += 4;
+                                       }
+                                       else if ((line & 0x18) == 0x18)
+                                       {
+                                               ili9341_drawhline(x + xoff, y + yoff, 2, fgcolor);
+                                               line <<= 3;
+                                               xoff += 3;
+                                       }
+                                       else if ((line & 0x10) == 0x10)
+                                       {
+                                               ili9341_drawpixel(x + xoff, y + yoff, fgcolor);
+                                               line <<= 2;
+                                               xoff += 2;
+                                       }
+                                       else
+                                       {
+                                               line <<= 1;
+                                               xoff += 1;
+                                       }
+                               }
+                               mask = mask << 1;
+                       }
+               }
+               else
+               {
+                       uint8_t mask = 0x01;
+                       int16_t xoff, yoff;
+                       for (yoff = 0; yoff < 8; yoff++)
+                       {
+                               uint8_t line = 0;
+                               for (xoff = 0; xoff < 5; xoff++)
+                               {
+                                       if (glcdfont[c * 5 + xoff] & mask)
+                                       {
+                                               line |= 1;
+                                       }
+                                       line <<= 1;
+                               }
+                               line >>= 1;
+                               xoff = 0;
+                               while (line)
+                               {
+                                       if (line == 0x1f)
+                                       {
+                                               ili9341_fillrect(x + xoff * size_x, y + yoff * size_y, 5 * size_x, size_y,fgcolor);
+                                               break;
+                                       }
+                                       else if (line == 0x1e)
+                                       {
+                                               ili9341_fillrect(x + xoff * size_x, y + yoff * size_y, 4 * size_x, size_y,fgcolor);
+                                               break;
+                                       }
+                                       else if ((line & 0x1c) == 0x1c)
+                                       {
+                                               ili9341_fillrect(x + xoff * size_x, y + yoff * size_y, 3 * size_x, size_y,fgcolor);
+                                               line <<= 4;
+                                               xoff += 4;
+                                       }
+                                       else if ((line & 0x18) == 0x18)
+                                       {
+                                               ili9341_fillrect(x + xoff * size_x, y + yoff * size_y, 2 * size_x, size_y,fgcolor);
+                                               line <<= 3;
+                                               xoff += 3;
+                                       }
+                                       else if ((line & 0x10) == 0x10)
+                                       {
+                                               ili9341_fillrect(x + xoff * size_x, y + yoff * size_y, size_x, size_y,fgcolor);
+                                               line <<= 2;
+                                               xoff += 2;
+                                       }
+                                       else
+                                       {
+                                               line <<= 1;
+                                               xoff += 1;
+                                       }
+                               }
+                               mask = mask << 1;
+                       }
+               }
+       }
+       else
+       {
+     // This solid background approach is about 5 time faster
+               uint8_t xc, yc;
+               uint8_t xr, yr;
+               uint8_t mask = 0x01;
+               uint16_t color;
+
+               // We need to offset by the origin.
+               x += _originx;
+               y += _originy;
+               int16_t x_char_start = x; // remember our X where we start outputting...
+
+               if ((x >= _displayclipx2) || (y >= _displayclipy2) || ((x + 6 * size_x - 1) < _displayclipx1) || ((y + 8 * size_y - 1) <_displayclipy1))
+               {
+                       return;
+               }
+               // need to build actual pixel rectangle we will output into.
+       int16_t y_char_top = y; // remember the y
+       int16_t w = 6 * size_x;
+       int16_t h = 8 * size_y;
+
+       if (x < _displayclipx1)
+       {
+          w -= (_displayclipx1 - x);
+          x = _displayclipx1;
+       }
+       if ((x + w - 1) >= _displayclipx2)
+       {
+           w = _displayclipx2 - x;
+       }
+       if (y < _displayclipy1)
+       {
+          h -= (_displayclipy1 - y);
+          y = _displayclipy1;
+       }
+       if ((y + h - 1) >= _displayclipy2)
+       {
+          h = _displayclipy2 - y;
+       }
+       ili9341_setaddress(x, y, x + w - 1, y + h - 1);
+       y = y_char_top; // restore the actual y.
+       for (yc = 0; (yc < 8) && (y < _displayclipy2); yc++)
+       {
+          for (yr = 0; (yr < size_y) && (y < _displayclipy2); yr++)
+          {
+                  x = x_char_start; // get our first x position...
+                  if (y >= _displayclipy1)
+                  {
+                          for (xc = 0; xc < 5; xc++)
+                          {
+                                  if (glcdfont[c * 5 + xc] & mask)
+                                  {
+                                          color = fgcolor;
+                                  }
+                                  else
+                                  {
+                                          color = bgcolor;
+                                  }
+                                  for (xr = 0; xr < size_x; xr++)
+                                  {
+                                          if ((x >= _displayclipx1) && (x < _displayclipx2))
+                                          {
+                                                  ili9341_pushcolor(color);
+                                          }
+                                          x++;
+                                  }
+                          }
+                          for (xr = 0; xr < size_x; xr++)
+                          {
+                                  if ((x >= _displayclipx1) && (x < _displayclipx2))
+                                  {
+                                          ili9341_pushcolor(bgcolor);
+                                  }
+                                  x++;
+                          }
+                  }
+                  y++;
+          }
+          mask = mask << 1;
+       }
+       }
+}
+
+
+
+
+void ili9341_drawfontbits(uint8_t opaque, uint32_t bits, uint32_t numbits, int32_t x, int32_t y, uint32_t repeat) {
+       if (bits == 0) {
+               if (opaque) {
+                       ili9341_fillrect(x, y, numbits, repeat, textbgcolor);
+               }
+       }
+       else
+       {
+               int32_t x1 = x;
+               uint32_t n = numbits;
+               int16_t w;
+               int16_t bgw;
+
+               w = 0;
+               bgw = 0;
+
+               do {
+                       n--;
+                       if (bits & (1 << n)) {
+                               if (bgw > 0) {
+                                       if (opaque) {
+                                               ili9341_fillrect(x1 - bgw, y, bgw, repeat, textbgcolor);
+                                       }
+                                       bgw = 0;
+                               }
+                               w++;
+                       }
+                       else
+                       {
+                               if (w > 0) {
+                                       ili9341_fillrect(x1 - w, y, w, repeat, textcolor);
+                                       w = 0;
+                               }
+                               bgw++;
+                       }
+                       x1++;
+               }
+               while (n > 0);
+
+               if (w > 0)
+               {
+                       ili9341_fillrect(x1 - w, y, w, repeat, textcolor);
+               }
+
+               if (bgw > 0)
+               {
+                       if (opaque)
+                       {
+                               ili9341_fillrect(x1 - bgw, y, bgw, repeat, textbgcolor);
+                       }
+               }
+       }
+}
+
+void ili9341_drawfontchar(unsigned char c) {
+       uint32_t bitoffset;
+       const uint8_t *data;
+
+       if (c >= font.index1_first && c <= font.index1_last) {
+               bitoffset = c - font.index1_first;
+               bitoffset *= font.bits_index;
+       }
+       else if (c >= font.index2_first && c <= font.index2_last)
+       {
+               bitoffset =
+        c - font.index2_first + font.index1_last - font.index1_first + 1;
+               bitoffset *= font.bits_index;
+       }
+       else if (font.unicode)
+       {
+               return; // TODO: implement sparse unicode
+       }
+       else
+       {
+               return;
+       }
+       data = font.data + fetchbits_unsigned(font.index, bitoffset, font.bits_index);
+
+       uint32_t encoding = fetchbits_unsigned(data, 0, 3);
+       if (encoding != 0)
+       {
+               return;
+       }
+       uint32_t width = fetchbits_unsigned(data, 3, font.bits_width);
+       bitoffset = font.bits_width + 3;
+       uint32_t height = fetchbits_unsigned(data, bitoffset, font.bits_height);
+       bitoffset += font.bits_height;
+       int32_t xoffset = fetchbits_signed(data, bitoffset, font.bits_xoffset);
+       bitoffset += font.bits_xoffset;
+       int32_t yoffset = fetchbits_signed(data, bitoffset, font.bits_yoffset);
+       bitoffset += font.bits_yoffset;
+    uint32_t delta = fetchbits_unsigned(data, bitoffset, font.bits_delta);
+    bitoffset += font.bits_delta;
+    if (cursor_x < 0)
+    {
+       cursor_x = 0;
+    }
+    int32_t origin_x = cursor_x + xoffset;
+    if (origin_x < 0) {
+       cursor_x -= xoffset;
+       origin_x = 0;
+    }
+    if (origin_x + (int)width >TFT_WIDTH) {
+       if (!wrap)
+               return;
+       origin_x = 0;
+       if (xoffset >= 0) {
+               cursor_x = 0;
+       }
+       else
+       {
+               cursor_x = -xoffset;
+       }
+       cursor_y += font.line_space;
+    }
+    if (cursor_y >= TFT_HEIGHT)
+    {
+       return;
+    }
+    // vertically, the top and/or bottom can be clipped
+    int32_t origin_y = cursor_y + font.cap_height - height - yoffset;
+
+    // TODO: compute top skip and number of lines
+    int32_t linecount = height;
+    // uint32_t loopcount = 0;
+    int32_t y = origin_y;
+    uint8_t opaque;
+    textbgcolor != textcolor ? opaque=1 : (opaque=0);
+
+    // Going to try a fast Opaque method which works similar to drawChar, which is
+    // near the speed of writerect
+    if (!opaque) {
+       while (linecount > 0)
+       {
+               uint32_t n = 1;
+               if (fetchbit(data, bitoffset++) != 0)
+               {
+                       n = fetchbits_unsigned(data, bitoffset, 3) + 2;
+                       bitoffset += 3;
+               }
+               uint32_t x = 0;
+               do
+               {
+                       int32_t xsize = width - x;
+                       if (xsize > 32)
+                       {
+                               xsize = 32;
+                       }
+
+                       uint32_t bits = fetchbits_unsigned(data, bitoffset, xsize);
+                       ili9341_drawfontbits(opaque, bits, xsize, origin_x + x, y, n);
+                       bitoffset += xsize;
+                       x       += xsize;
+               }
+               while (x < width);
+
+               y += n;
+               linecount -= n;
+       }
+       } // 1bpp
+    // opaque
+    else
+    {
+    // Now opaque mode...
+    // Now write out background color for the number of rows above the above the
+    // character
+    // figure out bounding rectangle...
+    // In this mode we need to update to use the offset and bounding rectangles
+    // as we are doing it it direct.
+    // also update the Origin
+       uint16_t cursor_x_origin = cursor_x + _originx;
+       uint16_t cursor_y_origin = cursor_y + _originy;
+       origin_x += _originx;
+       origin_y += _originy;
+
+       int16_t start_x = (origin_x < cursor_x_origin) ? origin_x : cursor_x_origin;
+       if (start_x < 0)
+       {
+               start_x = 0;
+       }
+       int16_t start_y = (origin_y < cursor_y_origin) ? origin_y : cursor_y_origin;
+       if (start_y < 0)
+       {
+               start_y = 0;
+       }
+       uint16_t end_x = cursor_x_origin + delta;
+       if ((origin_x + (int)width) > end_x)
+       {
+               end_x = origin_x + (int)width;
+       }
+       if (end_x >= _displayclipx2)
+       {
+               end_x = _displayclipx2;
+       }
+       uint16_t end_y = cursor_y_origin + font.line_space;
+       if ((origin_y + (int)height) > end_y)
+       {
+               end_y = origin_y + (int)height;
+       }
+       if (end_y >= _displayclipy2)
+       {
+               end_y = _displayclipy2;
+       }
+       end_x--; // setup to last one we draw
+       end_y--;
+       uint16_t start_x_min = (start_x >= _displayclipx1) ? start_x : _displayclipx1;
+       uint16_t start_y_min = (start_y >= _displayclipy1) ? start_y : _displayclipy1;
+
+       // See if anything is in the display area.
+
+       if ((end_x < _displayclipx1) || (start_x >= _displayclipx2) || (end_y < _displayclipy1) || (start_y >= _displayclipy2))
+       {
+               cursor_x += delta; // could use goto or another indent level...
+               return;
+       }
+
+       //setAddr(start_x, start_y_min, end_x, end_y);
+       //writecommand_cont(ILI9341_RAMWR);
+       ili9341_setaddress(start_x, start_y, end_x, end_y);
+       uint16_t screen_y = start_y_min;
+       uint16_t screen_x;
+
+       // Clear above character
+       while (screen_y < origin_y)
+       {
+               for (screen_x = start_x_min; screen_x <= end_x; screen_x++) {
+                       ili9341_pushcolor(textbgcolor);
+               }
+               screen_y++;
+       }
+
+
+       // Now lets process each of the data lines.
+       screen_y = origin_y;
+       while (linecount > 0)
+       {
+               uint32_t b = fetchbit(data, bitoffset++);
+               uint32_t n;
+               if (b == 0)
+               {
+                       n = 1;
+               }
+               else
+               {
+                       n = fetchbits_unsigned(data, bitoffset, 3) + 2;
+                       bitoffset += 3;
+               }
+               uint32_t bitoffset_row_start = bitoffset;
+               while (n--)
+               {
+                       // do some clipping here.
+                       bitoffset = bitoffset_row_start; // we will work through these bits
+                       // maybe multiple times
+                       // We need to handle case where some of the bits may not be visible,
+                       // but we still need to
+                       // read through them
+                       // _displayclipx1, _displayclipx2);
+                       if ((screen_y >= _displayclipy1) && (screen_y < _displayclipy2))
+                       {
+                               for (screen_x = start_x; screen_x < origin_x; screen_x++)
+                               {
+                                       if ((screen_x >= _displayclipx1) && (screen_x < _displayclipx2))
+                                       {
+                                               ili9341_pushcolor(textbgcolor);
+                                       }
+                               }
+                       }
+                       uint32_t x = 0;
+                       screen_x = origin_x;
+                       do
+                       {
+                               uint32_t xsize = width - x;
+                               if (xsize > 32)
+                               {
+                                       xsize = 32;
+                               }
+                               uint32_t bits = fetchbits_unsigned(data, bitoffset, xsize);
+                               uint32_t bit_mask = 1 << (xsize - 1);
+                               if ((screen_y >= _displayclipy1) && (screen_y < _displayclipy2))
+                               {
+                                       while (bit_mask)
+                                       {
+                                               if ((screen_x >= _displayclipx1) && (screen_x < _displayclipx2))
+                                               {
+                                                       ili9341_pushcolor((bits & bit_mask) ? textcolor : textbgcolor);
+                                               }
+                                               bit_mask = bit_mask >> 1;
+                                               screen_x++; // Current actual screen X
+                                       }
+                                       bitoffset += xsize;
+                               }
+                               x += xsize;
+                       }
+                       while (x < width);
+                       if ((screen_y >= _displayclipy1) && (screen_y < _displayclipy2))
+                       {
+                               // output bg color and right hand side
+                               while (screen_x++ <= end_x)
+                               {
+                                       ili9341_pushcolor(textbgcolor);
+                               }
+                       }
+                       screen_y++;
+                       linecount--;
+               }
+       }
+
+       screen_x = (end_y + 1 - screen_y) * (end_x + 1 - start_x_min); // How many bytes we need to still output
+       while(screen_x-- >1)
+       {
+               ili9341_pushcolor(textbgcolor);
+       }
+       ili9341_pushcolor(textbgcolor);
+    }
+    // 1bpp
+    // Increment to setup for the next character.
+    cursor_x += delta;
+}
+
+void ili9341_drawchar(char c)
+{
+       if (c == '\n')
+       {
+               cursor_y += textsize*8;
+               cursor_x  = 0;
+       }
+       else if (c == '\r')
+       {
+       }
+       else {
+               ili9341_drawcharbits(cursor_x, cursor_y, c, textcolor, textbgcolor, textsize, textsize);
+               cursor_x += textsize*6;
+               if (wrap && (cursor_x > (TFT_WIDTH - textsize*6)))
+               {
+                       cursor_y += textsize*8;
+                       cursor_x = 0;
+        }
+       }
+}
+
+
+void ili9341_out(char *strn) {
+    register char c;
+    while((c= *strn++)) {
+       if(font.index!=0)
+       {
+               ili9341_drawfontchar(c);
+       }
+       else
+       {
+               ili9341_drawchar(c);
+       }
+    }
+}
+
+
diff --git a/src/main.c b/src/main.c

new file mode 100644 (file)

index 0000000..b444db9
--- /dev/null
+++ b/src/main.c
@@ -0,0 +1,1967 @@
+/*
+ * This file is part of the ??OS++ distribution.
+ *   (https://github.com/micro-os-plus)
+ * Copyright (c) 2014 Liviu Ionescu.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+// ----------------------------------------------------------------------------
+
+#pragma GCC diagnostic ignored "-Wunknown-pragmas"
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <math.h>
+#include <stm32f0xx.h>
+#include <stm32f0xx_conf.h>
+#include <stm32f0xx_rcc.h>
+#include <stm32f0xx_gpio.h>
+#include <stm32f0xx_flash.h>
+#include <stm32f0xx_tim.h>
+#include <stm32f0xx_exti.h>
+#include <stm32f0xx_i2c.h>
+#include <stm32f0xx_pwr.h>
+#include <stm32f0xx_rtc.h>
+
+#include "delay.h"
+#include "ili9341.h"
+#include "ili9341gfx.h"
+#include "font_Arial.h"
+#include "glcdfont.h"
+#include "i2c.h"
+
+#include <24aaxx.h>
+
+//#define PHASE_A (GPIOA->IDR & 0x200)
+//#define PHASE_B (GPIOA->IDR & 0x400)
+//#define KEY (GPIOA->IDR & 0x100)
+
+#define PHASE_A (GPIOB->IDR & 0x2)
+#define PHASE_B (GPIOB->IDR & 0x4)
+#define KEY (GPIOB->IDR & 0x1)
+
+#define MCP3426 0x68
+#define MCP3421 0x68
+#define MCP4728 0x60
+#define MCP9808 0x18
+
+#define ADC_VOLT 0.8073F
+
+volatile uint16_t btn_hb=0;
+volatile uint8_t set_mode=2;
+volatile uint8_t read_adc=1;
+volatile uint8_t keyfunc=0;
+volatile uint8_t enc_event=0;
+volatile int8_t enc_delta;
+volatile uint16_t timer=0;
+volatile uint8_t run=0;
+volatile uint8_t check_temp=1;
+volatile uint8_t timeout=0;
+static int8_t enc_last;
+
+extern struct i2c_struct_type i2c;
+extern volatile uint8_t ili9341_buf;
+
+void RCC_Configuration(void);
+
+void i_to_a (char *a, uint32_t number, uint8_t count)
+{
+    a += count;
+    *a = '\0';
+
+    while (count--)
+    {
+        *--a = (number % 10) + '0';
+        number /= 10;
+    }
+}
+
+void encode_init( void )
+{
+    int8_t enc_new;
+
+    enc_new = 0;
+    if( PHASE_A )
+        enc_new = 3;
+    if( PHASE_B )
+        enc_new ^= 1;                                 // convert gray to binary
+    enc_last = enc_new;                                    // power on state
+    enc_delta = 0;
+}
+
+int8_t encode_read4( void )  // read four step encoders {
+{
+    int8_t enc_ret;
+
+    enc_ret = enc_delta;
+    enc_delta = enc_ret & 3;
+
+    return enc_ret >> 2;
+}
+
+
+
+void mcp4728_set_reference(uint8_t data)
+{
+       data = data & 0xf;
+       data += 0x80;
+
+       i2c_write(I2C1,&data,1,MCP4728);
+}
+
+void mcp4728_set_gain(uint8_t data)
+{
+       data = data & 0xf;
+       data += 0xc0;
+
+       i2c_write(I2C1,&data,1,MCP4728);
+}
+
+void mcp4728_set_pd(uint8_t data)
+{
+       uint8_t tmp[2] = { 0,0 };
+
+       tmp[0]=0xa0+((data & 0xf0)>>4);
+       tmp[1]=(data & 0xf)<<4;
+
+       i2c_write(I2C1,tmp,2,MCP4728);
+}
+
+void mcp4728_write_dac(uint8_t channel, uint16_t data, uint8_t ref, uint8_t gain)
+{
+
+       //uint8_t a,b,c;
+       uint8_t tmp[3] = { 0x58,0,0 };
+
+       tmp[0] += ((channel & 0x3)<<1);
+       tmp[1] = ((ref & 0x1)<<7);
+       if(gain)
+       {
+               tmp[1] += 0x10;
+       }
+//     b += ((gain & 0x1)<<4);
+
+       if(!data)
+       {
+               tmp[1] += 0x20;
+       }
+       tmp[1] += (uint8_t)((data & 0xf00)>>8);
+       //c = (uint8_t)(data & 0xff);
+
+       //tmp[0]=0x58+((channel & 0x3)<<1);
+       //tmp[1]=b;
+       tmp[2]=data & 0xff;
+
+       i2c_write(I2C1,tmp,3,MCP4728);
+       //i2c_start();
+       /*
+       i2c_set_nbytes(3);
+       i2c_autoend(0);
+       i2c_write_addr(MCP4728,WRITE);
+       i2c_start();
+       while(!(I2C1->ISR & I2C_ISR_TXIS));
+       i2c_write(a);
+       while(!(I2C1->ISR & I2C_ISR_TXIS));
+       i2c_write(b);
+       while(!(I2C1->ISR & I2C_ISR_TXIS));
+       i2c_write(c);
+       while(!(I2C1->ISR & I2C_ISR_TC));
+       //i2c_reset();
+       i2c_stop();
+       */
+}
+
+void mcp4728_write_fast_dac(uint16_t  *data)
+{
+
+       uint8_t  tmp[8] = { 0,0,0,0,0,0,0,0 };
+
+       for(uint8_t i=0;i<4;i++)
+       {
+               if(!data[i])
+               {
+                       data[i]+=0x1000;
+               }
+
+               tmp[(i*2)+1]=(uint8_t)(data[i] & 0xff);
+               tmp[i*2]=((uint8_t)((data[i] & 0xff00)>>8));
+       }
+
+       i2c_write(I2C1,tmp,8,MCP4728);
+
+}
+
+void mcp4728_general_update(void)
+{
+/*     i2c_start();
+       i2c_write_addr(MCP4728,WRITE);
+       i2c_write(0);
+       i2c_write(0x8);
+       i2c_stop();
+*/
+}
+
+void mcp3426_config(uint8_t cnf)
+{
+       i2c_write(I2C1,&cnf,1,MCP3426);
+       /*
+       i2c_autoend(0);
+       i2c_set_nbytes(1);
+    i2c_write_addr(MCP3426,WRITE);
+    i2c_start();
+    while(!(I2C1->ISR & I2C_ISR_TXIS));
+    i2c_write(cnf);
+    while(!(I2C1->ISR & I2C_ISR_TC));
+    */
+    //i2c_start();
+    //while(!(I2C1->ISR & I2C_ISR_TXIS));
+    //while(!(I2C1->ISR & I2C_ISR_TC));
+
+    i2c_stop(I2C1);
+}
+
+/*
+uint16_t mcp3426_read(uint8_t chan)
+{
+
+       uint16_t tmp;
+    uint8_t status;
+    chan=(chan & 0x1)<<5;
+    chan+=0x88;
+
+
+       i2c_autoend(0);
+       i2c_set_nbytes(1);
+    i2c_write_addr(MCP3426,WRITE);
+    i2c_start();
+    while(!(I2C1->ISR & I2C_ISR_TXIS));
+    i2c_write(chan);
+    while(!(I2C1->ISR & I2C_ISR_TC));
+
+    do
+    {
+       tmp=0;
+       i2c_set_nbytes(3);
+       i2c_write_addr(MCP3426,READ);
+       i2c_start();
+        while(!(I2C1->ISR & I2C_ISR_RXNE));
+        tmp=((uint16_t)(i2c_read_ack()) << 8);
+        while(!(I2C1->ISR & I2C_ISR_RXNE));
+        tmp+=i2c_read_ack();
+        while(!(I2C1->ISR & I2C_ISR_RXNE));
+        status=i2c_read_nack();
+        i2c_stop();
+
+    }
+
+       while (status & 0x80);
+    if(tmp & 0x8000) {
+       return 0;
+    }
+    else {
+       return tmp;
+    }
+}
+*/
+
+void mcp3421_config(uint8_t cnf, uint8_t device)
+{
+       uint16_t cycle;
+
+       if(i2c.state==I2C_IDLE && i2c.device==0)
+       {
+               i2c_autoend(I2C1,0);
+               i2c_set_nbytes(I2C1,1);
+               i2c_write_addr(I2C1,MCP3421+device,WRITE);
+               i2c.device=MCP3421+device;
+
+               i2c.rx_idx=0;
+               i2c.tx_idx=1;
+               i2c.buf_cnt=0;
+               i2c.tx_buf[0]=cnf;
+               I2C1->CR1 |= I2C_CR1_TXIE | I2C_CR1_TCIE;
+               i2c_start(I2C1);
+
+       }
+
+       cycle=(uint16_t)(SystemCoreClock/(100000/i2c.tx_idx));
+
+       while(cycle--)
+       {
+               asm("NOP");
+       }
+       (void)I2C1->ICR;
+
+    if(i2c.state==I2C_SENDING_DATA && i2c.device==MCP3421+device)
+    {
+               i2c.state=0;
+               i2c.device=0;
+    }
+       I2C1->ICR=0;
+}
+
+uint32_t mcp3421_read(uint8_t device)
+{
+
+       uint32_t tmp=0;
+    uint8_t temp[3];
+
+    i2c_read_ack(I2C1,temp,3,MCP3421+device);
+
+    tmp=temp[0]<<16;
+    tmp+=temp[1]<<8;
+    tmp+=temp[2];
+
+    if(tmp & 0x20000) {
+       return 0;
+       }
+    else {
+       return tmp;
+    }
+
+}
+
+
+uint16_t mcp9808_read(void)
+{
+       uint16_t temp=0;
+       uint16_t cycle;
+
+    if(i2c.state==I2C_IDLE && i2c.device==0)
+    {
+       i2c_autoend(I2C1,0);
+       i2c_set_nbytes(I2C1,1);
+       i2c_write_addr(I2C1,MCP9808,WRITE);
+       i2c.device=MCP9808;
+
+       i2c.rx_idx=0;
+       i2c.tx_idx=1;
+       i2c.buf_cnt=0;
+       i2c.tx_buf[0]=0x5;
+       I2C1->CR1 |= I2C_CR1_TCIE | I2C_CR1_TXIE;
+
+       i2c_start(I2C1);
+
+
+    }
+       cycle=(uint16_t)(SystemCoreClock/(100000/i2c.tx_idx));
+
+       while(cycle--)
+       {
+               asm("NOP");
+       }
+
+       I2C1->ICR=0;
+
+    if(i2c.state==I2C_SENDING_DATA && i2c.device==MCP9808)
+    {
+       i2c_autoend(I2C1,0);
+       i2c_set_nbytes(I2C1,2);
+       i2c_write_addr(I2C1,MCP9808,READ);
+       i2c.device=MCP9808;
+
+       i2c.rx_idx=2;
+       i2c.tx_idx=0;
+       i2c.buf_cnt=0;
+       I2C1->CR1 |= I2C_CR1_RXIE;
+       i2c_start(I2C1);
+
+       cycle=(uint16_t)(SystemCoreClock/(100000/i2c.rx_idx));
+
+       while(cycle--)
+       {
+               asm("NOP");
+       }
+
+       I2C1->ICR=0;
+    }
+
+    if(i2c.state==I2C_RECEIVING_DATA && i2c.device==MCP9808)
+    {
+
+       temp=(i2c.rx_buf[0] & 0xf) <<12;
+               temp+=i2c.rx_buf[1]<<4;
+               i2c.state=0;
+               i2c.device=0;
+    }
+
+    I2C1->ICR=0;
+
+       return temp;
+}
+
+void mcp9808_setalert(uint8_t upper, uint8_t lower, uint8_t crit)
+{
+
+       uint8_t tmp[3] = {0x1,0x0,0x1c};
+
+       i2c_write(I2C1,tmp,3,MCP9808);
+
+       /*
+       i2c_autoend(0);
+       i2c_set_nbytes(3);
+       i2c_write_addr(MCP9808,WRITE);
+       i2c_start();
+       while(!(I2C1->ISR & I2C_ISR_TXIS));
+       i2c_write(0x1);
+       while(!(I2C1->ISR & I2C_ISR_TXIS));
+       i2c_write(0x0);
+       while(!(I2C1->ISR & I2C_ISR_TXIS));
+       i2c_write(0x1c);
+       while(!(I2C1->ISR & I2C_ISR_TC));
+       */
+       //i2c_stop();
+       //i2c_reset();
+
+       tmp[0]=0x2;
+       tmp[1]=(uint8_t)((upper & 0xf0)>>4);
+       tmp[2]=(uint8_t)((upper & 0xf)<<4);
+
+       i2c_write(I2C1,tmp,3,MCP9808);
+
+       /*
+       i2c_autoend(0);
+       i2c_set_nbytes(3);
+       i2c_write_addr(MCP9808,WRITE);
+       i2c_start();
+       while(!(I2C1->ISR & I2C_ISR_TXIS));
+       i2c_write(0x2);
+       while(!(I2C1->ISR & I2C_ISR_TXIS));
+       i2c_write((uint8_t)((upper & 0xf0)>>4));
+       while(!(I2C1->ISR & I2C_ISR_TXIS));
+       i2c_write((uint8_t)((upper & 0xf)<<4));
+       while(!(I2C1->ISR & I2C_ISR_TC));
+       */
+       //i2c_reset();
+
+       tmp[0]=0x3;
+       tmp[1]=(uint8_t)((lower & 0xf0)>>4);
+       tmp[2]=(uint8_t)((lower & 0xf)<<4);
+
+       i2c_write(I2C1,tmp,3,MCP9808);
+
+
+
+       /*
+       i2c_autoend(0);
+       i2c_set_nbytes(3);
+       i2c_write_addr(MCP9808,WRITE);
+       i2c_start();
+       while(!(I2C1->ISR & I2C_ISR_TXIS));
+       i2c_write(0x3);
+       while(!(I2C1->ISR & I2C_ISR_TXIS));
+       i2c_write((uint8_t)((lower & 0xf0)>>4));
+       while(!(I2C1->ISR & I2C_ISR_TXIS));
+       i2c_write((uint8_t)((lower & 0xf)<<4));
+       while(!(I2C1->ISR & I2C_ISR_TC));
+       */
+       //i2c_reset();
+
+       tmp[0]=0x4;
+       tmp[1]=(uint8_t)((crit & 0xf0)>>4);
+       tmp[2]=(uint8_t)((crit & 0xf)<<4);
+
+       i2c_write(I2C1,tmp,3,MCP9808);
+
+       /*
+       i2c_autoend(0);
+       i2c_set_nbytes(3);
+       i2c_write_addr(MCP9808,WRITE);
+       i2c_start();
+       while(!(I2C1->ISR & I2C_ISR_TXIS));
+       i2c_write(0x4);
+       while(!(I2C1->ISR & I2C_ISR_TXIS));
+       i2c_write((uint8_t)((crit & 0xf0)>>4));
+       while(!(I2C1->ISR & I2C_ISR_TXIS));
+       i2c_write((uint8_t)((crit & 0xf)<<4));
+       while(!(I2C1->ISR & I2C_ISR_TC));
+       i2c_stop();
+       */
+
+}
+
+void show_amperes(uint16_t amperes, uint8_t factor) {
+
+       uint8_t amp[4],i;
+       char text[4];
+
+       amp[3]=(amperes/1000);
+       amp[2]=(amperes%1000)/100;
+       amp[1]=(amperes%100)/10;
+       amp[0]=(amperes%10);
+       ili9341_setfont(Arial_36);
+       ili9341_setcursor(28,12);
+       for(i=4;i>0;i--)
+       {
+               if(factor==(i-1))
+               {
+                       ili9341_settextcolor(BLACK,AMPERE);
+               }
+               else
+               {
+                       ili9341_settextcolor(AMPERE,BLACK);
+               }
+               if(i==4)
+               {
+                       i_to_a(text,amp[i-1],2);
+               }
+               else
+               {
+                       i_to_a(text,amp[i-1],1);
+               }
+               ili9341_out(text);
+               if(i==4)
+               {
+                       ili9341_settextcolor(AMPERE,BLACK);
+                       ili9341_out(".");
+               }
+       }
+
+       ili9341_setfont(Arial_10);
+       ili9341_setcursor(186,18);
+       ili9341_settextcolor(AMPERE,BLACK);
+       ili9341_out("Amps");
+}
+
+void show_voltage(uint16_t volt) {
+       uint8_t tmp1;
+       uint16_t tmp2;
+       char text[4];
+
+       tmp1=volt/1000;
+       tmp2=volt%1000;
+
+       ili9341_setfont(Arial_36);
+       ili9341_setcursor(0,67);
+       ili9341_settextcolor(VOLT,BLACK);
+       i_to_a(text,tmp1,3);
+       ili9341_out(text);
+       ili9341_out(".");
+       i_to_a(text,tmp2,3);
+       ili9341_out(text);
+       ili9341_setcursor(186,73);
+       ili9341_setfont(Arial_10);
+       ili9341_out("Volt");
+}
+
+/*
+void show_dec_mark(uint16_t dec) {
+
+//     ili9341_setcursor(4,41);
+//     ili9341_settextsize(4);
+//     ili9341_settextcolor(RED,BLACK);
+       ili9341_drawhline(4,75,180,BLACK);
+       switch(dec)
+       {
+       case 1:
+               //ili9341_out("      _");
+               ili9341_drawhline(148,75,20,RED);
+               break;
+       case 10:
+               //ili9341_out("     _ ");
+               ili9341_drawhline(124,75,20,RED);
+               break;
+       case 100:
+               //ili9341_out("    _  ");
+               ili9341_drawhline(100,75,20,RED);
+               break;
+       case 1000:
+               //ili9341_out(" _     ");
+               ili9341_drawhline(28,75,44,RED);
+               break;
+       }
+}
+*/
+
+void show_status(uint8_t stat)
+{
+       if(stat)
+       {
+               ili9341_fillrect(226,11,97,49,RED);
+               ili9341_setcursor(240,30);
+               ili9341_settextcolor(WHITE,RED);
+               ili9341_setfont(Arial_13);
+               ili9341_out("Running");
+       }
+       else
+       {
+               ili9341_fillrect(226,11,97,49,DARKGREEN);
+               ili9341_setcursor(240,30);
+               ili9341_settextcolor(WHITE,DARKGREEN);
+               ili9341_setfont(Arial_13);
+               ili9341_out("Standby");
+       }
+}
+
+void show_watt(uint32_t watt) {
+       uint8_t tmp1;
+       uint16_t tmp2;
+       char text[4];
+
+       tmp1=watt/1000;
+       tmp2=watt%1000;
+       ili9341_setcursor(0,115);
+       //ili9341_settextsize(3);
+       ili9341_setfont(Arial_36);
+       ili9341_settextcolor(WATT,BLACK);
+       i_to_a(text,tmp1,3);
+       ili9341_out(text);
+       ili9341_out(".");
+       i_to_a(text,tmp2,3);
+       ili9341_out(text);
+       //ili9341_settextsize(1);
+       ili9341_setcursor(186,121);
+       ili9341_setfont(Arial_10);
+       ili9341_out("Watt");
+}
+
+void show_resistance(uint32_t resistance) {
+       uint8_t tmp1;
+       uint16_t tmp2;
+       char text[5];
+
+       ili9341_settextcolor(OHM,BLACK);
+       if((resistance>99999) || (resistance==0) )
+       {
+               ili9341_fillrect(6,164,180,43,BLACK);
+               //ili9341_setcursor(14,166);
+               //ili9341_settextsize(3);
+               //ili9341_settextcolor(BLUE,BLACK);
+               //ili9341_out("     ");
+               //ili9341_write(0x82);
+               //ili9341_out("     ");
+       }
+       else
+       {
+               ili9341_setcursor(28,164);
+               //ili9341_settextsize(3);
+               ili9341_setfont(Arial_36);
+               tmp1=resistance%10;
+               tmp2=resistance/10;
+               i_to_a(text,tmp2,4);
+               ili9341_out(text);
+               ili9341_out(".");
+               i_to_a(text,tmp1,1);
+               ili9341_out(text);
+
+       //ili9341_out(0x81);
+
+       }
+       ili9341_setcursor(186,170);
+       //ili9341_settextsize(1);
+       ili9341_setfont(Arial_10);
+       ili9341_out("Ohms");
+       //ili9341_write(0x80);
+}
+
+void show_cutoffvoltage(uint16_t voltage)
+{
+       char text[4];
+
+       ili9341_settextcolor(NPURPLE,LIGHTGREY);
+       ili9341_setfont(Arial_13);
+       ili9341_setcursor(253,151);
+       i_to_a(text,voltage/100,3);
+       ili9341_out(text);
+       ili9341_out(".");
+       i_to_a(text,voltage%100,2);
+       ili9341_out(text);
+       ili9341_out("V");
+}
+
+void show_readbackcurrent(uint32_t current)
+{
+       char text[4];
+
+       //current-=256;
+       current*=10000;
+       //current/=64000;
+       current/=64750;
+       current-=4;
+       ili9341_settextcolor(LILAS,LIGHTGREY);
+       ili9341_setfont(Arial_13);
+       ili9341_setcursor(253,132);
+       i_to_a(text,current/1000,2);
+       ili9341_out(text);
+       i_to_a(text,current%1000,3);
+       ili9341_out(".");
+       ili9341_out(text);
+       ili9341_out("A");
+}
+
+void show_temperature(uint16_t temperature) {
+
+       uint16_t tmp1,tmp2;
+       char text[5];
+
+       tmp1 = (temperature & 0xff00)>>8;
+       tmp2 = (temperature & 0xf0) >> 4;
+
+       ili9341_settextcolor(RED,LIGHTGREY);
+       ili9341_setfont(Arial_13);
+       ili9341_setcursor(256,168);
+       i_to_a(text,tmp1,3);
+       ili9341_out(text);
+       ili9341_out(".");
+       tmp1=0;
+       if(tmp2 & 0x8) {
+               tmp1+=5000;
+       }
+       if(tmp2 & 0x4) {
+               tmp1+=2500;
+       }
+       if(tmp2 & 0x2) {
+               tmp1+=1250;
+       }
+       if(tmp2 & 0x1) {
+               tmp1+=625;
+       }
+       i_to_a(text,tmp1/1000,1);
+       ili9341_out(text);
+       ili9341_out("  ");
+       ili9341_setfont(Arial_8);
+       ili9341_setcursor(302,165);
+       ili9341_out("o");
+       ili9341_setcursor(307,168);
+       ili9341_setfont(Arial_13);
+       ili9341_out("C");
+
+}
+
+uint8_t bcd_to_epphex(uint8_t nmb)
+{
+       uint8_t o_0,d_1;
+
+       o_0=nmb%10;
+       d_1=(nmb-o_0)/10;
+       d_1*=0x10;
+       d_1+=(o_0*2);
+
+       return d_1;
+
+}
+
+void show_dacvals(uint16_t * data)
+{
+       char text[5];
+       ili9341_setfont(Arial_9);
+       ili9341_settextcolor(BLACK,LIGHTGREY);
+       ili9341_setcursor(245,204);
+       i_to_a(text,data[0],4);
+       ili9341_out(text);
+       ili9341_out(" ");
+       i_to_a(text,data[1],4);
+       ili9341_out(text);
+       ili9341_setcursor(245,220);
+       i_to_a(text,data[2],4);
+       ili9341_out(text);
+       ili9341_out(" ");
+       i_to_a(text,data[3],4);
+       ili9341_out(text);
+}
+
+void fet_pulldown(uint16_t *data)
+{
+       uint8_t i;
+       uint16_t t=0x100;
+
+       for(i=0;i<4;i++)
+       {
+               if(!data[i])
+               {
+                       GPIOA->BSRR = (uint32_t)(t<<i);
+
+               }
+               else
+               {
+                       GPIOA->BRR = (uint32_t)(t<<i);
+               }
+       }
+}
+
+
+int main(void)
+{
+
+       uint8_t init=1;
+       float volt=0;
+       uint16_t amperes=0;
+       uint8_t menu=0;
+       uint8_t calib=0;
+       uint8_t set_volt=0;
+       uint32_t cutoff_volt=0;
+       uint8_t i,j,m=0,s=0,h=0;
+       uint8_t step_width=0;
+       uint32_t current=0;
+       uint16_t factor=1;
+       uint32_t amp_readback[2];
+
+       float wh=0,ah=0;
+       uint16_t t1_16,t2_16;
+       uint32_t t1_32;
+       uint16_t t_clb=0;
+       uint16_t dac[4][21];
+       uint16_t adc[4][21];
+       //uint8_t current_read[4] = { 0,0,0,0 };
+       uint16_t dac_val[4] = { 0,9,0,0 };
+       uint16_t null[4] = { 0x0,0x0,0x0,0x0 };
+       uint16_t temperature=0;
+       uint16_t timer_local=0;
+       char text[6];
+       float flt1, flt2;
+
+       RCC_Configuration();
+
+       delay_init();
+
+       RCC->APB1RSTR |=  RCC_APB1RSTR_I2C1RST;
+       RCC->APB1RSTR &= ~RCC_APB1RSTR_I2C1RST;
+
+    i2c_init(I2C1);
+
+
+    GPIOA->MODER |= GPIO_MODER_MODER0_0 | GPIO_MODER_MODER1_0 | GPIO_MODER_MODER2_0 | GPIO_MODER_MODER3_0 | GPIO_MODER_MODER4_1 |
+                               GPIO_MODER_MODER5_1 | GPIO_MODER_MODER6_1 | GPIO_MODER_MODER7_1 | GPIO_MODER_MODER8_0 | GPIO_MODER_MODER9_0 |
+                                       GPIO_MODER_MODER10_0 | GPIO_MODER_MODER11_0;
+
+    GPIOA->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR0 | GPIO_OSPEEDER_OSPEEDR1 | GPIO_OSPEEDER_OSPEEDR2 | GPIO_OSPEEDER_OSPEEDR3 |
+                    GPIO_OSPEEDER_OSPEEDR4 | GPIO_OSPEEDER_OSPEEDR5 | GPIO_OSPEEDER_OSPEEDR6 | GPIO_OSPEEDER_OSPEEDR7 |
+                    GPIO_OSPEEDER_OSPEEDR8 | GPIO_OSPEEDER_OSPEEDR9 | GPIO_OSPEEDER_OSPEEDR10 | GPIO_OSPEEDER_OSPEEDR11;
+
+    GPIOA->PUPDR |= GPIO_PUPDR_PUPDR12_0 | GPIO_PUPDR_PUPDR15_0;
+    GPIOA->AFR[0] = 0x0;
+
+    GPIOB->MODER |=  GPIO_MODER_MODER4_1 | GPIO_MODER_MODER6_1 | GPIO_MODER_MODER7_1 | GPIO_MODER_MODER8_0 | GPIO_MODER_MODER9_0 |
+                               GPIO_MODER_MODER12_0;
+    GPIOB->OTYPER |= GPIO_OTYPER_OT_6 | GPIO_OTYPER_OT_7;
+    GPIOB->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR4 | GPIO_OSPEEDER_OSPEEDR6 | GPIO_OSPEEDER_OSPEEDR7 | GPIO_OSPEEDER_OSPEEDR8 | GPIO_OSPEEDER_OSPEEDR9;
+    GPIOB->PUPDR |= GPIO_PUPDR_PUPDR0_0 | GPIO_PUPDR_PUPDR1_0 | GPIO_PUPDR_PUPDR2_0 | GPIO_PUPDR_PUPDR3_0 |
+                    GPIO_PUPDR_PUPDR6_0 | GPIO_PUPDR_PUPDR7_0;
+    GPIOB->AFR[0] = 0x11010000;
+
+    SPI1->CR1 |= SPI_CR1_MSTR; // | SPI_CR1_SSI | SPI_CR1_SSM;
+    SPI1->CR2 |= SPI_CR2_SSOE | SPI_CR2_FRXTH | SPI_CR2_DS_0 | SPI_CR2_DS_1 | SPI_CR2_DS_2;
+    //SPI1->CR2 = 0x1700;
+    SPI1->CR1 |= SPI_CR1_SPE;
+    NVIC->ISER[0] |= (1<<(SPI1_IRQn & 0x1f));
+
+    TIM3->PSC = 7;
+    TIM3->ARR = 250;
+    TIM3->CCR1 = 0;
+    TIM3->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1PE;
+       TIM3->CCER |= TIM_CCER_CC1E | TIM_CCER_CC1P;
+    TIM3->BDTR |= TIM_BDTR_MOE;
+    TIM3->CR1 |=  TIM_CR1_CEN; // | TIM_CR1_CMS_0; // | TIM_CR1_DIR;
+    TIM3->EGR |= TIM_EGR_UG;
+
+    TIM14->PSC = 249;                 // Timer14 333ms
+    TIM14->ARR = 63935;
+    TIM14->CR1 |= TIM_CR1_URS;
+    TIM14->DIER |= TIM_DIER_UIE;
+    TIM14->CR1 |= (TIM_CR1_CEN);
+
+    TIM15->PSC = 749;
+    TIM15->ARR = 63999;
+    TIM15->DIER |= TIM_DIER_UIE;
+    TIM15->CR1 |= TIM_CR1_CEN;
+
+    TIM16->PSC = 0;                                      // Timer3 500uS
+    TIM16->ARR = 23999; //18001;
+    //TIM3->CR1 |= TIM_CR1_URS;
+    TIM16->DIER |= TIM_DIER_UIE;
+    TIM16->CR1 |= (TIM_CR1_CEN);
+
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+    PWR->CR |= PWR_CR_DBP;
+
+    RCC->BDCR |= RCC_BDCR_BDRST;
+    RCC->BDCR &= ~(RCC_BDCR_BDRST);
+
+    PWR->CR |= PWR_CR_DBP;
+
+    RCC->BDCR &= ~(RCC_BDCR_LSEBYP);
+    RCC->BDCR |= RCC_BDCR_LSEON;                                       // enable LSE
+    while((RCC->BDCR & RCC_BDCR_LSERDY)==0);
+
+    RCC->BDCR |= RCC_BDCR_RTCSEL_LSE;                          // LSE clock source select
+    RCC->BDCR |= RCC_BDCR_RTCEN;                                       // RTC enable
+
+    RTC->WPR = 0xca;
+       RTC->WPR = 0x53;
+    /* Reset TR, DR and CR registers */
+    RTC->TR        = (uint32_t)0x00000000;
+    RTC->WUTR      = (uint32_t)0x0000FFFF;
+    RTC->DR        = (uint32_t)0x00002101;
+    RTC->CR        &= (uint32_t)0x00000000;
+    RTC->PRER      = (uint32_t)0x007F00FF;
+    RTC->ALRMAR    = (uint32_t)0x00000000;
+    RTC->SHIFTR    = (uint32_t)0x00000000;
+    RTC->CALR       = (uint32_t)0x00000000;
+    RTC->ALRMASSR  = (uint32_t)0x00000000;
+    RTC->CR |= RTC_CR_COE;
+
+    /* Reset ISR register and exit initialization mode */
+    RTC->ISR = (uint32_t)0x00000000;
+
+    /* Reset Tamper and alternate functions configuration register */
+    RTC->TAFCR = 0x00000000;
+
+    RTC->WPR = 0xff;
+
+    //RCC->APB1ENR &= ~RCC_APB1ENR_PWREN;
+    PWR->CR |= PWR_CR_DBP;
+
+    RTC->WPR = 0xca;
+    RTC->WPR = 0x53;
+    //RTC->ISR |= RTC_ISR_INIT;
+    RTC->CR &= ~RTC_CR_ALRAE;
+    while(!(RTC->ISR & RTC_ISR_ALRAWF));
+    RTC->ALRMAR = 0x80808080;
+    RTC->CR |= RTC_CR_ALRAIE | RTC_CR_ALRAE; // | RTC_CR_COE | RTC_CR_COSEL; // | RTC_CR_OSEL_1;
+    RTC->WPR = 0xff;
+    //RTC->WPR = 0x64;
+
+    RTC->WPR = 0xca;
+    RTC->WPR = 0x53;
+
+    RTC->ISR |= RTC_ISR_INIT;
+    while((RTC->ISR & RTC_ISR_INITF)!=RTC_ISR_INITF);
+    RTC->TR = 0x0;
+    RTC->ISR &=~ RTC_ISR_INIT;
+    while((RTC->ISR & RTC_ISR_RECALPF) == RTC_ISR_RECALPF);
+    RTC->WPR = 0xff;
+    EXTI->IMR |= EXTI_IMR_MR17;
+    EXTI->RTSR |= EXTI_RTSR_TR17;
+
+
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+
+    SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI3_PB;
+    EXTI->IMR |= EXTI_IMR_MR3;
+    EXTI->EMR |= EXTI_EMR_MR3;
+    EXTI->FTSR |= EXTI_FTSR_TR3;
+
+    encode_init();
+
+    IWDG->KR = 0xcccc;
+    IWDG->KR = 0x5555;
+    IWDG->PR = IWDG_PR_PR_2; // IWDG_PR_PR_1 | IWDG_PR_PR_0 ;/* (3) */
+    IWDG->RLR = IWDG_RLR_RL;
+
+    delay_ms(100);
+    ili9341_init();
+    /*
+    mcp24aa32_write_word(0x1e00,0);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e02,200);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e04,400);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e06,600);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e08,800);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e0a,1000);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e0c,1200);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e0e,1400);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e10,1600);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e12,1800);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e14,2000);
+       delay_ms(50);
+    mcp24aa32_write_word(0x1e16,2200);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e18,2400);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e1a,2600);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e1c,2800);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e1e,3000);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e20,3200);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e22,3400);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e24,3600);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e26,3800);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e28,4000);
+*/
+
+       #pragma mark - initialisation -
+
+    ili9341_clear(BLACK);
+    ili9341_setrotation(3);
+    ili9341_setcursor(105,0);
+    //ili9341_settextsize(0);
+    ili9341_setfont(Arial_8);
+    ili9341_settextcolor(ORANGE,BLACK);
+    ili9341_out("Electronic Load by HB9EVI");
+    ili9341_drawhline(0,10,360,WHITE);
+    ili9341_drawvline(225,10,225,WHITE);
+    ili9341_drawhline(230,65,122,WHITE);
+    ili9341_drawhline(230,200,122,WHITE);
+    ili9341_drawhline(0,222,360,WHITE);
+    ili9341_fillrect(226,60,174,174,LIGHTGREY);
+    ili9341_fillrect(0,223,320,27,LIGHTGREY);
+
+       ili9341_setcursor(226,111);
+       //ili9341_setcursor(244,111);
+       ili9341_settextcolor(BLACK,LIGHTGREY);
+       ili9341_setfont(Arial_10);
+       ili9341_out("t");
+       ili9341_setcursor(231,116);
+       ili9341_setfont(Arial_8);
+       ili9341_out("run");
+
+       ili9341_setcursor(226,132);
+       ili9341_settextcolor(LILAS,LIGHTGREY);
+       ili9341_setfont(Arial_10);
+       ili9341_out("I");
+       ili9341_setcursor(231,137);
+       ili9341_setfont(Arial_8);
+       ili9341_out("read");
+
+       ili9341_settextcolor(NPURPLE,LIGHTGREY);
+       ili9341_setcursor(226,151);
+       ili9341_setfont(Arial_10);
+       ili9341_out("U");
+       ili9341_setcursor(235,156);
+       ili9341_setfont(Arial_8);
+       ili9341_out("cut");
+
+       ili9341_setfont(Arial_10);
+       ili9341_settextcolor(RED,LIGHTGREY);
+       ili9341_setcursor(226,168);
+       ili9341_out("T");
+       ili9341_setfont(Arial_8);
+       ili9341_setcursor(233,173);
+       ili9341_out("cool");
+
+    NVIC->ISER[0] |= (1<<(I2C1_IRQn & 0x1f));
+       //mcp3421_config(0x1c,1);
+       //current=mcp3421_read(1);
+    //mcp24aa32_write_word(0xfff0, 0x1234);
+
+    delay_ms(6);
+
+       for(j=0;j<4;j++)
+       {
+               for(i=0;i<21;i++)
+               {
+                       if(i==0)
+                       {
+                               dac[j][i]=0;
+                       }
+                       else
+                       {
+                               dac[j][i]=_24aa32_read(I2C1, (0x100*j)+(i*2),2);
+                       }
+                       adc[j][i]=_24aa32_read(I2C1, 0x400 +(0x100*j)+(i*2),2);
+               }
+       }
+
+       #pragma mark dac/adc init -
+
+       GPIOB->BRR=0x100;
+       mcp4728_set_gain(0x0);
+       delay_ms(1);
+       mcp4728_set_reference(0xf);
+       delay_ms(1);
+       mcp3421_config(0x1c,1);
+       delay_ms(1);
+       mcp3421_config(0x1c,0);
+       delay_ms(1);
+       mcp4728_write_fast_dac(dac_val);
+       delay_ms(4);
+       fet_pulldown(null);
+       mcp9808_setalert(28,40,60);
+
+
+
+       while (1)
+    {
+               if(check_temp)
+               {
+                       t1_16=((temperature & 0xff00)>>8);
+                       if(t1_16>=30)
+                       {
+                               TIM3->CCR1 = (t1_16-30)*10;
+                       }
+                       else {
+                               TIM3->CCR1 = 0;
+                       }
+                       check_temp=0;
+               }
+
+               if(btn_hb)
+               {
+            ili9341_setcursor(4,223);
+            //ili9341_settextsize(1);
+            ili9341_setfont(Arial_13);
+            ili9341_settextcolor(BLACK,LIGHTGREY);
+            if(btn_hb<1500) {
+                    ili9341_out("Toggle ON/OFF     ");
+            }
+            else if(btn_hb<3000) {
+                    ili9341_out("Set Step Width    ");
+            }
+            else if(btn_hb<4500) {
+                       ili9341_out("Set Cutoff Voltage");
+            }
+            else if(btn_hb<6000) {
+                    ili9341_out("Reset Counters    ");
+            }
+            else if(btn_hb<7500) {
+                       ili9341_out("Store Parameters  ");
+            }
+            else if(btn_hb<0xffff) {
+                       ili9341_out("Calibration       ");
+            }
+               }
+               if(timeout)
+               {
+                       switch(timeout)
+                       {
+                       case 10:
+                               ili9341_fillrect(230,204,90,35,LIGHTGREY);
+                               timeout=0;
+                               break;
+                       }
+               }
+
+               /*
+               if(read_adc)
+               {
+                       volt=(float)(mcp3421_read(1));
+                       current=mcp3421_read(0);
+                       set_mode=11;
+                       read_adc=0;
+               }
+               */
+               if(keyfunc)
+               {
+                       IWDG->KR = 0xaaaa;
+                       switch(keyfunc)
+                       {
+                       case 0xfe:                                                              // rotary encoder
+                               if(!calib && !set_volt)
+                               {
+                                       amperes+=(encode_read4()*factor);
+                                       if(amperes>=21000) {
+                                               amperes=0;
+                                       }
+                                       NVIC->ISER[0] &= ~(1<<(TIM14_IRQn & 0x1f));
+                                       set_mode=2;
+
+                               }
+                               else if(set_volt)
+                               {
+                                       cutoff_volt+=(encode_read4()*factor);
+                                       if(cutoff_volt>10000) {
+                                               cutoff_volt=0;
+                                       }
+                                       set_mode=6;
+
+                               }
+                               else
+                               {
+                                       t_clb+=encode_read4();
+                                       set_mode=10;
+                               }
+                               break;
+                       case 0xfd:
+                               if(calib)                                                       // calculate new eeprom values from calibration
+                               {
+                                       if(factor==100) {
+                                               flt1=(float)_24aa32_read(I2C1, 0x1e00 +((amperes/factor)%10)*2,2);
+                                       }
+                                       else if(factor==1000) {
+                                               flt1=(float)_24aa32_read(I2C1, 0x1e00 +((amperes/factor)%100)*2,2);
+                                       }
+                                       else {
+                                               flt1=(float)_24aa32_read(I2C1, 0x1f00 +((amperes/factor)%10)*2,2);
+                                       }
+                                       flt2=(float)(t_clb);
+                                       flt2/=1000;
+                                       flt1/=flt2;
+                                       if(amperes>9999) {
+                                               flt1*=(float)((amperes/factor)%100);
+                                               flt1/=10;
+                                       }
+                                       else {
+                                               flt1*=(float)((amperes/factor)%10);
+                                       }
+                                       i_to_a(text,(uint16_t)(flt1),4);
+                                       ili9341_settextcolor(BLACK,LIGHTGREY);
+                                       ili9341_setcursor(230,210);
+                                       ili9341_setfont(Arial_12);
+                                       //ili9341_settextsize(1);
+                                       ili9341_out(text);
+                                       if(factor==1000) {
+                                               _24aa32_write(I2C1, (0x100*step_width) + (((amperes/factor)%100)*2),(uint16_t)(flt1),2);
+                                               dac[step_width][(amperes/factor)%100]=(uint16_t)(flt1);
+                                               dac_val[step_width]=(uint16_t)(flt1);
+                                       }
+                                       else {
+                                               _24aa32_write(I2C1, (0x100*step_width) + (((amperes/factor)%10)*2),(uint16_t)(flt1),2);
+                                               dac[step_width][(amperes/factor)%10]=(uint16_t)(flt1);
+                                               dac_val[step_width]=(uint16_t)(flt1);
+                                       }
+                                       mcp4728_write_fast_dac(dac_val);
+                                       fet_pulldown(dac_val);
+                                       delay_ms(50);
+                                       /*
+                                       if(factor==1000)
+                                       {
+                                               amp_readback[0]=mcp3426_read(1);
+                                               mcp24aa32_write_word(0x400 + (0x100*step_width) + ((amperes/factor)%100)*2, amp_readback[0]);
+                                       }
+                                       else if(factor==100)
+                                       {
+                                               amp_readback[0]=mcp3426_read(1);
+                                               mcp24aa32_write_word(0x400 + (0x100*step_width) + ((amperes/factor)%10)*2, amp_readback[0]);
+                                       }
+                                       else
+                                       {
+                                               amp_readback[0]=mcp3426_read(0);
+                                               mcp24aa32_write_word(0x400 + (0x100*step_width) + ((amperes/factor)%10)*2, amp_readback[0]);
+                                       }
+                                       */
+                                       //amp_readback[0]=mcp3421_read(0);
+                                       adc[step_width][(amperes/factor)%10]=amp_readback[0];
+                                       GPIOB->BRR=0x100;
+                                       calib=0;
+                                       set_mode=2;
+                               }
+                               else if(set_volt) {
+                                       set_volt=0;
+                                       set_mode=2;
+                               }
+                               else                                                                    // outside calibration just toggle load on/off
+                               {
+                                       run^=1;
+                                       set_mode=9;
+                               }
+
+                               break;
+                       case 0xfc:                                                      // set step width
+                               step_width++;
+                               factor*=10;
+                               if(step_width==4)
+                               {
+                                       factor=1;
+                                       step_width=0;
+                               }
+                               set_mode=11;
+                               break;
+
+                       case 0xfb:                                                      // reset wh/ah counters
+                               wh=0;
+                               ah=0;
+                               s=0;
+                               m=0;
+                               h=0;
+                               set_mode=4;
+                               break;
+                       case 0xf9:
+                               set_volt=1;
+                               set_mode=6;
+                               break;
+                       case 0xea:                                                      // calibration mode
+                               calib=1;
+                               if(amperes>9999) {
+                                       t_clb=amperes/10;
+                               }
+                               else {
+                                       t_clb=amperes*(1000/factor);
+                               }
+                               dac_val[0]=0;
+                               dac_val[1]=0;
+                               dac_val[2]=0;
+                               dac_val[3]=0;
+                               if(factor==100) {
+                                       dac_val[step_width]=_24aa32_read(I2C1, 0x1e00 +((amperes/factor)%10)*2,2);
+                               }
+                               else if(factor==1000) {
+                                       dac_val[step_width]=_24aa32_read(I2C1, 0x1e00 +((amperes/factor)%100)*2,2);
+                               }
+                               else {
+                                       dac_val[step_width]=_24aa32_read(I2C1, 0x1f00 +((amperes/factor)%10)*2,2);
+                               }
+                               mcp4728_write_fast_dac(dac_val);
+                               fet_pulldown(dac_val);
+                               GPIOB->BSRR=0x100;
+                               set_mode=10;
+                               break;
+                       }
+
+            if(!menu) {
+                ili9341_fillrect(0,223,223,27,LIGHTGREY);
+            }
+            keyfunc=0;
+            btn_hb=0;
+
+               }
+               if((timer_local!=timer) && !(init) && (run) && (set_mode!=9))
+               {
+                       timer_local=timer;
+                       set_mode=4;
+               }
+               if(set_mode)
+               {
+                       switch(set_mode)
+                       {
+                       case 2:                                                         // adjust DAC
+                               show_amperes(amperes,step_width);
+                               dac_val[0]=dac[0][amperes%10];
+                               dac_val[1]=dac[1][(amperes/10)%10];
+                               dac_val[2]=dac[2][(amperes/100)%10];
+                               dac_val[3]=dac[3][(amperes/1000)%100];
+
+                               mcp4728_write_fast_dac(dac_val);
+                               show_dacvals(dac_val);
+                               timeout=0;
+                               if(run) {
+                                       fet_pulldown(dac_val);
+                                       mcp4728_set_pd(0x0);
+                               }
+                               else {
+                                       fet_pulldown(null);
+                                       mcp4728_set_pd(0xaa);
+                               }
+
+                               if (init) {
+                                       set_mode=4;
+                               }
+                               else {
+                                       set_mode=0;
+                               }
+                               break;
+                       case 4:
+                               if(s==60) {
+                                       m++;
+                                       s=0;
+                               }
+                               if(m==60) {
+                                       h++;
+                                       m=0;
+                               }
+                               if(h==100) {
+                                       h=0;
+                               }
+                               t1_32=(uint32_t)wh;
+                               t1_16=t1_32%1000;
+                               t2_16=t1_32/1000;
+                               ili9341_setcursor(227,73);
+                               //ili9341_settextsize(1);
+                               ili9341_setfont(Arial_13);
+                               ili9341_settextcolor(LIGHTBLUE,LIGHTGREY);
+                               i_to_a(text,t2_16,3);
+                               ili9341_out(text);
+                               ili9341_out(".");
+                               i_to_a(text,t1_16,3);
+                               ili9341_out(text);
+                               ili9341_out("Wh ");
+                               ili9341_setcursor(238,90);
+                               ili9341_settextcolor(DARKCYAN,LIGHTGREY);
+                               t1_32=(uint32_t)ah;
+                               t1_16=t1_32%1000;
+                               t2_16=t1_32/1000;
+                               i_to_a(text,t2_16,2);
+                               ili9341_out(" ");
+                               ili9341_out(text);
+                               ili9341_out(".");
+                               i_to_a(text,t1_16,3);
+                               ili9341_out(text);
+                               ili9341_out("Ah");
+                               ili9341_setcursor(244,111);
+                               ili9341_settextcolor(BLACK,LIGHTGREY);
+                               i_to_a(text,h,2);
+                               ili9341_out(" ");
+                               ili9341_out(text);
+                               ili9341_out(":");
+                               i_to_a(text,m,2);
+                               ili9341_out(text);
+                               ili9341_out(":");
+                               i_to_a(text,s,2);
+                               ili9341_out(text);
+
+                               temperature=mcp9808_read();
+                               //temperature=0;
+                               show_temperature((uint16_t)(temperature));
+
+                               if(init) {
+                                       set_mode=5;
+                               }
+                               else {
+                                       ah+=(amperes/(float)3600);
+                                       wh+=((amperes*(float)(volt/1000))/3600);
+                                       s++;
+                                       set_mode=0;
+
+                               }
+                               NVIC->ISER[0] |= (1<<(TIM14_IRQn & 0x1f));
+                               break;
+                       case 5:
+                               //show_dec_mark(factor);
+                               if(init) {
+                                       set_mode=6;
+                               }
+                               else {
+                                       set_mode=0;
+                               }
+                               break;
+                       case 6:
+                               show_cutoffvoltage(cutoff_volt);
+                               if(init) {
+                                       set_mode=9;
+                               }
+                               else {
+                                       set_mode=0;
+                               }
+                               break;
+                       case 9:
+                               if(run)
+                               {
+                                       EXTI->PR |= EXTI_PR_PR17;
+                                       RTC->ISR &= ~(RTC_ISR_ALRAF);
+                                       EXTI->IMR |= EXTI_IMR_MR17; /* (13) */
+                                       EXTI->RTSR |= EXTI_RTSR_TR17;
+                                       NVIC->ISER[0] |= (1<<(RTC_IRQn & 0x1f));
+                                       mcp4728_set_pd(0x0);
+                                       fet_pulldown(dac_val);
+                               }
+                               else
+                               {
+                                       EXTI->IMR &= ~EXTI_IMR_MR17; /* (13) */
+                                       EXTI->RTSR &= ~EXTI_RTSR_TR17;
+                                       NVIC->ISER[0] &= ~(1<<(RTC_IRQn & 0x1f));
+                                       EXTI->PR |= EXTI_PR_PR17;
+                                       RTC->ISR &= ~(RTC_ISR_ALRAF);
+                                       mcp4728_set_pd(0xaa);
+                                       fet_pulldown(null);
+                               }
+                               show_status(run);
+                               if(init) {
+                                       init=0;
+                                   NVIC->ISER[0] |= (1<<(TIM14_IRQn & 0x1f));
+                                   NVIC->ISER[0] |= (1<<(TIM15_IRQn & 0x1f));
+                                   NVIC->ISER[0] |= (1<<(TIM16_IRQn & 0x1f));
+                                   NVIC->ISER[0] |= (1<<(EXTI2_3_IRQn & 0x1f));
+                               }
+                               set_mode=0;
+                               break;
+                       case 10:
+
+                               ili9341_setcursor(230,210);
+                               //ili9341_settextsize(1);
+                               ili9341_setfont(Arial_12);
+                               ili9341_settextcolor(BLACK,LIGHTGREY);
+                               i_to_a(text,t_clb,4);
+                               ili9341_out(text);
+                               break;
+                       case 11:                                                                // read ADC values
+                               if(read_adc)
+                               {
+                                       delay_ms(2);
+                                       volt=(float)(mcp3421_read(1));
+                                       volt*=ADC_VOLT; // 0.8073;
+
+                                       delay_ms(2);
+                                       //amp_readback[1]=mcp3426_read(1);
+                                       //amp_readback[0]=mcp3421_read(0);
+                                       /*
+                                       current_read[0]=0;
+                                       current_read[1]=0;
+                                       current_read[2]=0;
+                                       current_read[3]=0;
+                                       */
+                                       //if(amp_readback>(uint32_t)((adc[2][9]<<15)+(adc[1][9])+(adc[0][9])))
+                                       if(amp_readback[1]>adc[2][9])
+                                       {
+                                               for(i=0;i<21;i++)
+                                               {
+                                                       //if((amp_readback>=(uint32_t)(adc[3][i]<<15)) && (amp_readback<(uint32_t)(adc[3][i+1]<<15)))
+                                                       if((amp_readback[1]>=adc[3][i]) && (amp_readback[1]<adc[3][i+1]))
+                                                       {
+                                                               //current_read[3]=i;
+                                                               amp_readback[1]-=adc[3][i];
+                                                       }
+                                               }
+                                       }
+                                       //if(amp_readback>(uint32_t)((adc[1][9])+(adc[0][9])))
+                                       //if(amp_readback[1]>adc[1][9])
+                                       //{
+                                       for(i=0;i<10;i++)
+                                       {
+                                               //if((amp_readback>=(uint32_t)(adc[2][i]<<15)) && (amp_readback<(uint32_t)(adc[2][i+1]<<15)))
+                                               if((amp_readback[1]+10>=adc[2][i]) && amp_readback[1]<adc[2][i+1])
+                                               {
+                                                       //current_read[2]=i;
+                                                               //amp_readback[1]-=adc[2][i];
+                                               }
+                                       }
+                                       //}
+                                       if(amp_readback[0]>(adc[0][9]))
+                                       {
+                                               for(i=0;i<10;i++)
+                                               {
+                                                       if((amp_readback[0]>=adc[1][i]) && (amp_readback[0]<adc[1][i+1]))
+                                                       {
+                                                               //current_read[1]=i;
+                                                               amp_readback[0]-=(adc[1][i]);
+                                                       }
+                                               }
+                                       }
+                                       for(i=0;i<10;i++)
+                                       {
+                                               if((amp_readback[0]>=adc[0][i]) && (amp_readback[0]<adc[0][i+1]))
+                                               {
+                                                       //current_read[0]=i;
+                                               }
+                                       }
+                                       //current=current_read[3]*1000+current_read[2]*100+current_read[1]*10+current_read[0];
+                                       //current=mcp3421_read(0);
+                                       current=mcp3421_read(0);
+
+                                       ili9341_setcursor(260,190);
+                                       ili9341_setfont(Arial_10);
+                                       i_to_a(text,current,6);
+                                       ili9341_out(text);
+                                       delay_ms(1);
+                                       //amp_readback=mcp3426_read(0);
+                                       /*
+                                       current_read[0]=0;
+                                       current_read[1]=0;
+
+                                       if(amp_readback>adc[0][9])
+                                       {
+                                               for(i=0;i<10;i++)
+                                               {
+                                                       if((amp_readback>=adc[1][i]) && (amp_readback<adc[1][i+1]))
+                                                       {
+                                                               current_read[1]=i;
+                                                               amp_readback-=adc[1][i];
+                                                       }
+                                               }
+                                       }
+                                       for(i=0;i<10;i++)
+                                       {
+                                               if((amp_readback>=adc[0][i]) && (amp_readback<adc[0][i+1]))
+                                               {
+                                                       current_read[0]=i;
+                                               }
+                                       }
+
+                                       */
+                                       read_adc=0;
+                               }
+
+                               show_voltage(volt);
+                               show_amperes(amperes,step_width);
+                               show_watt((uint32_t)(volt*amperes)/1000);
+                               show_resistance((volt*10)/amperes);
+                               if(!run)
+                               {
+                                       temperature=mcp9808_read();
+                                       show_temperature((uint16_t)(temperature));
+
+
+                               }
+                               //i_to_a(text,((current_read[3]*1000)+(current_read[2]*100)+current_read[1]*10)+current_read[0],5);
+
+                               /*
+                               ili9341_setcursor(240,190);
+                               ili9341_settextcolor(BLACK,LIGHTGREY);
+                               ili9341_settextsize(1);
+                               i_to_a(text,current/1000,2);
+                               ili9341_out(text);
+                               i_to_a(text,current%1000,3);
+                               ili9341_out(".");
+                               ili9341_out(text);
+                               ili9341_out("A");
+                               */
+
+                               show_readbackcurrent(current);
+
+                               if(cutoff_volt!=0)
+                               {
+                                       if(volt<=(cutoff_volt*10))
+                                       {
+                                               run=0;
+                                               //fet_pulldown(null);
+                                               //mcp4728_set_pd(0xaa);
+                                               set_mode=9;
+                                       }
+                               }
+                               else {
+                                       set_mode=0;
+                               }
+                               break;
+
+                       }
+                       //NVIC->ISER[0] |= (1<<(TIM14_IRQn & 0x1f));
+               }
+
+    }
+       return 0;
+}
+
+
+void RCC_Configuration(void)
+{
+       /*
+       RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+    while((RCC->CR & RCC_CR_HSERDY) == 0) {}
+
+    FLASH->ACR |= FLASH_ACR_LATENCY | FLASH_ACR_PRFTBE;
+
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
+
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMUL6);
+
+    RCC->CR |= RCC_CR_PLLON;
+
+    while((RCC->CR & RCC_CR_PLLRDY) == 0) {}
+
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+    while((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) { }
+    */
+
+
+    RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+    while((RCC->CR & RCC_CR_HSERDY) == 0) {}
+
+    FLASH->ACR |= FLASH_ACR_LATENCY | FLASH_ACR_PRFTBE;
+
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE_DIV1;
+
+    if ((RCC->CFGR & RCC_CFGR_SWS) == RCC_CFGR_SWS_PLL)
+    {
+        RCC->CFGR &= (uint32_t) (~RCC_CFGR_SW);
+        while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
+        {
+            // For robust implementation, add here time-out management
+        }
+    }
+    RCC->CR &= (uint32_t)(~RCC_CR_PLLON);
+    while((RCC->CR & RCC_CR_PLLRDY) != 0)
+    {
+    // For robust implementation, add here time-out management
+    }
+    RCC->CFGR = (RCC->CFGR & (~RCC_CFGR_PLLMUL)) | (RCC_CFGR_PLLSRC_HSE_PREDIV) | (RCC_CFGR_PLLMUL6);
+    RCC->CR |= RCC_CR_PLLON;
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    // For robust implementation, add here time-out management
+    }
+    RCC->CFGR |= (uint32_t) (RCC_CFGR_SW_PLL);
+    while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL)
+    {
+    // For robust implementation, add here time-out management
+    }
+
+
+       SystemCoreClockUpdate();
+
+       RCC->AHBENR |= RCC_AHBENR_GPIOAEN;
+       RCC->AHBENR |= RCC_AHBENR_GPIOBEN;
+       RCC->AHBENR |= RCC_AHBENR_GPIOCEN;
+       RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
+       RCC->APB1ENR |= RCC_APB1ENR_I2C1EN;
+    RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
+    RCC->APB1ENR |= RCC_APB1ENR_TIM14EN;
+    RCC->APB2ENR |= RCC_APB2ENR_TIM15EN;
+    RCC->APB2ENR |= RCC_APB2ENR_TIM16EN;
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+    RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
+    RCC->APB2ENR |= RCC_APB2ENR_SYSCFGCOMPEN;
+       //RCC->APB2ENR |= RCC_APB2ENR_IOPAEN;
+    //RCC->APB2ENR |= RCC_APB2ENR_IOPBEN;
+    //RCC->APB2ENR |= RCC_APB2ENR_IOPCEN;
+    //RCC->APB2ENR |= RCC_APB2ENR_AFIOEN;
+    //RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
+    //RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
+    //RCC->APB1ENR |= RCC_APB1ENR_BKPEN;
+    //RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+
+
+    //RCC->APB1ENR |= RCC_APB1ENR_I2C1EN;
+    //RCC->APB1ENR |= RCC_APB1ENR_SPI2EN;
+
+
+}
+
+extern void EXTI2_3_IRQHandler(void)
+{
+       if(EXTI->PR & EXTI_PR_PR3)
+       {
+/*
+               ili9341_setcursor(4, 200);
+               ili9341_settextsize(1);
+               ili9341_out("Interrupt");
+       */
+               keyfunc=0xfd;
+               run=1;
+               EXTI->PR |= EXTI_PR_PR3;
+       }
+}
+
+extern void SPI1_IRQHandler(void)
+{
+    if(SPI1->SR & SPI_SR_TXE)
+    {
+        *(uint8_t *)&(SPI1->DR)=ili9341_buf;
+        //GPIOA->BSRR = CS;
+        SPI1->CR2 &= ~SPI_CR2_TXEIE;
+
+        //GPIOB->BSRR |= GPIO_BSRR_BS_4;
+    }
+}
+
+void I2C1_IRQHandler(void)
+{
+       uint32_t i2c_isr = I2C1->ISR;
+
+       if((i2c_isr & I2C_ISR_ADDR) == I2C_ISR_ADDR)                                                            // detect local I2C address in slave mode
+       {
+               I2C1->ICR |= I2C_ICR_ADDRCF;
+       }
+
+       else if((i2c_isr & I2C_ISR_RXNE) == I2C_ISR_RXNE)                                                       // here we end when a byte was received, clears RXNE
+       {
+               i2c.rx_buf[i2c.buf_cnt]=I2C1->RXDR;
+               i2c.buf_cnt++;
+
+               if(i2c.rx_idx==i2c.buf_cnt)
+               {
+                       I2C1->CR1 &= ~I2C_CR1_RXIE;
+                       i2c.buf_cnt=0;
+
+                       if((I2C1->CR2 & I2C_CR2_AUTOEND) == 0)                                                          // fail-safe I2C STOP if autoend is not set
+                       {
+                               I2C1->CR2 |= I2C_CR2_STOP;
+                       }
+
+                       i2c.state=I2C_RECEIVING_DATA;
+
+               }
+       }
+       else if((i2c_isr & I2C_ISR_TXIS) == I2C_ISR_TXIS)                                                       // here we end after every transmitted byte, clears TXIS
+       {
+               I2C1->TXDR=i2c.tx_buf[i2c.buf_cnt];
+               i2c.buf_cnt++;
+
+               if(i2c.tx_idx==i2c.buf_cnt)
+               {
+                       I2C1->CR1 &= ~I2C_CR1_TXIE;
+                       i2c.state=I2C_SENDING_DATA;
+               }
+       }
+       else if((i2c_isr & I2C_ISR_TC) == I2C_ISR_TC)                                                           // if all bytes are transferred (NBYTES==0) we end here
+       {
+               I2C1->CR1 &= ~I2C_CR1_TCIE;
+               i2c.buf_cnt=0;
+
+               /*
+               if((I2C1->CR2 & I2C_CR2_AUTOEND) == 0)                                                                  // fail-safe I2C STOP if autoend is not set
+               {
+                       I2C1->CR2 |= I2C_CR2_STOP;
+               }
+               */
+       }
+       else
+       {
+
+       }
+
+}
+
+/*
+extern void DMA1_Channel2_3_IRQHandler(void)
+{
+
+    if(DMA1->ISR & DMA_ISR_TCIF2)
+    {
+
+        DMA1_Channel2->CCR &= ~DMA_CCR_EN;
+        DMA1_Channel2->CNDTR = 0;
+        //i2c_stop(I2C1);
+        i2c_transfer_set();
+        //ili9341_out("TX Error");
+        DMA1->IFCR |= DMA_IFCR_CTCIF2;
+    }
+
+    else if(DMA1->ISR & DMA_ISR_TCIF3)
+    {
+        DMA1_Channel3->CCR &= ~(DMA_CCR_EN);
+        DMA1_Channel3->CNDTR = 0;
+        //i2c_stop(I2C1);
+        i2c_transfer_set();
+        DMA1->IFCR |= DMA_IFCR_CTCIF3;
+    }
+    else if(DMA1->ISR & DMA_ISR_TEIF2)
+    {
+        //ili9341_out("TX Error");
+        DMA1->IFCR |= DMA_IFCR_CTEIF2;
+    }
+    else if(DMA1->ISR & DMA_ISR_TEIF3)
+    {
+        //ili9341_out("RX Error");
+        DMA1->IFCR |= DMA_IFCR_CTEIF3;
+    }
+
+}
+*/
+
+
+extern  void TIM16_IRQHandler(void)
+{
+//    NVIC->ISER[0] &= ~(1<<(TIM3_IRQn & 0x1f));
+
+       if(TIM16->SR & TIM_SR_UIF) // if UIF flag is set
+    {
+        int8_t enc_new=0;
+        int8_t enc_diff=0;
+        int8_t enc_temp;
+
+        enc_temp=enc_last;
+
+        enc_new = 0;
+        if( !PHASE_A ) {
+            enc_new = 3; }
+        if( !PHASE_B ) {
+            enc_new ^= 1; }                                     // convert gray to binary
+            enc_diff = enc_last - enc_new;                          // difference last - new
+        if( enc_diff & 1 ) {                            // bit 0 = value (1)
+            enc_last = enc_new; // store new as next last
+            enc_delta += (enc_diff & 2) - 1; }          // bit 1 = direction (+/-)
+        if(enc_temp!=enc_last) {
+            keyfunc=0xfe;
+        }
+
+        if(!KEY) {
+            btn_hb++;
+        }
+        else {
+            if(!btn_hb) {}  // keyfunc==0xfe) { keypress=0; keyfunc=0; }
+            else if(btn_hb<1500) {
+                    keyfunc=0xfd;
+                    btn_hb=0xffff;
+            }
+            else if(btn_hb<3000) {
+                    keyfunc=0xfc;
+                    btn_hb=0xffff;
+            }
+            else if(btn_hb<4500) {
+                       keyfunc=0xf9;
+                       btn_hb=0xffff;
+            }
+            else if(btn_hb<6000) {
+                    keyfunc=0xfb;
+                    btn_hb=0xffff;
+            }
+            else if(btn_hb<7500) {
+                       keyfunc=0xfa;
+                       btn_hb=0xffff;
+            }
+            else if(btn_hb<0xffff) {
+                    keyfunc=0xea;
+                    btn_hb=0xffff;
+            }
+
+        }
+        if(!keyfunc)
+        {
+
+        }
+               TIM16->SR &= ((uint16_t)~(0x1)); // clear UIF flag
+       }
+//    NVIC->ISER[0] &= ~(1<<(TIM3_IRQn & 0x1f));
+
+}
+
+extern  void TIM15_IRQHandler(void)
+{
+       if(TIM15->SR & TIM_SR_UIF) // if UIF flag is set
+    {
+               timeout++;
+
+               TIM15->SR &= ((uint16_t)~(0x1)); // clear UIF flag
+       }
+}
+
+extern  void TIM14_IRQHandler(void)
+{
+       if(TIM14->SR & TIM_SR_UIF) // if UIF flag is set
+    {
+               if(!set_mode)
+               {
+               set_mode=11;
+               read_adc=1;
+                       check_temp=1;
+                       //i2c_device=0;
+                       //i2c_state=I2C_IDLE;
+
+
+               }
+               //GPIOB->ODR ^= GPIO_ODR_12;
+
+               TIM14->SR &= ((uint16_t)~(0x1)); // clear UIF flag
+       }
+}
+
+
+extern void RTC_IRQHandler(void)
+{
+//    NVIC->ISER[0] &= ~(1<<(TIM3_IRQn & 0x1f));
+
+
+       if(RTC->ISR & RTC_ISR_ALRAF) {
+               NVIC->ISER[0] &= ~(1<<(TIM14_IRQn & 0x1f));
+               timer++;
+               //set_mode=4;
+               GPIOB->ODR ^= 0x200;
+               EXTI->PR |= EXTI_PR_PR17;
+               RTC->ISR &= ~(RTC_ISR_ALRAF);
+
+
+
+       }
+//    NVIC->ISER[0] &= ~(1<<(TIM3_IRQn & 0x1f));
+
+}
+
+// ----------------------------------------------------------------------------
diff --git a/src/main.c.bak b/src/main.c.bak

new file mode 100644 (file)

index 0000000..c78b2cb
--- /dev/null
+++ b/src/main.c.bak
@@ -0,0 +1,1343 @@
+/*
+ * Electronic Load by HB9EVI
+ */
+
+// ----------------------------------------------------------------------------
+
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+
+#include <stm32f0xx.h>
+#include <stm32f0xx_conf.h>
+#include <stm32f0xx_rcc.h>
+#include <stm32f0xx_gpio.h>
+#include <stm32f0xx_flash.h>
+#include <stm32f0xx_tim.h>
+#include <stm32f0xx_exti.h>
+#include <stm32f0xx_i2c.h>
+#include <stm32f0xx_pwr.h>
+#include <stm32f0xx_rtc.h>
+
+#include "delay.h"
+#include "ili9341.h"
+#include "ili9341gfx.h"
+
+#include "i2c.h"
+
+#include "mcp24aaxx.h"
+
+//#define PHASE_A (GPIOA->IDR & 0x200)
+//#define PHASE_B (GPIOA->IDR & 0x400)
+//#define KEY (GPIOA->IDR & 0x100)
+
+#define PHASE_A (GPIOB->IDR & 0x2)
+#define PHASE_B (GPIOB->IDR & 0x4)
+#define KEY (GPIOB->IDR & 0x1)
+
+volatile uint16_t btn_hb=0;
+volatile uint8_t set_mode=2;
+volatile uint8_t read_adc=0;
+volatile uint8_t check_temp=1;
+volatile uint8_t keyfunc=0;
+volatile uint8_t enc_event=0;
+volatile int8_t enc_delta;
+volatile uint16_t timer=0;
+volatile uint8_t run=0;
+static int8_t enc_last;
+
+
+
+void RCC_Configuration(void);
+
+GPIO_InitTypeDef  GPIO_InitStructure;
+I2C_InitTypeDef  I2C_InitStructure;
+
+void i_to_a (char *a, uint32_t number, uint8_t count)
+{
+    a += count;
+    *a = '\0';
+
+    while (count--)
+    {
+        *--a = (number % 10) + '0';
+        number /= 10;
+    }
+}
+
+void encode_init( void )
+{
+    int8_t enc_new;
+
+    enc_new = 0;
+    if( PHASE_A )
+        enc_new = 3;
+    if( PHASE_B )
+        enc_new ^= 1;                                 // convert gray to binary
+    enc_last = enc_new;                                    // power on state
+    enc_delta = 0;
+}
+
+int8_t encode_read4( void )  // read four step encoders {
+{
+    int8_t enc_ret;
+
+    enc_ret = enc_delta;
+    enc_delta = enc_ret & 3;
+
+    return enc_ret >> 2;
+}
+
+
+
+void mcp4728_set_reference(uint8_t data)
+{
+
+       data = data & 0xf;
+       data += 0x80;
+
+       i2c_autoend(1);
+       i2c_set_nbytes(1);
+       i2c_write_addr(0x60,WRITE);
+       i2c_write(data);
+       i2c_start();
+       i2c_reset();
+
+}
+
+void mcp4728_set_gain(uint8_t data)
+{
+
+       data = data & 0xf;
+       data += 0xc0;
+
+       i2c_autoend(1);
+       i2c_set_nbytes(1);
+       i2c_write_addr(0x60,WRITE);
+       i2c_write(data);
+       i2c_start();
+       i2c_reset();
+
+}
+
+void mcp4728_set_pd(uint8_t data)
+{
+
+       i2c_autoend(1);
+       i2c_set_nbytes(2);
+       i2c_write_addr(0x60,WRITE);
+       i2c_start();
+       i2c_write(0xa0 + ((data & 0xf0)>>4));
+       i2c_write((data & 0xf)<<4);
+       i2c_reset();
+
+}
+
+void mcp4728_write_dac(uint8_t channel, uint16_t data, uint8_t ref, uint8_t gain)
+{
+
+       uint8_t a=0x58,b,c;
+
+       a += ((channel & 0x3)<<1);
+       b = ((ref & 0x1)<<7);
+       if(gain)
+       {
+               b += 0x10;
+       }
+//     b += ((gain & 0x1)<<4);
+
+       if(!data)
+       {
+               b += 0x20;
+       }
+       b += (uint8_t)((data & 0xf00)>>8);
+       c = (uint8_t)(data & 0xff);
+
+       //i2c_start();
+       i2c_set_nbytes(3);
+       i2c_autoend(1);
+       i2c_write_addr(0x60,WRITE);
+       i2c_start();
+       while(!(I2C1->ISR & I2C_ISR_TXIS));
+       i2c_write(a);
+       i2c_write(b);
+       i2c_write(c);
+       i2c_reset();
+       //i2c_stop();
+
+}
+
+void mcp4728_write_fast_dac(uint16_t  *data)
+{
+
+       uint8_t i;
+       //uint16_t tmp;
+
+       //i2c_start();
+       i2c_autoend(1);
+       i2c_set_nbytes(8);
+       i2c_write_addr(0x60,WRITE);
+       i2c_start();
+       while(!(I2C1->ISR & I2C_ISR_TXIS));
+       for(i=0;i<4;i++)
+       {
+               /*
+               if(!data[i])
+               {
+                       data[i]+=0x1000;
+               }
+               */
+               i2c_write((uint8_t)((data[i] & 0xff00)>>8));
+               i2c_write((uint8_t)(data[i] & 0xff));
+       }
+       i2c_reset();
+       //i2c_stop();
+
+}
+
+void mcp4728_general_update(void)
+{
+/*     i2c_start();
+       i2c_write_addr(0x60,WRITE);
+       i2c_write(0);
+       i2c_write(0x8);
+       i2c_stop();
+*/
+}
+
+void mcp3421_config(uint8_t cnf)
+{
+       i2c_autoend(1);
+       i2c_set_nbytes(1);
+    i2c_write_addr(0x68,WRITE);
+    i2c_write(cnf);
+    i2c_start();
+    //while(!(I2C1->ISR & I2C_ISR_TXIS));
+    //while(!(I2C1->ISR & I2C_ISR_TC));
+
+    i2c_reset();
+}
+
+uint32_t mcp3421_read(void)
+{
+
+       uint32_t tmp;
+    uint8_t status;
+
+    do
+    {
+       tmp=0;
+       i2c_autoend(1);
+       i2c_set_nbytes(4);
+       i2c_write_addr(0x68,READ);
+       i2c_start();
+        tmp=((uint32_t)(i2c_read_ack() & 0x3) << 16);
+        tmp+=((uint32_t)(i2c_read_ack()) << 8);
+        tmp+=i2c_read_ack();
+        status=i2c_read_ack();
+        i2c_reset();
+
+    }
+       while (status & 0x80);
+    if(tmp & 0x20000) {
+       return 0;
+    }
+    else {
+       return tmp;
+    }
+}
+
+uint16_t mcp9808_read(void)
+{
+       uint16_t temp;
+
+       i2c_autoend(0);
+       i2c_set_nbytes(1);
+       i2c_write_addr(0x18,WRITE);
+       i2c_start();
+       while(!(I2C1->ISR & I2C_ISR_TXIS));
+       i2c_write(0x5);
+       while(!(I2C1->ISR & I2C_ISR_TC));
+       i2c_stop();
+       i2c_autoend(1);
+       i2c_set_nbytes(2);
+       i2c_write_addr(0x18,READ);
+       i2c_start();
+       temp=(uint16_t)(i2c_read_ack() & 0xf) << 12;
+       temp+=(uint16_t)(i2c_read_ack() << 4);
+       i2c_reset();
+
+       return temp;
+}
+
+void mcp9808_setalert(uint8_t upper, uint8_t lower, uint8_t crit)
+{
+       i2c_autoend(1);
+       i2c_set_nbytes(3);
+       i2c_write_addr(0x18,WRITE);
+       i2c_start();
+       while(!(I2C1->ISR & I2C_ISR_TXIS));
+       i2c_write(0x1);
+       i2c_write(0x0);
+       i2c_write(0x1c);
+       i2c_reset();
+
+       i2c_autoend(1);
+       i2c_set_nbytes(3);
+       i2c_write_addr(0x18,WRITE);
+       i2c_start();
+       while(!(I2C1->ISR & I2C_ISR_TXIS));
+       i2c_write(0x2);
+       i2c_write((uint8_t)((upper & 0xf0)>>4));
+       i2c_write((uint8_t)((upper & 0xf)<<4));
+       i2c_reset();
+
+       i2c_autoend(1);
+       i2c_set_nbytes(3);
+       i2c_write_addr(0x18,WRITE);
+       i2c_start();
+       while(!(I2C1->ISR & I2C_ISR_TXIS));
+       i2c_write(0x3);
+       i2c_write((uint8_t)((lower & 0xf0)>>4));
+       i2c_write((uint8_t)((lower & 0xf)<<4));
+       i2c_reset();
+
+       i2c_autoend(1);
+       i2c_set_nbytes(3);
+       i2c_write_addr(0x18,WRITE);
+       i2c_start();
+       while(!(I2C1->ISR & I2C_ISR_TXIS));
+       i2c_write(0x4);
+       i2c_write((uint8_t)((crit & 0xf0)>>4));
+       i2c_write((uint8_t)((crit & 0xf)<<4));
+       i2c_reset();
+
+}
+
+void show_amperes(uint16_t amperes) {
+       uint8_t tmp1;
+       uint16_t tmp2;
+       char text[4];
+
+       tmp1=amperes/1000;
+       tmp2=amperes%1000;
+       ili9341_setcursor(4,30);
+       ili9341_settextsize(4);
+       ili9341_settextcolour(RED,BLACK);
+       i_to_a(text,tmp1,2);
+       ili9341_out(" ");
+       ili9341_out(text);
+       ili9341_out(".");
+       i_to_a(text,tmp2,3);
+       ili9341_out(text);
+       ili9341_out("A");
+}
+
+void show_voltage(uint16_t volt) {
+       uint8_t tmp1;
+       uint16_t tmp2;
+       char text[4];
+
+       tmp1=volt/1000;
+       tmp2=volt%1000;
+       ili9341_setcursor(4,75);
+       ili9341_settextsize(4);
+       ili9341_settextcolour(DARKGREEN,BLACK);
+       i_to_a(text,tmp1,3);
+       ili9341_out(text);
+       ili9341_out(".");
+       i_to_a(text,tmp2,3);
+       ili9341_out(text);
+       ili9341_out("V");
+}
+
+void show_dec_mark(uint16_t dec) {
+
+//     ili9341_setcursor(4,41);
+//     ili9341_settextsize(4);
+//     ili9341_settextcolour(RED,BLACK);
+       ili9341_drawhline(4,63,180,BLACK);
+       switch(dec)
+       {
+       case 1:
+               //ili9341_out("      _");
+               ili9341_drawhline(148,63,20,RED);
+               break;
+       case 10:
+               //ili9341_out("     _ ");
+               ili9341_drawhline(124,63,20,RED);
+               break;
+       case 100:
+               //ili9341_out("    _  ");
+               ili9341_drawhline(100,63,20,RED);
+               break;
+       case 1000:
+               //ili9341_out(" _     ");
+               ili9341_drawhline(28,63,44,RED);
+               break;
+       }
+}
+
+void show_status(uint8_t stat)
+{
+       if(stat)
+       {
+               ili9341_fillrect(204,16,116,49,RED);
+               ili9341_setcursor(220,32);
+               ili9341_settextcolour(WHITE,RED);
+               ili9341_settextsize(2);
+               ili9341_out("Running");
+       }
+       else
+       {
+               ili9341_fillrect(204,16,116,49,DARKGREEN);
+               ili9341_setcursor(220,32);
+               ili9341_settextcolour(WHITE,DARKGREEN);
+               ili9341_settextsize(2);
+               ili9341_out("Standby");
+       }
+}
+
+void show_watt(uint32_t watt) {
+       uint8_t tmp1;
+       uint16_t tmp2;
+       char text[4];
+
+       tmp1=watt/1000;
+       tmp2=watt%1000;
+       ili9341_setcursor(4,115);
+       ili9341_settextsize(4);
+       ili9341_settextcolour(GOLD,BLACK);
+       i_to_a(text,tmp1,3);
+       ili9341_out(text);
+       ili9341_out(".");
+       i_to_a(text,tmp2,3);
+       ili9341_out(text);
+       ili9341_out("W");
+}
+
+void show_resistance(uint32_t resistance) {
+       uint8_t tmp1;
+       uint16_t tmp2;
+       char text[5];
+
+       if((resistance>99999) || (resistance==0) )
+       {
+               ili9341_setcursor(4,155);
+               ili9341_settextsize(4);
+               ili9341_settextcolour(BLUE,BLACK);
+               ili9341_out("     ");
+               ili9341_write(0x82);
+               ili9341_out(" ");
+               ili9341_write(0x81);
+       }
+       else
+       {
+               ili9341_setcursor(4,155);
+               ili9341_settextsize(4);
+               ili9341_settextcolour(BLUE,BLACK);
+               tmp1=resistance%10;
+               tmp2=resistance/10;
+               i_to_a(text,tmp2,4);
+               ili9341_out(" ");
+               ili9341_out(text);
+               ili9341_out(".");
+               i_to_a(text,tmp1,1);
+               ili9341_out(text);
+               ili9341_write(0x81);
+       //ili9341_out(0x81);
+
+       }
+}
+
+void show_temperature(uint16_t temperature) {
+
+       uint16_t tmp1,tmp2;
+       char text[5];
+
+       tmp1 = (temperature & 0xff00)>>8;
+       tmp2 = (temperature & 0xf0) >> 4;
+       ili9341_setcursor(210,142);
+       ili9341_settextsize(2);
+       ili9341_settextcolour(RED,LIGHTGREY);
+       i_to_a(text,tmp1,3);
+       ili9341_out("  ");
+       ili9341_out(text);
+       ili9341_out(".");
+       tmp1=0;
+       if(tmp2 & 0x8) {
+               tmp1+=5000;
+       }
+       if(tmp2 & 0x4) {
+               tmp1+=2500;
+       }
+       if(tmp2 & 0x2) {
+               tmp1+=1250;
+       }
+       if(tmp2 & 0x1) {
+               tmp1+=625;
+       }
+       i_to_a(text,tmp1/1000,1);
+       ili9341_out(text);
+       ili9341_write(0x83);
+       ili9341_out("C");
+}
+
+uint8_t bcd_to_epphex(uint8_t nmb)
+{
+       uint8_t o_0,d_1;
+
+       o_0=nmb%10;
+       d_1=(nmb-o_0)/10;
+       d_1*=0x10;
+       d_1+=(o_0*2);
+
+       return d_1;
+
+}
+
+void fet_pulldown(uint16_t *data)
+{
+       uint8_t i;
+       uint16_t t=0x100;
+
+       for(i=0;i<4;i++)
+       {
+               if(!data[i])
+               {
+                       GPIOA->BSRR = (uint32_t)(t<<i);
+
+               }
+               else
+               {
+                       GPIOA->BRR = (uint32_t)(t<<i);
+               }
+               /*
+                       if(i==0) {
+                       ili9341_setcursor(4,200);
+                       i_to_a(text,data[i],5);
+                       ili9341_out(text);
+               }
+               */
+       }
+}
+
+
+int main(void)
+{
+
+       uint8_t init=1;
+       float volt=0;
+       uint16_t amperes=0;
+       uint8_t menu=0;
+       uint8_t calib=0;
+       uint8_t set_volt=0;
+       uint32_t cutoff_volt=0;
+       uint8_t i,j,m=0,s=0,h=0;
+       uint8_t step_width=0;
+       uint16_t factor=1;
+       float wh=0,ah=0;
+       uint16_t t1_16,t2_16;
+       uint32_t t1_32;
+       uint16_t t_clb=0;
+       uint16_t dac[4][21];
+       uint16_t dac_val[4] = { 0,0,0,0 };
+       uint16_t null[4] = { 0x0,0x0,0x0,0x0 };
+       uint16_t temperature=0;
+       char text[6];
+       float flt1, flt2;
+
+       RCC_Configuration();
+
+       delay_init();
+
+       RCC->APB1RSTR |=  RCC_APB1RSTR_I2C1RST;
+       RCC->APB1RSTR &= ~RCC_APB1RSTR_I2C1RST;
+
+    i2c_init();
+
+    /*
+     * 0,1,2 Encoder; 3 MCP9808 Interrupt;
+     */
+
+    //GPIOA->MODER = 0x2855a955;
+    GPIOA->MODER |= GPIO_MODER_MODER0_0 | GPIO_MODER_MODER1_0 | GPIO_MODER_MODER2_0 | GPIO_MODER_MODER3_0 | GPIO_MODER_MODER4_0 |
+                               GPIO_MODER_MODER5_1 | GPIO_MODER_MODER6_1 | GPIO_MODER_MODER7_1 | GPIO_MODER_MODER8_0 | GPIO_MODER_MODER9_0 |
+                                       GPIO_MODER_MODER10_0 | GPIO_MODER_MODER11_0;
+
+    //GPIOA->OSPEEDR = 0xffffffff;
+    GPIOA->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR0 | GPIO_OSPEEDER_OSPEEDR1 | GPIO_OSPEEDER_OSPEEDR2 | GPIO_OSPEEDER_OSPEEDR3 |
+                                 GPIO_OSPEEDER_OSPEEDR4 | GPIO_OSPEEDER_OSPEEDR5 | GPIO_OSPEEDER_OSPEEDR6 | GPIO_OSPEEDER_OSPEEDR7 |
+                                         GPIO_OSPEEDER_OSPEEDR8 | GPIO_OSPEEDER_OSPEEDR9 | GPIO_OSPEEDER_OSPEEDR10 | GPIO_OSPEEDER_OSPEEDR11;
+
+    //GPIOA->PUPDR = 0x41000000;
+    GPIOA->PUPDR |= GPIO_PUPDR_PUPDR12_0 | GPIO_PUPDR_PUPDR15_0;
+    GPIOA->AFR[0] = 0x0;
+
+    GPIOB->MODER = 0x0001a200;
+    //GPIOB->MODER |= GPIO_MODER_MODER4_1 | GPIO_MODER_MODER6_1 | GPIO_MODER_MODER7_1 | GPIO_MODER_MODER8_0;
+    GPIOB->OTYPER = 0x000000c0;
+    //GPIOB->OTYPER |= GPIO_OTYPER_OT_6 | GPIO_OTYPER_OT_7;
+    GPIOB->OSPEEDR = 0xffffffff;
+    //GPIOB->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR4 | GPIO_OSPEEDER_OSPEEDR6 | GPIO_OSPEEDER_OSPEEDR7 | GPIO_OSPEEDER_OSPEEDR8;
+    GPIOB->PUPDR = 0x00005055;
+    //GPIOB->PUPDR |= GPIO_PUPDR_PUPDR0_0 | GPIO_PUPDR_PUPDR1_0 | GPIO_PUPDR_PUPDR2_0 | GPIO_PUPDR_PUPDR3_0 |
+    //                         GPIO_PUPDR_PUPDR6_0 | GPIO_PUPDR_PUPDR7_0;
+    GPIOB->AFR[0] = 0x11010000;
+
+    //SPI1->CR1 = 0x304;
+    SPI1->CR1 |= SPI_CR1_MSTR | SPI_CR1_SSI | SPI_CR1_SSM;
+    SPI1->CR2 = 0x1700;
+    SPI1->CR1 |= SPI_CR1_SPE;
+
+
+    TIM3->PSC = 7;
+    TIM3->ARR = 250;
+    TIM3->CCR1 = 0;
+    TIM3->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1PE;
+       TIM3->CCER |= TIM_CCER_CC1E | TIM_CCER_CC1P;
+    TIM3->BDTR |= TIM_BDTR_MOE;
+    TIM3->CR1 |=  TIM_CR1_CEN; // | TIM_CR1_CMS_0; // | TIM_CR1_DIR;
+    TIM3->EGR |= TIM_EGR_UG;
+
+    TIM14->PSC = 374;                 // Timer14 500ms
+    TIM14->ARR = 63999;
+    TIM14->CR1 |= TIM_CR1_URS;
+    TIM14->DIER |= TIM_DIER_UIE;
+    TIM14->CR1 |= (TIM_CR1_CEN);
+
+
+    TIM16->PSC = 0;                                      // Timer3 500uS
+    TIM16->ARR = 23999; //18001;
+    //TIM3->CR1 |= TIM_CR1_URS;
+    TIM16->DIER |= TIM_DIER_UIE;
+    TIM16->CR1 |= (TIM_CR1_CEN);
+
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+    PWR->CR |= PWR_CR_DBP;
+
+    RCC->BDCR |= RCC_BDCR_BDRST;
+    RCC->BDCR &= ~(RCC_BDCR_BDRST);
+
+    PWR->CR |= PWR_CR_DBP;
+
+    RCC->BDCR &= ~(RCC_BDCR_LSEBYP);
+    RCC->BDCR |= RCC_BDCR_LSEON;                                       // enable LSE
+    while((RCC->BDCR & RCC_BDCR_LSERDY)==0);
+
+    RCC->BDCR |= RCC_BDCR_RTCSEL_LSE;                          // LSE clock source select
+    RCC->BDCR |= RCC_BDCR_RTCEN;                                       // RTC enable
+
+    RTC->WPR = 0xca;
+       RTC->WPR = 0x53;
+    /* Reset TR, DR and CR registers */
+    RTC->TR        = (uint32_t)0x00000000;
+    RTC->WUTR      = (uint32_t)0x0000FFFF;
+    RTC->DR        = (uint32_t)0x00002101;
+    RTC->CR        &= (uint32_t)0x00000000;
+    RTC->PRER      = (uint32_t)0x007F00FF;
+    RTC->ALRMAR    = (uint32_t)0x00000000;
+    RTC->SHIFTR    = (uint32_t)0x00000000;
+    RTC->CALR       = (uint32_t)0x00000000;
+    RTC->ALRMASSR  = (uint32_t)0x00000000;
+
+    /* Reset ISR register and exit initialization mode */
+    RTC->ISR = (uint32_t)0x00000000;
+
+    /* Reset Tamper and alternate functions configuration register */
+    RTC->TAFCR = 0x00000000;
+
+    RTC->WPR = 0xff;
+
+    //RCC->APB1ENR &= ~RCC_APB1ENR_PWREN;
+    PWR->CR |= PWR_CR_DBP;
+
+    RTC->WPR = 0xca;
+    RTC->WPR = 0x53;
+    //RTC->ISR |= RTC_ISR_INIT;
+    RTC->CR &= ~RTC_CR_ALRAE;
+    while(!(RTC->ISR & RTC_ISR_ALRAWF));
+    RTC->ALRMAR = 0x80808080;
+    RTC->CR |= RTC_CR_ALRAIE | RTC_CR_ALRAE; // | RTC_CR_COE | RTC_CR_COSEL; // | RTC_CR_OSEL_1;
+    RTC->WPR = 0xff;
+    //RTC->WPR = 0x64;
+
+    RTC->WPR = 0xca;
+    RTC->WPR = 0x53;
+
+    RTC->ISR |= RTC_ISR_INIT;
+    while((RTC->ISR & RTC_ISR_INITF)!=RTC_ISR_INITF);
+    RTC->TR = 0x0;
+    RTC->ISR &=~ RTC_ISR_INIT;
+    while((RTC->ISR & RTC_ISR_RECALPF) == RTC_ISR_RECALPF);
+    RTC->WPR = 0xff;
+    EXTI->IMR |= EXTI_IMR_MR17;
+    EXTI->RTSR |= EXTI_RTSR_TR17;
+
+
+      RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+
+
+      SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI3_PB;
+      EXTI->IMR |= EXTI_IMR_MR3;
+      EXTI->EMR |= EXTI_EMR_MR3;
+      EXTI->FTSR |= EXTI_FTSR_TR3;
+
+    NVIC->ISER[0] |= (1<<(TIM16_IRQn & 0x1f));
+    //NVIC->ISER[0] |= (1<<(RTC_IRQn & 0x1f));
+
+
+    encode_init();
+
+    delay_ms(50);
+    ili9341_init();
+    /*
+    mcp24aa32_write_word(0x1e00,0);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e02,200);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e04,400);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e06,600);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e08,800);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e0a,1000);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e0c,1200);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e0e,1400);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e10,1600);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e12,1800);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e14,2000);
+       delay_ms(50);
+    mcp24aa32_write_word(0x1e16,2200);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e18,2400);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e1a,2600);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e1c,2800);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e1e,3000);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e20,3200);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e22,3400);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e24,3600);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e26,3800);
+    delay_ms(50);
+    mcp24aa32_write_word(0x1e28,4000);
+*/
+
+    ili9341_clear(BLACK);
+    ili9341_setRotation(3);
+    ili9341_setcursor(80,4);
+    ili9341_settextsize(1);
+    ili9341_settextcolour(ORANGE,BLACK);
+    ili9341_out("Electronic Load by HB9EVI");
+    ili9341_drawhline(0,15,360,WHITE);
+    ili9341_drawvline(203,15,185,WHITE);
+    ili9341_drawhline(203,65,122,WHITE);
+    ili9341_drawhline(203,200,122,WHITE);
+    ili9341_fillrect(204,66,116,134,LIGHTGREY);
+
+
+       for(j=0;j<4;j++)
+       {
+               for(i=0;i<21;i++)
+               {
+                       dac[j][i]=mcp24aa32_read_word((0x100*j)+(i*2));
+               }
+       }
+       GPIOB->BRR=0x100;
+       mcp4728_set_gain(0x0);
+       mcp4728_set_reference(0xf);
+       delay_ms(1);
+       mcp3421_config(0x1c);
+       delay_ms(1);
+       mcp4728_write_fast_dac(dac_val);
+       fet_pulldown(null);
+       mcp9808_setalert(28,40,75);
+
+       while (1)
+    {
+               //if(check_temp)
+               //{
+                       t1_16=((temperature & 0xff00)>>8);
+                       if(t1_16>=30)
+                       {
+                               TIM3->CCR1 = (t1_16-30)*10;
+                       }
+                       else {
+                               TIM3->CCR1 = 0;
+                       }
+                       //check_temp=0;
+               //}
+               if(btn_hb)
+               {
+            ili9341_setcursor(4,215);
+            ili9341_settextsize(2);
+            ili9341_settextcolour(WHITE,BLACK);
+            if(btn_hb<2000) {
+                    ili9341_out("Toggle ON/OFF     ");
+            }
+            else if(btn_hb<4000) {
+                    ili9341_out("Set Step Width    ");
+            }
+            else if(btn_hb<6000) {
+                       ili9341_out("Set Cutoff Voltage");
+            }
+            else if(btn_hb<8000) {
+                    ili9341_out("Reset Counters    ");
+            }
+            else if(btn_hb<10000) {
+                       ili9341_out("Store Parameters  ");
+            }
+            else if(btn_hb<0xffff) {
+                       ili9341_out("Calibration       ");
+            }
+               }
+
+               if(keyfunc)
+               {
+                       switch(keyfunc)
+                       {
+                       case 0xfe:                                                              // rotary encoder
+                               if(!calib && !set_volt)
+                               {
+                                       amperes+=(encode_read4()*factor);
+                                       if(amperes>=21000) {
+                                               amperes=0;
+                                       }
+                                       set_mode=2;
+
+                               }
+                               else if(set_volt)
+                               {
+                                       cutoff_volt+=(encode_read4()*factor);
+                                       if(cutoff_volt>10000) {
+                                               cutoff_volt=0;
+                                       }
+                                       set_mode=6;
+
+                               }
+                               else
+                               {
+                                       t_clb+=encode_read4();
+                                       set_mode=10;
+                               }
+                               break;
+                       case 0xfd:
+                               if(calib)                                                       // calculate new eeprom values from calibration
+                               {
+                                       if(factor==100) {
+                                               flt1=(float)mcp24aa32_read_word(0x1e00 +((amperes/factor)%10)*2);
+                                       }
+                                       else if(factor==1000) {
+                                               flt1=(float)mcp24aa32_read_word(0x1e00 +((amperes/factor)%100)*2);
+                                       }
+                                       else {
+                                               flt1=(float)mcp24aa32_read_word(0x1f00 +((amperes/factor)%10)*2);
+                                       }
+                                       flt2=(float)(t_clb);
+                                       flt2/=1000;
+                                       flt1/=flt2;
+                                       if(amperes>9999) {
+                                               flt1*=(float)((amperes/factor)%100);
+                                               flt1/=10;
+                                       }
+                                       else {
+                                               flt1*=(float)((amperes/factor)%10);
+                                       }
+                                       i_to_a(text,(uint16_t)(flt1),4);
+                                       ili9341_setcursor(230,210);
+                                       ili9341_settextsize(3);
+                                       ili9341_out(text);
+                                       if(factor==1000) {
+                                               mcp24aa32_write_word((0x100*step_width) + (((amperes/factor)%100)*2),(uint16_t)(flt1));
+                                               dac[step_width][(amperes/factor)%100]=(uint16_t)(flt1);
+                                       }
+                                       else {
+                                               mcp24aa32_write_word((0x100*step_width) + (((amperes/factor)%10)*2),(uint16_t)(flt1));
+                                               dac[step_width][(amperes/factor)%10]=(uint16_t)(flt1);
+                                       }
+                                       delay_ms(50);
+                                       GPIOB->BRR=0x100;
+                                       calib=0;
+                                       set_mode=2;
+                               }
+                               else if(set_volt) {
+                                       set_volt=0;
+                                       set_mode=2;
+                               }
+                               else                                                                    // outside calibration just toggle load on/off
+                               {
+                                       run^=1;
+                                       set_mode=9;
+                               }
+
+                               break;
+                       case 0xfc:                                                      // set step width
+                               step_width++;
+                               factor*=10;
+                               if(step_width==4)
+                               {
+                                       factor=1;
+                                       step_width=0;
+                               }
+                               set_mode=5;
+                               break;
+
+                       case 0xfb:                                                      // reset wh/ah counters
+                               wh=0;
+                               ah=0;
+                               s=0;
+                               m=0;
+                               h=0;
+                               set_mode=4;
+                               break;
+                       case 0xf9:
+                               set_volt=1;
+                               set_mode=6;
+                               break;
+                       case 0xea:                                                      // calibration mode
+                               calib=1;
+                               if(amperes>9999) {
+                                       t_clb=amperes/10;
+                               }
+                               else {
+                                       t_clb=amperes*(1000/factor);
+                               }
+                               dac_val[0]=0;
+                               dac_val[1]=0;
+                               dac_val[2]=0;
+                               dac_val[3]=0;
+                               if(factor==100) {
+                                       dac_val[step_width]=mcp24aa32_read_word(0x1e00 +((amperes/factor)%10)*2);
+                               }
+                               else if(factor==1000) {
+                                       dac_val[step_width]=mcp24aa32_read_word(0x1e00 +((amperes/factor)%100)*2);
+                               }
+                               else {
+                                       dac_val[step_width]=mcp24aa32_read_word(0x1f00 +((amperes/factor)%10)*2);
+                               }
+                               mcp4728_write_fast_dac(dac_val);
+                               fet_pulldown(dac_val);
+                               GPIOB->BSRR=0x100;
+                               set_mode=10;
+                               break;
+                       }
+
+            if(!menu) {
+                    ili9341_fillrect(4,215,225,25,BLACK);
+            }
+            keyfunc=0;
+            btn_hb=0;
+
+               }
+
+               if(set_mode)
+               {
+                       switch(set_mode)
+                       {
+                       case 2:                                                         // adjust DAC
+                               show_amperes(amperes);
+                               show_dec_mark(factor);
+                               dac_val[0]=dac[0][amperes%10];
+                               dac_val[1]=dac[1][(amperes/10)%10];
+                               dac_val[2]=dac[2][(amperes/100)%10];
+                               dac_val[3]=dac[3][(amperes/1000)%100];
+
+                               mcp4728_write_fast_dac(dac_val);
+
+                               if(run) {
+                                       fet_pulldown(dac_val);
+                                       mcp4728_set_pd(0x0);
+                               }
+                               else {
+                                       fet_pulldown(null);
+                                       mcp4728_set_pd(0xaa);
+                               }
+
+                               if (init) {
+                                       set_mode=4;
+                               }
+                               else {
+                                       set_mode=0;
+                               }
+                               break;
+                       case 4:
+                               if(s==60) {
+                                       m++;
+                                       s=0;
+                               }
+                               if(m==60) {
+                                       h++;
+                                       m=0;
+                               }
+                               if(h==100) {
+                                       h=0;
+                               }
+                               t1_32=(uint32_t)wh;
+                               t1_16=t1_32%1000;
+                               t2_16=t1_32/1000;
+                               ili9341_setcursor(210,75);
+                               ili9341_settextsize(2);
+                               ili9341_settextcolour(LIGHTBLUE,LIGHTGREY);
+                               i_to_a(text,t2_16,3);
+                               ili9341_out(text);
+                               ili9341_out(".");
+                               i_to_a(text,t1_16,3);
+                               ili9341_out(text);
+                               ili9341_out("Wh ");
+                               ili9341_setcursor(210,97);
+                               ili9341_settextcolour(DARKCYAN,LIGHTGREY);
+                               t1_32=(uint32_t)ah;
+                               t1_16=t1_32%1000;
+                               t2_16=t1_32/1000;
+                               i_to_a(text,t2_16,2);
+                               ili9341_out(" ");
+                               ili9341_out(text);
+                               ili9341_out(".");
+                               i_to_a(text,t1_16,3);
+                               ili9341_out(text);
+                               ili9341_out("Ah");
+                               ili9341_setcursor(210,119);
+                               ili9341_settextcolour(BLACK,LIGHTGREY);
+                               i_to_a(text,h,2);
+                               ili9341_out(" ");
+                               ili9341_out(text);
+                               ili9341_out(":");
+                               i_to_a(text,m,2);
+                               ili9341_out(text);
+                               ili9341_out(":");
+                               i_to_a(text,s,2);
+                               ili9341_out(text);
+                               temperature=mcp9808_read();
+                               show_temperature((uint16_t)(temperature));
+
+                               if(init) {
+                                       set_mode=5;
+                               }
+                               else {
+                                       ah+=(amperes/(float)3600);
+                                       wh+=((amperes*(float)(volt/1000))/3600);
+                                       s++;
+                                       set_mode=0;
+
+                               }
+                               break;
+                       case 5:
+                               show_dec_mark(factor);
+                               if(init) {
+                                       set_mode=6;
+                               }
+                               else {
+                                       set_mode=0;
+                               }
+                               break;
+                       case 6:
+                               ili9341_setcursor(230,175);
+                               ili9341_settextsize(2);
+                               ili9341_settextcolour(DARKGREEN,LIGHTGREY);
+                               t1_16=cutoff_volt/100;
+                               i_to_a(text,t1_16,3);
+                               ili9341_out(text);
+                               ili9341_out(".");
+                               t1_16=cutoff_volt%100;
+                               i_to_a(text,t1_16,2);
+                               ili9341_out(text);
+                               ili9341_out("V");
+                               if(init) {
+                                       set_mode=9;
+                               }
+                               else {
+                                       set_mode=0;
+                               }
+                               break;
+                       case 9:
+                               if(run)
+                               {
+                                       EXTI->PR |= EXTI_PR_PR17;
+                                       RTC->ISR &= ~(RTC_ISR_ALRAF);
+                                       EXTI->IMR |= EXTI_IMR_MR17; /* (13) */
+                                       EXTI->RTSR |= EXTI_RTSR_TR17;
+                                       NVIC->ISER[0] |= (1<<(RTC_IRQn & 0x1f));
+                                       mcp4728_set_pd(0x0);
+                                       fet_pulldown(dac_val);
+                               }
+                               else
+                               {
+                                       EXTI->IMR &= ~EXTI_IMR_MR17; /* (13) */
+                                       EXTI->RTSR &= ~EXTI_RTSR_TR17;
+                                       NVIC->ISER[0] &= ~(1<<(RTC_IRQn & 0x1f));
+                                       EXTI->PR |= EXTI_PR_PR17;
+                                       RTC->ISR &= ~(RTC_ISR_ALRAF);
+                                       mcp4728_set_pd(0xaa);
+                                       fet_pulldown(null);
+                               }
+                               show_status(run);
+                               if(init) {
+                                       init=0;
+                                   NVIC->ISER[0] |= (1<<(TIM14_IRQn & 0x1f));
+                                   NVIC->ISER[0] |= (1<<(EXTI2_3_IRQn & 0x1f));
+                               }
+                               set_mode=0;
+                               break;
+                       case 10:
+
+                               ili9341_setcursor(230,210);
+                               ili9341_settextsize(3);
+                               ili9341_settextcolour(WHITE,BLACK);
+                               i_to_a(text,t_clb,4);
+                               ili9341_out(text);
+                               break;
+                       case 11:                                                                // read ADC values
+                               if(read_adc)
+                               {
+                                       volt=(float)(mcp3421_read());
+                                       volt*=0.8055; //0.7856;
+                                       show_voltage((uint32_t)(volt));
+                                       show_amperes(amperes);
+                                       show_watt((uint32_t)((uint32_t)(volt)*amperes)/1000);
+                                       show_resistance((volt*10)/amperes);
+                                       if(!run) {
+                                       temperature=mcp9808_read();
+                                       show_temperature((uint16_t)(temperature));
+                                       }
+                                       if(cutoff_volt!=0)
+                                       {
+                                               if(volt<=(cutoff_volt*10))
+                                               {
+                                                       run=0;
+                                                       //fet_pulldown(null);
+                                                       //mcp4728_set_pd(0xaa);
+                                                       set_mode=9;
+                                               }
+                                       }
+                                       else {
+                                               set_mode=0;
+                                       }
+                                       read_adc=0;
+                               }
+                               break;
+
+                       }
+
+               }
+
+    }
+       return 0;
+}
+
+
+void RCC_Configuration(void)
+{
+
+       /*
+       RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+    while((RCC->CR & RCC_CR_HSERDY) == 0) {}
+
+    FLASH->ACR |= FLASH_ACR_LATENCY | FLASH_ACR_PRFTBE;
+
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
+
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMUL6);
+
+    RCC->CR |= RCC_CR_PLLON;
+
+    while((RCC->CR & RCC_CR_PLLRDY) == 0) {}
+
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+    while((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) { }
+       */
+
+
+    //RCC->CR |= ((uint32_t)RCC_CR_HSEBYP);
+    RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+    while((RCC->CR & RCC_CR_HSERDY) == 0) {}
+
+    FLASH->ACR |= FLASH_ACR_LATENCY | FLASH_ACR_PRFTBE;
+
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE_DIV1;
+
+    if ((RCC->CFGR & RCC_CFGR_SWS) == RCC_CFGR_SWS_PLL)
+    {
+       RCC->CFGR &= (uint32_t) (~RCC_CFGR_SW);
+       while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
+       {
+            // For robust implementation, add here time-out management
+       }
+    }
+    RCC->CR &= (uint32_t)(~RCC_CR_PLLON);
+    while((RCC->CR & RCC_CR_PLLRDY) != 0)
+    {
+    // For robust implementation, add here time-out management
+    }
+    RCC->CFGR = (RCC->CFGR & (~RCC_CFGR_PLLMUL)) | (RCC_CFGR_PLLSRC_HSE_PREDIV) | (RCC_CFGR_PLLMUL6);
+    RCC->CR |= RCC_CR_PLLON;
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    // For robust implementation, add here time-out management
+    }
+    RCC->CFGR |= (uint32_t) (RCC_CFGR_SW_PLL);
+    while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL)
+    {
+    // For robust implementation, add here time-out management
+    }
+
+
+       SystemCoreClockUpdate();
+
+       RCC->AHBENR |= RCC_AHBENR_GPIOAEN;
+       RCC->AHBENR |= RCC_AHBENR_GPIOBEN;
+       RCC->AHBENR |= RCC_AHBENR_GPIOCEN;
+       RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
+       RCC->APB1ENR |= RCC_APB1ENR_I2C1EN;
+    RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
+    RCC->APB1ENR |= RCC_APB1ENR_TIM14EN;
+    RCC->APB2ENR |= RCC_APB2ENR_TIM16EN;
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+    RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
+    RCC->APB2ENR |= RCC_APB2ENR_SYSCFGCOMPEN;
+       //RCC->APB2ENR |= RCC_APB2ENR_IOPAEN;
+    //RCC->APB2ENR |= RCC_APB2ENR_IOPBEN;
+    //RCC->APB2ENR |= RCC_APB2ENR_IOPCEN;
+    //RCC->APB2ENR |= RCC_APB2ENR_AFIOEN;
+    //RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
+    //RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
+    //RCC->APB1ENR |= RCC_APB1ENR_BKPEN;
+    //RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+
+
+    //RCC->APB1ENR |= RCC_APB1ENR_I2C1EN;
+    //RCC->APB1ENR |= RCC_APB1ENR_SPI2EN;
+
+
+}
+
+extern void EXTI2_3_IRQHandler(void)
+{
+       if(EXTI->PR & EXTI_PR_PR3)
+       {
+/*
+               ili9341_setcursor(4, 200);
+               ili9341_settextsize(1);
+               ili9341_out("Interrupt");
+       */
+               keyfunc=0xfd;
+               run=1;
+               EXTI->PR |= EXTI_PR_PR3;
+       }
+}
+
+extern  void TIM16_IRQHandler(void)
+{
+//    NVIC->ISER[0] &= ~(1<<(TIM3_IRQn & 0x1f));
+
+       if(TIM16->SR & TIM_SR_UIF) // if UIF flag is set
+    {
+        int8_t enc_new=0;
+        int8_t enc_diff=0;
+        int8_t enc_temp;
+
+        enc_temp=enc_last;
+
+        enc_new = 0;
+        if( !PHASE_A ) {
+            enc_new = 3; }
+        if( !PHASE_B ) {
+            enc_new ^= 1; }                                     // convert gray to binary
+            enc_diff = enc_last - enc_new;                          // difference last - new
+        if( enc_diff & 1 ) {                            // bit 0 = value (1)
+            enc_last = enc_new; // store new as next last
+            enc_delta += (enc_diff & 2) - 1; }          // bit 1 = direction (+/-)
+        if(enc_temp!=enc_last) {
+            keyfunc=0xfe;
+        }
+
+        if(!KEY) {
+            btn_hb++;
+        }
+        else {
+            if(!btn_hb) {}  // keyfunc==0xfe) { keypress=0; keyfunc=0; }
+            else if(btn_hb<2000) {
+                    keyfunc=0xfd;
+                    btn_hb=0xffff;
+            }
+            else if(btn_hb<4000) {
+                    keyfunc=0xfc;
+                    btn_hb=0xffff;
+            }
+            else if(btn_hb<6000) {
+                       keyfunc=0xf9;
+                       btn_hb=0xffff;
+            }
+            else if(btn_hb<8000) {
+                    keyfunc=0xfb;
+                    btn_hb=0xffff;
+            }
+            else if(btn_hb<10000) {
+                       keyfunc=0xfa;
+                       btn_hb=0xffff;
+            }
+            else if(btn_hb<0xffff) {
+                    keyfunc=0xea;
+                    btn_hb=0xffff;
+            }
+
+        }
+        if(!keyfunc)
+        {
+
+        }
+               TIM16->SR &= ((uint16_t)~(0x1)); // clear UIF flag
+       }
+//    NVIC->ISER[0] &= ~(1<<(TIM3_IRQn & 0x1f));
+
+}
+
+
+extern  void TIM14_IRQHandler(void)
+{
+       if(TIM14->SR & TIM_SR_UIF) // if UIF flag is set
+    {
+                               set_mode=11;
+                               read_adc=1;
+                               check_temp=1;
+
+
+               TIM14->SR &= ((uint16_t)~(0x1)); // clear UIF flag
+       }
+}
+
+
+extern void RTC_IRQHandler(void)
+{
+//    NVIC->ISER[0] &= ~(1<<(TIM3_IRQn & 0x1f));
+
+
+       if(RTC->ISR & RTC_ISR_ALRAF) {
+               timer++;
+               set_mode=4;
+               EXTI->PR |= EXTI_PR_PR17;
+               RTC->ISR &= ~(RTC_ISR_ALRAF);
+
+
+       }
+//    NVIC->ISER[0] &= ~(1<<(TIM3_IRQn & 0x1f));
+
+}
+
+// ----------------------------------------------------------------------------
diff --git a/src/main.old b/src/main.old

new file mode 100644 (file)

index 0000000..cdc8883
--- /dev/null
+++ b/src/main.old
@@ -0,0 +1,115 @@
+/*
+ * This file is part of the ??OS++ distribution.
+ *   (https://github.com/micro-os-plus)
+ * Copyright (c) 2014 Liviu Ionescu.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+// ----------------------------------------------------------------------------
+
+#include <stdio.h>
+#include <stdlib.h>
+#include "diag/Trace.h"
+
+#include "Timer.h"
+#include "BlinkLed.h"
+
+// ----------------------------------------------------------------------------
+//
+// Standalone STM32F0 led blink sample (trace via NONE).
+//
+// In debug configurations, demonstrate how to print a greeting message
+// on the trace device. In release configurations the message is
+// simply discarded.
+//
+// Then demonstrates how to blink a led with 1 Hz, using a
+// continuous loop and SysTick delays.
+//
+// Trace support is enabled by adding the TRACE macro definition.
+// By default the trace messages are forwarded to the NONE output,
+// but can be rerouted to any device or completely suppressed, by
+// changing the definitions required in system/src/diag/trace_impl.c
+// (currently OS_USE_TRACE_ITM, OS_USE_TRACE_SEMIHOSTING_DEBUG/_STDOUT).
+//
+// The external clock frequency is specified as a preprocessor definition
+// passed to the compiler via a command line option (see the 'C/C++ General' ->
+// 'Paths and Symbols' -> the 'Symbols' tab, if you want to change it).
+// The value selected during project creation was HSE_VALUE=8000000.
+//
+// Note: The default clock settings take the user defined HSE_VALUE and try
+// to reach the maximum possible system clock. For the default 8 MHz input
+// the result is guaranteed, but for other values it might not be possible,
+// so please adjust the PLL settings in system/src/cmsis/system_stm32f0xx.c
+//
+
+// ----- Timing definitions -------------------------------------------------
+
+// Keep the LED on for 2/3 of a second.
+#define BLINK_ON_TICKS  (TIMER_FREQUENCY_HZ * 3 / 4)
+#define BLINK_OFF_TICKS (TIMER_FREQUENCY_HZ - BLINK_ON_TICKS)
+
+// ----- main() ---------------------------------------------------------------
+
+// Sample pragmas to cope with warnings. Please note the related line at
+// the end of this function, used to pop the compiler diagnostics status.
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#pragma GCC diagnostic ignored "-Wmissing-declarations"
+#pragma GCC diagnostic ignored "-Wreturn-type"
+
+int
+main(int argc, char* argv[])
+{
+  // Send a greeting to the trace device (skipped on Release).
+  trace_puts("Hello ARM World!");
+
+  // At this stage the system clock should have already been configured
+  // at high speed.
+  trace_printf("System clock: %u Hz\n", SystemCoreClock);
+
+  timer_start();
+
+  blink_led_init();
+  
+  uint32_t seconds = 0;
+
+  // Infinite loop
+  while (1)
+    {
+      blink_led_on();
+      timer_sleep(seconds == 0 ? TIMER_FREQUENCY_HZ : BLINK_ON_TICKS);
+
+      blink_led_off();
+      timer_sleep(BLINK_OFF_TICKS);
+
+      ++seconds;
+
+      // Count seconds on the trace device.
+      trace_printf("Second %u\n", seconds);
+    }
+  // Infinite loop, never return.
+}
+
+#pragma GCC diagnostic pop
+
+// ----------------------------------------------------------------------------
diff --git a/system/include/arm/semihosting.h b/system/include/arm/semihosting.h

new file mode 100644 (file)

index 0000000..be713b2
--- /dev/null
+++ b/system/include/arm/semihosting.h
@@ -0,0 +1,142 @@
+/*
+ * This file is part of the ??OS++ distribution.
+ *   (https://github.com/micro-os-plus)
+ * Copyright (c) 2014 Liviu Ionescu.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef ARM_SEMIHOSTING_H_
+#define ARM_SEMIHOSTING_H_
+
+// ----------------------------------------------------------------------------
+
+// Semihosting operations.
+enum OperationNumber
+{
+  // Regular operations
+  SEMIHOSTING_EnterSVC = 0x17,
+  SEMIHOSTING_ReportException = 0x18,
+  SEMIHOSTING_SYS_CLOSE = 0x02,
+  SEMIHOSTING_SYS_CLOCK = 0x10,
+  SEMIHOSTING_SYS_ELAPSED = 0x30,
+  SEMIHOSTING_SYS_ERRNO = 0x13,
+  SEMIHOSTING_SYS_FLEN = 0x0C,
+  SEMIHOSTING_SYS_GET_CMDLINE = 0x15,
+  SEMIHOSTING_SYS_HEAPINFO = 0x16,
+  SEMIHOSTING_SYS_ISERROR = 0x08,
+  SEMIHOSTING_SYS_ISTTY = 0x09,
+  SEMIHOSTING_SYS_OPEN = 0x01,
+  SEMIHOSTING_SYS_READ = 0x06,
+  SEMIHOSTING_SYS_READC = 0x07,
+  SEMIHOSTING_SYS_REMOVE = 0x0E,
+  SEMIHOSTING_SYS_RENAME = 0x0F,
+  SEMIHOSTING_SYS_SEEK = 0x0A,
+  SEMIHOSTING_SYS_SYSTEM = 0x12,
+  SEMIHOSTING_SYS_TICKFREQ = 0x31,
+  SEMIHOSTING_SYS_TIME = 0x11,
+  SEMIHOSTING_SYS_TMPNAM = 0x0D,
+  SEMIHOSTING_SYS_WRITE = 0x05,
+  SEMIHOSTING_SYS_WRITEC = 0x03,
+  SEMIHOSTING_SYS_WRITE0 = 0x04,
+
+  // Codes returned by SEMIHOSTING_ReportException
+  ADP_Stopped_ApplicationExit = ((2 << 16) + 38),
+  ADP_Stopped_RunTimeError = ((2 << 16) + 35),
+
+};
+
+// ----------------------------------------------------------------------------
+
+// SWI numbers and reason codes for RDI (Angel) monitors.
+#define AngelSWI_ARM                    0x123456
+#ifdef __thumb__
+#define AngelSWI                        0xAB
+#else
+#define AngelSWI                        AngelSWI_ARM
+#endif
+// For thumb only architectures use the BKPT instruction instead of SWI.
+#if defined(__ARM_ARCH_7M__)     \
+    || defined(__ARM_ARCH_7EM__) \
+    || defined(__ARM_ARCH_6M__)
+#define AngelSWIInsn                    "bkpt"
+#define AngelSWIAsm                     bkpt
+#else
+#define AngelSWIInsn                    "swi"
+#define AngelSWIAsm                     swi
+#endif
+
+#if defined(OS_DEBUG_SEMIHOSTING_FAULTS)
+// Testing the local semihosting handler cannot use another BKPT, since this
+// configuration cannot trigger HaedFault exceptions while the debugger is
+// connected, so we use an illegal op code, that will trigger an
+// UsageFault exception.
+#define AngelSWITestFault       "setend be"
+#define AngelSWITestFaultOpCode (0xB658)
+#endif
+
+static inline int
+__attribute__ ((always_inline))
+call_host (int reason, void* arg)
+{
+  int value;
+  asm volatile (
+
+      " mov r0, %[rsn]  \n"
+      " mov r1, %[arg]  \n"
+#if defined(OS_DEBUG_SEMIHOSTING_FAULTS)
+      " " AngelSWITestFault " \n"
+#else
+      " " AngelSWIInsn " %[swi] \n"
+#endif
+      " mov %[val], r0"
+
+      : [val] "=r" (value) /* Outputs */
+      : [rsn] "r" (reason), [arg] "r" (arg), [swi] "i" (AngelSWI) /* Inputs */
+      : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc"
+      // Clobbers r0 and r1, and lr if in supervisor mode
+  );
+
+  // Accordingly to page 13-77 of ARM DUI 0040D other registers
+  // can also be clobbered. Some memory positions may also be
+  // changed by a system call, so they should not be kept in
+  // registers. Note: we are assuming the manual is right and
+  // Angel is respecting the APCS.
+  return value;
+}
+
+// ----------------------------------------------------------------------------
+
+// Function used in _exit() to return the status code as Angel exception.
+static inline void
+__attribute__ ((always_inline,noreturn))
+report_exception (int reason)
+{
+  call_host (SEMIHOSTING_ReportException, (void*) reason);
+
+  for (;;)
+    ;
+}
+
+// ----------------------------------------------------------------------------
+
+#endif // ARM_SEMIHOSTING_H_
diff --git a/system/include/cmsis/.stm32f0xx.h.swp b/system/include/cmsis/.stm32f0xx.h.swp

new file mode 100644 (file)

index 0000000..234a55b

Binary files /dev/null and b/system/include/cmsis/.stm32f0xx.h.swp differ
diff --git a/system/include/cmsis/README_DEVICE.txt b/system/include/cmsis/README_DEVICE.txt

new file mode 100644 (file)

index 0000000..15ad66e
--- /dev/null
+++ b/system/include/cmsis/README_DEVICE.txt
@@ -0,0 +1,7 @@
+The stm32f0xx.h and system_stm32f0xx.h files are from 
+STM32F0xx_StdPeriph_Lib_V1.5.0.zip, the folder:
+
+       STM32F0xx_StdPeriph_Lib_V1.5.0/Libraries/CMSIS/Device/ST/STM32F0xx/Include
+
+The cmsis_device.h is added for convenience.
+
diff --git a/system/include/cmsis/arm_common_tables.h b/system/include/cmsis/arm_common_tables.h

new file mode 100644 (file)

index 0000000..8742a56
--- /dev/null
+++ b/system/include/cmsis/arm_common_tables.h
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. October 2015
+* $Revision:   V.1.4.5 a
+*
+* Project:         CMSIS DSP Library
+* Title:           arm_common_tables.h
+*
+* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+/* extern const q31_t realCoefAQ31[1024]; */
+/* extern const q31_t realCoefBQ31[1024]; */
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */
diff --git a/system/include/cmsis/arm_const_structs.h b/system/include/cmsis/arm_const_structs.h

new file mode 100644 (file)

index 0000000..726d06e
--- /dev/null
+++ b/system/include/cmsis/arm_const_structs.h
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision:   V.1.4.5
+*
+* Project:         CMSIS DSP Library
+* Title:           arm_const_structs.h
+*
+* Description: This file has constant structs that are initialized for
+*              user convenience.  For example, some can be given as
+*              arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/system/include/cmsis/arm_math.h b/system/include/cmsis/arm_math.h

new file mode 100644 (file)

index 0000000..d33f8a9
--- /dev/null
+++ b/system/include/cmsis/arm_math.h
@@ -0,0 +1,7154 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+*
+* $Date:        20. October 2015
+* $Revision:    V1.4.5 b
+*
+* Project:      CMSIS DSP Library
+* Title:        arm_math.h
+*
+* Description:  Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * Introduction
+   * ------------
+   *
+   * This user manual describes the CMSIS DSP software library,
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * Using the Library
+   * ------------
+   *
+   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+   * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)
+   * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)
+   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)
+   * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)
+   *
+   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file <code> arm_math.h</code> for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or  ARM_MATH_CM3 or
+   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   *
+   * Examples
+   * --------
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * Toolchain Support
+   * ------------
+   *
+   * The library has been developed and tested with MDK-ARM version 5.14.0.0
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * Building the Library
+   * ------------
+   *
+   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * - arm_cortexM_math.uvprojx
+   *
+   *
+   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+   *
+   * Pre-processor Macros
+   * ------------
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
+   *
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+   * ARM_MATH_CM7 for building the library on cortex-M7.
+   *
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+   *
+   * <hr>
+   * CMSIS-DSP in ARM::CMSIS Pack
+   * -----------------------------
+   *
+   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
+   * |File/Folder                   |Content                                                                 |
+   * |------------------------------|------------------------------------------------------------------------|
+   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
+   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
+   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
+   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
+   *
+   * <hr>
+   * Revision History of CMSIS-DSP
+   * ------------
+   * Please refer to \ref ChangeLog_pg.
+   *
+   * Copyright Notice
+   * ------------
+   *
+   * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ *     pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * <pre>
+ *     ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ *     ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ *     ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+/* ignore some GCC warnings */
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+  #include "core_cm7.h"
+#elif defined (ARM_MATH_CM4)
+  #include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+  #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+  #include "core_cm0.h"
+  #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+  #include "core_cm0plus.h"
+  #define ARM_MATH_CM0_FAMILY
+#else
+  #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef   __cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31          (0x100)
+#define DELTA_Q15          0x5
+#define INDEX_MASK         0x0000003F
+#ifndef PI
+#define PI                 3.14159265358979f
+#endif
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define FAST_MATH_TABLE_SIZE  512
+#define FAST_MATH_Q31_SHIFT   (32 - 10)
+#define FAST_MATH_Q15_SHIFT   (16 - 10)
+#define CONTROLLER_Q31_SHIFT  (32 - 9)
+#define TABLE_SIZE  256
+#define TABLE_SPACING_Q31     0x400000
+#define TABLE_SPACING_Q15     0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING         0xB60B61
+
+  /**
+   * @brief Macro for Unaligned Support
+   */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+    #define ALIGN4
+#else
+  #if defined  (__GNUC__)
+    #define ALIGN4 __attribute__((aligned(4)))
+  #else
+    #define ALIGN4 __align(4)
+  #endif
+#endif   /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+  {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+  } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#if defined __CC_ARM
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED __attribute__((unused))
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+
+#elif defined __GNUC__
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+
+#elif defined __ICCARM__
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED
+
+#elif defined __CSMC__
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED
+
+#elif defined __TASKING__
+  #define __SIMD32_TYPE __unaligned int32_t
+  #define CMSIS_UNUSED
+
+#else
+  #error Unknown compiler
+#endif
+
+#define __SIMD32(addr)        (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
+#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
+#define __SIMD64(addr)        (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
+                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \
+                                         (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+#endif
+
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) | \
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) | \
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  static __INLINE q31_t clip_q63_to_q31(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  static __INLINE q15_t clip_q63_to_q15(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  static __INLINE q7_t clip_q31_to_q7(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  static __INLINE q15_t clip_q31_to_q15(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  static __INLINE q63_t mult32x64(
+  q63_t x,
+  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+/*
+  #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
+  #define __CLZ __clz
+  #endif
+ */
+/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__))  )
+  static __INLINE uint32_t __CLZ(
+  q31_t data);
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data)
+  {
+    uint32_t count = 0;
+    uint32_t mask = 0x80000000;
+
+    while((data & mask) == 0)
+    {
+      count += 1u;
+      mask = mask >> 1u;
+    }
+
+    return (count);
+  }
+#endif
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+   */
+
+  static __INLINE uint32_t arm_recip_q31(
+  q31_t in,
+  q31_t * dst,
+  q31_t * pRecipTable)
+  {
+    q31_t out;
+    uint32_t tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if(in > 0)
+    {
+      signBits = ((uint32_t) (__CLZ( in) - 1));
+    }
+    else
+    {
+      signBits = ((uint32_t) (__CLZ(-in) - 1));
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = (in << signBits);
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t)(in >> 24);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+    {
+      tempVal = (uint32_t) (((q63_t) in * out) >> 31);
+      tempVal = 0x7FFFFFFFu - tempVal;
+      /*      1.31 with exp 1 */
+      /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
+      out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+  }
+
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+   */
+  static __INLINE uint32_t arm_recip_q15(
+  q15_t in,
+  q15_t * dst,
+  q15_t * pRecipTable)
+  {
+    q15_t out = 0;
+    uint32_t tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if(in > 0)
+    {
+      signBits = ((uint32_t)(__CLZ( in) - 17));
+    }
+    else
+    {
+      signBits = ((uint32_t)(__CLZ(-in) - 17));
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = (in << signBits);
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t)(in >>  8);
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+    {
+      tempVal = (uint32_t) (((q31_t) in * out) >> 15);
+      tempVal = 0x7FFFu - tempVal;
+      /*      1.15 with exp 1 */
+      out = (q15_t) (((q31_t) out * tempVal) >> 14);
+      /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+  }
+
+
+  /*
+   * @brief C custom defined intrinisic function for only M0 processors
+   */
+#if defined(ARM_MATH_CM0_FAMILY)
+  static __INLINE q31_t __SSAT(
+  q31_t x,
+  uint32_t y)
+  {
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+    for (i = 0; i < (y - 1); i++)
+    {
+      posMax = posMax * 2;
+    }
+
+    if(x > 0)
+    {
+      posMax = (posMax - 1);
+
+      if(x > posMax)
+      {
+        x = posMax;
+      }
+    }
+    else
+    {
+      negMin = -posMax;
+
+      if(x < negMin)
+      {
+        x = negMin;
+      }
+    }
+    return (x);
+  }
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+  /*
+   * @brief C custom defined intrinsic function for M3 and M0 processors
+   */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  static __INLINE uint32_t __QADD8(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s, t, u;
+
+    r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+    s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+    t = __SSAT(((((q31_t)x <<  8) >> 24) + (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
+    u = __SSAT(((((q31_t)x      ) >> 24) + (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
+
+    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  static __INLINE uint32_t __QSUB8(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s, t, u;
+
+    r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+    s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+    t = __SSAT(((((q31_t)x <<  8) >> 24) - (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
+    u = __SSAT(((((q31_t)x      ) >> 24) - (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
+
+    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  static __INLINE uint32_t __QADD16(
+  uint32_t x,
+  uint32_t y)
+  {
+/*  q31_t r,     s;  without initialisation 'arm_offset_q15 test' fails  but 'intrinsic' tests pass! for armCC */
+    q31_t r = 0, s = 0;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  static __INLINE uint32_t __SHADD16(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  static __INLINE uint32_t __QSUB16(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  static __INLINE uint32_t __SHSUB16(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  static __INLINE uint32_t __QASX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  static __INLINE uint32_t __SHASX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  static __INLINE uint32_t __QSAX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  static __INLINE uint32_t __SHSAX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  static __INLINE uint32_t __SMUSDX(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  static __INLINE uint32_t __SMUADX(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
+  }
+
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  static __INLINE int32_t __QADD(
+  int32_t x,
+  int32_t y)
+  {
+    return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
+  }
+
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  static __INLINE int32_t __QSUB(
+  int32_t x,
+  int32_t y)
+  {
+    return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
+  }
+
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  static __INLINE uint32_t __SMLAD(
+  uint32_t x,
+  uint32_t y,
+  uint32_t sum)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ( ((q31_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  static __INLINE uint32_t __SMLADX(
+  uint32_t x,
+  uint32_t y,
+  uint32_t sum)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ( ((q31_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  static __INLINE uint32_t __SMLSDX(
+  uint32_t x,
+  uint32_t y,
+  uint32_t sum)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ( ((q31_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  static __INLINE uint64_t __SMLALD(
+  uint32_t x,
+  uint32_t y,
+  uint64_t sum)
+  {
+/*  return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
+    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ( ((q63_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  static __INLINE uint64_t __SMLALDX(
+  uint32_t x,
+  uint32_t y,
+  uint64_t sum)
+  {
+/*  return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
+    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ( ((q63_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  static __INLINE uint32_t __SMUAD(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  static __INLINE uint32_t __SMUSD(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
+  }
+
+
+  /*
+   * @brief C custom defined SXTB16 for M3 and M0 processors
+   */
+  static __INLINE uint32_t __SXTB16(
+  uint32_t x)
+  {
+    return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
+                       ((((q31_t)x <<  8) >>  8) & (q31_t)0xFFFF0000)  ));
+  }
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in]  S          points to an instance of the Q7 FIR filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] S          points to an instance of the Q7 FIR structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed.
+   */
+  void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in]  S          points to an instance of the Q15 FIR structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q15 FIR filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] S          points to an instance of the Q15 FIR filter structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * <code>numTaps</code> is not a supported value.
+   */
+  arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in]  S          points to an instance of the Q31 FIR filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q31 FIR structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] S          points to an instance of the Q31 FIR structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed at a time.
+   */
+  void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in]  S          points to an instance of the floating-point FIR structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] S          points to an instance of the floating-point FIR filter structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed at a time.
+   */
+  void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;        /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;        /**< Additional shift, in bits, applied to each output sample. */
+  } arm_biquad_casd_df1_inst_q15;
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;       /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;      /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_casd_df1_inst_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
+   */
+  void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
+   */
+  void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  S          points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float64_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f64;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+  } arm_matrix_instance_q31;
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]   pSrcA  points to the first input matrix structure
+   * @param[in]   pSrcB  points to the second input matrix structure
+   * @param[out]  pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point, complex, matrix multiplication.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_cmplx_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15, complex,  matrix multiplication.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_cmplx_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Q31, complex, matrix multiplication.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_cmplx_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  pSrc  points to the input matrix
+   * @param[out] pDst  points to the output matrix
+   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  pSrc  points to the input matrix
+   * @param[out] pDst  points to the output matrix
+   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  pSrc  points to the input matrix
+   * @param[out] pDst  points to the output matrix
+   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]  pSrcA   points to the first input matrix structure
+   * @param[in]  pSrcB   points to the second input matrix structure
+   * @param[out] pDst    points to output matrix structure
+   * @param[in]  pState  points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA   points to the first input matrix structure
+   * @param[in]  pSrcB   points to the second input matrix structure
+   * @param[out] pDst    points to output matrix structure
+   * @param[in]  pState  points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  pSrc   points to the input matrix
+   * @param[in]  scale  scale factor
+   * @param[out] pDst   points to the output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]  pSrc        points to input matrix
+   * @param[in]  scaleFract  fractional portion of the scale factor
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]  pSrc        points to input matrix
+   * @param[in]  scaleFract  fractional portion of the scale factor
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] S         points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows     number of rows in the matrix.
+   * @param[in]     nColumns  number of columns in the matrix.
+   * @param[in]     pData     points to the matrix data array.
+   */
+  void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData);
+
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] S         points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows     number of rows in the matrix.
+   * @param[in]     nColumns  number of columns in the matrix.
+   * @param[in]     pData     points to the matrix data array.
+   */
+  void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData);
+
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] S         points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows     number of rows in the matrix.
+   * @param[in]     nColumns  number of columns in the matrix.
+   * @param[in]     pData     points to the matrix data array.
+   */
+  void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0;           /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];     /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;          /**< The proportional gain. */
+    float32_t Ki;          /**< The integral gain. */
+    float32_t Kd;          /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] S               points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   */
+  void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] S  is an instance of the floating-point PID Control structure
+   */
+  void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] S               points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   */
+  void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] S   points to an instance of the Q31 PID Control structure
+   */
+
+  void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] S               points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   */
+  void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] S  points to an instance of the q15 PID Control structure
+   */
+  void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t *pData;   /**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t *pData;        /**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the Sin twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc);
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q31(
+  const arm_cfft_radix2_instance_q31 * S,
+  q31_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+  void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc);
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;             /**< value of 1/fftLen. */
+  } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_f32(
+  const arm_cfft_radix2_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;             /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q15;
+
+void arm_cfft_q15(
+    const arm_cfft_instance_q15 * S,
+    q15_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q31;
+
+void arm_cfft_q31(
+    const arm_cfft_instance_q31 * S,
+    q31_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_f32;
+
+  void arm_cfft_f32(
+  const arm_cfft_instance_f32 * S,
+  float32_t * p1,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst);
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+typedef struct
+  {
+    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
+    uint16_t fftLenRFFT;             /**< length of the real sequence */
+    float32_t * pTwiddleRFFT;        /**< Twiddle factors real stage  */
+  } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+   arm_rfft_fast_instance_f32 * S,
+   uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+  arm_rfft_fast_instance_f32 * S,
+  float32_t * p, float32_t * pOut,
+  uint8_t ifftFlag);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+  typedef struct
+  {
+    uint16_t N;                          /**< length of the DCT4. */
+    uint16_t Nby2;                       /**< half of the length of the DCT4. */
+    float32_t normalize;                 /**< normalizing factor. */
+    float32_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;               /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] S          points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     S_RFFT     points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     S_CFFT     points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+   */
+  arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize);
+
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]     S              points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]     pState         points to state buffer.
+   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
+   */
+  void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer);
+
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+  typedef struct
+  {
+    uint16_t N;                          /**< length of the DCT4. */
+    uint16_t Nby2;                       /**< half of the length of the DCT4. */
+    q31_t normalize;                     /**< normalizing factor. */
+    q31_t *pTwiddle;                     /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                   /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] S          points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     S_RFFT     points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     S_CFFT     points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+  arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize);
+
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]     S              points to an instance of the Q31 DCT4 structure.
+   * @param[in]     pState         points to state buffer.
+   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
+   */
+  void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer);
+
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+  typedef struct
+  {
+    uint16_t N;                          /**< length of the DCT4. */
+    uint16_t Nby2;                       /**< half of the length of the DCT4. */
+    q15_t normalize;                     /**< normalizing factor. */
+    q15_t *pTwiddle;                     /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                   /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] S          points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     S_RFFT     points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     S_CFFT     points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+  arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize);
+
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]     S              points to an instance of the Q15 DCT4 structure.
+   * @param[in]     pState         points to state buffer.
+   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
+   */
+  void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer);
+
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  scale      scale factor to be applied
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_scale_f32(
+  float32_t * pSrc,
+  float32_t scale,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]  pSrc        points to the input vector
+   * @param[in]  scaleFract  fractional portion of the scale value
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to the output vector
+   * @param[in]  blockSize   number of samples in the vector
+   */
+  void arm_scale_q7(
+  q7_t * pSrc,
+  q7_t scaleFract,
+  int8_t shift,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]  pSrc        points to the input vector
+   * @param[in]  scaleFract  fractional portion of the scale value
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to the output vector
+   * @param[in]  blockSize   number of samples in the vector
+   */
+  void arm_scale_q15(
+  q15_t * pSrc,
+  q15_t scaleFract,
+  int8_t shift,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]  pSrc        points to the input vector
+   * @param[in]  scaleFract  fractional portion of the scale value
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to the output vector
+   * @param[in]  blockSize   number of samples in the vector
+   */
+  void arm_scale_q31(
+  q31_t * pSrc,
+  q31_t scaleFract,
+  int8_t shift,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t blockSize,
+  float32_t * result);
+
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  uint32_t blockSize,
+  q31_t * result);
+
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_shift_q7(
+  q7_t * pSrc,
+  int8_t shiftBits,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_shift_q15(
+  q15_t * pSrc,
+  int8_t shiftBits,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_shift_q31(
+  q31_t * pSrc,
+  int8_t shiftBits,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_f32(
+  float32_t * pSrc,
+  float32_t offset,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_q7(
+  q7_t * pSrc,
+  q7_t offset,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_q15(
+  q15_t * pSrc,
+  q15_t offset,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_q31(
+  q31_t * pSrc,
+  q31_t offset,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a floating-point vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a Q7 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a Q15 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a Q31 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a floating-point vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ */
+  void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences.
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
+   */
+  void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ */
+  void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_fast_q15(
+          q15_t * pSrcA,
+          uint32_t srcALen,
+          q15_t * pSrcB,
+          uint32_t srcBLen,
+          q15_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
+   */
+  void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+    /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   */
+  void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q7 sequences
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @param[in]  pScratch1   points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2   points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;         /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;          /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in]  S          points to an instance of the floating-point FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] S          points to an instance of the floating-point FIR decimator structure.
+   * @param[in]     numTaps    number of coefficients in the filter.
+   * @param[in]     M          decimation factor.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+  arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] S          points to an instance of the Q15 FIR decimator structure.
+   * @param[in]     numTaps    number of coefficients in the filter.
+   * @param[in]     M          decimation factor.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+  arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in]  S     points to an instance of the Q31 FIR decimator structure.
+   * @param[in]  pSrc  points to the block of input data.
+   * @param[out] pDst  points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   */
+  void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q31 FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] S          points to an instance of the Q31 FIR decimator structure.
+   * @param[in]     numTaps    number of coefficients in the filter.
+   * @param[in]     M          decimation factor.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+  arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;            /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;             /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] S          points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L          upsample factor.
+   * @param[in]     numTaps    number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficient buffer.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+  arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] S          points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L          upsample factor.
+   * @param[in]     numTaps    number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficient buffer.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+  arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in]  S          points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] S          points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L          upsample factor.
+   * @param[in]     numTaps    number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficient buffer.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+  arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  S          points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] S          points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     postShift  shift to be applied to the output. Varies according to the coefficients format
+   */
+  void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift);
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f64;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  S          points to an instance of the filter data structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+   * @param[in]  S          points to an instance of the filter data structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_stereo_df2T_f32(
+  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  S          points to an instance of the filter data structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df2T_f64(
+  const arm_biquad_cascade_df2T_instance_f64 * S,
+  float64_t * pSrc,
+  float64_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the filter data structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the filter data structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_stereo_df2T_init_f32(
+  arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the filter data structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_df2T_init_f64(
+  arm_biquad_cascade_df2T_instance_f64 * S,
+  uint8_t numStages,
+  float64_t * pCoeffs,
+  float64_t * pState);
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] S          points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] pState     points to the state buffer.  The array is of length numStages.
+   */
+  void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in]  S          points to an instance of the Q15 FIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] S          points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] pState     points to the state buffer.   The array is of length numStages.
+   */
+  void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  S          points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] S          points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] pState     points to the state buffer.  The array is of length numStages.
+ */
+  void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  S          points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of stages in the filter. */
+    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of stages in the filter. */
+    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of stages in the filter. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                 /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                 /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in]  S          points to an instance of the floating-point IIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] S          points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages  number of stages in the filter.
+   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in]  S          points to an instance of the Q31 IIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] S          points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages  number of stages in the filter.
+   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in]  S          points to an instance of the Q15 IIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] S          points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] pkCoeffs   points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] pvCoeffs   points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] pState     points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize  number of samples to process per call.
+ */
+  void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  S          points to an instance of the floating-point LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] S          points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to the coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] S          points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to the coefficient buffer.
+   * @param[in] pState     points to the state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in]  S          points to an instance of the Q15 LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q31;
+
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  S          points to an instance of the Q15 LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] S          points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;         /**< step size that control filter coefficient updates. */
+    float32_t energy;     /**< saves previous frame energy. */
+    float32_t x0;         /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in]  S          points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] S          points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in]  S          points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] S          points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q15_t *recipTable;    /**< Points to the reciprocal initial value table. */
+    q15_t energy;         /**< saves previous frame energy. */
+    q15_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in]  S          points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] S          points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+   /**
+   * @brief Correlation of Q15 sequences
+   * @param[in]  pSrcA     points to the first input sequence.
+   * @param[in]  srcALen   length of the first input sequence.
+   * @param[in]  pSrcB     points to the second input sequence.
+   * @param[in]  srcBLen   length of the second input sequence.
+   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   */
+  void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+
+  void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+
+  void arm_correlate_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in]  pSrcA     points to the first input sequence.
+   * @param[in]  srcALen   length of the first input sequence.
+   * @param[in]  pSrcB     points to the second input sequence.
+   * @param[in]  srcBLen   length of the second input sequence.
+   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   */
+  void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+ /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   */
+  void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  S           points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  pSrc        points to the block of input data.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   */
+  void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  S           points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  pSrc        points to the block of input data.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   */
+  void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  S            points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  pSrc         points to the block of input data.
+   * @param[out] pDst         points to the block of output data
+   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
+   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   */
+  void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] S          points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  S            points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  pSrc         points to the block of input data.
+   * @param[out] pDst         points to the block of output data
+   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
+   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   */
+  void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] S          points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta   input value in degrees
+   * @param[out] pSinVal  points to the processed sine output.
+   * @param[out] pCosVal  points to the processed cos output.
+   */
+  void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCosVal);
+
+
+  /**
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees
+   * @param[out] pSinVal  points to the processed sine output.
+   * @param[out] pCosVal  points to the processed cosine output.
+   */
+  void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  pSrc        points to the input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  pSrc        points to the input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  pSrc        points to the input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * <pre>
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  </pre>
+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   *
+   * \par
+   * \image html PID.gif "Proportional Integral Derivative Controller"
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.
+   * The proportional value determines the reaction to the current error,
+   * the integral value determines the reaction based on the sum of recent errors,
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+   * A separate instance structure must be defined for each PID Controller.
+   * There are separate instance structure declarations for each of the 3 supported data types.
+   *
+   * \par Reset Functions
+   * There is also an associated reset function for each data type which clears the state array.
+   *
+   * \par Initialization Functions
+   * There is also an associated initialization function for each data type.
+   * The initialization function performs the following operations:
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.
+   *
+   * \par
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+   *
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the fixed-point versions of the PID Controller functions.
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] S   is an instance of the floating-point PID Control structure
+   * @param[in]     in  input sample to process
+   * @return out processed output sample.
+   */
+  static __INLINE float32_t arm_pid_f32(
+  arm_pid_instance_f32 * S,
+  float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] S  points to an instance of the Q31 PID Control structure
+   * @param[in]     in  input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 64-bit accumulator.
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+   * Thus, if the accumulator result overflows it wraps around rather than clip.
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+   */
+  static __INLINE q31_t arm_pid_q31(
+  arm_pid_instance_q31 * S,
+  q31_t in)
+  {
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+  }
+
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] S   points to an instance of the Q15 PID Control structure
+   * @param[in]     in  input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using a 64-bit internal accumulator.
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+  static __INLINE q15_t arm_pid_q15(
+  arm_pid_instance_q15 * S,
+  q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+    __SIMD32_TYPE *vstate;
+
+    /* Implementation of PID controller */
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    vstate = __SIMD32_CONST(S->state);
+    acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);
+#else
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+  }
+
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  src   points to the instance of the input floating-point matrix structure.
+   * @param[out] dst   points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+  arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * src,
+  arm_matrix_instance_f32 * dst);
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  src   points to the instance of the input floating-point matrix structure.
+   * @param[out] dst   points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+  arm_status arm_mat_inverse_f64(
+  const arm_matrix_instance_f64 * src,
+  arm_matrix_instance_f64 * dst);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]  Ia       input three-phase coordinate <code>a</code>
+   * @param[in]  Ib       input three-phase coordinate <code>b</code>
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   */
+  static __INLINE void arm_clarke_f32(
+  float32_t Ia,
+  float32_t Ib,
+  float32_t * pIalpha,
+  float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+  }
+
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]  Ia       input three-phase coordinate <code>a</code>
+   * @param[in]  Ib       input three-phase coordinate <code>b</code>
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+  static __INLINE void arm_clarke_q31(
+  q31_t Ia,
+  q31_t Ib,
+  q31_t * pIalpha,
+  q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out] pIa     points to output three-phase coordinate <code>a</code>
+   * @param[out] pIb     points to output three-phase coordinate <code>b</code>
+   */
+  static __INLINE void arm_inv_clarke_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pIa,
+  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
+  }
+
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version
+   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out] pIa     points to output three-phase coordinate <code>a</code>
+   * @param[out] pIb     points to output three-phase coordinate <code>b</code>
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+  static __INLINE void arm_inv_clarke_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pIa,
+  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+   * from the stationary to the moving reference frame and control the spatial relationship between
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]  Ialpha  input two-phase vector coordinate alpha
+   * @param[in]  Ibeta   input two-phase vector coordinate beta
+   * @param[out] pId     points to output   rotor reference frame d
+   * @param[out] pIq     points to output   rotor reference frame q
+   * @param[in]  sinVal  sine value of rotation angle theta
+   * @param[in]  cosVal  cosine value of rotation angle theta
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+  static __INLINE void arm_park_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pId,
+  float32_t * pIq,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+  }
+
+
+  /**
+   * @brief  Park transform for Q31 version
+   * @param[in]  Ialpha  input two-phase vector coordinate alpha
+   * @param[in]  Ibeta   input two-phase vector coordinate beta
+   * @param[out] pId     points to output rotor reference frame d
+   * @param[out] pIq     points to output rotor reference frame q
+   * @param[in]  sinVal  sine value of rotation angle theta
+   * @param[in]  cosVal  cosine value of rotation angle theta
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+  static __INLINE void arm_park_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pId,
+  q31_t * pIq,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]  Id       input coordinate of rotor reference frame d
+   * @param[in]  Iq       input coordinate of rotor reference frame q
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]  sinVal   sine value of rotation angle theta
+   * @param[in]  cosVal   cosine value of rotation angle theta
+   */
+  static __INLINE void arm_inv_park_f32(
+  float32_t Id,
+  float32_t Iq,
+  float32_t * pIalpha,
+  float32_t * pIbeta,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for   Q31 version
+   * @param[in]  Id       input coordinate of rotor reference frame d
+   * @param[in]  Iq       input coordinate of rotor reference frame q
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]  sinVal   sine value of rotation angle theta
+   * @param[in]  cosVal   cosine value of rotation angle theta
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+  static __INLINE void arm_inv_park_q31(
+  q31_t Id,
+  q31_t Iq,
+  q31_t * pIalpha,
+  q31_t * pIbeta,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * <pre>
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * </pre>
+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+   * <code>x</code> is the input sample value. The functions returns the output value.
+   *
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table
+   * if x is below input range and returns last value of table if x is above range.
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] S  is an instance of the floating-point Linear Interpolation structure
+   * @param[in]     x  input sample to process
+   * @return y processed output sample.
+   *
+   */
+  static __INLINE float32_t arm_linear_interp_f32(
+  arm_linear_interp_instance_f32 * S,
+  float32_t x)
+  {
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t *pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (int32_t) ((x - S->x1) / xSpacing);
+
+    if(i < 0)
+    {
+      /* Iniatilize output for below specified range as least output value of table */
+      y = pYData[0];
+    }
+    else if((uint32_t)i >= S->nValues)
+    {
+      /* Iniatilize output for above specified range as last output value of table */
+      y = pYData[S->nValues - 1];
+    }
+    else
+    {
+      /* Calculation of nearest input values */
+      x0 = S->x1 +  i      * xSpacing;
+      x1 = S->x1 + (i + 1) * xSpacing;
+
+      /* Read of nearest output values */
+      y0 = pYData[i];
+      y1 = pYData[i + 1];
+
+      /* Calculation of output */
+      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+  }
+
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] pYData   pointer to Q31 Linear Interpolation table
+   * @param[in] x        input sample to process
+   * @param[in] nValues  number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+  static __INLINE q31_t arm_linear_interp_q31(
+  q31_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & (q31_t)0xFFF00000) >> 20);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* shift left by 11 to keep fract in 1.31 format */
+      fract = (x & 0x000FFFFF) << 11;
+
+      /* Read two nearest output values from the index in 1.31(q31) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1];
+
+      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+      /* Convert y to 1.31 format */
+      return (y << 1u);
+    }
+  }
+
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] pYData   pointer to Q15 Linear Interpolation table
+   * @param[in] x        input sample to process
+   * @param[in] nValues  number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+  static __INLINE q15_t arm_linear_interp_q15(
+  q15_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & (int32_t)0xFFF00000) >> 20);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index */
+      y0 = pYData[index];
+      y1 = pYData[index + 1];
+
+      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+      y = ((q63_t) y0 * (0xFFFFF - fract));
+
+      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+      y += ((q63_t) y1 * (fract));
+
+      /* convert y to 1.15 format */
+      return (q15_t) (y >> 20);
+    }
+  }
+
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] pYData   pointer to Q7 Linear Interpolation table
+   * @param[in] x        input sample to process
+   * @param[in] nValues  number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+  static __INLINE q7_t arm_linear_interp_q7(
+  q7_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    uint32_t index;                              /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    if (x < 0)
+    {
+      return (pYData[0]);
+    }
+    index = (x >> 20) & 0xfff;
+
+    if(index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index and are in 1.7(q7) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1];
+
+      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+      y = ((y0 * (0xFFFFF - fract)));
+
+      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+      y += (y1 * fract);
+
+      /* convert y to 1.7(q7) format */
+      return (q7_t) (y >> 20);
+     }
+  }
+
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x  input value in radians.
+   * @return  sin(x).
+   */
+  float32_t arm_sin_f32(
+  float32_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  sin(x).
+   */
+  q31_t arm_sin_q31(
+  q31_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  sin(x).
+   */
+  q15_t arm_sin_q15(
+  q15_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x  input value in radians.
+   * @return  cos(x).
+   */
+  float32_t arm_cos_f32(
+  float32_t x);
+
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  cos(x).
+   */
+  q31_t arm_cos_q31(
+  q31_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  cos(x).
+   */
+  q15_t arm_cos_q15(
+  q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * <pre>
+   *      x1 = x0 - f(x0)/f'(x0)
+   * </pre>
+   * where <code>x1</code> is the current estimate,
+   * <code>x0</code> is the previous estimate, and
+   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+   * For the square root function, the algorithm reduces to:
+   * <pre>
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * </pre>
+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in    input value.
+   * @param[out] pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  static __INLINE arm_status arm_sqrt_f32(
+  float32_t in,
+  float32_t * pOut)
+  {
+    if(in >= 0.0f)
+    {
+
+#if   (__FPU_USED == 1) && defined ( __CC_ARM   )
+      *pOut = __sqrtf(in);
+#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+      *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined(__GNUC__)
+      *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
+      __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
+#else
+      *pOut = sqrtf(in);
+#endif
+
+      return (ARM_MATH_SUCCESS);
+    }
+    else
+    {
+      *pOut = 0.0f;
+      return (ARM_MATH_ARGUMENT_ERROR);
+    }
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out] pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut);
+
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out] pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+  static __INLINE void arm_circularWrite_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const int32_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = (uint16_t)wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  static __INLINE void arm_circularRead_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  int32_t * dst,
+  int32_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (int32_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value  */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+  static __INLINE void arm_circularWrite_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q15_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = (uint16_t)wOffset;
+  }
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q15_t * dst,
+  q15_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q15_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+  static __INLINE void arm_circularWrite_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q7_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = (uint16_t)wOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q7_t * dst,
+  q7_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q7_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   * @param[out] realResult  real part of the result returned here
+   * @param[out] imagResult  imaginary part of the result returned here
+   */
+  void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult);
+
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   * @param[out] realResult  real part of the result returned here
+   * @param[out] imagResult  imaginary part of the result returned here
+   */
+  void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult);
+
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   * @param[out] realResult  real part of the result returned here
+   * @param[out] imagResult  imaginary part of the result returned here
+   */
+  void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult);
+
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  pSrcCmplx   points to the complex input vector
+   * @param[in]  pSrcReal    points to the real input vector
+   * @param[out] pCmplxDst   points to the complex output vector
+   * @param[in]  numSamples  number of samples in each vector
+   */
+  void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  pSrcCmplx   points to the complex input vector
+   * @param[in]  pSrcReal    points to the real input vector
+   * @param[out] pCmplxDst   points to the complex output vector
+   * @param[in]  numSamples  number of samples in each vector
+   */
+  void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  pSrcCmplx   points to the complex input vector
+   * @param[in]  pSrcReal    points to the real input vector
+   * @param[out] pCmplxDst   points to the complex output vector
+   * @param[in]  numSamples  number of samples in each vector
+   */
+  void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] result     is output pointer
+   * @param[in]  index      is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * result,
+  uint32_t * index);
+
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output pointer
+   * @param[in]  pIndex     is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output pointer
+   * @param[out] pIndex     is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output pointer
+   * @param[out] pIndex     is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector.
+   * @param[in]  pSrc       points to the floating-point input vector
+   * @param[out] pDst       points to the Q31 output vector
+   * @param[in]  blockSize  length of the input vector
+   */
+  void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector.
+   * @param[in]  pSrc       points to the floating-point input vector
+   * @param[out] pDst       points to the Q15 output vector
+   * @param[in]  blockSize  length of the input vector
+   */
+  void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector.
+   * @param[in]  pSrc       points to the floating-point input vector
+   * @param[out] pDst       points to the Q7 output vector
+   * @param[in]  blockSize  length of the input vector
+   */
+  void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * <b>Algorithm</b>
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * <pre>
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * </pre>
+   *
+   * \par
+   * where <code>numRows</code> specifies the number of rows in the table;
+   * <code>numCols</code> specifies the number of columns in the table;
+   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+   *
+   * \par
+   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
+   * <pre>
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * </pre>
+   * \par
+   * The interpolated output point is computed as:
+   * <pre>
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * </pre>
+   * Note that the coordinates (x, y) contain integer and fractional components.
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate.
+  * @param[in]     Y  interpolation coordinate.
+  * @return out interpolated value.
+  */
+  static __INLINE float32_t arm_bilinear_interp_f32(
+  const arm_bilinear_interp_instance_f32 * S,
+  float32_t X,
+  float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+  }
+
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate in 12.20 format.
+  * @param[in]     Y  interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+  static __INLINE q31_t arm_bilinear_interp_q31(
+  arm_bilinear_interp_instance_q31 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + (int32_t)nCols * (cI)    ];
+    x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + (int32_t)nCols * (cI + 1)    ];
+    y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1  * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return ((q31_t)(acc << 2));
+  }
+
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate in 12.20 format.
+  * @param[in]     Y  interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+  static __INLINE q15_t arm_bilinear_interp_q15(
+  arm_bilinear_interp_instance_q15 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
+    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
+    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return ((q15_t)(acc >> 36));
+  }
+
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate in 12.20 format.
+  * @param[in]     Y  interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+  static __INLINE q7_t arm_bilinear_interp_q7(
+  arm_bilinear_interp_instance_q7 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & (q31_t)0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
+    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & (q31_t)0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
+    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return ((q7_t)(acc >> 40));
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+
+
+/* SMMLAR */
+#define multAcc_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMLSR */
+#define multSub_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMULR */
+#define mult_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+/* SMMLA */
+#define multAcc_32x32_keep32(a, x, y) \
+    a += (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMLS */
+#define multSub_32x32_keep32(a, x, y) \
+    a -= (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMUL */
+#define mult_32x32_keep32(a, x, y) \
+    a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM )
+  /* Enter low optimization region - place directly above function definition */
+  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+    #define LOW_OPTIMIZATION_ENTER \
+       _Pragma ("push")         \
+       _Pragma ("O1")
+  #else
+    #define LOW_OPTIMIZATION_ENTER
+  #endif
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+    #define LOW_OPTIMIZATION_EXIT \
+       _Pragma ("pop")
+  #else
+    #define LOW_OPTIMIZATION_EXIT
+  #endif
+
+  /* Enter low optimization region - place directly above function definition */
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+  #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__)
+  /* Enter low optimization region - place directly above function definition */
+  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+    #define LOW_OPTIMIZATION_ENTER \
+       _Pragma ("optimize=low")
+  #else
+    #define LOW_OPTIMIZATION_ENTER
+  #endif
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #define LOW_OPTIMIZATION_EXIT
+
+  /* Enter low optimization region - place directly above function definition */
+  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+       _Pragma ("optimize=low")
+  #else
+    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #endif
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__CSMC__)
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__TASKING__)
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef   __cplusplus
+}
+#endif
+
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/system/include/cmsis/cmsis_armcc.h b/system/include/cmsis/cmsis_armcc.h

new file mode 100644 (file)

index 0000000..74c49c6
--- /dev/null
+++ b/system/include/cmsis/cmsis_armcc.h
@@ -0,0 +1,734 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS Cortex-M Core Function/Instruction Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+
+#if       (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in integer value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in two unsigned short values.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/**
+  \brief   Reverse byte order in signed short value
+  \details Reverses the byte order in a signed short value with sign extension to integer.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    value  Value to rotate
+  \param [in]    value  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (__CORTEX_M >= 0x04U)  /* only for Cortex-M4 and above */
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#endif /* (__CORTEX_M >= 0x04) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/system/include/cmsis/cmsis_armcc_V6.h b/system/include/cmsis/cmsis_armcc_V6.h

new file mode 100644 (file)

index 0000000..cd13240
--- /dev/null
+++ b/system/include/cmsis/cmsis_armcc_V6.h
@@ -0,0 +1,1800 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc_V6.h
+ * @brief    CMSIS Cortex-M Core Function/Instruction Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CMSIS_ARMCC_V6_H
+#define __CMSIS_ARMCC_V6_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if  (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if  (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+#if  (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get IPSR Register (non-secure)
+  \details Returns the content of the non-secure IPSR Register when in secure state.
+  \return               IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+#if  (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get APSR Register (non-secure)
+  \details Returns the content of the non-secure APSR Register when in secure state.
+  \return               APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+#if  (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get xPSR Register (non-secure)
+  \details Returns the content of the non-secure xPSR Register when in secure state.
+  \return               xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if  (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp");
+}
+
+
+#if  (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp");
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if  (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp");
+}
+
+
+#if  (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp");
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if  (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if  (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U))  /* ToDo:  ARMCC_V6: check if this is ok for cortex >=3 */
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if  (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+#if  (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+}
+
+
+#if  (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Base Priority with condition (non_secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled,
+              or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value)
+{
+  __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if  (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if  (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+
+#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */
+
+
+#if (__ARM_ARCH_8M__ == 1U)
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return(result);
+}
+
+
+#if  (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M')     /* ToDo:  ARMCC_V6: check predefined macro for mainline */
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+}
+
+
+#if  (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M')     /* ToDo:  ARMCC_V6: check predefined macro for mainline */
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+
+  return(result);
+}
+
+
+#if  (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M')     /* ToDo:  ARMCC_V6: check predefined macro for mainline */
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+}
+
+
+#if  (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M')     /* ToDo:  ARMCC_V6: check predefined macro for mainline */
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+}
+#endif
+
+#endif /* (__ARM_ARCH_8M__ == 1U) */
+
+
+#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U))  /* ToDo:  ARMCC_V6: check if this is ok for cortex >=4 */
+
+/**
+  \brief   Get FPSCR
+  \details eturns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+#define __get_FPSCR      __builtin_arm_get_fpscr
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+  uint32_t result;
+
+  __ASM volatile ("");                                 /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+#endif
+
+#if  (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get FPSCR (non-secure)
+  \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state.
+  \return               Floating Point Status/Control register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+  uint32_t result;
+
+  __ASM volatile ("");                                 /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+#define __set_FPSCR      __builtin_arm_set_fpscr
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+  __ASM volatile ("");                                 /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+#endif
+
+#if  (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set FPSCR (non-secure)
+  \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+  __ASM volatile ("");                                 /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+#endif
+
+#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP          __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI          __builtin_arm_wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE          __builtin_arm_wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV          __builtin_arm_sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()        __builtin_arm_isb(0xF);
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()        __builtin_arm_dsb(0xF);
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()        __builtin_arm_dmb(0xF);
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in integer value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV          __builtin_bswap32
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in two unsigned short values.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16          __builtin_bswap16                           /* ToDo:  ARMCC_V6: check if __builtin_bswap16 could be used */
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order in signed short value
+  \details Reverses the byte order in a signed short value with sign extension to integer.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+                                                          /* ToDo:  ARMCC_V6: check if __builtin_bswap16 could be used */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+  int32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+            Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+                                                          /* ToDo:  ARMCC_V6: check if __builtin_arm_rbit is supported */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U))  /* ToDo:  ARMCC_V6: check if this is ok for cortex >=3 */
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return(result);
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             __builtin_clz
+
+
+#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U))  /* ToDo:  ARMCC_V6: check if this is ok for cortex >=3 */
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+/*#define __SSAT             __builtin_arm_ssat*/
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+#if 0
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+#endif
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */
+
+
+#if (__ARM_ARCH_8M__ == 1U)
+
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEX                  (uint32_t)__builtin_arm_stlex
+
+#endif /* (__ARM_ARCH_8M__ == 1U) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (__ARM_FEATURE_DSP == 1U)        /* ToDo:  ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1U) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_V6_H */
diff --git a/system/include/cmsis/cmsis_device.h b/system/include/cmsis/cmsis_device.h

new file mode 100644 (file)

index 0000000..9c74ee2
--- /dev/null
+++ b/system/include/cmsis/cmsis_device.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the ??OS++ distribution.
+ *   (https://github.com/micro-os-plus)
+ * Copyright (c) 2014 Liviu Ionescu.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef STM32F0_CMSIS_DEVICE_H_
+#define STM32F0_CMSIS_DEVICE_H_
+
+#include "stm32f0xx.h"
+
+#endif // STM32F0_CMSIS_DEVICE_H_
diff --git a/system/include/cmsis/cmsis_gcc.h b/system/include/cmsis/cmsis_gcc.h

new file mode 100644 (file)

index 0000000..bb89fbb
--- /dev/null
+++ b/system/include/cmsis/cmsis_gcc.h
@@ -0,0 +1,1373 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS Cortex-M Core Function/Instruction Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03U)
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03U) */
+
+
+#if       (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in integer value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in two unsigned short values.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   Reverse byte order in signed short value
+  \details Reverses the byte order in a signed short value with sign extension to integer.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  int32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    value  Value to rotate
+  \param [in]    value  Number of Bits to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return(result);
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             __builtin_clz
+
+
+#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (__CORTEX_M >= 0x04U)  /* only for Cortex-M4 and above */
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x04) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+#endif /* __CMSIS_GCC_H */
diff --git a/system/include/cmsis/core_cm0.h b/system/include/cmsis/core_cm0.h

new file mode 100644 (file)

index 0000000..a881376
--- /dev/null
+++ b/system/include/cmsis/core_cm0.h
@@ -0,0 +1,811 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+// [ILG]
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M0
+  @{
+ */
+
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM0_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                (0x00U)                                      /*!< Cortex-M Core */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */
+  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+  #define __STATIC_INLINE  static inline
+
+#else
+  #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "core_cmInstr.h"                /* Core Instruction Access */
+#include "core_cmFunc.h"                 /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000U
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable External Interrupt
+  \details Enables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Disable External Interrupt
+  \details Disables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of an external interrupt.
+  \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of an external interrupt.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of an interrupt.
+  \note    The priority cannot be set for every core interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) < 0)
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of an interrupt.
+           The interrupt number can be positive to specify an external (device specific) interrupt,
+           or negative to specify an internal (core) interrupt.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) < 0)
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+// [ILG]
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+#endif /* __CMSIS_GENERIC */
diff --git a/system/include/cmsis/core_cm0plus.h b/system/include/cmsis/core_cm0plus.h

new file mode 100644 (file)

index 0000000..dd2559a
--- /dev/null
+++ b/system/include/cmsis/core_cm0plus.h
@@ -0,0 +1,927 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+// [ILG]
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex-M0+
+  @{
+ */
+
+/*  CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U)                                   /*!< [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (0x1EU)                                   /*!< [15:0]  CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB           ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                (0x00U)                                      /*!< Cortex-M Core */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */
+  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+  #define __STATIC_INLINE  static inline
+
+#else
+  #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "core_cmInstr.h"                /* Core Instruction Access */
+#include "core_cmFunc.h"                 /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000U
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0+ header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable External Interrupt
+  \details Enables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Disable External Interrupt
+  \details Disables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of an external interrupt.
+  \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of an external interrupt.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of an interrupt.
+  \note    The priority cannot be set for every core interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) < 0)
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of an interrupt.
+           The interrupt number can be positive to specify an external (device specific) interrupt,
+           or negative to specify an internal (core) interrupt.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) < 0)
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+// [ILG]
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+#endif /* __CMSIS_GENERIC */
diff --git a/system/include/cmsis/core_cm3.h b/system/include/cmsis/core_cm3.h

new file mode 100644 (file)

index 0000000..c8a4d3d
--- /dev/null
+++ b/system/include/cmsis/core_cm3.h
@@ -0,0 +1,1776 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+// [ILG]
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M3
+  @{
+ */
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM3_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                (0x03U)                                      /*!< Cortex-M Core */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */
+  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+  #define __STATIC_INLINE  static inline
+
+#else
+  #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "core_cmInstr.h"                /* Core Instruction Access */
+#include "core_cmFunc.h"                 /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200U
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201U)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U))
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+#else
+        uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable External Interrupt
+  \details Enables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Disable External Interrupt
+  \details Disables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of an external interrupt.
+  \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of an external interrupt.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in NVIC and returns the active bit.
+  \param [in]      IRQn  Interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of an interrupt.
+  \note    The priority cannot be set for every core interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) < 0)
+  {
+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of an interrupt.
+           The interrupt number can be positive to specify an external (device specific) interrupt,
+           or negative to specify an internal (core) interrupt.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) < 0)
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY   0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+// [ILG]
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+#endif /* __CMSIS_GENERIC */
diff --git a/system/include/cmsis/core_cm4.h b/system/include/cmsis/core_cm4.h

new file mode 100644 (file)

index 0000000..e62f7af
--- /dev/null
+++ b/system/include/cmsis/core_cm4.h
@@ -0,0 +1,1950 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+// [ILG]
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM4_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                (0x04U)                                      /*!< Cortex-M Core */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */
+  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+  #define __STATIC_INLINE  static inline
+
+#else
+  #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "core_cmInstr.h"                /* Core Instruction Access */
+#include "core_cmFunc.h"                 /* Core Function Access */
+#include "core_cmSimd.h"                 /* Compiler specific SIMD Intrinsics */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000U
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1U)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable External Interrupt
+  \details Enables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Disable External Interrupt
+  \details Disables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of an external interrupt.
+  \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of an external interrupt.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in NVIC and returns the active bit.
+  \param [in]      IRQn  Interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of an interrupt.
+  \note    The priority cannot be set for every core interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) < 0)
+  {
+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of an interrupt.
+           The interrupt number can be positive to specify an external (device specific) interrupt,
+           or negative to specify an internal (core) interrupt.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) < 0)
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY   0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+// [ILG]
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+#endif /* __CMSIS_GENERIC */
diff --git a/system/include/cmsis/core_cm7.h b/system/include/cmsis/core_cm7.h

new file mode 100644 (file)

index 0000000..b7d370b
--- /dev/null
+++ b/system/include/cmsis/core_cm7.h
@@ -0,0 +1,2525 @@
+/**************************************************************************//**
+ * @file     core_cm7.h
+ * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+// [ILG]
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M7
+  @{
+ */
+
+/*  CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM7_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                (0x07U)                                      /*!< Cortex-M Core */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */
+  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+  #define __STATIC_INLINE  static inline
+
+#else
+  #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "core_cmInstr.h"                /* Core Instruction Access */
+#include "core_cmFunc.h"                 /* Core Function Access */
+#include "core_cmSimd.h"                 /* Compiler specific SIMD Intrinsics */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM7_REV
+    #define __CM7_REV               0x0000U
+    #warning "__CM7_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ICACHE_PRESENT
+    #define __ICACHE_PRESENT          0U
+    #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DCACHE_PRESENT
+    #define __DCACHE_PRESENT          0U
+    #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DTCM_PRESENT
+    #define __DTCM_PRESENT            0U
+    #warning "__DTCM_PRESENT        not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED3[93U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED3[981U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1U)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable External Interrupt
+  \details Enables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Disable External Interrupt
+  \details Disables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of an external interrupt.
+  \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of an external interrupt.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in NVIC and returns the active bit.
+  \param [in]      IRQn  Interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of an interrupt.
+  \note    The priority cannot be set for every core interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) < 0)
+  {
+    SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of an interrupt.
+           The interrupt number can be positive to specify an external (device specific) interrupt,
+           or negative to specify an internal (core) interrupt.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) < 0)
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = SCB->MVFR0;
+  if        ((mvfr0 & 0x00000FF0UL) == 0x220UL)
+  {
+    return 2UL;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & 0x00000FF0UL) == 0x020UL)
+  {
+    return 1UL;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0UL;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################  Cache functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
+
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_INLINE void SCB_EnableICache (void)
+{
+  #if (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_INLINE void SCB_DisableICache (void)
+{
+  #if (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateICache (void)
+{
+  #if (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  */
+__STATIC_INLINE void SCB_EnableDCache (void)
+{
+  #if (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = (0U << 1U) | 0U;          /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways--);
+    } while(sets--);
+    __DSB();
+
+    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  */
+__STATIC_INLINE void SCB_DisableDCache (void)
+{
+  #if (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = (0U << 1U) | 0U;          /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways--);
+    } while(sets--);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateDCache (void)
+{
+  #if (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = (0U << 1U) | 0U;          /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways--);
+    } while(sets--);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  */
+__STATIC_INLINE void SCB_CleanDCache (void)
+{
+  #if (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = (0U << 1U) | 0U;          /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways--);
+    } while(sets--);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+{
+  #if (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = (0U << 1U) | 0U;          /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways--);
+    } while(sets--);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t)addr;
+     int32_t linesize = 32U;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCIMVAC = op_addr;
+      op_addr += linesize;
+      op_size -= linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if (__DCACHE_PRESENT == 1)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+     int32_t linesize = 32U;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCMVAC = op_addr;
+      op_addr += linesize;
+      op_size -= linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+     int32_t linesize = 32U;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCIMVAC = op_addr;
+      op_addr += linesize;
+      op_size -= linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY   0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+// [ILG]
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+#endif /* __CMSIS_GENERIC */
diff --git a/system/include/cmsis/core_cmFunc.h b/system/include/cmsis/core_cmFunc.h

new file mode 100644 (file)

index 0000000..652a48a
--- /dev/null
+++ b/system/include/cmsis/core_cmFunc.h
@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/system/include/cmsis/core_cmInstr.h b/system/include/cmsis/core_cmInstr.h

new file mode 100644 (file)

index 0000000..f474b0e
--- /dev/null
+++ b/system/include/cmsis/core_cmInstr.h
@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/system/include/cmsis/core_cmSimd.h b/system/include/cmsis/core_cmSimd.h

new file mode 100644 (file)

index 0000000..66bf5c2
--- /dev/null
+++ b/system/include/cmsis/core_cmSimd.h
@@ -0,0 +1,96 @@
+/**************************************************************************//**
+ * @file     core_cmSimd.h
+ * @brief    CMSIS Cortex-M SIMD Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */
diff --git a/system/include/cmsis/core_sc000.h b/system/include/cmsis/core_sc000.h

new file mode 100644 (file)

index 0000000..514dbd8
--- /dev/null
+++ b/system/include/cmsis/core_sc000.h
@@ -0,0 +1,926 @@
+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC000
+  @{
+ */
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  (0x04U)                                    /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (0x1EU)                                    /*!< [15:0]  CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC000_CMSIS_VERSION_SUB           )    /*!< CMSIS HAL version number */
+
+#define __CORTEX_SC                 (000U)                                     /*!< Cortex secure core */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */
+  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+  #define __STATIC_INLINE  static inline
+
+#else
+  #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "core_cmInstr.h"                /* Core Instruction Access */
+#include "core_cmFunc.h"                 /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC000_REV
+    #define __SC000_REV             0x0000U
+    #warning "__SC000_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+        uint32_t RESERVED1[154U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the SC000 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of SC000 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable External Interrupt
+  \details Enables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Disable External Interrupt
+  \details Disables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of an external interrupt.
+  \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of an external interrupt.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of an interrupt.
+  \note    The priority cannot be set for every core interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) < 0)
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of an interrupt.
+           The interrupt number can be positive to specify an external (device specific) interrupt,
+           or negative to specify an internal (core) interrupt.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) < 0)
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/system/include/cmsis/core_sc300.h b/system/include/cmsis/core_sc300.h

new file mode 100644 (file)

index 0000000..8bd18aa
--- /dev/null
+++ b/system/include/cmsis/core_sc300.h
@@ -0,0 +1,1745 @@
+/**************************************************************************//**
+ * @file     core_sc300.h
+ * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC3000
+  @{
+ */
+
+/*  CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN  (0x04U)                                    /*!< [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   (0x1EU)                                    /*!< [15:0]  CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC300_CMSIS_VERSION_SUB           )    /*!< CMSIS HAL version number */
+
+#define __CORTEX_SC                 (300U)                                     /*!< Cortex secure core */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */
+  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+  #define __STATIC_INLINE  static inline
+
+#else
+  #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "core_cmInstr.h"                /* Core Instruction Access */
+#include "core_cmFunc.h"                 /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC300_REV
+    #define __SC300_REV               0x0000U
+    #warning "__SC300_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED1[129U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+        uint32_t RESERVED1[1U];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable External Interrupt
+  \details Enables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Disable External Interrupt
+  \details Disables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of an external interrupt.
+  \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of an external interrupt.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in NVIC and returns the active bit.
+  \param [in]      IRQn  Interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of an interrupt.
+  \note    The priority cannot be set for every core interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) < 0)
+  {
+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of an interrupt.
+           The interrupt number can be positive to specify an external (device specific) interrupt,
+           or negative to specify an internal (core) interrupt.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) < 0)
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY   0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/system/include/cmsis/stm32f0xx.h b/system/include/cmsis/stm32f0xx.h

new file mode 100644 (file)

index 0000000..fe71a43
--- /dev/null
+++ b/system/include/cmsis/stm32f0xx.h
@@ -0,0 +1,5707 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx.h
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer Header File. 
+  *          This file contains all the peripheral register's definitions, bits 
+  *          definitions and memory mapping for STM32F0xx devices.  
+  *          
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The device used in the target application
+  *              - To use or not the peripheral???s drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral???s registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_STDPERIPH_DRIVER"
+  *              - To change few application-specific parameters such as the HSE 
+  *                crystal frequency
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral???s registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f0xx
+  * @{
+  */
+    
+#ifndef __STM32F0XX_H
+#define __STM32F0XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+  
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+  
+/* Uncomment the line below according to the target STM32F0 device used in your 
+   application 
+  */
+
+#if !defined (STM32F030) && !defined (STM32F031) && !defined (STM32F051) && \
+    !defined (STM32F072) && !defined (STM32F042) && !defined (STM32F091) && \
+    !defined (STM32F070xB) && !defined (STM32F070x6) && !defined (STM32F030xC)
+  /* #define STM32F030 */   
+  /* #define STM32F031 */   
+  /* #define STM32F051 */   
+  /* #define STM32F072 */
+  /* #define STM32F070xB */   
+  /* #define STM32F042 */
+  /* #define STM32F070x6 */   
+  /* #define STM32F091 */
+  /* #define STM32F030xC */  
+#endif /* STM32F030 || STM32F031 || STM32F051 || STM32F072 || STM32F042 || STM32F091 ||
+          STM32F070xB || STM32F070x6 || STM32F030xC */
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+
+/* Old STM32F0XX definition, maintained for legacy purpose */
+#if defined(STM32F0XX) || defined(STM32F0XX_MD) 
+  #define STM32F051
+#endif /* STM32F0XX */
+
+/* Old STM32F0XX_LD definition, maintained for legacy purpose */
+#ifdef STM32F0XX_LD
+  #define     STM32F031
+#endif /* STM32F0XX_LD */
+
+/* Old STM32F0XX_HD definition, maintained for legacy purpose */
+#ifdef STM32F0XX_HD
+   #define   STM32F072
+#endif /* STM32F0XX_HD */
+
+/* Old STM32F030X6/X8 definition, maintained for legacy purpose */
+#if defined (STM32F030X8) || defined (STM32F030X6)
+  #define    STM32F030
+#endif /* STM32F030X8 or  STM32F030X6 */
+
+
+#if !defined (STM32F030) && !defined (STM32F031) && !defined (STM32F051) && \
+    !defined (STM32F072) && !defined (STM32F042) && !defined (STM32F091) && \
+    !defined (STM32F070xB) && !defined (STM32F070x6) && !defined (STM32F030xC)
+ #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
+#endif /* STM32F030 || STM32F031 || STM32F051 || STM32F072 || STM32F042 || STM32F091 ||
+          STM32F070xB || STM32F070x6 || STM32F030xC */
+
+#if !defined  USE_STDPERIPH_DRIVER
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+  /*#define USE_STDPERIPH_DRIVER*/
+#endif /* USE_STDPERIPH_DRIVER */
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+   used in your application 
+   
+   Tip: To avoid modifying this file each time you need to use different HSE, you
+        can define the HSE value in your toolchain compiler preprocessor.
+  */
+#if !defined  (HSE_VALUE)     
+#define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/
+#endif /* HSE_VALUE */
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
+   Timeout value 
+   */
+#if !defined  (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT   ((uint16_t)0x5000) /*!< Time out for HSE start up */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup 
+   Timeout value 
+   */
+#if !defined  (HSI_STARTUP_TIMEOUT)
+#define HSI_STARTUP_TIMEOUT   ((uint16_t)0x5000) /*!< Time out for HSI start up */
+#endif /* HSI_STARTUP_TIMEOUT */
+
+#if !defined  (HSI_VALUE) 
+#define HSI_VALUE  ((uint32_t)8000000) /*!< Value of the Internal High Speed oscillator in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI_VALUE */
+
+#if !defined  (HSI14_VALUE) 
+#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI14_VALUE */
+
+#if !defined  (HSI48_VALUE) 
+#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI48_VALUE */
+
+#if !defined  (LSI_VALUE) 
+#define LSI_VALUE  ((uint32_t)40000)    /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* LSI_VALUE */
+
+#if !defined  (LSE_VALUE) 
+#define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+/**
+ * @brief STM32F0xx Standard Peripheral Library version number V1.4.0
+   */
+#define __STM32F0XX_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32F0XX_STDPERIPH_VERSION_SUB1   (0x05) /*!< [23:16] sub1 version */
+#define __STM32F0XX_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32F0XX_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
+#define __STM32F0XX_STDPERIPH_VERSION        ((__STM32F0XX_STDPERIPH_VERSION_MAIN << 24)\
+                                             |(__STM32F0XX_STDPERIPH_VERSION_SUB1 << 16)\
+                                             |(__STM32F0XX_STDPERIPH_VERSION_SUB2 << 8)\
+                                             |(__STM32F0XX_STDPERIPH_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+ * @brief STM32F0xx Interrupt Number Definition, according to the selected device 
+ *        in @ref Library_configuration_section 
+ */
+#define __CM0_REV                 0 /*!< Core Revision r0p0                            */
+#define __MPU_PRESENT             0 /*!< STM32F0xx do not provide MPU                  */
+#define __NVIC_PRIO_BITS          2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used  */
+
+/*!< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0 Hard Fault Interrupt                        */
+  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                          */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                          */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0 System Tick Interrupt                      */
+
+#if defined (STM32F051)
+/******  STM32F051  specific Interrupt Numbers *************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
+  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
+  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
+  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
+  RCC_IRQn                    = 4,      /*!< RCC Interrupt                                           */
+  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
+  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
+  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
+  TS_IRQn                     = 8,      /*!< Touch sense controller Interrupt                        */
+  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
+  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
+  DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4 and Channel 5 Interrupts                 */
+  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                        */
+  TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts  */
+  TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                          */
+  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
+  TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                          */
+  TIM6_DAC_IRQn               = 17,     /*!< TIM6 and DAC Interrupts                                 */
+  TIM14_IRQn                  = 19,     /*!< TIM14 Interrupt                                         */
+  TIM15_IRQn                  = 20,     /*!< TIM15 Interrupt                                         */
+  TIM16_IRQn                  = 21,     /*!< TIM16 Interrupt                                         */
+  TIM17_IRQn                  = 22,     /*!< TIM17 Interrupt                                         */
+  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
+  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                          */
+  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
+  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                          */
+  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                        */
+  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
+  CEC_IRQn                    = 30      /*!< CEC Interrupt                                           */
+#elif defined (STM32F031)
+/******  STM32F031 specific Interrupt Numbers *************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
+  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
+  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
+  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
+  RCC_IRQn                    = 4,      /*!< RCC Interrupt                                           */
+  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
+  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
+  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
+  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
+  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
+  DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4 and Channel 5 Interrupts                 */
+  ADC1_IRQn                   = 12,     /*!< ADC1 Interrupt                                          */
+  TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts  */
+  TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                          */
+  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
+  TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                          */
+  TIM14_IRQn                  = 19,     /*!< TIM14 Interrupt                                         */
+  TIM16_IRQn                  = 21,     /*!< TIM16 Interrupt                                         */
+  TIM17_IRQn                  = 22,     /*!< TIM17 Interrupt                                         */
+  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
+  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
+  USART1_IRQn                 = 27      /*!< USART1 Interrupt                                        */
+#elif defined (STM32F030)
+/******  STM32F030 specific Interrupt Numbers *************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
+  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
+  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
+  RCC_IRQn                    = 4,      /*!< RCC Interrupt                                           */
+  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
+  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
+  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
+  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
+  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
+  DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4 and Channel 5 Interrupts                 */
+  ADC1_IRQn                   = 12,     /*!< ADC1 Interrupt                                          */
+  TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts  */
+  TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                          */
+  TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                          */
+  TIM14_IRQn                  = 19,     /*!< TIM14 Interrupt                                         */
+  TIM15_IRQn                  = 20,     /*!< TIM15 Interrupt                                         */
+  TIM16_IRQn                  = 21,     /*!< TIM16 Interrupt                                         */
+  TIM17_IRQn                  = 22,     /*!< TIM17 Interrupt                                         */
+  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
+  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                          */
+  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
+  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                          */
+  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                        */
+  USART2_IRQn                 = 28      /*!< USART2 Interrupt                                        */
+#elif defined (STM32F072)
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                     */
+  PVD_VDDIO2_IRQn             = 1,      /*!< PVD and VDDIO2 supply comparator through EXTI Line detect Interrupt */
+  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                               */
+  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                               */
+  RCC_CRS_IRQn                = 4,      /*!< RCC and CRS Interrupts                                        */
+  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                                  */
+  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                                  */
+  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                                  */
+  TSC_IRQn                    = 8,      /*!< TSC Interrupt                                                 */
+  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                      */
+  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                       */
+  DMA1_Channel4_5_6_7_IRQn    = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
+  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                              */
+  TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts        */
+  TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                                */
+  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                                */
+  TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                                */
+  TIM6_DAC_IRQn               = 17,     /*!< TIM6 and DAC Interrupts                                       */
+  TIM7_IRQn                   = 18,     /*!< TIM7 Interrupts                                               */
+  TIM14_IRQn                  = 19,     /*!< TIM14 Interrupt                                               */
+  TIM15_IRQn                  = 20,     /*!< TIM15 Interrupt                                               */
+  TIM16_IRQn                  = 21,     /*!< TIM16 Interrupt                                               */
+  TIM17_IRQn                  = 22,     /*!< TIM17 Interrupt                                               */
+  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                                */
+  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                                */
+  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                                */
+  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                                */
+  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                              */
+  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                              */
+  USART3_4_IRQn               = 29,     /*!< USART3 and USART4 Interrupts                                  */
+  CEC_CAN_IRQn                = 30,     /*!< CEC and CAN Interrupts                                        */
+  USB_IRQn                    = 31      /*!< USB Low Priority global Interrupt                             */
+#elif defined (STM32F042)
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                     */
+  PVD_VDDIO2_IRQn             = 1,      /*!< PVD and VDDIO2 supply comparator through EXTI Line detect Interrupt */
+  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                               */
+  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                               */
+  RCC_CRS_IRQn                = 4,      /*!< RCC and CRS Interrupts                                        */
+  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                                  */
+  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                                  */
+  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                                  */
+  TSC_IRQn                    = 8,      /*!< TSC Interrupt                                                 */
+  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                      */
+  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                       */
+  DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4, Channel 5 Interrupts                          */
+  ADC1_IRQn                   = 12,     /*!< ADC1 Interrupts                                               */
+  TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts        */
+  TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                                */
+  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                                */
+  TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                                */
+  TIM14_IRQn                  = 19,     /*!< TIM14 Interrupt                                               */
+  TIM16_IRQn                  = 21,     /*!< TIM16 Interrupt                                               */
+  TIM17_IRQn                  = 22,     /*!< TIM17 Interrupt                                               */
+  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                                */
+  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                                */
+  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                                */
+  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                              */
+  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                              */
+  CEC_CAN_IRQn                = 30,     /*!< CEC and CAN Interrupts                                        */
+  USB_IRQn                    = 31      /*!< USB Low Priority global Interrupt                             */
+#elif defined (STM32F091)
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                       */
+  PVD_VDDIO2_IRQn             = 1,      /*!< PVD & VDDIO2 Interrupts through EXTI Lines 16 and 31            */
+  RTC_IRQn                    = 2,      /*!< RTC Interrupt through EXTI Lines 17, 19 and 20                  */
+  FLASH_IRQn                  = 3,      /*!< FLASH global Interrupt                                          */
+  RCC_CRS_IRQn                = 4,      /*!< RCC & CRS Global Interrupts                                     */
+  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                                    */
+  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                                    */
+  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                                    */
+  TSC_IRQn                    = 8,      /*!< Touch Sensing Controller Interrupts                             */
+  DMA1_Ch1_IRQn               = 9,      /*!< DMA1 Channel 1 Interrupt                                        */
+  DMA1_Ch2_3_DMA2_Ch1_2_IRQn  = 10,     /*!< DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2 Interrupts          */
+  DMA1_Ch4_7_DMA2_Ch3_5_IRQn  = 11,     /*!< DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5 Interrupts            */
+  ADC1_COMP_IRQn               = 12,     /*!< ADC, COMP1 and COMP2 Interrupts (EXTI Lines 21 and 22)          */
+  TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts          */
+  TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                                  */
+  TIM2_IRQn                   = 15,     /*!< TIM2 global Interrupt                                           */
+  TIM3_IRQn                   = 16,     /*!< TIM3 global Interrupt                                           */
+  TIM6_DAC_IRQn               = 17,     /*!< TIM6 global and DAC channel underrun error Interrupts           */
+  TIM7_IRQn                   = 18,     /*!< TIM7 global Interrupt                                           */
+  TIM14_IRQn                  = 19,     /*!< TIM14 global Interrupt                                          */
+  TIM15_IRQn                  = 20,     /*!< TIM15 global Interrupt                                          */
+  TIM16_IRQn                  = 21,     /*!< TIM16 global Interrupt                                          */
+  TIM17_IRQn                  = 22,     /*!< TIM17 global Interrupt                                          */
+  I2C1_IRQn                   = 23,     /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup)      */
+  I2C2_IRQn                   = 24,     /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup)      */
+  SPI1_IRQn                   = 25,     /*!< SPI1 global Interrupt                                           */
+  SPI2_IRQn                   = 26,     /*!< SPI2 global Interrupt                                           */
+  USART1_IRQn                 = 27,     /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
+  USART2_IRQn                 = 28,     /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
+  USART3_8_IRQn               = 29,     /*!< USART3 to USART8 global Interrupts                              */
+  CEC_CAN_IRQn                = 30      /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt           */
+#elif defined (STM32F070xB)
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                       */
+  RTC_IRQn                    = 2,      /*!< RTC Interrupt through EXTI Lines 17, 19 and 20                  */
+  FLASH_IRQn                  = 3,      /*!< FLASH global Interrupt                                          */
+  RCC_IRQn                    = 4,      /*!< RCC Global Interrupts                                           */
+  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                                    */
+  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                                    */
+  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                                    */
+  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                        */
+  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                         */
+  DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4 and Channel 5 Interrupts                          */
+  ADC1_IRQn                   = 12,     /*!< ADC1 interrupts (ADC interrupt combined with EXTI Lines 21 and 22 */
+  TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts          */
+  TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                                  */
+  TIM3_IRQn                   = 16,     /*!< TIM3 global Interrupt                                           */
+  TIM6_IRQn                   = 17,     /*!< TIM6 global Interrupts                                          */
+  TIM7_IRQn                   = 18,     /*!< TIM7 global Interrupt                                           */
+  TIM14_IRQn                  = 19,     /*!< TIM14 global Interrupt                                          */
+  TIM15_IRQn                  = 20,     /*!< TIM15 global Interrupt                                          */
+  TIM16_IRQn                  = 21,     /*!< TIM16 global Interrupt                                          */
+  TIM17_IRQn                  = 22,     /*!< TIM17 global Interrupt                                          */
+  I2C1_IRQn                   = 23,     /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup)      */
+  I2C2_IRQn                   = 24,     /*!< I2C2 Event Interrupt                                            */
+  SPI1_IRQn                   = 25,     /*!< SPI1 global Interrupt                                           */
+  SPI2_IRQn                   = 26,     /*!< SPI2 global Interrupt                                           */
+  USART1_IRQn                 = 27,     /*!< USART1 global Interrupt                                         */
+  USART2_IRQn                 = 28,     /*!< USART2 global Interrupt                                         */
+  USART3_4_IRQn               = 29,     /*!< USART3 and USART4 global Interrupts                             */
+  USB_IRQn                    = 31      /*!< USB global Interrupts & EXTI Line18 Interrupt                   */
+#elif defined (STM32F070x6)
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                       */
+  RTC_IRQn                    = 2,      /*!< RTC Interrupt through EXTI Lines 17, 19 and 20                  */
+  FLASH_IRQn                  = 3,      /*!< FLASH global Interrupt                                          */
+  RCC_IRQn                    = 4,      /*!< RCC Global Interrupts                                     */
+  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                                    */
+  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                                    */
+  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                                    */
+  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                        */
+  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                         */
+  DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4 and Channel 5 Interrupts                         */
+  ADC1_IRQn                   = 12,     /*!< ADC1 Interrupt                                                  */
+  TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts          */
+  TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                                  */
+  TIM3_IRQn                   = 16,     /*!< TIM3 global Interrupt                                           */
+  TIM14_IRQn                  = 19,     /*!< TIM14 global Interrupt                                          */
+  TIM16_IRQn                  = 21,     /*!< TIM16 global Interrupt                                          */
+  TIM17_IRQn                  = 22,     /*!< TIM17 global Interrupt                                          */
+  I2C1_IRQn                   = 23,     /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup)      */
+  SPI1_IRQn                   = 25,     /*!< SPI1 global Interrupt                                           */
+  USART1_IRQn                 = 27,     /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
+  USART2_IRQn                 = 28,     /*!< USART2 global Interrupt                                         */
+  USB_IRQn                    = 31      /*!< USB global Interrupts & EXTI Line18 Interrupt                   */
+#elif defined (STM32F030xC)
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                       */
+  RTC_IRQn                    = 2,      /*!< RTC Interrupt through EXTI Lines 17, 19 and 20                  */
+  FLASH_IRQn                  = 3,      /*!< FLASH global Interrupt                                          */
+  RCC_IRQn                    = 4,      /*!< RCC Global Interrupts                                           */
+  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                                    */
+  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                                    */
+  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                                    */
+  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                        */
+  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                         */
+  DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4 and Channel 5 Interrupts                         */
+  ADC1_IRQn                   = 12,     /*!< ADC Interrupts                                                  */
+  TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts          */
+  TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                                  */
+  TIM3_IRQn                   = 16,     /*!< TIM3 global Interrupt                                           */
+  TIM6_IRQn                   = 17,     /*!< TIM6 global Interrupts                                          */
+  TIM7_IRQn                   = 18,     /*!< TIM7 global Interrupt                                           */
+  TIM14_IRQn                  = 19,     /*!< TIM14 global Interrupt                                          */
+  TIM15_IRQn                  = 20,     /*!< TIM15 global Interrupt                                          */
+  TIM16_IRQn                  = 21,     /*!< TIM16 global Interrupt                                          */
+  TIM17_IRQn                  = 22,     /*!< TIM17 global Interrupt                                          */
+  I2C1_IRQn                   = 23,     /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup)      */
+  I2C2_IRQn                   = 24,     /*!< I2C2 Event Interrupt                                            */
+  SPI1_IRQn                   = 25,     /*!< SPI1 global Interrupt                                           */
+  SPI2_IRQn                   = 26,     /*!< SPI2 global Interrupt                                           */
+  USART1_IRQn                 = 27,     /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
+  USART2_IRQn                 = 28,     /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
+  USART3_6_IRQn               = 29,     /*!< USART3 to USART6 global Interrupts                              */
+#endif /* STM32F051 */
+}IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm0.h"
+#include "system_stm32f0xx.h"
+#include <stdint.h>
+
+/** @addtogroup Exported_types
+  * @{
+  */  
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */   
+
+/** 
+  * @brief Analog to Digital Converter  
+  */
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
+  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
+  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
+  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
+  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
+  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
+  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
+  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
+  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
+  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
+  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
+  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
+   __IO uint32_t DR;          /*!< ADC data register,                                          Address offset:0x40 */
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CCR;
+} ADC_Common_TypeDef;
+
+
+/** 
+  * @brief Controller Area Network TxMailBox 
+  */
+typedef struct
+{
+  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
+  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/** 
+  * @brief Controller Area Network FIFOMailBox 
+  */
+typedef struct
+{
+  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
+  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+  
+/** 
+  * @brief Controller Area Network FilterRegister 
+  */
+typedef struct
+{
+  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/** 
+  * @brief Controller Area Network 
+  */
+typedef struct
+{
+  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
+  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
+  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
+  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
+  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
+  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
+  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
+  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
+  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
+  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
+  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
+  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
+  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
+  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
+  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
+  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
+  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
+  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
+  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
+  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
+  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
+  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
+} CAN_TypeDef;
+
+/** 
+  * @brief HDMI-CEC 
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;           /*!< CEC control register,                                       Address offset:0x00 */
+  __IO uint32_t CFGR;         /*!< CEC configuration register,                                 Address offset:0x04 */
+  __IO uint32_t TXDR;         /*!< CEC Tx data register ,                                      Address offset:0x08 */
+  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,                                       Address offset:0x0C */
+  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register,                          Address offset:0x10 */
+  __IO uint32_t IER;          /*!< CEC interrupt enable register,                              Address offset:0x14 */
+}CEC_TypeDef;
+
+/**
+  * @brief Comparator 
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;     /*!< COMP comparator control and status register, Address offset: 0x1C */
+} COMP_TypeDef;
+
+
+/** 
+  * @brief CRC calculation unit 
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
+  __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
+  uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */
+  uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */
+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+  * @brief Clock Recovery System 
+  */
+typedef struct 
+{
+__IO uint32_t CR;     /*!< CRS ccontrol register,              Address offset: 0x00 */
+__IO uint32_t CFGR;   /*!< CRS configuration register,         Address offset: 0x04 */
+__IO uint32_t ISR;    /*!< CRS interrupt and status register,  Address offset: 0x08 */
+__IO uint32_t ICR;    /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
+} CRS_TypeDef;
+
+/** 
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
+} DAC_TypeDef;
+
+/** 
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
+  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
+  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
+  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/** 
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CCR;          /*!< DMA channel x configuration register                                           */
+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register                                          */
+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register                                      */
+  __IO uint32_t CMAR;         /*!< DMA channel x memory address register                                          */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< DMA interrupt status register,                            Address offset: 0x00 */
+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,                        Address offset: 0x04 */
+  uint32_t      RESERVED0[40];/*!< Reserved as declared by channel typedef                         0x08 - 0xA4*/
+  __IO uint32_t RMPCR;        /*!< Remap control register,                                      Address offset: 0xA8 */
+}DMA_TypeDef;
+
+/** 
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                             Address offset: 0x00 */
+  __IO uint32_t EMR;          /*!<EXTI Event mask register,                                 Address offset: 0x04 */
+  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,                  Address offset: 0x08 */
+  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,                  Address offset: 0x0C */
+  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,                   Address offset: 0x10 */
+  __IO uint32_t PR;           /*!<EXTI Pending register,                                    Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/** 
+  * @brief FLASH Registers
+  */
+typedef struct
+{
+  __IO uint32_t ACR;          /*!<FLASH access control register,                 Address offset: 0x00 */
+  __IO uint32_t KEYR;         /*!<FLASH key register,                            Address offset: 0x04 */
+  __IO uint32_t OPTKEYR;      /*!<FLASH OPT key register,                        Address offset: 0x08 */
+  __IO uint32_t SR;           /*!<FLASH status register,                         Address offset: 0x0C */
+  __IO uint32_t CR;           /*!<FLASH control register,                        Address offset: 0x10 */
+  __IO uint32_t AR;           /*!<FLASH address register,                        Address offset: 0x14 */
+  __IO uint32_t RESERVED;     /*!< Reserved,                                                     0x18 */
+  __IO uint32_t OBR;          /*!<FLASH option bytes register,                   Address offset: 0x1C */
+  __IO uint32_t WRPR;         /*!<FLASH option bytes register,                   Address offset: 0x20 */
+} FLASH_TypeDef;
+
+
+/** 
+  * @brief Option Bytes Registers
+  */
+typedef struct
+{
+  __IO uint16_t RDP;          /*!< FLASH option byte Read protection,             Address offset: 0x00 */
+  __IO uint16_t USER;         /*!< FLASH option byte user options,                Address offset: 0x02 */
+  __IO uint16_t DATA0;        /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
+  __IO uint16_t DATA1;        /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
+  __IO uint16_t WRP0;         /*!< FLASH option byte write protection 0,          Address offset: 0x08 */
+  __IO uint16_t WRP1;         /*!< FLASH option byte write protection 1,          Address offset: 0x0A */
+  __IO uint16_t WRP2;         /*!< FLASH option byte write protection 2,          Address offset: 0x0C */
+  __IO uint16_t WRP3;         /*!< FLASH option byte write protection 3,          Address offset: 0x0E */
+} OB_TypeDef;
+  
+
+/** 
+  * @brief General Purpose IO
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;        /*!< GPIO port mode register,                                  Address offset: 0x00 */
+  __IO uint16_t OTYPER;       /*!< GPIO port output type register,                           Address offset: 0x04 */
+  uint16_t RESERVED0;         /*!< Reserved,                                                                 0x06 */
+  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,                          Address offset: 0x08 */
+  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,                     Address offset: 0x0C */
+  __IO uint16_t IDR;          /*!< GPIO port input data register,                            Address offset: 0x10 */
+  uint16_t RESERVED1;         /*!< Reserved,                                                                 0x12 */
+  __IO uint16_t ODR;          /*!< GPIO port output data register,                           Address offset: 0x14 */
+  uint16_t RESERVED2;         /*!< Reserved,                                                                 0x16 */
+  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,                     Address offset: 0x18 */
+  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,                    Address offset: 0x1C */
+  __IO uint32_t AFR[2];       /*!< GPIO alternate function low register,                Address offset: 0x20-0x24 */
+  __IO uint16_t BRR;          /*!< GPIO bit reset register,                                  Address offset: 0x28 */
+  uint16_t RESERVED3;         /*!< Reserved,                                                                 0x2A */
+}GPIO_TypeDef;
+
+/** 
+  * @brief SysTem Configuration
+  */
+
+typedef struct
+{
+  __IO uint32_t CFGR1;          /*!< SYSCFG configuration register 1,                        Address offset: 0x00 */
+       uint32_t RESERVED;       /*!< Reserved,                                                               0x04 */
+  __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration register,  Address offset: 0x14-0x08 */
+  __IO uint32_t CFGR2;          /*!< SYSCFG configuration register 2,                        Address offset: 0x18 */
+       uint32_t RESERVED1[25];  /*!< Reserved + COMP,                                                                                             0x1C */
+  __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register,                  Address offset: 0x80 */
+       
+}SYSCFG_TypeDef;
+
+/** 
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
+}I2C_TypeDef;
+
+
+/** 
+  * @brief Independent WATCHDOG
+  */
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/** 
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
+  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+
+/** 
+  * @brief Reset and Clock Control
+  */
+typedef struct
+{
+  __IO uint32_t CR;         /*!< RCC clock control register,                                  Address offset: 0x00 */
+  __IO uint32_t CFGR;       /*!< RCC clock configuration register,                            Address offset: 0x04 */
+  __IO uint32_t CIR;        /*!< RCC clock interrupt register,                                Address offset: 0x08 */
+  __IO uint32_t APB2RSTR;   /*!< RCC APB2 peripheral reset register,                          Address offset: 0x0C */
+  __IO uint32_t APB1RSTR;   /*!< RCC APB1 peripheral reset register,                          Address offset: 0x10 */
+  __IO uint32_t AHBENR;     /*!< RCC AHB peripheral clock register,                           Address offset: 0x14 */
+  __IO uint32_t APB2ENR;    /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x18 */
+  __IO uint32_t APB1ENR;    /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x1C */
+  __IO uint32_t BDCR;       /*!< RCC Backup domain control register,                          Address offset: 0x20 */ 
+  __IO uint32_t CSR;        /*!< RCC clock control & status register,                         Address offset: 0x24 */
+  __IO uint32_t AHBRSTR;    /*!< RCC AHB peripheral reset register,                           Address offset: 0x28 */
+  __IO uint32_t CFGR2;      /*!< RCC clock configuration register 2,                          Address offset: 0x2C */
+  __IO uint32_t CFGR3;      /*!< RCC clock configuration register 3,                          Address offset: 0x30 */
+  __IO uint32_t CR2;        /*!< RCC clock control register 2,                                Address offset: 0x34 */
+} RCC_TypeDef;
+
+/** 
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{                           
+  __IO uint32_t TR;         /*!< RTC time register,                                        Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< RTC date register,                                        Address offset: 0x04 */
+  __IO uint32_t CR;         /*!< RTC control register,                                     Address offset: 0x08 */
+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                   Address offset: 0x0C */
+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                   Address offset: 0x10 */
+  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,(only for STM32F072 devices)    Address offset: 0x14 */
+       uint32_t RESERVED1;  /*!< Reserved,                                                 Address offset: 0x18 */
+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                     Address offset: 0x1C */
+       uint32_t RESERVED2;  /*!< Reserved,                                                 Address offset: 0x20 */
+  __IO uint32_t WPR;        /*!< RTC write protection register,                            Address offset: 0x24 */
+  __IO uint32_t SSR;        /*!< RTC sub second register,                                  Address offset: 0x28 */
+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                               Address offset: 0x2C */
+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                             Address offset: 0x30 */
+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                             Address offset: 0x34 */
+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
+  __IO uint32_t CALR;       /*!< RTC calibration register,                                 Address offset: 0x3C */
+  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                          Address offset: 0x44 */
+       uint32_t RESERVED3;  /*!< Reserved,                                                 Address offset: 0x48 */
+       uint32_t RESERVED4;  /*!< Reserved,                                                 Address offset: 0x4C */
+  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                    Address offset: 0x50 */
+  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                    Address offset: 0x54 */
+  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                    Address offset: 0x58 */
+  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                    Address offset: 0x5C */
+  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                    Address offset: 0x60 */
+} RTC_TypeDef;
+
+/* Old register name definition maintained for legacy purpose */
+#define CAL   CALR
+
+/** 
+  * @brief Serial Peripheral Interface
+  */
+  
+typedef struct
+{
+  __IO uint16_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
+  uint16_t  RESERVED0;    /*!< Reserved, 0x02                                                            */
+  __IO uint16_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
+  uint16_t  RESERVED1;    /*!< Reserved, 0x06                                                            */
+  __IO uint16_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
+  uint16_t  RESERVED2;    /*!< Reserved, 0x0A                                                            */
+  __IO uint16_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
+  uint16_t  RESERVED3;    /*!< Reserved, 0x0E                                                            */
+  __IO uint16_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
+  uint16_t  RESERVED4;    /*!< Reserved, 0x12                                                            */
+  __IO uint16_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
+  uint16_t  RESERVED5;    /*!< Reserved, 0x16                                                            */
+  __IO uint16_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
+  uint16_t  RESERVED6;    /*!< Reserved, 0x1A                                                            */ 
+  __IO uint16_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
+  uint16_t  RESERVED7;    /*!< Reserved, 0x1E                                                            */
+  __IO uint16_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
+  uint16_t  RESERVED8;    /*!< Reserved, 0x22                                                            */    
+} SPI_TypeDef;
+
+
+/** 
+  * @brief TIM
+  */
+typedef struct
+{
+  __IO uint16_t CR1;             /*!< TIM control register 1,                      Address offset: 0x00 */
+  uint16_t      RESERVED0;       /*!< Reserved,                                                    0x02 */
+  __IO uint16_t CR2;             /*!< TIM control register 2,                      Address offset: 0x04 */
+  uint16_t      RESERVED1;       /*!< Reserved,                                                    0x06 */
+  __IO uint16_t SMCR;            /*!< TIM slave Mode Control register,             Address offset: 0x08 */
+  uint16_t      RESERVED2;       /*!< Reserved,                                                    0x0A */
+  __IO uint16_t DIER;            /*!< TIM DMA/interrupt enable register,           Address offset: 0x0C */
+  uint16_t      RESERVED3;       /*!< Reserved,                                                    0x0E */
+  __IO uint16_t SR;              /*!< TIM status register,                         Address offset: 0x10 */
+  uint16_t      RESERVED4;       /*!< Reserved,                                                    0x12 */
+  __IO uint16_t EGR;             /*!< TIM event generation register,               Address offset: 0x14 */
+  uint16_t      RESERVED5;       /*!< Reserved,                                                    0x16 */
+  __IO uint16_t CCMR1;           /*!< TIM  capture/compare mode register 1,        Address offset: 0x18 */
+  uint16_t      RESERVED6;       /*!< Reserved,                                                    0x1A */
+  __IO uint16_t CCMR2;           /*!< TIM  capture/compare mode register 2,        Address offset: 0x1C */
+  uint16_t      RESERVED7;       /*!< Reserved,                                                    0x1E */
+  __IO uint16_t CCER;            /*!< TIM capture/compare enable register,         Address offset: 0x20 */
+  uint16_t      RESERVED8;       /*!< Reserved,                                                    0x22 */
+  __IO uint32_t CNT;             /*!< TIM counter register,                        Address offset: 0x24 */
+  __IO uint16_t PSC;             /*!< TIM prescaler register,                      Address offset: 0x28 */
+  uint16_t      RESERVED10;      /*!< Reserved,                                                    0x2A */
+  __IO uint32_t ARR;             /*!< TIM auto-reload register,                    Address offset: 0x2C */
+  __IO uint16_t RCR;             /*!< TIM  repetition counter register,            Address offset: 0x30 */
+  uint16_t      RESERVED12;      /*!< Reserved,                                                    0x32 */
+  __IO uint32_t CCR1;            /*!< TIM capture/compare register 1,              Address offset: 0x34 */
+  __IO uint32_t CCR2;            /*!< TIM capture/compare register 2,              Address offset: 0x38 */
+  __IO uint32_t CCR3;            /*!< TIM capture/compare register 3,              Address offset: 0x3C */
+  __IO uint32_t CCR4;            /*!< TIM capture/compare register 4,              Address offset: 0x40 */
+  __IO uint16_t BDTR;            /*!< TIM break and dead-time register,            Address offset: 0x44 */
+  uint16_t      RESERVED17;      /*!< Reserved,                                                    0x26 */
+  __IO uint16_t DCR;             /*!< TIM DMA control register,                    Address offset: 0x48 */
+  uint16_t      RESERVED18;      /*!< Reserved,                                                    0x4A */
+  __IO uint16_t DMAR;            /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */
+  uint16_t      RESERVED19;      /*!< Reserved,                                                    0x4E */
+  __IO uint16_t OR;              /*!< TIM option register,                         Address offset: 0x50 */
+  uint16_t      RESERVED20;      /*!< Reserved,                                                    0x52 */
+} TIM_TypeDef;
+
+/** 
+  * @brief Touch Sensing Controller (TSC)
+  */
+typedef struct
+{
+  __IO uint32_t CR;        /*!< TSC control register,                                     Address offset: 0x00 */
+  __IO uint32_t IER;       /*!< TSC interrupt enable register,                            Address offset: 0x04 */
+  __IO uint32_t ICR;       /*!< TSC interrupt clear register,                             Address offset: 0x08 */ 
+  __IO uint32_t ISR;       /*!< TSC interrupt status register,                            Address offset: 0x0C */
+  __IO uint32_t IOHCR;     /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
+  __IO uint32_t RESERVED1; /*!< Reserved,                                                 Address offset: 0x14 */
+  __IO uint32_t IOASCR;    /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
+  __IO uint32_t RESERVED2; /*!< Reserved,                                                 Address offset: 0x1C */
+  __IO uint32_t IOSCR;     /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
+  __IO uint32_t RESERVED3; /*!< Reserved,                                                 Address offset: 0x24 */
+  __IO uint32_t IOCCR;     /*!< TSC I/O channel control register,                         Address offset: 0x28 */
+  __IO uint32_t RESERVED4; /*!< Reserved,                                                 Address offset: 0x2C */
+  __IO uint32_t IOGCSR;    /*!< TSC I/O group control status register,                    Address offset: 0x30 */
+  __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register,                         Address offset: 0x34-50 */
+} TSC_TypeDef;
+
+/** 
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+  
+typedef struct
+{
+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint16_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
+  uint16_t  RESERVED1;  /*!< Reserved, 0x0E                                                 */  
+  __IO uint16_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  uint16_t  RESERVED2;  /*!< Reserved, 0x12                                                 */
+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
+  __IO uint16_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
+  uint16_t  RESERVED3;  /*!< Reserved, 0x1A                                                 */
+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint16_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
+  uint16_t  RESERVED4;  /*!< Reserved, 0x26                                                 */
+  __IO uint16_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
+  uint16_t  RESERVED5;  /*!< Reserved, 0x2A                                                 */
+} USART_TypeDef;
+
+
+/** 
+  * @brief Window WATCHDOG
+  */
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+
+#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE        PERIPH_BASE
+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000)
+
+#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000)
+#define TIM3_BASE             (APBPERIPH_BASE + 0x00000400)
+#define TIM6_BASE             (APBPERIPH_BASE + 0x00001000)
+#define TIM7_BASE             (APBPERIPH_BASE + 0x00001400)
+#define TIM14_BASE            (APBPERIPH_BASE + 0x00002000)
+#define RTC_BASE              (APBPERIPH_BASE + 0x00002800)
+#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00)
+#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000)
+#define SPI2_BASE             (APBPERIPH_BASE + 0x00003800)
+#define USART2_BASE           (APBPERIPH_BASE + 0x00004400)
+#define USART3_BASE           (APBPERIPH_BASE + 0x00004800)
+#define USART4_BASE           (APBPERIPH_BASE + 0x00004C00)
+#define USART5_BASE           (APBPERIPH_BASE + 0x00005000)
+#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400)
+#define I2C2_BASE             (APBPERIPH_BASE + 0x00005800)
+#define CAN_BASE              (APBPERIPH_BASE + 0x00006400)
+#define CRS_BASE              (APBPERIPH_BASE + 0x00006C00)
+#define PWR_BASE              (APBPERIPH_BASE + 0x00007000)
+#define DAC_BASE              (APBPERIPH_BASE + 0x00007400)
+#define CEC_BASE              (APBPERIPH_BASE + 0x00007800)
+
+#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000)
+#define COMP_BASE             (APBPERIPH_BASE + 0x0001001C)
+#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400)
+#define USART6_BASE           (APBPERIPH_BASE + 0x00011400)
+#define USART7_BASE           (APBPERIPH_BASE + 0x00011800)
+#define USART8_BASE           (APBPERIPH_BASE + 0x00011C00)
+#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400) /* KVL: TBC*/
+#define ADC_BASE              (APBPERIPH_BASE + 0x00012708) /* KVL: TBC*/
+#define TIM1_BASE             (APBPERIPH_BASE + 0x00012C00)
+#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000)
+#define USART1_BASE           (APBPERIPH_BASE + 0x00013800)
+#define TIM15_BASE            (APBPERIPH_BASE + 0x00014000)
+#define TIM16_BASE            (APBPERIPH_BASE + 0x00014400)
+#define TIM17_BASE            (APBPERIPH_BASE + 0x00014800)
+#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800)
+
+#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000)
+#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008)
+#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001C)
+#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030)
+#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044)
+#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058)
+#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006C)
+#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080)
+#define DMA2_BASE             (AHBPERIPH_BASE + 0x00000400)
+#define DMA2_Channel1_BASE    (DMA2_BASE + 0x00000008)
+#define DMA2_Channel2_BASE    (DMA2_BASE + 0x0000001C)
+#define DMA2_Channel3_BASE    (DMA2_BASE + 0x00000030)
+#define DMA2_Channel4_BASE    (DMA2_BASE + 0x00000044)
+#define DMA2_Channel5_BASE    (DMA2_BASE + 0x00000058)
+
+#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000)
+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
+#define OB_BASE               ((uint32_t)0x1FFFF800)        /*!< FLASH Option Bytes base address */
+#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000)
+#define TSC_BASE              (AHBPERIPH_BASE + 0x00004000)
+
+#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x00000000)
+#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x00000400)
+#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x00000800)
+#define GPIOD_BASE            (AHB2PERIPH_BASE + 0x00000C00)
+#define GPIOE_BASE            (AHB2PERIPH_BASE + 0x00001000)
+#define GPIOF_BASE            (AHB2PERIPH_BASE + 0x00001400)
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_declaration
+  * @{
+  */  
+
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define USART4              ((USART_TypeDef *) USART4_BASE)
+#define USART5              ((USART_TypeDef *) USART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define CAN                 ((CAN_TypeDef *) CAN_BASE)
+#define CRS                 ((CRS_TypeDef *) CRS_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+#define CEC                 ((CEC_TypeDef *) CEC_BASE)
+
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP                ((COMP_TypeDef *) COMP_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define USART6              ((USART_TypeDef *) USART6_BASE)
+#define USART7              ((USART_TypeDef *) USART7_BASE)
+#define USART8              ((USART_TypeDef *) USART8_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB                  ((OB_TypeDef *) OB_BASE) 
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define TSC                 ((TSC_TypeDef *) TSC_BASE)
+
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+  
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+    
+/******************************************************************************/
+/*                         Peripheral Registers Bits Definition               */
+/******************************************************************************/
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog to Digital Converter (ADC)                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for ADC_ISR register  ******************/
+#define ADC_ISR_AWD                          ((uint32_t)0x00000080)        /*!< Analog watchdog flag */
+#define ADC_ISR_OVR                          ((uint32_t)0x00000010)        /*!< Overrun flag */
+#define ADC_ISR_EOSEQ                        ((uint32_t)0x00000008)        /*!< End of Sequence flag */
+#define ADC_ISR_EOC                          ((uint32_t)0x00000004)        /*!< End of Conversion */
+#define ADC_ISR_EOSMP                        ((uint32_t)0x00000002)        /*!< End of sampling flag */
+#define ADC_ISR_ADRDY                        ((uint32_t)0x00000001)        /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
+
+/********************  Bits definition for ADC_IER register  ******************/
+#define ADC_IER_AWDIE                        ((uint32_t)0x00000080)        /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE                        ((uint32_t)0x00000010)        /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE                      ((uint32_t)0x00000008)        /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE                        ((uint32_t)0x00000004)        /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE                      ((uint32_t)0x00000002)        /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE                      ((uint32_t)0x00000001)        /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
+
+/********************  Bits definition for ADC_CR register  *******************/
+#define ADC_CR_ADCAL                         ((uint32_t)0x80000000)        /*!< ADC calibration */
+#define ADC_CR_ADSTP                         ((uint32_t)0x00000010)        /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART                       ((uint32_t)0x00000004)        /*!< ADC start of conversion */
+#define ADC_CR_ADDIS                         ((uint32_t)0x00000002)        /*!< ADC disable command */
+#define ADC_CR_ADEN                          ((uint32_t)0x00000001)        /*!< ADC enable control */
+
+/*******************  Bits definition for ADC_CFGR1 register  *****************/
+#define  ADC_CFGR1_AWDCH                      ((uint32_t)0x7C000000)       /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CFGR1_AWDCH_0                    ((uint32_t)0x04000000)       /*!< Bit 0 */
+#define  ADC_CFGR1_AWDCH_1                    ((uint32_t)0x08000000)       /*!< Bit 1 */
+#define  ADC_CFGR1_AWDCH_2                    ((uint32_t)0x10000000)       /*!< Bit 2 */
+#define  ADC_CFGR1_AWDCH_3                    ((uint32_t)0x20000000)       /*!< Bit 3 */
+#define  ADC_CFGR1_AWDCH_4                    ((uint32_t)0x40000000)       /*!< Bit 4 */
+#define  ADC_CFGR1_AWDEN                      ((uint32_t)0x00800000)       /*!< Analog watchdog enable on regular channels */
+#define  ADC_CFGR1_AWDSGL                     ((uint32_t)0x00400000)       /*!< Enable the watchdog on a single channel or on all channels  */
+#define  ADC_CFGR1_DISCEN                     ((uint32_t)0x00010000)       /*!< Discontinuous mode on regular channels */
+#define  ADC_CFGR1_AUTOFF                     ((uint32_t)0x00008000)       /*!< ADC auto power off */
+#define  ADC_CFGR1_WAIT                       ((uint32_t)0x00004000)       /*!< ADC wait conversion mode */
+#define  ADC_CFGR1_CONT                       ((uint32_t)0x00002000)       /*!< Continuous Conversion */
+#define  ADC_CFGR1_OVRMOD                     ((uint32_t)0x00001000)       /*!< Overrun mode */
+#define  ADC_CFGR1_EXTEN                      ((uint32_t)0x00000C00)       /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define  ADC_CFGR1_EXTEN_0                    ((uint32_t)0x00000400)       /*!< Bit 0 */
+#define  ADC_CFGR1_EXTEN_1                    ((uint32_t)0x00000800)       /*!< Bit 1 */
+#define  ADC_CFGR1_EXTSEL                     ((uint32_t)0x000001C0)       /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define  ADC_CFGR1_EXTSEL_0                   ((uint32_t)0x00000040)       /*!< Bit 0 */
+#define  ADC_CFGR1_EXTSEL_1                   ((uint32_t)0x00000080)       /*!< Bit 1 */
+#define  ADC_CFGR1_EXTSEL_2                   ((uint32_t)0x00000100)       /*!< Bit 2 */
+#define  ADC_CFGR1_ALIGN                      ((uint32_t)0x00000020)       /*!< Data Alignment */
+#define  ADC_CFGR1_RES                        ((uint32_t)0x00000018)       /*!< RES[1:0] bits (Resolution) */
+#define  ADC_CFGR1_RES_0                      ((uint32_t)0x00000008)       /*!< Bit 0 */
+#define  ADC_CFGR1_RES_1                      ((uint32_t)0x00000010)       /*!< Bit 1 */
+#define  ADC_CFGR1_SCANDIR                    ((uint32_t)0x00000004)       /*!< Sequence scan direction */
+#define  ADC_CFGR1_DMACFG                     ((uint32_t)0x00000002)       /*!< Direct memory access configuration */
+#define  ADC_CFGR1_DMAEN                      ((uint32_t)0x00000001)       /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define  ADC_CFGR1_AUTDLY                     ADC_CFGR1_WAIT
+
+/*******************  Bits definition for ADC_CFGR2 register  *****************/
+#define  ADC_CFGR2_CKMODE                     ((uint32_t)0xC0000000)       /*!< ADC clock mode */
+#define  ADC_CFGR2_CKMODE_1                   ((uint32_t)0x80000000)       /*!< ADC clocked by PCLK div4 */
+#define  ADC_CFGR2_CKMODE_0                   ((uint32_t)0x40000000)       /*!< ADC clocked by PCLK div2 */
+
+/* Old bit definition, maintained for legacy purpose */
+#define  ADC_CFGR2_JITOFFDIV4                 ADC_CFGR2_CKMODE_1           /*!< ADC clocked by PCLK div4 */
+#define  ADC_CFGR2_JITOFFDIV2                 ADC_CFGR2_CKMODE_0           /*!< ADC clocked by PCLK div2 */
+
+/******************  Bit definition for ADC_SMPR register  ********************/
+#define  ADC_SMPR_SMP                      ((uint32_t)0x00000007)        /*!< SMP[2:0] bits (Sampling time selection) */
+#define  ADC_SMPR_SMP_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SMPR_SMP_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SMPR_SMP_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
+
+/* Old bit definition, maintained for legacy purpose */
+#define  ADC_SMPR1_SMPR                      ADC_SMPR_SMP        /*!< SMP[2:0] bits (Sampling time selection) */
+#define  ADC_SMPR1_SMPR_0                    ADC_SMPR_SMP_0        /*!< Bit 0 */
+#define  ADC_SMPR1_SMPR_1                    ADC_SMPR_SMP_1        /*!< Bit 1 */
+#define  ADC_SMPR1_SMPR_2                    ADC_SMPR_SMP_2        /*!< Bit 2 */
+
+/*******************  Bit definition for ADC_TR register  ********************/
+#define  ADC_TR_HT                          ((uint32_t)0x0FFF0000)        /*!< Analog watchdog high threshold */
+#define  ADC_TR_LT                          ((uint32_t)0x00000FFF)        /*!< Analog watchdog low threshold */
+
+/* Old bit definition, maintained for legacy purpose */
+#define  ADC_HTR_HT                          ADC_TR_HT                    /*!< Analog watchdog high threshold */
+#define  ADC_LTR_LT                          ADC_TR_LT                    /*!< Analog watchdog low threshold */
+
+/******************  Bit definition for ADC_CHSELR register  ******************/
+#define  ADC_CHSELR_CHSEL18                   ((uint32_t)0x00040000)        /*!< Channel 18 selection */
+#define  ADC_CHSELR_CHSEL17                   ((uint32_t)0x00020000)        /*!< Channel 17 selection */
+#define  ADC_CHSELR_CHSEL16                   ((uint32_t)0x00010000)        /*!< Channel 16 selection */
+#define  ADC_CHSELR_CHSEL15                   ((uint32_t)0x00008000)        /*!< Channel 15 selection */
+#define  ADC_CHSELR_CHSEL14                   ((uint32_t)0x00004000)        /*!< Channel 14 selection */
+#define  ADC_CHSELR_CHSEL13                   ((uint32_t)0x00002000)        /*!< Channel 13 selection */
+#define  ADC_CHSELR_CHSEL12                   ((uint32_t)0x00001000)        /*!< Channel 12 selection */
+#define  ADC_CHSELR_CHSEL11                   ((uint32_t)0x00000800)        /*!< Channel 11 selection */
+#define  ADC_CHSELR_CHSEL10                   ((uint32_t)0x00000400)        /*!< Channel 10 selection */
+#define  ADC_CHSELR_CHSEL9                    ((uint32_t)0x00000200)        /*!< Channel 9 selection */
+#define  ADC_CHSELR_CHSEL8                    ((uint32_t)0x00000100)        /*!< Channel 8 selection */
+#define  ADC_CHSELR_CHSEL7                    ((uint32_t)0x00000080)        /*!< Channel 7 selection */
+#define  ADC_CHSELR_CHSEL6                    ((uint32_t)0x00000040)        /*!< Channel 6 selection */
+#define  ADC_CHSELR_CHSEL5                    ((uint32_t)0x00000020)        /*!< Channel 5 selection */
+#define  ADC_CHSELR_CHSEL4                    ((uint32_t)0x00000010)        /*!< Channel 4 selection */
+#define  ADC_CHSELR_CHSEL3                    ((uint32_t)0x00000008)        /*!< Channel 3 selection */
+#define  ADC_CHSELR_CHSEL2                    ((uint32_t)0x00000004)        /*!< Channel 2 selection */
+#define  ADC_CHSELR_CHSEL1                    ((uint32_t)0x00000002)        /*!< Channel 1 selection */
+#define  ADC_CHSELR_CHSEL0                    ((uint32_t)0x00000001)        /*!< Channel 0 selection */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */
+
+/*******************  Bit definition for ADC_CCR register  ********************/
+#define  ADC_CCR_VBATEN                       ((uint32_t)0x01000000)       /*!< Voltage battery enable */
+#define  ADC_CCR_TSEN                         ((uint32_t)0x00800000)       /*!< Tempurature sensore enable */
+#define  ADC_CCR_VREFEN                       ((uint32_t)0x00400000)       /*!< Vrefint enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                   Controller Area Network (CAN )                           */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CAN_MCR register  ********************/
+#define  CAN_MCR_INRQ                        ((uint16_t)0x0001)            /*!<Initialization Request */
+#define  CAN_MCR_SLEEP                       ((uint16_t)0x0002)            /*!<Sleep Mode Request */
+#define  CAN_MCR_TXFP                        ((uint16_t)0x0004)            /*!<Transmit FIFO Priority */
+#define  CAN_MCR_RFLM                        ((uint16_t)0x0008)            /*!<Receive FIFO Locked Mode */
+#define  CAN_MCR_NART                        ((uint16_t)0x0010)            /*!<No Automatic Retransmission */
+#define  CAN_MCR_AWUM                        ((uint16_t)0x0020)            /*!<Automatic Wakeup Mode */
+#define  CAN_MCR_ABOM                        ((uint16_t)0x0040)            /*!<Automatic Bus-Off Management */
+#define  CAN_MCR_TTCM                        ((uint16_t)0x0080)            /*!<Time Triggered Communication Mode */
+#define  CAN_MCR_RESET                       ((uint16_t)0x8000)            /*!<bxCAN software master reset */
+
+/*******************  Bit definition for CAN_MSR register  ********************/
+#define  CAN_MSR_INAK                        ((uint16_t)0x0001)            /*!<Initialization Acknowledge */
+#define  CAN_MSR_SLAK                        ((uint16_t)0x0002)            /*!<Sleep Acknowledge */
+#define  CAN_MSR_ERRI                        ((uint16_t)0x0004)            /*!<Error Interrupt */
+#define  CAN_MSR_WKUI                        ((uint16_t)0x0008)            /*!<Wakeup Interrupt */
+#define  CAN_MSR_SLAKI                       ((uint16_t)0x0010)            /*!<Sleep Acknowledge Interrupt */
+#define  CAN_MSR_TXM                         ((uint16_t)0x0100)            /*!<Transmit Mode */
+#define  CAN_MSR_RXM                         ((uint16_t)0x0200)            /*!<Receive Mode */
+#define  CAN_MSR_SAMP                        ((uint16_t)0x0400)            /*!<Last Sample Point */
+#define  CAN_MSR_RX                          ((uint16_t)0x0800)            /*!<CAN Rx Signal */
+
+/*******************  Bit definition for CAN_TSR register  ********************/
+#define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001)        /*!<Request Completed Mailbox0 */
+#define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002)        /*!<Transmission OK of Mailbox0 */
+#define  CAN_TSR_ALST0                       ((uint32_t)0x00000004)        /*!<Arbitration Lost for Mailbox0 */
+#define  CAN_TSR_TERR0                       ((uint32_t)0x00000008)        /*!<Transmission Error of Mailbox0 */
+#define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080)        /*!<Abort Request for Mailbox0 */
+#define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100)        /*!<Request Completed Mailbox1 */
+#define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200)        /*!<Transmission OK of Mailbox1 */
+#define  CAN_TSR_ALST1                       ((uint32_t)0x00000400)        /*!<Arbitration Lost for Mailbox1 */
+#define  CAN_TSR_TERR1                       ((uint32_t)0x00000800)        /*!<Transmission Error of Mailbox1 */
+#define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000)        /*!<Abort Request for Mailbox 1 */
+#define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000)        /*!<Request Completed Mailbox2 */
+#define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000)        /*!<Transmission OK of Mailbox 2 */
+#define  CAN_TSR_ALST2                       ((uint32_t)0x00040000)        /*!<Arbitration Lost for mailbox 2 */
+#define  CAN_TSR_TERR2                       ((uint32_t)0x00080000)        /*!<Transmission Error of Mailbox 2 */
+#define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000)        /*!<Abort Request for Mailbox 2 */
+#define  CAN_TSR_CODE                        ((uint32_t)0x03000000)        /*!<Mailbox Code */
+
+#define  CAN_TSR_TME                         ((uint32_t)0x1C000000)        /*!<TME[2:0] bits */
+#define  CAN_TSR_TME0                        ((uint32_t)0x04000000)        /*!<Transmit Mailbox 0 Empty */
+#define  CAN_TSR_TME1                        ((uint32_t)0x08000000)        /*!<Transmit Mailbox 1 Empty */
+#define  CAN_TSR_TME2                        ((uint32_t)0x10000000)        /*!<Transmit Mailbox 2 Empty */
+
+#define  CAN_TSR_LOW                         ((uint32_t)0xE0000000)        /*!<LOW[2:0] bits */
+#define  CAN_TSR_LOW0                        ((uint32_t)0x20000000)        /*!<Lowest Priority Flag for Mailbox 0 */
+#define  CAN_TSR_LOW1                        ((uint32_t)0x40000000)        /*!<Lowest Priority Flag for Mailbox 1 */
+#define  CAN_TSR_LOW2                        ((uint32_t)0x80000000)        /*!<Lowest Priority Flag for Mailbox 2 */
+
+/*******************  Bit definition for CAN_RF0R register  *******************/
+#define  CAN_RF0R_FMP0                       ((uint8_t)0x03)               /*!<FIFO 0 Message Pending */
+#define  CAN_RF0R_FULL0                      ((uint8_t)0x08)               /*!<FIFO 0 Full */
+#define  CAN_RF0R_FOVR0                      ((uint8_t)0x10)               /*!<FIFO 0 Overrun */
+#define  CAN_RF0R_RFOM0                      ((uint8_t)0x20)               /*!<Release FIFO 0 Output Mailbox */
+
+/*******************  Bit definition for CAN_RF1R register  *******************/
+#define  CAN_RF1R_FMP1                       ((uint8_t)0x03)               /*!<FIFO 1 Message Pending */
+#define  CAN_RF1R_FULL1                      ((uint8_t)0x08)               /*!<FIFO 1 Full */
+#define  CAN_RF1R_FOVR1                      ((uint8_t)0x10)               /*!<FIFO 1 Overrun */
+#define  CAN_RF1R_RFOM1                      ((uint8_t)0x20)               /*!<Release FIFO 1 Output Mailbox */
+
+/********************  Bit definition for CAN_IER register  *******************/
+#define  CAN_IER_TMEIE                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Empty Interrupt Enable */
+#define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002)        /*!<FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE0                       ((uint32_t)0x00000004)        /*!<FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008)        /*!<FIFO Overrun Interrupt Enable */
+#define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010)        /*!<FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE1                       ((uint32_t)0x00000020)        /*!<FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040)        /*!<FIFO Overrun Interrupt Enable */
+#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100)        /*!<Error Warning Interrupt Enable */
+#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200)        /*!<Error Passive Interrupt Enable */
+#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400)        /*!<Bus-Off Interrupt Enable */
+#define  CAN_IER_LECIE                       ((uint32_t)0x00000800)        /*!<Last Error Code Interrupt Enable */
+#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000)        /*!<Error Interrupt Enable */
+#define  CAN_IER_WKUIE                       ((uint32_t)0x00010000)        /*!<Wakeup Interrupt Enable */
+#define  CAN_IER_SLKIE                       ((uint32_t)0x00020000)        /*!<Sleep Interrupt Enable */
+
+/********************  Bit definition for CAN_ESR register  *******************/
+#define  CAN_ESR_EWGF                        ((uint32_t)0x00000001)        /*!<Error Warning Flag */
+#define  CAN_ESR_EPVF                        ((uint32_t)0x00000002)        /*!<Error Passive Flag */
+#define  CAN_ESR_BOFF                        ((uint32_t)0x00000004)        /*!<Bus-Off Flag */
+
+#define  CAN_ESR_LEC                         ((uint32_t)0x00000070)        /*!<LEC[2:0] bits (Last Error Code) */
+#define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040)        /*!<Bit 2 */
+
+#define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000)        /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define  CAN_ESR_REC                         ((uint32_t)0xFF000000)        /*!<Receive Error Counter */
+
+/*******************  Bit definition for CAN_BTR register  ********************/
+#define  CAN_BTR_BRP                         ((uint32_t)0x000003FF)        /*!<Baud Rate Prescaler */
+#define  CAN_BTR_TS1                         ((uint32_t)0x000F0000)        /*!<Time Segment 1 */
+#define  CAN_BTR_TS2                         ((uint32_t)0x00700000)        /*!<Time Segment 2 */
+#define  CAN_BTR_SJW                         ((uint32_t)0x03000000)        /*!<Resynchronization Jump Width */
+#define  CAN_BTR_LBKM                        ((uint32_t)0x40000000)        /*!<Loop Back Mode (Debug) */
+#define  CAN_BTR_SILM                        ((uint32_t)0x80000000)        /*!<Silent Mode */
+
+/*!<Mailbox registers */
+/******************  Bit definition for CAN_TI0R register  ********************/
+#define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
+#define  CAN_TI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
+#define  CAN_TI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
+#define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
+#define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/******************  Bit definition for CAN_TDT0R register  *******************/
+#define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
+#define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/******************  Bit definition for CAN_TDL0R register  *******************/
+#define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/******************  Bit definition for CAN_TDH0R register  *******************/
+#define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI1R register  *******************/
+#define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
+#define  CAN_TI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
+#define  CAN_TI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
+#define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
+#define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT1R register  ******************/
+#define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
+#define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL1R register  ******************/
+#define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH1R register  ******************/
+#define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI2R register  *******************/
+#define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
+#define  CAN_TI2R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
+#define  CAN_TI2R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
+#define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
+#define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT2R register  ******************/  
+#define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
+#define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL2R register  ******************/
+#define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH2R register  ******************/
+#define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI0R register  *******************/
+#define  CAN_RI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
+#define  CAN_RI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
+#define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
+#define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT0R register  ******************/
+#define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
+#define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL0R register  ******************/
+#define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH0R register  ******************/
+#define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI1R register  *******************/
+#define  CAN_RI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
+#define  CAN_RI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
+#define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
+#define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT1R register  ******************/
+#define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
+#define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL1R register  ******************/
+#define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH1R register  ******************/
+#define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/*******************  Bit definition for CAN_FMR register  ********************/
+#define  CAN_FMR_FINIT                       ((uint8_t)0x01)               /*!<Filter Init Mode */
+
+/*******************  Bit definition for CAN_FM1R register  *******************/
+#define  CAN_FM1R_FBM                        ((uint16_t)0x3FFF)            /*!<Filter Mode */
+#define  CAN_FM1R_FBM0                       ((uint16_t)0x0001)            /*!<Filter Init Mode bit 0 */
+#define  CAN_FM1R_FBM1                       ((uint16_t)0x0002)            /*!<Filter Init Mode bit 1 */
+#define  CAN_FM1R_FBM2                       ((uint16_t)0x0004)            /*!<Filter Init Mode bit 2 */
+#define  CAN_FM1R_FBM3                       ((uint16_t)0x0008)            /*!<Filter Init Mode bit 3 */
+#define  CAN_FM1R_FBM4                       ((uint16_t)0x0010)            /*!<Filter Init Mode bit 4 */
+#define  CAN_FM1R_FBM5                       ((uint16_t)0x0020)            /*!<Filter Init Mode bit 5 */
+#define  CAN_FM1R_FBM6                       ((uint16_t)0x0040)            /*!<Filter Init Mode bit 6 */
+#define  CAN_FM1R_FBM7                       ((uint16_t)0x0080)            /*!<Filter Init Mode bit 7 */
+#define  CAN_FM1R_FBM8                       ((uint16_t)0x0100)            /*!<Filter Init Mode bit 8 */
+#define  CAN_FM1R_FBM9                       ((uint16_t)0x0200)            /*!<Filter Init Mode bit 9 */
+#define  CAN_FM1R_FBM10                      ((uint16_t)0x0400)            /*!<Filter Init Mode bit 10 */
+#define  CAN_FM1R_FBM11                      ((uint16_t)0x0800)            /*!<Filter Init Mode bit 11 */
+#define  CAN_FM1R_FBM12                      ((uint16_t)0x1000)            /*!<Filter Init Mode bit 12 */
+#define  CAN_FM1R_FBM13                      ((uint16_t)0x2000)            /*!<Filter Init Mode bit 13 */
+
+/*******************  Bit definition for CAN_FS1R register  *******************/
+#define  CAN_FS1R_FSC                        ((uint16_t)0x3FFF)            /*!<Filter Scale Configuration */
+#define  CAN_FS1R_FSC0                       ((uint16_t)0x0001)            /*!<Filter Scale Configuration bit 0 */
+#define  CAN_FS1R_FSC1                       ((uint16_t)0x0002)            /*!<Filter Scale Configuration bit 1 */
+#define  CAN_FS1R_FSC2                       ((uint16_t)0x0004)            /*!<Filter Scale Configuration bit 2 */
+#define  CAN_FS1R_FSC3                       ((uint16_t)0x0008)            /*!<Filter Scale Configuration bit 3 */
+#define  CAN_FS1R_FSC4                       ((uint16_t)0x0010)            /*!<Filter Scale Configuration bit 4 */
+#define  CAN_FS1R_FSC5                       ((uint16_t)0x0020)            /*!<Filter Scale Configuration bit 5 */
+#define  CAN_FS1R_FSC6                       ((uint16_t)0x0040)            /*!<Filter Scale Configuration bit 6 */
+#define  CAN_FS1R_FSC7                       ((uint16_t)0x0080)            /*!<Filter Scale Configuration bit 7 */
+#define  CAN_FS1R_FSC8                       ((uint16_t)0x0100)            /*!<Filter Scale Configuration bit 8 */
+#define  CAN_FS1R_FSC9                       ((uint16_t)0x0200)            /*!<Filter Scale Configuration bit 9 */
+#define  CAN_FS1R_FSC10                      ((uint16_t)0x0400)            /*!<Filter Scale Configuration bit 10 */
+#define  CAN_FS1R_FSC11                      ((uint16_t)0x0800)            /*!<Filter Scale Configuration bit 11 */
+#define  CAN_FS1R_FSC12                      ((uint16_t)0x1000)            /*!<Filter Scale Configuration bit 12 */
+#define  CAN_FS1R_FSC13                      ((uint16_t)0x2000)            /*!<Filter Scale Configuration bit 13 */
+
+/******************  Bit definition for CAN_FFA1R register  *******************/
+#define  CAN_FFA1R_FFA                       ((uint16_t)0x3FFF)            /*!<Filter FIFO Assignment */
+#define  CAN_FFA1R_FFA0                      ((uint16_t)0x0001)            /*!<Filter FIFO Assignment for Filter 0 */
+#define  CAN_FFA1R_FFA1                      ((uint16_t)0x0002)            /*!<Filter FIFO Assignment for Filter 1 */
+#define  CAN_FFA1R_FFA2                      ((uint16_t)0x0004)            /*!<Filter FIFO Assignment for Filter 2 */
+#define  CAN_FFA1R_FFA3                      ((uint16_t)0x0008)            /*!<Filter FIFO Assignment for Filter 3 */
+#define  CAN_FFA1R_FFA4                      ((uint16_t)0x0010)            /*!<Filter FIFO Assignment for Filter 4 */
+#define  CAN_FFA1R_FFA5                      ((uint16_t)0x0020)            /*!<Filter FIFO Assignment for Filter 5 */
+#define  CAN_FFA1R_FFA6                      ((uint16_t)0x0040)            /*!<Filter FIFO Assignment for Filter 6 */
+#define  CAN_FFA1R_FFA7                      ((uint16_t)0x0080)            /*!<Filter FIFO Assignment for Filter 7 */
+#define  CAN_FFA1R_FFA8                      ((uint16_t)0x0100)            /*!<Filter FIFO Assignment for Filter 8 */
+#define  CAN_FFA1R_FFA9                      ((uint16_t)0x0200)            /*!<Filter FIFO Assignment for Filter 9 */
+#define  CAN_FFA1R_FFA10                     ((uint16_t)0x0400)            /*!<Filter FIFO Assignment for Filter 10 */
+#define  CAN_FFA1R_FFA11                     ((uint16_t)0x0800)            /*!<Filter FIFO Assignment for Filter 11 */
+#define  CAN_FFA1R_FFA12                     ((uint16_t)0x1000)            /*!<Filter FIFO Assignment for Filter 12 */
+#define  CAN_FFA1R_FFA13                     ((uint16_t)0x2000)            /*!<Filter FIFO Assignment for Filter 13 */
+
+/*******************  Bit definition for CAN_FA1R register  *******************/
+#define  CAN_FA1R_FACT                       ((uint16_t)0x3FFF)            /*!<Filter Active */
+#define  CAN_FA1R_FACT0                      ((uint16_t)0x0001)            /*!<Filter 0 Active */
+#define  CAN_FA1R_FACT1                      ((uint16_t)0x0002)            /*!<Filter 1 Active */
+#define  CAN_FA1R_FACT2                      ((uint16_t)0x0004)            /*!<Filter 2 Active */
+#define  CAN_FA1R_FACT3                      ((uint16_t)0x0008)            /*!<Filter 3 Active */
+#define  CAN_FA1R_FACT4                      ((uint16_t)0x0010)            /*!<Filter 4 Active */
+#define  CAN_FA1R_FACT5                      ((uint16_t)0x0020)            /*!<Filter 5 Active */
+#define  CAN_FA1R_FACT6                      ((uint16_t)0x0040)            /*!<Filter 6 Active */
+#define  CAN_FA1R_FACT7                      ((uint16_t)0x0080)            /*!<Filter 7 Active */
+#define  CAN_FA1R_FACT8                      ((uint16_t)0x0100)            /*!<Filter 8 Active */
+#define  CAN_FA1R_FACT9                      ((uint16_t)0x0200)            /*!<Filter 9 Active */
+#define  CAN_FA1R_FACT10                     ((uint16_t)0x0400)            /*!<Filter 10 Active */
+#define  CAN_FA1R_FACT11                     ((uint16_t)0x0800)            /*!<Filter 11 Active */
+#define  CAN_FA1R_FACT12                     ((uint16_t)0x1000)            /*!<Filter 12 Active */
+#define  CAN_FA1R_FACT13                     ((uint16_t)0x2000)            /*!<Filter 13 Active */
+
+/*******************  Bit definition for CAN_F0R1 register  *******************/
+#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R1 register  *******************/
+#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R1 register  *******************/
+#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R1 register  *******************/
+#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R1 register  *******************/
+#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R1 register  *******************/
+#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R1 register  *******************/
+#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R1 register  *******************/
+#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R1 register  *******************/
+#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R1 register  *******************/
+#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R1 register  ******************/
+#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R1 register  ******************/
+#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R1 register  ******************/
+#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R1 register  ******************/
+#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F0R2 register  *******************/
+#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R2 register  *******************/
+#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R2 register  *******************/
+#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R2 register  *******************/
+#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R2 register  *******************/
+#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R2 register  *******************/
+#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R2 register  *******************/
+#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R2 register  *******************/
+#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R2 register  *******************/
+#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R2 register  *******************/
+#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R2 register  ******************/
+#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R2 register  ******************/
+#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R2 register  ******************/
+#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R2 register  ******************/
+#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 HDMI-CEC (CEC)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for CEC_CR register  *********************/
+#define  CEC_CR_CECEN                        ((uint32_t)0x00000001)       /*!< CEC Enable                         */
+#define  CEC_CR_TXSOM                        ((uint32_t)0x00000002)       /*!< CEC Tx Start Of Message            */
+#define  CEC_CR_TXEOM                        ((uint32_t)0x00000004)       /*!< CEC Tx End Of Message              */
+
+/*******************  Bit definition for CEC_CFGR register  *******************/
+#define  CEC_CFGR_SFT                        ((uint32_t)0x00000007)       /*!< CEC Signal Free Time               */
+#define  CEC_CFGR_RXTOL                      ((uint32_t)0x00000008)       /*!< CEC Tolerance                      */
+#define  CEC_CFGR_BRESTP                     ((uint32_t)0x00000010)       /*!< CEC Rx Stop                        */
+#define  CEC_CFGR_BREGEN                     ((uint32_t)0x00000020)       /*!< CEC Bit Rising Error generation    */
+#define  CEC_CFGR_LREGEN                     ((uint32_t)0x00000040)       /*!< CEC Long Period Error generation   */
+#define  CEC_CFGR_BRDNOGEN                   ((uint32_t)0x00000080)       /*!< CEC Broadcast no Error generation  */
+#define  CEC_CFGR_SFTOPT                     ((uint32_t)0x00000100)       /*!< CEC Signal Free Time optional      */
+#define  CEC_CFGR_OAR                        ((uint32_t)0x7FFF0000)       /*!< CEC Own Address                    */
+#define  CEC_CFGR_LSTN                       ((uint32_t)0x80000000)       /*!< CEC Listen mode                    */
+
+/*******************  Bit definition for CEC_TXDR register  *******************/
+#define  CEC_TXDR_TXD                        ((uint32_t)0x000000FF)       /*!< CEC Tx Data                        */
+
+/*******************  Bit definition for CEC_RXDR register  *******************/
+#define  CEC_TXDR_RXD                        ((uint32_t)0x000000FF)       /*!< CEC Rx Data                        */
+
+/*******************  Bit definition for CEC_ISR register  ********************/
+#define  CEC_ISR_RXBR                        ((uint32_t)0x00000001)       /*!< CEC Rx-Byte Received                   */
+#define  CEC_ISR_RXEND                       ((uint32_t)0x00000002)       /*!< CEC End Of Reception                   */
+#define  CEC_ISR_RXOVR                       ((uint32_t)0x00000004)       /*!< CEC Rx-Overrun                         */
+#define  CEC_ISR_BRE                         ((uint32_t)0x00000008)       /*!< CEC Rx Bit Rising Error                */
+#define  CEC_ISR_SBPE                        ((uint32_t)0x00000010)       /*!< CEC Rx Short Bit period Error          */
+#define  CEC_ISR_LBPE                        ((uint32_t)0x00000020)       /*!< CEC Rx Long Bit period Error           */
+#define  CEC_ISR_RXACKE                      ((uint32_t)0x00000040)       /*!< CEC Rx Missing Acknowledge             */
+#define  CEC_ISR_ARBLST                      ((uint32_t)0x00000080)       /*!< CEC Arbitration Lost                   */
+#define  CEC_ISR_TXBR                        ((uint32_t)0x00000100)       /*!< CEC Tx Byte Request                    */
+#define  CEC_ISR_TXEND                       ((uint32_t)0x00000200)       /*!< CEC End of Transmission                */
+#define  CEC_ISR_TXUDR                       ((uint32_t)0x00000400)       /*!< CEC Tx-Buffer Underrun                 */
+#define  CEC_ISR_TXERR                       ((uint32_t)0x00000800)       /*!< CEC Tx-Error                           */
+#define  CEC_ISR_TXACKE                      ((uint32_t)0x00001000)       /*!< CEC Tx Missing Acknowledge             */
+
+/*******************  Bit definition for CEC_IER register  ********************/
+#define  CEC_IER_RXBRIE                      ((uint32_t)0x00000001)       /*!< CEC Rx-Byte Received IT Enable         */
+#define  CEC_IER_RXENDIE                     ((uint32_t)0x00000002)       /*!< CEC End Of Reception IT Enable         */
+#define  CEC_IER_RXOVRIE                     ((uint32_t)0x00000004)       /*!< CEC Rx-Overrun IT Enable               */
+#define  CEC_IER_BREIEIE                     ((uint32_t)0x00000008)       /*!< CEC Rx Bit Rising Error IT Enable      */
+#define  CEC_IER_SBPEIE                      ((uint32_t)0x00000010)       /*!< CEC Rx Short Bit period Error IT Enable*/
+#define  CEC_IER_LBPEIE                      ((uint32_t)0x00000020)       /*!< CEC Rx Long Bit period Error IT Enable */
+#define  CEC_IER_RXACKEIE                    ((uint32_t)0x00000040)       /*!< CEC Rx Missing Acknowledge IT Enable   */
+#define  CEC_IER_ARBLSTIE                    ((uint32_t)0x00000080)       /*!< CEC Arbitration Lost IT Enable         */
+#define  CEC_IER_TXBRIE                      ((uint32_t)0x00000100)       /*!< CEC Tx Byte Request  IT Enable         */
+#define  CEC_IER_TXENDIE                     ((uint32_t)0x00000200)       /*!< CEC End of Transmission IT Enable      */
+#define  CEC_IER_TXUDRIE                     ((uint32_t)0x00000400)       /*!< CEC Tx-Buffer Underrun IT Enable       */
+#define  CEC_IER_TXERRIE                     ((uint32_t)0x00000800)       /*!< CEC Tx-Error IT Enable                 */
+#define  CEC_IER_TXACKEIE                    ((uint32_t)0x00001000)       /*!< CEC Tx Missing Acknowledge IT Enable   */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+/***********************  Bit definition for COMP_CSR register  ***************/
+/* COMP1 bits definition */
+#define COMP_CSR_COMP1EN               ((uint32_t)0x00000001) /*!< COMP1 enable */
+#define COMP_CSR_COMP1SW1              ((uint32_t)0x00000002) /*!< SW1 switch control */
+#define COMP_CSR_COMP1MODE             ((uint32_t)0x0000000C) /*!< COMP1 power mode */
+#define COMP_CSR_COMP1MODE_0           ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
+#define COMP_CSR_COMP1MODE_1           ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
+#define COMP_CSR_COMP1INSEL            ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
+#define COMP_CSR_COMP1INSEL_0          ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
+#define COMP_CSR_COMP1INSEL_1          ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
+#define COMP_CSR_COMP1INSEL_2          ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
+#define COMP_CSR_COMP1OUTSEL           ((uint32_t)0x00000700) /*!< COMP1 output select */
+#define COMP_CSR_COMP1OUTSEL_0         ((uint32_t)0x00000100) /*!< COMP1 output select bit 0 */
+#define COMP_CSR_COMP1OUTSEL_1         ((uint32_t)0x00000200) /*!< COMP1 output select bit 1 */
+#define COMP_CSR_COMP1OUTSEL_2         ((uint32_t)0x00000400) /*!< COMP1 output select bit 2 */
+#define COMP_CSR_COMP1POL              ((uint32_t)0x00000800) /*!< COMP1 output polarity */
+#define COMP_CSR_COMP1HYST             ((uint32_t)0x00003000) /*!< COMP1 hysteresis */
+#define COMP_CSR_COMP1HYST_0           ((uint32_t)0x00001000) /*!< COMP1 hysteresis bit 0 */
+#define COMP_CSR_COMP1HYST_1           ((uint32_t)0x00002000) /*!< COMP1 hysteresis bit 1 */
+#define COMP_CSR_COMP1OUT              ((uint32_t)0x00004000) /*!< COMP1 output level */
+#define COMP_CSR_COMP1LOCK             ((uint32_t)0x00008000) /*!< COMP1 lock */
+/* COMP2 bits definition */
+#define COMP_CSR_COMP2EN               ((uint32_t)0x00010000) /*!< COMP2 enable */
+#define COMP_CSR_COMP2MODE             ((uint32_t)0x000C0000) /*!< COMP2 power mode */
+#define COMP_CSR_COMP2MODE_0           ((uint32_t)0x00040000) /*!< COMP2 power mode bit 0 */
+#define COMP_CSR_COMP2MODE_1           ((uint32_t)0x00080000) /*!< COMP2 power mode bit 1 */
+#define COMP_CSR_COMP2INSEL            ((uint32_t)0x00700000) /*!< COMP2 inverting input select */
+#define COMP_CSR_COMP2INSEL_0          ((uint32_t)0x00100000) /*!< COMP2 inverting input select bit 0 */
+#define COMP_CSR_COMP2INSEL_1          ((uint32_t)0x00200000) /*!< COMP2 inverting input select bit 1 */
+#define COMP_CSR_COMP2INSEL_2          ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 2 */
+#define COMP_CSR_WNDWEN                ((uint32_t)0x00800000) /*!< Comparators window mode enable */
+#define COMP_CSR_COMP2OUTSEL           ((uint32_t)0x07000000) /*!< COMP2 output select */
+#define COMP_CSR_COMP2OUTSEL_0         ((uint32_t)0x01000000) /*!< COMP2 output select bit 0 */
+#define COMP_CSR_COMP2OUTSEL_1         ((uint32_t)0x02000000) /*!< COMP2 output select bit 1 */
+#define COMP_CSR_COMP2OUTSEL_2         ((uint32_t)0x04000000) /*!< COMP2 output select bit 2 */
+#define COMP_CSR_COMP2POL              ((uint32_t)0x08000000) /*!< COMP2 output polarity */
+#define COMP_CSR_COMP2HYST             ((uint32_t)0x30000000) /*!< COMP2 hysteresis */
+#define COMP_CSR_COMP2HYST_0           ((uint32_t)0x10000000) /*!< COMP2 hysteresis bit 0 */
+#define COMP_CSR_COMP2HYST_1           ((uint32_t)0x20000000) /*!< COMP2 hysteresis bit 1 */
+#define COMP_CSR_COMP2OUT              ((uint32_t)0x40000000) /*!< COMP2 output level */
+#define COMP_CSR_COMP2LOCK             ((uint32_t)0x80000000) /*!< COMP2 lock */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       CRC calculation unit (CRC)                           */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define  CRC_CR_RESET                        ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
+#define  CRC_CR_POLSIZE                      ((uint32_t)0x00000018) /*!< Polynomial size bits (only for STM32F072 devices)*/
+#define  CRC_CR_POLSIZE_0                    ((uint32_t)0x00000008) /*!< Polynomial size bit 0 (only for STM32F072 devices) */
+#define  CRC_CR_POLSIZE_1                    ((uint32_t)0x00000010) /*!< Polynomial size bit 1 (only for STM32F072 devices) */
+#define  CRC_CR_REV_IN                       ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
+#define  CRC_CR_REV_IN_0                     ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
+#define  CRC_CR_REV_IN_1                     ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
+#define  CRC_CR_REV_OUT                      ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define  CRC_INIT_INIT                       ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+#define  CRC_POL_POL                         ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial (only for STM32F072 devices) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRS Clock Recovery System                         */
+/*                   (Available only for STM32F072 devices)                */
+/******************************************************************************/
+
+/*******************  Bit definition for CRS_CR register  *********************/
+#define  CRS_CR_SYNCOKIE                     ((uint32_t)0x00000001) /* SYNC event OK interrupt enable        */
+#define  CRS_CR_SYNCWARNIE                   ((uint32_t)0x00000002) /* SYNC warning interrupt enable         */
+#define  CRS_CR_ERRIE                        ((uint32_t)0x00000004) /* SYNC error interrupt enable           */
+#define  CRS_CR_ESYNCIE                      ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
+#define  CRS_CR_CEN                          ((uint32_t)0x00000020) /* Frequency error counter enable        */
+#define  CRS_CR_AUTOTRIMEN                   ((uint32_t)0x00000040) /* Automatic trimming enable             */
+#define  CRS_CR_SWSYNC                       ((uint32_t)0x00000080) /* A Software SYNC event is generated    */
+#define  CRS_CR_TRIM                         ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming      */
+
+/*******************  Bit definition for CRS_CFGR register  *********************/
+#define  CRS_CFGR_RELOAD                     ((uint32_t)0x0000FFFF) /* Counter reload value               */
+#define  CRS_CFGR_FELIM                      ((uint32_t)0x00FF0000) /* Frequency error limit              */
+#define  CRS_CFGR_SYNCDIV                    ((uint32_t)0x07000000) /* SYNC divider                       */
+#define  CRS_CFGR_SYNCDIV_0                  ((uint32_t)0x01000000) /* Bit 0                              */
+#define  CRS_CFGR_SYNCDIV_1                  ((uint32_t)0x02000000) /* Bit 1                              */
+#define  CRS_CFGR_SYNCDIV_2                  ((uint32_t)0x04000000) /* Bit 2                              */
+#define  CRS_CFGR_SYNCSRC                    ((uint32_t)0x30000000) /* SYNC signal source selection       */
+#define  CRS_CFGR_SYNCSRC_0                  ((uint32_t)0x10000000) /* Bit 0                              */
+#define  CRS_CFGR_SYNCSRC_1                  ((uint32_t)0x20000000) /* Bit 1                              */
+#define  CRS_CFGR_SYNCPOL                    ((uint32_t)0x80000000) /* SYNC polarity selection            */
+
+/*******************  Bit definition for CRS_ISR register  *********************/
+#define  CRS_ISR_SYNCOKF                     ((uint32_t)0x00000001) /* SYNC event OK flag             */
+#define  CRS_ISR_SYNCWARNF                   ((uint32_t)0x00000002) /* SYNC warning                   */
+#define  CRS_ISR_ERRF                        ((uint32_t)0x00000004) /* SYNC error flag                */
+#define  CRS_ISR_ESYNCF                      ((uint32_t)0x00000008) /* Expected SYNC flag             */
+#define  CRS_ISR_SYNCERR                     ((uint32_t)0x00000100) /* SYNC error                     */
+#define  CRS_ISR_SYNCMISS                    ((uint32_t)0x00000200) /* SYNC missed                    */
+#define  CRS_ISR_TRIMOVF                     ((uint32_t)0x00000400) /* Trimming overflow or underflow */
+#define  CRS_ISR_FEDIR                       ((uint32_t)0x00008000) /* Frequency error direction      */
+#define  CRS_ISR_FECAP                       ((uint32_t)0xFFFF0000) /* Frequency error capture        */
+
+/*******************  Bit definition for CRS_ICR register  *********************/
+#define  CRS_ICR_SYNCOKC                     ((uint32_t)0x00000001) /* SYNC event OK clear flag     */
+#define  CRS_ICR_SYNCWARNC                   ((uint32_t)0x00000002) /* SYNC warning clear flag      */
+#define  CRS_ICR_ERRC                        ((uint32_t)0x00000004) /* Error clear flag        */
+#define  CRS_ICR_ESYNCC                      ((uint32_t)0x00000008) /* Expected SYNC clear flag     */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Digital to Analog Converter (DAC)                          */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DAC_CR register  ********************/
+#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!< DAC channel1 enable */
+#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!< DAC channel1 output buffer disable */
+#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!< DAC channel1 Trigger enable */
+
+#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!< Bit 2 */
+
+#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)(only for STM32F072 devices) */
+#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!< Bit 1 */
+
+#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) (only for STM32F072 devices) */
+#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!< DAC channel1 DMA enable */
+#define  DAC_CR_DMAUDRIE1                    ((uint32_t)0x00002000)        /*!<DAC channel1 DMA Underrun Interrupt enable */
+#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!< DAC channel2 enable */
+#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!< DAC channel2 output buffer disable */
+#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!< DAC channel2 Trigger enable */
+
+#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!< Bit 0 */
+#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!< Bit 1 */
+#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!< Bit 2 */
+
+#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!< Bit 0 */
+#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!< Bit 1 */
+
+#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!< DAC channel2 DMA enabled */
+#define  DAC_CR_DMAUDRIE2                    ((uint32_t)0x20000000)        /*!<DAC channel2 DMA Underrun Interrupt enable */
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define  DAC_SWTRIGR_SWTRIG1                 ((uint32_t)0x00000001)        /*!<DAC channel1 software trigger */
+#define  DAC_SWTRIGR_SWTRIG2                 ((uint32_t)0x00000002)        /*!<DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define  DAC_DHR12R1_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define  DAC_DHR12L1_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define  DAC_DHR8R1_DACC1DHR                 ((uint32_t)0x000000FF)         /*!<DAC channel1 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define  DAC_DOR1_DACC1DOR                   ((uint32_t)0x00000FFF)        /*!<DAC channel1 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!< DAC channel1 DMA underrun flag */
+#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!< DAC channel2 DMA underrun flag (only for STM32F072 and STM32F042 devices) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Debug MCU (DBGMCU)                               */
+/*                                                                            */
+/******************************************************************************/
+
+/****************  Bit definition for DBGMCU_IDCODE register  *****************/
+#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */
+
+#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */
+#define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */
+#define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */
+#define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */
+#define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */
+#define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */
+#define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */
+#define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */
+#define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */
+
+/******************  Bit definition for DBGMCU_CR register  *******************/
+#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
+#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */
+
+/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP        ((uint32_t)0x00000001)        /*!< TIM2 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP        ((uint32_t)0x00000002)        /*!< TIM3 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP        ((uint32_t)0x00000010)        /*!< TIM6 counter stopped when core is halted (not available on STM32F042 devices)*/
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP        ((uint32_t)0x00000020)        /*!< TIM7 counter stopped when core is halted (only for STM32F072 devices) */
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP       ((uint32_t)0x00000100)        /*!< TIM14 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP         ((uint32_t)0x00000400)        /*!< RTC Calendar frozen when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP        ((uint32_t)0x00000800)        /*!< Debug Window Watchdog stopped when Core is halted */
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP        ((uint32_t)0x00001000)        /*!< Debug Independent Watchdog stopped when Core is halted */
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00200000)   /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define  DBGMCU_APB1_FZ_DBG_CAN_STOP         ((uint32_t)0x02000000)        /*!< CAN debug stopped when Core is halted (only for STM32F072 devices) */
+
+/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
+#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000800)        /*!< TIM1 counter stopped when core is halted */
+#define  DBGMCU_APB2_FZ_DBG_TIM15_STOP       ((uint32_t)0x00010000)        /*!< TIM15 counter stopped when core is halted (not available on STM32F042 devices) */
+#define  DBGMCU_APB2_FZ_DBG_TIM16_STOP       ((uint32_t)0x00020000)        /*!< TIM16 counter stopped when core is halted */
+#define  DBGMCU_APB2_FZ_DBG_TIM17_STOP       ((uint32_t)0x00040000)        /*!< TIM17 counter stopped when core is halted */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           DMA Controller (DMA)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_ISR register  ********************/
+#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag    */
+#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag   */
+#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag       */
+#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag      */
+#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag    */
+#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag   */
+#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag       */
+#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag      */
+#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag    */
+#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag   */
+#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag       */
+#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag      */
+#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag    */
+#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag   */
+#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag       */
+#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag      */
+#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag    */
+#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag   */
+#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag       */
+#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag      */
+#define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag (only for STM32F072 devices) */
+#define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag (only for STM32F072 devices) */
+#define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag (only for STM32F072 devices) */
+#define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag (only for STM32F072 devices) */
+#define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag (only for STM32F072 devices) */
+#define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag (only for STM32F072 devices) */
+#define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag (only for STM32F072 devices) */
+#define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag (only for STM32F072 devices) */
+
+/*******************  Bit definition for DMA_IFCR register  *******************/
+#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear      */
+#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear      */
+#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear      */
+#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear      */
+#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear      */
+#define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear (only for STM32F072 devices) */
+#define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear (only for STM32F072 devices) */
+#define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear (only for STM32F072 devices) */
+#define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear (only for STM32F072 devices) */
+#define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear (only for STM32F072 devices) */
+#define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear (only for STM32F072 devices) */
+#define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear (only for STM32F072 devices) */
+#define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear (only for STM32F072 devices) */
+
+/*******************  Bit definition for DMA_CCR register  ********************/
+#define  DMA_CCR_EN                          ((uint32_t)0x00000001)        /*!< Channel enable                      */
+#define  DMA_CCR_TCIE                        ((uint32_t)0x00000002)        /*!< Transfer complete interrupt enable  */
+#define  DMA_CCR_HTIE                        ((uint32_t)0x00000004)        /*!< Half Transfer interrupt enable      */
+#define  DMA_CCR_TEIE                        ((uint32_t)0x00000008)        /*!< Transfer error interrupt enable     */
+#define  DMA_CCR_DIR                         ((uint32_t)0x00000010)        /*!< Data transfer direction             */
+#define  DMA_CCR_CIRC                        ((uint32_t)0x00000020)        /*!< Circular mode                       */
+#define  DMA_CCR_PINC                        ((uint32_t)0x00000040)        /*!< Peripheral increment mode           */
+#define  DMA_CCR_MINC                        ((uint32_t)0x00000080)        /*!< Memory increment mode               */
+
+#define  DMA_CCR_PSIZE                       ((uint32_t)0x00000300)        /*!< PSIZE[1:0] bits (Peripheral size)   */
+#define  DMA_CCR_PSIZE_0                     ((uint32_t)0x00000100)        /*!< Bit 0                               */
+#define  DMA_CCR_PSIZE_1                     ((uint32_t)0x00000200)        /*!< Bit 1                               */
+
+#define  DMA_CCR_MSIZE                       ((uint32_t)0x00000C00)        /*!< MSIZE[1:0] bits (Memory size)       */
+#define  DMA_CCR_MSIZE_0                     ((uint32_t)0x00000400)        /*!< Bit 0                               */
+#define  DMA_CCR_MSIZE_1                     ((uint32_t)0x00000800)        /*!< Bit 1                               */
+
+#define  DMA_CCR_PL                          ((uint32_t)0x00003000)        /*!< PL[1:0] bits(Channel Priority level)*/
+#define  DMA_CCR_PL_0                        ((uint32_t)0x00001000)        /*!< Bit 0                               */
+#define  DMA_CCR_PL_1                        ((uint32_t)0x00002000)        /*!< Bit 1                               */
+
+#define  DMA_CCR_MEM2MEM                     ((uint32_t)0x00004000)        /*!< Memory to memory mode               */
+
+/******************  Bit definition for DMA_CNDTR register  *******************/
+#define  DMA_CNDTR_NDT                       ((uint32_t)0x0000FFFF)        /*!< Number of data to Transfer          */
+
+/******************  Bit definition for DMA_CPAR register  ********************/
+#define  DMA_CPAR_PA                         ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+
+/******************  Bit definition for DMA_CMAR register  ********************/
+#define  DMA_CMAR_MA                         ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+
+/******************  Bit definition for DMA_RMPCR1 register  ********************/
+#define DMA_RMPCR1_DEFAULT                  ((uint32_t)0x00000000)        /*!< Default remap position for DMA1 */
+#define DMA_RMPCR1_CH1_ADC                  ((uint32_t)0x00000001)        /*!< Remap ADC on DMA1 Channel 1*/
+#define DMA_RMPCR1_CH1_TIM17_CH1            ((uint32_t)0x00000007)        /*!< Remap TIM17 channel 1 on DMA1 channel 1 */
+#define DMA_RMPCR1_CH1_TIM17_UP             ((uint32_t)0x00000007)        /*!< Remap TIM17 up on DMA1 channel 1 */
+#define DMA_RMPCR1_CH1_USART1_RX            ((uint32_t)0x00000008)        /*!< Remap USART1 Rx on DMA1 channel 1 */
+#define DMA_RMPCR1_CH1_USART2_RX            ((uint32_t)0x00000009)        /*!< Remap USART2 Rx on DMA1 channel 1 */
+#define DMA_RMPCR1_CH1_USART3_RX            ((uint32_t)0x0000000A)        /*!< Remap USART3 Rx on DMA1 channel 1 */
+#define DMA_RMPCR1_CH1_USART4_RX            ((uint32_t)0x0000000B)        /*!< Remap USART4 Rx on DMA1 channel 1 */
+#define DMA_RMPCR1_CH1_USART5_RX            ((uint32_t)0x0000000C)        /*!< Remap USART5 Rx on DMA1 channel 1 */
+#define DMA_RMPCR1_CH1_USART6_RX            ((uint32_t)0x0000000D)        /*!< Remap USART6 Rx on DMA1 channel 1 */
+#define DMA_RMPCR1_CH1_USART7_RX            ((uint32_t)0x0000000E)        /*!< Remap USART7 Rx on DMA1 channel 1 */
+#define DMA_RMPCR1_CH1_USART8_RX            ((uint32_t)0x0000000F)        /*!< Remap USART8 Rx on DMA1 channel 1 */
+#define DMA_RMPCR1_CH2_ADC                  ((uint32_t)0x00000010)        /*!< Remap ADC on DMA1 channel 2 */
+#define DMA_RMPCR1_CH2_I2C1_TX              ((uint32_t)0x00000020)        /*!< Remap I2C1 Tx on DMA1 channel 2 */
+#define DMA_RMPCR1_CH2_SPI_1RX              ((uint32_t)0x00000030)        /*!< Remap SPI1 Rx on DMA1 channel 2 */
+#define DMA_RMPCR1_CH2_TIM1_CH1             ((uint32_t)0x00000040)        /*!< Remap TIM1 channel 1 on DMA1 channel 2 */
+#define DMA_RMPCR1_CH2_TIM17_CH1            ((uint32_t)0x00000070)        /*!< Remap TIM17 channel 1 on DMA1 channel 2 */
+#define DMA_RMPCR1_CH2_TIM17_UP             ((uint32_t)0x00000070)        /*!< Remap TIM17 up on DMA1 channel 2 */
+#define DMA_RMPCR1_CH2_USART1_TX            ((uint32_t)0x00000080)        /*!< Remap USART1 Tx on DMA1 channel 2 */
+#define DMA_RMPCR1_CH2_USART2_TX            ((uint32_t)0x00000090)        /*!< Remap USART2 Tx on DMA1 channel 2 */
+#define DMA_RMPCR1_CH2_USART3_TX            ((uint32_t)0x000000A0)        /*!< Remap USART3 Tx on DMA1 channel 2 */
+#define DMA_RMPCR1_CH2_USART4_TX            ((uint32_t)0x000000B0)        /*!< Remap USART4 Tx on DMA1 channel 2 */
+#define DMA_RMPCR1_CH2_USART5_TX            ((uint32_t)0x000000C0)        /*!< Remap USART5 Tx on DMA1 channel 2 */
+#define DMA_RMPCR1_CH2_USART6_TX            ((uint32_t)0x000000D0)        /*!< Remap USART6 Tx on DMA1 channel 2 */
+#define DMA_RMPCR1_CH2_USART7_TX            ((uint32_t)0x000000E0)        /*!< Remap USART7 Tx on DMA1 channel 2 */
+#define DMA_RMPCR1_CH2_USART8_TX            ((uint32_t)0x000000F0)        /*!< Remap USART8 Tx on DMA1 channel 2 */
+#define DMA_RMPCR1_CH3_TIM6_UP              ((uint32_t)0x00000100)        /*!< Remap TIM6 up on DMA1 channel 3 */
+#define DMA_RMPCR1_CH3_DAC_CH1              ((uint32_t)0x00000100)        /*!< Remap DAC Channel 1on DMA1 channel 3 */
+#define DMA_RMPCR1_CH3_I2C1_RX              ((uint32_t)0x00000200)        /*!< Remap I2C1 Rx on DMA1 channel 3 */
+#define DMA_RMPCR1_CH3_SPI1_TX              ((uint32_t)0x00000300)        /*!< Remap SPI1 Tx on DMA1 channel 3 */
+#define DMA_RMPCR1_CH3_TIM1_CH2             ((uint32_t)0x00000400)        /*!< Remap TIM1 channel 2 on DMA1 channel 3 */
+#define DMA_RMPCR1_CH3_TIM2_CH2             ((uint32_t)0x00000500)        /*!< Remap TIM2 channel 2 on DMA1 channel 3 */
+#define DMA_RMPCR1_CH3_TIM16_CH1            ((uint32_t)0x00000700)        /*!< Remap TIM16 channel 1 on DMA1 channel 3 */
+#define DMA_RMPCR1_CH3_TIM16_UP             ((uint32_t)0x00000700)        /*!< Remap TIM16 up on DMA1 channel 3 */
+#define DMA_RMPCR1_CH3_USART1_RX            ((uint32_t)0x00000800)        /*!< Remap USART1 Rx on DMA1 channel 3 */
+#define DMA_RMPCR1_CH3_USART2_RX            ((uint32_t)0x00000900)        /*!< Remap USART2 Rx on DMA1 channel 3 */
+#define DMA_RMPCR1_CH3_USART3_RX            ((uint32_t)0x00000A00)        /*!< Remap USART3 Rx on DMA1 channel 3 */
+#define DMA_RMPCR1_CH3_USART4_RX            ((uint32_t)0x00000B00)        /*!< Remap USART4 Rx on DMA1 channel 3 */
+#define DMA_RMPCR1_CH3_USART5_RX            ((uint32_t)0x00000C00)        /*!< Remap USART5 Rx on DMA1 channel 3 */
+#define DMA_RMPCR1_CH3_USART6_RX            ((uint32_t)0x00000D00)        /*!< Remap USART6 Rx on DMA1 channel 3 */
+#define DMA_RMPCR1_CH3_USART7_RX            ((uint32_t)0x00000E00)        /*!< Remap USART7 Rx on DMA1 channel 3 */
+#define DMA_RMPCR1_CH3_USART8_RX            ((uint32_t)0x00000F00)        /*!< Remap USART8 Rx on DMA1 channel 3 */
+#define DMA_RMPCR1_CH4_TIM7_UP              ((uint32_t)0x00001000)        /*!< Remap TIM7 up on DMA1 channel 4 */
+#define DMA_RMPCR1_CH4_DAC_CH2              ((uint32_t)0x00001000)        /*!< Remap DAC Channel 2 on DMA1 channel 4 */
+#define DMA_RMPCR1_CH4_I2C2_TX              ((uint32_t)0x00002000)        /*!< Remap I2C2 Tx on DMA1 channel 4 */
+#define DMA_RMPCR1_CH4_SPI2_RX              ((uint32_t)0x00003000)        /*!< Remap SPI2 Rx on DMA1 channel 4 */
+#define DMA_RMPCR1_CH4_TIM2_CH4             ((uint32_t)0x00005000)        /*!< Remap TIM2 channel 4 on DMA1 channel 4 */
+#define DMA_RMPCR1_CH4_TIM3_CH1             ((uint32_t)0x00006000)        /*!< Remap TIM3 channel 1 on DMA1 channel 4 */
+#define DMA_RMPCR1_CH4_TIM3_TRIG            ((uint32_t)0x00006000)        /*!< Remap TIM3 Trig on DMA1 channel 4 */
+#define DMA_RMPCR1_CH4_TIM16_CH1            ((uint32_t)0x00007000)        /*!< Remap TIM16 channel 1 on DMA1 channel 4 */
+#define DMA_RMPCR1_CH4_TIM16_UP             ((uint32_t)0x00007000)        /*!< Remap TIM16 up on DMA1 channel 4 */
+#define DMA_RMPCR1_CH4_USART1_TX            ((uint32_t)0x00008000)        /*!< Remap USART1 Tx on DMA1 channel 4 */
+#define DMA_RMPCR1_CH4_USART2_TX            ((uint32_t)0x00009000)        /*!< Remap USART2 Tx on DMA1 channel 4 */
+#define DMA_RMPCR1_CH4_USART3_TX            ((uint32_t)0x0000A000)        /*!< Remap USART3 Tx on DMA1 channel 4 */
+#define DMA_RMPCR1_CH4_USART4_TX            ((uint32_t)0x0000B000)        /*!< Remap USART4 Tx on DMA1 channel 4 */
+#define DMA_RMPCR1_CH4_USART5_TX            ((uint32_t)0x0000C000)        /*!< Remap USART5 Tx on DMA1 channel 4 */
+#define DMA_RMPCR1_CH4_USART6_TX            ((uint32_t)0x0000D000)        /*!< Remap USART6 Tx on DMA1 channel 4 */
+#define DMA_RMPCR1_CH4_USART7_TX            ((uint32_t)0x0000E000)        /*!< Remap USART7 Tx on DMA1 channel 4 */
+#define DMA_RMPCR1_CH4_USART8_TX            ((uint32_t)0x0000F000)        /*!< Remap USART8 Tx on DMA1 channel 4 */
+#define DMA_RMPCR1_CH5_I2C2_RX              ((uint32_t)0x00020000)        /*!< Remap I2C2 Rx on DMA1 channel 5 */
+#define DMA_RMPCR1_CH5_SPI2_TX              ((uint32_t)0x00030000)        /*!< Remap SPI1 Tx on DMA1 channel 5 */
+#define DMA_RMPCR1_CH5_TIM1_CH3             ((uint32_t)0x00040000)        /*!< Remap TIM1 channel 3 on DMA1 channel 5 */
+#define DMA_RMPCR1_CH5_USART1_RX            ((uint32_t)0x00080000)        /*!< Remap USART1 Rx on DMA1 channel 5 */
+#define DMA_RMPCR1_CH5_USART2_RX            ((uint32_t)0x00090000)        /*!< Remap USART2 Rx on DMA1 channel 5 */
+#define DMA_RMPCR1_CH5_USART3_RX            ((uint32_t)0x000A0000)        /*!< Remap USART3 Rx on DMA1 channel 5 */
+#define DMA_RMPCR1_CH5_USART4_RX            ((uint32_t)0x000B0000)        /*!< Remap USART4 Rx on DMA1 channel 5 */
+#define DMA_RMPCR1_CH5_USART5_RX            ((uint32_t)0x000C0000)        /*!< Remap USART5 Rx on DMA1 channel 5 */
+#define DMA_RMPCR1_CH5_USART6_RX            ((uint32_t)0x000D0000)        /*!< Remap USART6 Rx on DMA1 channel 5 */
+#define DMA_RMPCR1_CH5_USART7_RX            ((uint32_t)0x000E0000)        /*!< Remap USART7 Rx on DMA1 channel 5 */
+#define DMA_RMPCR1_CH5_USART8_RX            ((uint32_t)0x000F0000)        /*!< Remap USART8 Rx on DMA1 channel 5 */
+#define DMA_RMPCR1_CH6_I2C1_TX              ((uint32_t)0x00200000)        /*!< Remap I2C1 Tx on DMA1 channel 6 */
+#define DMA_RMPCR1_CH6_SPI2_RX              ((uint32_t)0x00300000)        /*!< Remap SPI2 Rx on DMA1 channel 6 */
+#define DMA_RMPCR1_CH6_TIM1_CH1             ((uint32_t)0x00400000)        /*!< Remap TIM1 channel 1 on DMA1 channel 6 */
+#define DMA_RMPCR1_CH6_TIM1_CH2             ((uint32_t)0x00400000)        /*!< Remap TIM1 channel 2 on DMA1 channel 6 */
+#define DMA_RMPCR1_CH6_TIM1_CH3             ((uint32_t)0x00400000)        /*!< Remap TIM1 channel 3 on DMA1 channel 6 */
+#define DMA_RMPCR1_CH6_TIM3_CH1             ((uint32_t)0x00600000)        /*!< Remap TIM3 channel 1 on DMA1 channel 6 */
+#define DMA_RMPCR1_CH6_TIM3_TRIG            ((uint32_t)0x00600000)        /*!< Remap TIM3 Trig on DMA1 channel 6 */
+#define DMA_RMPCR1_CH6_TIM16_CH1            ((uint32_t)0x00700000)        /*!< Remap TIM16 channel 1 on DMA1 channel 6 */
+#define DMA_RMPCR1_CH6_TIM16_UP             ((uint32_t)0x00700000)        /*!< Remap TIM16 up on DMA1 channel 6 */
+#define DMA_RMPCR1_CH6_USART1_RX            ((uint32_t)0x00800000)        /*!< Remap USART1 Rx on DMA1 channel 6 */
+#define DMA_RMPCR1_CH6_USART2_RX            ((uint32_t)0x00900000)        /*!< Remap USART2 Rx on DMA1 channel 6 */
+#define DMA_RMPCR1_CH6_USART3_RX            ((uint32_t)0x00A00000)        /*!< Remap USART3 Rx on DMA1 channel 6 */
+#define DMA_RMPCR1_CH6_USART4_RX            ((uint32_t)0x00B00000)        /*!< Remap USART4 Rx on DMA1 channel 6 */
+#define DMA_RMPCR1_CH6_USART5_RX            ((uint32_t)0x00C00000)        /*!< Remap USART5 Rx on DMA1 channel 6 */
+#define DMA_RMPCR1_CH6_USART6_RX            ((uint32_t)0x00D00000)        /*!< Remap USART6 Rx on DMA1 channel 6 */
+#define DMA_RMPCR1_CH6_USART7_RX            ((uint32_t)0x00E00000)        /*!< Remap USART7 Rx on DMA1 channel 6 */
+#define DMA_RMPCR1_CH6_USART8_RX            ((uint32_t)0x00F00000)        /*!< Remap USART8 Rx on DMA1 channel 6 */
+#define DMA_RMPCR1_CH7_I2C1_RX              ((uint32_t)0x02000000)        /*!< Remap I2C1 Rx on DMA1 channel 7 */
+#define DMA_RMPCR1_CH7_SPI2_TX              ((uint32_t)0x03000000)        /*!< Remap SPI2 Tx on DMA1 channel 7 */
+#define DMA_RMPCR1_CH7_TIM2_CH2             ((uint32_t)0x05000000)        /*!< Remap TIM2 channel 2 on DMA1 channel 7 */
+#define DMA_RMPCR1_CH7_TIM2_CH4             ((uint32_t)0x05000000)        /*!< Remap TIM2 channel 4 on DMA1 channel 7 */
+#define DMA_RMPCR1_CH7_TIM17_CH1            ((uint32_t)0x07000000)        /*!< Remap TIM17 channel 1 on DMA1 channel 7 */
+#define DMA_RMPCR1_CH7_TIM17_UP             ((uint32_t)0x07000000)        /*!< Remap TIM17 up on DMA1 channel 7 */
+#define DMA_RMPCR1_CH7_USART1_TX            ((uint32_t)0x08000000)        /*!< Remap USART1 Tx on DMA1 channel 7 */
+#define DMA_RMPCR1_CH7_USART2_TX            ((uint32_t)0x09000000)        /*!< Remap USART2 Tx on DMA1 channel 7 */
+#define DMA_RMPCR1_CH7_USART3_TX            ((uint32_t)0x0A000000)        /*!< Remap USART3 Tx on DMA1 channel 7 */
+#define DMA_RMPCR1_CH7_USART4_TX            ((uint32_t)0x0B000000)        /*!< Remap USART4 Tx on DMA1 channel 7 */
+#define DMA_RMPCR1_CH7_USART5_TX            ((uint32_t)0x0C000000)        /*!< Remap USART5 Tx on DMA1 channel 7 */
+#define DMA_RMPCR1_CH7_USART6_TX            ((uint32_t)0x0D000000)        /*!< Remap USART6 Tx on DMA1 channel 7 */
+#define DMA_RMPCR1_CH7_USART7_TX            ((uint32_t)0x0E000000)        /*!< Remap USART7 Tx on DMA1 channel 7 */
+#define DMA_RMPCR1_CH7_USART8_TX            ((uint32_t)0x0F000000)        /*!< Remap USART8 Tx on DMA1 channel 7 */
+
+/******************  Bit definition for DMA_RMPCR2 register  ********************/
+#define DMA_RMPCR2_DEFAULT                  ((uint32_t)0x00000000)        /*!< Default remap position for DMA2 */
+#define DMA_RMPCR2_CH1_I2C2_TX              ((uint32_t)0x00000002)        /*!< Remap I2C2 TX on DMA2 channel 1 */
+#define DMA_RMPCR2_CH1_USART1_TX            ((uint32_t)0x00000008)        /*!< Remap USART1 Tx on DMA2 channel 1 */
+#define DMA_RMPCR2_CH1_USART2_TX            ((uint32_t)0x00000009)        /*!< Remap USART2 Tx on DMA2 channel 1 */
+#define DMA_RMPCR2_CH1_USART3_TX            ((uint32_t)0x0000000A)        /*!< Remap USART3 Tx on DMA2 channel 1 */
+#define DMA_RMPCR2_CH1_USART4_TX            ((uint32_t)0x0000000B)        /*!< Remap USART4 Tx on DMA2 channel 1 */
+#define DMA_RMPCR2_CH1_USART5_TX            ((uint32_t)0x0000000C)        /*!< Remap USART5 Tx on DMA2 channel 1 */
+#define DMA_RMPCR2_CH1_USART6_TX            ((uint32_t)0x0000000D)        /*!< Remap USART6 Tx on DMA2 channel 1 */
+#define DMA_RMPCR2_CH1_USART7_TX            ((uint32_t)0x0000000E)        /*!< Remap USART7 Tx on DMA2 channel 1 */
+#define DMA_RMPCR2_CH1_USART8_TX            ((uint32_t)0x0000000F)        /*!< Remap USART8 Tx on DMA2 channel 1 */
+#define DMA_RMPCR2_CH2_I2C2_RX              ((uint32_t)0x00000020)        /*!< Remap I2C2 Rx on DMA2 channel 2 */
+#define DMA_RMPCR2_CH2_USART1_RX            ((uint32_t)0x00000080)        /*!< Remap USART1 Rx on DMA2 channel 2 */
+#define DMA_RMPCR2_CH2_USART2_RX            ((uint32_t)0x00000090)        /*!< Remap USART2 Rx on DMA2 channel 2 */
+#define DMA_RMPCR2_CH2_USART3_RX            ((uint32_t)0x000000A0)        /*!< Remap USART3 Rx on DMA2 channel 2 */
+#define DMA_RMPCR2_CH2_USART4_RX            ((uint32_t)0x000000B0)        /*!< Remap USART4 Rx on DMA2 channel 2 */
+#define DMA_RMPCR2_CH2_USART5_RX            ((uint32_t)0x000000C0)        /*!< Remap USART5 Rx on DMA2 channel 2 */
+#define DMA_RMPCR2_CH2_USART6_RX            ((uint32_t)0x000000D0)        /*!< Remap USART6 Rx on DMA2 channel 2 */
+#define DMA_RMPCR2_CH2_USART7_RX            ((uint32_t)0x000000E0)        /*!< Remap USART7 Rx on DMA2 channel 2 */
+#define DMA_RMPCR2_CH2_USART8_RX            ((uint32_t)0x000000F0)        /*!< Remap USART8 Rx on DMA2 channel 2 */
+#define DMA_RMPCR2_CH3_TIM6_UP              ((uint32_t)0x00000100)        /*!< Remap TIM6 up on DMA2 channel 3 */
+#define DMA_RMPCR2_CH3_DAC_CH1              ((uint32_t)0x00000100)        /*!< Remap DAC channel 1 on DMA2 channel 3 */
+#define DMA_RMPCR2_CH3_SPI1_RX              ((uint32_t)0x00000300)        /*!< Remap SPI1 Rx on DMA2 channel 3 */
+#define DMA_RMPCR2_CH3_USART1_RX            ((uint32_t)0x00000800)        /*!< Remap USART1 Rx on DMA2 channel 3 */
+#define DMA_RMPCR2_CH3_USART2_RX            ((uint32_t)0x00000900)        /*!< Remap USART2 Rx on DMA2 channel 3 */
+#define DMA_RMPCR2_CH3_USART3_RX            ((uint32_t)0x00000A00)        /*!< Remap USART3 Rx on DMA2 channel 3 */
+#define DMA_RMPCR2_CH3_USART4_RX            ((uint32_t)0x00000B00)        /*!< Remap USART4 Rx on DMA2 channel 3 */
+#define DMA_RMPCR2_CH3_USART5_RX            ((uint32_t)0x00000C00)        /*!< Remap USART5 Rx on DMA2 channel 3 */
+#define DMA_RMPCR2_CH3_USART6_RX            ((uint32_t)0x00000D00)        /*!< Remap USART6 Rx on DMA2 channel 3 */
+#define DMA_RMPCR2_CH3_USART7_RX            ((uint32_t)0x00000E00)        /*!< Remap USART7 Rx on DMA2 channel 3 */
+#define DMA_RMPCR2_CH3_USART8_RX            ((uint32_t)0x00000F00)        /*!< Remap USART8 Rx on DMA2 channel 3 */
+#define DMA_RMPCR2_CH4_TIM7_UP              ((uint32_t)0x00001000)        /*!< Remap TIM7 up on DMA2 channel 4 */
+#define DMA_RMPCR2_CH4_DAC_CH2              ((uint32_t)0x00001000)        /*!< Remap DAC channel 2 on DMA2 channel 4 */
+#define DMA_RMPCR2_CH4_SPI1_TX              ((uint32_t)0x00003000)        /*!< Remap SPI1 Tx on DMA2 channel 4 */
+#define DMA_RMPCR2_CH4_USART1_TX            ((uint32_t)0x00008000)        /*!< Remap USART1 Tx on DMA2 channel 4 */
+#define DMA_RMPCR2_CH4_USART2_TX            ((uint32_t)0x00009000)        /*!< Remap USART2 Tx on DMA2 channel 4 */
+#define DMA_RMPCR2_CH4_USART3_TX            ((uint32_t)0x0000A000)        /*!< Remap USART3 Tx on DMA2 channel 4 */
+#define DMA_RMPCR2_CH4_USART4_TX            ((uint32_t)0x0000B000)        /*!< Remap USART4 Tx on DMA2 channel 4 */
+#define DMA_RMPCR2_CH4_USART5_TX            ((uint32_t)0x0000C000)        /*!< Remap USART5 Tx on DMA2 channel 4 */
+#define DMA_RMPCR2_CH4_USART6_TX            ((uint32_t)0x0000D000)        /*!< Remap USART6 Tx on DMA2 channel 4 */
+#define DMA_RMPCR2_CH4_USART7_TX            ((uint32_t)0x0000E000)        /*!< Remap USART7 Tx on DMA2 channel 4 */
+#define DMA_RMPCR2_CH4_USART8_TX            ((uint32_t)0x0000F000)        /*!< Remap USART8 Tx on DMA2 channel 4 */
+#define DMA_RMPCR2_CH5_ADC                  ((uint32_t)0x00010000)        /*!< Remap ADC on DMA2 channel 5 */
+#define DMA_RMPCR2_CH5_USART1_TX            ((uint32_t)0x00080000)        /*!< Remap USART1 Tx on DMA2 channel 5 */
+#define DMA_RMPCR2_CH5_USART2_TX            ((uint32_t)0x00090000)        /*!< Remap USART2 Tx on DMA2 channel 5 */
+#define DMA_RMPCR2_CH5_USART3_TX            ((uint32_t)0x000A0000)        /*!< Remap USART3 Tx on DMA2 channel 5 */
+#define DMA_RMPCR2_CH5_USART4_TX            ((uint32_t)0x000B0000)        /*!< Remap USART4 Tx on DMA2 channel 5 */
+#define DMA_RMPCR2_CH5_USART5_TX            ((uint32_t)0x000C0000)        /*!< Remap USART5 Tx on DMA2 channel 5 */
+#define DMA_RMPCR2_CH5_USART6_TX            ((uint32_t)0x000D0000)        /*!< Remap USART6 Tx on DMA2 channel 5 */
+#define DMA_RMPCR2_CH5_USART7_TX            ((uint32_t)0x000E0000)        /*!< Remap USART7 Tx on DMA2 channel 5 */
+#define DMA_RMPCR2_CH5_USART8_TX            ((uint32_t)0x000F0000)        /*!< Remap USART8 Tx on DMA2 channel 5 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 External Interrupt/Event Controller (EXTI)                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0  */
+#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1  */
+#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2  */
+#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3  */
+#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4  */
+#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5  */
+#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6  */
+#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7  */
+#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8  */
+#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9  */
+#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000)        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR23                       ((uint32_t)0x00800000)        /*!< Interrupt Mask on line 23 */
+#define  EXTI_IMR_MR24                       ((uint32_t)0x01000000)        /*!< Interrupt Mask on line 24 */
+#define  EXTI_IMR_MR25                       ((uint32_t)0x02000000)        /*!< Interrupt Mask on line 25 */
+#define  EXTI_IMR_MR26                       ((uint32_t)0x04000000)        /*!< Interrupt Mask on line 26 */
+#define  EXTI_IMR_MR27                       ((uint32_t)0x08000000)        /*!< Interrupt Mask on line 27 */
+#define  EXTI_IMR_MR28                       ((uint32_t)0x10000000)        /*!< Interrupt Mask on line 28 */
+#define  EXTI_IMR_MR29                       ((uint32_t)0x20000000)        /*!< Interrupt Mask on line 29 */
+#define  EXTI_IMR_MR30                       ((uint32_t)0x40000000)        /*!< Interrupt Mask on line 30 */
+#define  EXTI_IMR_MR31                       ((uint32_t)0x80000000)        /*!< Interrupt Mask on line 31 */
+
+/******************  Bit definition for EXTI_EMR register  ********************/
+#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0  */
+#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1  */
+#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2  */
+#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3  */
+#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4  */
+#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5  */
+#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6  */
+#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7  */
+#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8  */
+#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9  */
+#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000)        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR23                       ((uint32_t)0x00800000)        /*!< Event Mask on line 23 */
+#define  EXTI_EMR_MR24                       ((uint32_t)0x01000000)        /*!< Event Mask on line 24 */
+#define  EXTI_EMR_MR25                       ((uint32_t)0x02000000)        /*!< Event Mask on line 25 */
+#define  EXTI_EMR_MR26                       ((uint32_t)0x04000000)        /*!< Event Mask on line 26 */
+#define  EXTI_EMR_MR27                       ((uint32_t)0x08000000)        /*!< Event Mask on line 27 */
+#define  EXTI_EMR_MR28                       ((uint32_t)0x10000000)        /*!< Event Mask on line 28 */
+#define  EXTI_EMR_MR29                       ((uint32_t)0x20000000)        /*!< Event Mask on line 29 */
+#define  EXTI_EMR_MR30                       ((uint32_t)0x40000000)        /*!< Event Mask on line 30 */
+#define  EXTI_EMR_MR31                       ((uint32_t)0x80000000)        /*!< Event Mask on line 31 */
+
+/*******************  Bit definition for EXTI_RTSR register  ******************/
+#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
+#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000)        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000)        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000)        /*!< Rising trigger event configuration bit of line 22 */
+
+/*******************  Bit definition for EXTI_FTSR register *******************/
+#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
+#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000)        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000)        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000)        /*!< Falling trigger event configuration bit of line 22 */
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0  */
+#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1  */
+#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2  */
+#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3  */
+#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4  */
+#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5  */
+#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6  */
+#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7  */
+#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8  */
+#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9  */
+#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
+#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000)        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000)        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000)        /*!< Software Interrupt on line 22 */
+
+/******************  Bit definition for EXTI_PR register  *********************/
+#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit 0  */
+#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit 1  */
+#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit 2  */
+#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit 3  */
+#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit 4  */
+#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit 5  */
+#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit 6  */
+#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit 7  */
+#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit 8  */
+#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit 9  */
+#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit 10 */
+#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit 11 */
+#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit 12 */
+#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit 13 */
+#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit 14 */
+#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit 15 */
+#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit 16 */
+#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit 17 */
+#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit 19 */
+#define  EXTI_PR_PR20                        ((uint32_t)0x00100000)        /*!< Pending bit 20 */
+#define  EXTI_PR_PR21                        ((uint32_t)0x00200000)        /*!< Pending bit 21 */
+#define  EXTI_PR_PR22                        ((uint32_t)0x00400000)        /*!< Pending bit 22 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      FLASH and Option Bytes Registers                      */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for FLASH_ACR register  ******************/
+#define  FLASH_ACR_LATENCY                   ((uint32_t)0x00000001)        /*!< LATENCY bit (Latency) */
+
+#define  FLASH_ACR_PRFTBE                    ((uint32_t)0x00000010)        /*!< Prefetch Buffer Enable */
+#define  FLASH_ACR_PRFTBS                    ((uint32_t)0x00000020)        /*!< Prefetch Buffer Status */
+
+/******************  Bit definition for FLASH_KEYR register  ******************/
+#define  FLASH_KEYR_FKEYR                    ((uint32_t)0xFFFFFFFF)        /*!< FPEC Key */
+
+/*****************  Bit definition for FLASH_OPTKEYR register  ****************/
+#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option Byte Key */
+
+/******************  FLASH Keys  **********************************************/
+#define FLASH_FKEY1                          ((uint32_t)0x45670123)        /*!< Flash program erase key1 */
+#define FLASH_FKEY2                          ((uint32_t)0xCDEF89AB)        /*!< Flash program erase key2: used with FLASH_PEKEY1
+                                                                                to unlock the write access to the FPEC. */
+                                                               
+#define FLASH_OPTKEY1                        ((uint32_t)0x45670123)        /*!< Flash option key1 */
+#define FLASH_OPTKEY2                        ((uint32_t)0xCDEF89AB)        /*!< Flash option key2: used with FLASH_OPTKEY1 to
+                                                                                unlock the write access to the option byte block */
+
+/******************  Bit definition for FLASH_SR register  *******************/
+#define  FLASH_SR_BSY                        ((uint32_t)0x00000001)        /*!< Busy */
+#define  FLASH_SR_PGERR                      ((uint32_t)0x00000004)        /*!< Programming Error */
+#define  FLASH_SR_WRPRTERR                   ((uint32_t)0x00000010)        /*!< Write Protection Error */
+#define  FLASH_SR_EOP                        ((uint32_t)0x00000020)        /*!< End of operation */
+#define  FLASH_SR_WRPERR                     FLASH_SR_WRPRTERR             /*!< Legacy of Write Protection Error */
+
+/*******************  Bit definition for FLASH_CR register  *******************/
+#define  FLASH_CR_PG                         ((uint32_t)0x00000001)        /*!< Programming */
+#define  FLASH_CR_PER                        ((uint32_t)0x00000002)        /*!< Page Erase */
+#define  FLASH_CR_MER                        ((uint32_t)0x00000004)        /*!< Mass Erase */
+#define  FLASH_CR_OPTPG                      ((uint32_t)0x00000010)        /*!< Option Byte Programming */
+#define  FLASH_CR_OPTER                      ((uint32_t)0x00000020)        /*!< Option Byte Erase */
+#define  FLASH_CR_STRT                       ((uint32_t)0x00000040)        /*!< Start */
+#define  FLASH_CR_LOCK                       ((uint32_t)0x00000080)        /*!< Lock */
+#define  FLASH_CR_OPTWRE                     ((uint32_t)0x00000200)        /*!< Option Bytes Write Enable */
+#define  FLASH_CR_ERRIE                      ((uint32_t)0x00000400)        /*!< Error Interrupt Enable */
+#define  FLASH_CR_EOPIE                      ((uint32_t)0x00001000)        /*!< End of operation interrupt enable */
+#define  FLASH_CR_OBL_LAUNCH                 ((uint32_t)0x00002000)        /*!< Option Bytes Loader Launch */
+
+/*******************  Bit definition for FLASH_AR register  *******************/
+#define  FLASH_AR_FAR                        ((uint32_t)0xFFFFFFFF)        /*!< Flash Address */
+
+/******************  Bit definition for FLASH_OBR register  *******************/
+#define  FLASH_OBR_OPTERR                    ((uint32_t)0x00000001)        /*!< Option Byte Error */
+#define  FLASH_OBR_RDPRT1                    ((uint32_t)0x00000002)        /*!< Read protection Level bit 1 */
+#define  FLASH_OBR_RDPRT2                    ((uint32_t)0x00000004)        /*!< Read protection Level bit 2 */
+
+#define  FLASH_OBR_USER                      ((uint32_t)0x00003700)        /*!< User Option Bytes */
+#define  FLASH_OBR_IWDG_SW                   ((uint32_t)0x00000100)        /*!< IWDG SW */
+#define  FLASH_OBR_nRST_STOP                 ((uint32_t)0x00000200)        /*!< nRST_STOP */
+#define  FLASH_OBR_nRST_STDBY                ((uint32_t)0x00000400)        /*!< nRST_STDBY */
+#define  FLASH_OBR_nBOOT0                    ((uint32_t)0x00000800)        /*!< nBOOT0 */
+#define  FLASH_OBR_nBOOT1                    ((uint32_t)0x00001000)        /*!< nBOOT1 */
+#define  FLASH_OBR_VDDA_MONITOR              ((uint32_t)0x00002000)        /*!< VDDA power supply supervisor */
+#define  FLASH_OBR_RAM_PARITY_CHECK          ((uint32_t)0x00004000)        /*!< RAM Parity Check */
+#define  FLASH_OBR_nBOOT0_SW                 ((uint32_t)0x00008000)        /*!< nBOOT0 SW  (available only in the STM32F042 devices)*/
+#define  FLASH_OBR_DATA0                     ((uint32_t)0x00FF0000)        /*!< DATA0 */
+#define  FLASH_OBR_DATA1                     ((uint32_t)0xFF000000)        /*!< DATA0 */
+
+/* Old BOOT1 bit definition, maintained for legacy purpose */
+#define FLASH_OBR_BOOT1                      FLASH_OBR_nBOOT1
+
+/* Old OBR_VDDA bit definition, maintained for legacy purpose */
+#define FLASH_OBR_VDDA_ANALOG                FLASH_OBR_VDDA_MONITOR
+
+/******************  Bit definition for FLASH_WRPR register  ******************/
+#define  FLASH_WRPR_WRP                      ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/******************  Bit definition for OB_RDP register  **********************/
+#define  OB_RDP_RDP                          ((uint32_t)0x000000FF)        /*!< Read protection option byte */
+#define  OB_RDP_nRDP                         ((uint32_t)0x0000FF00)        /*!< Read protection complemented option byte */
+
+/******************  Bit definition for OB_USER register  *********************/
+#define  OB_USER_USER                        ((uint32_t)0x00FF0000)        /*!< User option byte */
+#define  OB_USER_nUSER                       ((uint32_t)0xFF000000)        /*!< User complemented option byte */
+
+/******************  Bit definition for OB_WRP0 register  *********************/
+#define  OB_WRP0_WRP0                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
+#define  OB_WRP0_nWRP0                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for OB_WRP1 register  *********************/
+#define  OB_WRP1_WRP1                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
+#define  OB_WRP1_nWRP1                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for OB_WRP2 register  *********************/
+#define  OB_WRP2_WRP2                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes (only for STM32F072 devices) */
+#define  OB_WRP2_nWRP2                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes (only for STM32F072 devices) */
+
+/******************  Bit definition for OB_WRP3 register  *********************/
+#define  OB_WRP3_WRP3                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes (only for STM32F072 devices) */
+#define  OB_WRP3_nWRP3                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes (only for STM32F072 devices) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       General Purpose IOs (GPIO)                           */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODER0          ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0        ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1        ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1          ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0        ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1        ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2          ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0        ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1        ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3          ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0        ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1        ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4          ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0        ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1        ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5          ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0        ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1        ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6          ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0        ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1        ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7          ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0        ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1        ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8          ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0        ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1        ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9          ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0        ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1        ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10         ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0       ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1       ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11         ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0       ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1       ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12         ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0       ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1       ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13         ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0       ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1       ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14         ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0       ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1       ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15         ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0       ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1       ((uint32_t)0x80000000)
+
+/******************  Bit definition for GPIO_OTYPER register  *****************/
+#define GPIO_OTYPER_OT_0           ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1           ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2           ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3           ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4           ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5           ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6           ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7           ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8           ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9           ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10          ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11          ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12          ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13          ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14          ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15          ((uint32_t)0x00008000)
+
+/****************  Bit definition for GPIO_OSPEEDR register  ******************/
+#define GPIO_OSPEEDR_OSPEEDR0     ((uint32_t)0x00000003)
+#define GPIO_OSPEEDR_OSPEEDR0_0   ((uint32_t)0x00000001)
+#define GPIO_OSPEEDR_OSPEEDR0_1   ((uint32_t)0x00000002)
+#define GPIO_OSPEEDR_OSPEEDR1     ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDR_OSPEEDR1_0   ((uint32_t)0x00000004)
+#define GPIO_OSPEEDR_OSPEEDR1_1   ((uint32_t)0x00000008)
+#define GPIO_OSPEEDR_OSPEEDR2     ((uint32_t)0x00000030)
+#define GPIO_OSPEEDR_OSPEEDR2_0   ((uint32_t)0x00000010)
+#define GPIO_OSPEEDR_OSPEEDR2_1   ((uint32_t)0x00000020)
+#define GPIO_OSPEEDR_OSPEEDR3     ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDR_OSPEEDR3_0   ((uint32_t)0x00000040)
+#define GPIO_OSPEEDR_OSPEEDR3_1   ((uint32_t)0x00000080)
+#define GPIO_OSPEEDR_OSPEEDR4     ((uint32_t)0x00000300)
+#define GPIO_OSPEEDR_OSPEEDR4_0   ((uint32_t)0x00000100)
+#define GPIO_OSPEEDR_OSPEEDR4_1   ((uint32_t)0x00000200)
+#define GPIO_OSPEEDR_OSPEEDR5     ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDR_OSPEEDR5_0   ((uint32_t)0x00000400)
+#define GPIO_OSPEEDR_OSPEEDR5_1   ((uint32_t)0x00000800)
+#define GPIO_OSPEEDR_OSPEEDR6     ((uint32_t)0x00003000)
+#define GPIO_OSPEEDR_OSPEEDR6_0   ((uint32_t)0x00001000)
+#define GPIO_OSPEEDR_OSPEEDR6_1   ((uint32_t)0x00002000)
+#define GPIO_OSPEEDR_OSPEEDR7     ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDR_OSPEEDR7_0   ((uint32_t)0x00004000)
+#define GPIO_OSPEEDR_OSPEEDR7_1   ((uint32_t)0x00008000)
+#define GPIO_OSPEEDR_OSPEEDR8     ((uint32_t)0x00030000)
+#define GPIO_OSPEEDR_OSPEEDR8_0   ((uint32_t)0x00010000)
+#define GPIO_OSPEEDR_OSPEEDR8_1   ((uint32_t)0x00020000)
+#define GPIO_OSPEEDR_OSPEEDR9     ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDR_OSPEEDR9_0   ((uint32_t)0x00040000)
+#define GPIO_OSPEEDR_OSPEEDR9_1   ((uint32_t)0x00080000)
+#define GPIO_OSPEEDR_OSPEEDR10    ((uint32_t)0x00300000)
+#define GPIO_OSPEEDR_OSPEEDR10_0  ((uint32_t)0x00100000)
+#define GPIO_OSPEEDR_OSPEEDR10_1  ((uint32_t)0x00200000)
+#define GPIO_OSPEEDR_OSPEEDR11    ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDR_OSPEEDR11_0  ((uint32_t)0x00400000)
+#define GPIO_OSPEEDR_OSPEEDR11_1  ((uint32_t)0x00800000)
+#define GPIO_OSPEEDR_OSPEEDR12    ((uint32_t)0x03000000)
+#define GPIO_OSPEEDR_OSPEEDR12_0  ((uint32_t)0x01000000)
+#define GPIO_OSPEEDR_OSPEEDR12_1  ((uint32_t)0x02000000)
+#define GPIO_OSPEEDR_OSPEEDR13    ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDR_OSPEEDR13_0  ((uint32_t)0x04000000)
+#define GPIO_OSPEEDR_OSPEEDR13_1  ((uint32_t)0x08000000)
+#define GPIO_OSPEEDR_OSPEEDR14    ((uint32_t)0x30000000)
+#define GPIO_OSPEEDR_OSPEEDR14_0  ((uint32_t)0x10000000)
+#define GPIO_OSPEEDR_OSPEEDR14_1  ((uint32_t)0x20000000)
+#define GPIO_OSPEEDR_OSPEEDR15    ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDR_OSPEEDR15_0  ((uint32_t)0x40000000)
+#define GPIO_OSPEEDR_OSPEEDR15_1  ((uint32_t)0x80000000)
+
+/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
+#define GPIO_OSPEEDER_OSPEEDR0     GPIO_OSPEEDR_OSPEEDR0
+#define GPIO_OSPEEDER_OSPEEDR0_0   GPIO_OSPEEDR_OSPEEDR0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1   GPIO_OSPEEDR_OSPEEDR0_1
+#define GPIO_OSPEEDER_OSPEEDR1     GPIO_OSPEEDR_OSPEEDR1
+#define GPIO_OSPEEDER_OSPEEDR1_0   GPIO_OSPEEDR_OSPEEDR1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1   GPIO_OSPEEDR_OSPEEDR1_1
+#define GPIO_OSPEEDER_OSPEEDR2     GPIO_OSPEEDR_OSPEEDR2
+#define GPIO_OSPEEDER_OSPEEDR2_0   GPIO_OSPEEDR_OSPEEDR2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1   GPIO_OSPEEDR_OSPEEDR2_1
+#define GPIO_OSPEEDER_OSPEEDR3     GPIO_OSPEEDR_OSPEEDR3
+#define GPIO_OSPEEDER_OSPEEDR3_0   GPIO_OSPEEDR_OSPEEDR3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1   GPIO_OSPEEDR_OSPEEDR3_1
+#define GPIO_OSPEEDER_OSPEEDR4     GPIO_OSPEEDR_OSPEEDR4
+#define GPIO_OSPEEDER_OSPEEDR4_0   GPIO_OSPEEDR_OSPEEDR4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1   GPIO_OSPEEDR_OSPEEDR4_1
+#define GPIO_OSPEEDER_OSPEEDR5     GPIO_OSPEEDR_OSPEEDR5
+#define GPIO_OSPEEDER_OSPEEDR5_0   GPIO_OSPEEDR_OSPEEDR5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1   GPIO_OSPEEDR_OSPEEDR5_1
+#define GPIO_OSPEEDER_OSPEEDR6     GPIO_OSPEEDR_OSPEEDR6
+#define GPIO_OSPEEDER_OSPEEDR6_0   GPIO_OSPEEDR_OSPEEDR6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1   GPIO_OSPEEDR_OSPEEDR6_1
+#define GPIO_OSPEEDER_OSPEEDR7     GPIO_OSPEEDR_OSPEEDR7
+#define GPIO_OSPEEDER_OSPEEDR7_0   GPIO_OSPEEDR_OSPEEDR7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1   GPIO_OSPEEDR_OSPEEDR7_1
+#define GPIO_OSPEEDER_OSPEEDR8     GPIO_OSPEEDR_OSPEEDR8
+#define GPIO_OSPEEDER_OSPEEDR8_0   GPIO_OSPEEDR_OSPEEDR8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1   GPIO_OSPEEDR_OSPEEDR8_1
+#define GPIO_OSPEEDER_OSPEEDR9     GPIO_OSPEEDR_OSPEEDR9
+#define GPIO_OSPEEDER_OSPEEDR9_0   GPIO_OSPEEDR_OSPEEDR9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1   GPIO_OSPEEDR_OSPEEDR9_1
+#define GPIO_OSPEEDER_OSPEEDR10    GPIO_OSPEEDR_OSPEEDR10
+#define GPIO_OSPEEDER_OSPEEDR10_0  GPIO_OSPEEDR_OSPEEDR10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1  GPIO_OSPEEDR_OSPEEDR10_1
+#define GPIO_OSPEEDER_OSPEEDR11    GPIO_OSPEEDR_OSPEEDR11
+#define GPIO_OSPEEDER_OSPEEDR11_0  GPIO_OSPEEDR_OSPEEDR11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1  GPIO_OSPEEDR_OSPEEDR11_1
+#define GPIO_OSPEEDER_OSPEEDR12    GPIO_OSPEEDR_OSPEEDR12
+#define GPIO_OSPEEDER_OSPEEDR12_0  GPIO_OSPEEDR_OSPEEDR12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1  GPIO_OSPEEDR_OSPEEDR12_1
+#define GPIO_OSPEEDER_OSPEEDR13    GPIO_OSPEEDR_OSPEEDR13
+#define GPIO_OSPEEDER_OSPEEDR13_0  GPIO_OSPEEDR_OSPEEDR13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1  GPIO_OSPEEDR_OSPEEDR13_1
+#define GPIO_OSPEEDER_OSPEEDR14    GPIO_OSPEEDR_OSPEEDR14
+#define GPIO_OSPEEDER_OSPEEDR14_0  GPIO_OSPEEDR_OSPEEDR14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1  GPIO_OSPEEDR_OSPEEDR14_1
+#define GPIO_OSPEEDER_OSPEEDR15    GPIO_OSPEEDR_OSPEEDR15
+#define GPIO_OSPEEDER_OSPEEDR15_0  GPIO_OSPEEDR_OSPEEDR15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1  GPIO_OSPEEDR_OSPEEDR15_1
+
+/*******************  Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPDR0          ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0        ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1        ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR1          ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0        ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1        ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR2          ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0        ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1        ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR3          ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0        ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1        ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR4          ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0        ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1        ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR5          ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0        ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1        ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR6          ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0        ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1        ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR7          ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0        ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1        ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR8          ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0        ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1        ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR9          ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0        ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1        ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR10         ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0       ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1       ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR11         ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0       ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1       ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR12         ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0       ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1       ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR13         ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0       ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1       ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR14         ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0       ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1       ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR15         ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0       ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1       ((uint32_t)0x80000000)
+
+/*******************  Bit definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_0                 ((uint32_t)0x00000001)
+#define GPIO_IDR_1                 ((uint32_t)0x00000002)
+#define GPIO_IDR_2                 ((uint32_t)0x00000004)
+#define GPIO_IDR_3                 ((uint32_t)0x00000008)
+#define GPIO_IDR_4                 ((uint32_t)0x00000010)
+#define GPIO_IDR_5                 ((uint32_t)0x00000020)
+#define GPIO_IDR_6                 ((uint32_t)0x00000040)
+#define GPIO_IDR_7                 ((uint32_t)0x00000080)
+#define GPIO_IDR_8                 ((uint32_t)0x00000100)
+#define GPIO_IDR_9                 ((uint32_t)0x00000200)
+#define GPIO_IDR_10                ((uint32_t)0x00000400)
+#define GPIO_IDR_11                ((uint32_t)0x00000800)
+#define GPIO_IDR_12                ((uint32_t)0x00001000)
+#define GPIO_IDR_13                ((uint32_t)0x00002000)
+#define GPIO_IDR_14                ((uint32_t)0x00004000)
+#define GPIO_IDR_15                ((uint32_t)0x00008000)
+
+/******************  Bit definition for GPIO_ODR register  ********************/
+#define GPIO_ODR_0                 ((uint32_t)0x00000001)
+#define GPIO_ODR_1                 ((uint32_t)0x00000002)
+#define GPIO_ODR_2                 ((uint32_t)0x00000004)
+#define GPIO_ODR_3                 ((uint32_t)0x00000008)
+#define GPIO_ODR_4                 ((uint32_t)0x00000010)
+#define GPIO_ODR_5                 ((uint32_t)0x00000020)
+#define GPIO_ODR_6                 ((uint32_t)0x00000040)
+#define GPIO_ODR_7                 ((uint32_t)0x00000080)
+#define GPIO_ODR_8                 ((uint32_t)0x00000100)
+#define GPIO_ODR_9                 ((uint32_t)0x00000200)
+#define GPIO_ODR_10                ((uint32_t)0x00000400)
+#define GPIO_ODR_11                ((uint32_t)0x00000800)
+#define GPIO_ODR_12                ((uint32_t)0x00001000)
+#define GPIO_ODR_13                ((uint32_t)0x00002000)
+#define GPIO_ODR_14                ((uint32_t)0x00004000)
+#define GPIO_ODR_15                ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_BSRR register  ********************/
+#define GPIO_BSRR_BS_0             ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1             ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2             ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3             ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4             ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5             ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6             ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7             ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8             ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9             ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10            ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11            ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12            ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13            ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14            ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15            ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0             ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1             ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2             ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3             ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4             ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5             ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6             ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7             ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8             ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9             ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10            ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11            ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12            ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13            ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14            ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15            ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register  ********************/
+#define GPIO_LCKR_LCK0             ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1             ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2             ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3             ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4             ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5             ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6             ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7             ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8             ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9             ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10            ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11            ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12            ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13            ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14            ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15            ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK             ((uint32_t)0x00010000)
+
+/****************** Bit definition for GPIO_AFRL register  ********************/
+#define GPIO_AFRL_AFR0            ((uint32_t)0x0000000F)
+#define GPIO_AFRL_AFR1            ((uint32_t)0x000000F0)
+#define GPIO_AFRL_AFR2            ((uint32_t)0x00000F00)
+#define GPIO_AFRL_AFR3            ((uint32_t)0x0000F000)
+#define GPIO_AFRL_AFR4            ((uint32_t)0x000F0000)
+#define GPIO_AFRL_AFR5            ((uint32_t)0x00F00000)
+#define GPIO_AFRL_AFR6            ((uint32_t)0x0F000000)
+#define GPIO_AFRL_AFR7            ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_AFRH register  ********************/
+#define GPIO_AFRH_AFR8            ((uint32_t)0x0000000F)
+#define GPIO_AFRH_AFR9            ((uint32_t)0x000000F0)
+#define GPIO_AFRH_AFR10            ((uint32_t)0x00000F00)
+#define GPIO_AFRH_AFR11            ((uint32_t)0x0000F000)
+#define GPIO_AFRH_AFR12            ((uint32_t)0x000F0000)
+#define GPIO_AFRH_AFR13            ((uint32_t)0x00F00000)
+#define GPIO_AFRH_AFR14            ((uint32_t)0x0F000000)
+#define GPIO_AFRH_AFR15            ((uint32_t)0xF0000000)
+
+/* Old Bit definition for GPIO_AFRL register maintained for legacy purpose ****/
+#define GPIO_AFRL_AFRL0            GPIO_AFRL_AFR0
+#define GPIO_AFRL_AFRL1            GPIO_AFRL_AFR1
+#define GPIO_AFRL_AFRL2            GPIO_AFRL_AFR2
+#define GPIO_AFRL_AFRL3            GPIO_AFRL_AFR3
+#define GPIO_AFRL_AFRL4            GPIO_AFRL_AFR4
+#define GPIO_AFRL_AFRL5            GPIO_AFRL_AFR5
+#define GPIO_AFRL_AFRL6            GPIO_AFRL_AFR6
+#define GPIO_AFRL_AFRL7            GPIO_AFRL_AFR7
+
+/* Old Bit definition for GPIO_AFRH register maintained for legacy purpose ****/
+#define GPIO_AFRH_AFRH0            GPIO_AFRH_AFR8
+#define GPIO_AFRH_AFRH1            GPIO_AFRH_AFR9
+#define GPIO_AFRH_AFRH2            GPIO_AFRH_AFR10
+#define GPIO_AFRH_AFRH3            GPIO_AFRH_AFR11
+#define GPIO_AFRH_AFRH4            GPIO_AFRH_AFR12
+#define GPIO_AFRH_AFRH5            GPIO_AFRH_AFR13
+#define GPIO_AFRH_AFRH6            GPIO_AFRH_AFR14
+#define GPIO_AFRH_AFRH7            GPIO_AFRH_AFR15
+
+/****************** Bit definition for GPIO_BRR register  *********************/
+#define GPIO_BRR_BR_0              ((uint32_t)0x00000001)
+#define GPIO_BRR_BR_1              ((uint32_t)0x00000002)
+#define GPIO_BRR_BR_2              ((uint32_t)0x00000004)
+#define GPIO_BRR_BR_3              ((uint32_t)0x00000008)
+#define GPIO_BRR_BR_4              ((uint32_t)0x00000010)
+#define GPIO_BRR_BR_5              ((uint32_t)0x00000020)
+#define GPIO_BRR_BR_6              ((uint32_t)0x00000040)
+#define GPIO_BRR_BR_7              ((uint32_t)0x00000080)
+#define GPIO_BRR_BR_8              ((uint32_t)0x00000100)
+#define GPIO_BRR_BR_9              ((uint32_t)0x00000200)
+#define GPIO_BRR_BR_10             ((uint32_t)0x00000400)
+#define GPIO_BRR_BR_11             ((uint32_t)0x00000800)
+#define GPIO_BRR_BR_12             ((uint32_t)0x00001000)
+#define GPIO_BRR_BR_13             ((uint32_t)0x00002000)
+#define GPIO_BRR_BR_14             ((uint32_t)0x00004000)
+#define GPIO_BRR_BR_15             ((uint32_t)0x00008000)
+
+/******************************************************************************/
+/*                                                                            */
+/*                   Inter-integrated Circuit Interface (I2C)                 */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define  I2C_CR1_PE                          ((uint32_t)0x00000001)        /*!< Peripheral enable */
+#define  I2C_CR1_TXIE                        ((uint32_t)0x00000002)        /*!< TX interrupt enable */
+#define  I2C_CR1_RXIE                        ((uint32_t)0x00000004)        /*!< RX interrupt enable */
+#define  I2C_CR1_ADDRIE                      ((uint32_t)0x00000008)        /*!< Address match interrupt enable */
+#define  I2C_CR1_NACKIE                      ((uint32_t)0x00000010)        /*!< NACK received interrupt enable */
+#define  I2C_CR1_STOPIE                      ((uint32_t)0x00000020)        /*!< STOP detection interrupt enable */
+#define  I2C_CR1_TCIE                        ((uint32_t)0x00000040)        /*!< Transfer complete interrupt enable */
+#define  I2C_CR1_ERRIE                       ((uint32_t)0x00000080)        /*!< Errors interrupt enable */
+#define  I2C_CR1_DFN                         ((uint32_t)0x00000F00)        /*!< Digital noise filter */
+#define  I2C_CR1_ANFOFF                      ((uint32_t)0x00001000)        /*!< Analog noise filter OFF */
+#define  I2C_CR1_SWRST                       ((uint32_t)0x00002000)        /*!< Software reset */
+#define  I2C_CR1_TXDMAEN                     ((uint32_t)0x00004000)        /*!< DMA transmission requests enable */
+#define  I2C_CR1_RXDMAEN                     ((uint32_t)0x00008000)        /*!< DMA reception requests enable */
+#define  I2C_CR1_SBC                         ((uint32_t)0x00010000)        /*!< Slave byte control */
+#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00020000)        /*!< Clock stretching disable */
+#define  I2C_CR1_WUPEN                       ((uint32_t)0x00040000)        /*!< Wakeup from STOP enable */
+#define  I2C_CR1_GCEN                        ((uint32_t)0x00080000)        /*!< General call enable */
+#define  I2C_CR1_SMBHEN                      ((uint32_t)0x00100000)        /*!< SMBus host address enable */
+#define  I2C_CR1_SMBDEN                      ((uint32_t)0x00200000)        /*!< SMBus device default address enable */
+#define  I2C_CR1_ALERTEN                     ((uint32_t)0x00400000)        /*!< SMBus alert enable */
+#define  I2C_CR1_PECEN                       ((uint32_t)0x00800000)        /*!< PEC enable */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define  I2C_CR2_SADD                        ((uint32_t)0x000003FF)        /*!< Slave address (master mode) */
+#define  I2C_CR2_RD_WRN                      ((uint32_t)0x00000400)        /*!< Transfer direction (master mode) */
+#define  I2C_CR2_ADD10                       ((uint32_t)0x00000800)        /*!< 10-bit addressing mode (master mode) */
+#define  I2C_CR2_HEAD10R                     ((uint32_t)0x00001000)        /*!< 10-bit address header only read direction (master mode) */
+#define  I2C_CR2_START                       ((uint32_t)0x00002000)        /*!< START generation */
+#define  I2C_CR2_STOP                        ((uint32_t)0x00004000)        /*!< STOP generation (master mode) */
+#define  I2C_CR2_NACK                        ((uint32_t)0x00008000)        /*!< NACK generation (slave mode) */
+#define  I2C_CR2_NBYTES                      ((uint32_t)0x00FF0000)        /*!< Number of bytes */
+#define  I2C_CR2_RELOAD                      ((uint32_t)0x01000000)        /*!< NBYTES reload mode */
+#define  I2C_CR2_AUTOEND                     ((uint32_t)0x02000000)        /*!< Automatic end mode (master mode) */
+#define  I2C_CR2_PECBYTE                     ((uint32_t)0x04000000)        /*!< Packet error checking byte */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define  I2C_OAR1_OA1                        ((uint32_t)0x000003FF)        /*!< Interface own address 1 */
+#define  I2C_OAR1_OA1MODE                    ((uint32_t)0x00000400)        /*!< Own address 1 10-bit mode */
+#define  I2C_OAR1_OA1EN                      ((uint32_t)0x00008000)        /*!< Own address 1 enable */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define  I2C_OAR2_OA2                        ((uint32_t)0x000000FE)        /*!< Interface own address 2 */
+#define  I2C_OAR2_OA2MSK                     ((uint32_t)0x00000700)        /*!< Own address 2 masks */
+#define  I2C_OAR2_OA2EN                      ((uint32_t)0x00008000)        /*!< Own address 2 enable */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define  I2C_TIMINGR_SCLL                    ((uint32_t)0x000000FF)        /*!< SCL low period (master mode) */
+#define  I2C_TIMINGR_SCLH                    ((uint32_t)0x0000FF00)        /*!< SCL high period (master mode) */
+#define  I2C_TIMINGR_SDADEL                  ((uint32_t)0x000F0000)        /*!< Data hold time */
+#define  I2C_TIMINGR_SCLDEL                  ((uint32_t)0x00F00000)        /*!< Data setup time */
+#define  I2C_TIMINGR_PRESC                   ((uint32_t)0xF0000000)        /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define  I2C_TIMEOUTR_TIMEOUTA               ((uint32_t)0x00000FFF)        /*!< Bus timeout A */
+#define  I2C_TIMEOUTR_TIDLE                  ((uint32_t)0x00001000)        /*!< Idle clock timeout detection */
+#define  I2C_TIMEOUTR_TIMOUTEN               ((uint32_t)0x00008000)        /*!< Clock timeout enable */
+#define  I2C_TIMEOUTR_TIMEOUTB               ((uint32_t)0x0FFF0000)        /*!< Bus timeout B*/
+#define  I2C_TIMEOUTR_TEXTEN                 ((uint32_t)0x80000000)        /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define  I2C_ISR_TXE                         ((uint32_t)0x00000001)        /*!< Transmit data register empty */
+#define  I2C_ISR_TXIS                        ((uint32_t)0x00000002)        /*!< Transmit interrupt status */
+#define  I2C_ISR_RXNE                        ((uint32_t)0x00000004)        /*!< Receive data register not empty */
+#define  I2C_ISR_ADDR                        ((uint32_t)0x00000008)        /*!< Address matched (slave mode)*/
+#define  I2C_ISR_NACKF                       ((uint32_t)0x00000010)        /*!< NACK received flag */
+#define  I2C_ISR_STOPF                       ((uint32_t)0x00000020)        /*!< STOP detection flag */
+#define  I2C_ISR_TC                          ((uint32_t)0x00000040)        /*!< Transfer complete (master mode) */
+#define  I2C_ISR_TCR                         ((uint32_t)0x00000080)        /*!< Transfer complete reload */
+#define  I2C_ISR_BERR                        ((uint32_t)0x00000100)        /*!< Bus error */
+#define  I2C_ISR_ARLO                        ((uint32_t)0x00000200)        /*!< Arbitration lost */
+#define  I2C_ISR_OVR                         ((uint32_t)0x00000400)        /*!< Overrun/Underrun */
+#define  I2C_ISR_PECERR                      ((uint32_t)0x00000800)        /*!< PEC error in reception */
+#define  I2C_ISR_TIMEOUT                     ((uint32_t)0x00001000)        /*!< Timeout or Tlow detection flag */
+#define  I2C_ISR_ALERT                       ((uint32_t)0x00002000)        /*!< SMBus alert */
+#define  I2C_ISR_BUSY                        ((uint32_t)0x00008000)        /*!< Bus busy */
+#define  I2C_ISR_DIR                         ((uint32_t)0x00010000)        /*!< Transfer direction (slave mode) */
+#define  I2C_ISR_ADDCODE                     ((uint32_t)0x00FE0000)        /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define  I2C_ICR_ADDRCF                      ((uint32_t)0x00000008)        /*!< Address matched clear flag */
+#define  I2C_ICR_NACKCF                      ((uint32_t)0x00000010)        /*!< NACK clear flag */
+#define  I2C_ICR_STOPCF                      ((uint32_t)0x00000020)        /*!< STOP detection clear flag */
+#define  I2C_ICR_BERRCF                      ((uint32_t)0x00000100)        /*!< Bus error clear flag */
+#define  I2C_ICR_ARLOCF                      ((uint32_t)0x00000200)        /*!< Arbitration lost clear flag */
+#define  I2C_ICR_OVRCF                       ((uint32_t)0x00000400)        /*!< Overrun/Underrun clear flag */
+#define  I2C_ICR_PECCF                       ((uint32_t)0x00000800)        /*!< PAC error clear flag */
+#define  I2C_ICR_TIMOUTCF                    ((uint32_t)0x00001000)        /*!< Timeout clear flag */
+#define  I2C_ICR_ALERTCF                     ((uint32_t)0x00002000)        /*!< Alert clear flag */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define  I2C_PECR_PEC                        ((uint32_t)0x000000FF)       /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define  I2C_RXDR_RXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define  I2C_TXDR_TXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Independent WATCHDOG (IWDG)                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */
+#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */
+#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */
+#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */
+#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */
+#define  IWDG_SR_WVU                         ((uint8_t)0x04)               /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_WINR_WIN                         ((uint16_t)0x0FFF)            /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Power Control (PWR)                               */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for PWR_CR register  ********************/
+#define  PWR_CR_LPDS                         ((uint16_t)0x0001)     /*!< Low-power deepsleep/sleep */
+#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
+#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
+#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
+#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
+
+#define  PWR_CR_PLS                          ((uint16_t)0x00E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */
+/* PVD level configuration */
+#define  PWR_CR_PLS_LEV0                     ((uint16_t)0x0000)     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     ((uint16_t)0x0020)     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     ((uint16_t)0x0040)     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     ((uint16_t)0x0060)     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     ((uint16_t)0x0080)     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     ((uint16_t)0x00A0)     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     ((uint16_t)0x00C0)     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     ((uint16_t)0x00E0)     /*!< PVD level 7 */
+
+#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
+
+/* Old Bit definition maintained for legacy purpose ****/
+#define  PWR_CR_LPSDSR                       PWR_CR_LPDS     /*!< Low-power deepsleep */
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
+#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
+#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
+#define  PWR_CSR_VREFINTRDY                  ((uint16_t)0x0008)     /*!< Internal voltage reference (VREFINT) ready */
+
+#define  PWR_CSR_EWUP1                       ((uint16_t)0x0100)     /*!< Enable WKUP pin 1 */
+#define  PWR_CSR_EWUP2                       ((uint16_t)0x0200)     /*!< Enable WKUP pin 2 */
+#define  PWR_CSR_EWUP3                       ((uint16_t)0x0400)     /*!< Enable WKUP pin 3 */
+#define  PWR_CSR_EWUP4                       ((uint16_t)0x0800)     /*!< Enable WKUP pin 4 */
+#define  PWR_CSR_EWUP5                       ((uint16_t)0x1000)     /*!< Enable WKUP pin 5 */
+#define  PWR_CSR_EWUP6                       ((uint16_t)0x2000)     /*!< Enable WKUP pin 6 */
+#define  PWR_CSR_EWUP7                       ((uint16_t)0x4000)     /*!< Enable WKUP pin 7 */
+#define  PWR_CSR_EWUP8                       ((uint16_t)0x8000)     /*!< Enable WKUP pin 8 */
+
+/* Old Bit definition maintained for legacy purpose ****/
+#define  PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDY     /*!< Internal voltage reference (VREFINT) ready flag */
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for RCC_CR register  ********************/
+#define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
+#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */
+#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)        /*!< Internal High Speed clock trimming */
+#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)        /*!< Internal High Speed clock Calibration */
+#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
+#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
+#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
+#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)        /*!< Clock Security System enable */
+#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
+#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
+
+/*******************  Bit definition for RCC_CFGR register  *******************/
+#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
+/* SW configuration */
+#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
+#define  RCC_CFGR_SW_HSI48                   ((uint32_t)0x00000003)        /*!< HSI48 selected as system clock */
+
+#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
+/* SWS configuration */
+#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
+#define  RCC_CFGR_SWS_HSI48                  ((uint32_t)0x0000000C)        /*!< HSI48 used as system clock */
+
+#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
+/* HPRE configuration */
+#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
+
+#define  RCC_CFGR_PPRE                       ((uint32_t)0x00000700)        /*!< PRE[2:0] bits (APB prescaler) */
+#define  RCC_CFGR_PPRE_0                     ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE_1                     ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE_2                     ((uint32_t)0x00000400)        /*!< Bit 2 */
+/* PPRE configuration */
+#define  RCC_CFGR_PPRE_DIV1                  ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE_DIV2                  ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE_DIV4                  ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE_DIV8                  ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE_DIV16                 ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
+
+#define  RCC_CFGR_ADCPRE                     ((uint32_t)0x00004000)        /*!< ADC prescaler: Obsolete. Proper ADC clock selection is 
+                                                                                done inside the ADC_CFGR2 */
+
+#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00018000)        /*!< PLL entry clock source */
+#define  RCC_CFGR_PLLSRC_0                   ((uint32_t)0x00008000)        /*!< Bit 0 (available only in the STM32F072 devices) */
+#define  RCC_CFGR_PLLSRC_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
+
+#define  RCC_CFGR_PLLSRC_PREDIV1             ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source; 
+                                                                                Old PREDIV1 bit definition, maintained for legacy purpose */
+#define  RCC_CFGR_PLLSRC_HSI_DIV2            ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#define  RCC_CFGR_PLLSRC_HSI_PREDIV          ((uint32_t)0x00008000)        /*!< HSI PREDIV clock selected as PLL entry clock source 
+                                                                                (This bit and configuration is only available for STM32F072 devices)*/
+#define  RCC_CFGR_PLLSRC_HSE_PREDIV          ((uint32_t)0x00010000)        /*!< HSE PREDIV clock selected as PLL entry clock source */
+#define  RCC_CFGR_PLLSRC_HSI48_PREDIV        ((uint32_t)0x00018000)        /*!< HSI48 PREDIV clock selected as PLL entry clock source */
+
+#define  RCC_CFGR_PLLXTPRE                   ((uint32_t)0x00020000)        /*!< HSE divider for PLL entry */
+#define  RCC_CFGR_PLLXTPRE_PREDIV1           ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
+#define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2      ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+/*!< Old bit definition maintained for legacy purposes */
+#define  RCC_CFGR_PLLSRC_HSI_Div2            RCC_CFGR_PLLSRC_HSI_DIV2
+
+/* PLLMUL configuration */
+#define  RCC_CFGR_PLLMUL                    ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define  RCC_CFGR_PLLMUL_0                  ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  RCC_CFGR_PLLMUL_1                  ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  RCC_CFGR_PLLMUL_2                  ((uint32_t)0x00100000)        /*!< Bit 2 */
+#define  RCC_CFGR_PLLMUL_3                  ((uint32_t)0x00200000)        /*!< Bit 3 */
+
+#define  RCC_CFGR_PLLMUL2                   ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
+#define  RCC_CFGR_PLLMUL3                   ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
+#define  RCC_CFGR_PLLMUL4                   ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
+#define  RCC_CFGR_PLLMUL5                   ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
+#define  RCC_CFGR_PLLMUL6                   ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
+#define  RCC_CFGR_PLLMUL7                   ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
+#define  RCC_CFGR_PLLMUL8                   ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
+#define  RCC_CFGR_PLLMUL9                   ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
+#define  RCC_CFGR_PLLMUL10                  ((uint32_t)0x00200000)        /*!< PLL input clock10 */
+#define  RCC_CFGR_PLLMUL11                  ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
+#define  RCC_CFGR_PLLMUL12                  ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
+#define  RCC_CFGR_PLLMUL13                  ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
+#define  RCC_CFGR_PLLMUL14                  ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
+#define  RCC_CFGR_PLLMUL15                  ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
+#define  RCC_CFGR_PLLMUL16                  ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
+
+/* Old PLLMUL configuration bit definition maintained for legacy purposes */
+#define  RCC_CFGR_PLLMULL                    RCC_CFGR_PLLMUL        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define  RCC_CFGR_PLLMULL_0                  RCC_CFGR_PLLMUL_0        /*!< Bit 0 */
+#define  RCC_CFGR_PLLMULL_1                  RCC_CFGR_PLLMUL_1        /*!< Bit 1 */
+#define  RCC_CFGR_PLLMULL_2                  RCC_CFGR_PLLMUL_2        /*!< Bit 2 */
+#define  RCC_CFGR_PLLMULL_3                  RCC_CFGR_PLLMUL_3       /*!< Bit 3 */
+
+#define  RCC_CFGR_PLLMULL2                   RCC_CFGR_PLLMUL2       /*!< PLL input clock*2 */
+#define  RCC_CFGR_PLLMULL3                   RCC_CFGR_PLLMUL3        /*!< PLL input clock*3 */
+#define  RCC_CFGR_PLLMULL4                   RCC_CFGR_PLLMUL4        /*!< PLL input clock*4 */
+#define  RCC_CFGR_PLLMULL5                   RCC_CFGR_PLLMUL5        /*!< PLL input clock*5 */
+#define  RCC_CFGR_PLLMULL6                   RCC_CFGR_PLLMUL6        /*!< PLL input clock*6 */
+#define  RCC_CFGR_PLLMULL7                   RCC_CFGR_PLLMUL7        /*!< PLL input clock*7 */
+#define  RCC_CFGR_PLLMULL8                   RCC_CFGR_PLLMUL8        /*!< PLL input clock*8 */
+#define  RCC_CFGR_PLLMULL9                   RCC_CFGR_PLLMUL9        /*!< PLL input clock*9 */
+#define  RCC_CFGR_PLLMULL10                  RCC_CFGR_PLLMUL10        /*!< PLL input clock10 */
+#define  RCC_CFGR_PLLMULL11                  RCC_CFGR_PLLMUL11        /*!< PLL input clock*11 */
+#define  RCC_CFGR_PLLMULL12                  RCC_CFGR_PLLMUL12        /*!< PLL input clock*12 */
+#define  RCC_CFGR_PLLMULL13                  RCC_CFGR_PLLMUL13        /*!< PLL input clock*13 */
+#define  RCC_CFGR_PLLMULL14                  RCC_CFGR_PLLMUL14        /*!< PLL input clock*14 */
+#define  RCC_CFGR_PLLMULL15                  RCC_CFGR_PLLMUL15        /*!< PLL input clock*15 */
+#define  RCC_CFGR_PLLMULL16                  RCC_CFGR_PLLMUL16        /*!< PLL input clock*16 */
+
+#define  RCC_CFGR_MCO                        ((uint32_t)0x0F000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define  RCC_CFGR_MCO_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  RCC_CFGR_MCO_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  RCC_CFGR_MCO_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  RCC_CFGR_MCO_3                      ((uint32_t)0x08000000)        /*!< Bit 3 */
+/* MCO configuration */
+#define  RCC_CFGR_MCO_NOCLOCK                ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_CFGR_MCO_HSI14                  ((uint32_t)0x01000000)        /*!< HSI14 clock selected as MCO source */
+#define  RCC_CFGR_MCO_LSI                    ((uint32_t)0x02000000)        /*!< LSI clock selected as MCO source */
+#define  RCC_CFGR_MCO_LSE                    ((uint32_t)0x03000000)        /*!< LSE clock selected as MCO source */
+#define  RCC_CFGR_MCO_SYSCLK                 ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSI                    ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSE                    ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
+#define  RCC_CFGR_MCO_PLL                    ((uint32_t)0x07000000)        /*!< PLL clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSI48                  ((uint32_t)0x08000000)        /*!< HSI48 clock selected as MCO source */
+
+#define  RCC_CFGR_MCO_PRE                    ((uint32_t)0x70000000)        /*!< MCO prescaler (these bits are not available in the STM32F051 devices)*/
+#define  RCC_CFGR_MCO_PRE_1                  ((uint32_t)0x00000000)        /*!< MCO is divided by 1 (this bit are not available in the STM32F051 devices)*/
+#define  RCC_CFGR_MCO_PRE_2                  ((uint32_t)0x10000000)        /*!< MCO is divided by 2 (this bit are not available in the STM32F051 devices)*/
+#define  RCC_CFGR_MCO_PRE_4                  ((uint32_t)0x20000000)        /*!< MCO is divided by 4 (this bit are not available in the STM32F051 devices)*/
+#define  RCC_CFGR_MCO_PRE_8                  ((uint32_t)0x30000000)        /*!< MCO is divided by 8 (this bit are not available in the STM32F051 devices)*/
+#define  RCC_CFGR_MCO_PRE_16                 ((uint32_t)0x40000000)        /*!< MCO is divided by 16 (this bit are not available in the STM32F051 devices)*/
+#define  RCC_CFGR_MCO_PRE_32                 ((uint32_t)0x50000000)        /*!< MCO is divided by 32 (this bit are not available in the STM32F051 devices)*/
+#define  RCC_CFGR_MCO_PRE_64                 ((uint32_t)0x60000000)        /*!< MCO is divided by 64 (this bit are not available in the STM32F051 devices)*/
+#define  RCC_CFGR_MCO_PRE_128                ((uint32_t)0x70000000)        /*!< MCO is divided by 128 (this bit are not available in the STM32F051 devices)*/
+
+#define  RCC_CFGR_PLLNODIV                   ((uint32_t)0x80000000)        /*!< PLL is not divided to MCO (this bit are not available in the STM32F051 devices) */
+
+/*******************  Bit definition for RCC_CIR register  ********************/
+#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
+#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
+#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
+#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
+#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
+#define  RCC_CIR_HSI14RDYF                   ((uint32_t)0x00000020)        /*!< HSI14 Ready Interrupt flag */
+#define  RCC_CIR_HSI48RDYF                   ((uint32_t)0x00000040)        /*!< HSI48 Ready Interrupt flag */
+#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
+#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
+#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
+#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
+#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
+#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
+#define  RCC_CIR_HSI14RDYIE                  ((uint32_t)0x00002000)        /*!< HSI14 Ready Interrupt Enable */
+#define  RCC_CIR_HSI48RDYIE                  ((uint32_t)0x00004000)        /*!< HSI48 Ready Interrupt Enable */
+#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
+#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
+#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
+#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
+#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
+#define  RCC_CIR_HSI14RDYC                   ((uint32_t)0x00200000)        /*!< HSI14 Ready Interrupt Clear */
+#define  RCC_CIR_HSI48RDYC                   ((uint32_t)0x00400000)        /*!< HSI48 Ready Interrupt Clear */
+#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
+
+/*****************  Bit definition for RCC_APB2RSTR register  *****************/
+#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00000001)        /*!< SYSCFG clock reset */
+#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000200)        /*!< ADC clock reset */
+#define  RCC_APB2RSTR_USART8RST              ((uint32_t)0x00000080)        /*!< USART8 clock reset */
+#define  RCC_APB2RSTR_USART7RST              ((uint32_t)0x00000040)        /*!< USART7 clock reset */
+#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020)        /*!< USART6 clock reset */
+#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000800)        /*!< TIM1 clock reset */
+#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI1 clock reset */
+#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 clock reset */
+#define  RCC_APB2RSTR_TIM15RST               ((uint32_t)0x00010000)        /*!< TIM15 clock reset */
+#define  RCC_APB2RSTR_TIM16RST               ((uint32_t)0x00020000)        /*!< TIM16 clock reset */
+#define  RCC_APB2RSTR_TIM17RST               ((uint32_t)0x00040000)        /*!< TIM17 clock reset */
+#define  RCC_APB2RSTR_DBGMCURST              ((uint32_t)0x00400000)        /*!< DBGMCU clock reset */
+
+/* Old ADC1 clock reset bit definition maintained for legacy purpose */
+#define  RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST          
+
+/*****************  Bit definition for RCC_APB1RSTR register  *****************/
+#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 clock reset */
+#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 clock reset */
+#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 clock reset */
+#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 clock reset */
+#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)        /*!< Timer 14 clock reset */
+#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog clock reset */
+#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)        /*!< SPI2 clock reset */
+#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 clock reset */
+#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)        /*!< USART 3 clock reset */
+#define  RCC_APB1RSTR_USART4RST              ((uint32_t)0x00080000)        /*!< USART 4 clock reset */
+#define  RCC_APB1RSTR_USART5RST              ((uint32_t)0x00100000)        /*!< USART 5 clock reset */
+#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 clock reset */
+#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)        /*!< I2C 2 clock reset */
+#define  RCC_APB1RSTR_USBRST                 ((uint32_t)0x00800000)        /*!< USB clock reset */
+#define  RCC_APB1RSTR_CANRST                 ((uint32_t)0x02000000)        /*!< CAN clock reset */
+#define  RCC_APB1RSTR_CRSRST                 ((uint32_t)0x08000000)        /*!< CRS clock reset */
+#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< PWR clock reset */
+#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC clock reset */
+#define  RCC_APB1RSTR_CECRST                 ((uint32_t)0x40000000)        /*!< CEC clock reset */
+
+/******************  Bit definition for RCC_AHBENR register  ******************/
+#define  RCC_AHBENR_DMAEN                    ((uint32_t)0x00000001)        /*!< DMA clock enable */
+#define  RCC_AHBENR_DMA2EN                   ((uint32_t)0x00000002)        /*!< DMA2 clock enable */
+#define  RCC_AHBENR_SRAMEN                   ((uint32_t)0x00000004)        /*!< SRAM interface clock enable */
+#define  RCC_AHBENR_FLITFEN                  ((uint32_t)0x00000010)        /*!< FLITF clock enable */
+#define  RCC_AHBENR_CRCEN                    ((uint32_t)0x00000040)        /*!< CRC clock enable */
+#define  RCC_AHBENR_GPIOAEN                  ((uint32_t)0x00020000)        /*!< GPIOA clock enable */
+#define  RCC_AHBENR_GPIOBEN                  ((uint32_t)0x00040000)        /*!< GPIOB clock enable */
+#define  RCC_AHBENR_GPIOCEN                  ((uint32_t)0x00080000)        /*!< GPIOC clock enable */
+#define  RCC_AHBENR_GPIODEN                  ((uint32_t)0x00100000)        /*!< GPIOD clock enable */
+#define  RCC_AHBENR_GPIOEEN                  ((uint32_t)0x00200000)        /*!< GPIOE clock enable */
+#define  RCC_AHBENR_GPIOFEN                  ((uint32_t)0x00400000)        /*!< GPIOF clock enable */
+#define  RCC_AHBENR_TSCEN                    ((uint32_t)0x01000000)        /*!< TS controller clock enable */
+
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN        /*!< DMA1 clock enable */
+#define  RCC_AHBENR_TSEN                     RCC_AHBENR_TSCEN        /*!< TS clock enable */
+
+/*****************  Bit definition for RCC_APB2ENR register  ******************/
+#define  RCC_APB2ENR_SYSCFGCOMPEN            ((uint32_t)0x00000001)        /*!< SYSCFG and comparator clock enable */
+#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020)        /*!< USART6 clock enable */
+#define  RCC_APB2ENR_USART7EN                ((uint32_t)0x00000040)        /*!< USART7 clock enable */
+#define  RCC_APB2ENR_USART8EN                ((uint32_t)0x00000080)        /*!< USART8 clock enable */
+#define  RCC_APB2ENR_ADCEN                   ((uint32_t)0x00000200)        /*!< ADC1 clock enable */
+#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000800)        /*!< TIM1 clock enable */
+#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)        /*!< SPI1 clock enable */
+#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)        /*!< USART1 clock enable */
+#define  RCC_APB2ENR_TIM15EN                 ((uint32_t)0x00010000)        /*!< TIM15 clock enable */
+#define  RCC_APB2ENR_TIM16EN                 ((uint32_t)0x00020000)        /*!< TIM16 clock enable */
+#define  RCC_APB2ENR_TIM17EN                 ((uint32_t)0x00040000)        /*!< TIM17 clock enable */
+#define  RCC_APB2ENR_DBGMCUEN                ((uint32_t)0x00400000)        /*!< DBGMCU clock enable */
+
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGCOMPEN        /*!< SYSCFG clock enable */
+#define  RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN               /*!< ADC1 clock enable */
+
+/*****************  Bit definition for RCC_APB1ENR register  ******************/
+#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enable */
+#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
+#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
+#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
+#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100)        /*!< Timer 14 clock enable */
+#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
+#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)        /*!< SPI2 clock enable */
+#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART2 clock enable */
+#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)        /*!< USART3 clock enable */
+#define  RCC_APB1ENR_USART4EN                ((uint32_t)0x00080000)        /*!< USART4 clock enable */
+#define  RCC_APB1ENR_USART5EN                ((uint32_t)0x00100000)        /*!< USART5 clock enable */
+#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C1 clock enable */
+#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)        /*!< I2C2 clock enable */
+#define  RCC_APB1ENR_USBEN                   ((uint32_t)0x00800000)        /*!< USB clock enable */
+#define  RCC_APB1ENR_CANEN                   ((uint32_t)0x02000000)         /*!< CAN clock enable */
+#define  RCC_APB1ENR_CRSEN                   ((uint32_t)0x08000000)        /*!< CRS clock enable */
+#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< PWR clock enable */
+#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)        /*!< DAC clock enable */
+#define  RCC_APB1ENR_CECEN                   ((uint32_t)0x40000000)        /*!< CEC clock enable */
+
+/*******************  Bit definition for RCC_BDCR register  *******************/
+#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)        /*!< External Low Speed oscillator enable */
+#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)        /*!< External Low Speed oscillator Ready */
+#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)        /*!< External Low Speed oscillator Bypass */
+
+#define  RCC_BDCR_LSEDRV                     ((uint32_t)0x00000018)        /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define  RCC_BDCR_LSEDRV_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  RCC_BDCR_LSEDRV_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
+
+#define  RCC_BDCR_RTCSEL                     ((uint32_t)0x00000300)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define  RCC_BDCR_RTCSEL_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_BDCR_RTCSEL_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+/* RTC configuration */
+#define  RCC_BDCR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_BDCR_RTCSEL_LSE                 ((uint32_t)0x00000100)        /*!< LSE oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_LSI                 ((uint32_t)0x00000200)        /*!< LSI oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_HSE                 ((uint32_t)0x00000300)        /*!< HSE oscillator clock divided by 32 used as RTC clock */
+
+#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)        /*!< RTC clock enable */
+#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)        /*!< Backup domain software reset  */
+
+/*******************  Bit definition for RCC_CSR register  ********************/  
+#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
+#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
+#define  RCC_CSR_V18PWRRSTF                  ((uint32_t)0x00800000)        /*!< V1.8 power domain reset flag */
+#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)        /*!< Remove reset flag */
+#define  RCC_CSR_OBLRSTF                     ((uint32_t)0x02000000)        /*!< OBL reset flag */
+#define  RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)        /*!< PIN reset flag */
+#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
+#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */
+#define  RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
+#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
+#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
+
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_CSR_OBL                         RCC_CSR_OBLRSTF        /*!< OBL reset flag */
+/*******************  Bit definition for RCC_AHBRSTR register  ****************/
+#define  RCC_AHBRSTR_GPIOARST                ((uint32_t)0x00020000)         /*!< GPIOA clock reset */
+#define  RCC_AHBRSTR_GPIOBRST                ((uint32_t)0x00040000)         /*!< GPIOB clock reset */
+#define  RCC_AHBRSTR_GPIOCRST                ((uint32_t)0x00080000)         /*!< GPIOC clock reset */
+#define  RCC_AHBRSTR_GPIODRST                ((uint32_t)0x00010000)         /*!< GPIOD clock reset */
+#define  RCC_AHBRSTR_GPIOERST                ((uint32_t)0x00020000)         /*!< GPIOE clock reset */
+#define  RCC_AHBRSTR_GPIOFRST                ((uint32_t)0x00040000)         /*!< GPIOF clock reset */
+#define  RCC_AHBRSTR_TSCRST                  ((uint32_t)0x00100000)         /*!< TS clock reset */
+
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_AHBRSTR_TSRST                   RCC_AHBRSTR_TSCRST         /*!< TS clock reset */
+
+/*******************  Bit definition for RCC_CFGR2 register  ******************/
+/* PREDIV1 configuration */
+#define  RCC_CFGR2_PREDIV1                   ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
+#define  RCC_CFGR2_PREDIV1_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR2_PREDIV1_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  RCC_CFGR2_PREDIV1_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  RCC_CFGR2_PREDIV1_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  RCC_CFGR2_PREDIV1_DIV1              ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
+#define  RCC_CFGR2_PREDIV1_DIV2              ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
+#define  RCC_CFGR2_PREDIV1_DIV3              ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
+#define  RCC_CFGR2_PREDIV1_DIV4              ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
+#define  RCC_CFGR2_PREDIV1_DIV5              ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
+#define  RCC_CFGR2_PREDIV1_DIV6              ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
+#define  RCC_CFGR2_PREDIV1_DIV7              ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
+#define  RCC_CFGR2_PREDIV1_DIV8              ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
+#define  RCC_CFGR2_PREDIV1_DIV9              ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
+#define  RCC_CFGR2_PREDIV1_DIV10             ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
+#define  RCC_CFGR2_PREDIV1_DIV11             ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
+#define  RCC_CFGR2_PREDIV1_DIV12             ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
+#define  RCC_CFGR2_PREDIV1_DIV13             ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
+#define  RCC_CFGR2_PREDIV1_DIV14             ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
+#define  RCC_CFGR2_PREDIV1_DIV15             ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
+#define  RCC_CFGR2_PREDIV1_DIV16             ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
+
+/*******************  Bit definition for RCC_CFGR3 register  ******************/
+#define  RCC_CFGR3_USART1SW                  ((uint32_t)0x00000003)        /*!< USART1SW[1:0] bits */
+#define  RCC_CFGR3_USART1SW_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR3_USART1SW_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  RCC_CFGR3_I2C1SW                    ((uint32_t)0x00000010)        /*!< I2C1SW bits */
+#define  RCC_CFGR3_CECSW                     ((uint32_t)0x00000040)        /*!< CECSW bits */
+#define  RCC_CFGR3_USBSW                     ((uint32_t)0x00000080)        /*!< USBSW bits */
+#define  RCC_CFGR3_ADCSW                     ((uint32_t)0x00000100)        /*!< ADCSW bits */
+#define  RCC_CFGR3_USART2SW                  ((uint32_t)0x00030000)        /*!< USART2SW[1:0] bits */
+#define  RCC_CFGR3_USART2SW_0                ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  RCC_CFGR3_USART2SW_1                ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  RCC_CFGR3_USART3SW                  ((uint32_t)0x000C0000)        /*!< USART3SW[1:0] bits */
+#define  RCC_CFGR3_USART3SW_0                ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  RCC_CFGR3_USART3SW_1                ((uint32_t)0x00080000)        /*!< Bit 1 */
+
+
+/*******************  Bit definition for RCC_CR2 register  ********************/
+#define  RCC_CR2_HSI14ON                     ((uint32_t)0x00000001)        /*!< Internal High Speed 14MHz clock enable */
+#define  RCC_CR2_HSI14RDY                    ((uint32_t)0x00000002)        /*!< Internal High Speed 14MHz clock ready flag */
+#define  RCC_CR2_HSI14DIS                    ((uint32_t)0x00000004)        /*!< Internal High Speed 14MHz clock disable */
+#define  RCC_CR2_HSI14TRIM                   ((uint32_t)0x000000F8)        /*!< Internal High Speed 14MHz clock trimming */
+#define  RCC_CR2_HSI14CAL                    ((uint32_t)0x0000FF00)        /*!< Internal High Speed 14MHz clock Calibration */
+#define  RCC_CR2_HSI48ON                     ((uint32_t)0x00010000)        /*!< Internal High Speed 48MHz clock enable */
+#define  RCC_CR2_HSI48RDY                    ((uint32_t)0x00020000)        /*!< Internal High Speed 48MHz clock ready flag */
+#define  RCC_CR2_HSI48CAL                    ((uint32_t)0xFF000000)        /*!< Internal High Speed 48MHz clock Calibration */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM                            ((uint32_t)0x00400000)
+#define RTC_TR_HT                            ((uint32_t)0x00300000)        
+#define RTC_TR_HT_0                          ((uint32_t)0x00100000)        
+#define RTC_TR_HT_1                          ((uint32_t)0x00200000)        
+#define RTC_TR_HU                            ((uint32_t)0x000F0000)        
+#define RTC_TR_HU_0                          ((uint32_t)0x00010000)        
+#define RTC_TR_HU_1                          ((uint32_t)0x00020000)        
+#define RTC_TR_HU_2                          ((uint32_t)0x00040000)        
+#define RTC_TR_HU_3                          ((uint32_t)0x00080000)        
+#define RTC_TR_MNT                           ((uint32_t)0x00007000)        
+#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)        
+#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)        
+#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)        
+#define RTC_TR_MNU                           ((uint32_t)0x00000F00)        
+#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)        
+#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)        
+#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)        
+#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)        
+#define RTC_TR_ST                            ((uint32_t)0x00000070)        
+#define RTC_TR_ST_0                          ((uint32_t)0x00000010)        
+#define RTC_TR_ST_1                          ((uint32_t)0x00000020)        
+#define RTC_TR_ST_2                          ((uint32_t)0x00000040)        
+#define RTC_TR_SU                            ((uint32_t)0x0000000F)        
+#define RTC_TR_SU_0                          ((uint32_t)0x00000001)        
+#define RTC_TR_SU_1                          ((uint32_t)0x00000002)        
+#define RTC_TR_SU_2                          ((uint32_t)0x00000004)        
+#define RTC_TR_SU_3                          ((uint32_t)0x00000008)        
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT                            ((uint32_t)0x00F00000)        
+#define RTC_DR_YT_0                          ((uint32_t)0x00100000)        
+#define RTC_DR_YT_1                          ((uint32_t)0x00200000)        
+#define RTC_DR_YT_2                          ((uint32_t)0x00400000)        
+#define RTC_DR_YT_3                          ((uint32_t)0x00800000)        
+#define RTC_DR_YU                            ((uint32_t)0x000F0000)        
+#define RTC_DR_YU_0                          ((uint32_t)0x00010000)        
+#define RTC_DR_YU_1                          ((uint32_t)0x00020000)        
+#define RTC_DR_YU_2                          ((uint32_t)0x00040000)        
+#define RTC_DR_YU_3                          ((uint32_t)0x00080000)        
+#define RTC_DR_WDU                           ((uint32_t)0x0000E000)        
+#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)        
+#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)        
+#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)        
+#define RTC_DR_MT                            ((uint32_t)0x00001000)        
+#define RTC_DR_MU                            ((uint32_t)0x00000F00)        
+#define RTC_DR_MU_0                          ((uint32_t)0x00000100)        
+#define RTC_DR_MU_1                          ((uint32_t)0x00000200)        
+#define RTC_DR_MU_2                          ((uint32_t)0x00000400)        
+#define RTC_DR_MU_3                          ((uint32_t)0x00000800)        
+#define RTC_DR_DT                            ((uint32_t)0x00000030)        
+#define RTC_DR_DT_0                          ((uint32_t)0x00000010)        
+#define RTC_DR_DT_1                          ((uint32_t)0x00000020)        
+#define RTC_DR_DU                            ((uint32_t)0x0000000F)        
+#define RTC_DR_DU_0                          ((uint32_t)0x00000001)        
+#define RTC_DR_DU_1                          ((uint32_t)0x00000002)        
+#define RTC_DR_DU_2                          ((uint32_t)0x00000004)        
+#define RTC_DR_DU_3                          ((uint32_t)0x00000008)        
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_COE                           ((uint32_t)0x00800000)        
+#define RTC_CR_OSEL                          ((uint32_t)0x00600000)        
+#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)        
+#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)        
+#define RTC_CR_POL                           ((uint32_t)0x00100000)        
+#define RTC_CR_COSEL                         ((uint32_t)0x00080000)        
+#define RTC_CR_BKP                           ((uint32_t)0x00040000)        
+#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)        
+#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)        
+#define RTC_CR_TSIE                          ((uint32_t)0x00008000)        
+#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
+#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)        
+#define RTC_CR_TSE                           ((uint32_t)0x00000800)        
+#define RTC_CR_WUTE                          ((uint32_t)0x00000400)        
+#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)        
+#define RTC_CR_FMT                           ((uint32_t)0x00000040)        
+#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)        
+#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)        
+#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)        
+#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)        
+#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)        
+#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)        
+#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)        
+
+/* Old bit definition maintained for legacy purpose */
+#define RTC_CR_BCK                           RTC_CR_BKP
+#define RTC_CR_CALSEL                        RTC_CR_COSEL
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)        
+#define RTC_ISR_TAMP3F                       ((uint32_t)0x00008000)        
+#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)        
+#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)        
+#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)        
+#define RTC_ISR_TSF                          ((uint32_t)0x00000800)        
+#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)        
+#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)        
+#define RTC_ISR_INIT                         ((uint32_t)0x00000080)        
+#define RTC_ISR_INITF                        ((uint32_t)0x00000040)        
+#define RTC_ISR_RSF                          ((uint32_t)0x00000020)        
+#define RTC_ISR_INITS                        ((uint32_t)0x00000010)        
+#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)        
+#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)        
+#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)        
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)        
+#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)        
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)        
+#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)        
+#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)        
+#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)        
+#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)        
+#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)        
+#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)        
+#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)        
+#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)        
+#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)        
+#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)        
+#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)        
+#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)        
+#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)        
+#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)        
+#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)        
+#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)        
+#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)        
+#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)        
+#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)        
+#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)        
+#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)        
+#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)        
+#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)        
+#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)        
+#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)        
+#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)        
+#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)        
+#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)        
+#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)        
+#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)        
+#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)        
+#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)        
+#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)        
+#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)        
+#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)        
+#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)        
+#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)        
+#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)        
+#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)        
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)        
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS                           ((uint32_t)0x0003FFFF)        
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)        
+#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)        
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM                          ((uint32_t)0x00400000)        
+#define RTC_TSTR_HT                          ((uint32_t)0x00300000)        
+#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)        
+#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)        
+#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)        
+#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)        
+#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)        
+#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)        
+#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)        
+#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)        
+#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)        
+#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)        
+#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)        
+#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)        
+#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)        
+#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)        
+#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)        
+#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)        
+#define RTC_TSTR_ST                          ((uint32_t)0x00000070)        
+#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)        
+#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)        
+#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)        
+#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)        
+#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)        
+#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)        
+#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)        
+#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)        
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)        
+#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)        
+#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)        
+#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)        
+#define RTC_TSDR_MT                          ((uint32_t)0x00001000)        
+#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)        
+#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)        
+#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)        
+#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)        
+#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)        
+#define RTC_TSDR_DT                          ((uint32_t)0x00000030)        
+#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)        
+#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)        
+#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)        
+#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)        
+#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)        
+#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)        
+#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)        
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS                         ((uint32_t)0x0003FFFF)
+
+/********************  Bits definition for RTC_CALR register  ******************/
+#define RTC_CALR_CALP                         ((uint32_t)0x00008000)        
+#define RTC_CALR_CALW8                        ((uint32_t)0x00004000)        
+#define RTC_CALR_CALW16                       ((uint32_t)0x00002000)        
+#define RTC_CALR_CALM                         ((uint32_t)0x000001FF)        
+#define RTC_CALR_CALM_0                       ((uint32_t)0x00000001)        
+#define RTC_CALR_CALM_1                       ((uint32_t)0x00000002)        
+#define RTC_CALR_CALM_2                       ((uint32_t)0x00000004)        
+#define RTC_CALR_CALM_3                       ((uint32_t)0x00000008)        
+#define RTC_CALR_CALM_4                       ((uint32_t)0x00000010)        
+#define RTC_CALR_CALM_5                       ((uint32_t)0x00000020)        
+#define RTC_CALR_CALM_6                       ((uint32_t)0x00000040)        
+#define RTC_CALR_CALM_7                       ((uint32_t)0x00000080)        
+#define RTC_CALR_CALM_8                       ((uint32_t)0x00000100)
+
+/* Old Bits definition for RTC_CAL register maintained for legacy purpose */
+#define RTC_CAL_CALP                         RTC_CALR_CALP  
+#define RTC_CAL_CALW8                        RTC_CALR_CALW8 
+#define RTC_CAL_CALW16                       RTC_CALR_CALW16
+#define RTC_CAL_CALM                         RTC_CALR_CALM  
+#define RTC_CAL_CALM_0                       RTC_CALR_CALM_0
+#define RTC_CAL_CALM_1                       RTC_CALR_CALM_1
+#define RTC_CAL_CALM_2                       RTC_CALR_CALM_2
+#define RTC_CAL_CALM_3                       RTC_CALR_CALM_3
+#define RTC_CAL_CALM_4                       RTC_CALR_CALM_4
+#define RTC_CAL_CALM_5                       RTC_CALR_CALM_5
+#define RTC_CAL_CALM_6                       RTC_CALR_CALM_6
+#define RTC_CAL_CALM_7                       RTC_CALR_CALM_7
+#define RTC_CAL_CALM_8                       RTC_CALR_CALM_8
+
+/********************  Bits definition for RTC_TAFCR register  ****************/
+#define RTC_TAFCR_PC15MODE                   ((uint32_t)0x00800000)
+#define RTC_TAFCR_PC15VALUE                  ((uint32_t)0x00400000)
+#define RTC_TAFCR_PC14MODE                   ((uint32_t)0x00200000)
+#define RTC_TAFCR_PC14VALUE                  ((uint32_t)0x00100000)
+#define RTC_TAFCR_PC13MODE                   ((uint32_t)0x00080000)
+#define RTC_TAFCR_PC13VALUE                  ((uint32_t)0x00040000)        
+#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)        
+#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)        
+#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)        
+#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)        
+#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)        
+#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)        
+#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)        
+#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)        
+#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)        
+#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)        
+#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)        
+#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)        
+#define RTC_TAFCR_TAMP3EDGE                  ((uint32_t)0x00000040)        
+#define RTC_TAFCR_TAMP3E                     ((uint32_t)0x00000020)        
+#define RTC_TAFCR_TAMP2EDGE                  ((uint32_t)0x00000010)        
+#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)        
+#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)        
+#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)        
+#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)        
+
+/* Old bit definition maintained for legacy purpose */
+#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_PC13VALUE
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)        
+#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)        
+#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)        
+#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)        
+#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)        
+#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)        
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)        
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)        
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)        
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)        
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)        
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface (SPI)                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */
+#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */
+#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */
+#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */
+#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */
+#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */
+#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */
+#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */
+#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */
+#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */
+#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */
+#define  SPI_CR1_CRCL                        ((uint16_t)0x0800)            /*!< CRC Length */
+#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */
+#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */
+#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define  SPI_CR2_RXDMAEN                     ((uint16_t)0x0001)            /*!< Rx Buffer DMA Enable */
+#define  SPI_CR2_TXDMAEN                     ((uint16_t)0x0002)            /*!< Tx Buffer DMA Enable */
+#define  SPI_CR2_SSOE                        ((uint16_t)0x0004)            /*!< SS Output Enable */
+#define  SPI_CR2_NSSP                        ((uint16_t)0x0008)            /*!< NSS pulse management Enable */
+#define  SPI_CR2_FRF                         ((uint16_t)0x0010)            /*!< Frame Format Enable */
+#define  SPI_CR2_ERRIE                       ((uint16_t)0x0020)            /*!< Error Interrupt Enable */
+#define  SPI_CR2_RXNEIE                      ((uint16_t)0x0040)            /*!< RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       ((uint16_t)0x0080)            /*!< Tx buffer Empty Interrupt Enable */
+#define  SPI_CR2_DS                          ((uint16_t)0x0F00)            /*!< DS[3:0] Data Size */
+#define  SPI_CR2_DS_0                        ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  SPI_CR2_DS_1                        ((uint16_t)0x0200)            /*!< Bit 1 */
+#define  SPI_CR2_DS_2                        ((uint16_t)0x0400)            /*!< Bit 2 */
+#define  SPI_CR2_DS_3                        ((uint16_t)0x0800)            /*!< Bit 3 */
+#define  SPI_CR2_FRXTH                       ((uint16_t)0x1000)            /*!< FIFO reception Threshold */
+#define  SPI_CR2_LDMARX                      ((uint16_t)0x2000)            /*!< Last DMA transfer for reception */
+#define  SPI_CR2_LDMATX                      ((uint16_t)0x4000)            /*!< Last DMA transfer for transmission */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define  SPI_SR_RXNE                         ((uint16_t)0x0001)            /*!< Receive buffer Not Empty */
+#define  SPI_SR_TXE                          ((uint16_t)0x0002)            /*!< Transmit buffer Empty */
+#define  SPI_SR_CHSIDE                       ((uint16_t)0x0004)            /*!< Channel side */
+#define  SPI_SR_UDR                          ((uint16_t)0x0008)            /*!< Underrun flag */
+#define  SPI_SR_CRCERR                       ((uint16_t)0x0010)            /*!< CRC Error flag */
+#define  SPI_SR_MODF                         ((uint16_t)0x0020)            /*!< Mode fault */
+#define  SPI_SR_OVR                          ((uint16_t)0x0040)            /*!< Overrun flag */
+#define  SPI_SR_BSY                          ((uint16_t)0x0080)            /*!< Busy flag */
+#define  SPI_SR_FRE                          ((uint16_t)0x0100)            /*!< TI frame format error */
+#define  SPI_SR_FRLVL                        ((uint16_t)0x0600)            /*!< FIFO Reception Level */
+#define  SPI_SR_FRLVL_0                      ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  SPI_SR_FRLVL_1                      ((uint16_t)0x0400)            /*!< Bit 1 */
+#define  SPI_SR_FTLVL                        ((uint16_t)0x1800)            /*!< FIFO Transmission Level */
+#define  SPI_SR_FTLVL_0                      ((uint16_t)0x0800)            /*!< Bit 0 */
+#define  SPI_SR_FTLVL_1                      ((uint16_t)0x1000)            /*!< Bit 1 */  
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!<Channel length (number of bits per audio channel) */
+#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!<steady state clock polarity */
+#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!<PCM frame synchronization */
+#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!<I2S Enable */
+#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!<I2S mode selection */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!<I2S Linear prescaler */
+#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!<Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       System Configuration (SYSCFG)                        */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
+#define SYSCFG_CFGR1_MEM_MODE               ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0             ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
+#define SYSCFG_CFGR1_MEM_MODE_1             ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
+#define SYSCFG_CFGR1_IRDA_ENV_SEL           ((uint32_t)0x000000C0) /*!< IRDA_SEL_ENV config */
+#define SYSCFG_CFGR1_IRDA_ENV_SEL_0         ((uint32_t)0x00000040) /*!< IRDA_SEL_ENV Bit 0 */
+#define SYSCFG_CFGR1_IRDA_ENV_SEL_1         ((uint32_t)0x00000080) /*!< IRDA_SEL_ENV Bit 1 */
+#define SYSCFG_CFGR1_PA11_PA12_RMP          ((uint32_t)0x00000010) /*!< PA11 and PA12 remap on QFN28 and TSSOP20 packages (only for STM32F042 devices)*/
+#define SYSCFG_CFGR1_ADC_DMA_RMP            ((uint32_t)0x00000100) /*!< ADC DMA remap */
+#define SYSCFG_CFGR1_USART1TX_DMA_RMP       ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
+#define SYSCFG_CFGR1_USART1RX_DMA_RMP       ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
+#define SYSCFG_CFGR1_TIM16_DMA_RMP          ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
+#define SYSCFG_CFGR1_TIM17_DMA_RMP          ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
+#define SYSCFG_CFGR1_TIM16_DMA_RMP2         ((uint32_t)0x00002000) /*!< Timer 16 DMA remap 2 (only for STM32F072) */
+#define SYSCFG_CFGR1_TIM17_DMA_RMP2         ((uint32_t)0x00004000) /*!< Timer 17 DMA remap 2 (only for STM32F072) */
+#define SYSCFG_CFGR1_I2C_FMP_PB6            ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB7            ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB8            ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB9            ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_I2C1           ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7(only for STM32F030, STM32F031 and STM32F072 devices) */
+#define SYSCFG_CFGR1_I2C_FMP_I2C2           ((uint32_t)0x00200000) /*!< Enable I2C2 Fast mode plus (only for STM32F072) */
+#define SYSCFG_CFGR1_I2C_FMP_PA9            ((uint32_t)0x00400000) /*!< Enable Fast Mode Plus on PA9 (only for STM32F030, STM32F031, STM32F042, STM32F072 and STM32F091 devices) */
+#define SYSCFG_CFGR1_I2C_FMP_PA10           ((uint32_t)0x00800000) /*!< Enable Fast Mode Plus on PA10(only for STM32F030, STM32F031, STM32F042, STM32F072 and STM32F091 devices) */
+#define SYSCFG_CFGR1_SPI2_DMA_RMP           ((uint32_t)0x01000000) /*!< SPI2 DMA remap (only for STM32F072) */
+#define SYSCFG_CFGR1_USART2_DMA_RMP         ((uint32_t)0x02000000) /*!< USART2 DMA remap (only for STM32F072) */
+#define SYSCFG_CFGR1_USART3_DMA_RMP         ((uint32_t)0x04000000) /*!< USART3 DMA remap (only for STM32F072) */
+#define SYSCFG_CFGR1_I2C1_DMA_RMP           ((uint32_t)0x08000000) /*!< I2C1 DMA remap (only for STM32F072) */
+#define SYSCFG_CFGR1_TIM1_DMA_RMP           ((uint32_t)0x10000000) /*!< TIM1 DMA remap (only for STM32F072) */
+#define SYSCFG_CFGR1_TIM2_DMA_RMP           ((uint32_t)0x20000000) /*!< TIM2 DMA remap (only for STM32F072) */
+#define SYSCFG_CFGR1_TIM3_DMA_RMP           ((uint32_t)0x40000000) /*!< TIM3 DMA remap (only for STM32F072) */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+
+/** 
+  * @brief  EXTI0 configuration  
+  */
+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         ((uint16_t)0x0003) /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         ((uint16_t)0x0004) /*!< PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0005) /*!< PF[0] pin */
+
+/** 
+  * @brief  EXTI1 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         ((uint16_t)0x0030) /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         ((uint16_t)0x0040) /*!< PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0050) /*!< PF[1] pin */
+
+/** 
+  * @brief  EXTI2 configuration  
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         ((uint16_t)0x0400) /*!< PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         ((uint16_t)0x0500) /*!< PF[2] pin */
+
+/** 
+  * @brief  EXTI3 configuration  
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         ((uint16_t)0x3000) /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         ((uint16_t)0x4000) /*!< PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         ((uint16_t)0x5000) /*!< PF[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
+#define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+
+/** 
+  * @brief  EXTI4 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         ((uint16_t)0x0003) /*!< PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         ((uint16_t)0x0004) /*!< PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint16_t)0x0005) /*!< PF[4] pin */
+
+/** 
+  * @brief  EXTI5 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         ((uint16_t)0x0030) /*!< PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         ((uint16_t)0x0040) /*!< PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint16_t)0x0050) /*!< PF[5] pin */
+
+/** 
+  * @brief  EXTI6 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         ((uint16_t)0x0300) /*!< PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         ((uint16_t)0x0400) /*!< PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint16_t)0x0500) /*!< PF[6] pin */
+
+/** 
+  * @brief  EXTI7 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         ((uint16_t)0x3000) /*!< PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         ((uint16_t)0x4000) /*!< PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint16_t)0x5000) /*!< PF[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
+#define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+
+/** 
+  * @brief  EXTI8 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         ((uint16_t)0x0003) /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         ((uint16_t)0x0004) /*!< PE[8] pin */
+
+/** 
+  * @brief  EXTI9 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         ((uint16_t)0x0030) /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         ((uint16_t)0x0040) /*!< PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         ((uint16_t)0x0050) /*!< PF[9] pin */
+
+/** 
+  * @brief  EXTI10 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        ((uint16_t)0x0300) /*!< PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        ((uint16_t)0x0400) /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        ((uint16_t)0x0500) /*!< PF[10] pin */
+
+/** 
+  * @brief  EXTI11 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint16_t)0x1000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        ((uint16_t)0x3000) /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        ((uint16_t)0x4000) /*!< PE[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
+#define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+
+/** 
+  * @brief  EXTI12 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint16_t)0x0001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        ((uint16_t)0x0003) /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        ((uint16_t)0x0004) /*!< PE[12] pin */
+
+/** 
+  * @brief  EXTI13 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint16_t)0x0010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        ((uint16_t)0x0030) /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        ((uint16_t)0x0040) /*!< PE[13] pin */
+
+/** 
+  * @brief  EXTI14 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        ((uint16_t)0x0300) /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        ((uint16_t)0x0400) /*!< PE[14] pin */
+
+/** 
+  * @brief  EXTI15 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        ((uint16_t)0x3000) /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        ((uint16_t)0x4000) /*!< PE[15] pin */
+
+/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK               ((uint32_t)0x00000001) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK          ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
+#define SYSCFG_CFGR2_PVD_LOCK                  ((uint32_t)0x00000004) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
+#define SYSCFG_CFGR2_SRAM_PEF                  ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
+
+/* Old Bit definition maintained for legacy purpose */
+#define SYSCFG_CFGR2_SRAM_PE                   SYSCFG_CFGR2_SRAM_PEF
+
+/*****************  Bit definition for SYSCFG_xxx ISR Wrapper register  ****************/
+#define SYSCFG_ITLINE0_SR_EWDG                ((uint32_t)0x00000001) /*!< EWDG interrupt */
+#define SYSCFG_ITLINE1_SR_PVDOUT              ((uint32_t)0x00000001) /*!< Power voltage detection -> exti[31] Interrupt */
+#define SYSCFG_ITLINE1_SR_VDDIO2              ((uint32_t)0x00000002) /*!< VDDIO2 -> exti[16] Interrupt */
+#define SYSCFG_ITLINE2_SR_RTC_WAKEUP          ((uint32_t)0x00000001) /*!< RTC WAKEUP -> exti[20] Interrupt */
+#define SYSCFG_ITLINE2_SR_RTC_TSTAMP          ((uint32_t)0x00000002) /*!< RTC Time Stamp -> exti[19] interrupt */
+#define SYSCFG_ITLINE2_SR_RTC_ALRA            ((uint32_t)0x00000003) /*!< RTC Alarm -> exti[17] interrupt .... */
+#define SYSCFG_ITLINE3_SR_FLASH_ITF           ((uint32_t)0x00000001) /*!< Flash ITF Interrupt */
+#define SYSCFG_ITLINE4_SR_CRS                 ((uint32_t)0x00000001) /*!< CRS interrupt */
+#define SYSCFG_ITLINE4_SR_CLK_CTRL            ((uint32_t)0x00000002) /*!< CLK CTRL interrupt */
+#define SYSCFG_ITLINE5_SR_EXTI0               ((uint32_t)0x00000001) /*!< External Interrupt 0 */
+#define SYSCFG_ITLINE5_SR_EXTI1               ((uint32_t)0x00000002) /*!< External Interrupt 1 */
+#define SYSCFG_ITLINE6_SR_EXTI2               ((uint32_t)0x00000001) /*!< External Interrupt 2 */
+#define SYSCFG_ITLINE6_SR_EXTI3               ((uint32_t)0x00000002) /*!< External Interrupt 3 */
+#define SYSCFG_ITLINE7_SR_EXTI4               ((uint32_t)0x00000001) /*!< External Interrupt 15 to 4 */
+#define SYSCFG_ITLINE7_SR_EXTI5               ((uint32_t)0x00000002) /*!< External Interrupt 15 to 4 */
+#define SYSCFG_ITLINE7_SR_EXTI6               ((uint32_t)0x00000004) /*!< External Interrupt 15 to 4 */
+#define SYSCFG_ITLINE7_SR_EXTI7               ((uint32_t)0x00000008) /*!< External Interrupt 15 to 4 */
+#define SYSCFG_ITLINE7_SR_EXTI8               ((uint32_t)0x00000010) /*!< External Interrupt 15 to 4 */
+#define SYSCFG_ITLINE7_SR_EXTI9               ((uint32_t)0x00000020) /*!< External Interrupt 15 to 4 */
+#define SYSCFG_ITLINE7_SR_EXTI10              ((uint32_t)0x00000040) /*!< External Interrupt 15 to 4 */
+#define SYSCFG_ITLINE7_SR_EXTI11              ((uint32_t)0x00000080) /*!< External Interrupt 15 to 4 */
+#define SYSCFG_ITLINE7_SR_EXTI12              ((uint32_t)0x00000100) /*!< External Interrupt 15 to 4 */
+#define SYSCFG_ITLINE7_SR_EXTI13              ((uint32_t)0x00000200) /*!< External Interrupt 15 to 4 */
+#define SYSCFG_ITLINE7_SR_EXTI14              ((uint32_t)0x00000400) /*!< External Interrupt 15 to 4 */
+#define SYSCFG_ITLINE7_SR_EXTI15              ((uint32_t)0x00000800) /*!< External Interrupt 15 to 4 */
+#define SYSCFG_ITLINE8_SR_TSC_EOA             ((uint32_t)0x00000001) /*!< Touch control EOA Interrupt */
+#define SYSCFG_ITLINE8_SR_TSC_MCE             ((uint32_t)0x00000002) /*!< Touch control MCE Interrupt */
+#define SYSCFG_ITLINE9_SR_DMA1_CH1            ((uint32_t)0x00000001) /*!< DMA1 Channel 1 Interrupt */
+#define SYSCFG_ITLINE10_SR_DMA1_CH2           ((uint32_t)0x00000001) /*!< DMA1 Channel 2 Interrupt */
+#define SYSCFG_ITLINE10_SR_DMA1_CH3           ((uint32_t)0x00000002) /*!< DMA2 Channel 3 Interrupt */
+#define SYSCFG_ITLINE10_SR_DMA2_CH1           ((uint32_t)0x00000004) /*!< DMA2 Channel 1 Interrupt */
+#define SYSCFG_ITLINE10_SR_DMA2_CH2           ((uint32_t)0x00000008) /*!< DMA2 Channel 2 Interrupt */
+#define SYSCFG_ITLINE11_SR_DMA1_CH4           ((uint32_t)0x00000001) /*!< DMA1 Channel 4 Interrupt */
+#define SYSCFG_ITLINE11_SR_DMA1_CH5           ((uint32_t)0x00000002) /*!< DMA1 Channel 5 Interrupt */
+#define SYSCFG_ITLINE11_SR_DMA1_CH6           ((uint32_t)0x00000004) /*!< DMA1 Channel 6 Interrupt */
+#define SYSCFG_ITLINE11_SR_DMA1_CH7           ((uint32_t)0x00000008) /*!< DMA1 Channel 7 Interrupt */
+#define SYSCFG_ITLINE11_SR_DMA2_CH3           ((uint32_t)0x00000010) /*!< DMA2 Channel 3 Interrupt */
+#define SYSCFG_ITLINE11_SR_DMA2_CH4           ((uint32_t)0x00000020) /*!< DMA2 Channel 4 Interrupt */
+#define SYSCFG_ITLINE11_SR_DMA2_CH5           ((uint32_t)0x00000040) /*!< DMA2 Channel 5 Interrupt */
+#define SYSCFG_ITLINE12_SR_ADC                ((uint32_t)0x00000001) /*!< ADC Interrupt */
+#define SYSCFG_ITLINE12_SR_COMP1              ((uint32_t)0x00000002) /*!< COMP1 Interrupt -> exti[21] */
+#define SYSCFG_ITLINE12_SR_COMP2              ((uint32_t)0x00000004) /*!< COMP2 Interrupt -> exti[22] */
+#define SYSCFG_ITLINE13_SR_TIM1_BRK           ((uint32_t)0x00000001) /*!< TIM1 BRK Interrupt */
+#define SYSCFG_ITLINE13_SR_TIM1_UPD           ((uint32_t)0x00000002) /*!< TIM1 UPD Interrupt */
+#define SYSCFG_ITLINE13_SR_TIM1_TRG           ((uint32_t)0x00000004) /*!< TIM1 TRG Interrupt */
+#define SYSCFG_ITLINE13_SR_TIM1_CCU           ((uint32_t)0x00000008) /*!< TIM1 CCU Interrupt */
+#define SYSCFG_ITLINE14_SR_TIM1_CC            ((uint32_t)0x00000001) /*!< TIM1 CC Interrupt */
+#define SYSCFG_ITLINE15_SR_TIM2_GLB           ((uint32_t)0x00000001) /*!< TIM2 GLB Interrupt */
+#define SYSCFG_ITLINE16_SR_TIM3_GLB           ((uint32_t)0x00000001) /*!< TIM3 GLB Interrupt */
+#define SYSCFG_ITLINE17_SR_DAC                ((uint32_t)0x00000001) /*!< DAC Interrupt */
+#define SYSCFG_ITLINE17_SR_TIM6_GLB           ((uint32_t)0x00000002) /*!< TIM6 GLB Interrupt */
+#define SYSCFG_ITLINE18_SR_TIM7_GLB           ((uint32_t)0x00000001) /*!< TIM7 GLB Interrupt */
+#define SYSCFG_ITLINE19_SR_TIM14_GLB          ((uint32_t)0x00000001) /*!< TIM14 GLB Interrupt */
+#define SYSCFG_ITLINE20_SR_TIM15_GLB          ((uint32_t)0x00000001) /*!< TIM15 GLB Interrupt */
+#define SYSCFG_ITLINE21_SR_TIM16_GLB          ((uint32_t)0x00000001) /*!< TIM16 GLB Interrupt */
+#define SYSCFG_ITLINE22_SR_TIM17_GLB          ((uint32_t)0x00000001) /*!< TIM17 GLB Interrupt */
+#define SYSCFG_ITLINE23_SR_I2C1_GLB           ((uint32_t)0x00000001) /*!< I2C1 GLB Interrupt -> exti[23] */
+#define SYSCFG_ITLINE24_SR_I2C2_GLB           ((uint32_t)0x00000001) /*!< I2C2 GLB Interrupt */
+#define SYSCFG_ITLINE25_SR_SPI1               ((uint32_t)0x00000001) /*!< SPI1 Interrupt */
+#define SYSCFG_ITLINE26_SR_SPI2               ((uint32_t)0x00000001) /*!< SPI2  Interrupt */
+#define SYSCFG_ITLINE27_SR_USART1_GLB         ((uint32_t)0x00000001) /*!< USART1 GLB Interrupt -> exti[25] */
+#define SYSCFG_ITLINE28_SR_USART2_GLB         ((uint32_t)0x00000001) /*!< USART2 GLB Interrupt -> exti[26] */
+#define SYSCFG_ITLINE29_SR_USART3_GLB         ((uint32_t)0x00000001) /*!< USART3 GLB Interrupt -> exti[28] */
+#define SYSCFG_ITLINE29_SR_USART4_GLB         ((uint32_t)0x00000002) /*!< USART4 GLB Interrupt */
+#define SYSCFG_ITLINE29_SR_USART5_GLB         ((uint32_t)0x00000004) /*!< USART5 GLB Interrupt */
+#define SYSCFG_ITLINE29_SR_USART6_GLB         ((uint32_t)0x00000008) /*!< USART6 GLB Interrupt */
+#define SYSCFG_ITLINE29_SR_USART7_GLB         ((uint32_t)0x00000010) /*!< USART7 GLB Interrupt */
+#define SYSCFG_ITLINE29_SR_USART8_GLB         ((uint32_t)0x00000020) /*!< USART8 GLB Interrupt */
+#define SYSCFG_ITLINE30_SR_CAN                ((uint32_t)0x00000001) /*!< CAN Interrupt */
+#define SYSCFG_ITLINE30_SR_CEC                ((uint32_t)0x00000002) /*!< CEC Interrupt */
+
+/******************************************************************************/
+/*                                                                            */
+/*                               Timers (TIM)                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable */
+#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable */
+#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
+#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode */
+#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction */
+
+#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */
+
+#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable */
+
+#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!<Capture/Compare Preloaded Control */
+#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection */
+
+#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!<Output Idle state 1 (OC1 output) */
+#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!<Output Idle state 2 (OC2 output) */
+#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!<Output Idle state 3 (OC3 output) */
+#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!<Output Idle state 4 (OC4 output) */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection) */
+#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+
+#define  TIM_SMCR_OCCS                       ((uint16_t)0x0008)            /*!< OCREF clear selection */
+
+#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection) */
+#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode */
+
+#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */
+
+#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable */
+#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable */
+#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable */
+#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable */
+#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable */
+#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!<COM interrupt enable */
+#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable */
+#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!<Break interrupt enable */
+#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable */
+#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable */
+#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag */
+#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag */
+#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag */
+#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag */
+#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag */
+#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!<COM interrupt Flag */
+#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag */
+#define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!<Break interrupt Flag */
+#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation */
+#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation */
+#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation */
+#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation */
+#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation */
+#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation */
+#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!<Break Generation */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable */
+#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable */
+
+#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable */
+
+#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable */
+#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable */
+
+#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable */
+#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable */
+
+#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */
+
+#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable */
+#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */
+
+#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable */
+#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity */
+#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable */
+#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable */
+#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity */
+#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable */
+#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable */
+#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity */
+#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable */
+#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable */
+#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity */
+#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!<Bit 7 */
+
+#define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!<Off-State Selection for Run mode */
+#define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!<Break enable */
+#define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!<Break Polarity */
+#define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!<Automatic Output enable */
+#define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!<Main Output enable */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */
+
+#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses */
+
+/*******************  Bit definition for TIM_OR register  *********************/
+#define TIM14_OR_TI1_RMP                       ((uint16_t)0x0003)            /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
+#define TIM14_OR_TI1_RMP_0                     ((uint16_t)0x0001)            /*!<Bit 0 */
+#define TIM14_OR_TI1_RMP_1                     ((uint16_t)0x0002)            /*!<Bit 1 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for USART_CR1 register  *******************/
+#define  USART_CR1_UE                        ((uint32_t)0x00000001)            /*!< USART Enable */
+#define  USART_CR1_UESM                      ((uint32_t)0x00000002)            /*!< USART Enable in STOP Mode */
+#define  USART_CR1_RE                        ((uint32_t)0x00000004)            /*!< Receiver Enable */
+#define  USART_CR1_TE                        ((uint32_t)0x00000008)            /*!< Transmitter Enable */
+#define  USART_CR1_IDLEIE                    ((uint32_t)0x00000010)            /*!< IDLE Interrupt Enable */
+#define  USART_CR1_RXNEIE                    ((uint32_t)0x00000020)            /*!< RXNE Interrupt Enable */
+#define  USART_CR1_TCIE                      ((uint32_t)0x00000040)            /*!< Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     ((uint32_t)0x00000080)            /*!< TXE Interrupt Enable */
+#define  USART_CR1_PEIE                      ((uint32_t)0x00000100)            /*!< PE Interrupt Enable */
+#define  USART_CR1_PS                        ((uint32_t)0x00000200)            /*!< Parity Selection */
+#define  USART_CR1_PCE                       ((uint32_t)0x00000400)            /*!< Parity Control Enable */
+#define  USART_CR1_WAKE                      ((uint32_t)0x00000800)            /*!< Receiver Wakeup method */
+#define  USART_CR1_M                         ((uint32_t)0x00001000)            /*!< Word length */
+#define  USART_CR1_MME                       ((uint32_t)0x00002000)            /*!< Mute Mode Enable */
+#define  USART_CR1_CMIE                      ((uint32_t)0x00004000)            /*!< Character match interrupt enable */
+#define  USART_CR1_OVER8                     ((uint32_t)0x00008000)            /*!< Oversampling by 8-bit or 16-bit mode */
+#define  USART_CR1_DEDT                      ((uint32_t)0x001F0000)            /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define  USART_CR1_DEDT_0                    ((uint32_t)0x00010000)            /*!< Bit 0 */
+#define  USART_CR1_DEDT_1                    ((uint32_t)0x00020000)            /*!< Bit 1 */
+#define  USART_CR1_DEDT_2                    ((uint32_t)0x00040000)            /*!< Bit 2 */
+#define  USART_CR1_DEDT_3                    ((uint32_t)0x00080000)            /*!< Bit 3 */
+#define  USART_CR1_DEDT_4                    ((uint32_t)0x00100000)            /*!< Bit 4 */
+#define  USART_CR1_DEAT                      ((uint32_t)0x03E00000)            /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define  USART_CR1_DEAT_0                    ((uint32_t)0x00200000)            /*!< Bit 0 */
+#define  USART_CR1_DEAT_1                    ((uint32_t)0x00400000)            /*!< Bit 1 */
+#define  USART_CR1_DEAT_2                    ((uint32_t)0x00800000)            /*!< Bit 2 */
+#define  USART_CR1_DEAT_3                    ((uint32_t)0x01000000)            /*!< Bit 3 */
+#define  USART_CR1_DEAT_4                    ((uint32_t)0x02000000)            /*!< Bit 4 */
+#define  USART_CR1_RTOIE                     ((uint32_t)0x04000000)            /*!< Receive Time Out interrupt enable */
+#define  USART_CR1_EOBIE                     ((uint32_t)0x08000000)            /*!< End of Block interrupt enable */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define  USART_CR2_ADDM7                     ((uint32_t)0x00000010)            /*!< 7-bit or 4-bit Address Detection */
+#define  USART_CR2_LBDL                      ((uint32_t)0x00000020)            /*!< LIN Break Detection Length */
+#define  USART_CR2_LBDIE                     ((uint32_t)0x00000040)            /*!< LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      ((uint32_t)0x00000100)            /*!< Last Bit Clock pulse */
+#define  USART_CR2_CPHA                      ((uint32_t)0x00000200)            /*!< Clock Phase */
+#define  USART_CR2_CPOL                      ((uint32_t)0x00000400)            /*!< Clock Polarity */
+#define  USART_CR2_CLKEN                     ((uint32_t)0x00000800)            /*!< Clock Enable */
+#define  USART_CR2_STOP                      ((uint32_t)0x00003000)            /*!< STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    ((uint32_t)0x00001000)            /*!< Bit 0 */
+#define  USART_CR2_STOP_1                    ((uint32_t)0x00002000)            /*!< Bit 1 */
+#define  USART_CR2_LINEN                     ((uint32_t)0x00004000)            /*!< LIN mode enable */
+#define  USART_CR2_SWAP                      ((uint32_t)0x00008000)            /*!< SWAP TX/RX pins */
+#define  USART_CR2_RXINV                     ((uint32_t)0x00010000)            /*!< RX pin active level inversion */
+#define  USART_CR2_TXINV                     ((uint32_t)0x00020000)            /*!< TX pin active level inversion */
+#define  USART_CR2_DATAINV                   ((uint32_t)0x00040000)            /*!< Binary data inversion */
+#define  USART_CR2_MSBFIRST                  ((uint32_t)0x00080000)            /*!< Most Significant Bit First */
+#define  USART_CR2_ABREN                     ((uint32_t)0x00100000)            /*!< Auto Baud-Rate Enable*/
+#define  USART_CR2_ABRMODE                   ((uint32_t)0x00600000)            /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define  USART_CR2_ABRMODE_0                 ((uint32_t)0x00200000)            /*!< Bit 0 */
+#define  USART_CR2_ABRMODE_1                 ((uint32_t)0x00400000)            /*!< Bit 1 */
+#define  USART_CR2_RTOEN                     ((uint32_t)0x00800000)            /*!< Receiver Time-Out enable */
+#define  USART_CR2_ADD                       ((uint32_t)0xFF000000)            /*!< Address of the USART node */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define  USART_CR3_EIE                       ((uint32_t)0x00000001)            /*!< Error Interrupt Enable */
+#define  USART_CR3_IREN                      ((uint32_t)0x00000002)            /*!< IrDA mode Enable */
+#define  USART_CR3_IRLP                      ((uint32_t)0x00000004)            /*!< IrDA Low-Power */
+#define  USART_CR3_HDSEL                     ((uint32_t)0x00000008)            /*!< Half-Duplex Selection */
+#define  USART_CR3_NACK                      ((uint32_t)0x00000010)            /*!< SmartCard NACK enable */
+#define  USART_CR3_SCEN                      ((uint32_t)0x00000020)            /*!< SmartCard mode enable */
+#define  USART_CR3_DMAR                      ((uint32_t)0x00000040)            /*!< DMA Enable Receiver */
+#define  USART_CR3_DMAT                      ((uint32_t)0x00000080)            /*!< DMA Enable Transmitter */
+#define  USART_CR3_RTSE                      ((uint32_t)0x00000100)            /*!< RTS Enable */
+#define  USART_CR3_CTSE                      ((uint32_t)0x00000200)            /*!< CTS Enable */
+#define  USART_CR3_CTSIE                     ((uint32_t)0x00000400)            /*!< CTS Interrupt Enable */
+#define  USART_CR3_ONEBIT                    ((uint32_t)0x00000800)            /*!< One sample bit method enable */
+#define  USART_CR3_OVRDIS                    ((uint32_t)0x00001000)            /*!< Overrun Disable */
+#define  USART_CR3_DDRE                      ((uint32_t)0x00002000)            /*!< DMA Disable on Reception Error */
+#define  USART_CR3_DEM                       ((uint32_t)0x00004000)            /*!< Driver Enable Mode */
+#define  USART_CR3_DEP                       ((uint32_t)0x00008000)            /*!< Driver Enable Polarity Selection */
+#define  USART_CR3_SCARCNT                   ((uint32_t)0x000E0000)            /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define  USART_CR3_SCARCNT_0                 ((uint32_t)0x00020000)            /*!< Bit 0 */
+#define  USART_CR3_SCARCNT_1                 ((uint32_t)0x00040000)            /*!< Bit 1 */
+#define  USART_CR3_SCARCNT_2                 ((uint32_t)0x00080000)            /*!< Bit 2 */
+#define  USART_CR3_WUS                       ((uint32_t)0x00300000)            /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define  USART_CR3_WUS_0                     ((uint32_t)0x00100000)            /*!< Bit 0 */
+#define  USART_CR3_WUS_1                     ((uint32_t)0x00200000)            /*!< Bit 1 */
+#define  USART_CR3_WUFIE                     ((uint32_t)0x00400000)            /*!< Wake Up Interrupt Enable */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define  USART_BRR_DIV_FRACTION              ((uint16_t)0x000F)                /*!< Fraction of USARTDIV */
+#define  USART_BRR_DIV_MANTISSA              ((uint16_t)0xFFF0)                /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)                /*!< PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_GT                       ((uint16_t)0xFF00)                /*!< GT[7:0] bits (Guard time value) */
+
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define  USART_RTOR_RTO                      ((uint32_t)0x00FFFFFF)            /*!< Receiver Time Out Value */
+#define  USART_RTOR_BLEN                     ((uint32_t)0xFF000000)            /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define  USART_RQR_ABRRQ                    ((uint16_t)0x0001)                /*!< Auto-Baud Rate Request */
+#define  USART_RQR_SBKRQ                    ((uint16_t)0x0002)                /*!< Send Break Request */
+#define  USART_RQR_MMRQ                     ((uint16_t)0x0004)                /*!< Mute Mode Request */
+#define  USART_RQR_RXFRQ                    ((uint16_t)0x0008)                /*!< Receive Data flush Request */
+#define  USART_RQR_TXFRQ                    ((uint16_t)0x0010)                /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define  USART_ISR_PE                        ((uint32_t)0x00000001)            /*!< Parity Error */
+#define  USART_ISR_FE                        ((uint32_t)0x00000002)            /*!< Framing Error */
+#define  USART_ISR_NE                        ((uint32_t)0x00000004)            /*!< Noise detected Flag */
+#define  USART_ISR_ORE                       ((uint32_t)0x00000008)            /*!< OverRun Error */
+#define  USART_ISR_IDLE                      ((uint32_t)0x00000010)            /*!< IDLE line detected */
+#define  USART_ISR_RXNE                      ((uint32_t)0x00000020)            /*!< Read Data Register Not Empty */
+#define  USART_ISR_TC                        ((uint32_t)0x00000040)            /*!< Transmission Complete */
+#define  USART_ISR_TXE                       ((uint32_t)0x00000080)            /*!< Transmit Data Register Empty */
+#define  USART_ISR_LBD                       ((uint32_t)0x00000100)            /*!< LIN Break Detection Flag */
+#define  USART_ISR_CTSIF                     ((uint32_t)0x00000200)            /*!< CTS interrupt flag */
+#define  USART_ISR_CTS                       ((uint32_t)0x00000400)            /*!< CTS flag */
+#define  USART_ISR_RTOF                      ((uint32_t)0x00000800)            /*!< Receiver Time Out */
+#define  USART_ISR_EOBF                      ((uint32_t)0x00001000)            /*!< End Of Block Flag */
+#define  USART_ISR_ABRE                      ((uint32_t)0x00004000)            /*!< Auto-Baud Rate Error */
+#define  USART_ISR_ABRF                      ((uint32_t)0x00008000)            /*!< Auto-Baud Rate Flag */
+#define  USART_ISR_BUSY                      ((uint32_t)0x00010000)            /*!< Busy Flag */
+#define  USART_ISR_CMF                       ((uint32_t)0x00020000)            /*!< Character Match Flag */
+#define  USART_ISR_SBKF                      ((uint32_t)0x00040000)            /*!< Send Break Flag */
+#define  USART_ISR_RWU                       ((uint32_t)0x00080000)            /*!< Receive Wake Up from mute mode Flag */
+#define  USART_ISR_WUF                       ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Flag */
+#define  USART_ISR_TEACK                     ((uint32_t)0x00200000)            /*!< Transmit Enable Acknowledge Flag */
+#define  USART_ISR_REACK                     ((uint32_t)0x00400000)            /*!< Receive Enable Acknowledge Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define  USART_ICR_PECF                      ((uint32_t)0x00000001)            /*!< Parity Error Clear Flag */
+#define  USART_ICR_FECF                      ((uint32_t)0x00000002)            /*!< Framing Error Clear Flag */
+#define  USART_ICR_NCF                      ((uint32_t)0x00000004)             /*!< Noise detected Clear Flag */
+#define  USART_ICR_ORECF                     ((uint32_t)0x00000008)            /*!< OverRun Error Clear Flag */
+#define  USART_ICR_IDLECF                    ((uint32_t)0x00000010)            /*!< IDLE line detected Clear Flag */
+#define  USART_ICR_TCCF                      ((uint32_t)0x00000040)            /*!< Transmission Complete Clear Flag */
+#define  USART_ICR_LBDCF                     ((uint32_t)0x00000100)            /*!< LIN Break Detection Clear Flag */
+#define  USART_ICR_CTSCF                     ((uint32_t)0x00000200)            /*!< CTS Interrupt Clear Flag */
+#define  USART_ICR_RTOCF                     ((uint32_t)0x00000800)            /*!< Receiver Time Out Clear Flag */
+#define  USART_ICR_EOBCF                     ((uint32_t)0x00001000)            /*!< End Of Block Clear Flag */
+#define  USART_ICR_CMCF                      ((uint32_t)0x00020000)            /*!< Character Match Clear Flag */
+#define  USART_ICR_WUCF                      ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define  USART_RDR_RDR                       ((uint16_t)0x01FF)                /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define  USART_TDR_TDR                       ((uint16_t)0x01FF)                /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Window WATCHDOG (WWDG)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!< Bit 0 */
+#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!< Bit 1 */
+#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!< Bit 2 */
+#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!< Bit 3 */
+#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!< Bit 4 */
+#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!< Bit 5 */
+#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!< Bit 6 */
+
+#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!< Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!< W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!< Bit 6 */
+
+#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!< WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!< Bit 0 */
+#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!< Bit 1 */
+
+#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!< Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!< Early Wakeup Interrupt Flag */
+
+#if defined (STM32F091)
+/******************************************************************************/
+/*  For a painless codes migration between the STM32F0xx device product       */
+/*  lines, the aliases defined below are put in place to overcome the         */
+/*  differences in the interrupt handlers and IRQn definitions.               */
+/*  No need to update developed interrupt code when moving across             */ 
+/*  product lines within the same STM32L0 Family                              */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define PVD_IRQn                          PVD_VDDIO2_IRQn
+#define RCC_IRQn                          RCC_CRS_IRQn
+#define TS_IRQn                           TSC_IRQn
+#define DMA1_Channel1_IRQn                DMA1_Ch1_IRQn
+#define DMA1_Channel2_3_IRQn              DMA1_Ch2_3_DMA2_Ch1_2_IRQn
+#define DMA1_Channel4_5_IRQn              DMA1_Ch4_7_DMA2_Ch3_5_IRQn
+#define DMA1_Channel4_5_6_7_IRQn          DMA1_Ch4_7_DMA2_Ch3_5_IRQn
+#define ADC1_IRQn                         ADC1_COMP_IRQn
+#define USART3_4_IRQn                     USART3_8_IRQn
+#define CEC_IRQn                          CEC_CAN_IRQn
+
+/* Aliases for __IRQHandler */
+#define PVD_IRQHandler                    PVD_VDDIO2_IRQHandler
+#define RCC_IRQHandler                    RCC_CRS_IRQHandler
+#define TS_IRQHandler                     TSC_IRQHandler 
+#define DMA1_Channel1_IRQHandler          DMA1_Ch1_IRQHandler
+#define DMA1_Channel2_3_IRQHandler        DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
+#define DMA1_Channel4_5_IRQHandler        DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
+#define DMA1_Channel4_5_6_7_IRQHandler    DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
+#define ADC1_IRQHandler                   ADC1_COMP_IRQHandler
+#define USART3_4_IRQHandler               USART3_8_IRQHandler
+#define CEC_IRQHandler                    CEC_CAN_IRQHandler 
+
+#elif defined (STM32F072)
+/* Aliases for __IRQn */
+#define PVD_IRQn                          PVD_VDDIO2_IRQn
+#define RCC_IRQn                          RCC_CRS_IRQn
+#define TS_IRQn                           TSC_IRQn
+#define DMA1_Ch1_IRQn                     DMA1_Channel1_IRQn
+#define DMA1_Ch2_3_DMA2_Ch1_2_IRQn        DMA1_Channel2_3_IRQn           
+#define DMA1_Channel4_5_IRQn              DMA1_Channel4_5_6_7_IRQn
+#define DMA1_Ch4_7_DMA2_Ch3_5_IRQn        DMA1_Channel4_5_6_7_IRQn          
+#define ADC1_IRQn                         ADC1_COMP_IRQn
+#define USART3_8_IRQn                     USART3_4_IRQn
+#define CEC_IRQn                          CEC_CAN_IRQn
+
+/* Aliases for __IRQHandler */
+#define PVD_IRQHandler                    PVD_VDDIO2_IRQHandler
+#define RCC_IRQHandler                    RCC_CRS_IRQHandler
+#define TS_IRQHandler                     TSC_IRQHandler 
+#define DMA1_Ch1_IRQHandler               DMA1_Channel1_IRQHandler
+#define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler  DMA1_Channel2_3_IRQHandler      
+#define DMA1_Channel4_5_IRQHandler        DMA1_Channel4_5_6_7_IRQHandler
+#define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler  DMA1_Channel4_5_6_7_IRQHandler
+#define ADC1_IRQHandler                   ADC1_COMP_IRQHandler
+#define USART3_8_IRQHandler               USART3_4_IRQHandler
+#define CEC_IRQHandler                    CEC_CAN_IRQHandler 
+
+#elif defined (STM32F051)
+/* Aliases for __IRQn */
+#define PVD_VDDIO2_IRQn                   PVD_IRQn                          
+#define RCC_CRS_IRQn                      RCC_IRQn
+#define TSC_IRQn                          TS_IRQn                           
+#define DMA1_Ch1_IRQn                     DMA1_Channel1_IRQn
+#define DMA1_Ch2_3_DMA2_Ch1_2_IRQn        DMA1_Channel2_3_IRQn 
+#define DMA1_Channel4_5_6_7_IRQn          DMA1_Channel4_5_IRQn 
+#define DMA1_Ch4_7_DMA2_Ch3_5_IRQn        DMA1_Channel4_5_IRQn             
+#define ADC1_IRQn                         ADC1_COMP_IRQn
+#define CEC_CAN_IRQn                      CEC_IRQn
+
+/* Aliases for __IRQHandler */
+#define PVD_VDDIO2_IRQHandler             PVD_IRQHandler                         
+#define RCC_CRS_IRQHandler                RCC_IRQHandler
+#define TSC_IRQHandler                    TS_IRQHandler                           
+#define DMA1_Ch1_IRQHandler               DMA1_Channel1_IRQHandler
+#define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler  DMA1_Channel2_3_IRQHandler 
+#define DMA1_Channel4_5_6_7_IRQHandler    DMA1_Channel4_5_IRQHandler 
+#define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler  DMA1_Channel4_5_IRQHandler             
+#define ADC1_IRQHandler                   ADC1_COMP_IRQHandler
+#define CEC_CAN_IRQHandler                CEC_IRQHandler
+
+#elif defined (STM32F042)
+/* Aliases for __IRQn */
+#define PVD_IRQn                          PVD_VDDIO2_IRQn
+#define RCC_IRQn                          RCC_CRS_IRQn
+#define TS_IRQn                           TSC_IRQn
+#define DMA1_Ch1_IRQn                     DMA1_Channel1_IRQn
+#define DMA1_Ch2_3_DMA2_Ch1_2_IRQn        DMA1_Channel2_3_IRQn           
+#define DMA1_Channel4_5_IRQn              DMA1_Channel4_5_6_7_IRQn
+#define DMA1_Ch4_7_DMA2_Ch3_5_IRQn        DMA1_Channel4_5_6_7_IRQn          
+#define ADC1_COMP_IRQn                    ADC1_IRQn                         
+#define CEC_IRQn                          CEC_CAN_IRQn
+
+/* Aliases for __IRQHandler */
+#define PVD_IRQHandler                    PVD_VDDIO2_IRQHandler
+#define RCC_IRQHandler                    RCC_CRS_IRQHandler
+#define TS_IRQHandler                     TSC_IRQHandler 
+#define DMA1_Ch1_IRQHandler               DMA1_Channel1_IRQHandler
+#define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler  DMA1_Channel2_3_IRQHandler      
+#define DMA1_Channel4_5_IRQHandler        DMA1_Channel4_5_6_7_IRQHandler
+#define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler  DMA1_Channel4_5_6_7_IRQHandler
+#define ADC1_COMP_IRQHandler              ADC1_IRQHandler                   
+#define CEC_IRQHandler                    CEC_CAN_IRQHandler 
+
+#elif defined (STM32F031)
+/* Aliases for __IRQn */
+#define PVD_VDDIO2_IRQn                   PVD_IRQn                          
+#define RCC_CRS_IRQn                      RCC_IRQn                         
+#define DMA1_Ch1_IRQn                     DMA1_Channel1_IRQn
+#define DMA1_Ch2_3_DMA2_Ch1_2_IRQn        DMA1_Channel2_3_IRQn 
+#define DMA1_Channel4_5_6_7_IRQn          DMA1_Channel4_5_IRQn 
+#define DMA1_Ch4_7_DMA2_Ch3_5_IRQn        DMA1_Channel4_5_IRQn             
+#define ADC1_COMP_IRQn                    ADC1_IRQn                         
+
+/* Aliases for __IRQHandler */
+#define PVD_VDDIO2_IRQHandler             PVD_IRQHandler                         
+#define RCC_CRS_IRQHandler                RCC_IRQHandler                          
+#define DMA1_Ch1_IRQHandler               DMA1_Channel1_IRQHandler
+#define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler  DMA1_Channel2_3_IRQHandler 
+#define DMA1_Channel4_5_6_7_IRQHandler    DMA1_Channel4_5_IRQHandler 
+#define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler  DMA1_Channel4_5_IRQHandler             
+#define ADC1_COMP_IRQHandler              ADC1_IRQHandler                   
+  
+#elif defined (STM32F030)
+/* Aliases for __IRQn */
+#define RCC_CRS_IRQn                      RCC_IRQn
+#define DMA1_Ch1_IRQn                     DMA1_Channel1_IRQn
+#define DMA1_Ch2_3_DMA2_Ch1_2_IRQn        DMA1_Channel2_3_IRQn
+#define DMA1_Channel4_5_6_7_IRQn          DMA1_Channel4_5_IRQn 
+#define DMA1_Ch4_7_DMA2_Ch3_5_IRQn        DMA1_Channel4_5_IRQn
+#define ADC1_COMP_IRQn                    ADC1_IRQn
+
+/* Aliases for __IRQHandler */
+#define RCC_CRS_IRQHandler                RCC_IRQHandler
+#define DMA1_Ch1_IRQHandler               DMA1_Channel1_IRQHandler
+#define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler  DMA1_Channel2_3_IRQHandler
+#define DMA1_Channel4_5_6_7_IRQHandler    DMA1_Channel4_5_IRQHandler 
+#define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler  DMA1_Channel4_5_IRQHandler
+#define ADC1_COMP_IRQHandler              ADC1_IRQHandler
+
+#elif defined (STM32F070xB)
+/* Aliases for __IRQn */              
+#define RCC_CRS_IRQn                       RCC_IRQn
+#define DMA1_Ch1_IRQn                      DMA1_Channel1_IRQn
+#define DMA1_Ch2_3_DMA2_Ch1_2_IRQn         DMA1_Channel2_3_IRQn
+#define DMA1_Ch4_7_DMA2_Ch3_5_IRQn         DMA1_Channel4_5_IRQn
+#define DMA1_Channel4_5_6_7_IRQn           DMA1_Channel4_5_IRQn
+#define ADC1_COMP_IRQn                     ADC1_IRQn
+#define TIM6_DAC_IRQn                      TIM6_IRQn
+#define USART3_8_IRQn                      USART3_4_IRQn
+#define USART3_6_IRQn                      USART3_4_IRQn
+
+/* Aliases for __IRQHandler */       
+#define RCC_CRS_IRQHandler                 RCC_IRQHandler
+#define DMA1_Ch1_IRQHandler                DMA1_Channel1_IRQHandler
+#define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler   DMA1_Channel2_3_IRQHandler
+#define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler   DMA1_Channel4_5_IRQHandler
+#define DMA1_Channel4_5_6_7_IRQHandler     DMA1_Channel4_5_IRQHandler
+#define ADC1_COMP_IRQHandler               ADC1_IRQHandler
+#define TIM6_DAC_IRQHandler                TIM6_IRQHandler
+#define USART3_8_IRQHandler                USART3_4_IRQHandler
+#define USART3_6_IRQHandler                USART3_4_IRQHandler
+
+#elif defined (STM32F070x6)
+/* Aliases for __IRQn */
+#define RCC_CRS_IRQn                       RCC_IRQn
+#define DMA1_Ch1_IRQn                      DMA1_Channel1_IRQn
+#define DMA1_Ch2_3_DMA2_Ch1_2_IRQn         DMA1_Channel2_3_IRQn
+#define DMA1_Ch4_7_DMA2_Ch3_5_IRQn         DMA1_Channel4_5_IRQn
+#define DMA1_Channel4_5_6_7_IRQn           DMA1_Channel4_5_IRQn
+#define ADC1_COMP_IRQn                     ADC1_IRQn
+
+/* Aliases for __IRQHandler */
+#define RCC_CRS_IRQHandler                 RCC_IRQHandler
+#define DMA1_Ch1_IRQHandler                DMA1_Channel1_IRQHandler
+#define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler   DMA1_Channel2_3_IRQHandler
+#define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler   DMA1_Channel4_5_IRQHandler
+#define DMA1_Channel4_5_6_7_IRQHandler     DMA1_Channel4_5_IRQHandler
+#define ADC1_COMP_IRQHandler               ADC1_IRQHandler
+
+#elif defined (STM32F030xC)
+/* Aliases for __IRQn */
+#define RCC_CRS_IRQn                       RCC_IRQn
+#define DMA1_Ch1_IRQn                      DMA1_Channel1_IRQn
+#define DMA1_Ch2_3_DMA2_Ch1_2_IRQn         DMA1_Channel2_3_IRQn
+#define DMA1_Ch4_7_DMA2_Ch3_5_IRQn         DMA1_Channel4_5_IRQn
+#define DMA1_Channel4_5_6_7_IRQn           DMA1_Channel4_5_IRQn
+#define ADC1_COMP_IRQn                     ADC1_IRQn
+#define TIM6_DAC_IRQn                      TIM6_IRQn
+#define USART3_8_IRQn                      USART3_6_IRQn
+#define USART3_4_IRQn                      USART3_6_IRQn
+
+/* Aliases for __IRQHandler */       
+#define RCC_CRS_IRQHandler                 RCC_IRQHandler
+#define DMA1_Ch1_IRQHandler                DMA1_Channel1_IRQHandler
+#define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler   DMA1_Channel2_3_IRQHandler
+#define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler   DMA1_Channel4_5_IRQHandler
+#define DMA1_Channel4_5_6_7_IRQHandler     DMA1_Channel4_5_IRQHandler
+#define ADC1_COMP_IRQHandler               ADC1_IRQHandler
+#define TIM6_DAC_IRQHandler                TIM6_IRQHandler
+#define USART3_8_IRQHandler                USART3_6_IRQHandler
+#define USART3_4_IRQHandler                USART3_6_IRQHandler
+
+#endif /* STM32F091 */
+/**
+  * @}
+  */
+
+ /**
+  * @}
+  */ 
+
+#ifdef USE_STDPERIPH_DRIVER
+  #include "stm32f0xx_conf.h"
+#endif
+
+/** @addtogroup Exported_macro
+  * @{
+  */
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0XX_H */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/include/cmsis/system_stm32f0xx.h b/system/include/cmsis/system_stm32f0xx.h

new file mode 100644 (file)

index 0000000..12027a8
--- /dev/null
+++ b/system/include/cmsis/system_stm32f0xx.h
@@ -0,0 +1,104 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f0xx.h
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer System Header File.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f0xx_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32F0XX_H
+#define __SYSTEM_STM32F0XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup STM32F0xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32F0xx_System_Exported_types
+  * @{
+  */
+
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F0XX_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/include/cortexm/ExceptionHandlers.h b/system/include/cortexm/ExceptionHandlers.h

new file mode 100644 (file)

index 0000000..4ab9dfe
--- /dev/null
+++ b/system/include/cortexm/ExceptionHandlers.h
@@ -0,0 +1,116 @@
+/*
+ * This file is part of the ??OS++ distribution.
+ *   (https://github.com/micro-os-plus)
+ * Copyright (c) 2014 Liviu Ionescu.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef CORTEXM_EXCEPTION_HANDLERS_H_
+#define CORTEXM_EXCEPTION_HANDLERS_H_
+
+#include <stdint.h>
+
+#if defined(DEBUG)
+#define __DEBUG_BKPT()  asm volatile ("bkpt 0")
+#endif
+
+// ----------------------------------------------------------------------------
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+// External references to cortexm_handlers.c
+
+  extern void
+  Reset_Handler (void);
+  extern void
+  NMI_Handler (void);
+  extern void
+  HardFault_Handler (void);
+
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+  extern void
+  MemManage_Handler (void);
+  extern void
+  BusFault_Handler (void);
+  extern void
+  UsageFault_Handler (void);
+  extern void
+  DebugMon_Handler (void);
+#endif
+
+  extern void
+  SVC_Handler (void);
+
+  extern void
+  PendSV_Handler (void);
+  extern void
+  SysTick_Handler (void);
+
+  // Exception Stack Frame of the Cortex-M3 or Cortex-M4 processor.
+  typedef struct
+  {
+    uint32_t r0;
+    uint32_t r1;
+    uint32_t r2;
+    uint32_t r3;
+    uint32_t r12;
+    uint32_t lr;
+    uint32_t pc;
+    uint32_t psr;
+#if  defined(__ARM_ARCH_7EM__)
+    uint32_t s[16];
+#endif
+  } ExceptionStackFrame;
+
+#if defined(TRACE)
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+  void
+  dumpExceptionStack (ExceptionStackFrame* frame, uint32_t cfsr, uint32_t mmfar,
+                      uint32_t bfar, uint32_t lr);
+#endif // defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+#if defined(__ARM_ARCH_6M__)
+  void
+  dumpExceptionStack (ExceptionStackFrame* frame, uint32_t lr);
+#endif // defined(__ARM_ARCH_6M__)
+#endif // defined(TRACE)
+
+  void
+  HardFault_Handler_C (ExceptionStackFrame* frame, uint32_t lr);
+
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+  void
+  UsageFault_Handler_C (ExceptionStackFrame* frame, uint32_t lr);
+  void
+  BusFault_Handler_C (ExceptionStackFrame* frame, uint32_t lr);
+#endif // defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+
+#if defined(__cplusplus)
+}
+#endif
+
+// ----------------------------------------------------------------------------
+
+#endif // CORTEXM_EXCEPTION_HANDLERS_H_
diff --git a/system/include/diag/Trace.h b/system/include/diag/Trace.h

new file mode 100644 (file)

index 0000000..b90005e
--- /dev/null
+++ b/system/include/diag/Trace.h
@@ -0,0 +1,168 @@
+/*
+ * This file is part of the ??OS++ distribution.
+ *   (https://github.com/micro-os-plus)
+ * Copyright (c) 2014 Liviu Ionescu.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef DIAG_TRACE_H_
+#define DIAG_TRACE_H_
+
+// ----------------------------------------------------------------------------
+
+#include <unistd.h>
+
+// ----------------------------------------------------------------------------
+
+// The trace device is an independent output channel, intended for debug
+// purposes.
+//
+// The API is simple, and mimics the standard output calls:
+// - trace_printf()
+// - trace_puts()
+// - trace_putchar();
+//
+// The implementation is done in
+// - trace_write()
+//
+// Trace support is enabled by adding the TRACE definition.
+// By default the trace messages are forwarded to the ITM output,
+// but can be rerouted via any device or completely suppressed by
+// changing the definitions required in system/src/diag/trace_impl.c
+// (currently OS_USE_TRACE_ITM, OS_USE_TRACE_SEMIHOSTING_DEBUG/_STDOUT).
+//
+// When TRACE is not defined, all functions are inlined to empty bodies.
+// This has the advantage that the trace call do not need to be conditionally
+// compiled with #ifdef TRACE/#endif
+
+
+#if defined(TRACE)
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+  void
+  trace_initialize(void);
+
+  // Implementation dependent
+  ssize_t
+  trace_write(const char* buf, size_t nbyte);
+
+  // ----- Portable -----
+
+  int
+  trace_printf(const char* format, ...);
+
+  int
+  trace_puts(const char *s);
+
+  int
+  trace_putchar(int c);
+
+  void
+  trace_dump_args(int argc, char* argv[]);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#else // !defined(TRACE)
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+  inline void
+  trace_initialize(void);
+
+  // Implementation dependent
+  inline ssize_t
+  trace_write(const char* buf, size_t nbyte);
+
+  inline int
+  trace_printf(const char* format, ...);
+
+  inline int
+  trace_puts(const char *s);
+
+  inline int
+  trace_putchar(int c);
+
+  inline void
+  trace_dump_args(int argc, char* argv[]);
+
+#if defined(__cplusplus)
+}
+#endif
+
+inline void
+__attribute__((always_inline))
+trace_initialize(void)
+{
+}
+
+// Empty definitions when trace is not defined
+inline ssize_t
+__attribute__((always_inline))
+trace_write(const char* buf __attribute__((unused)),
+    size_t nbyte __attribute__((unused)))
+{
+  return 0;
+}
+
+inline int
+__attribute__((always_inline))
+trace_printf(const char* format __attribute__((unused)), ...)
+  {
+    return 0;
+  }
+
+inline int
+__attribute__((always_inline))
+trace_puts(const char *s __attribute__((unused)))
+{
+  return 0;
+}
+
+inline int
+__attribute__((always_inline))
+trace_putchar(int c)
+{
+  return c;
+}
+
+inline void
+__attribute__((always_inline))
+trace_dump_args(int argc __attribute__((unused)),
+    char* argv[] __attribute__((unused)))
+{
+}
+
+#endif // defined(TRACE)
+
+// ----------------------------------------------------------------------------
+
+#endif // DIAG_TRACE_H_
diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_adc.h b/system/include/stm32f0-stdperiph/stm32f0xx_adc.h

new file mode 100644 (file)

index 0000000..f364d9c
--- /dev/null
+++ b/system/include/stm32f0-stdperiph/stm32f0xx_adc.h
@@ -0,0 +1,450 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_adc.h
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file contains all the functions prototypes for the ADC firmware 
+  *          library
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_ADC_H
+#define __STM32F0XX_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup ADC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  ADC Init structure definition
+  */
+  
+typedef struct
+{
+  uint32_t ADC_Resolution;                  /*!< Selects the resolution of the conversion.
+                                                 This parameter can be a value of @ref ADC_Resolution */
+
+  FunctionalState ADC_ContinuousConvMode;   /*!< Specifies whether the conversion is performed in
+                                                 Continuous or Single mode.
+                                                 This parameter can be set to ENABLE or DISABLE. */
+
+  uint32_t ADC_ExternalTrigConvEdge;        /*!< Selects the external trigger Edge and enables the
+                                                 trigger of a regular group. This parameter can be a value
+                                                 of @ref ADC_external_trigger_edge_conversion */
+
+  uint32_t ADC_ExternalTrigConv;            /*!< Defines the external trigger used to start the analog
+                                                 to digital conversion of regular channels. This parameter
+                                                 can be a value of @ref ADC_external_trigger_sources_for_channels_conversion */
+
+  uint32_t ADC_DataAlign;                   /*!< Specifies whether the ADC data alignment is left or right.
+                                                 This parameter can be a value of @ref ADC_data_align */
+
+  uint32_t  ADC_ScanDirection;              /*!< Specifies in which direction the channels will be scanned
+                                                 in the sequence. 
+                                                 This parameter can be a value of @ref ADC_Scan_Direction */
+}ADC_InitTypeDef;
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants
+  * @{
+  */ 
+#define IS_ADC_ALL_PERIPH(PERIPH)                  ((PERIPH) == ADC1)
+
+/** @defgroup ADC_JitterOff
+  * @{
+  */ 
+/* These defines are obsolete and maintained for legacy purpose only. They are replaced  by the ADC_ClockMode */  
+#define ADC_JitterOff_PCLKDiv2                    ADC_CFGR2_JITOFFDIV2
+#define ADC_JitterOff_PCLKDiv4                    ADC_CFGR2_JITOFFDIV4
+
+#define IS_ADC_JITTEROFF(JITTEROFF) (((JITTEROFF) & 0x3FFFFFFF) == (uint32_t)RESET)
+
+/**
+  * @}
+  */
+  
+/** @defgroup ADC_ClockMode
+  * @{
+  */ 
+#define ADC_ClockMode_AsynClk                  ((uint32_t)0x00000000)   /*!< ADC Asynchronous clock mode */
+#define ADC_ClockMode_SynClkDiv2               ADC_CFGR2_CKMODE_0   /*!<  Synchronous clock mode divided by 2 */
+#define ADC_ClockMode_SynClkDiv4               ADC_CFGR2_CKMODE_1   /*!<  Synchronous clock mode divided by 4 */
+#define IS_ADC_CLOCKMODE(CLOCK) (((CLOCK) == ADC_ClockMode_AsynClk) ||\
+                                                       ((CLOCK) == ADC_ClockMode_SynClkDiv2) ||\
+                                                       ((CLOCK) == ADC_ClockMode_SynClkDiv4))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_Resolution
+  * @{
+  */ 
+#define ADC_Resolution_12b                         ((uint32_t)0x00000000)
+#define ADC_Resolution_10b                         ADC_CFGR1_RES_0
+#define ADC_Resolution_8b                          ADC_CFGR1_RES_1
+#define ADC_Resolution_6b                          ADC_CFGR1_RES
+
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
+                                       ((RESOLUTION) == ADC_Resolution_10b) || \
+                                       ((RESOLUTION) == ADC_Resolution_8b) || \
+                                       ((RESOLUTION) == ADC_Resolution_6b))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_external_trigger_edge_conversion 
+  * @{
+  */ 
+#define ADC_ExternalTrigConvEdge_None              ((uint32_t)0x00000000)
+#define ADC_ExternalTrigConvEdge_Rising            ADC_CFGR1_EXTEN_0
+#define ADC_ExternalTrigConvEdge_Falling           ADC_CFGR1_EXTEN_1
+#define ADC_ExternalTrigConvEdge_RisingFalling     ADC_CFGR1_EXTEN
+
+#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
+                                    ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
+                                    ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
+                                    ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_external_trigger_sources_for_channels_conversion
+  * @{
+  */ 
+
+/* TIM1 */
+#define ADC_ExternalTrigConv_T1_TRGO               ((uint32_t)0x00000000)
+#define ADC_ExternalTrigConv_T1_CC4                ADC_CFGR1_EXTSEL_0
+
+/* TIM2 */
+#define ADC_ExternalTrigConv_T2_TRGO               ADC_CFGR1_EXTSEL_1
+
+/* TIM3 */
+#define ADC_ExternalTrigConv_T3_TRGO               ((uint32_t)(ADC_CFGR1_EXTSEL_0 | ADC_CFGR1_EXTSEL_1))
+
+/* TIM15 */
+#define ADC_ExternalTrigConv_T15_TRGO              ADC_CFGR1_EXTSEL_2
+
+#define IS_ADC_EXTERNAL_TRIG_CONV(CONV) (((CONV) == ADC_ExternalTrigConv_T1_TRGO) || \
+                                         ((CONV) == ADC_ExternalTrigConv_T1_CC4)   || \
+                                         ((CONV) == ADC_ExternalTrigConv_T2_TRGO)  || \
+                                         ((CONV) == ADC_ExternalTrigConv_T3_TRGO)  || \
+                                         ((CONV) == ADC_ExternalTrigConv_T15_TRGO)) 
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_data_align 
+  * @{
+  */ 
+  
+#define ADC_DataAlign_Right                        ((uint32_t)0x00000000)
+#define ADC_DataAlign_Left                         ADC_CFGR1_ALIGN
+
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
+                                  ((ALIGN) == ADC_DataAlign_Left))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Scan_Direction 
+  * @{
+  */ 
+  
+#define ADC_ScanDirection_Upward                   ((uint32_t)0x00000000)
+#define ADC_ScanDirection_Backward                 ADC_CFGR1_SCANDIR
+
+#define IS_ADC_SCAN_DIRECTION(DIRECTION) (((DIRECTION) == ADC_ScanDirection_Upward) || \
+                                          ((DIRECTION) == ADC_ScanDirection_Backward))
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_DMA_Mode 
+  * @{
+  */ 
+  
+#define ADC_DMAMode_OneShot                        ((uint32_t)0x00000000)
+#define ADC_DMAMode_Circular                       ADC_CFGR1_DMACFG
+
+#define IS_ADC_DMA_MODE(MODE) (((MODE) == ADC_DMAMode_OneShot) || \
+                               ((MODE) == ADC_DMAMode_Circular))
+/**
+  * @}
+  */ 
+    
+/** @defgroup ADC_analog_watchdog_selection 
+  * @{
+  */ 
+  
+#define ADC_AnalogWatchdog_Channel_0                 ((uint32_t)0x00000000)
+#define ADC_AnalogWatchdog_Channel_1                 ((uint32_t)0x04000000)
+#define ADC_AnalogWatchdog_Channel_2                 ((uint32_t)0x08000000)
+#define ADC_AnalogWatchdog_Channel_3                 ((uint32_t)0x0C000000)
+#define ADC_AnalogWatchdog_Channel_4                 ((uint32_t)0x10000000)
+#define ADC_AnalogWatchdog_Channel_5                 ((uint32_t)0x14000000)
+#define ADC_AnalogWatchdog_Channel_6                 ((uint32_t)0x18000000)
+#define ADC_AnalogWatchdog_Channel_7                 ((uint32_t)0x1C000000)
+#define ADC_AnalogWatchdog_Channel_8                 ((uint32_t)0x20000000)
+#define ADC_AnalogWatchdog_Channel_9                 ((uint32_t)0x24000000)
+#define ADC_AnalogWatchdog_Channel_10                ((uint32_t)0x28000000) /*!< Not available for STM32F031 devices */
+#define ADC_AnalogWatchdog_Channel_11                ((uint32_t)0x2C000000) /*!< Not available for STM32F031 devices */
+#define ADC_AnalogWatchdog_Channel_12                ((uint32_t)0x30000000) /*!< Not available for STM32F031 devices */
+#define ADC_AnalogWatchdog_Channel_13                ((uint32_t)0x34000000) /*!< Not available for STM32F031 devices */
+#define ADC_AnalogWatchdog_Channel_14                ((uint32_t)0x38000000) /*!< Not available for STM32F031 devices */
+#define ADC_AnalogWatchdog_Channel_15                ((uint32_t)0x3C000000) /*!< Not available for STM32F031 devices */
+#define ADC_AnalogWatchdog_Channel_16                ((uint32_t)0x40000000)
+#define ADC_AnalogWatchdog_Channel_17                ((uint32_t)0x44000000)
+#define ADC_AnalogWatchdog_Channel_18                ((uint32_t)0x48000000)
+
+
+#define IS_ADC_ANALOG_WATCHDOG_CHANNEL(CHANNEL) (((CHANNEL) == ADC_AnalogWatchdog_Channel_0)  || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_1)  || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_2)  || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_3)  || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_4)  || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_5)  || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_6)  || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_7)  || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_8)  || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_9)  || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_10) || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_11) || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_12) || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_13) || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_14) || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_15) || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_16) || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_17) || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_18))
+/**
+  * @}
+  */ 
+  
+/** @defgroup ADC_sampling_times 
+  * @{
+  */ 
+
+#define ADC_SampleTime_1_5Cycles                     ((uint32_t)0x00000000)
+#define ADC_SampleTime_7_5Cycles                     ((uint32_t)0x00000001)
+#define ADC_SampleTime_13_5Cycles                    ((uint32_t)0x00000002)
+#define ADC_SampleTime_28_5Cycles                    ((uint32_t)0x00000003)
+#define ADC_SampleTime_41_5Cycles                    ((uint32_t)0x00000004)
+#define ADC_SampleTime_55_5Cycles                    ((uint32_t)0x00000005)
+#define ADC_SampleTime_71_5Cycles                    ((uint32_t)0x00000006)
+#define ADC_SampleTime_239_5Cycles                   ((uint32_t)0x00000007)
+
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1_5Cycles)   || \
+                                  ((TIME) == ADC_SampleTime_7_5Cycles)   || \
+                                  ((TIME) == ADC_SampleTime_13_5Cycles)  || \
+                                  ((TIME) == ADC_SampleTime_28_5Cycles)  || \
+                                  ((TIME) == ADC_SampleTime_41_5Cycles)  || \
+                                  ((TIME) == ADC_SampleTime_55_5Cycles)  || \
+                                  ((TIME) == ADC_SampleTime_71_5Cycles)  || \
+                                  ((TIME) == ADC_SampleTime_239_5Cycles))
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_thresholds 
+  * @{
+  */ 
+  
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_channels 
+  * @{
+  */ 
+  
+#define ADC_Channel_0                              ADC_CHSELR_CHSEL0
+#define ADC_Channel_1                              ADC_CHSELR_CHSEL1
+#define ADC_Channel_2                              ADC_CHSELR_CHSEL2
+#define ADC_Channel_3                              ADC_CHSELR_CHSEL3
+#define ADC_Channel_4                              ADC_CHSELR_CHSEL4
+#define ADC_Channel_5                              ADC_CHSELR_CHSEL5
+#define ADC_Channel_6                              ADC_CHSELR_CHSEL6
+#define ADC_Channel_7                              ADC_CHSELR_CHSEL7
+#define ADC_Channel_8                              ADC_CHSELR_CHSEL8
+#define ADC_Channel_9                              ADC_CHSELR_CHSEL9
+#define ADC_Channel_10                             ADC_CHSELR_CHSEL10 /*!< Not available for STM32F031 devices */
+#define ADC_Channel_11                             ADC_CHSELR_CHSEL11 /*!< Not available for STM32F031 devices */
+#define ADC_Channel_12                             ADC_CHSELR_CHSEL12 /*!< Not available for STM32F031 devices */
+#define ADC_Channel_13                             ADC_CHSELR_CHSEL13 /*!< Not available for STM32F031 devices */
+#define ADC_Channel_14                             ADC_CHSELR_CHSEL14 /*!< Not available for STM32F031 devices */
+#define ADC_Channel_15                             ADC_CHSELR_CHSEL15 /*!< Not available for STM32F031 devices */
+#define ADC_Channel_16                             ADC_CHSELR_CHSEL16
+#define ADC_Channel_17                             ADC_CHSELR_CHSEL17
+#define ADC_Channel_18                             ADC_CHSELR_CHSEL18 /*!< Not available for STM32F030 devices */
+
+#define ADC_Channel_TempSensor                     ((uint32_t)ADC_Channel_16)
+#define ADC_Channel_Vrefint                        ((uint32_t)ADC_Channel_17)
+#define ADC_Channel_Vbat                           ((uint32_t)ADC_Channel_18) /*!< Not available for STM32F030 devices */
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) != (uint32_t)RESET) && (((CHANNEL) & 0xFFF80000) == (uint32_t)RESET))
+
+/**
+  * @}
+  */ 
+  
+/** @defgroup ADC_interrupts_definition 
+  * @{
+  */ 
+  
+#define ADC_IT_ADRDY                               ADC_IER_ADRDYIE
+#define ADC_IT_EOSMP                               ADC_IER_EOSMPIE
+#define ADC_IT_EOC                                 ADC_IER_EOCIE
+#define ADC_IT_EOSEQ                               ADC_IER_EOSEQIE
+#define ADC_IT_OVR                                 ADC_IER_OVRIE
+#define ADC_IT_AWD                                 ADC_IER_AWDIE
+ 
+#define IS_ADC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFF60) == (uint32_t)RESET))
+
+#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_ADRDY) || ((IT) == ADC_IT_EOSMP) || \
+                           ((IT) == ADC_IT_EOC)   || ((IT) == ADC_IT_EOSEQ) || \
+                           ((IT) == ADC_IT_OVR)   || ((IT) == ADC_IT_AWD))
+
+#define IS_ADC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFF60) == (uint32_t)RESET))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_flags_definition 
+  * @{
+  */ 
+  
+#define ADC_FLAG_ADRDY                             ADC_ISR_ADRDY
+#define ADC_FLAG_EOSMP                             ADC_ISR_EOSMP
+#define ADC_FLAG_EOC                               ADC_ISR_EOC
+#define ADC_FLAG_EOSEQ                             ADC_ISR_EOSEQ
+#define ADC_FLAG_OVR                               ADC_ISR_OVR
+#define ADC_FLAG_AWD                               ADC_ISR_AWD
+
+#define ADC_FLAG_ADEN                              ((uint32_t)0x01000001)
+#define ADC_FLAG_ADDIS                             ((uint32_t)0x01000002)
+#define ADC_FLAG_ADSTART                           ((uint32_t)0x01000004)
+#define ADC_FLAG_ADSTP                             ((uint32_t)0x01000010)
+#define ADC_FLAG_ADCAL                             ((uint32_t)0x81000000) 
+
+#define IS_ADC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFFFF60) == (uint32_t)RESET))
+
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_ADRDY)   || ((FLAG) == ADC_FLAG_EOSMP) || \
+                               ((FLAG) == ADC_FLAG_EOC)     || ((FLAG) == ADC_FLAG_EOSEQ) || \
+                               ((FLAG) == ADC_FLAG_AWD)     || ((FLAG) == ADC_FLAG_OVR)   || \
+                               ((FLAG) == ADC_FLAG_ADEN)    || ((FLAG) == ADC_FLAG_ADDIS) || \
+                               ((FLAG) == ADC_FLAG_ADSTART) || ((FLAG) == ADC_FLAG_ADSTP) || \
+                               ((FLAG) == ADC_FLAG_ADCAL))
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */ 
+
+/*  Function used to set the ADC configuration to the default reset state *****/
+void ADC_DeInit(ADC_TypeDef* ADCx);
+
+/* Initialization and Configuration functions *********************************/ 
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
+void ADC_ClockModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ClockMode);
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+/* This Function is obsolete and maintained for legacy purpose only.
+   ADC_ClockModeConfig() function should be used instead */
+void ADC_JitterCmd(ADC_TypeDef* ADCx, uint32_t ADC_JitterOff, FunctionalState NewState);
+
+/* Power saving functions *****************************************************/
+void ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+
+/* Analog Watchdog configuration functions ************************************/
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog_Channel);
+void ADC_AnalogWatchdogSingleChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+
+/* Temperature Sensor , Vrefint and Vbat management function ******************/
+void ADC_TempSensorCmd(FunctionalState NewState);
+void ADC_VrefintCmd(FunctionalState NewState);
+void ADC_VbatCmd(FunctionalState NewState); /*!< Not applicable for STM32F030 devices */
+
+/* Channels Configuration functions *******************************************/
+void ADC_ChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_Channel, uint32_t ADC_SampleTime);
+void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_OverrunModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+uint32_t ADC_GetCalibrationFactor(ADC_TypeDef* ADCx);
+void ADC_StopOfConversion(ADC_TypeDef* ADCx);
+void ADC_StartOfConversion(ADC_TypeDef* ADCx);
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
+
+/* Regular Channels DMA Configuration functions *******************************/
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DMARequestModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMARequestMode);
+
+/* Interrupts and flags management functions **********************************/
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT);
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F0XX_ADC_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_can.h b/system/include/stm32f0-stdperiph/stm32f0xx_can.h

new file mode 100644 (file)

index 0000000..7e4ca37
--- /dev/null
+++ b/system/include/stm32f0-stdperiph/stm32f0xx_can.h
@@ -0,0 +1,643 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_can.h
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file contains all the functions prototypes for the CAN firmware 
+  *          library, applicable only for STM32F072 devices.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_CAN_H
+#define __STM32F0xx_CAN_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup CAN
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN))
+
+/** 
+  * @brief  CAN init structure definition
+  */
+typedef struct
+{
+  uint16_t CAN_Prescaler;   /*!< Specifies the length of a time quantum. 
+                                 It ranges from 1 to 1024. */
+  
+  uint8_t CAN_Mode;         /*!< Specifies the CAN operating mode.
+                                 This parameter can be a value of @ref CAN_operating_mode */
+
+  uint8_t CAN_SJW;          /*!< Specifies the maximum number of time quanta 
+                                 the CAN hardware is allowed to lengthen or 
+                                 shorten a bit to perform resynchronization.
+                                 This parameter can be a value of @ref CAN_synchronisation_jump_width */
+
+  uint8_t CAN_BS1;          /*!< Specifies the number of time quanta in Bit 
+                                 Segment 1. This parameter can be a value of 
+                                 @ref CAN_time_quantum_in_bit_segment_1 */
+
+  uint8_t CAN_BS2;          /*!< Specifies the number of time quanta in Bit Segment 2.
+                                 This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
+  
+  FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.
+                                This parameter can be set either to ENABLE or DISABLE. */
+  
+  FunctionalState CAN_ABOM;  /*!< Enable or disable the automatic bus-off management.
+                                  This parameter can be set either to ENABLE or DISABLE. */
+
+  FunctionalState CAN_AWUM;  /*!< Enable or disable the automatic wake-up mode. 
+                                  This parameter can be set either to ENABLE or DISABLE. */
+
+  FunctionalState CAN_NART;  /*!< Enable or disable the non-automatic retransmission mode.
+                                  This parameter can be set either to ENABLE or DISABLE. */
+
+  FunctionalState CAN_RFLM;  /*!< Enable or disable the Receive FIFO Locked mode.
+                                  This parameter can be set either to ENABLE or DISABLE. */
+
+  FunctionalState CAN_TXFP;  /*!< Enable or disable the transmit FIFO priority.
+                                  This parameter can be set either to ENABLE or DISABLE. */
+} CAN_InitTypeDef;
+
+/** 
+  * @brief  CAN filter init structure definition
+  */
+typedef struct
+{
+  uint16_t CAN_FilterIdHigh;         /*!< Specifies the filter identification number (MSBs for a 32-bit
+                                              configuration, first one for a 16-bit configuration).
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterIdLow;          /*!< Specifies the filter identification number (LSBs for a 32-bit
+                                              configuration, second one for a 16-bit configuration).
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterMaskIdHigh;     /*!< Specifies the filter mask number or identification number,
+                                              according to the mode (MSBs for a 32-bit configuration,
+                                              first one for a 16-bit configuration).
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterMaskIdLow;      /*!< Specifies the filter mask number or identification number,
+                                              according to the mode (LSBs for a 32-bit configuration,
+                                              second one for a 16-bit configuration).
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+                                              This parameter can be a value of @ref CAN_filter_FIFO */
+  
+  uint8_t CAN_FilterNumber;          /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
+
+  uint8_t CAN_FilterMode;            /*!< Specifies the filter mode to be initialized.
+                                              This parameter can be a value of @ref CAN_filter_mode */
+
+  uint8_t CAN_FilterScale;           /*!< Specifies the filter scale.
+                                              This parameter can be a value of @ref CAN_filter_scale */
+
+  FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
+                                              This parameter can be set either to ENABLE or DISABLE. */
+} CAN_FilterInitTypeDef;
+
+/** 
+  * @brief  CAN Tx message structure definition  
+  */
+typedef struct
+{
+  uint32_t StdId;  /*!< Specifies the standard identifier.
+                        This parameter can be a value between 0 to 0x7FF. */
+
+  uint32_t ExtId;  /*!< Specifies the extended identifier.
+                        This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+  uint8_t IDE;     /*!< Specifies the type of identifier for the message that 
+                        will be transmitted. This parameter can be a value 
+                        of @ref CAN_identifier_type */
+
+  uint8_t RTR;     /*!< Specifies the type of frame for the message that will 
+                        be transmitted. This parameter can be a value of 
+                        @ref CAN_remote_transmission_request */
+
+  uint8_t DLC;     /*!< Specifies the length of the frame that will be 
+                        transmitted. This parameter can be a value between 
+                        0 to 8 */
+
+  uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 
+                        to 0xFF. */
+} CanTxMsg;
+
+/** 
+  * @brief  CAN Rx message structure definition  
+  */
+typedef struct
+{
+  uint32_t StdId;  /*!< Specifies the standard identifier.
+                        This parameter can be a value between 0 to 0x7FF. */
+
+  uint32_t ExtId;  /*!< Specifies the extended identifier.
+                        This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+  uint8_t IDE;     /*!< Specifies the type of identifier for the message that 
+                        will be received. This parameter can be a value of 
+                        @ref CAN_identifier_type */
+
+  uint8_t RTR;     /*!< Specifies the type of frame for the received message.
+                        This parameter can be a value of 
+                        @ref CAN_remote_transmission_request */
+
+  uint8_t DLC;     /*!< Specifies the length of the frame that will be received.
+                        This parameter can be a value between 0 to 8 */
+
+  uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 
+                        0xFF. */
+
+  uint8_t FMI;     /*!< Specifies the index of the filter the message stored in 
+                        the mailbox passes through. This parameter can be a 
+                        value between 0 to 0xFF */
+} CanRxMsg;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CAN_Exported_Constants
+  * @{
+  */
+
+/** @defgroup CAN_InitStatus 
+  * @{
+  */
+
+#define CAN_InitStatus_Failed              ((uint8_t)0x00) /*!< CAN initialization failed */
+#define CAN_InitStatus_Success             ((uint8_t)0x01) /*!< CAN initialization OK */
+
+
+/* Legacy defines */
+#define CANINITFAILED    CAN_InitStatus_Failed
+#define CANINITOK        CAN_InitStatus_Success
+/**
+  * @}
+  */
+
+/** @defgroup CAN_operating_mode 
+  * @{
+  */
+
+#define CAN_Mode_Normal             ((uint8_t)0x00)  /*!< normal mode */
+#define CAN_Mode_LoopBack           ((uint8_t)0x01)  /*!< loopback mode */
+#define CAN_Mode_Silent             ((uint8_t)0x02)  /*!< silent mode */
+#define CAN_Mode_Silent_LoopBack    ((uint8_t)0x03)  /*!< loopback combined with silent mode */
+
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
+                           ((MODE) == CAN_Mode_LoopBack)|| \
+                           ((MODE) == CAN_Mode_Silent) || \
+                           ((MODE) == CAN_Mode_Silent_LoopBack))
+/**
+  * @}
+  */
+
+
+ /**
+  * @defgroup CAN_operating_mode 
+  * @{
+  */  
+#define CAN_OperatingMode_Initialization  ((uint8_t)0x00) /*!< Initialization mode */
+#define CAN_OperatingMode_Normal          ((uint8_t)0x01) /*!< Normal mode */
+#define CAN_OperatingMode_Sleep           ((uint8_t)0x02) /*!< sleep mode */
+
+
+#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
+                                    ((MODE) == CAN_OperatingMode_Normal)|| \
+                                                                                                                                               ((MODE) == CAN_OperatingMode_Sleep))
+/**
+  * @}
+  */
+  
+/**
+  * @defgroup CAN_operating_mode_status
+  * @{
+  */  
+
+#define CAN_ModeStatus_Failed    ((uint8_t)0x00)                /*!< CAN entering the specific mode failed */
+#define CAN_ModeStatus_Success   ((uint8_t)!CAN_ModeStatus_Failed)   /*!< CAN entering the specific mode Succeed */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_synchronisation_jump_width 
+  * @{
+  */
+#define CAN_SJW_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_SJW_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_SJW_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_SJW_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
+
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
+                         ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_1 
+  * @{
+  */
+#define CAN_BS1_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_BS1_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_BS1_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_BS1_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
+#define CAN_BS1_5tq                 ((uint8_t)0x04)  /*!< 5 time quantum */
+#define CAN_BS1_6tq                 ((uint8_t)0x05)  /*!< 6 time quantum */
+#define CAN_BS1_7tq                 ((uint8_t)0x06)  /*!< 7 time quantum */
+#define CAN_BS1_8tq                 ((uint8_t)0x07)  /*!< 8 time quantum */
+#define CAN_BS1_9tq                 ((uint8_t)0x08)  /*!< 9 time quantum */
+#define CAN_BS1_10tq                ((uint8_t)0x09)  /*!< 10 time quantum */
+#define CAN_BS1_11tq                ((uint8_t)0x0A)  /*!< 11 time quantum */
+#define CAN_BS1_12tq                ((uint8_t)0x0B)  /*!< 12 time quantum */
+#define CAN_BS1_13tq                ((uint8_t)0x0C)  /*!< 13 time quantum */
+#define CAN_BS1_14tq                ((uint8_t)0x0D)  /*!< 14 time quantum */
+#define CAN_BS1_15tq                ((uint8_t)0x0E)  /*!< 15 time quantum */
+#define CAN_BS1_16tq                ((uint8_t)0x0F)  /*!< 16 time quantum */
+
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
+/**
+  * @}
+  */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2 
+  * @{
+  */
+#define CAN_BS2_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_BS2_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_BS2_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_BS2_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
+#define CAN_BS2_5tq                 ((uint8_t)0x04)  /*!< 5 time quantum */
+#define CAN_BS2_6tq                 ((uint8_t)0x05)  /*!< 6 time quantum */
+#define CAN_BS2_7tq                 ((uint8_t)0x06)  /*!< 7 time quantum */
+#define CAN_BS2_8tq                 ((uint8_t)0x07)  /*!< 8 time quantum */
+
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
+/**
+  * @}
+  */
+
+/** @defgroup CAN_clock_prescaler 
+  * @{
+  */
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_number 
+  * @{
+  */
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_mode 
+  * @{
+  */
+#define CAN_FilterMode_IdMask       ((uint8_t)0x00)  /*!< identifier/mask mode */
+#define CAN_FilterMode_IdList       ((uint8_t)0x01)  /*!< identifier list mode */
+
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
+                                  ((MODE) == CAN_FilterMode_IdList))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_scale 
+  * @{
+  */
+#define CAN_FilterScale_16bit       ((uint8_t)0x00) /*!< Two 16-bit filters */
+#define CAN_FilterScale_32bit       ((uint8_t)0x01) /*!< One 32-bit filter */
+
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
+                                    ((SCALE) == CAN_FilterScale_32bit))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_FIFO
+  * @{
+  */
+#define CAN_Filter_FIFO0             ((uint8_t)0x00)  /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_Filter_FIFO1             ((uint8_t)0x01)  /*!< Filter FIFO 1 assignment for filter x */
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
+                                  ((FIFO) == CAN_FilterFIFO1))
+
+/* Legacy defines */
+#define CAN_FilterFIFO0  CAN_Filter_FIFO0
+#define CAN_FilterFIFO1  CAN_Filter_FIFO1
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Start_bank_filter_for_slave_CAN 
+  * @{
+  */
+#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Tx 
+  * @{
+  */
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_identifier_type 
+  * @{
+  */
+#define CAN_Id_Standard             ((uint32_t)0x00000000)  /*!< Standard Id */
+#define CAN_Id_Extended             ((uint32_t)0x00000004)  /*!< Extended Id */
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
+                               ((IDTYPE) == CAN_Id_Extended))
+
+/* Legacy defines */
+#define CAN_ID_STD      CAN_Id_Standard           
+#define CAN_ID_EXT      CAN_Id_Extended
+/**
+  * @}
+  */
+
+/** @defgroup CAN_remote_transmission_request 
+  * @{
+  */
+#define CAN_RTR_Data                ((uint32_t)0x00000000)  /*!< Data frame */
+#define CAN_RTR_Remote              ((uint32_t)0x00000002)  /*!< Remote frame */
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
+
+/* Legacy defines */
+#define CAN_RTR_DATA     CAN_RTR_Data         
+#define CAN_RTR_REMOTE   CAN_RTR_Remote
+/**
+  * @}
+  */
+
+/** @defgroup CAN_transmit_constants 
+  * @{
+  */
+#define CAN_TxStatus_Failed         ((uint8_t)0x00)/*!< CAN transmission failed */
+#define CAN_TxStatus_Ok             ((uint8_t)0x01) /*!< CAN transmission succeeded */
+#define CAN_TxStatus_Pending        ((uint8_t)0x02) /*!< CAN transmission pending */
+#define CAN_TxStatus_NoMailBox      ((uint8_t)0x04) /*!< CAN cell did not provide 
+                                                         an empty mailbox */
+/* Legacy defines */   
+#define CANTXFAILED                  CAN_TxStatus_Failed
+#define CANTXOK                      CAN_TxStatus_Ok
+#define CANTXPENDING                 CAN_TxStatus_Pending
+#define CAN_NO_MB                    CAN_TxStatus_NoMailBox
+/**
+  * @}
+  */
+
+/** @defgroup CAN_receive_FIFO_number_constants 
+  * @{
+  */
+#define CAN_FIFO0                 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
+#define CAN_FIFO1                 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
+
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_sleep_constants 
+  * @{
+  */
+#define CAN_Sleep_Failed     ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
+#define CAN_Sleep_Ok         ((uint8_t)0x01) /*!< CAN entered the sleep mode */
+
+/* Legacy defines */   
+#define CANSLEEPFAILED   CAN_Sleep_Failed
+#define CANSLEEPOK       CAN_Sleep_Ok
+/**
+  * @}
+  */
+
+/** @defgroup CAN_wake_up_constants 
+  * @{
+  */
+#define CAN_WakeUp_Failed        ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
+#define CAN_WakeUp_Ok            ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
+
+/* Legacy defines */
+#define CANWAKEUPFAILED   CAN_WakeUp_Failed        
+#define CANWAKEUPOK       CAN_WakeUp_Ok        
+/**
+  * @}
+  */
+
+/**
+  * @defgroup CAN_Error_Code_constants
+  * @{
+  */                                                         
+#define CAN_ErrorCode_NoErr           ((uint8_t)0x00) /*!< No Error */ 
+#define        CAN_ErrorCode_StuffErr        ((uint8_t)0x10) /*!< Stuff Error */ 
+#define        CAN_ErrorCode_FormErr         ((uint8_t)0x20) /*!< Form Error */ 
+#define        CAN_ErrorCode_ACKErr          ((uint8_t)0x30) /*!< Acknowledgment Error */ 
+#define        CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ 
+#define        CAN_ErrorCode_BitDominantErr  ((uint8_t)0x50) /*!< Bit Dominant Error */ 
+#define        CAN_ErrorCode_CRCErr          ((uint8_t)0x60) /*!< CRC Error  */ 
+#define        CAN_ErrorCode_SoftwareSetErr  ((uint8_t)0x70) /*!< Software Set Error */ 
+/**
+  * @}
+  */
+
+/** @defgroup CAN_flags 
+  * @{
+  */
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
+   and CAN_ClearFlag() functions. */
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with 
+   CAN_GetFlagStatus() function.  */
+
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0             ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
+#define CAN_FLAG_RQCP1             ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
+#define CAN_FLAG_RQCP2             ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FMP0              ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
+#define CAN_FLAG_FF0               ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag            */
+#define CAN_FLAG_FOV0              ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag         */
+#define CAN_FLAG_FMP1              ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
+#define CAN_FLAG_FF1               ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag            */
+#define CAN_FLAG_FOV1              ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag         */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_WKU               ((uint32_t)0x31000008) /*!< Wake up Flag */
+#define CAN_FLAG_SLAK              ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
+/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. 
+         In this case the SLAK bit can be polled.*/
+
+/* Error Flags */
+#define CAN_FLAG_EWG               ((uint32_t)0x10F00001) /*!< Error Warning Flag   */
+#define CAN_FLAG_EPV               ((uint32_t)0x10F00002) /*!< Error Passive Flag   */
+#define CAN_FLAG_BOF               ((uint32_t)0x10F00004) /*!< Bus-Off Flag         */
+#define CAN_FLAG_LEC               ((uint32_t)0x30F00070) /*!< Last error code Flag */
+
+#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC)  || ((FLAG) == CAN_FLAG_BOF)   || \
+                               ((FLAG) == CAN_FLAG_EPV)  || ((FLAG) == CAN_FLAG_EWG)   || \
+                               ((FLAG) == CAN_FLAG_WKU)  || ((FLAG) == CAN_FLAG_FOV0)  || \
+                               ((FLAG) == CAN_FLAG_FF0)  || ((FLAG) == CAN_FLAG_FMP0)  || \
+                               ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1)   || \
+                               ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
+                               ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
+                               ((FLAG) == CAN_FLAG_SLAK ))
+
+#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
+                                ((FLAG) == CAN_FLAG_RQCP1)  || ((FLAG) == CAN_FLAG_RQCP0) || \
+                                ((FLAG) == CAN_FLAG_FF0)  || ((FLAG) == CAN_FLAG_FOV0) ||\
+                                ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
+                                ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
+/**
+  * @}
+  */
+
+  
+/** @defgroup CAN_interrupts 
+  * @{
+  */ 
+#define CAN_IT_TME                  ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
+
+/* Receive Interrupts */
+#define CAN_IT_FMP0                 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
+#define CAN_IT_FF0                  ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
+#define CAN_IT_FOV0                 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
+#define CAN_IT_FMP1                 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
+#define CAN_IT_FF1                  ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
+#define CAN_IT_FOV1                 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
+
+/* Operating Mode Interrupts */
+#define CAN_IT_WKU                  ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
+#define CAN_IT_SLK                  ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
+
+/* Error Interrupts */
+#define CAN_IT_EWG                  ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
+#define CAN_IT_EPV                  ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
+#define CAN_IT_BOF                  ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
+#define CAN_IT_LEC                  ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
+#define CAN_IT_ERR                  ((uint32_t)0x00008000) /*!< Error Interrupt*/
+
+/* Flags named as Interrupts : kept only for FW compatibility */
+#define CAN_IT_RQCP0   CAN_IT_TME
+#define CAN_IT_RQCP1   CAN_IT_TME
+#define CAN_IT_RQCP2   CAN_IT_TME
+
+
+#define IS_CAN_IT(IT)        (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0)  ||\
+                             ((IT) == CAN_IT_FF0)  || ((IT) == CAN_IT_FOV0)  ||\
+                             ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1)   ||\
+                             ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG)   ||\
+                             ((IT) == CAN_IT_EPV)  || ((IT) == CAN_IT_BOF)   ||\
+                             ((IT) == CAN_IT_LEC)  || ((IT) == CAN_IT_ERR)   ||\
+                             ((IT) == CAN_IT_WKU)  || ((IT) == CAN_IT_SLK))
+
+#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0)    ||\
+                             ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1)    ||\
+                             ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG)    ||\
+                             ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF)    ||\
+                             ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR)    ||\
+                             ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/  
+
+/*  Function used to set the CAN configuration to the default reset state *****/ 
+void CAN_DeInit(CAN_TypeDef* CANx);
+
+/* Initialization and Configuration functions *********************************/ 
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber); 
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
+void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
+
+/* CAN Frames Transmission functions ******************************************/
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
+
+/* CAN Frames Reception functions *********************************************/
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
+
+/* Operation modes functions **************************************************/
+uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
+uint8_t CAN_Sleep(CAN_TypeDef* CANx);
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
+
+/* CAN Bus Error management functions *****************************************/
+uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
+uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
+
+/* Interrupts and flags management functions **********************************/
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_CAN_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_cec.h b/system/include/stm32f0-stdperiph/stm32f0xx_cec.h

new file mode 100644 (file)

index 0000000..f02fec0
--- /dev/null
+++ b/system/include/stm32f0-stdperiph/stm32f0xx_cec.h
@@ -0,0 +1,300 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_cec.h
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file contains all the functions prototypes for the CEC firmware 
+  *          library, applicable only for STM32F051, STM32F042 and STM32F072 devices.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_CEC_H
+#define __STM32F0XX_CEC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup CEC
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/
+  
+/** 
+  * @brief CEC Init structure definition 
+  */
+typedef struct
+{
+  uint32_t CEC_SignalFreeTime;     /*!< Specifies the CEC Signal Free Time configuration.
+                                   This parameter can be a value of @ref CEC_Signal_Free_Time */
+  uint32_t CEC_RxTolerance;        /*!< Specifies the CEC Reception Tolerance.
+                                   This parameter can be a value of @ref CEC_RxTolerance */
+  uint32_t CEC_StopReception;      /*!< Specifies the CEC Stop Reception.
+                                   This parameter can be a value of @ref CEC_Stop_Reception */
+  uint32_t CEC_BitRisingError;     /*!< Specifies the CEC Bit Rising Error generation.
+                                   This parameter can be a value of @ref CEC_Bit_Rising_Error_Generation */
+  uint32_t CEC_LongBitPeriodError; /*!< Specifies the CEC Long Bit Error generation.
+                                   This parameter can be a value of @ref CEC_Long_Bit_Error_Generation */
+  uint32_t CEC_BRDNoGen;           /*!< Specifies the CEC Broadcast Error generation.
+                                   This parameter can be a value of @ref CEC_BDR_No_Gen */
+  uint32_t CEC_SFTOption;          /*!< Specifies the CEC Signal Free Time option.
+                                   This parameter can be a value of @ref CEC_SFT_Option */
+
+}CEC_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CEC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup CEC_Signal_Free_Time
+  * @{
+  */
+#define CEC_SignalFreeTime_Standard     ((uint32_t)0x00000000) /*!< CEC Signal Free Time Standard         */
+#define CEC_SignalFreeTime_1T           ((uint32_t)0x00000001) /*!< CEC  1.5 nominal data bit periods     */
+#define CEC_SignalFreeTime_2T           ((uint32_t)0x00000002) /*!< CEC  2.5 nominal data bit periods     */
+#define CEC_SignalFreeTime_3T           ((uint32_t)0x00000003) /*!< CEC  3.5 nominal data bit periods     */
+#define CEC_SignalFreeTime_4T           ((uint32_t)0x00000004) /*!< CEC  4.5 nominal data bit periods     */
+#define CEC_SignalFreeTime_5T           ((uint32_t)0x00000005) /*!< CEC  5.5 nominal data bit periods     */
+#define CEC_SignalFreeTime_6T           ((uint32_t)0x00000006) /*!< CEC  6.5 nominal data bit periods     */
+#define CEC_SignalFreeTime_7T           ((uint32_t)0x00000007) /*!< CEC  7.5 nominal data bit periods     */
+
+#define IS_CEC_SIGNAL_FREE_TIME(TIME) (((TIME) == CEC_SignalFreeTime_Standard) || \
+                                       ((TIME) == CEC_SignalFreeTime_1T)|| \
+                                       ((TIME) == CEC_SignalFreeTime_2T)|| \
+                                       ((TIME) == CEC_SignalFreeTime_3T)|| \
+                                       ((TIME) == CEC_SignalFreeTime_4T)|| \
+                                       ((TIME) == CEC_SignalFreeTime_5T)|| \
+                                       ((TIME) == CEC_SignalFreeTime_6T)|| \
+                                       ((TIME) == CEC_SignalFreeTime_7T))
+/**
+  * @}
+  */
+
+/** @defgroup CEC_RxTolerance
+  * @{
+  */
+#define CEC_RxTolerance_Standard        ((uint32_t)0x00000000) /*!< Standard Tolerance Margin            */
+#define CEC_RxTolerance_Extended        CEC_CFGR_RXTOL         /*!< Extended Tolerance Margin            */
+
+#define IS_CEC_RX_TOLERANCE(TOLERANCE) (((TOLERANCE) == CEC_RxTolerance_Standard) || \
+                                        ((TOLERANCE) == CEC_RxTolerance_Extended))
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Stop_Reception
+  * @{
+  */
+#define CEC_StopReception_Off           ((uint32_t)0x00000000) /*!< No RX Stop on bit Rising Error (BRE) */
+#define CEC_StopReception_On            CEC_CFGR_BRESTP        /*!< RX Stop on bit Rising Error (BRE)    */
+
+#define IS_CEC_STOP_RECEPTION(RECEPTION) (((RECEPTION) == CEC_StopReception_On) || \
+                                          ((RECEPTION) == CEC_StopReception_Off))
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Bit_Rising_Error_Generation
+  * @{
+  */
+#define CEC_BitRisingError_Off          ((uint32_t)0x00000000) /*!< Bit Rising Error generation turned Off */
+#define CEC_BitRisingError_On           CEC_CFGR_BREGEN        /*!< Bit Rising Error generation turned On  */
+
+#define IS_CEC_BIT_RISING_ERROR(ERROR) (((ERROR) == CEC_BitRisingError_Off) || \
+                                        ((ERROR) == CEC_BitRisingError_On))
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Long_Bit_Error_Generation
+  * @{
+  */
+#define CEC_LongBitPeriodError_Off      ((uint32_t)0x00000000)  /*!< Long Bit Period Error generation turned Off */
+#define CEC_LongBitPeriodError_On       CEC_CFGR_LREGEN         /*!< Long Bit Period Error generation turned On  */
+
+#define IS_CEC_LONG_BIT_PERIOD_ERROR(ERROR) (((ERROR) == CEC_LongBitPeriodError_Off) || \
+                                             ((ERROR) == CEC_LongBitPeriodError_On))
+/**
+  * @}
+  */
+
+/** @defgroup CEC_BDR_No_Gen
+  * @{
+  */
+
+#define CEC_BRDNoGen_Off      ((uint32_t)0x00000000)  /*!< Broadcast Bit Rising Error generation turned Off */
+#define CEC_BRDNoGen_On       CEC_CFGR_BRDNOGEN       /*!< Broadcast Bit Rising Error generation turned On  */
+
+#define IS_CEC_BDR_NO_GEN_ERROR(ERROR) (((ERROR) == CEC_BRDNoGen_Off) || \
+                                        ((ERROR) == CEC_BRDNoGen_On))
+/**
+  * @}
+  */
+
+/** @defgroup CEC_SFT_Option
+  * @{
+  */
+#define CEC_SFTOption_Off              ((uint32_t)0x00000000)  /*!< SFT option turned Off                   */
+#define CEC_SFTOption_On               CEC_CFGR_SFTOPT         /*!< SFT option turned On                    */
+
+#define IS_CEC_SFT_OPTION(OPTION) (((OPTION) == CEC_SFTOption_Off) || \
+                                  ((OPTION) == CEC_SFTOption_On))
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Own_Address
+  * @{
+  */
+#define IS_CEC_ADDRESS(ADDRESS)         ((ADDRESS) < 0x10)
+
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Interrupt_Configuration_definition
+  * @{
+  */
+#define CEC_IT_TXACKE                   CEC_IER_TXACKEIE
+#define CEC_IT_TXERR                    CEC_IER_TXERRIE
+#define CEC_IT_TXUDR                    CEC_IER_TXUDRIE
+#define CEC_IT_TXEND                    CEC_IER_TXENDIE
+#define CEC_IT_TXBR                     CEC_IER_TXBRIE
+#define CEC_IT_ARBLST                   CEC_IER_ARBLSTIE
+#define CEC_IT_RXACKE                   CEC_IER_RXACKEIE
+#define CEC_IT_LBPE                     CEC_IER_LBPEIE
+#define CEC_IT_SBPE                     CEC_IER_SBPEIE
+#define CEC_IT_BRE                      CEC_IER_BREIEIE
+#define CEC_IT_RXOVR                    CEC_IER_RXOVRIE
+#define CEC_IT_RXEND                    CEC_IER_RXENDIE
+#define CEC_IT_RXBR                     CEC_IER_RXBRIE
+
+#define IS_CEC_IT(IT) ((((IT) & (uint32_t)0xFFFFE000) == 0x00) && ((IT) != 0x00))
+
+#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TXACKE) || \
+                           ((IT) == CEC_IT_TXERR)|| \
+                           ((IT) == CEC_IT_TXUDR)|| \
+                           ((IT) == CEC_IT_TXEND)|| \
+                           ((IT) == CEC_IT_TXBR)|| \
+                           ((IT) == CEC_IT_ARBLST)|| \
+                           ((IT) == CEC_IT_RXACKE)|| \
+                           ((IT) == CEC_IT_LBPE)|| \
+                           ((IT) == CEC_IT_SBPE)|| \
+                           ((IT) == CEC_IT_BRE)|| \
+                           ((IT) == CEC_IT_RXOVR)|| \
+                           ((IT) == CEC_IT_RXEND)|| \
+                           ((IT) == CEC_IT_RXBR))
+/**
+  * @}
+  */
+
+/** @defgroup CEC_ISR_register_flags_definition
+  * @{
+  */
+#define CEC_FLAG_TXACKE                 CEC_ISR_TXACKE
+#define CEC_FLAG_TXERR                  CEC_ISR_TXERR
+#define CEC_FLAG_TXUDR                  CEC_ISR_TXUDR
+#define CEC_FLAG_TXEND                  CEC_ISR_TXEND
+#define CEC_FLAG_TXBR                   CEC_ISR_TXBR
+#define CEC_FLAG_ARBLST                 CEC_ISR_ARBLST
+#define CEC_FLAG_RXACKE                 CEC_ISR_RXACKE
+#define CEC_FLAG_LBPE                   CEC_ISR_LBPE
+#define CEC_FLAG_SBPE                   CEC_ISR_SBPE
+#define CEC_FLAG_BRE                    CEC_ISR_BRE
+#define CEC_FLAG_RXOVR                  CEC_ISR_RXOVR
+#define CEC_FLAG_RXEND                  CEC_ISR_RXEND
+#define CEC_FLAG_RXBR                   CEC_ISR_RXBR
+
+#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFE000) == 0x00) && ((FLAG) != 0x00))
+
+#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_TXACKE) || \
+                               ((FLAG) == CEC_FLAG_TXERR)|| \
+                               ((FLAG) == CEC_FLAG_TXUDR)|| \
+                               ((FLAG) == CEC_FLAG_TXEND)|| \
+                               ((FLAG) == CEC_FLAG_TXBR)|| \
+                               ((FLAG) == CEC_FLAG_ARBLST)|| \
+                               ((FLAG) == CEC_FLAG_RXACKE)|| \
+                               ((FLAG) == CEC_FLAG_LBPE)|| \
+                               ((FLAG) == CEC_FLAG_SBPE)|| \
+                               ((FLAG) == CEC_FLAG_BRE)|| \
+                               ((FLAG) == CEC_FLAG_RXOVR)|| \
+                               ((FLAG) == CEC_FLAG_RXEND)|| \
+                               ((FLAG) == CEC_FLAG_RXBR))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/*  Function used to set the CEC configuration to the default reset state *****/
+void CEC_DeInit(void);
+
+/* CEC_Initialization and Configuration functions *****************************/
+void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
+void CEC_StructInit(CEC_InitTypeDef* CEC_InitStruct);
+void CEC_Cmd(FunctionalState NewState);
+void CEC_ListenModeCmd(FunctionalState NewState);
+void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);
+void CEC_OwnAddressClear(void);
+
+/* CEC_Data transfers functions ***********************************************/
+void CEC_SendData(uint8_t Data);
+uint8_t CEC_ReceiveData(void);
+void CEC_StartOfMessage(void);
+void CEC_EndOfMessage(void);
+
+/* CEC_Interrupts and flags management functions ******************************/
+void CEC_ITConfig(uint16_t CEC_IT, FunctionalState NewState);
+FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG);
+void CEC_ClearFlag(uint32_t CEC_FLAG);
+ITStatus CEC_GetITStatus(uint16_t CEC_IT);
+void CEC_ClearITPendingBit(uint16_t CEC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0XX_CEC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_comp.h b/system/include/stm32f0-stdperiph/stm32f0xx_comp.h

new file mode 100644 (file)

index 0000000..6854d55
--- /dev/null
+++ b/system/include/stm32f0-stdperiph/stm32f0xx_comp.h
@@ -0,0 +1,245 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_comp.h
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file contains all the functions prototypes for the COMP firmware 
+  *          library, applicable only for STM32F051 and STM32F072 devices.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_COMP_H
+#define __STM32F0XX_COMP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup COMP
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  COMP Init structure definition  
+  */
+  
+typedef struct
+{
+
+  uint32_t COMP_InvertingInput;     /*!< Selects the inverting input of the comparator.
+                                          This parameter can be a value of @ref COMP_InvertingInput */
+
+  uint32_t COMP_Output;             /*!< Selects the output redirection of the comparator.
+                                          This parameter can be a value of @ref COMP_Output */
+
+  uint32_t COMP_OutputPol;           /*!< Selects the output polarity of the comparator.
+                                          This parameter can be a value of @ref COMP_OutputPolarity */
+
+  uint32_t COMP_Hysteresis;         /*!< Selects the hysteresis voltage of the comparator.
+                                          This parameter can be a value of @ref COMP_Hysteresis */
+
+  uint32_t COMP_Mode;               /*!< Selects the operating mode of the comparator
+                                         and allows to adjust the speed/consumption.
+                                          This parameter can be a value of @ref COMP_Mode */
+
+}COMP_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+   
+/** @defgroup COMP_Exported_Constants
+  * @{
+  */ 
+
+/** @defgroup COMP_Selection
+  * @{
+  */
+
+#define COMP_Selection_COMP1                    ((uint32_t)0x00000000) /*!< COMP1 Selection */
+#define COMP_Selection_COMP2                    ((uint32_t)0x00000010) /*!< COMP2 Selection */
+
+#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \
+                                    ((PERIPH) == COMP_Selection_COMP2))
+ 
+/**
+  * @}
+  */ 
+
+/** @defgroup COMP_InvertingInput
+  * @{
+  */
+
+#define COMP_InvertingInput_1_4VREFINT          ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */
+#define COMP_InvertingInput_1_2VREFINT          COMP_CSR_COMP1INSEL_0  /*!< 1/2 VREFINT connected to comparator inverting input */
+#define COMP_InvertingInput_3_4VREFINT          COMP_CSR_COMP1INSEL_1  /*!< 3/4 VREFINT connected to comparator inverting input */
+#define COMP_InvertingInput_VREFINT             ((uint32_t)0x00000030) /*!< VREFINT connected to comparator inverting input */
+#define COMP_InvertingInput_DAC1                COMP_CSR_COMP1INSEL_2  /*!< DAC1_OUT (PA4) connected to comparator inverting input */
+#define COMP_InvertingInput_DAC2                ((uint32_t)0x00000050) /*!< DAC2_OUT (PA5) connected to comparator inverting input, applicable only for STM32F072 devices */
+#define COMP_InvertingInput_IO                  ((uint32_t)0x00000060) /*!< I/O (PA0 for COMP1 and PA2 for COMP2) connected to comparator inverting input */
+
+#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
+                                        ((INPUT) == COMP_InvertingInput_1_2VREFINT) || \
+                                        ((INPUT) == COMP_InvertingInput_3_4VREFINT) || \
+                                        ((INPUT) == COMP_InvertingInput_VREFINT)    || \
+                                        ((INPUT) == COMP_InvertingInput_DAC1)       || \
+                                        ((INPUT) == COMP_InvertingInput_DAC2)       || \
+                                        ((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
+                                        ((INPUT) == COMP_InvertingInput_IO))
+/**
+  * @}
+  */ 
+  
+/** @defgroup COMP_Output
+  * @{
+  */
+
+#define COMP_Output_None                  ((uint32_t)0x00000000)   /*!< COMP output isn't connected to other peripherals */
+#define COMP_Output_TIM1BKIN              COMP_CSR_COMP1OUTSEL_0   /*!< COMP output connected to TIM1 Break Input (BKIN) */
+#define COMP_Output_TIM1IC1               COMP_CSR_COMP1OUTSEL_1   /*!< COMP output connected to TIM1 Input Capture 1 */
+#define COMP_Output_TIM1OCREFCLR          ((uint32_t)0x00000300)   /*!< COMP output connected to TIM1 OCREF Clear */
+#define COMP_Output_TIM2IC4               COMP_CSR_COMP1OUTSEL_2   /*!< COMP output connected to TIM2 Input Capture 4 */
+#define COMP_Output_TIM2OCREFCLR          ((uint32_t)0x00000500)   /*!< COMP output connected to TIM2 OCREF Clear */
+#define COMP_Output_TIM3IC1               ((uint32_t)0x00000600)   /*!< COMP output connected to TIM3 Input Capture 1 */
+#define COMP_Output_TIM3OCREFCLR          COMP_CSR_COMP1OUTSEL     /*!< COMP output connected to TIM3 OCREF Clear */
+
+
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_Output_None)         || \
+                                ((OUTPUT) == COMP_Output_TIM1BKIN)     || \
+                                ((OUTPUT) == COMP_Output_TIM1IC1)      || \
+                                ((OUTPUT) == COMP_Output_TIM1OCREFCLR) || \
+                                ((OUTPUT) == COMP_Output_TIM2IC4)      || \
+                                ((OUTPUT) == COMP_Output_TIM2OCREFCLR) || \
+                                ((OUTPUT) == COMP_Output_TIM3IC1)      || \
+                                ((OUTPUT) == COMP_Output_TIM3OCREFCLR))
+/**
+  * @}
+  */ 
+
+/** @defgroup COMP_OutputPolarity
+  * @{
+  */
+#define COMP_OutputPol_NonInverted          ((uint32_t)0x00000000)  /*!< COMP output on GPIO isn't inverted */
+#define COMP_OutputPol_Inverted             COMP_CSR_COMP1POL       /*!< COMP output on GPIO is inverted */
+
+#define IS_COMP_OUTPUT_POL(POL) (((POL) == COMP_OutputPol_NonInverted)  || \
+                                 ((POL) == COMP_OutputPol_Inverted))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup COMP_Hysteresis
+  * @{
+  */
+/* Please refer to the electrical characteristics in the device datasheet for
+   the hysteresis level */
+#define COMP_Hysteresis_No                         0x00000000           /*!< No hysteresis */
+#define COMP_Hysteresis_Low                        COMP_CSR_COMP1HYST_0 /*!< Hysteresis level low */
+#define COMP_Hysteresis_Medium                     COMP_CSR_COMP1HYST_1 /*!< Hysteresis level medium */
+#define COMP_Hysteresis_High                       COMP_CSR_COMP1HYST   /*!< Hysteresis level high */
+
+#define IS_COMP_HYSTERESIS(HYSTERESIS)    (((HYSTERESIS) == COMP_Hysteresis_No) || \
+                                           ((HYSTERESIS) == COMP_Hysteresis_Low) || \
+                                           ((HYSTERESIS) == COMP_Hysteresis_Medium) || \
+                                           ((HYSTERESIS) == COMP_Hysteresis_High))
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Mode
+  * @{
+  */
+/* Please refer to the electrical characteristics in the device datasheet for
+   the power consumption values */
+#define COMP_Mode_HighSpeed                     0x00000000            /*!< High Speed */
+#define COMP_Mode_MediumSpeed                   COMP_CSR_COMP1MODE_0  /*!< Medium Speed */
+#define COMP_Mode_LowPower                      COMP_CSR_COMP1MODE_1 /*!< Low power mode */
+#define COMP_Mode_UltraLowPower                 COMP_CSR_COMP1MODE   /*!< Ultra-low power mode */
+
+#define IS_COMP_MODE(MODE)    (((MODE) == COMP_Mode_UltraLowPower) || \
+                               ((MODE) == COMP_Mode_LowPower)      || \
+                               ((MODE) == COMP_Mode_MediumSpeed)   || \
+                               ((MODE) == COMP_Mode_HighSpeed))
+/**
+  * @}
+  */
+
+/** @defgroup COMP_OutputLevel
+  * @{
+  */ 
+/* When output polarity is not inverted, comparator output is high when
+   the non-inverting input is at a higher voltage than the inverting input */
+#define COMP_OutputLevel_High                   COMP_CSR_COMP1OUT
+/* When output polarity is not inverted, comparator output is low when
+   the non-inverting input is at a lower voltage than the inverting input*/
+#define COMP_OutputLevel_Low                    ((uint32_t)0x00000000)
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/*  Function used to set the COMP configuration to the default reset state ****/
+void COMP_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct);
+void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct);
+void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState);
+void COMP_SwitchCmd(FunctionalState NewState);
+uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection);
+
+/* Window mode control function ***********************************************/
+void COMP_WindowCmd(FunctionalState NewState);
+
+/* COMP configuration locking function ****************************************/
+void COMP_LockConfig(uint32_t COMP_Selection);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F0XX_COMP_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_crc.h b/system/include/stm32f0-stdperiph/stm32f0xx_crc.h

new file mode 100644 (file)

index 0000000..3b235e6
--- /dev/null
+++ b/system/include/stm32f0-stdperiph/stm32f0xx_crc.h
@@ -0,0 +1,122 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_crc.h
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file contains all the functions prototypes for the CRC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_CRC_H
+#define __STM32F0XX_CRC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*!< Includes ----------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup CRC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CRC_ReverseInputData
+  * @{
+  */
+#define CRC_ReverseInputData_No             ((uint32_t)0x00000000) /*!< No reverse operation of Input Data */
+#define CRC_ReverseInputData_8bits          CRC_CR_REV_IN_0        /*!< Reverse operation of Input Data on 8 bits */
+#define CRC_ReverseInputData_16bits         CRC_CR_REV_IN_1        /*!< Reverse operation of Input Data on 16 bits */
+#define CRC_ReverseInputData_32bits         CRC_CR_REV_IN          /*!< Reverse operation of Input Data on 32 bits */
+
+#define IS_CRC_REVERSE_INPUT_DATA(DATA) (((DATA) == CRC_ReverseInputData_No)     || \
+                                         ((DATA) == CRC_ReverseInputData_8bits)  || \
+                                         ((DATA) == CRC_ReverseInputData_16bits) || \
+                                         ((DATA) == CRC_ReverseInputData_32bits))
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_PolynomialSize
+  * @brief    Only applicable for STM32F042 and STM32F072 devices 
+  * @{
+  */
+#define CRC_PolSize_7                       CRC_CR_POLSIZE        /*!< 7-bit polynomial for CRC calculation */
+#define CRC_PolSize_8                       CRC_CR_POLSIZE_1      /*!< 8-bit polynomial for CRC calculation */
+#define CRC_PolSize_16                      CRC_CR_POLSIZE_0      /*!< 16-bit polynomial for CRC calculation */
+#define CRC_PolSize_32                      ((uint32_t)0x00000000)/*!< 32-bit polynomial for CRC calculation */
+
+#define IS_CRC_POL_SIZE(SIZE) (((SIZE) == CRC_PolSize_7)  || \
+                               ((SIZE) == CRC_PolSize_8)  || \
+                               ((SIZE) == CRC_PolSize_16) || \
+                               ((SIZE) == CRC_PolSize_32))
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Configuration of the CRC computation unit **********************************/
+void CRC_DeInit(void);
+void CRC_ResetDR(void);
+void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize); /*!< Only applicable for STM32F042 and STM32F072 devices */ 
+void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData);
+void CRC_ReverseOutputDataCmd(FunctionalState NewState);
+void CRC_SetInitRegister(uint32_t CRC_InitValue); 
+void CRC_SetPolynomial(uint32_t CRC_Pol); /*!< Only applicable for STM32F042 and STM32F072 devices */
+
+/* CRC computation ************************************************************/
+uint32_t CRC_CalcCRC(uint32_t CRC_Data);
+uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data); /*!< Only applicable for STM32F042 and STM32F072 devices */
+uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data); /*!< Only applicable for STM32F042 and STM32F072 devices */
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t CRC_GetCRC(void);
+
+/* Independent register (IDR) access (write/read) *****************************/
+void CRC_SetIDRegister(uint8_t CRC_IDValue);
+uint8_t CRC_GetIDRegister(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0XX_CRC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_crs.h b/system/include/stm32f0-stdperiph/stm32f0xx_crs.h

new file mode 100644 (file)

index 0000000..d47e865
--- /dev/null
+++ b/system/include/stm32f0-stdperiph/stm32f0xx_crs.h
@@ -0,0 +1,183 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_crs.h
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file contains all the functions prototypes for the CRS firmware 
+  *          library, applicable only for STM32F042 and STM32F072 devices.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_CRS_H
+#define __STM32F0XX_CRS_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*!< Includes ----------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup CRS
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CRS_Interrupt_Sources
+  * @{
+  */
+#define CRS_IT_SYNCOK             CRS_ISR_SYNCOKF    /*!< SYNC event OK */
+#define CRS_IT_SYNCWARN           CRS_ISR_SYNCWARNF  /*!< SYNC warning */
+#define CRS_IT_ERR                CRS_ISR_ERRF       /*!< error */
+#define CRS_IT_ESYNC              CRS_ISR_ESYNCF     /*!< Expected SYNC */
+#define CRS_IT_TRIMOVF            CRS_ISR_TRIMOVF    /*!< Trimming overflow or underflow */
+#define CRS_IT_SYNCERR            CRS_ISR_SYNCERR    /*!< SYNC error */
+#define CRS_IT_SYNCMISS           CRS_ISR_SYNCMISS    /*!< SYNC missed*/
+
+#define IS_CRS_IT(IT) (((IT) == CRS_IT_SYNCOK) || ((IT) == CRS_IT_SYNCWARN) || \
+                       ((IT) == CRS_IT_ERR)  || ((IT) == CRS_IT_ESYNC))
+                       
+#define IS_CRS_GET_IT(IT) (((IT) == CRS_IT_SYNCOK) || ((IT) == CRS_IT_SYNCWARN) || \
+                           ((IT) == CRS_IT_ERR) || ((IT) == CRS_IT_ESYNC) || \
+                           ((IT) == CRS_IT_TRIMOVF) || ((IT) == CRS_IT_SYNCERR) || \
+                           ((IT) == CRS_IT_SYNCMISS))
+
+#define IS_CRS_CLEAR_IT(IT) ((IT) != 0x00)                                         
+
+/**
+  * @}
+  */
+
+/** @defgroup CRS_Flags
+  * @{
+  */
+#define CRS_FLAG_SYNCOK             CRS_ISR_SYNCOKF    /*!< SYNC event OK */
+#define CRS_FLAG_SYNCWARN           CRS_ISR_SYNCWARNF  /*!< SYNC warning */
+#define CRS_FLAG_ERR                CRS_ISR_ERRF       /*!< error */
+#define CRS_FLAG_ESYNC              CRS_ISR_ESYNCF     /*!< Expected SYNC */
+#define CRS_FLAG_TRIMOVF            CRS_ISR_TRIMOVF    /*!< Trimming overflow or underflow */
+#define CRS_FLAG_SYNCERR            CRS_ISR_SYNCERR    /*!< SYNC error */
+#define CRS_FLAG_SYNCMISS           CRS_ISR_SYNCMISS    /*!< SYNC missed*/
+
+#define IS_CRS_FLAG(FLAG) (((FLAG) == CRS_FLAG_SYNCOK) || ((FLAG) == CRS_FLAG_SYNCWARN) || \
+                           ((FLAG) == CRS_FLAG_ERR) || ((FLAG) == CRS_FLAG_ESYNC) || \
+                           ((FLAG) == CRS_FLAG_TRIMOVF) || ((FLAG) == CRS_FLAG_SYNCERR) || \
+                           ((FLAG) == CRS_FLAG_SYNCMISS))
+
+/**
+  * @}
+  */
+  
+/** @defgroup CRS_Synchro_Source
+  * @{
+  */
+#define CRS_SYNCSource_GPIO       ((uint32_t)0x00)        /*!< Synchro Signal soucre GPIO */
+#define CRS_SYNCSource_LSE        CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */
+#define CRS_SYNCSource_USB        CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF */
+
+#define IS_CRS_SYNC_SOURCE(SOURCE) (((SOURCE) == CRS_SYNCSource_GPIO) || \
+                                    ((SOURCE) == CRS_SYNCSource_LSE) ||\
+                                    ((SOURCE) == CRS_SYNCSource_USB))
+/**
+  * @}
+  */
+
+/** @defgroup CRS_SynchroDivider
+  * @{
+  */
+#define CRS_SYNC_Div1        ((uint32_t)0x00)                          /*!< Synchro Signal not divided */
+#define CRS_SYNC_Div2        CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */
+#define CRS_SYNC_Div4        CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */
+#define CRS_SYNC_Div8        (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
+#define CRS_SYNC_Div16       CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
+#define CRS_SYNC_Div32       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
+#define CRS_SYNC_Div64       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
+#define CRS_SYNC_Div128      CRS_CFGR_SYNCDIV                          /*!< Synchro Signal divided by 128 */
+
+#define IS_CRS_SYNC_DIV(DIV) (((DIV) == CRS_SYNC_Div1) || ((DIV) == CRS_SYNC_Div2)   ||\
+                              ((DIV) == CRS_SYNC_Div4) || ((DIV) == CRS_SYNC_Div8)   || \
+                              ((DIV) == CRS_SYNC_Div16) || ((DIV) == CRS_SYNC_Div32) || \
+                              ((DIV) == CRS_SYNC_Div64) || ((DIV) == CRS_SYNC_Div128))
+/**
+  * @}
+  */
+
+/** @defgroup CRS_SynchroPolarity
+  * @{
+  */
+#define CRS_SYNCPolarity_Rising       ((uint32_t)0x00)      /*!< Synchro Active on rising edge */
+#define CRS_SYNCPolarity_Falling      CRS_CFGR_SYNCPOL      /*!< Synchro Active on falling edge */
+
+#define IS_CRS_SYNC_POLARITY(POLARITY) (((POLARITY) == CRS_SYNCPolarity_Rising) || \
+                                    ((POLARITY) == CRS_SYNCPolarity_Falling))
+/**
+  * @}
+  */
+
+
+    
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Configuration of the CRS **********************************/
+void CRS_DeInit(void);
+void CRS_AdjustHSI48CalibrationValue(uint8_t CRS_HSI48CalibrationValue);
+void CRS_FrequencyErrorCounterCmd(FunctionalState NewState);
+void CRS_AutomaticCalibrationCmd(FunctionalState NewState); 
+void CRS_SoftwareSynchronizationGenerate(void);
+void CRS_FrequencyErrorCounterReload(uint32_t CRS_ReloadValue);
+void CRS_FrequencyErrorLimitConfig(uint8_t CRS_ErrorLimitValue);
+void CRS_SynchronizationPrescalerConfig(uint32_t CRS_Prescaler);
+void CRS_SynchronizationSourceConfig(uint32_t CRS_Source);
+void CRS_SynchronizationPolarityConfig(uint32_t CRS_Polarity);
+uint32_t CRS_GetReloadValue(void);
+uint32_t CRS_GetHSI48CalibrationValue(void);
+uint32_t CRS_GetFrequencyErrorValue(void);
+uint32_t CRS_GetFrequencyErrorDirection(void);
+
+/* Interrupts and flags management functions **********************************/
+void CRS_ITConfig(uint32_t CRS_IT, FunctionalState NewState);
+FlagStatus CRS_GetFlagStatus(uint32_t CRS_FLAG);
+void CRS_ClearFlag(uint32_t CRS_FLAG);
+ITStatus CRS_GetITStatus(uint32_t CRS_IT);
+void CRS_ClearITPendingBit(uint32_t CRS_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0XX_CRS_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_dac.h b/system/include/stm32f0-stdperiph/stm32f0xx_dac.h

new file mode 100644 (file)

index 0000000..30ec216
--- /dev/null
+++ b/system/include/stm32f0-stdperiph/stm32f0xx_dac.h
@@ -0,0 +1,312 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_dac.h
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file contains all the functions prototypes for the DAC firmware 
+  *          library, applicable only for STM32F051 and STM32F072 devices.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_DAC_H
+#define __STM32F0XX_DAC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+ 
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DAC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  DAC Init structure definition
+  */
+  
+typedef struct
+{
+  uint32_t DAC_Trigger;                      /*!< Specifies the external trigger for the selected DAC channel.
+                                                  This parameter can be a value of @ref DAC_trigger_selection */
+
+  uint32_t DAC_WaveGeneration;               /*!< Specifies whether DAC channel noise waves or triangle waves
+                                                  are generated, or whether no wave is generated.
+                                                  This parameter can be a value of @ref DAC_wave_generation
+                                                  This parameter is only applicable for STM32F072 devices */
+
+  uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
+                                                  the maximum amplitude triangle generation for the DAC channel. 
+                                                  This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude 
+                                                  This parameter is only applicable for STM32F072 devices */
+
+  uint32_t DAC_OutputBuffer;                 /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+                                                  This parameter can be a value of @ref DAC_output_buffer */
+}DAC_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup DAC_Trigger 
+  * @{
+  */
+  
+#define DAC_Trigger_None                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
+                                                                       has been loaded, and not by external trigger */
+#define DAC_Trigger_T6_TRGO                ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel1 */
+#define DAC_Trigger_T3_TRGO                ((uint32_t)0x0000000C) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel1 */
+#define DAC_Trigger_T7_TRGO                ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel1, 
+                                                                       applicable only for STM32F072 devices */
+#define DAC_Trigger_T15_TRGO               ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel1 */
+#define DAC_Trigger_T2_TRGO                ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel1 */
+#define DAC_Trigger_Ext_IT9                ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channels */
+#define DAC_Trigger_Software               ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channels */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None)     || \
+                                 ((TRIGGER) == DAC_Trigger_T6_TRGO)  || \
+                                 ((TRIGGER) == DAC_Trigger_T7_TRGO)  || \
+                                 ((TRIGGER) == DAC_Trigger_T3_TRGO)  || \
+                                 ((TRIGGER) == DAC_Trigger_T15_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T2_TRGO)  || \
+                                 ((TRIGGER) == DAC_Trigger_Ext_IT9)  || \
+                                 ((TRIGGER) == DAC_Trigger_Software))
+                                 
+/**
+  * @}
+  */
+
+/** @defgroup DAC_wave_generation 
+  * @brief    This parameters are only applicable for STM32F072 devices.
+  * @{
+  */
+
+#define DAC_WaveGeneration_None            ((uint32_t)0x00000000)
+#define DAC_WaveGeneration_Noise           ((uint32_t)0x00000040)
+#define DAC_WaveGeneration_Triangle        ((uint32_t)0x00000080)
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None)  || \
+                                    ((WAVE) == DAC_WaveGeneration_Noise) || \
+                                    ((WAVE) == DAC_WaveGeneration_Triangle))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_lfsrunmask_triangleamplitude   
+  * @brief    These parameters are only applicable for STM32F072 devices.
+  * @{
+  */
+
+#define DAC_LFSRUnmask_Bit0                ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUnmask_Bits1_0             ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits2_0             ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits3_0             ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits4_0             ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits5_0             ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits6_0             ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits7_0             ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits8_0             ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits9_0             ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits10_0            ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits11_0            ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TriangleAmplitude_1            ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TriangleAmplitude_3            ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
+#define DAC_TriangleAmplitude_7            ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
+#define DAC_TriangleAmplitude_15           ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
+#define DAC_TriangleAmplitude_31           ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
+#define DAC_TriangleAmplitude_63           ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
+#define DAC_TriangleAmplitude_127          ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
+#define DAC_TriangleAmplitude_255          ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
+#define DAC_TriangleAmplitude_511          ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
+#define DAC_TriangleAmplitude_1023         ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TriangleAmplitude_2047         ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TriangleAmplitude_4095         ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_1) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_3) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_7) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_15) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_31) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_63) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_127) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_255) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_511) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_1023) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_2047) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_4095))
+/**
+  * @}
+  */                                      
+
+/** @defgroup DAC_OutputBuffer 
+  * @{
+  */
+
+#define DAC_OutputBuffer_Enable            ((uint32_t)0x00000000)
+#define DAC_OutputBuffer_Disable           DAC_CR_BOFF1
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
+                                           ((STATE) == DAC_OutputBuffer_Disable))
+/**
+  * @}
+  */
+  
+/** @defgroup DAC_Channel_selection 
+  * @{
+  */
+
+#define DAC_Channel_1                      ((uint32_t)0x00000000)
+#define DAC_Channel_2                      ((uint32_t)0x00000010) /*!< Only applicable for STM32F072 devices */
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
+                                 ((CHANNEL) == DAC_Channel_2))
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data_alignment
+  * @{
+  */
+
+#define DAC_Align_12b_R                    ((uint32_t)0x00000000)
+#define DAC_Align_12b_L                    ((uint32_t)0x00000004)
+#define DAC_Align_8b_R                     ((uint32_t)0x00000008)
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
+                             ((ALIGN) == DAC_Align_12b_L) || \
+                             ((ALIGN) == DAC_Align_8b_R))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_wave_generation 
+  * @brief    These parameters are only applicable for STM32F072 devices.
+  * @{
+  */
+
+#define DAC_Wave_Noise                     ((uint32_t)0x00000040)
+#define DAC_Wave_Triangle                  ((uint32_t)0x00000080)
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
+                           ((WAVE) == DAC_Wave_Triangle))
+/**
+  * @}
+  */
+  
+/** @defgroup DAC_data 
+  * @{
+  */
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) 
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_interrupts_definition 
+  * @{
+  */ 
+  
+#define DAC_IT_DMAUDR                      DAC_SR_DMAUDR1
+#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) 
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DAC_flags_definition 
+  * @{
+  */ 
+  
+#define DAC_FLAG_DMAUDR                    DAC_SR_DMAUDR1
+  
+#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/*  Function used to set the DAC configuration to the default reset state *****/
+void DAC_DeInit(void);
+
+/*  DAC channels configuration: trigger, output buffer, data format functions */
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); /*!< Only applicable for STM32F072 devices */
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); /*!< Only applicable for STM32F072 devices */ 
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); /*!< Only applicable for STM32F072 devices */
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); /*!< Only applicable for STM32F072 devices */
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
+
+/* DMA management functions ***************************************************/
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F0XX_DAC_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h b/system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h

new file mode 100644 (file)

index 0000000..6efeac8
--- /dev/null
+++ b/system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h
@@ -0,0 +1,107 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_dbgmcu.h
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file contains all the functions prototypes for the DBGMCU firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_DBGMCU_H
+#define __STM32F0XX_DBGMCU_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DBGMCU
+  * @{
+  */ 
+/* Exported types ------------------------------------------------------------*/ 
+/* Exported constants --------------------------------------------------------*/
+
+
+/** @defgroup DBGMCU_Exported_Constants
+  * @{
+  */
+
+#define DBGMCU_STOP                  DBGMCU_CR_DBG_STOP
+#define DBGMCU_STANDBY               DBGMCU_CR_DBG_STANDBY
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF9) == 0x00) && ((PERIPH) != 0x00))
+
+#define DBGMCU_TIM2_STOP             DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< Not applicable for STM32F030 devices */
+#define DBGMCU_TIM3_STOP             DBGMCU_APB1_FZ_DBG_TIM3_STOP
+#define DBGMCU_TIM6_STOP             DBGMCU_APB1_FZ_DBG_TIM6_STOP
+#define DBGMCU_TIM7_STOP             DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< Only applicable for STM32F072 devices */ 
+#define DBGMCU_TIM14_STOP            DBGMCU_APB1_FZ_DBG_TIM14_STOP
+#define DBGMCU_RTC_STOP              DBGMCU_APB1_FZ_DBG_RTC_STOP
+#define DBGMCU_WWDG_STOP             DBGMCU_APB1_FZ_DBG_WWDG_STOP
+#define DBGMCU_IWDG_STOP             DBGMCU_APB1_FZ_DBG_IWDG_STOP
+#define DBGMCU_I2C1_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT
+#define DBGMCU_CAN1_STOP             DBGMCU_APB1_FZ_DBG_CAN1_STOP /*!< Only applicable for STM32F042 and STM32F072 devices */
+#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFDDFE2CC) == 0x00) && ((PERIPH) != 0x00))
+
+#define DBGMCU_TIM1_STOP             DBGMCU_APB2_FZ_DBG_TIM1_STOP
+#define DBGMCU_TIM15_STOP            DBGMCU_APB2_FZ_DBG_TIM15_STOP
+#define DBGMCU_TIM16_STOP            DBGMCU_APB2_FZ_DBG_TIM16_STOP
+#define DBGMCU_TIM17_STOP            DBGMCU_APB2_FZ_DBG_TIM17_STOP
+#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8F7FF) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */ 
+
+/* Device and Revision ID management functions ********************************/ 
+uint32_t DBGMCU_GetREVID(void);
+uint32_t DBGMCU_GetDEVID(void);
+
+/* Peripherals Configuration functions ****************************************/ 
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0XX_DBGMCU_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_dma.h b/system/include/stm32f0-stdperiph/stm32f0xx_dma.h

new file mode 100644 (file)

index 0000000..08c93ea
--- /dev/null
+++ b/system/include/stm32f0-stdperiph/stm32f0xx_dma.h
@@ -0,0 +1,804 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_dma.h
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file contains all the functions prototypes for the DMA firmware
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_DMA_H
+#define __STM32F0XX_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DMA
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  DMA Init structures definition
+  */
+typedef struct
+{
+  uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx.              */
+
+  uint32_t DMA_MemoryBaseAddr;     /*!< Specifies the memory base address for DMAy Channelx.                  */
+
+  uint32_t DMA_DIR;                /*!< Specifies if the peripheral is the source or destination.
+                                        This parameter can be a value of @ref DMA_data_transfer_direction     */
+
+  uint32_t DMA_BufferSize;         /*!< Specifies the buffer size, in data unit, of the specified Channel. 
+                                        The data unit is equal to the configuration set in DMA_PeripheralDataSize
+                                        or DMA_MemoryDataSize members depending in the transfer direction     */
+
+  uint32_t DMA_PeripheralInc;      /*!< Specifies whether the Peripheral address register is incremented or not.
+                                        This parameter can be a value of @ref DMA_peripheral_incremented_mode */
+
+  uint32_t DMA_MemoryInc;          /*!< Specifies whether the memory address register is incremented or not.
+                                        This parameter can be a value of @ref DMA_memory_incremented_mode     */
+
+  uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
+                                        This parameter can be a value of @ref DMA_peripheral_data_size        */
+
+  uint32_t DMA_MemoryDataSize;     /*!< Specifies the Memory data width.
+                                        This parameter can be a value of @ref DMA_memory_data_size            */
+
+  uint32_t DMA_Mode;               /*!< Specifies the operation mode of the DMAy Channelx.
+                                        This parameter can be a value of @ref DMA_circular_normal_mode
+                                        @note: The circular buffer mode cannot be used if the memory-to-memory
+                                              data transfer is configured on the selected Channel */
+
+  uint32_t DMA_Priority;           /*!< Specifies the software priority for the DMAy Channelx.
+                                        This parameter can be a value of @ref DMA_priority_level              */
+
+  uint32_t DMA_M2M;                /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
+                                        This parameter can be a value of @ref DMA_memory_to_memory            */
+}DMA_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants
+  * @{
+  */
+
+#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
+                                   ((PERIPH) == DMA1_Channel2) || \
+                                   ((PERIPH) == DMA1_Channel3) || \
+                                   ((PERIPH) == DMA1_Channel4) || \
+                                   ((PERIPH) == DMA1_Channel5) || \
+                                   ((PERIPH) == DMA1_Channel6) || \
+                                   ((PERIPH) == DMA1_Channel7) || \
+                                   ((PERIPH) == DMA2_Channel1) || \
+                                   ((PERIPH) == DMA2_Channel2) || \
+                                   ((PERIPH) == DMA2_Channel3) || \
+                                   ((PERIPH) == DMA2_Channel4) || \
+                                   ((PERIPH) == DMA2_Channel5))
+
+/** @defgroup DMA_data_transfer_direction 
+  * @{
+  */
+
+#define DMA_DIR_PeripheralSRC              ((uint32_t)0x00000000)
+#define DMA_DIR_PeripheralDST              DMA_CCR_DIR
+
+#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \
+                         ((DIR) == DMA_DIR_PeripheralDST))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_peripheral_incremented_mode 
+  * @{
+  */
+
+#define DMA_PeripheralInc_Disable          ((uint32_t)0x00000000)
+#define DMA_PeripheralInc_Enable           DMA_CCR_PINC
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \
+                                            ((STATE) == DMA_PeripheralInc_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_memory_incremented_mode 
+  * @{
+  */
+
+#define DMA_MemoryInc_Disable              ((uint32_t)0x00000000)
+#define DMA_MemoryInc_Enable               DMA_CCR_MINC
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \
+                                        ((STATE) == DMA_MemoryInc_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_peripheral_data_size 
+  * @{
+  */
+
+#define DMA_PeripheralDataSize_Byte        ((uint32_t)0x00000000)
+#define DMA_PeripheralDataSize_HalfWord    DMA_CCR_PSIZE_0
+#define DMA_PeripheralDataSize_Word        DMA_CCR_PSIZE_1
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
+                                           ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
+                                           ((SIZE) == DMA_PeripheralDataSize_Word))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_memory_data_size 
+  * @{
+  */
+
+#define DMA_MemoryDataSize_Byte            ((uint32_t)0x00000000)
+#define DMA_MemoryDataSize_HalfWord        DMA_CCR_MSIZE_0
+#define DMA_MemoryDataSize_Word            DMA_CCR_MSIZE_1
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
+                                       ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
+                                       ((SIZE) == DMA_MemoryDataSize_Word))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_circular_normal_mode 
+  * @{
+  */
+
+#define DMA_Mode_Normal                    ((uint32_t)0x00000000)
+#define DMA_Mode_Circular                  DMA_CCR_CIRC
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_priority_level 
+  * @{
+  */
+
+#define DMA_Priority_VeryHigh              DMA_CCR_PL
+#define DMA_Priority_High                  DMA_CCR_PL_1
+#define DMA_Priority_Medium                DMA_CCR_PL_0
+#define DMA_Priority_Low                   ((uint32_t)0x00000000)
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
+                                   ((PRIORITY) == DMA_Priority_High) || \
+                                   ((PRIORITY) == DMA_Priority_Medium) || \
+                                   ((PRIORITY) == DMA_Priority_Low))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_memory_to_memory 
+  * @{
+  */
+
+#define DMA_M2M_Disable                    ((uint32_t)0x00000000)
+#define DMA_M2M_Enable                     DMA_CCR_MEM2MEM
+
+#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable))
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Remap_Config 
+  * @{
+  */ 
+#define DMAx_CHANNEL1_RMP                                     0x00000000
+#define DMAx_CHANNEL2_RMP                                     0x10000000
+#define DMAx_CHANNEL3_RMP                                     0x20000000
+#define DMAx_CHANNEL4_RMP                                     0x30000000
+#define DMAx_CHANNEL5_RMP                                     0x40000000
+#define DMAx_CHANNEL6_RMP                                     0x50000000
+#define DMAx_CHANNEL7_RMP                                     0x60000000
+
+
+#define IS_DMA_ALL_LIST(LIST) (((LIST) == DMA1) || \
+                               ((LIST) == DMA2))
+
+/****************** DMA1 remap bit field definition********************/
+/* DMA1 - Channel 1 */
+#define DMA1_CH1_DEFAULT      (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_DEFAULT)       /*!< Default remap position for DMA1 */   
+#define DMA1_CH1_ADC          (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_ADC)       /*!< Remap ADC on DMA1 Channel 1*/   
+#define DMA1_CH1_TIM17_CH1    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */
+#define DMA1_CH1_TIM17_UP     (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_TIM17_UP)  /*!< Remap TIM17 up on DMA1 channel 1 */ 
+#define DMA1_CH1_USART1_RX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 1 */ 
+#define DMA1_CH1_USART2_RX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 1 */ 
+#define DMA1_CH1_USART3_RX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 1 */ 
+#define DMA1_CH1_USART4_RX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 1 */ 
+#define DMA1_CH1_USART5_RX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 1 */ 
+#define DMA1_CH1_USART6_RX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 1 */ 
+#define DMA1_CH1_USART7_RX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 1 */ 
+#define DMA1_CH1_USART8_RX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 1 */ 
+/* DMA1 - Channel 2 */
+#define DMA1_CH2_DEFAULT      (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_DEFAULT)       /*!< Default remap position for DMA1 */   
+#define DMA1_CH2_ADC          (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_ADC)       /*!< Remap ADC on DMA1 channel 2 */  
+#define DMA1_CH2_I2C1_TX      (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_I2C1_TX)   /*!< Remap I2C1 Tx on DMA1 channel 2 */ 
+#define DMA1_CH2_SPI1_RX      (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_SPI_1RX)   /*!< Remap SPI1 Rx on DMA1 channel 2 */ 
+#define DMA1_CH2_TIM1_CH1     (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM1_CH1)  /*!< Remap TIM1 channel 1 on DMA1 channel 2 */
+#define DMA1_CH2_TIM17_CH1    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */
+#define DMA1_CH2_TIM17_UP     (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM17_UP)  /*!< Remap TIM17 up on DMA1 channel 2 */ 
+#define DMA1_CH2_USART1_TX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 2 */ 
+#define DMA1_CH2_USART2_TX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 2 */ 
+#define DMA1_CH2_USART3_TX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 2 */ 
+#define DMA1_CH2_USART4_TX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 2 */ 
+#define DMA1_CH2_USART5_TX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 2 */ 
+#define DMA1_CH2_USART6_TX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 2 */ 
+#define DMA1_CH2_USART7_TX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 2 */ 
+#define DMA1_CH2_USART8_TX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 2 */ 
+/* DMA1 - Channel 3 */
+#define DMA1_CH3_DEFAULT      (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_DEFAULT)       /*!< Default remap position for DMAx */   
+#define DMA1_CH3_TIM6_UP      (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM6_UP)   /*!< Remap TIM6 up on DMA1 channel 3 */ 
+#define DMA1_CH3_DAC_CH1      (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_DAC_CH1)   /*!< Remap DAC Channel 1on DMA1 channel 3 */ 
+#define DMA1_CH3_I2C1_RX      (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_I2C1_RX)   /*!< Remap I2C1 Rx on DMA1 channel 3 */ 
+#define DMA1_CH3_SPI1_TX      (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_SPI1_TX)   /*!< Remap SPI1 Tx on DMA1 channel 3 */ 
+#define DMA1_CH3_TIM1_CH2     (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM1_CH2)  /*!< Remap TIM1 channel 2 on DMA1 channel 3 */
+#define DMA1_CH3_TIM2_CH2     (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM2_CH2)  /*!< Remap TIM2 channel 2 on DMA1 channel 3 */
+#define DMA1_CH3_TIM16_CH1    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */
+#define DMA1_CH3_TIM16_UP     (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM16_UP)  /*!< Remap TIM16 up on DMA1 channel 3 */ 
+#define DMA1_CH3_USART1_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 3 */ 
+#define DMA1_CH3_USART2_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 3 */ 
+#define DMA1_CH3_USART3_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 3 */ 
+#define DMA1_CH3_USART4_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 3 */ 
+#define DMA1_CH3_USART5_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 3 */ 
+#define DMA1_CH3_USART6_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 3 */ 
+#define DMA1_CH3_USART7_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 3 */ 
+#define DMA1_CH3_USART8_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 3 */ 
+/* DMA1 - Channel 4 */
+#define DMA1_CH4_DEFAULT      (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_DEFAULT)       /*!< Default remap position for DMA1 */   
+#define DMA1_CH4_TIM7_UP      (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM7_UP)   /*!< Remap TIM7 up on DMA1 channel 4 */ 
+#define DMA1_CH4_DAC_CH2      (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_DAC_CH2)   /*!< Remap DAC Channel 2 on DMA1 channel 4 */
+#define DMA1_CH4_I2C2_TX      (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_I2C2_TX)   /*!< Remap I2C2 Tx on DMA1 channel 4 */ 
+#define DMA1_CH4_SPI2_RX      (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_SPI2_RX)   /*!< Remap SPI2 Rx on DMA1 channel 4 */ 
+#define DMA1_CH4_TIM2_CH4     (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM2_CH4)  /*!< Remap TIM2 channel 4 on DMA1 channel 4 */
+#define DMA1_CH4_TIM3_CH1     (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM3_CH1)  /*!< Remap TIM3 channel 1 on DMA1 channel 4 */
+#define DMA1_CH4_TIM3_TRIG    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 4 */ 
+#define DMA1_CH4_TIM16_CH1    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */
+#define DMA1_CH4_TIM16_UP     (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM16_UP)  /*!< Remap TIM16 up on DMA1 channel 4 */ 
+#define DMA1_CH4_USART1_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 4 */ 
+#define DMA1_CH4_USART2_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 4 */ 
+#define DMA1_CH4_USART3_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 4 */ 
+#define DMA1_CH4_USART4_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 4 */ 
+#define DMA1_CH4_USART5_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 4 */ 
+#define DMA1_CH4_USART6_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 4 */ 
+#define DMA1_CH4_USART7_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 4 */ 
+#define DMA1_CH4_USART8_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 4 */ 
+/* DMA1 - Channel 5 */
+#define DMA1_CH5_DEFAULT      (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_DEFAULT)       /*!< Default remap position for DMA1 */   
+#define DMA1_CH5_I2C2_RX      (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_I2C2_RX)   /*!< Remap I2C2 Rx on DMA1 channel 5 */ 
+#define DMA1_CH5_SPI2_TX      (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_SPI2_TX)   /*!< Remap SPI1 Tx on DMA1 channel 5 */ 
+#define DMA1_CH5_TIM1_CH3     (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_TIM1_CH3)  /*!< Remap TIM1 channel 3 on DMA1 channel 5 */
+#define DMA1_CH5_USART1_RX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 5 */ 
+#define DMA1_CH5_USART2_RX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 5 */ 
+#define DMA1_CH5_USART3_RX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 5 */ 
+#define DMA1_CH5_USART4_RX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 5 */ 
+#define DMA1_CH5_USART5_RX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 5 */ 
+#define DMA1_CH5_USART6_RX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 5 */ 
+#define DMA1_CH5_USART7_RX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 5 */ 
+#define DMA1_CH5_USART8_RX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 5 */ 
+/* DMA1 - Channel 6 */
+#define DMA1_CH6_DEFAULT      (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_DEFAULT)       /*!< Default remap position for DMA1 */   
+#define DMA1_CH6_I2C1_TX      (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_I2C1_TX)   /*!< Remap I2C1 Tx on DMA1 channel 6 */ 
+#define DMA1_CH6_SPI2_RX      (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_SPI2_RX)   /*!< Remap SPI2 Rx on DMA1 channel 6 */ 
+#define DMA1_CH6_TIM1_CH1     (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH1)  /*!< Remap TIM1 channel 1 on DMA1 channel 6 */
+#define DMA1_CH6_TIM1_CH2     (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH2)  /*!< Remap TIM1 channel 2 on DMA1 channel 6 */
+#define DMA1_CH6_TIM1_CH3     (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH3)  /*!< Remap TIM1 channel 3 on DMA1 channel 6 */
+#define DMA1_CH6_TIM3_CH1     (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM3_CH1)  /*!< Remap TIM3 channel 1 on DMA1 channel 6 */
+#define DMA1_CH6_TIM3_TRIG    (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 6 */ 
+#define DMA1_CH6_TIM16_CH1    (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */
+#define DMA1_CH6_TIM16_UP     (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM16_UP)  /*!< Remap TIM16 up on DMA1 channel 6 */ 
+#define DMA1_CH6_USART1_RX    (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 6 */ 
+#define DMA1_CH6_USART2_RX    (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 6 */ 
+#define DMA1_CH6_USART3_RX    (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 6 */ 
+#define DMA1_CH6_USART4_RX    (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 6 */ 
+#define DMA1_CH6_USART5_RX    (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 6 */ 
+#define DMA1_CH6_USART6_RX    (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 6 */ 
+#define DMA1_CH6_USART7_RX    (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 6 */ 
+#define DMA1_CH6_USART8_RX    (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 6 */ 
+/* DMA1 - Channel 7 */
+#define DMA1_CH7_DEFAULT      (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_DEFAULT)       /*!< Default remap position for DMA1 */   
+#define DMA1_CH7_I2C1_RX      (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_I2C1_RX)   /*!< Remap I2C1 Rx on DMA1 channel 7 */ 
+#define DMA1_CH7_SPI2_TX      (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_SPI2_TX)   /*!< Remap SPI2 Tx on DMA1 channel 7 */ 
+#define DMA1_CH7_TIM2_CH2     (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM2_CH2)  /*!< Remap TIM2 channel 2 on DMA1 channel 7 */
+#define DMA1_CH7_TIM2_CH4     (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM2_CH4)  /*!< Remap TIM2 channel 4 on DMA1 channel 7 */
+#define DMA1_CH7_TIM17_CH1    (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */
+#define DMA1_CH7_TIM17_UP     (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM17_UP)  /*!< Remap TIM17 up on DMA1 channel 7 */ 
+#define DMA1_CH7_USART1_TX    (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 7 */ 
+#define DMA1_CH7_USART2_TX    (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 7 */ 
+#define DMA1_CH7_USART3_TX    (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 7 */ 
+#define DMA1_CH7_USART4_TX    (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 7 */ 
+#define DMA1_CH7_USART5_TX    (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 7 */ 
+#define DMA1_CH7_USART6_TX    (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 7 */ 
+#define DMA1_CH7_USART7_TX    (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 7 */ 
+#define DMA1_CH7_USART8_TX    (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 7 */
+
+#define IS_DMA1_REMAP(REMAP)  ((REMAP == DMA1_CH1_DEFAULT)   ||\
+                                    (REMAP == DMA1_CH1_ADC)       ||\
+                                    (REMAP == DMA1_CH1_TIM17_CH1) ||\
+                                    (REMAP == DMA1_CH1_TIM17_UP)  ||\
+                                    (REMAP == DMA1_CH1_USART1_RX) ||\
+                                    (REMAP == DMA1_CH1_USART2_RX) ||\
+                                    (REMAP == DMA1_CH1_USART3_RX) ||\
+                                    (REMAP == DMA1_CH1_USART4_RX) ||\
+                                    (REMAP == DMA1_CH1_USART5_RX) ||\
+                                    (REMAP == DMA1_CH1_USART6_RX) ||\
+                                    (REMAP == DMA1_CH1_USART7_RX) ||\
+                                    (REMAP == DMA1_CH1_USART8_RX) ||\
+                                    (REMAP == DMA1_CH2_DEFAULT)   ||\
+                                    (REMAP == DMA1_CH2_ADC)       ||\
+                                    (REMAP == DMA1_CH2_I2C1_TX)   ||\
+                                    (REMAP == DMA1_CH2_SPI1_RX)   ||\
+                                    (REMAP == DMA1_CH2_TIM1_CH1)  ||\
+                                    (REMAP == DMA1_CH2_I2C1_TX)   ||\
+                                    (REMAP == DMA1_CH2_TIM17_CH1) ||\
+                                    (REMAP == DMA1_CH2_TIM17_UP)  ||\
+                                    (REMAP == DMA1_CH2_USART1_TX) ||\
+                                    (REMAP == DMA1_CH2_USART2_TX) ||\
+                                    (REMAP == DMA1_CH2_USART3_TX) ||\
+                                    (REMAP == DMA1_CH2_USART4_TX) ||\
+                                    (REMAP == DMA1_CH2_USART5_TX) ||\
+                                    (REMAP == DMA1_CH2_USART6_TX) ||\
+                                    (REMAP == DMA1_CH2_USART7_TX) ||\
+                                    (REMAP == DMA1_CH2_USART8_TX) ||\
+                                    (REMAP == DMA1_CH3_DEFAULT)   ||\
+                                    (REMAP == DMA1_CH3_TIM6_UP)   ||\
+                                    (REMAP == DMA1_CH3_DAC_CH1)   ||\
+                                    (REMAP == DMA1_CH3_I2C1_RX)   ||\
+                                    (REMAP == DMA1_CH3_SPI1_TX)   ||\
+                                    (REMAP == DMA1_CH3_TIM1_CH2)  ||\
+                                    (REMAP == DMA1_CH3_TIM2_CH2)  ||\
+                                    (REMAP == DMA1_CH3_TIM16_CH1) ||\
+                                    (REMAP == DMA1_CH3_TIM16_UP)  ||\
+                                    (REMAP == DMA1_CH3_USART1_RX) ||\
+                                    (REMAP == DMA1_CH3_USART2_RX) ||\
+                                    (REMAP == DMA1_CH3_USART3_RX) ||\
+                                    (REMAP == DMA1_CH3_USART4_RX) ||\
+                                    (REMAP == DMA1_CH3_USART5_RX) ||\
+                                    (REMAP == DMA1_CH3_USART6_RX) ||\
+                                    (REMAP == DMA1_CH3_USART7_RX) ||\
+                                    (REMAP == DMA1_CH3_USART8_RX) ||\
+                                    (REMAP == DMA1_CH4_DEFAULT)   ||\
+                                    (REMAP == DMA1_CH4_TIM7_UP)   ||\
+                                    (REMAP == DMA1_CH4_DAC_CH2)   ||\
+                                    (REMAP == DMA1_CH4_I2C2_TX)   ||\
+                                    (REMAP == DMA1_CH4_SPI2_RX)   ||\
+                                    (REMAP == DMA1_CH4_TIM2_CH4)  ||\
+                                    (REMAP == DMA1_CH4_TIM3_CH1)  ||\
+                                    (REMAP == DMA1_CH4_TIM3_TRIG) ||\
+                                    (REMAP == DMA1_CH4_TIM16_CH1) ||\
+                                    (REMAP == DMA1_CH4_TIM16_UP)  ||\
+                                    (REMAP == DMA1_CH4_USART1_TX) ||\
+                                    (REMAP == DMA1_CH4_USART2_TX) ||\
+                                    (REMAP == DMA1_CH4_USART3_TX) ||\
+                                    (REMAP == DMA1_CH4_USART4_TX) ||\
+                                    (REMAP == DMA1_CH4_USART5_TX) ||\
+                                    (REMAP == DMA1_CH4_USART6_TX) ||\
+                                    (REMAP == DMA1_CH4_USART7_TX) ||\
+                                    (REMAP == DMA1_CH4_USART8_TX) ||\
+                                    (REMAP == DMA1_CH5_DEFAULT)   ||\
+                                    (REMAP == DMA1_CH5_I2C2_RX)   ||\
+                                    (REMAP == DMA1_CH5_SPI2_TX)   ||\
+                                    (REMAP == DMA1_CH5_TIM1_CH3)  ||\
+                                    (REMAP == DMA1_CH5_USART1_RX) ||\
+                                    (REMAP == DMA1_CH5_USART2_RX) ||\
+                                    (REMAP == DMA1_CH5_USART3_RX) ||\
+                                    (REMAP == DMA1_CH5_USART4_RX) ||\
+                                    (REMAP == DMA1_CH5_USART5_RX) ||\
+                                    (REMAP == DMA1_CH5_USART6_RX) ||\
+                                    (REMAP == DMA1_CH5_USART7_RX) ||\
+                                    (REMAP == DMA1_CH5_USART8_RX) ||\
+                                    (REMAP == DMA1_CH6_DEFAULT)   ||\
+                                    (REMAP == DMA1_CH6_I2C1_TX)   ||\
+                                    (REMAP == DMA1_CH6_SPI2_RX)   ||\
+                                    (REMAP == DMA1_CH6_TIM1_CH1)  ||\
+                                    (REMAP == DMA1_CH6_TIM1_CH2)  ||\
+                                    (REMAP == DMA1_CH6_TIM1_CH3)  ||\
+                                    (REMAP == DMA1_CH6_TIM3_CH1)  ||\
+                                    (REMAP == DMA1_CH6_TIM3_TRIG) ||\
+                                    (REMAP == DMA1_CH6_TIM16_CH1) ||\
+                                    (REMAP == DMA1_CH6_TIM16_UP)  ||\
+                                    (REMAP == DMA1_CH6_USART1_RX) ||\
+                                    (REMAP == DMA1_CH6_USART2_RX) ||\
+                                    (REMAP == DMA1_CH6_USART3_RX) ||\
+                                    (REMAP == DMA1_CH6_USART4_RX) ||\
+                                    (REMAP == DMA1_CH6_USART5_RX) ||\
+                                    (REMAP == DMA1_CH6_USART6_RX) ||\
+                                    (REMAP == DMA1_CH6_USART7_RX) ||\
+                                    (REMAP == DMA1_CH6_USART8_RX) ||\
+                                    (REMAP == DMA1_CH7_DEFAULT)   ||\
+                                    (REMAP == DMA1_CH7_I2C1_RX)   ||\
+                                    (REMAP == DMA1_CH7_SPI2_TX)   ||\
+                                    (REMAP == DMA1_CH7_TIM2_CH2)  ||\
+                                    (REMAP == DMA1_CH7_TIM2_CH4)  ||\
+                                    (REMAP == DMA1_CH7_TIM17_CH1) ||\
+                                    (REMAP == DMA1_CH7_TIM17_UP)  ||\
+                                    (REMAP == DMA1_CH7_USART1_TX) ||\
+                                    (REMAP == DMA1_CH7_USART2_TX) ||\
+                                    (REMAP == DMA1_CH7_USART3_TX) ||\
+                                    (REMAP == DMA1_CH7_USART4_TX) ||\
+                                    (REMAP == DMA1_CH7_USART5_TX) ||\
+                                    (REMAP == DMA1_CH7_USART6_TX) ||\
+                                    (REMAP == DMA1_CH7_USART7_TX) ||\
+                                    (REMAP == DMA1_CH7_USART8_TX))
+
+/****************** DMA2 remap bit field definition********************/
+/* DMA2 - Channel 1 */
+#define DMA2_CH1_DEFAULT      (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_DEFAULT)       /*!< Default remap position for DMA2 */   
+#define DMA2_CH1_I2C2_TX      (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_I2C2_TX)   /*!< Remap I2C2 TX on DMA2 channel 1 */ 
+#define DMA2_CH1_USART1_TX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 1 */ 
+#define DMA2_CH1_USART2_TX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 1 */ 
+#define DMA2_CH1_USART3_TX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 1 */ 
+#define DMA2_CH1_USART4_TX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 1 */ 
+#define DMA2_CH1_USART5_TX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 1 */ 
+#define DMA2_CH1_USART6_TX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 1 */ 
+#define DMA2_CH1_USART7_TX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 1 */ 
+#define DMA2_CH1_USART8_TX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 1 */ 
+/* DMA2 - Channel 2 */
+#define DMA2_CH2_DEFAULT      (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_DEFAULT)       /*!< Default remap position for DMA2 */   
+#define DMA2_CH2_I2C2_RX      (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_I2C2_RX)   /*!< Remap I2C2 Rx on DMA2 channel 2 */ 
+#define DMA2_CH2_USART1_RX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 2 */ 
+#define DMA2_CH2_USART2_RX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 2 */ 
+#define DMA2_CH2_USART3_RX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 2 */ 
+#define DMA2_CH2_USART4_RX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 2 */ 
+#define DMA2_CH2_USART5_RX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 2 */ 
+#define DMA2_CH2_USART6_RX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 2 */ 
+#define DMA2_CH2_USART7_RX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 2 */ 
+#define DMA2_CH2_USART8_RX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 2 */ 
+/* DMA2 - Channel 3 */
+#define DMA2_CH3_DEFAULT      (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_DEFAULT)       /*!< Default remap position for DMA2 */   
+#define DMA2_CH3_TIM6_UP      (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_TIM6_UP)   /*!< Remap TIM6 up on DMA2 channel 3 */ 
+#define DMA2_CH3_DAC_CH1      (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_DAC_CH1)   /*!< Remap DAC channel 1 on DMA2 channel 3 */
+#define DMA2_CH3_SPI1_RX      (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_SPI1_RX)   /*!< Remap SPI1 Rx on DMA2 channel 3 */ 
+#define DMA2_CH3_USART1_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 3 */ 
+#define DMA2_CH3_USART2_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 3 */ 
+#define DMA2_CH3_USART3_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 3 */ 
+#define DMA2_CH3_USART4_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 3 */ 
+#define DMA2_CH3_USART5_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 3 */ 
+#define DMA2_CH3_USART6_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 3 */ 
+#define DMA2_CH3_USART7_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 3 */ 
+#define DMA2_CH3_USART8_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 3 */ 
+/* DMA2 - Channel 4 */
+#define DMA2_CH4_DEFAULT      (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_DEFAULT)       /*!< Default remap position for DMA2 */   
+#define DMA2_CH4_TIM7_UP      (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_TIM7_UP)   /*!< Remap TIM7 up on DMA2 channel 4 */ 
+#define DMA2_CH4_DAC_CH2      (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_DAC_CH2)   /*!< Remap DAC channel 2 on DMA2 channel 4 */
+#define DMA2_CH4_SPI1_TX      (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_SPI1_TX)   /*!< Remap SPI1 Tx on DMA2 channel 4 */ 
+#define DMA2_CH4_USART1_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 4 */ 
+#define DMA2_CH4_USART2_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 4 */ 
+#define DMA2_CH4_USART3_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 4 */ 
+#define DMA2_CH4_USART4_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 4 */ 
+#define DMA2_CH4_USART5_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 4 */ 
+#define DMA2_CH4_USART6_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 4 */ 
+#define DMA2_CH4_USART7_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 4 */ 
+#define DMA2_CH4_USART8_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 4 */ 
+/* DMA2 - Channel 5 */
+#define DMA2_CH5_DEFAULT      (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_DEFAULT)       /*!< Default remap position for DMA2 */   
+#define DMA2_CH5_ADC          (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_ADC)       /*!< Remap ADC on DMA2 channel 5 */  
+#define DMA2_CH5_USART1_TX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 5 */ 
+#define DMA2_CH5_USART2_TX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 5 */ 
+#define DMA2_CH5_USART3_TX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 5 */ 
+#define DMA2_CH5_USART4_TX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 5 */ 
+#define DMA2_CH5_USART5_TX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 5 */ 
+#define DMA2_CH5_USART6_TX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 5 */ 
+#define DMA2_CH5_USART7_TX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 5 */ 
+#define DMA2_CH5_USART8_TX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 5 */ 
+
+#define IS_DMA2_REMAP(REMAP)  ((REMAP == DMA2_CH1_DEFAULT)   ||\
+                                    (REMAP == DMA2_CH1_I2C2_TX)   ||\
+                                    (REMAP == DMA2_CH1_USART1_TX) ||\
+                                    (REMAP == DMA2_CH1_USART2_TX) ||\
+                                    (REMAP == DMA2_CH1_USART3_TX) ||\
+                                    (REMAP == DMA2_CH1_USART4_TX) ||\
+                                    (REMAP == DMA2_CH1_USART5_TX) ||\
+                                    (REMAP == DMA2_CH1_USART6_TX) ||\
+                                    (REMAP == DMA2_CH1_USART7_TX) ||\
+                                    (REMAP == DMA2_CH1_USART8_TX) ||\
+                                    (REMAP == DMA2_CH2_DEFAULT)   ||\
+                                    (REMAP == DMA2_CH2_I2C2_RX)   ||\
+                                    (REMAP == DMA2_CH2_USART1_RX) ||\
+                                    (REMAP == DMA2_CH2_USART2_RX) ||\
+                                    (REMAP == DMA2_CH2_USART3_RX) ||\
+                                    (REMAP == DMA2_CH2_USART4_RX) ||\
+                                    (REMAP == DMA2_CH2_USART5_RX) ||\
+                                    (REMAP == DMA2_CH2_USART6_RX) ||\
+                                    (REMAP == DMA2_CH2_USART7_RX) ||\
+                                    (REMAP == DMA2_CH2_USART8_RX) ||\
+                                    (REMAP == DMA2_CH3_DEFAULT)   ||\
+                                    (REMAP == DMA2_CH3_TIM6_UP)   ||\
+                                    (REMAP == DMA2_CH3_DAC_CH1)   ||\
+                                    (REMAP == DMA2_CH3_SPI1_RX)   ||\
+                                    (REMAP == DMA2_CH3_USART1_RX) ||\
+                                    (REMAP == DMA2_CH3_USART2_RX) ||\
+                                    (REMAP == DMA2_CH3_USART3_RX) ||\
+                                    (REMAP == DMA2_CH3_USART4_RX) ||\
+                                    (REMAP == DMA2_CH3_USART5_RX) ||\
+                                    (REMAP == DMA2_CH3_USART6_RX) ||\
+                                    (REMAP == DMA2_CH3_USART7_RX) ||\
+                                    (REMAP == DMA2_CH3_USART8_RX) ||\
+                                    (REMAP == DMA2_CH4_DEFAULT)   ||\
+                                    (REMAP == DMA2_CH4_TIM7_UP)   ||\
+                                    (REMAP == DMA2_CH4_DAC_CH2)   ||\
+                                    (REMAP == DMA2_CH4_SPI1_TX)   ||\
+                                    (REMAP == DMA2_CH4_USART1_TX) ||\
+                                    (REMAP == DMA2_CH4_USART2_TX) ||\
+                                    (REMAP == DMA2_CH4_USART3_TX) ||\
+                                    (REMAP == DMA2_CH4_USART4_TX) ||\
+                                    (REMAP == DMA2_CH4_USART5_TX) ||\
+                                    (REMAP == DMA2_CH4_USART6_TX) ||\
+                                    (REMAP == DMA2_CH4_USART7_TX) ||\
+                                    (REMAP == DMA2_CH4_USART8_TX) ||\
+                                    (REMAP == DMA2_CH5_DEFAULT)   ||\
+                                    (REMAP == DMA2_CH5_ADC)       ||\
+                                    (REMAP == DMA2_CH5_USART1_TX) ||\
+                                    (REMAP == DMA2_CH5_USART2_TX) ||\
+                                    (REMAP == DMA2_CH5_USART3_TX) ||\
+                                    (REMAP == DMA2_CH5_USART4_TX) ||\
+                                    (REMAP == DMA2_CH5_USART5_TX) ||\
+                                    (REMAP == DMA2_CH5_USART6_TX) ||\
+                                    (REMAP == DMA2_CH5_USART7_TX) ||\
+                                    (REMAP == DMA2_CH5_USART8_TX ))
+
+/**
+  * @}
+  */
+  
+/** @defgroup DMA_interrupts_definition
+  * @{
+  */
+
+#define DMA_IT_TC                          DMA_CCR_TCIE
+#define DMA_IT_HT                          DMA_CCR_HTIE
+#define DMA_IT_TE                          DMA_CCR_TEIE
+
+#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
+
+#define DMA1_IT_GL1                        DMA_ISR_GIF1
+#define DMA1_IT_TC1                        DMA_ISR_TCIF1
+#define DMA1_IT_HT1                        DMA_ISR_HTIF1
+#define DMA1_IT_TE1                        DMA_ISR_TEIF1
+#define DMA1_IT_GL2                        DMA_ISR_GIF2
+#define DMA1_IT_TC2                        DMA_ISR_TCIF2
+#define DMA1_IT_HT2                        DMA_ISR_HTIF2
+#define DMA1_IT_TE2                        DMA_ISR_TEIF2
+#define DMA1_IT_GL3                        DMA_ISR_GIF3
+#define DMA1_IT_TC3                        DMA_ISR_TCIF3
+#define DMA1_IT_HT3                        DMA_ISR_HTIF3
+#define DMA1_IT_TE3                        DMA_ISR_TEIF3
+#define DMA1_IT_GL4                        DMA_ISR_GIF4
+#define DMA1_IT_TC4                        DMA_ISR_TCIF4
+#define DMA1_IT_HT4                        DMA_ISR_HTIF4
+#define DMA1_IT_TE4                        DMA_ISR_TEIF4
+#define DMA1_IT_GL5                        DMA_ISR_GIF5
+#define DMA1_IT_TC5                        DMA_ISR_TCIF5
+#define DMA1_IT_HT5                        DMA_ISR_HTIF5
+#define DMA1_IT_TE5                        DMA_ISR_TEIF5
+#define DMA1_IT_GL6                        DMA_ISR_GIF6   /*!< Only applicable for STM32F072 and STM32F091 devices */
+#define DMA1_IT_TC6                        DMA_ISR_TCIF6  /*!< Only applicable for STM32F072 and STM32F091 devices */
+#define DMA1_IT_HT6                        DMA_ISR_HTIF6  /*!< Only applicable for STM32F072 and STM32F091 devices */
+#define DMA1_IT_TE6                        DMA_ISR_TEIF6  /*!< Only applicable for STM32F072 and STM32F091 devices */
+#define DMA1_IT_GL7                        DMA_ISR_GIF7   /*!< Only applicable for STM32F072 and STM32F091 devices */
+#define DMA1_IT_TC7                        DMA_ISR_TCIF7  /*!< Only applicable for STM32F072 and STM32F091 devices */
+#define DMA1_IT_HT7                        DMA_ISR_HTIF7  /*!< Only applicable for STM32F072 and STM32F091 devices */
+#define DMA1_IT_TE7                        DMA_ISR_TEIF7  /*!< Only applicable for STM32F072 and STM32F091 devices */
+
+#define DMA2_IT_GL1                        ((uint32_t)0x10000001)  /*!< Only applicable for STM32F091 devices */
+#define DMA2_IT_TC1                        ((uint32_t)0x10000002)  /*!< Only applicable for STM32F091 devices */
+#define DMA2_IT_HT1                        ((uint32_t)0x10000004)  /*!< Only applicable for STM32F091 devices */
+#define DMA2_IT_TE1                        ((uint32_t)0x10000008)  /*!< Only applicable for STM32F091 devices */
+#define DMA2_IT_GL2                        ((uint32_t)0x10000010)  /*!< Only applicable for STM32F091 devices */
+#define DMA2_IT_TC2                        ((uint32_t)0x10000020)  /*!< Only applicable for STM32F091 devices */
+#define DMA2_IT_HT2                        ((uint32_t)0x10000040)  /*!< Only applicable for STM32F091 devices */
+#define DMA2_IT_TE2                        ((uint32_t)0x10000080)  /*!< Only applicable for STM32F091 devices */
+#define DMA2_IT_GL3                        ((uint32_t)0x10000100)  /*!< Only applicable for STM32F091 devices */
+#define DMA2_IT_TC3                        ((uint32_t)0x10000200)  /*!< Only applicable for STM32F091 devices */
+#define DMA2_IT_HT3                        ((uint32_t)0x10000400)  /*!< Only applicable for STM32F091 devices */
+#define DMA2_IT_TE3                        ((uint32_t)0x10000800)  /*!< Only applicable for STM32F091 devices */
+#define DMA2_IT_GL4                        ((uint32_t)0x10001000)  /*!< Only applicable for STM32F091 devices */
+#define DMA2_IT_TC4                        ((uint32_t)0x10002000)  /*!< Only applicable for STM32F091 devices */
+#define DMA2_IT_HT4                        ((uint32_t)0x10004000)  /*!< Only applicable for STM32F091 devices */
+#define DMA2_IT_TE4                        ((uint32_t)0x10008000)  /*!< Only applicable for STM32F091 devices */
+#define DMA2_IT_GL5                        ((uint32_t)0x10010000)  /*!< Only applicable for STM32F091 devices */
+#define DMA2_IT_TC5                        ((uint32_t)0x10020000)  /*!< Only applicable for STM32F091 devices */
+#define DMA2_IT_HT5                        ((uint32_t)0x10040000)  /*!< Only applicable for STM32F091 devices */
+#define DMA2_IT_TE5                        ((uint32_t)0x10080000)  /*!< Only applicable for STM32F091 devices */
+
+#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
+
+#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
+                           ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
+                           ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
+                           ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
+                           ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
+                           ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
+                           ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
+                           ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
+                           ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
+                           ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
+                           ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
+                           ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
+                           ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
+                           ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
+                           ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
+                           ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
+                           ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
+                           ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
+                           ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
+                           ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
+                           ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
+                           ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
+                           ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
+                           ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_flags_definition 
+  * @{
+  */
+#define DMA1_FLAG_GL1                      DMA_ISR_GIF1
+#define DMA1_FLAG_TC1                      DMA_ISR_TCIF1
+#define DMA1_FLAG_HT1                      DMA_ISR_HTIF1
+#define DMA1_FLAG_TE1                      DMA_ISR_TEIF1
+#define DMA1_FLAG_GL2                      DMA_ISR_GIF2
+#define DMA1_FLAG_TC2                      DMA_ISR_TCIF2
+#define DMA1_FLAG_HT2                      DMA_ISR_HTIF2
+#define DMA1_FLAG_TE2                      DMA_ISR_TEIF2
+#define DMA1_FLAG_GL3                      DMA_ISR_GIF3
+#define DMA1_FLAG_TC3                      DMA_ISR_TCIF3
+#define DMA1_FLAG_HT3                      DMA_ISR_HTIF3
+#define DMA1_FLAG_TE3                      DMA_ISR_TEIF3
+#define DMA1_FLAG_GL4                      DMA_ISR_GIF4
+#define DMA1_FLAG_TC4                      DMA_ISR_TCIF4
+#define DMA1_FLAG_HT4                      DMA_ISR_HTIF4
+#define DMA1_FLAG_TE4                      DMA_ISR_TEIF4
+#define DMA1_FLAG_GL5                      DMA_ISR_GIF5
+#define DMA1_FLAG_TC5                      DMA_ISR_TCIF5
+#define DMA1_FLAG_HT5                      DMA_ISR_HTIF5
+#define DMA1_FLAG_TE5                      DMA_ISR_TEIF5
+#define DMA1_FLAG_GL6                      DMA_ISR_GIF6   /*!< Only applicable for STM32F072 and STM32F091 devices */
+#define DMA1_FLAG_TC6                      DMA_ISR_TCIF6  /*!< Only applicable for STM32F072 and STM32F091 devices */
+#define DMA1_FLAG_HT6                      DMA_ISR_HTIF6  /*!< Only applicable for STM32F072 and STM32F091 devices */
+#define DMA1_FLAG_TE6                      DMA_ISR_TEIF6  /*!< Only applicable for STM32F072 and STM32F091 devices */
+#define DMA1_FLAG_GL7                      DMA_ISR_GIF7   /*!< Only applicable for STM32F072 and STM32F091 devices */
+#define DMA1_FLAG_TC7                      DMA_ISR_TCIF7  /*!< Only applicable for STM32F072 and STM32F091 devices */
+#define DMA1_FLAG_HT7                      DMA_ISR_HTIF7  /*!< Only applicable for STM32F072 and STM32F091 devices */
+#define DMA1_FLAG_TE7                      DMA_ISR_TEIF7  /*!< Only applicable for STM32F072 and STM32F091 devices */
+
+#define DMA2_FLAG_GL1                      ((uint32_t)0x10000001)
+#define DMA2_FLAG_TC1                      ((uint32_t)0x10000002)
+#define DMA2_FLAG_HT1                      ((uint32_t)0x10000004)
+#define DMA2_FLAG_TE1                      ((uint32_t)0x10000008)
+#define DMA2_FLAG_GL2                      ((uint32_t)0x10000010)
+#define DMA2_FLAG_TC2                      ((uint32_t)0x10000020)
+#define DMA2_FLAG_HT2                      ((uint32_t)0x10000040)
+#define DMA2_FLAG_TE2                      ((uint32_t)0x10000080)
+#define DMA2_FLAG_GL3                      ((uint32_t)0x10000100)
+#define DMA2_FLAG_TC3                      ((uint32_t)0x10000200)
+#define DMA2_FLAG_HT3                      ((uint32_t)0x10000400)
+#define DMA2_FLAG_TE3                      ((uint32_t)0x10000800)
+#define DMA2_FLAG_GL4                      ((uint32_t)0x10001000)
+#define DMA2_FLAG_TC4                      ((uint32_t)0x10002000)
+#define DMA2_FLAG_HT4                      ((uint32_t)0x10004000)
+#define DMA2_FLAG_TE4                      ((uint32_t)0x10008000)
+#define DMA2_FLAG_GL5                      ((uint32_t)0x10010000)
+#define DMA2_FLAG_TC5                      ((uint32_t)0x10020000)
+#define DMA2_FLAG_HT5                      ((uint32_t)0x10040000)
+#define DMA2_FLAG_TE5                      ((uint32_t)0x10080000)
+
+#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
+
+#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
+                               ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
+                               ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
+                               ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
+                               ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
+                               ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
+                               ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
+                               ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
+                               ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
+                               ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
+                               ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
+                               ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
+                               ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
+                               ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
+                               ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
+                               ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
+                               ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
+                               ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
+                               ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
+                               ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
+                               ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
+                               ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
+                               ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
+                               ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Buffer_Size 
+  * @{
+  */
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the DMA configuration to the default reset state ******/
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
+
+/* Initialization and Configuration functions *********************************/
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
+void DMA_RemapConfig(DMA_TypeDef* DMAy, uint32_t DMAx_CHy_RemapRequest);
+
+/* Data Counter functions******************************************************/ 
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
+
+/* Interrupts and flags management functions **********************************/
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
+void DMA_ClearFlag(uint32_t DMAy_FLAG);
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
+void DMA_ClearITPendingBit(uint32_t DMAy_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F0XX_DMA_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_exti.h b/system/include/stm32f0-stdperiph/stm32f0xx_exti.h

new file mode 100644 (file)

index 0000000..beeac72
--- /dev/null
+++ b/system/include/stm32f0-stdperiph/stm32f0xx_exti.h
@@ -0,0 +1,216 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_exti.h
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file contains all the functions prototypes for the EXTI 
+  *          firmware library
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_EXTI_H
+#define __STM32F0XX_EXTI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup EXTI
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  EXTI mode enumeration  
+  */
+
+typedef enum
+{
+  EXTI_Mode_Interrupt = 0x00,
+  EXTI_Mode_Event = 0x04
+}EXTIMode_TypeDef;
+
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
+
+/** 
+  * @brief  EXTI Trigger enumeration  
+  */
+
+typedef enum
+{
+  EXTI_Trigger_Rising = 0x08,
+  EXTI_Trigger_Falling = 0x0C,
+  EXTI_Trigger_Rising_Falling = 0x10
+}EXTITrigger_TypeDef;
+
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
+                                  ((TRIGGER) == EXTI_Trigger_Falling) || \
+                                  ((TRIGGER) == EXTI_Trigger_Rising_Falling))
+/**
+  * @brief  EXTI Init Structure definition
+  */
+
+typedef struct
+{
+  uint32_t EXTI_Line;               /*!< Specifies the EXTI lines to be enabled or disabled.
+                                         This parameter can be any combination of @ref EXTI_Lines */
+
+  EXTIMode_TypeDef EXTI_Mode;       /*!< Specifies the mode for the EXTI lines.
+                                         This parameter can be a value of @ref EXTIMode_TypeDef */
+
+  EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+                                         This parameter can be a value of @ref EXTIMode_TypeDef */
+
+  FunctionalState EXTI_LineCmd;     /*!< Specifies the new state of the selected EXTI lines.
+                                         This parameter can be set either to ENABLE or DISABLE */
+}EXTI_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup EXTI_Exported_Constants
+  * @{
+  */
+/** @defgroup EXTI_Lines 
+  * @{
+  */
+
+#define EXTI_Line0       ((uint32_t)0x00000001)  /*!< External interrupt line 0  */
+#define EXTI_Line1       ((uint32_t)0x00000002)  /*!< External interrupt line 1  */
+#define EXTI_Line2       ((uint32_t)0x00000004)  /*!< External interrupt line 2  */
+#define EXTI_Line3       ((uint32_t)0x00000008)  /*!< External interrupt line 3  */
+#define EXTI_Line4       ((uint32_t)0x00000010)  /*!< External interrupt line 4  */
+#define EXTI_Line5       ((uint32_t)0x00000020)  /*!< External interrupt line 5  */
+#define EXTI_Line6       ((uint32_t)0x00000040)  /*!< External interrupt line 6  */
+#define EXTI_Line7       ((uint32_t)0x00000080)  /*!< External interrupt line 7  */
+#define EXTI_Line8       ((uint32_t)0x00000100)  /*!< External interrupt line 8  */
+#define EXTI_Line9       ((uint32_t)0x00000200)  /*!< External interrupt line 9  */
+#define EXTI_Line10      ((uint32_t)0x00000400)  /*!< External interrupt line 10 */
+#define EXTI_Line11      ((uint32_t)0x00000800)  /*!< External interrupt line 11 */
+#define EXTI_Line12      ((uint32_t)0x00001000)  /*!< External interrupt line 12 */
+#define EXTI_Line13      ((uint32_t)0x00002000)  /*!< External interrupt line 13 */
+#define EXTI_Line14      ((uint32_t)0x00004000)  /*!< External interrupt line 14 */
+#define EXTI_Line15      ((uint32_t)0x00008000)  /*!< External interrupt line 15 */
+#define EXTI_Line16      ((uint32_t)0x00010000)  /*!< External interrupt line 16 
+                                                      Connected to the PVD Output, 
+                                                      not applicable for STM32F030 devices */
+#define EXTI_Line17      ((uint32_t)0x00020000)  /*!< Internal interrupt line 17 
+                                                      Connected to the RTC Alarm 
+                                                      event */
+#define EXTI_Line18      ((uint32_t)0x00040000)  /*!< Internal interrupt line 18 
+                                                      Connected to the USB
+                                                      event, only applicable for 
+                                                      STM32F072 devices */
+#define EXTI_Line19      ((uint32_t)0x00080000)  /*!< Internal interrupt line 19
+                                                      Connected to the RTC Tamper
+                                                      and Time Stamp events */
+#define EXTI_Line20      ((uint32_t)0x00100000)   /*!< Internal interrupt line 20
+                                                      Connected to the RTC wakeup
+                                                      event, only applicable for 
+                                                      STM32F072 devices  */ 
+#define EXTI_Line21      ((uint32_t)0x00200000)  /*!< Internal interrupt line 21
+                                                      Connected to the Comparator 1
+                                                      event, only applicable for STM32F051
+                                                      ans STM32F072 devices */
+#define EXTI_Line22      ((uint32_t)0x00400000)  /*!< Internal interrupt line 22
+                                                      Connected to the Comparator 2
+                                                      event, only applicable for STM32F051
+                                                      and STM32F072 devices */
+#define EXTI_Line23      ((uint32_t)0x00800000)  /*!< Internal interrupt line 23
+                                                      Connected to the I2C1 wakeup
+                                                      event, not applicable for STM32F030 devices */
+#define EXTI_Line25      ((uint32_t)0x02000000)  /*!< Internal interrupt line 25
+                                                      Connected to the USART1 wakeup
+                                                      event, not applicable for STM32F030 devices */
+#define EXTI_Line26      ((uint32_t)0x04000000)  /*!< Internal interrupt line 26
+                                                      Connected to the USART2 wakeup
+                                                      event, applicable only for 
+                                                      STM32F072 devices */
+#define EXTI_Line27      ((uint32_t)0x08000000)  /*!< Internal interrupt line 27
+                                                      Connected to the CEC wakeup
+                                                      event, applicable only for STM32F051
+                                                      and STM32F072 devices */
+#define EXTI_Line31      ((uint32_t)0x80000000)  /*!< Internal interrupt line 31
+                                                      Connected to the VDD USB monitor
+                                                      event, applicable only for 
+                                                      STM32F072 devices */
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0x71000000) == 0x00) && ((LINE) != (uint16_t)0x00))
+
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
+                                ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
+                                ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
+                                ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
+                                ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
+                                ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
+                                ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
+                                ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
+                                ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
+                                ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
+                                ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \
+                                ((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line23) || \
+                                ((LINE) == EXTI_Line25) || ((LINE) == EXTI_Line26) || \
+                                ((LINE) == EXTI_Line27) || ((LINE) == EXTI_Line31))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Function used to set the EXTI configuration to the default reset state *****/
+void EXTI_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
+
+/* Interrupts and flags management functions **********************************/
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
+void EXTI_ClearFlag(uint32_t EXTI_Line);
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0XX_EXTI_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_flash.h b/system/include/stm32f0-stdperiph/stm32f0xx_flash.h

new file mode 100644 (file)

index 0000000..236cdde
--- /dev/null
+++ b/system/include/stm32f0-stdperiph/stm32f0xx_flash.h
@@ -0,0 +1,435 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_flash.h
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file contains all the functions prototypes for the FLASH 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_FLASH_H
+#define __STM32F0XX_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  FLASH Status
+  */ 
+typedef enum
+{
+  FLASH_BUSY = 1,
+  FLASH_ERROR_WRP,
+  FLASH_ERROR_PROGRAM,
+  FLASH_COMPLETE,
+  FLASH_TIMEOUT
+}FLASH_Status;
+
+/* Exported constants --------------------------------------------------------*/
+  
+/** @defgroup FLASH_Exported_Constants
+  * @{
+  */ 
+  
+/** @defgroup FLASH_Latency 
+  * @{
+  */ 
+#define FLASH_Latency_0                ((uint32_t)0x00000000)  /*!< FLASH Zero Latency cycle */
+#define FLASH_Latency_1                FLASH_ACR_LATENCY       /*!< FLASH One Latency cycle */
+
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
+                                   ((LATENCY) == FLASH_Latency_1))
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Interrupts 
+  * @{
+  */
+   
+#define FLASH_IT_EOP                   FLASH_CR_EOPIE  /*!< End of programming interrupt source */
+#define FLASH_IT_ERR                   FLASH_CR_ERRIE  /*!< Error interrupt source */
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Address 
+  * @{
+  */
+#if defined(STM32F042) || defined(STM32F031) || defined(STM32F070x6)      /*32K devices */
+ #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x08007FFF))
+#elif defined(STM32F030) || defined(STM32F051)                            /*64K devices */
+ #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0800FFFF))
+#elif defined(STM32F072) || defined(STM32F070xB)                          /*128K devices */
+ #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0801FFFF))
+#else /* STM32F091 || STM32F030 || STM32F030xC  */                        /*256K Flash devices */
+ #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0800FFFF))
+#endif /* STM32F042 || STM32F031 || STM32F070x6 */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_OB_DATA_ADDRESS 
+  * @{
+  */  
+#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) 
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Option_Bytes_Write_Protection 
+  * @{
+  */
+  
+#if !defined (STM32F072) && !defined (STM32F070xB) && !defined (STM32F091) && !defined (STM32F030) && !defined (STM32F030xC)  /* 32K and 64K Flash devices */  
+#define OB_WRP_Pages0to3               ((uint32_t)0x00000001) /* Write protection of page 0 to 3 */
+#define OB_WRP_Pages4to7               ((uint32_t)0x00000002) /* Write protection of page 4 to 7 */
+#define OB_WRP_Pages8to11              ((uint32_t)0x00000004) /* Write protection of page 8 to 11 */
+#define OB_WRP_Pages12to15             ((uint32_t)0x00000008) /* Write protection of page 12 to 15 */
+#define OB_WRP_Pages16to19             ((uint32_t)0x00000010) /* Write protection of page 16 to 19 */
+#define OB_WRP_Pages20to23             ((uint32_t)0x00000020) /* Write protection of page 20 to 23 */
+#define OB_WRP_Pages24to27             ((uint32_t)0x00000040) /* Write protection of page 24 to 27 */
+#define OB_WRP_Pages28to31             ((uint32_t)0x00000080) /* Write protection of page 28 to 31 */
+#define OB_WRP_Pages32to35             ((uint32_t)0x00000100) /* Write protection of page 32 to 35 */
+#define OB_WRP_Pages36to39             ((uint32_t)0x00000200) /* Write protection of page 36 to 39 */
+#define OB_WRP_Pages40to43             ((uint32_t)0x00000400) /* Write protection of page 40 to 43 */
+#define OB_WRP_Pages44to47             ((uint32_t)0x00000800) /* Write protection of page 44 to 47 */
+#define OB_WRP_Pages48to51             ((uint32_t)0x00001000) /* Write protection of page 48 to 51 */
+#define OB_WRP_Pages52to55             ((uint32_t)0x00002000) /* Write protection of page 52 to 55 */
+#define OB_WRP_Pages56to59             ((uint32_t)0x00004000) /* Write protection of page 56 to 59 */
+#define OB_WRP_Pages60to63             ((uint32_t)0x00008000) /* Write protection of page 60 to 63 */
+
+#define OB_WRP_AllPages                ((uint32_t)0x0000FFFF) /*!< Write protection of all Sectors */
+
+#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
+
+#else  /* 128K and 256K Flash devices */
+
+#define OB_WRP_Pages0to1               ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */
+#define OB_WRP_Pages2to3               ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */
+#define OB_WRP_Pages4to5               ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */
+#define OB_WRP_Pages6to7               ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */
+#define OB_WRP_Pages8to9               ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */
+#define OB_WRP_Pages10to11             ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */
+#define OB_WRP_Pages12to13             ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */
+#define OB_WRP_Pages14to15             ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */
+#define OB_WRP_Pages16to17             ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */
+#define OB_WRP_Pages18to19             ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */
+#define OB_WRP_Pages20to21             ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */
+#define OB_WRP_Pages22to23             ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */
+#define OB_WRP_Pages24to25             ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */
+#define OB_WRP_Pages26to27             ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */
+#define OB_WRP_Pages28to29             ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */
+#define OB_WRP_Pages30to31             ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */
+#define OB_WRP_Pages32to33             ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */
+#define OB_WRP_Pages34to35             ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */
+#define OB_WRP_Pages36to37             ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */
+#define OB_WRP_Pages38to39             ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */
+#define OB_WRP_Pages40to41             ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */
+#define OB_WRP_Pages42to43             ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */
+#define OB_WRP_Pages44to45             ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */
+#define OB_WRP_Pages46to47             ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */
+#define OB_WRP_Pages48to49             ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */
+#define OB_WRP_Pages50to51             ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */
+#define OB_WRP_Pages52to53             ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */
+#define OB_WRP_Pages54to55             ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */
+#define OB_WRP_Pages56to57             ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */
+#define OB_WRP_Pages58to59             ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */
+#define OB_WRP_Pages60to61             ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */
+
+#if defined(STM32F091) || defined(STM32F030xC)  /* 256K Flash devices */
+#define OB_WRP_Pages62to127            ((uint32_t)0x80000000) /* Write protection of page 62 to 127 */
+#else    /* 128K Flash devices */
+#define OB_WRP_Pages62to63             ((uint32_t)0x80000000) /* Write protection of page 62 to 63 */
+#endif /* STM32F091 || STM32F030xC */
+#define OB_WRP_AllPages                ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
+#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
+
+#endif /* STM32F072 || STM32F070xB || STM32F091 || STM32F030 || STM32F030xC */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Option_Bytes_Read_Protection 
+  * @{
+  */ 
+
+/** 
+  * @brief  FLASH_Read Protection Level  
+  */ 
+#define OB_RDP_Level_0   ((uint8_t)0xAA)
+#define OB_RDP_Level_1   ((uint8_t)0xBB)
+/*#define OB_RDP_Level_2   ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2 
+                                                it's no more possible to go back to level 1 or 0 */
+
+#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
+                          ((LEVEL) == OB_RDP_Level_1))/*||\
+                          ((LEVEL) == OB_RDP_Level_2))*/
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Option_Bytes_IWatchdog 
+  * @{
+  */
+
+#define OB_IWDG_SW                     ((uint8_t)0x01)  /*!< Software IWDG selected */
+#define OB_IWDG_HW                     ((uint8_t)0x00)  /*!< Hardware IWDG selected */
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Option_Bytes_nRST_STOP 
+  * @{
+  */
+
+#define OB_STOP_NoRST                  ((uint8_t)0x02) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST                    ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Option_Bytes_nRST_STDBY 
+  * @{
+  */
+
+#define OB_STDBY_NoRST                 ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST                   ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Option_Bytes_BOOT1
+  * @{
+  */
+
+#define OB_BOOT1_RESET                 ((uint8_t)0x00) /*!< BOOT1 Reset */
+#define OB_BOOT1_SET                   ((uint8_t)0x10) /*!< BOOT1 Set */
+#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Option_Bytes_BOOT0
+  * @{
+  */
+
+#define OB_BOOT0_RESET                 ((uint8_t)0x00) /*!< BOOT0 Reset */
+#define OB_BOOT0_SET                   ((uint8_t)0x08) /*!< BOOT0 Set */
+#define IS_OB_BOOT0(BOOT0) (((BOOT0) == OB_BOOT0_RESET) || ((BOOT0) == OB_BOOT0_SET))
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Option_Bytes_BOOT0SW
+  * @{
+  */
+
+#define OB_BOOT0_SW                   ((uint8_t)0x00) /*!< BOOT0 pin disabled */  
+#define OB_BOOT0_HW                   ((uint8_t)0x80) /*!< BOOT0 pin bonded with GPIO */
+#define IS_OB_BOOT0SW(BOOT0) (((BOOT0) == OB_BOOT0_SW) || ((BOOT0) == OB_BOOT0_HW))
+
+/**
+  * @}
+  */
+  
+/** @defgroup FLASH_Option_Bytes_VDDA_Analog_Monitoring
+  * @{
+  */
+
+#define OB_VDDA_ANALOG_ON              ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source ON */
+#define OB_VDDA_ANALOG_OFF             ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source OFF */
+
+#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
+
+/**
+  * @}
+  */    
+
+/** @defgroup FLASH_Option_Bytes_SRAM_Parity_Enable 
+  * @{
+  */
+
+#define OB_SRAM_PARITY_SET              ((uint8_t)0x00) /*!< SRAM parity enable Set */
+#define OB_SRAM_PARITY_RESET            ((uint8_t)0x40) /*!< SRAM parity enable reset */
+
+#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
+
+/**
+  * @}
+  */ 
+  
+/** @defgroup FLASH_Flags 
+  * @{
+  */ 
+
+#define FLASH_FLAG_BSY                 FLASH_SR_BSY     /*!< FLASH Busy flag */
+#define FLASH_FLAG_PGERR               FLASH_SR_PGERR   /*!< FLASH Programming error flag */
+#define FLASH_FLAG_WRPERR              FLASH_SR_WRPERR  /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_EOP                 FLASH_SR_EOP     /*!< FLASH End of Programming flag */
+ 
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCB) == 0x00000000) && ((FLAG) != 0x00000000))
+
+#define IS_FLASH_GET_FLAG(FLAG)  (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PGERR) || \
+                                  ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP))
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Timeout_definition 
+  * @{
+  */ 
+#define FLASH_ER_PRG_TIMEOUT         ((uint32_t)0x000B0000)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Legacy 
+  * @{
+  */
+#define FLASH_WRProt_Pages0to3        OB_WRP_Pages0to3
+#define FLASH_WRProt_Pages4to7        OB_WRP_Pages4to7
+#define FLASH_WRProt_Pages8to11               OB_WRP_Pages8to11
+#define FLASH_WRProt_Pages12to15          OB_WRP_Pages12to15
+#define FLASH_WRProt_Pages16to19          OB_WRP_Pages16to19
+#define FLASH_WRProt_Pages20to23          OB_WRP_Pages20to23
+#define FLASH_WRProt_Pages24to27          OB_WRP_Pages24to27
+#define FLASH_WRProt_Pages28to31          OB_WRP_Pages28to31
+#define FLASH_WRProt_Pages32to35          OB_WRP_Pages32to35
+#define FLASH_WRProt_Pages36to39          OB_WRP_Pages36to39
+#define FLASH_WRProt_Pages40to43          OB_WRP_Pages40to21
+#define FLASH_WRProt_Pages44to47          OB_WRP_Pages44to23
+#define FLASH_WRProt_Pages48to51          OB_WRP_Pages48to51
+#define FLASH_WRProt_Pages52to55          OB_WRP_Pages52to55
+#define FLASH_WRProt_Pages56to59          OB_WRP_Pages56to59
+#define FLASH_WRProt_Pages60to63          OB_WRP_Pages60to63
+
+
+#define FLASH_WRProt_AllPages          OB_WRP_AllPages
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+  
+/** 
+  * @brief  FLASH memory functions that can be executed from FLASH.  
+  */  
+/* FLASH Interface configuration functions ************************************/
+void FLASH_SetLatency(uint32_t FLASH_Latency);
+void FLASH_PrefetchBufferCmd(FunctionalState NewState);
+FlagStatus FLASH_GetPrefetchBufferStatus(void);
+
+/* FLASH Memory Programming functions *****************************************/
+void FLASH_Unlock(void);
+void FLASH_Lock(void);
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
+FLASH_Status FLASH_EraseAllPages(void);
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
+
+/* FLASH Option Bytes Programming functions *****************************************/
+void FLASH_OB_Unlock(void);
+void FLASH_OB_Lock(void);
+void FLASH_OB_Launch(void);
+FLASH_Status FLASH_OB_Erase(void);
+FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP);
+FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
+FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
+FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);
+FLASH_Status FLASH_OB_BOOT0Config(uint8_t OB_BOOT0);
+FLASH_Status FLASH_OB_BOOT0SWConfig(uint8_t OB_BOOT0SW);
+FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);
+FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity);
+FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);
+FLASH_Status FLASH_OB_ProgramData(uint32_t Address, uint8_t Data);
+uint8_t FLASH_OB_GetUser(void);
+uint32_t FLASH_OB_GetWRP(void);
+FlagStatus FLASH_OB_GetRDP(void);
+
+/* FLASH Interrupts and flags management functions **********************************/
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);
+FLASH_Status FLASH_GetStatus(void);
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
+
+/** @defgroup FLASH_Legacy 
+  * @{
+  */
+#define FLASH_EraseOptionBytes               FLASH_OB_Erase
+#define FLASH_EnableWriteProtection             FLASH_OB_EnableWRP
+#define FLASH_UserOptionByteConfig              FLASH_OB_UserConfig
+#define FLASH_ProgramOptionByteData          FLASH_OB_ProgramData
+#define FLASH_GetUserOptionByte                     FLASH_OB_GetUser
+#define FLASH_GetWriteProtectionOptionByte   FLASH_OB_GetWRP
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0XX_FLASH_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_gpio.h b/system/include/stm32f0-stdperiph/stm32f0xx_gpio.h

new file mode 100644 (file)

index 0000000..867e4d8
--- /dev/null
+++ b/system/include/stm32f0-stdperiph/stm32f0xx_gpio.h
@@ -0,0 +1,358 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_gpio.h
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file contains all the functions prototypes for the GPIO 
+  *          firmware library. 
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_GPIO_H
+#define __STM32F0XX_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup GPIO
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/
+
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+                                    ((PERIPH) == GPIOB) || \
+                                    ((PERIPH) == GPIOC) || \
+                                    ((PERIPH) == GPIOD) || \
+                                    ((PERIPH) == GPIOE) || \
+                                    ((PERIPH) == GPIOF))
+
+#define IS_GPIO_LIST_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+                                     ((PERIPH) == GPIOB))
+
+/** @defgroup Configuration_Mode_enumeration 
+  * @{
+  */
+typedef enum
+{
+  GPIO_Mode_IN   = 0x00, /*!< GPIO Input Mode              */
+  GPIO_Mode_OUT  = 0x01, /*!< GPIO Output Mode             */
+  GPIO_Mode_AF   = 0x02, /*!< GPIO Alternate function Mode */
+  GPIO_Mode_AN   = 0x03  /*!< GPIO Analog In/Out Mode      */
+}GPIOMode_TypeDef;
+
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)|| ((MODE) == GPIO_Mode_OUT) || \
+                            ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
+/**
+  * @}
+  */
+
+/** @defgroup Output_type_enumeration
+  * @{
+  */
+typedef enum
+{
+  GPIO_OType_PP = 0x00,
+  GPIO_OType_OD = 0x01
+}GPIOOType_TypeDef;
+
+#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
+
+/**
+  * @}
+  */
+
+/** @defgroup Output_Maximum_frequency_enumeration 
+  * @{
+  */
+typedef enum
+{
+  GPIO_Speed_Level_1  = 0x00, /*!< I/O output speed: Low 2 MHz */
+  GPIO_Speed_Level_2  = 0x01, /*!< I/O output speed: Medium 10 MHz */
+  GPIO_Speed_Level_3  = 0x03  /*!< I/O output speed: High 50 MHz */
+}GPIOSpeed_TypeDef;
+
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_Level_1) || ((SPEED) == GPIO_Speed_Level_2) || \
+                              ((SPEED) == GPIO_Speed_Level_3))
+/**
+  * @}
+  */
+
+/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration 
+  * @{
+  */
+typedef enum
+{
+  GPIO_PuPd_NOPULL = 0x00,
+  GPIO_PuPd_UP     = 0x01,
+  GPIO_PuPd_DOWN   = 0x02
+}GPIOPuPd_TypeDef;
+
+#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
+                            ((PUPD) == GPIO_PuPd_DOWN))
+/**
+  * @}
+  */
+
+/** @defgroup Bit_SET_and_Bit_RESET_enumeration
+  * @{
+  */
+typedef enum
+{ 
+  Bit_RESET = 0,
+  Bit_SET
+}BitAction;
+
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
+/**
+  * @}
+  */
+
+/**
+  * @brief  GPIO Init structure definition  
+  */
+typedef struct
+{
+  uint32_t GPIO_Pin;              /*!< Specifies the GPIO pins to be configured.
+                                       This parameter can be any value of @ref GPIO_pins_define */
+                                       
+  GPIOMode_TypeDef GPIO_Mode;     /*!< Specifies the operating mode for the selected pins.
+                                       This parameter can be a value of @ref GPIOMode_TypeDef   */
+
+  GPIOSpeed_TypeDef GPIO_Speed;   /*!< Specifies the speed for the selected pins.
+                                       This parameter can be a value of @ref GPIOSpeed_TypeDef  */
+
+  GPIOOType_TypeDef GPIO_OType;   /*!< Specifies the operating output type for the selected pins.
+                                       This parameter can be a value of @ref GPIOOType_TypeDef  */
+
+  GPIOPuPd_TypeDef GPIO_PuPd;     /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+                                       This parameter can be a value of @ref GPIOPuPd_TypeDef   */
+}GPIO_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants
+  * @{
+  */
+
+/** @defgroup GPIO_pins_define 
+  * @{
+  */
+#define GPIO_Pin_0                 ((uint16_t)0x0001)  /*!< Pin 0 selected    */
+#define GPIO_Pin_1                 ((uint16_t)0x0002)  /*!< Pin 1 selected    */
+#define GPIO_Pin_2                 ((uint16_t)0x0004)  /*!< Pin 2 selected    */
+#define GPIO_Pin_3                 ((uint16_t)0x0008)  /*!< Pin 3 selected    */
+#define GPIO_Pin_4                 ((uint16_t)0x0010)  /*!< Pin 4 selected    */
+#define GPIO_Pin_5                 ((uint16_t)0x0020)  /*!< Pin 5 selected    */
+#define GPIO_Pin_6                 ((uint16_t)0x0040)  /*!< Pin 6 selected    */
+#define GPIO_Pin_7                 ((uint16_t)0x0080)  /*!< Pin 7 selected    */
+#define GPIO_Pin_8                 ((uint16_t)0x0100)  /*!< Pin 8 selected    */
+#define GPIO_Pin_9                 ((uint16_t)0x0200)  /*!< Pin 9 selected    */
+#define GPIO_Pin_10                ((uint16_t)0x0400)  /*!< Pin 10 selected   */
+#define GPIO_Pin_11                ((uint16_t)0x0800)  /*!< Pin 11 selected   */
+#define GPIO_Pin_12                ((uint16_t)0x1000)  /*!< Pin 12 selected   */
+#define GPIO_Pin_13                ((uint16_t)0x2000)  /*!< Pin 13 selected   */
+#define GPIO_Pin_14                ((uint16_t)0x4000)  /*!< Pin 14 selected   */
+#define GPIO_Pin_15                ((uint16_t)0x8000)  /*!< Pin 15 selected   */
+#define GPIO_Pin_All               ((uint16_t)0xFFFF)  /*!< All pins selected */
+
+#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
+
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
+                              ((PIN) == GPIO_Pin_1) || \
+                              ((PIN) == GPIO_Pin_2) || \
+                              ((PIN) == GPIO_Pin_3) || \
+                              ((PIN) == GPIO_Pin_4) || \
+                              ((PIN) == GPIO_Pin_5) || \
+                              ((PIN) == GPIO_Pin_6) || \
+                              ((PIN) == GPIO_Pin_7) || \
+                              ((PIN) == GPIO_Pin_8) || \
+                              ((PIN) == GPIO_Pin_9) || \
+                              ((PIN) == GPIO_Pin_10) || \
+                              ((PIN) == GPIO_Pin_11) || \
+                              ((PIN) == GPIO_Pin_12) || \
+                              ((PIN) == GPIO_Pin_13) || \
+                              ((PIN) == GPIO_Pin_14) || \
+                              ((PIN) == GPIO_Pin_15))
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Pin_sources 
+  * @{
+  */
+#define GPIO_PinSource0            ((uint8_t)0x00)
+#define GPIO_PinSource1            ((uint8_t)0x01)
+#define GPIO_PinSource2            ((uint8_t)0x02)
+#define GPIO_PinSource3            ((uint8_t)0x03)
+#define GPIO_PinSource4            ((uint8_t)0x04)
+#define GPIO_PinSource5            ((uint8_t)0x05)
+#define GPIO_PinSource6            ((uint8_t)0x06)
+#define GPIO_PinSource7            ((uint8_t)0x07)
+#define GPIO_PinSource8            ((uint8_t)0x08)
+#define GPIO_PinSource9            ((uint8_t)0x09)
+#define GPIO_PinSource10           ((uint8_t)0x0A)
+#define GPIO_PinSource11           ((uint8_t)0x0B)
+#define GPIO_PinSource12           ((uint8_t)0x0C)
+#define GPIO_PinSource13           ((uint8_t)0x0D)
+#define GPIO_PinSource14           ((uint8_t)0x0E)
+#define GPIO_PinSource15           ((uint8_t)0x0F)
+
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
+                                       ((PINSOURCE) == GPIO_PinSource1) || \
+                                       ((PINSOURCE) == GPIO_PinSource2) || \
+                                       ((PINSOURCE) == GPIO_PinSource3) || \
+                                       ((PINSOURCE) == GPIO_PinSource4) || \
+                                       ((PINSOURCE) == GPIO_PinSource5) || \
+                                       ((PINSOURCE) == GPIO_PinSource6) || \
+                                       ((PINSOURCE) == GPIO_PinSource7) || \
+                                       ((PINSOURCE) == GPIO_PinSource8) || \
+                                       ((PINSOURCE) == GPIO_PinSource9) || \
+                                       ((PINSOURCE) == GPIO_PinSource10) || \
+                                       ((PINSOURCE) == GPIO_PinSource11) || \
+                                       ((PINSOURCE) == GPIO_PinSource12) || \
+                                       ((PINSOURCE) == GPIO_PinSource13) || \
+                                       ((PINSOURCE) == GPIO_PinSource14) || \
+                                       ((PINSOURCE) == GPIO_PinSource15))
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Alternate_function_selection_define 
+  * @{
+  */
+
+/** 
+  * @brief  AF 0 selection
+  */
+#define GPIO_AF_0            ((uint8_t)0x00) /* WKUP, EVENTOUT, TIM15, SPI1, TIM17,
+                                                MCO, SWDAT, SWCLK, TIM14, BOOT,
+                                                USART1, CEC, IR_OUT, SPI2, TS, TIM3,
+                                                USART4, CAN, TIM3, USART2, USART3, 
+                                                CRS, TIM16, TIM1 */
+/** 
+  * @brief  AF 1 selection
+  */
+#define GPIO_AF_1            ((uint8_t)0x01) /* USART2, CEC, TIM3, USART1, IR,
+                                                EVENTOUT, I2C1, I2C2, TIM15, SPI2,
+                                                USART3, TS, SPI1 */
+/** 
+  * @brief  AF 2 selection
+  */
+#define GPIO_AF_2            ((uint8_t)0x02) /* TIM2, TIM1, EVENTOUT, TIM16, TIM17,
+                                                USB */
+/** 
+  * @brief  AF 3 selection
+  */
+#define GPIO_AF_3            ((uint8_t)0x03) /* TS, I2C1, TIM15, EVENTOUT */
+
+/** 
+  * @brief  AF 4 selection
+  */
+#define GPIO_AF_4            ((uint8_t)0x04) /* TIM14, USART4, USART3, CRS, CAN,
+                                                I2C1 */
+
+/** 
+  * @brief  AF 5 selection
+  */
+#define GPIO_AF_5            ((uint8_t)0x05) /* TIM16, TIM17, TIM15, SPI2, I2C2, 
+                                                MCO, I2C1, USB */
+
+/** 
+  * @brief  AF 6 selection
+  */
+#define GPIO_AF_6            ((uint8_t)0x06) /* EVENTOUT */
+/** 
+  * @brief  AF 7 selection
+  */
+#define GPIO_AF_7            ((uint8_t)0x07) /* COMP1 OUT and COMP2 OUT */
+
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF_0) || ((AF) == GPIO_AF_1) || \
+                          ((AF) == GPIO_AF_2) || ((AF) == GPIO_AF_3) || \
+                          ((AF) == GPIO_AF_4) || ((AF) == GPIO_AF_5) || \
+                          ((AF) == GPIO_AF_6) || ((AF) == GPIO_AF_7))
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Speed_Legacy 
+  * @{
+  */
+
+#define GPIO_Speed_2MHz  GPIO_Speed_Level_1   /*!< I/O output speed: Low 2 MHz  */
+#define GPIO_Speed_10MHz GPIO_Speed_Level_2   /*!< I/O output speed: Medium 10 MHz */
+#define GPIO_Speed_50MHz GPIO_Speed_Level_3   /*!< I/O output speed: High 50 MHz */
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Function used to set the GPIO configuration to the default reset state *****/
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);
+
+/* Initialization and Configuration functions *********************************/
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+
+/* GPIO Read and Write functions **********************************************/
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
+
+/* GPIO Alternate functions configuration functions ***************************/
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0XX_GPIO_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_i2c.h b/system/include/stm32f0-stdperiph/stm32f0xx_i2c.h

new file mode 100644 (file)

index 0000000..0e29f5d
--- /dev/null
+++ b/system/include/stm32f0-stdperiph/stm32f0xx_i2c.h
@@ -0,0 +1,478 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_i2c.h
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file contains all the functions prototypes for the I2C firmware
+  *          library
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_I2C_H
+#define __STM32F0XX_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup I2C
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  I2C Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t I2C_Timing;              /*!< Specifies the I2C_TIMINGR_register value.
+                                         This parameter must be set by referring to I2C_Timing_Config_Tool*/
+
+  uint32_t I2C_AnalogFilter;        /*!< Enables or disables analog noise filter.
+                                         This parameter can be a value of @ref I2C_Analog_Filter*/
+
+  uint32_t I2C_DigitalFilter;       /*!< Configures the digital noise filter.
+                                         This parameter can be a number between 0x00 and 0x0F*/
+
+  uint32_t I2C_Mode;                /*!< Specifies the I2C mode.
+                                         This parameter can be a value of @ref I2C_mode*/
+
+  uint32_t I2C_OwnAddress1;         /*!< Specifies the device own address 1.
+                                         This parameter can be a 7-bit or 10-bit address*/
+
+  uint32_t I2C_Ack;                 /*!< Enables or disables the acknowledgement.
+                                         This parameter can be a value of @ref I2C_acknowledgement*/
+
+  uint32_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
+                                         This parameter can be a value of @ref I2C_acknowledged_address*/
+}I2C_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+
+/** @defgroup I2C_Exported_Constants
+  * @{
+  */
+
+#define IS_I2C_ALL_PERIPH(PERIPH)       (((PERIPH) == I2C1) || \
+                                         ((PERIPH) == I2C2))
+                                         
+#define IS_I2C_1_PERIPH(PERIPH)         ((PERIPH) == I2C1) 
+
+/** @defgroup I2C_Analog_Filter 
+  * @{
+  */
+
+#define I2C_AnalogFilter_Enable         ((uint32_t)0x00000000)
+#define I2C_AnalogFilter_Disable        I2C_CR1_ANFOFF
+
+#define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_AnalogFilter_Enable) || \
+                                         ((FILTER) == I2C_AnalogFilter_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Digital_Filter
+  * @{
+  */
+
+#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000F)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_mode 
+  * @{
+  */
+
+#define I2C_Mode_I2C                    ((uint32_t)0x00000000)
+#define I2C_Mode_SMBusDevice            I2C_CR1_SMBDEN
+#define I2C_Mode_SMBusHost              I2C_CR1_SMBHEN
+
+#define IS_I2C_MODE(MODE)               (((MODE) == I2C_Mode_I2C) || \
+                                         ((MODE) == I2C_Mode_SMBusDevice) || \
+                                         ((MODE) == I2C_Mode_SMBusHost))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_acknowledgement
+  * @{
+  */
+
+#define I2C_Ack_Enable                  ((uint32_t)0x00000000)
+#define I2C_Ack_Disable                 I2C_CR2_NACK
+
+#define IS_I2C_ACK(ACK)                 (((ACK) == I2C_Ack_Enable) || \
+                                         ((ACK) == I2C_Ack_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_acknowledged_address
+  * @{
+  */
+
+#define I2C_AcknowledgedAddress_7bit    ((uint32_t)0x00000000)
+#define I2C_AcknowledgedAddress_10bit   I2C_OAR1_OA1MODE
+
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
+                                             ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_own_address1
+  * @{
+  */
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1)   ((ADDRESS1) <= (uint32_t)0x000003FF)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_transfer_direction 
+  * @{
+  */
+
+#define I2C_Direction_Transmitter       ((uint16_t)0x0000)
+#define I2C_Direction_Receiver          ((uint16_t)0x0400)
+
+#define IS_I2C_DIRECTION(DIRECTION)     (((DIRECTION) == I2C_Direction_Transmitter) || \
+                                         ((DIRECTION) == I2C_Direction_Receiver))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_DMA_transfer_requests 
+  * @{
+  */
+
+#define I2C_DMAReq_Tx                   I2C_CR1_TXDMAEN
+#define I2C_DMAReq_Rx                   I2C_CR1_RXDMAEN
+
+#define IS_I2C_DMA_REQ(REQ)             ((((REQ) & (uint32_t)0xFFFF3FFF) == 0x00) && ((REQ) != 0x00))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_slave_address
+  * @{
+  */
+
+#define IS_I2C_SLAVE_ADDRESS(ADDRESS)   ((ADDRESS) <= (uint16_t)0x03FF)
+/**
+  * @}
+  */
+
+
+/** @defgroup I2C_own_address2
+  * @{
+  */
+
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2)   ((ADDRESS2) <= (uint16_t)0x00FF)
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_own_address2_mask
+  * @{
+  */
+
+#define I2C_OA2_NoMask                  ((uint8_t)0x00)
+#define I2C_OA2_Mask01                  ((uint8_t)0x01)                 
+#define I2C_OA2_Mask02                  ((uint8_t)0x02)
+#define I2C_OA2_Mask03                  ((uint8_t)0x03)
+#define I2C_OA2_Mask04                  ((uint8_t)0x04)
+#define I2C_OA2_Mask05                  ((uint8_t)0x05)
+#define I2C_OA2_Mask06                  ((uint8_t)0x06)
+#define I2C_OA2_Mask07                  ((uint8_t)0x07)
+
+#define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NoMask) || \
+                                         ((MASK) == I2C_OA2_Mask01) || \
+                                         ((MASK) == I2C_OA2_Mask02) || \
+                                         ((MASK) == I2C_OA2_Mask03) || \
+                                         ((MASK) == I2C_OA2_Mask04) || \
+                                         ((MASK) == I2C_OA2_Mask05) || \
+                                         ((MASK) == I2C_OA2_Mask06) || \
+                                         ((MASK) == I2C_OA2_Mask07))  
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_timeout
+  * @{
+  */
+
+#define IS_I2C_TIMEOUT(TIMEOUT)   ((TIMEOUT) <= (uint16_t)0x0FFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_registers 
+  * @{
+  */
+
+#define I2C_Register_CR1                ((uint8_t)0x00)
+#define I2C_Register_CR2                ((uint8_t)0x04)
+#define I2C_Register_OAR1               ((uint8_t)0x08)
+#define I2C_Register_OAR2               ((uint8_t)0x0C)
+#define I2C_Register_TIMINGR            ((uint8_t)0x10)
+#define I2C_Register_TIMEOUTR           ((uint8_t)0x14)
+#define I2C_Register_ISR                ((uint8_t)0x18)
+#define I2C_Register_ICR                ((uint8_t)0x1C)
+#define I2C_Register_PECR               ((uint8_t)0x20)
+#define I2C_Register_RXDR               ((uint8_t)0x24)
+#define I2C_Register_TXDR               ((uint8_t)0x28)
+
+#define IS_I2C_REGISTER(REGISTER)       (((REGISTER) == I2C_Register_CR1) || \
+                                         ((REGISTER) == I2C_Register_CR2) || \
+                                         ((REGISTER) == I2C_Register_OAR1) || \
+                                         ((REGISTER) == I2C_Register_OAR2) || \
+                                         ((REGISTER) == I2C_Register_TIMINGR) || \
+                                         ((REGISTER) == I2C_Register_TIMEOUTR) || \
+                                         ((REGISTER) == I2C_Register_ISR) || \
+                                         ((REGISTER) == I2C_Register_ICR) || \
+                                         ((REGISTER) == I2C_Register_PECR) || \
+                                         ((REGISTER) == I2C_Register_RXDR) || \
+                                         ((REGISTER) == I2C_Register_TXDR))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_interrupts_definition 
+  * @{
+  */
+
+#define I2C_IT_ERRI                     I2C_CR1_ERRIE
+#define I2C_IT_TCI                      I2C_CR1_TCIE
+#define I2C_IT_STOPI                    I2C_CR1_STOPIE
+#define I2C_IT_NACKI                    I2C_CR1_NACKIE
+#define I2C_IT_ADDRI                    I2C_CR1_ADDRIE
+#define I2C_IT_RXI                      I2C_CR1_RXIE
+#define I2C_IT_TXI                      I2C_CR1_TXIE
+
+#define IS_I2C_CONFIG_IT(IT)            ((((IT) & (uint32_t)0xFFFFFF01) == 0x00) && ((IT) != 0x00))
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_flags_definition 
+  * @{
+  */
+
+#define  I2C_FLAG_TXE                   I2C_ISR_TXE
+#define  I2C_FLAG_TXIS                  I2C_ISR_TXIS
+#define  I2C_FLAG_RXNE                  I2C_ISR_RXNE
+#define  I2C_FLAG_ADDR                  I2C_ISR_ADDR
+#define  I2C_FLAG_NACKF                 I2C_ISR_NACKF
+#define  I2C_FLAG_STOPF                 I2C_ISR_STOPF
+#define  I2C_FLAG_TC                    I2C_ISR_TC
+#define  I2C_FLAG_TCR                   I2C_ISR_TCR
+#define  I2C_FLAG_BERR                  I2C_ISR_BERR
+#define  I2C_FLAG_ARLO                  I2C_ISR_ARLO
+#define  I2C_FLAG_OVR                   I2C_ISR_OVR
+#define  I2C_FLAG_PECERR                I2C_ISR_PECERR
+#define  I2C_FLAG_TIMEOUT               I2C_ISR_TIMEOUT
+#define  I2C_FLAG_ALERT                 I2C_ISR_ALERT
+#define  I2C_FLAG_BUSY                  I2C_ISR_BUSY
+
+#define IS_I2C_CLEAR_FLAG(FLAG)         ((((FLAG) & (uint32_t)0xFFFF4000) == 0x00) && ((FLAG) != 0x00))
+
+#define IS_I2C_GET_FLAG(FLAG)           (((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_TXIS) || \
+                                         ((FLAG) == I2C_FLAG_RXNE) || ((FLAG) == I2C_FLAG_ADDR) || \
+                                         ((FLAG) == I2C_FLAG_NACKF) || ((FLAG) == I2C_FLAG_STOPF) || \
+                                         ((FLAG) == I2C_FLAG_TC) || ((FLAG) == I2C_FLAG_TCR) || \
+                                         ((FLAG) == I2C_FLAG_BERR) || ((FLAG) == I2C_FLAG_ARLO) || \
+                                         ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_PECERR) || \
+                                         ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_ALERT) || \
+                                         ((FLAG) == I2C_FLAG_BUSY))
+
+/**
+  * @}
+  */
+
+
+/** @defgroup I2C_interrupts_definition 
+  * @{
+  */
+
+#define  I2C_IT_TXIS                    I2C_ISR_TXIS
+#define  I2C_IT_RXNE                    I2C_ISR_RXNE
+#define  I2C_IT_ADDR                    I2C_ISR_ADDR
+#define  I2C_IT_NACKF                   I2C_ISR_NACKF
+#define  I2C_IT_STOPF                   I2C_ISR_STOPF
+#define  I2C_IT_TC                      I2C_ISR_TC
+#define  I2C_IT_TCR                     I2C_ISR_TCR
+#define  I2C_IT_BERR                    I2C_ISR_BERR
+#define  I2C_IT_ARLO                    I2C_ISR_ARLO
+#define  I2C_IT_OVR                     I2C_ISR_OVR
+#define  I2C_IT_PECERR                  I2C_ISR_PECERR
+#define  I2C_IT_TIMEOUT                 I2C_ISR_TIMEOUT
+#define  I2C_IT_ALERT                   I2C_ISR_ALERT
+
+#define IS_I2C_CLEAR_IT(IT)             ((((IT) & (uint32_t)0xFFFFC001) == 0x00) && ((IT) != 0x00))
+                               
+#define IS_I2C_GET_IT(IT)               (((IT) == I2C_IT_TXIS) || ((IT) == I2C_IT_RXNE) || \
+                                         ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_NACKF) || \
+                                         ((IT) == I2C_IT_STOPF) || ((IT) == I2C_IT_TC) || \
+                                         ((IT) == I2C_IT_TCR) || ((IT) == I2C_IT_BERR) || \
+                                         ((IT) == I2C_IT_ARLO) || ((IT) == I2C_IT_OVR) || \
+                                         ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_TIMEOUT) || \
+                                         ((IT) == I2C_IT_ALERT))
+                               
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_ReloadEndMode_definition 
+  * @{
+  */
+
+#define  I2C_Reload_Mode                I2C_CR2_RELOAD
+#define  I2C_AutoEnd_Mode               I2C_CR2_AUTOEND
+#define  I2C_SoftEnd_Mode               ((uint32_t)0x00000000)
+
+                              
+#define IS_RELOAD_END_MODE(MODE)        (((MODE) == I2C_Reload_Mode) || \
+                                         ((MODE) == I2C_AutoEnd_Mode) || \
+                                         ((MODE) == I2C_SoftEnd_Mode))
+                               
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_StartStopMode_definition 
+  * @{
+  */
+
+#define  I2C_No_StartStop                 ((uint32_t)0x00000000)
+#define  I2C_Generate_Stop                I2C_CR2_STOP
+#define  I2C_Generate_Start_Read          (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
+#define  I2C_Generate_Start_Write         I2C_CR2_START
+
+                              
+#define IS_START_STOP_MODE(MODE)        (((MODE) == I2C_Generate_Stop) || \
+                                         ((MODE) == I2C_Generate_Start_Read) || \
+                                         ((MODE) == I2C_Generate_Start_Write) || \
+                                         ((MODE) == I2C_No_StartStop))
+                               
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+
+/* Initialization and Configuration functions *********************************/
+void I2C_DeInit(I2C_TypeDef* I2Cx);
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx);
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState);
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); /*!< not applicable for STM32F030 devices */
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask);
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address);
+void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
+/* Communications handling functions ******************************************/
+void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes);
+void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction);
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
+uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx);
+uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx);
+void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode);
+
+/*  SMBUS management functions ************************************************/
+void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
+void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
+
+/* I2C registers management functions *****************************************/
+uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
+
+/* Data transfers management functions ****************************************/
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
+
+/* DMA transfers management functions *****************************************/
+void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F0XX_I2C_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h b/system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h

new file mode 100644 (file)

index 0000000..1f2eece
--- /dev/null
+++ b/system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h
@@ -0,0 +1,140 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_iwdg.h
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file contains all the functions prototypes for the IWDG 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_IWDG_H
+#define __STM32F0XX_IWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup IWDG
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup IWDG_Exported_Constants
+  * @{
+  */
+
+/** @defgroup IWDG_WriteAccess
+  * @{
+  */
+
+#define IWDG_WriteAccess_Enable     ((uint16_t)0x5555)
+#define IWDG_WriteAccess_Disable    ((uint16_t)0x0000)
+#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
+                                      ((ACCESS) == IWDG_WriteAccess_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_prescaler 
+  * @{
+  */
+
+#define IWDG_Prescaler_4            ((uint8_t)0x00)
+#define IWDG_Prescaler_8            ((uint8_t)0x01)
+#define IWDG_Prescaler_16           ((uint8_t)0x02)
+#define IWDG_Prescaler_32           ((uint8_t)0x03)
+#define IWDG_Prescaler_64           ((uint8_t)0x04)
+#define IWDG_Prescaler_128          ((uint8_t)0x05)
+#define IWDG_Prescaler_256          ((uint8_t)0x06)
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4)  || \
+                                      ((PRESCALER) == IWDG_Prescaler_8)  || \
+                                      ((PRESCALER) == IWDG_Prescaler_16) || \
+                                      ((PRESCALER) == IWDG_Prescaler_32) || \
+                                      ((PRESCALER) == IWDG_Prescaler_64) || \
+                                      ((PRESCALER) == IWDG_Prescaler_128)|| \
+                                      ((PRESCALER) == IWDG_Prescaler_256))
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Flag 
+  * @{
+  */
+
+#define IWDG_FLAG_PVU               IWDG_SR_PVU
+#define IWDG_FLAG_RVU               IWDG_SR_RVU
+#define IWDG_FLAG_WVU               IWDG_SR_WVU
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)  || \
+                            ((FLAG) == IWDG_FLAG_WVU))
+
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
+
+#define IS_IWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0xFFF)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Prescaler and Counter configuration functions ******************************/
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
+void IWDG_SetReload(uint16_t Reload);
+void IWDG_ReloadCounter(void);
+void IWDG_SetWindowValue(uint16_t WindowValue);
+
+/* IWDG activation function ***************************************************/
+void IWDG_Enable(void);
+
+/* Flag management function ***************************************************/
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0XX_IWDG_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_misc.h b/system/include/stm32f0-stdperiph/stm32f0xx_misc.h

new file mode 100644 (file)

index 0000000..3811f0f
--- /dev/null
+++ b/system/include/stm32f0-stdperiph/stm32f0xx_misc.h
@@ -0,0 +1,143 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_misc.h
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file contains all the functions prototypes for the miscellaneous
+  *          firmware library functions (add-on to CMSIS functions).
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_MISC_H
+#define __STM32F0XX_MISC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup MISC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  NVIC Init Structure definition  
+  */
+
+typedef struct
+{
+  uint8_t NVIC_IRQChannel;             /*!< Specifies the IRQ channel to be enabled or disabled.
+                                            This parameter can be a value of @ref IRQn_Type 
+                                            (For the complete STM32 Devices IRQ Channels list, 
+                                            please refer to stm32f0xx.h file) */
+
+  uint8_t NVIC_IRQChannelPriority;     /*!< Specifies the priority level for the IRQ channel specified
+                                            in NVIC_IRQChannel. This parameter can be a value
+                                            between 0 and 3.  */
+
+  FunctionalState NVIC_IRQChannelCmd;  /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
+                                            will be enabled or disabled. 
+                                            This parameter can be set either to ENABLE or DISABLE */   
+} NVIC_InitTypeDef;
+
+/**  
+  *
+@verbatim   
+
+@endverbatim
+*/
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup MISC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup MISC_System_Low_Power 
+  * @{
+  */
+
+#define NVIC_LP_SEVONPEND            ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP            ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT          ((uint8_t)0x02)
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
+                        ((LP) == NVIC_LP_SLEEPDEEP) || \
+                        ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Preemption_Priority_Group 
+  * @{
+  */
+#define IS_NVIC_PRIORITY(PRIORITY)  ((PRIORITY) < 0x04)
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_SysTick_clock_source 
+  * @{
+  */
+
+#define SysTick_CLKSource_HCLK_Div8    ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK         ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
+                                       ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */ 
+
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0XX_MISC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_pwr.h b/system/include/stm32f0-stdperiph/stm32f0xx_pwr.h

new file mode 100644 (file)

index 0000000..378e07e
--- /dev/null
+++ b/system/include/stm32f0-stdperiph/stm32f0xx_pwr.h
@@ -0,0 +1,197 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_pwr.h
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file contains all the functions prototypes for the PWR firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_PWR_H
+#define __STM32F0XX_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup PWR
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Constants
+  * @{
+  */ 
+
+/** @defgroup PWR_PVD_detection_level 
+  * @brief    This parameters are only applicable for STM32F051 and STM32F072 devices
+  * @{
+  */ 
+
+#define PWR_PVDLevel_0                  PWR_CR_PLS_LEV0
+#define PWR_PVDLevel_1                  PWR_CR_PLS_LEV1
+#define PWR_PVDLevel_2                  PWR_CR_PLS_LEV2
+#define PWR_PVDLevel_3                  PWR_CR_PLS_LEV3
+#define PWR_PVDLevel_4                  PWR_CR_PLS_LEV4
+#define PWR_PVDLevel_5                  PWR_CR_PLS_LEV5
+#define PWR_PVDLevel_6                  PWR_CR_PLS_LEV6
+#define PWR_PVDLevel_7                  PWR_CR_PLS_LEV7 
+
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
+                                 ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
+                                 ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
+                                 ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
+/**
+  * @}
+  */
+
+/** @defgroup PWR_WakeUp_Pins 
+  * @{
+  */
+
+#define PWR_WakeUpPin_1                 PWR_CSR_EWUP1
+#define PWR_WakeUpPin_2                 PWR_CSR_EWUP2
+#define PWR_WakeUpPin_3                 PWR_CSR_EWUP3 /*!< only applicable for STM32F072 devices */
+#define PWR_WakeUpPin_4                 PWR_CSR_EWUP4 /*!< only applicable for STM32F072 devices */
+#define PWR_WakeUpPin_5                 PWR_CSR_EWUP5 /*!< only applicable for STM32F072 devices */
+#define PWR_WakeUpPin_6                 PWR_CSR_EWUP6 /*!< only applicable for STM32F072 devices */
+#define PWR_WakeUpPin_7                 PWR_CSR_EWUP7 /*!< only applicable for STM32F072 devices */
+#define PWR_WakeUpPin_8                 PWR_CSR_EWUP8 /*!< only applicable for STM32F072 devices */
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || ((PIN) == PWR_WakeUpPin_2) || \
+                                ((PIN) == PWR_WakeUpPin_3) || ((PIN) == PWR_WakeUpPin_4) || \
+                                ((PIN) == PWR_WakeUpPin_5) || ((PIN) == PWR_WakeUpPin_6) || \
+                                ((PIN) == PWR_WakeUpPin_7) || ((PIN) == PWR_WakeUpPin_8))
+/**
+  * @}
+  */
+
+ 
+/** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode 
+  * @{
+  */
+
+#define PWR_Regulator_ON                ((uint32_t)0x00000000)
+#define PWR_Regulator_LowPower          PWR_CR_LPSDSR
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
+                                     ((REGULATOR) == PWR_Regulator_LowPower))
+/**
+  * @}
+  */
+
+/** @defgroup PWR_SLEEP_mode_entry 
+  * @{
+  */
+
+#define PWR_SLEEPEntry_WFI              ((uint8_t)0x01)
+#define PWR_SLEEPEntry_WFE              ((uint8_t)0x02)
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))
+ 
+/**
+  * @}
+  */
+
+/** @defgroup PWR_STOP_mode_entry 
+  * @{
+  */
+
+#define PWR_STOPEntry_WFI               ((uint8_t)0x01)
+#define PWR_STOPEntry_WFE               ((uint8_t)0x02)
+#define PWR_STOPEntry_SLEEPONEXIT       ((uint8_t)0x03)
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE) ||\
+                                  ((ENTRY) == PWR_STOPEntry_SLEEPONEXIT))
+ 
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Flag 
+  * @{
+  */
+
+#define PWR_FLAG_WU                     PWR_CSR_WUF
+#define PWR_FLAG_SB                     PWR_CSR_SBF
+#define PWR_FLAG_PVDO                   PWR_CSR_PVDO /*!< Not applicable for STM32F030 devices */
+#define PWR_FLAG_VREFINTRDY             PWR_CSR_VREFINTRDYF 
+
+#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
+                               ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY))
+
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the PWR configuration to the default reset state ******/
+void PWR_DeInit(void);
+
+/* Backup Domain Access function **********************************************/
+void PWR_BackupAccessCmd(FunctionalState NewState);
+
+/* PVD configuration functions ************************************************/
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); /*!< only applicable for STM32F051 and STM32F072 devices */
+void PWR_PVDCmd(FunctionalState NewState); /*!< only applicable for STM32F051 and STM32F072 devices */
+
+/* WakeUp pins configuration functions ****************************************/
+void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);
+
+/* Low Power modes configuration functions ************************************/
+void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry);
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+void PWR_EnterSTANDBYMode(void);
+
+/* Flags management functions *************************************************/
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
+void PWR_ClearFlag(uint32_t PWR_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0XX_PWR_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_rcc.h b/system/include/stm32f0-stdperiph/stm32f0xx_rcc.h

new file mode 100644 (file)

index 0000000..380f98d
--- /dev/null
+++ b/system/include/stm32f0-stdperiph/stm32f0xx_rcc.h
@@ -0,0 +1,624 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_rcc.h
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file contains all the functions prototypes for the RCC 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_RCC_H
+#define __STM32F0XX_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup RCC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+typedef struct
+{
+  uint32_t SYSCLK_Frequency;
+  uint32_t HCLK_Frequency;
+  uint32_t PCLK_Frequency;
+  uint32_t ADCCLK_Frequency;
+  uint32_t CECCLK_Frequency;
+  uint32_t I2C1CLK_Frequency;
+  uint32_t USART1CLK_Frequency;
+  uint32_t USART2CLK_Frequency; /*!< Only applicable for STM32F072 and STM32F091 devices */
+  uint32_t USART3CLK_Frequency; /*!< Only applicable for STM32F091 devices */
+  uint32_t USBCLK_Frequency;    /*!< Only applicable for STM32F072 devices */
+}RCC_ClocksTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup RCC_HSE_configuration 
+  * @{
+  */
+
+#define RCC_HSE_OFF                      ((uint8_t)0x00)
+#define RCC_HSE_ON                       ((uint8_t)0x01)
+#define RCC_HSE_Bypass                   ((uint8_t)0x05)
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+                         ((HSE) == RCC_HSE_Bypass))
+
+/**
+  * @}
+  */ 
+ 
+/** @defgroup RCC_PLL_Clock_Source 
+  * @{
+  */
+
+#define RCC_PLLSource_HSI_Div2           RCC_CFGR_PLLSRC_HSI_Div2
+#define RCC_PLLSource_PREDIV1            RCC_CFGR_PLLSRC_HSE_PREDIV /* Old HSEPREDIV1 bit definition, maintained for legacy purpose */
+#define RCC_PLLSource_HSE                RCC_CFGR_PLLSRC_HSE_PREDIV /*!< Only applicable for STM32F072 devices */
+#define RCC_PLLSource_HSI48              RCC_CFGR_PLLSRC_HSI48_PREDIV /*!< Only applicable for STM32F072 devices */
+#define RCC_PLLSource_HSI                RCC_CFGR_PLLSRC_HSI_PREDIV /*!< Only applicable for STM32F072 devices */
+
+#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
+                                   ((SOURCE) == RCC_PLLSource_HSI48)    || \
+                                   ((SOURCE) == RCC_PLLSource_HSI)      || \
+                                   ((SOURCE) == RCC_PLLSource_HSE)      || \
+                                   ((SOURCE) == RCC_PLLSource_PREDIV1))
+/**
+  * @}
+  */ 
+
+/** @defgroup RCC_PLL_Multiplication_Factor 
+  * @{
+  */
+
+#define RCC_PLLMul_2                    RCC_CFGR_PLLMULL2
+#define RCC_PLLMul_3                    RCC_CFGR_PLLMULL3
+#define RCC_PLLMul_4                    RCC_CFGR_PLLMULL4
+#define RCC_PLLMul_5                    RCC_CFGR_PLLMULL5
+#define RCC_PLLMul_6                    RCC_CFGR_PLLMULL6
+#define RCC_PLLMul_7                    RCC_CFGR_PLLMULL7
+#define RCC_PLLMul_8                    RCC_CFGR_PLLMULL8
+#define RCC_PLLMul_9                    RCC_CFGR_PLLMULL9
+#define RCC_PLLMul_10                   RCC_CFGR_PLLMULL10
+#define RCC_PLLMul_11                   RCC_CFGR_PLLMULL11
+#define RCC_PLLMul_12                   RCC_CFGR_PLLMULL12
+#define RCC_PLLMul_13                   RCC_CFGR_PLLMULL13
+#define RCC_PLLMul_14                   RCC_CFGR_PLLMULL14
+#define RCC_PLLMul_15                   RCC_CFGR_PLLMULL15
+#define RCC_PLLMul_16                   RCC_CFGR_PLLMULL16
+#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3)   || \
+                             ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5)   || \
+                             ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7)   || \
+                             ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9)   || \
+                             ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
+                             ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
+                             ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
+                             ((MUL) == RCC_PLLMul_16))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PREDIV1_division_factor
+  * @{
+  */
+#define  RCC_PREDIV1_Div1               RCC_CFGR2_PREDIV1_DIV1
+#define  RCC_PREDIV1_Div2               RCC_CFGR2_PREDIV1_DIV2
+#define  RCC_PREDIV1_Div3               RCC_CFGR2_PREDIV1_DIV3
+#define  RCC_PREDIV1_Div4               RCC_CFGR2_PREDIV1_DIV4
+#define  RCC_PREDIV1_Div5               RCC_CFGR2_PREDIV1_DIV5
+#define  RCC_PREDIV1_Div6               RCC_CFGR2_PREDIV1_DIV6
+#define  RCC_PREDIV1_Div7               RCC_CFGR2_PREDIV1_DIV7
+#define  RCC_PREDIV1_Div8               RCC_CFGR2_PREDIV1_DIV8
+#define  RCC_PREDIV1_Div9               RCC_CFGR2_PREDIV1_DIV9
+#define  RCC_PREDIV1_Div10              RCC_CFGR2_PREDIV1_DIV10
+#define  RCC_PREDIV1_Div11              RCC_CFGR2_PREDIV1_DIV11
+#define  RCC_PREDIV1_Div12              RCC_CFGR2_PREDIV1_DIV12
+#define  RCC_PREDIV1_Div13              RCC_CFGR2_PREDIV1_DIV13
+#define  RCC_PREDIV1_Div14              RCC_CFGR2_PREDIV1_DIV14
+#define  RCC_PREDIV1_Div15              RCC_CFGR2_PREDIV1_DIV15
+#define  RCC_PREDIV1_Div16              RCC_CFGR2_PREDIV1_DIV16
+
+#define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
+                                 ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
+                                 ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
+                                 ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
+                                 ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
+                                 ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
+                                 ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
+                                 ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
+/**
+  * @}
+  */
+ 
+/** @defgroup RCC_System_Clock_Source 
+  * @{
+  */
+
+#define RCC_SYSCLKSource_HSI             RCC_CFGR_SW_HSI
+#define RCC_SYSCLKSource_HSE             RCC_CFGR_SW_HSE
+#define RCC_SYSCLKSource_PLLCLK          RCC_CFGR_SW_PLL
+#define RCC_SYSCLKSource_HSI48           RCC_CFGR_SW_HSI48 /*!< Only applicable for STM32F072 devices */
+
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI)   || \
+                                      ((SOURCE) == RCC_SYSCLKSource_HSE)   || \
+                                      ((SOURCE) == RCC_SYSCLKSource_HSI48) || \
+                                      ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB_Clock_Source
+  * @{
+  */
+
+#define RCC_SYSCLK_Div1                  RCC_CFGR_HPRE_DIV1
+#define RCC_SYSCLK_Div2                  RCC_CFGR_HPRE_DIV2
+#define RCC_SYSCLK_Div4                  RCC_CFGR_HPRE_DIV4
+#define RCC_SYSCLK_Div8                  RCC_CFGR_HPRE_DIV8
+#define RCC_SYSCLK_Div16                 RCC_CFGR_HPRE_DIV16
+#define RCC_SYSCLK_Div64                 RCC_CFGR_HPRE_DIV64
+#define RCC_SYSCLK_Div128                RCC_CFGR_HPRE_DIV128
+#define RCC_SYSCLK_Div256                RCC_CFGR_HPRE_DIV256
+#define RCC_SYSCLK_Div512                RCC_CFGR_HPRE_DIV512
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
+                           ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
+                           ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
+                           ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
+                           ((HCLK) == RCC_SYSCLK_Div512))
+/**
+  * @}
+  */ 
+
+/** @defgroup RCC_APB_Clock_Source
+  * @{
+  */
+
+#define RCC_HCLK_Div1                    RCC_CFGR_PPRE_DIV1
+#define RCC_HCLK_Div2                    RCC_CFGR_PPRE_DIV2
+#define RCC_HCLK_Div4                    RCC_CFGR_PPRE_DIV4
+#define RCC_HCLK_Div8                    RCC_CFGR_PPRE_DIV8
+#define RCC_HCLK_Div16                   RCC_CFGR_PPRE_DIV16
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
+                           ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
+                           ((PCLK) == RCC_HCLK_Div16))
+/**
+  * @}
+  */
+  
+/** @defgroup RCC_ADC_clock_source 
+  * @{
+  */
+/* These defines are obsolete and kept for legacy purpose only.
+Proper ADC clock selection is done within ADC driver by mean of the ADC_ClockModeConfig() function */
+#define RCC_ADCCLK_HSI14                 ((uint32_t)0x00000000)
+#define RCC_ADCCLK_PCLK_Div2             ((uint32_t)0x01000000)
+#define RCC_ADCCLK_PCLK_Div4             ((uint32_t)0x01004000)
+
+#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADCCLK_HSI14) || ((ADCCLK) == RCC_ADCCLK_PCLK_Div2) || \
+                               ((ADCCLK) == RCC_ADCCLK_PCLK_Div4))
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_CEC_clock_source 
+  * @{
+  */
+
+#define RCC_CECCLK_HSI_Div244            ((uint32_t)0x00000000)
+#define RCC_CECCLK_LSE                   RCC_CFGR3_CECSW
+
+#define IS_RCC_CECCLK(CECCLK) (((CECCLK) == RCC_CECCLK_HSI_Div244) || ((CECCLK) == RCC_CECCLK_LSE))
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_I2C_clock_source 
+  * @{
+  */
+
+#define RCC_I2C1CLK_HSI                   ((uint32_t)0x00000000)
+#define RCC_I2C1CLK_SYSCLK                RCC_CFGR3_I2C1SW
+
+#define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK))
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_USB_clock_source
+  * @brief    Applicable only for STM32F072 devices
+  * @{
+  */
+
+#define RCC_USBCLK_HSI48                 ((uint32_t)0x00000000)
+#define RCC_USBCLK_PLLCLK                RCC_CFGR3_USBSW
+
+#define IS_RCC_USBCLK(USBCLK) (((USBCLK) == RCC_USBCLK_HSI48) || ((USBCLK) == RCC_USBCLK_PLLCLK))
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_USART_clock_source 
+  * @{
+  */
+
+#define RCC_USART1CLK_PCLK                  ((uint32_t)0x10000000)
+#define RCC_USART1CLK_SYSCLK                ((uint32_t)0x10000001)
+#define RCC_USART1CLK_LSE                   ((uint32_t)0x10000002)
+#define RCC_USART1CLK_HSI                   ((uint32_t)0x10000003)
+
+#define RCC_USART2CLK_PCLK                  ((uint32_t)0x20000000) /*!< Only applicable for STM32F072 and STM32F091 devices */
+#define RCC_USART2CLK_SYSCLK                ((uint32_t)0x20010000) /*!< Only applicable for STM32F072 and STM32F091 devices */
+#define RCC_USART2CLK_LSE                   ((uint32_t)0x20020000) /*!< Only applicable for STM32F072 and STM32F091 devices */
+#define RCC_USART2CLK_HSI                   ((uint32_t)0x20030000) /*!< Only applicable for STM32F072 and STM32F091 devices */
+
+#define RCC_USART3CLK_PCLK                  ((uint32_t)0x30000000) /*!< Only applicable for STM32F091 devices */
+#define RCC_USART3CLK_SYSCLK                ((uint32_t)0x30040000) /*!< Only applicable for STM32F091 devices */
+#define RCC_USART3CLK_LSE                   ((uint32_t)0x30080000) /*!< Only applicable for STM32F091 devices */
+#define RCC_USART3CLK_HSI                   ((uint32_t)0x300C0000) /*!< Only applicable for STM32F091 devices */
+
+
+#define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK)   || \
+                                   ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \
+                                   ((USARTCLK) == RCC_USART1CLK_LSE)    || \
+                                   ((USARTCLK) == RCC_USART1CLK_HSI)    || \
+                                   ((USARTCLK) == RCC_USART2CLK_PCLK)   || \
+                                   ((USARTCLK) == RCC_USART2CLK_SYSCLK) || \
+                                   ((USARTCLK) == RCC_USART2CLK_LSE)    || \
+                                   ((USARTCLK) == RCC_USART2CLK_HSI)|| \
+                                   ((USARTCLK) == RCC_USART3CLK_PCLK)   || \
+                                   ((USARTCLK) == RCC_USART3CLK_SYSCLK) || \
+                                   ((USARTCLK) == RCC_USART3CLK_LSE)    || \
+                                   ((USARTCLK) == RCC_USART3CLK_HSI))
+
+/**
+  * @}
+  */
+         
+/** @defgroup RCC_Interrupt_Source 
+  * @{
+  */
+
+#define RCC_IT_LSIRDY                    ((uint8_t)0x01)
+#define RCC_IT_LSERDY                    ((uint8_t)0x02)
+#define RCC_IT_HSIRDY                    ((uint8_t)0x04)
+#define RCC_IT_HSERDY                    ((uint8_t)0x08)
+#define RCC_IT_PLLRDY                    ((uint8_t)0x10)
+#define RCC_IT_HSI14RDY                  ((uint8_t)0x20)
+#define RCC_IT_HSI48RDY                  ((uint8_t)0x40) /*!< Only applicable for STM32F072 devices */
+#define RCC_IT_CSS                       ((uint8_t)0x80)
+
+#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
+
+#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
+                           ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
+                           ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_HSI14RDY) || \
+                           ((IT) == RCC_IT_CSS)    || ((IT) == RCC_IT_HSI48RDY))
+
+#define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)
+
+/**
+  * @}
+  */
+  
+/** @defgroup RCC_LSE_Configuration 
+  * @{
+  */
+
+#define RCC_LSE_OFF                      ((uint32_t)0x00000000)
+#define RCC_LSE_ON                       RCC_BDCR_LSEON
+#define RCC_LSE_Bypass                   ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP))
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+                         ((LSE) == RCC_LSE_Bypass))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_RTC_Clock_Source
+  * @{
+  */
+
+#define RCC_RTCCLKSource_LSE             RCC_BDCR_RTCSEL_LSE
+#define RCC_RTCCLKSource_LSI             RCC_BDCR_RTCSEL_LSI
+#define RCC_RTCCLKSource_HSE_Div32       RCC_BDCR_RTCSEL_HSE
+
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_LSI) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div32))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSE_Drive_Configuration 
+  * @{
+  */
+
+#define RCC_LSEDrive_Low                 ((uint32_t)0x00000000)
+#define RCC_LSEDrive_MediumLow           RCC_BDCR_LSEDRV_0
+#define RCC_LSEDrive_MediumHigh          RCC_BDCR_LSEDRV_1
+#define RCC_LSEDrive_High                RCC_BDCR_LSEDRV
+#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \
+                                 ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High))
+/**
+  * @}
+  */
+  
+/** @defgroup RCC_AHB_Peripherals 
+  * @{
+  */
+
+#define RCC_AHBPeriph_GPIOA               RCC_AHBENR_GPIOAEN
+#define RCC_AHBPeriph_GPIOB               RCC_AHBENR_GPIOBEN
+#define RCC_AHBPeriph_GPIOC               RCC_AHBENR_GPIOCEN
+#define RCC_AHBPeriph_GPIOD               RCC_AHBENR_GPIODEN
+#define RCC_AHBPeriph_GPIOE               RCC_AHBENR_GPIOEEN /*!< Only applicable for STM32F072 and STM32F091 devices */
+#define RCC_AHBPeriph_GPIOF               RCC_AHBENR_GPIOFEN
+#define RCC_AHBPeriph_TS                  RCC_AHBENR_TSEN
+#define RCC_AHBPeriph_CRC                 RCC_AHBENR_CRCEN
+#define RCC_AHBPeriph_FLITF               RCC_AHBENR_FLITFEN
+#define RCC_AHBPeriph_SRAM                RCC_AHBENR_SRAMEN
+#define RCC_AHBPeriph_DMA1                RCC_AHBENR_DMA1EN
+#define RCC_AHBPeriph_DMA2                RCC_AHBENR_DMA2EN
+
+#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFE81FFA8) == 0x00) && ((PERIPH) != 0x00))
+#define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xFE81FFA8) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Peripherals 
+  * @{
+  */
+
+#define RCC_APB2Periph_SYSCFG            RCC_APB2ENR_SYSCFGEN
+#define RCC_APB2Periph_USART6            RCC_APB2ENR_USART6EN
+#define RCC_APB2Periph_USART7            RCC_APB2ENR_USART7EN
+#define RCC_APB2Periph_USART8            RCC_APB2ENR_USART8EN
+#define RCC_APB2Periph_ADC1              RCC_APB2ENR_ADC1EN
+#define RCC_APB2Periph_TIM1              RCC_APB2ENR_TIM1EN
+#define RCC_APB2Periph_SPI1              RCC_APB2ENR_SPI1EN
+#define RCC_APB2Periph_USART1            RCC_APB2ENR_USART1EN
+#define RCC_APB2Periph_TIM15             RCC_APB2ENR_TIM15EN
+#define RCC_APB2Periph_TIM16             RCC_APB2ENR_TIM16EN
+#define RCC_APB2Periph_TIM17             RCC_APB2ENR_TIM17EN
+#define RCC_APB2Periph_DBGMCU            RCC_APB2ENR_DBGMCUEN
+
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFB8A51E) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RCC_APB1_Peripherals 
+  * @{
+  */
+
+#define RCC_APB1Periph_TIM2              RCC_APB1ENR_TIM2EN    /*!< Only applicable for STM32F051, STM32F072 and STM32F091 devices */
+#define RCC_APB1Periph_TIM3              RCC_APB1ENR_TIM3EN
+#define RCC_APB1Periph_TIM6              RCC_APB1ENR_TIM6EN
+#define RCC_APB1Periph_TIM7              RCC_APB1ENR_TIM7EN    /*!< Only applicable for STM32F072 devices */
+#define RCC_APB1Periph_TIM14             RCC_APB1ENR_TIM14EN
+#define RCC_APB1Periph_WWDG              RCC_APB1ENR_WWDGEN
+#define RCC_APB1Periph_SPI2              RCC_APB1ENR_SPI2EN
+#define RCC_APB1Periph_USART2            RCC_APB1ENR_USART2EN
+#define RCC_APB1Periph_USART3            RCC_APB1ENR_USART3EN  /*!< Only applicable for STM32F072 and STM32F091 devices */
+#define RCC_APB1Periph_USART4            RCC_APB1ENR_USART4EN  /*!< Only applicable for STM32F072 and STM32F091 devices */
+#define RCC_APB1Periph_USART5            RCC_APB1ENR_USART5EN  /*!< Only applicable for STM32F091 devices */
+#define RCC_APB1Periph_I2C1              RCC_APB1ENR_I2C1EN
+#define RCC_APB1Periph_I2C2              RCC_APB1ENR_I2C2EN
+#define RCC_APB1Periph_USB               RCC_APB1ENR_USBEN     /*!< Only applicable for STM32F072 and STM32F042 devices */
+#define RCC_APB1Periph_CAN               RCC_APB1ENR_CANEN     /*!< Only applicable for STM32F072, STM32F042 and STM32F091 devices */
+#define RCC_APB1Periph_CRS               RCC_APB1ENR_CRSEN     /*!< Only applicable for STM32F072, STM32F042 and STM32F091 devices */
+#define RCC_APB1Periph_PWR               RCC_APB1ENR_PWREN
+#define RCC_APB1Periph_DAC               RCC_APB1ENR_DACEN     /*!< Only applicable for STM32F051, STM32F072 and STM32F091 devices */
+#define RCC_APB1Periph_CEC               RCC_APB1ENR_CECEN     /*!< Only applicable for STM32F051, STM32F042, STM32F072 and STM32F091 devices */
+
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x8581B6CC) == 0x00) && ((PERIPH) != 0x00))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCO_Clock_Source
+  * @{
+  */
+
+#define RCC_MCOSource_NoClock            ((uint8_t)0x00)
+#define RCC_MCOSource_HSI14              ((uint8_t)0x01)
+#define RCC_MCOSource_LSI                ((uint8_t)0x02)
+#define RCC_MCOSource_LSE                ((uint8_t)0x03)
+#define RCC_MCOSource_SYSCLK             ((uint8_t)0x04)
+#define RCC_MCOSource_HSI                ((uint8_t)0x05)
+#define RCC_MCOSource_HSE                ((uint8_t)0x06)
+#define RCC_MCOSource_PLLCLK_Div2        ((uint8_t)0x07)
+#define RCC_MCOSource_HSI48              ((uint8_t)0x08)  /*!< Only applicable for STM32F072 devices */
+#define RCC_MCOSource_PLLCLK             ((uint8_t)0x87)
+
+#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_HSI14)      || \
+                                   ((SOURCE) == RCC_MCOSource_SYSCLK)  || ((SOURCE) == RCC_MCOSource_HSI)        || \
+                                   ((SOURCE) == RCC_MCOSource_HSE)     || ((SOURCE) == RCC_MCOSource_PLLCLK_Div2)|| \
+                                   ((SOURCE) == RCC_MCOSource_LSI)     || ((SOURCE) == RCC_MCOSource_HSI48)      || \
+                                   ((SOURCE) == RCC_MCOSource_PLLCLK)  || ((SOURCE) == RCC_MCOSource_LSE))
+/**
+  * @}
+  */ 
+
+/** @defgroup RCC_MCOPrescaler
+  * @{
+  */
+#if !defined (STM32F051)
+#define RCC_MCOPrescaler_1            RCC_CFGR_MCO_PRE_1
+#define RCC_MCOPrescaler_2            RCC_CFGR_MCO_PRE_2
+#define RCC_MCOPrescaler_4            RCC_CFGR_MCO_PRE_4
+#define RCC_MCOPrescaler_8            RCC_CFGR_MCO_PRE_8
+#define RCC_MCOPrescaler_16           RCC_CFGR_MCO_PRE_16
+#define RCC_MCOPrescaler_32           RCC_CFGR_MCO_PRE_32
+#define RCC_MCOPrescaler_64           RCC_CFGR_MCO_PRE_64
+#define RCC_MCOPrescaler_128          RCC_CFGR_MCO_PRE_128
+
+#define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1)  || \
+                                         ((PRESCALER) == RCC_MCOPrescaler_2)  || \
+                                         ((PRESCALER) == RCC_MCOPrescaler_4)  || \
+                                         ((PRESCALER) == RCC_MCOPrescaler_8)  || \
+                                         ((PRESCALER) == RCC_MCOPrescaler_16) || \
+                                         ((PRESCALER) == RCC_MCOPrescaler_32) || \
+                                         ((PRESCALER) == RCC_MCOPrescaler_64) || \
+                                         ((PRESCALER) == RCC_MCOPrescaler_128))
+#endif /* STM32F051 */                                         
+/**
+  * @}
+  */ 
+
+/** @defgroup RCC_Flag 
+  * @{
+  */
+#define RCC_FLAG_HSIRDY                  ((uint8_t)0x01)
+#define RCC_FLAG_HSERDY                  ((uint8_t)0x11)
+#define RCC_FLAG_PLLRDY                  ((uint8_t)0x19)
+#define RCC_FLAG_LSERDY                  ((uint8_t)0x21)
+#define RCC_FLAG_LSIRDY                  ((uint8_t)0x41)
+#define RCC_FLAG_V18PWRRSTF              ((uint8_t)0x57)
+#define RCC_FLAG_OBLRST                  ((uint8_t)0x59)
+#define RCC_FLAG_PINRST                  ((uint8_t)0x5A)
+#define RCC_FLAG_PORRST                  ((uint8_t)0x5B)
+#define RCC_FLAG_SFTRST                  ((uint8_t)0x5C)
+#define RCC_FLAG_IWDGRST                 ((uint8_t)0x5D)
+#define RCC_FLAG_WWDGRST                 ((uint8_t)0x5E)
+#define RCC_FLAG_LPWRRST                 ((uint8_t)0x5F)
+#define RCC_FLAG_HSI14RDY                ((uint8_t)0x61)
+#define RCC_FLAG_HSI48RDY                ((uint8_t)0x71) /*!< Only applicable for STM32F072 devices */ 
+
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)  || ((FLAG) == RCC_FLAG_HSERDY)  || \
+                           ((FLAG) == RCC_FLAG_PLLRDY)  || ((FLAG) == RCC_FLAG_LSERDY)  || \
+                           ((FLAG) == RCC_FLAG_LSIRDY)  || ((FLAG) == RCC_FLAG_OBLRST)  || \
+                           ((FLAG) == RCC_FLAG_PINRST)  || ((FLAG) == RCC_FLAG_PORRST)  || \
+                           ((FLAG) == RCC_FLAG_SFTRST)  || ((FLAG) == RCC_FLAG_IWDGRST) || \
+                           ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST) || \
+                           ((FLAG) == RCC_FLAG_HSI14RDY)|| ((FLAG) == RCC_FLAG_HSI48RDY)|| \
+                           ((FLAG) == RCC_FLAG_V18PWRRSTF))
+
+#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+#define IS_RCC_HSI14_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the RCC clock configuration to the default reset state */
+void RCC_DeInit(void);
+
+/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
+void RCC_HSEConfig(uint8_t RCC_HSE);
+ErrorStatus RCC_WaitForHSEStartUp(void);
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
+void RCC_HSICmd(FunctionalState NewState);
+void RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue);
+void RCC_HSI14Cmd(FunctionalState NewState);
+void RCC_HSI14ADCRequestCmd(FunctionalState NewState);
+void RCC_LSEConfig(uint32_t RCC_LSE);
+void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive);
+void RCC_LSICmd(FunctionalState NewState);
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
+void RCC_PLLCmd(FunctionalState NewState);
+void RCC_HSI48Cmd(FunctionalState NewState); /*!< Only applicable for STM32F072 devices */
+uint32_t RCC_GetHSI48CalibrationValue(void); /*!< Only applicable for STM32F072 devices */
+void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div);
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
+#ifdef STM32F051
+void RCC_MCOConfig(uint8_t RCC_MCOSource);
+#else
+void RCC_MCOConfig(uint8_t RCC_MCOSource,uint32_t RCC_MCOPrescaler);
+#endif /* STM32F051 */
+
+/* System, AHB and APB busses clocks configuration functions ******************/
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
+uint8_t RCC_GetSYSCLKSource(void);
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
+void RCC_PCLKConfig(uint32_t RCC_HCLK);
+void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK); /* This function is obsolete.
+                                               For proper ADC clock selection, refer to
+                                               ADC_ClockModeConfig() in the ADC driver */
+void RCC_CECCLKConfig(uint32_t RCC_CECCLK);
+void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK);
+void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK);
+void RCC_USBCLKConfig(uint32_t RCC_USBCLK); /*!< Only applicable for STM32F042 and STM32F072 devices */
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
+
+/* Peripheral clocks configuration functions **********************************/
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
+void RCC_RTCCLKCmd(FunctionalState NewState);
+void RCC_BackupResetCmd(FunctionalState NewState);
+
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
+void RCC_ClearFlag(void);
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);
+void RCC_ClearITPendingBit(uint8_t RCC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0XX_RCC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_rtc.h b/system/include/stm32f0-stdperiph/stm32f0xx_rtc.h

new file mode 100644 (file)

index 0000000..60aa00c
--- /dev/null
+++ b/system/include/stm32f0-stdperiph/stm32f0xx_rtc.h
@@ -0,0 +1,807 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_rtc.h
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file contains all the functions prototypes for the RTC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_RTC_H
+#define __STM32F0XX_RTC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup RTC
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  RTC Init structures definition  
+  */ 
+typedef struct
+{
+  uint32_t RTC_HourFormat;   /*!< Specifies the RTC Hour Format.
+                             This parameter can be a value of @ref RTC_Hour_Formats */
+  
+  uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
+                             This parameter must be set to a value lower than 0x7F */
+  
+  uint32_t RTC_SynchPrediv;  /*!< Specifies the RTC Synchronous Predivider value.
+                             This parameter must be set to a value lower than 0x1FFF */
+}RTC_InitTypeDef;
+
+/** 
+  * @brief  RTC Time structure definition  
+  */
+typedef struct
+{
+  uint8_t RTC_Hours;    /*!< Specifies the RTC Time Hour.
+                        This parameter must be set to a value in the 0-12 range
+                        if the RTC_HourFormat_12 is selected or 0-23 range if
+                        the RTC_HourFormat_24 is selected. */
+
+  uint8_t RTC_Minutes;  /*!< Specifies the RTC Time Minutes.
+                        This parameter must be set to a value in the 0-59 range. */
+  
+  uint8_t RTC_Seconds;  /*!< Specifies the RTC Time Seconds.
+                        This parameter must be set to a value in the 0-59 range. */
+
+  uint8_t RTC_H12;      /*!< Specifies the RTC AM/PM Time.
+                        This parameter can be a value of @ref RTC_AM_PM_Definitions */
+}RTC_TimeTypeDef; 
+
+/** 
+  * @brief  RTC Date structure definition  
+  */
+typedef struct
+{
+  uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.
+                        This parameter can be a value of @ref RTC_WeekDay_Definitions */
+  
+  uint8_t RTC_Month;   /*!< Specifies the RTC Date Month.
+                        This parameter can be a value of @ref RTC_Month_Date_Definitions */
+
+  uint8_t RTC_Date;     /*!< Specifies the RTC Date.
+                        This parameter must be set to a value in the 1-31 range. */
+  
+  uint8_t RTC_Year;     /*!< Specifies the RTC Date Year.
+                        This parameter must be set to a value in the 0-99 range. */
+}RTC_DateTypeDef;
+
+/** 
+  * @brief  RTC Alarm structure definition  
+  */
+typedef struct
+{
+  RTC_TimeTypeDef RTC_AlarmTime;     /*!< Specifies the RTC Alarm Time members. */
+
+  uint32_t RTC_AlarmMask;            /*!< Specifies the RTC Alarm Masks.
+                                     This parameter can be a value of @ref RTC_AlarmMask_Definitions */
+
+  uint32_t RTC_AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
+                                     This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
+  
+  uint8_t RTC_AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
+                                     This parameter must be set to a value in the 1-31 range 
+                                     if the Alarm Date is selected.
+                                     This parameter can be a value of @ref RTC_WeekDay_Definitions 
+                                     if the Alarm WeekDay is selected. */
+}RTC_AlarmTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RTC_Exported_Constants
+  * @{
+  */ 
+
+
+/** @defgroup RTC_Hour_Formats 
+  * @{
+  */ 
+#define RTC_HourFormat_24              ((uint32_t)0x00000000)
+#define RTC_HourFormat_12              ((uint32_t)0x00000040)
+#define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HourFormat_12) || \
+                                        ((FORMAT) == RTC_HourFormat_24))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Asynchronous_Predivider 
+  * @{
+  */ 
+#define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= 0x7F)
+ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_Synchronous_Predivider 
+  * @{
+  */ 
+#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= 0x7FFF)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Time_Definitions 
+  * @{
+  */ 
+#define IS_RTC_HOUR12(HOUR)            (((HOUR) > 0) && ((HOUR) <= 12))
+#define IS_RTC_HOUR24(HOUR)            ((HOUR) <= 23)
+#define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= 59)
+#define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= 59)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_AM_PM_Definitions 
+  * @{
+  */ 
+#define RTC_H12_AM                     ((uint8_t)0x00)
+#define RTC_H12_PM                     ((uint8_t)0x40)
+#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Year_Date_Definitions 
+  * @{
+  */ 
+#define IS_RTC_YEAR(YEAR)              ((YEAR) <= 99)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Month_Date_Definitions 
+  * @{
+  */ 
+#define RTC_Month_January              ((uint8_t)0x01)
+#define RTC_Month_February             ((uint8_t)0x02)
+#define RTC_Month_March                ((uint8_t)0x03)
+#define RTC_Month_April                ((uint8_t)0x04)
+#define RTC_Month_May                  ((uint8_t)0x05)
+#define RTC_Month_June                 ((uint8_t)0x06)
+#define RTC_Month_July                 ((uint8_t)0x07)
+#define RTC_Month_August               ((uint8_t)0x08)
+#define RTC_Month_September            ((uint8_t)0x09)
+#define RTC_Month_October              ((uint8_t)0x10)
+#define RTC_Month_November             ((uint8_t)0x11)
+#define RTC_Month_December             ((uint8_t)0x12)
+#define IS_RTC_MONTH(MONTH)            (((MONTH) >= 1) && ((MONTH) <= 12))
+#define IS_RTC_DATE(DATE)              (((DATE) >= 1) && ((DATE) <= 31))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_WeekDay_Definitions 
+  * @{
+  */ 
+  
+#define        RTC_Weekday_Monday             ((uint8_t)0x01)
+#define        RTC_Weekday_Tuesday            ((uint8_t)0x02)
+#define        RTC_Weekday_Wednesday          ((uint8_t)0x03)
+#define        RTC_Weekday_Thursday           ((uint8_t)0x04)
+#define        RTC_Weekday_Friday             ((uint8_t)0x05)
+#define        RTC_Weekday_Saturday           ((uint8_t)0x6)
+#define        RTC_Weekday_Sunday             ((uint8_t)0x07)
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Tuesday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Wednesday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Thursday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Friday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Saturday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Sunday))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_Alarm_Definitions 
+  * @{
+  */ 
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Tuesday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Wednesday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Thursday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Friday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Saturday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Sunday))
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_AlarmDateWeekDay_Definitions 
+  * @{
+  */ 
+#define RTC_AlarmDateWeekDaySel_Date      ((uint32_t)0x00000000)  
+#define RTC_AlarmDateWeekDaySel_WeekDay   ((uint32_t)0x40000000)  
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
+                                            ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_AlarmMask_Definitions 
+  * @{
+  */ 
+#define RTC_AlarmMask_None                ((uint32_t)0x00000000)
+#define RTC_AlarmMask_DateWeekDay         ((uint32_t)0x80000000)  
+#define RTC_AlarmMask_Hours               ((uint32_t)0x00800000)
+#define RTC_AlarmMask_Minutes             ((uint32_t)0x00008000)
+#define RTC_AlarmMask_Seconds             ((uint32_t)0x00000080)
+#define RTC_AlarmMask_All                 ((uint32_t)0x80808080)
+#define IS_RTC_ALARM_MASK(MASK)  (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Alarms_Definitions 
+  * @{
+  */ 
+#define RTC_Alarm_A                       ((uint32_t)0x00000100)
+#define IS_RTC_ALARM(ALARM)      ((ALARM) == RTC_Alarm_A)
+#define IS_RTC_CMD_ALARM(ALARM)  (((ALARM) & (RTC_Alarm_A)) != (uint32_t)RESET)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Alarm_Sub_Seconds_Masks Definitions.
+  * @{
+  */ 
+#define RTC_AlarmSubSecondMask_All         ((uint8_t)0x00) /*!< All Alarm SS fields are masked. 
+                                                                There is no comparison on sub seconds 
+                                                                for Alarm */
+#define RTC_AlarmSubSecondMask_SS14_1      ((uint8_t)0x01) /*!< SS[14:1] are don't care in Alarm 
+                                                                comparison. Only SS[0] is compared. */
+#define RTC_AlarmSubSecondMask_SS14_2      ((uint8_t)0x02) /*!< SS[14:2] are don't care in Alarm 
+                                                                comparison. Only SS[1:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_3      ((uint8_t)0x03) /*!< SS[14:3] are don't care in Alarm 
+                                                                comparison. Only SS[2:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_4      ((uint8_t)0x04) /*!< SS[14:4] are don't care in Alarm 
+                                                                comparison. Only SS[3:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_5      ((uint8_t)0x05) /*!< SS[14:5] are don't care in Alarm 
+                                                                comparison. Only SS[4:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_6      ((uint8_t)0x06) /*!< SS[14:6] are don't care in Alarm 
+                                                                comparison. Only SS[5:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_7      ((uint8_t)0x07) /*!< SS[14:7] are don't care in Alarm 
+                                                                comparison. Only SS[6:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_8      ((uint8_t)0x08) /*!< SS[14:8] are don't care in Alarm 
+                                                                comparison. Only SS[7:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_9      ((uint8_t)0x09) /*!< SS[14:9] are don't care in Alarm 
+                                                                comparison. Only SS[8:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_10     ((uint8_t)0x0A) /*!< SS[14:10] are don't care in Alarm 
+                                                                comparison. Only SS[9:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_11     ((uint8_t)0x0B) /*!< SS[14:11] are don't care in Alarm 
+                                                                comparison. Only SS[10:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_12     ((uint8_t)0x0C) /*!< SS[14:12] are don't care in Alarm 
+                                                                comparison.Only SS[11:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_13     ((uint8_t)0x0D) /*!< SS[14:13] are don't care in Alarm 
+                                                                comparison. Only SS[12:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14        ((uint8_t)0x0E) /*!< SS[14] is don't care in Alarm 
+                                                                comparison.Only SS[13:0] are compared */
+#define RTC_AlarmSubSecondMask_None        ((uint8_t)0x0F) /*!< SS[14:0] are compared and must match 
+                                                                to activate alarm. */
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)   (((MASK) == RTC_AlarmSubSecondMask_All) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_None))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Alarm_Sub_Seconds_Value
+  * @{
+  */ 
+  
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Wakeup_Timer_Definitions 
+  * @brief    These parameters are only available for STM32F072 devices
+  * @{
+  */
+#define RTC_WakeUpClock_RTCCLK_Div16        ((uint32_t)0x00000000)
+#define RTC_WakeUpClock_RTCCLK_Div8         ((uint32_t)0x00000001)
+#define RTC_WakeUpClock_RTCCLK_Div4         ((uint32_t)0x00000002)
+#define RTC_WakeUpClock_RTCCLK_Div2         ((uint32_t)0x00000003)
+#define RTC_WakeUpClock_CK_SPRE_16bits      ((uint32_t)0x00000004)
+#define RTC_WakeUpClock_CK_SPRE_17bits      ((uint32_t)0x00000006)
+#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \
+                                    ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \
+                                    ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \
+                                    ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \
+                                    ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \
+                                    ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))
+#define IS_RTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= 0xFFFF)
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Time_Stamp_Edges_definitions 
+  * @{
+  */ 
+#define RTC_TimeStampEdge_Rising          ((uint32_t)0x00000000)
+#define RTC_TimeStampEdge_Falling         ((uint32_t)0x00000008)
+#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \
+                                     ((EDGE) == RTC_TimeStampEdge_Falling))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Output_selection_Definitions 
+  * @{
+  */ 
+#define RTC_Output_Disable             ((uint32_t)0x00000000)
+#define RTC_Output_AlarmA              ((uint32_t)0x00200000)
+#define RTC_Output_WakeUp              ((uint32_t)0x00600000) /*!< available only for STM32F072 devices */
+ 
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \
+                               ((OUTPUT) == RTC_Output_AlarmA)  || \
+                               ((OUTPUT) == RTC_Output_WakeUp))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Output_Polarity_Definitions 
+  * @{
+  */ 
+#define RTC_OutputPolarity_High           ((uint32_t)0x00000000)
+#define RTC_OutputPolarity_Low            ((uint32_t)0x00100000)
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \
+                                ((POL) == RTC_OutputPolarity_Low))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_Calib_Output_selection_Definitions 
+  * @{
+  */ 
+#define RTC_CalibOutput_512Hz            ((uint32_t)0x00000000) 
+#define RTC_CalibOutput_1Hz              ((uint32_t)0x00080000)
+#define IS_RTC_CALIB_OUTPUT(OUTPUT)  (((OUTPUT) == RTC_CalibOutput_512Hz) || \
+                                      ((OUTPUT) == RTC_CalibOutput_1Hz))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Smooth_calib_period_Definitions 
+  * @{
+  */ 
+#define RTC_SmoothCalibPeriod_32sec   ((uint32_t)0x00000000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation
+                                                             period is 32s,  else 2exp20 RTCCLK seconds */
+#define RTC_SmoothCalibPeriod_16sec   ((uint32_t)0x00002000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation 
+                                                             period is 16s, else 2exp19 RTCCLK seconds */
+#define RTC_SmoothCalibPeriod_8sec    ((uint32_t)0x00004000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation 
+                                                             period is 8s, else 2exp18 RTCCLK seconds */
+#define  IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \
+                                             ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \
+                                             ((PERIOD) == RTC_SmoothCalibPeriod_8sec))
+                                          
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions 
+  * @{
+  */ 
+#define RTC_SmoothCalibPlusPulses_Set    ((uint32_t)0x00008000) /*!<  The number of RTCCLK pulses added  
+                                                                during a X -second window = Y - CALM[8:0]. 
+                                                                 with Y = 512, 256, 128 when X = 32, 16, 8 */
+#define RTC_SmoothCalibPlusPulses_Reset  ((uint32_t)0x00000000) /*!<  The number of RTCCLK pulses subbstited
+                                                                 during a 32-second window =   CALM[8:0]. */
+#define  IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \
+                                         ((PLUS) == RTC_SmoothCalibPlusPulses_Reset))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions 
+  * @{
+  */ 
+#define  IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_DayLightSaving_Definitions 
+  * @{
+  */ 
+#define RTC_DayLightSaving_SUB1H   ((uint32_t)0x00020000)
+#define RTC_DayLightSaving_ADD1H   ((uint32_t)0x00010000)
+#define IS_RTC_DAYLIGHT_SAVING(SAVING) (((SAVING) == RTC_DayLightSaving_SUB1H) || \
+                                        ((SAVING) == RTC_DayLightSaving_ADD1H))
+
+#define RTC_StoreOperation_Reset        ((uint32_t)0x00000000)
+#define RTC_StoreOperation_Set          ((uint32_t)0x00040000)
+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \
+                                           ((OPERATION) == RTC_StoreOperation_Set))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Tamper_Trigger_Definitions 
+  * @{
+  */ 
+#define RTC_TamperTrigger_RisingEdge            ((uint32_t)0x00000000)
+#define RTC_TamperTrigger_FallingEdge           ((uint32_t)0x00000001)
+#define RTC_TamperTrigger_LowLevel              ((uint32_t)0x00000000)
+#define RTC_TamperTrigger_HighLevel             ((uint32_t)0x00000001)
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
+                                        ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
+                                        ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
+                                        ((TRIGGER) == RTC_TamperTrigger_HighLevel)) 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Tamper_Filter_Definitions 
+  * @{
+  */ 
+#define RTC_TamperFilter_Disable   ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
+
+#define RTC_TamperFilter_2Sample   ((uint32_t)0x00000800) /*!< Tamper is activated after 2 
+                                                          consecutive samples at the active level */
+#define RTC_TamperFilter_4Sample   ((uint32_t)0x00001000) /*!< Tamper is activated after 4 
+                                                          consecutive samples at the active level */
+#define RTC_TamperFilter_8Sample   ((uint32_t)0x00001800) /*!< Tamper is activated after 8 
+                                                          consecutive samples at the active leve. */
+#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
+                                      ((FILTER) == RTC_TamperFilter_2Sample) || \
+                                      ((FILTER) == RTC_TamperFilter_4Sample) || \
+                                      ((FILTER) == RTC_TamperFilter_8Sample))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions 
+  * @{
+  */ 
+#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
+                                                                      with a frequency =  RTCCLK / 32768 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x00000100) /*!< Each of the tamper inputs are sampled
+                                                                      with a frequency =  RTCCLK / 16384 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div8192  ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
+                                                                      with a frequency =  RTCCLK / 8192  */
+#define RTC_TamperSamplingFreq_RTCCLK_Div4096  ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
+                                                                      with a frequency =  RTCCLK / 4096  */
+#define RTC_TamperSamplingFreq_RTCCLK_Div2048  ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
+                                                                      with a frequency =  RTCCLK / 2048  */
+#define RTC_TamperSamplingFreq_RTCCLK_Div1024  ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
+                                                                      with a frequency =  RTCCLK / 1024  */
+#define RTC_TamperSamplingFreq_RTCCLK_Div512   ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
+                                                                      with a frequency =  RTCCLK / 512   */
+#define RTC_TamperSamplingFreq_RTCCLK_Div256   ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
+                                                                      with a frequency =  RTCCLK / 256   */
+#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
+                                           
+/**
+  * @}
+  */
+
+  /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions 
+  * @{
+  */ 
+#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 1 RTCCLK cycle */
+#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 2 RTCCLK cycles */
+#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 4 RTCCLK cycles */
+#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 8 RTCCLK cycles */
+
+#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
+                                                    ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
+                                                    ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
+                                                    ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Tamper_Pins_Definitions 
+  * @{
+  */ 
+#define RTC_Tamper_1            RTC_TAFCR_TAMP1E /*!< Tamper detection enable for 
+                                                 input tamper 1 */
+#define RTC_Tamper_2            RTC_TAFCR_TAMP2E /*!< Tamper detection enable for 
+                                                 input tamper 2 */
+#define RTC_Tamper_3            RTC_TAFCR_TAMP3E /*!< Tamper detection enable for 
+                                                 input tamper 3, available only 
+                                                 for STM32F072 devices */
+#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Output_Type_ALARM_OUT 
+  * @{
+  */ 
+#define RTC_OutputType_OpenDrain           ((uint32_t)0x00000000)
+#define RTC_OutputType_PushPull            ((uint32_t)0x00040000)
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \
+                                  ((TYPE) == RTC_OutputType_PushPull))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Add_1_Second_Parameter_Definitions
+  * @{
+  */ 
+#define RTC_ShiftAdd1S_Reset      ((uint32_t)0x00000000)
+#define RTC_ShiftAdd1S_Set        ((uint32_t)0x80000000)
+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \
+                                 ((SEL) == RTC_ShiftAdd1S_Set))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Substract_Fraction_Of_Second_Value
+  * @{
+  */ 
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Backup_Registers_Definitions 
+  * @{
+  */
+
+#define RTC_BKP_DR0                       ((uint32_t)0x00000000)
+#define RTC_BKP_DR1                       ((uint32_t)0x00000001)
+#define RTC_BKP_DR2                       ((uint32_t)0x00000002)
+#define RTC_BKP_DR3                       ((uint32_t)0x00000003)
+#define RTC_BKP_DR4                       ((uint32_t)0x00000004)
+#define IS_RTC_BKP(BKP)                   (((BKP) == RTC_BKP_DR0) || \
+                                           ((BKP) == RTC_BKP_DR1) || \
+                                           ((BKP) == RTC_BKP_DR2) || \
+                                           ((BKP) == RTC_BKP_DR3) || \
+                                           ((BKP) == RTC_BKP_DR4)) 
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Input_parameter_format_definitions 
+  * @{
+  */ 
+#define RTC_Format_BIN                    ((uint32_t)0x000000000)
+#define RTC_Format_BCD                    ((uint32_t)0x000000001)
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Flags_Definitions 
+  * @{
+  */ 
+#define RTC_FLAG_RECALPF                  RTC_ISR_RECALPF
+#define RTC_FLAG_TAMP3F                   RTC_ISR_TAMP3F /*!< Only available for STM32F072 devices */
+#define RTC_FLAG_TAMP2F                   RTC_ISR_TAMP2F
+#define RTC_FLAG_TAMP1F                   RTC_ISR_TAMP1F
+#define RTC_FLAG_TSOVF                    RTC_ISR_TSOVF
+#define RTC_FLAG_TSF                      RTC_ISR_TSF
+#define RTC_FLAG_WUTF                     RTC_ISR_WUTF /*!< Only available for STM32F072 devices */
+#define RTC_FLAG_ALRAF                    RTC_ISR_ALRAF
+#define RTC_FLAG_INITF                    RTC_ISR_INITF
+#define RTC_FLAG_RSF                      RTC_ISR_RSF
+#define RTC_FLAG_INITS                    RTC_ISR_INITS
+#define RTC_FLAG_SHPF                     RTC_ISR_SHPF
+#define RTC_FLAG_WUTWF                    RTC_ISR_WUTWF /*!< Only available for STM32F072 devices */
+#define RTC_FLAG_ALRAWF                   RTC_ISR_ALRAWF 
+
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF)  || ((FLAG) == RTC_FLAG_TSF)     || \
+                               ((FLAG) == RTC_FLAG_WUTF)   || ((FLAG) == RTC_FLAG_ALRAWF)  || \
+                               ((FLAG) == RTC_FLAG_ALRAF)  || ((FLAG) == RTC_FLAG_INITF)   || \
+                               ((FLAG) == RTC_FLAG_RSF)    || ((FLAG) == RTC_FLAG_WUTWF)   || \
+                               ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_TAMP2F)  || \
+                               ((FLAG) == RTC_FLAG_TAMP3F) || ((FLAG) == RTC_FLAG_RECALPF) || \
+                               ((FLAG) == RTC_FLAG_SHPF))
+#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF02DF) == (uint32_t)RESET))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Interrupts_Definitions 
+  * @{
+  */ 
+#define RTC_IT_TS                         ((uint32_t)0x00008000)
+#define RTC_IT_WUT                        ((uint32_t)0x00004000) /* Available only for STM32F072 devices */
+#define RTC_IT_ALRA                       ((uint32_t)0x00001000)
+#define RTC_IT_TAMP                       ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
+#define RTC_IT_TAMP1                      ((uint32_t)0x00020000)
+#define RTC_IT_TAMP2                      ((uint32_t)0x00040000)
+#define RTC_IT_TAMP3                      ((uint32_t)0x00080000) /* Available only for STM32F072 devices */
+
+#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF2FFB) == (uint32_t)RESET))
+#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS)    || ((IT) == RTC_IT_ALRA)  || \
+                           ((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_WUT)   || \
+                           ((IT) == RTC_IT_TAMP2) || ((IT) == RTC_IT_TAMP3))                           
+
+#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF12FFF) == (uint32_t)RESET))
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/*  Function used to set the RTC configuration to the default reset state *****/
+ErrorStatus RTC_DeInit(void);
+
+
+/* Initialization and Configuration functions *********************************/
+ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
+void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
+void RTC_WriteProtectionCmd(FunctionalState NewState);
+ErrorStatus RTC_EnterInitMode(void);
+void RTC_ExitInitMode(void);
+ErrorStatus RTC_WaitForSynchro(void);
+ErrorStatus RTC_RefClockCmd(FunctionalState NewState);
+void RTC_BypassShadowCmd(FunctionalState NewState);
+
+/* Time and Date configuration functions **************************************/
+ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
+void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
+uint32_t RTC_GetSubSecond(void);
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
+void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
+
+/* Alarms (Alarm A) configuration functions  **********************************/
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
+void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
+ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);
+void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint8_t RTC_AlarmSubSecondMask);
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
+
+/* WakeUp Timer configuration functions ***************************************/ 
+void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock); /*!< available only for STM32F072 devices */ 
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter); /*!< available only for STM32F072 devices */ 
+uint32_t RTC_GetWakeUpCounter(void); /*!< available only for STM32F072 devices */ 
+ErrorStatus RTC_WakeUpCmd(FunctionalState NewState); /*!< available only for STM32F072 devices */ 
+
+/* Daylight Saving configuration functions ************************************/
+void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
+uint32_t RTC_GetStoreOperation(void);
+
+/* Output pin Configuration function ******************************************/
+void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
+
+/* Digital Calibration configuration functions ********************************/
+void RTC_CalibOutputCmd(FunctionalState NewState);
+void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);
+ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, 
+                                  uint32_t RTC_SmoothCalibPlusPulses,
+                                  uint32_t RTC_SmouthCalibMinusPulsesValue);
+
+/* TimeStamp configuration functions ******************************************/
+void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, RTC_DateTypeDef* RTC_StampDateStruct);
+uint32_t RTC_GetTimeStampSubSecond(void);
+
+/* Tampers configuration functions ********************************************/
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
+void RTC_TamperPullUpCmd(FunctionalState NewState);
+
+/* Backup Data Registers configuration functions ******************************/
+void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);
+uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);
+
+/* Output Type Config configuration functions *********************************/
+void RTC_OutputTypeConfig(uint32_t RTC_OutputType);
+ 
+/* RTC_Shift_control_synchonisation_functions *********************************/
+ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
+
+/* Interrupts and flags management functions **********************************/
+void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
+void RTC_ClearFlag(uint32_t RTC_FLAG);
+ITStatus RTC_GetITStatus(uint32_t RTC_IT);
+void RTC_ClearITPendingBit(uint32_t RTC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F0XX_RTC_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_spi.h b/system/include/stm32f0-stdperiph/stm32f0xx_spi.h

new file mode 100644 (file)

index 0000000..edaea32
--- /dev/null
+++ b/system/include/stm32f0-stdperiph/stm32f0xx_spi.h
@@ -0,0 +1,588 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_spi.h
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file contains all the functions prototypes for the SPI 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_SPI_H
+#define __STM32F0XX_SPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup SPI
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  SPI Init structure definition  
+  */
+
+typedef struct
+{
+  uint16_t SPI_Direction;           /*!< Specifies the SPI unidirectional or bidirectional data mode.
+                                         This parameter can be a value of @ref SPI_data_direction */
+
+  uint16_t SPI_Mode;                /*!< Specifies the SPI mode (Master/Slave).
+                                         This parameter can be a value of @ref SPI_mode */
+  
+  uint16_t SPI_DataSize;            /*!< Specifies the SPI data size.
+                                         This parameter can be a value of @ref SPI_data_size */
+
+  uint16_t SPI_CPOL;                /*!< Specifies the serial clock steady state.
+                                         This parameter can be a value of @ref SPI_Clock_Polarity */
+
+  uint16_t SPI_CPHA;                /*!< Specifies the clock active edge for the bit capture.
+                                         This parameter can be a value of @ref SPI_Clock_Phase */
+
+  uint16_t SPI_NSS;                 /*!< Specifies whether the NSS signal is managed by
+                                         hardware (NSS pin) or by software using the SSI bit.
+                                         This parameter can be a value of @ref SPI_Slave_Select_management */
+ 
+  uint16_t SPI_BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
+                                         used to configure the transmit and receive SCK clock.
+                                         This parameter can be a value of @ref SPI_BaudRate_Prescaler
+                                         @note The communication clock is derived from the master
+                                               clock. The slave clock does not need to be set. */
+
+  uint16_t SPI_FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
+                                         This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+  uint16_t SPI_CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation. */
+}SPI_InitTypeDef;
+
+
+/** 
+  * @brief  I2S Init structure definition
+  * @note   These parameters are not available for STM32F030 devices.    
+  */
+
+typedef struct
+{
+  uint16_t I2S_Mode;         /*!< Specifies the I2S operating mode.
+                                  This parameter can be a value of @ref SPI_I2S_Mode */
+
+  uint16_t I2S_Standard;     /*!< Specifies the standard used for the I2S communication.
+                                  This parameter can be a value of @ref SPI_I2S_Standard */
+
+  uint16_t I2S_DataFormat;   /*!< Specifies the data format for the I2S communication.
+                                  This parameter can be a value of @ref SPI_I2S_Data_Format */
+
+  uint16_t I2S_MCLKOutput;   /*!< Specifies whether the I2S MCLK output is enabled or not.
+                                  This parameter can be a value of @ref SPI_I2S_MCLK_Output */
+
+  uint32_t I2S_AudioFreq;    /*!< Specifies the frequency selected for the I2S communication.
+                                  This parameter can be a value of @ref SPI_I2S_Audio_Frequency */
+
+  uint16_t I2S_CPOL;         /*!< Specifies the idle state of the I2S clock.
+                                  This parameter can be a value of @ref SPI_I2S_Clock_Polarity */
+}I2S_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SPI_Exported_Constants
+  * @{
+  */
+
+#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
+                                   ((PERIPH) == SPI2))
+                                   
+#define IS_SPI_1_PERIPH(PERIPH) (((PERIPH) == SPI1))
+
+/** @defgroup SPI_data_direction 
+  * @{
+  */
+  
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
+#define SPI_Direction_2Lines_RxOnly     ((uint16_t)0x0400)
+#define SPI_Direction_1Line_Rx          ((uint16_t)0x8000)
+#define SPI_Direction_1Line_Tx          ((uint16_t)0xC000)
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
+                                     ((MODE) == SPI_Direction_2Lines_RxOnly) || \
+                                     ((MODE) == SPI_Direction_1Line_Rx) || \
+                                     ((MODE) == SPI_Direction_1Line_Tx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_mode 
+  * @{
+  */
+
+#define SPI_Mode_Master                 ((uint16_t)0x0104)
+#define SPI_Mode_Slave                  ((uint16_t)0x0000)
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
+                           ((MODE) == SPI_Mode_Slave))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_data_size
+  * @{
+  */
+
+#define SPI_DataSize_4b                 ((uint16_t)0x0300)
+#define SPI_DataSize_5b                 ((uint16_t)0x0400)
+#define SPI_DataSize_6b                 ((uint16_t)0x0500)
+#define SPI_DataSize_7b                 ((uint16_t)0x0600)
+#define SPI_DataSize_8b                 ((uint16_t)0x0700)
+#define SPI_DataSize_9b                 ((uint16_t)0x0800)
+#define SPI_DataSize_10b                ((uint16_t)0x0900)
+#define SPI_DataSize_11b                ((uint16_t)0x0A00)
+#define SPI_DataSize_12b                ((uint16_t)0x0B00)
+#define SPI_DataSize_13b                ((uint16_t)0x0C00)
+#define SPI_DataSize_14b                ((uint16_t)0x0D00)
+#define SPI_DataSize_15b                ((uint16_t)0x0E00)
+#define SPI_DataSize_16b                ((uint16_t)0x0F00)
+#define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \
+                                 ((SIZE) == SPI_DataSize_5b) || \
+                                 ((SIZE) == SPI_DataSize_6b) || \
+                                 ((SIZE) == SPI_DataSize_7b) || \
+                                 ((SIZE) == SPI_DataSize_8b) || \
+                                 ((SIZE) == SPI_DataSize_9b) || \
+                                 ((SIZE) == SPI_DataSize_10b) || \
+                                 ((SIZE) == SPI_DataSize_11b) || \
+                                 ((SIZE) == SPI_DataSize_12b) || \
+                                 ((SIZE) == SPI_DataSize_13b) || \
+                                 ((SIZE) == SPI_DataSize_14b) || \
+                                 ((SIZE) == SPI_DataSize_15b) || \
+                                 ((SIZE) == SPI_DataSize_16b))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_length
+  * @{
+  */
+
+#define SPI_CRCLength_8b                ((uint16_t)0x0000)
+#define SPI_CRCLength_16b               SPI_CR1_CRCL
+#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \
+                                   ((LENGTH) == SPI_CRCLength_16b))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Clock_Polarity 
+  * @{
+  */
+
+#define SPI_CPOL_Low                    ((uint16_t)0x0000)
+#define SPI_CPOL_High                   SPI_CR1_CPOL
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
+                           ((CPOL) == SPI_CPOL_High))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Clock_Phase 
+  * @{
+  */
+
+#define SPI_CPHA_1Edge                  ((uint16_t)0x0000)
+#define SPI_CPHA_2Edge                  SPI_CR1_CPHA
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
+                           ((CPHA) == SPI_CPHA_2Edge))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Slave_Select_management 
+  * @{
+  */
+
+#define SPI_NSS_Soft                    SPI_CR1_SSM
+#define SPI_NSS_Hard                    ((uint16_t)0x0000)
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
+                         ((NSS) == SPI_NSS_Hard))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_BaudRate_Prescaler 
+  * @{
+  */
+
+#define SPI_BaudRatePrescaler_2         ((uint16_t)0x0000)
+#define SPI_BaudRatePrescaler_4         ((uint16_t)0x0008)
+#define SPI_BaudRatePrescaler_8         ((uint16_t)0x0010)
+#define SPI_BaudRatePrescaler_16        ((uint16_t)0x0018)
+#define SPI_BaudRatePrescaler_32        ((uint16_t)0x0020)
+#define SPI_BaudRatePrescaler_64        ((uint16_t)0x0028)
+#define SPI_BaudRatePrescaler_128       ((uint16_t)0x0030)
+#define SPI_BaudRatePrescaler_256       ((uint16_t)0x0038)
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_256))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_MSB_LSB_transmission 
+  * @{
+  */
+
+#define SPI_FirstBit_MSB                ((uint16_t)0x0000)
+#define SPI_FirstBit_LSB                SPI_CR1_LSBFIRST
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
+                               ((BIT) == SPI_FirstBit_LSB))
+/**
+  * @}
+  */
+  
+/** @defgroup SPI_I2S_Mode 
+  * @{
+  */
+
+#define I2S_Mode_SlaveTx                ((uint16_t)0x0000)
+#define I2S_Mode_SlaveRx                ((uint16_t)0x0100)
+#define I2S_Mode_MasterTx               ((uint16_t)0x0200)
+#define I2S_Mode_MasterRx               ((uint16_t)0x0300)
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
+                           ((MODE) == I2S_Mode_SlaveRx) || \
+                           ((MODE) == I2S_Mode_MasterTx)|| \
+                           ((MODE) == I2S_Mode_MasterRx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_Standard 
+  * @{
+  */
+
+#define I2S_Standard_Phillips           ((uint16_t)0x0000)
+#define I2S_Standard_MSB                ((uint16_t)0x0010)
+#define I2S_Standard_LSB                ((uint16_t)0x0020)
+#define I2S_Standard_PCMShort           ((uint16_t)0x0030)
+#define I2S_Standard_PCMLong            ((uint16_t)0x00B0)
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
+                                   ((STANDARD) == I2S_Standard_MSB) || \
+                                   ((STANDARD) == I2S_Standard_LSB) || \
+                                   ((STANDARD) == I2S_Standard_PCMShort) || \
+                                   ((STANDARD) == I2S_Standard_PCMLong))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_Data_Format 
+  * @{
+  */
+
+#define I2S_DataFormat_16b              ((uint16_t)0x0000)
+#define I2S_DataFormat_16bextended      ((uint16_t)0x0001)
+#define I2S_DataFormat_24b              ((uint16_t)0x0003)
+#define I2S_DataFormat_32b              ((uint16_t)0x0005)
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
+                                    ((FORMAT) == I2S_DataFormat_16bextended) || \
+                                    ((FORMAT) == I2S_DataFormat_24b) || \
+                                    ((FORMAT) == I2S_DataFormat_32b))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_MCLK_Output 
+  * @{
+  */
+
+#define I2S_MCLKOutput_Enable           SPI_I2SPR_MCKOE
+#define I2S_MCLKOutput_Disable          ((uint16_t)0x0000)
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
+                                    ((OUTPUT) == I2S_MCLKOutput_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_Audio_Frequency 
+  * @{
+  */
+
+#define I2S_AudioFreq_192k               ((uint32_t)192000)
+#define I2S_AudioFreq_96k                ((uint32_t)96000)
+#define I2S_AudioFreq_48k                ((uint32_t)48000)
+#define I2S_AudioFreq_44k                ((uint32_t)44100)
+#define I2S_AudioFreq_32k                ((uint32_t)32000)
+#define I2S_AudioFreq_22k                ((uint32_t)22050)
+#define I2S_AudioFreq_16k                ((uint32_t)16000)
+#define I2S_AudioFreq_11k                ((uint32_t)11025)
+#define I2S_AudioFreq_8k                 ((uint32_t)8000)
+#define I2S_AudioFreq_Default            ((uint32_t)2)
+
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
+                                 ((FREQ) <= I2S_AudioFreq_192k)) || \
+                                 ((FREQ) == I2S_AudioFreq_Default))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_Clock_Polarity 
+  * @{
+  */
+
+#define I2S_CPOL_Low                    ((uint16_t)0x0000)
+#define I2S_CPOL_High                   SPI_I2SCFGR_CKPOL
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
+                           ((CPOL) == I2S_CPOL_High))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_FIFO_reception_threshold 
+  * @{
+  */
+
+#define SPI_RxFIFOThreshold_HF          ((uint16_t)0x0000)
+#define SPI_RxFIFOThreshold_QF          SPI_CR2_FRXTH
+#define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \
+                                             ((THRESHOLD) == SPI_RxFIFOThreshold_QF))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_DMA_transfer_requests 
+  * @{
+  */
+
+#define SPI_I2S_DMAReq_Tx               SPI_CR2_TXDMAEN
+#define SPI_I2S_DMAReq_Rx               SPI_CR2_RXDMAEN
+#define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_last_DMA_transfers
+  * @{
+  */
+
+#define SPI_LastDMATransfer_TxEvenRxEven   ((uint16_t)0x0000)
+#define SPI_LastDMATransfer_TxOddRxEven    ((uint16_t)0x4000)
+#define SPI_LastDMATransfer_TxEvenRxOdd    ((uint16_t)0x2000)
+#define SPI_LastDMATransfer_TxOddRxOdd     ((uint16_t)0x6000)
+#define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \
+                                            ((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \
+                                            ((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \
+                                            ((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd))
+/**
+  * @}
+  */
+/** @defgroup SPI_NSS_internal_software_management 
+  * @{
+  */
+
+#define SPI_NSSInternalSoft_Set         SPI_CR1_SSI
+#define SPI_NSSInternalSoft_Reset       ((uint16_t)0xFEFF)
+#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
+                                       ((INTERNAL) == SPI_NSSInternalSoft_Reset))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_Transmit_Receive 
+  * @{
+  */
+
+#define SPI_CRC_Tx                      ((uint8_t)0x00)
+#define SPI_CRC_Rx                      ((uint8_t)0x01)
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_direction_transmit_receive 
+  * @{
+  */
+
+#define SPI_Direction_Rx                ((uint16_t)0xBFFF)
+#define SPI_Direction_Tx                ((uint16_t)0x4000)
+#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
+                                     ((DIRECTION) == SPI_Direction_Tx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_interrupts_definition 
+  * @{
+  */
+
+#define SPI_I2S_IT_TXE                  ((uint8_t)0x71)
+#define SPI_I2S_IT_RXNE                 ((uint8_t)0x60)
+#define SPI_I2S_IT_ERR                  ((uint8_t)0x50)
+
+#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
+                                  ((IT) == SPI_I2S_IT_RXNE) || \
+                                  ((IT) == SPI_I2S_IT_ERR))
+
+#define I2S_IT_UDR                      ((uint8_t)0x53)
+#define SPI_IT_MODF                     ((uint8_t)0x55)
+#define SPI_I2S_IT_OVR                  ((uint8_t)0x56)
+#define SPI_I2S_IT_FRE                  ((uint8_t)0x58)
+
+#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
+                               ((IT) == SPI_I2S_IT_OVR) || ((IT) == SPI_IT_MODF) || \
+                               ((IT) == SPI_I2S_IT_FRE)|| ((IT) == I2S_IT_UDR))
+/**
+  * @}
+  */
+
+
+/** @defgroup SPI_transmission_fifo_status_level 
+  * @{
+  */ 
+
+#define SPI_TransmissionFIFOStatus_Empty           ((uint16_t)0x0000)
+#define SPI_TransmissionFIFOStatus_1QuarterFull    ((uint16_t)0x0800) 
+#define SPI_TransmissionFIFOStatus_HalfFull        ((uint16_t)0x1000) 
+#define SPI_TransmissionFIFOStatus_Full            ((uint16_t)0x1800)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup SPI_reception_fifo_status_level 
+  * @{
+  */ 
+#define SPI_ReceptionFIFOStatus_Empty           ((uint16_t)0x0000)
+#define SPI_ReceptionFIFOStatus_1QuarterFull    ((uint16_t)0x0200) 
+#define SPI_ReceptionFIFOStatus_HalfFull        ((uint16_t)0x0400) 
+#define SPI_ReceptionFIFOStatus_Full            ((uint16_t)0x0600)
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup SPI_I2S_flags_definition 
+  * @{
+  */
+
+#define SPI_I2S_FLAG_RXNE               SPI_SR_RXNE
+#define SPI_I2S_FLAG_TXE                SPI_SR_TXE
+#define I2S_FLAG_CHSIDE                 SPI_SR_CHSIDE
+#define I2S_FLAG_UDR                    SPI_SR_UDR
+#define SPI_FLAG_CRCERR                 SPI_SR_CRCERR
+#define SPI_FLAG_MODF                   SPI_SR_MODF
+#define SPI_I2S_FLAG_OVR                SPI_SR_OVR
+#define SPI_I2S_FLAG_BSY                SPI_SR_BSY
+#define SPI_I2S_FLAG_FRE                SPI_SR_FRE
+
+
+
+#define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
+#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
+                                   ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
+                                   ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
+                                   ((FLAG) == SPI_I2S_FLAG_FRE)|| ((FLAG) == I2S_FLAG_CHSIDE)|| \
+                                   ((FLAG) == I2S_FLAG_UDR))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_polynomial 
+  * @{
+  */
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Initialization and Configuration functions *********************************/
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); /*!< Not applicable for STM32F030 devices */
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); /*!< Not applicable for STM32F030 devices */
+void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); /*!< Not applicable for STM32F030 devices */
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
+void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold);
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+
+/* Data transfers functions ***************************************************/
+void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data);
+void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data);
+uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx);
+uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx);
+
+/* Hardware CRC Calculation functions *****************************************/
+void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength);
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
+
+/* DMA transfers management functions *****************************************/
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
+void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer);
+
+/* Interrupts and flags management functions **********************************/
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
+uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx);
+uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx);
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F0XX_SPI_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h b/system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h

new file mode 100644 (file)

index 0000000..8c96414
--- /dev/null
+++ b/system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h
@@ -0,0 +1,459 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_syscfg.h
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file contains all the functions prototypes for the SYSCFG firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/*!< Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_SYSCFG_H
+#define __STM32F0XX_SYSCFG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*!< Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup SYSCFG
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SYSCFG_Exported_Constants
+  * @{
+  */ 
+  
+/** @defgroup SYSCFG_EXTI_Port_Sources 
+  * @{
+  */ 
+#define EXTI_PortSourceGPIOA       ((uint8_t)0x00)
+#define EXTI_PortSourceGPIOB       ((uint8_t)0x01)
+#define EXTI_PortSourceGPIOC       ((uint8_t)0x02)
+#define EXTI_PortSourceGPIOD       ((uint8_t)0x03) /*!< not available for STM32F031 devices */
+#define EXTI_PortSourceGPIOE       ((uint8_t)0x04) /*!< only available for STM32F072 devices */
+#define EXTI_PortSourceGPIOF       ((uint8_t)0x05)
+
+#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOF)) 
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_EXTI_Pin_sources 
+  * @{
+  */ 
+#define EXTI_PinSource0            ((uint8_t)0x00)
+#define EXTI_PinSource1            ((uint8_t)0x01)
+#define EXTI_PinSource2            ((uint8_t)0x02)
+#define EXTI_PinSource3            ((uint8_t)0x03)
+#define EXTI_PinSource4            ((uint8_t)0x04)
+#define EXTI_PinSource5            ((uint8_t)0x05)
+#define EXTI_PinSource6            ((uint8_t)0x06)
+#define EXTI_PinSource7            ((uint8_t)0x07)
+#define EXTI_PinSource8            ((uint8_t)0x08)
+#define EXTI_PinSource9            ((uint8_t)0x09)
+#define EXTI_PinSource10           ((uint8_t)0x0A)
+#define EXTI_PinSource11           ((uint8_t)0x0B)
+#define EXTI_PinSource12           ((uint8_t)0x0C)
+#define EXTI_PinSource13           ((uint8_t)0x0D)
+#define EXTI_PinSource14           ((uint8_t)0x0E)
+#define EXTI_PinSource15           ((uint8_t)0x0F)
+
+#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
+                                       ((PINSOURCE) == EXTI_PinSource1) || \
+                                       ((PINSOURCE) == EXTI_PinSource2) || \
+                                       ((PINSOURCE) == EXTI_PinSource3) || \
+                                       ((PINSOURCE) == EXTI_PinSource4) || \
+                                       ((PINSOURCE) == EXTI_PinSource5) || \
+                                       ((PINSOURCE) == EXTI_PinSource6) || \
+                                       ((PINSOURCE) == EXTI_PinSource7) || \
+                                       ((PINSOURCE) == EXTI_PinSource8) || \
+                                       ((PINSOURCE) == EXTI_PinSource9) || \
+                                       ((PINSOURCE) == EXTI_PinSource10) || \
+                                       ((PINSOURCE) == EXTI_PinSource11) || \
+                                       ((PINSOURCE) == EXTI_PinSource12) || \
+                                       ((PINSOURCE) == EXTI_PinSource13) || \
+                                       ((PINSOURCE) == EXTI_PinSource14) || \
+                                       ((PINSOURCE) == EXTI_PinSource15))
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Memory_Remap_Config 
+  * @{
+  */ 
+#define SYSCFG_MemoryRemap_Flash                ((uint8_t)0x00)
+#define SYSCFG_MemoryRemap_SystemMemory         ((uint8_t)0x01)
+#define SYSCFG_MemoryRemap_SRAM                 ((uint8_t)0x03)
+
+
+#define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
+                                       ((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \
+                                       ((REMAP) == SYSCFG_MemoryRemap_SRAM))
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_DMA_Remap_Config 
+  * @{
+  */ 
+#define SYSCFG_DMARemap_TIM3        SYSCFG_CFGR1_TIM3_DMA_RMP      /* Remap TIM3 DMA requests from channel4 to channel6, 
+                                                                      available only for STM32F072 devices */
+#define SYSCFG_DMARemap_TIM2        SYSCFG_CFGR1_TIM2_DMA_RMP      /* Remap TIM2 DMA requests from channel3/4 to channel7, 
+                                                                      available only for STM32F072 devices */ 
+#define SYSCFG_DMARemap_TIM1        SYSCFG_CFGR1_TIM1_DMA_RMP      /* Remap TIM1 DMA requests from channel2/3/4 to channel6, 
+                                                                      available only for STM32F072 devices */
+#define SYSCFG_DMARemap_I2C1        SYSCFG_CFGR1_I2C1_DMA_RMP      /* Remap I2C1 DMA requests from channel3/2 to channel7/6, 
+                                                                      available only for STM32F072 devices */
+#define SYSCFG_DMARemap_USART3      SYSCFG_CFGR1_USART3_DMA_RMP    /* Remap USART3 DMA requests from channel6/7 to channel3/2, 
+                                                                      available only for STM32F072 devices */
+#define SYSCFG_DMARemap_USART2      SYSCFG_CFGR1_USART2_DMA_RMP    /* Remap USART2 DMA requests from channel4/5 to channel6/7, 
+                                                                      available only for STM32F072 devices */
+#define SYSCFG_DMARemap_SPI2        SYSCFG_CFGR1_SPI2_DMA_RMP      /* Remap SPI2 DMA requests from channel4/5 to channel6/7, 
+                                                                      available only for STM32F072 devices */
+#define SYSCFG_DMARemap_TIM17_2     SYSCFG_CFGR1_TIM17_DMA_RMP2    /* Remap TIM17 DMA requests from channel1/2 to channel7, 
+                                                                      available only for STM32F072 devices */
+#define SYSCFG_DMARemap_TIM16_2     SYSCFG_CFGR1_TIM16_DMA_RMP2    /* Remap TIM16 DMA requests from channel3/4 to channel6, 
+                                                                      available only for STM32F072 devices */
+#define SYSCFG_DMARemap_TIM17       SYSCFG_CFGR1_TIM17_DMA_RMP    /* Remap TIM17 DMA requests from channel1 to channel2 */
+#define SYSCFG_DMARemap_TIM16       SYSCFG_CFGR1_TIM16_DMA_RMP    /* Remap TIM16 DMA requests from channel3 to channel4 */
+#define SYSCFG_DMARemap_USART1Rx    SYSCFG_CFGR1_USART1RX_DMA_RMP /* Remap USART1 Rx DMA requests from channel3 to channel5 */
+#define SYSCFG_DMARemap_USART1Tx    SYSCFG_CFGR1_USART1TX_DMA_RMP /* Remap USART1 Tx DMA requests from channel2 to channel4 */
+#define SYSCFG_DMARemap_ADC1        SYSCFG_CFGR1_ADC_DMA_RMP      /* Remap ADC1 DMA requests from channel1 to channel2 */
+  
+#define IS_SYSCFG_DMA_REMAP(REMAP) (((REMAP) == SYSCFG_DMARemap_TIM17) || \
+                                    ((REMAP) == SYSCFG_DMARemap_TIM16) || \
+                                    ((REMAP) == SYSCFG_DMARemap_USART1Rx) || \
+                                    ((REMAP) == SYSCFG_DMARemap_USART1Tx) || \
+                                    ((REMAP) == SYSCFG_CFGR1_TIM3_DMA_RMP) || \
+                                    ((REMAP) == SYSCFG_CFGR1_TIM2_DMA_RMP) || \
+                                    ((REMAP) == SYSCFG_CFGR1_TIM1_DMA_RMP) || \
+                                    ((REMAP) == SYSCFG_CFGR1_I2C1_DMA_RMP) || \
+                                    ((REMAP) == SYSCFG_CFGR1_USART3_DMA_RMP) || \
+                                    ((REMAP) == SYSCFG_CFGR1_USART2_DMA_RMP) || \
+                                    ((REMAP) == SYSCFG_CFGR1_SPI2_DMA_RMP) || \
+                                    ((REMAP) == SYSCFG_CFGR1_TIM17_DMA_RMP2) || \
+                                    ((REMAP) == SYSCFG_CFGR1_TIM16_DMA_RMP2) || \
+                                    ((REMAP) == SYSCFG_DMARemap_ADC1))
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_I2C_FastModePlus_Config 
+  * @{
+  */ 
+#define SYSCFG_I2CFastModePlus_PB6       SYSCFG_CFGR1_I2C_FMP_PB6 /* Enable Fast Mode Plus on PB6 */
+#define SYSCFG_I2CFastModePlus_PB7       SYSCFG_CFGR1_I2C_FMP_PB7 /* Enable Fast Mode Plus on PB7 */
+#define SYSCFG_I2CFastModePlus_PB8       SYSCFG_CFGR1_I2C_FMP_PB8 /* Enable Fast Mode Plus on PB8 */
+#define SYSCFG_I2CFastModePlus_PB9       SYSCFG_CFGR1_I2C_FMP_PB9 /* Enable Fast Mode Plus on PB9 */
+#define SYSCFG_I2CFastModePlus_I2C1      SYSCFG_CFGR1_I2C_FMP_I2C1 /* Enable Fast Mode Plus on PB10, PB11, PF6 and PF7(only for STM32F0031 and STM32F030 devices) */
+#define SYSCFG_I2CFastModePlus_I2C2      SYSCFG_CFGR1_I2C_FMP_I2C2 /* Enable Fast Mode Plus on I2C2 pins, available only for STM32F072 devices */
+#define SYSCFG_I2CFastModePlus_PA9       SYSCFG_CFGR1_I2C_FMP_PA9 /* Enable Fast Mode Plus on PA9 (only for STM32F031 and STM32F030 devices) */
+#define SYSCFG_I2CFastModePlus_PA10      SYSCFG_CFGR1_I2C_FMP_PA10/* Enable Fast Mode Plus on PA10(only for STM32F031 and STM32F030 devices) */
+
+#define IS_SYSCFG_I2C_FMP(PIN) (((PIN) == SYSCFG_I2CFastModePlus_PB6)  || \
+                                ((PIN) == SYSCFG_I2CFastModePlus_PB7)  || \
+                                ((PIN) == SYSCFG_I2CFastModePlus_PB8)  || \
+                                ((PIN) == SYSCFG_I2CFastModePlus_PB9)  || \
+                                ((PIN) == SYSCFG_I2CFastModePlus_I2C1) || \
+                                ((PIN) == SYSCFG_I2CFastModePlus_I2C2) || \
+                                ((PIN) == SYSCFG_I2CFastModePlus_PA9)  || \
+                                ((PIN) == SYSCFG_I2CFastModePlus_PA10))
+
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Lock_Config 
+  * @{
+  */ 
+#define SYSCFG_Break_PVD                     SYSCFG_CFGR2_PVD_LOCK       /*!< Connects the PVD event to the Break Input of TIM1, not available for STM32F030 devices */
+#define SYSCFG_Break_SRAMParity              SYSCFG_CFGR2_SRAM_PARITY_LOCK  /*!< Connects the SRAM_PARITY error signal to the Break Input of TIM1 */
+#define SYSCFG_Break_Lockup                  SYSCFG_CFGR2_LOCKUP_LOCK       /*!< Connects Lockup output of CortexM0 to the break input of TIM1 */
+
+#define IS_SYSCFG_LOCK_CONFIG(CONFIG) (((CONFIG) == SYSCFG_Break_PVD)        || \
+                                       ((CONFIG) == SYSCFG_Break_SRAMParity) || \
+                                       ((CONFIG) == SYSCFG_Break_Lockup))
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_flags_definition 
+  * @{
+  */
+
+#define SYSCFG_FLAG_PE               SYSCFG_CFGR2_SRAM_PE
+
+#define IS_SYSCFG_FLAG(FLAG) (((FLAG) == SYSCFG_FLAG_PE))
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_ISR_WRAPPER
+  * @{
+  */
+#define SYSCFG_ITLINE0                           ((uint32_t) 0x00000000)
+#define SYSCFG_ITLINE1                           ((uint32_t) 0x00000001)
+#define SYSCFG_ITLINE2                           ((uint32_t) 0x00000002)
+#define SYSCFG_ITLINE3                           ((uint32_t) 0x00000003)
+#define SYSCFG_ITLINE4                           ((uint32_t) 0x00000004)
+#define SYSCFG_ITLINE5                           ((uint32_t) 0x00000005)
+#define SYSCFG_ITLINE6                           ((uint32_t) 0x00000006)
+#define SYSCFG_ITLINE7                           ((uint32_t) 0x00000007)
+#define SYSCFG_ITLINE8                           ((uint32_t) 0x00000008)
+#define SYSCFG_ITLINE9                           ((uint32_t) 0x00000009)
+#define SYSCFG_ITLINE10                          ((uint32_t) 0x0000000A)
+#define SYSCFG_ITLINE11                          ((uint32_t) 0x0000000B)
+#define SYSCFG_ITLINE12                          ((uint32_t) 0x0000000C)
+#define SYSCFG_ITLINE13                          ((uint32_t) 0x0000000D)
+#define SYSCFG_ITLINE14                          ((uint32_t) 0x0000000E)
+#define SYSCFG_ITLINE15                          ((uint32_t) 0x0000000F)
+#define SYSCFG_ITLINE16                          ((uint32_t) 0x00000010)
+#define SYSCFG_ITLINE17                          ((uint32_t) 0x00000011)
+#define SYSCFG_ITLINE18                          ((uint32_t) 0x00000012)
+#define SYSCFG_ITLINE19                          ((uint32_t) 0x00000013)
+#define SYSCFG_ITLINE20                          ((uint32_t) 0x00000014)
+#define SYSCFG_ITLINE21                          ((uint32_t) 0x00000015)
+#define SYSCFG_ITLINE22                          ((uint32_t) 0x00000016)
+#define SYSCFG_ITLINE23                          ((uint32_t) 0x00000017)
+#define SYSCFG_ITLINE24                          ((uint32_t) 0x00000018)
+#define SYSCFG_ITLINE25                          ((uint32_t) 0x00000019)
+#define SYSCFG_ITLINE26                          ((uint32_t) 0x0000001A)
+#define SYSCFG_ITLINE27                          ((uint32_t) 0x0000001B)
+#define SYSCFG_ITLINE28                          ((uint32_t) 0x0000001C)
+#define SYSCFG_ITLINE29                          ((uint32_t) 0x0000001D)
+#define SYSCFG_ITLINE30                          ((uint32_t) 0x0000001E)
+#define SYSCFG_ITLINE31                          ((uint32_t) 0x0000001F)
+
+#define ITLINE_EWDG           ((uint32_t) ((SYSCFG_ITLINE0 << 0x18) | SYSCFG_ITLINE0_SR_EWDG)) /* EWDG Interrupt */
+#define ITLINE_PVDOUT         ((uint32_t) ((SYSCFG_ITLINE1 << 0x18) | SYSCFG_ITLINE1_SR_PVDOUT)) /* Power voltage detection Interrupt */
+#define ITLINE_VDDIO2         ((uint32_t) ((SYSCFG_ITLINE1 << 0x18) | SYSCFG_ITLINE1_SR_VDDIO2)) /* VDDIO2 Interrupt */
+#define ITLINE_RTC_WAKEUP     ((uint32_t) ((SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_WAKEUP)) /* RTC WAKEUP -> exti[20] Interrupt */
+#define ITLINE_RTC_TSTAMP     ((uint32_t) ((SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_TSTAMP)) /* RTC Time Stamp -> exti[19] interrupt */
+#define ITLINE_RTC_ALRA       ((uint32_t) ((SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_ALRA)) /* RTC Alarm -> exti[17] interrupt */
+#define ITLINE_FLASH_ITF      ((uint32_t) ((SYSCFG_ITLINE3 << 0x18) | SYSCFG_ITLINE3_SR_FLASH_ITF)) /* Flash ITF Interrupt */
+#define ITLINE_CRS            ((uint32_t) ((SYSCFG_ITLINE4 << 0x18) | SYSCFG_ITLINE4_SR_CRS)) /* CRS Interrupt */
+#define ITLINE_CLK_CTRL       ((uint32_t) ((SYSCFG_ITLINE4 << 0x18) | SYSCFG_ITLINE4_SR_CLK_CTRL)) /* CLK Control Interrupt */
+#define ITLINE_EXTI0          ((uint32_t) ((SYSCFG_ITLINE5 << 0x18) | SYSCFG_ITLINE5_SR_EXTI0)) /* External Interrupt 0 */
+#define ITLINE_EXTI1          ((uint32_t) ((SYSCFG_ITLINE5 << 0x18) | SYSCFG_ITLINE5_SR_EXTI1)) /* External Interrupt 1 */
+#define ITLINE_EXTI2          ((uint32_t) ((SYSCFG_ITLINE6 << 0x18) | SYSCFG_ITLINE6_SR_EXTI2)) /* External Interrupt 2 */
+#define ITLINE_EXTI3          ((uint32_t) ((SYSCFG_ITLINE6 << 0x18) | SYSCFG_ITLINE6_SR_EXTI3)) /* External Interrupt 3 */
+#define ITLINE_EXTI4          ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI4)) /* EXTI4 Interrupt */
+#define ITLINE_EXTI5          ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI5)) /* EXTI5 Interrupt */
+#define ITLINE_EXTI6          ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI6)) /* EXTI6 Interrupt */
+#define ITLINE_EXTI7          ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI7)) /* EXTI7 Interrupt */
+#define ITLINE_EXTI8          ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI8)) /* EXTI8 Interrupt */
+#define ITLINE_EXTI9          ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI9)) /* EXTI9 Interrupt */
+#define ITLINE_EXTI10         ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI10)) /* EXTI10 Interrupt */
+#define ITLINE_EXTI11         ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI11)) /* EXTI11 Interrupt */
+#define ITLINE_EXTI12         ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI12)) /* EXTI12 Interrupt */
+#define ITLINE_EXTI13         ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI13)) /* EXTI13 Interrupt */
+#define ITLINE_EXTI14         ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI14)) /* EXTI14 Interrupt */
+#define ITLINE_EXTI15         ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI15)) /* EXTI15 Interrupt */
+#define ITLINE_TSC_EOA        ((uint32_t) ((SYSCFG_ITLINE8 << 0x18) | SYSCFG_ITLINE8_SR_TSC_EOA)) /* Touch control EOA Interrupt */
+#define ITLINE_TSC_MCE        ((uint32_t) ((SYSCFG_ITLINE8 << 0x18) | SYSCFG_ITLINE8_SR_TSC_MCE)) /* Touch control MCE Interrupt */
+#define ITLINE_DMA1_CH1       ((uint32_t) ((SYSCFG_ITLINE9 << 0x18) | SYSCFG_ITLINE9_SR_DMA1_CH1)) /* DMA1 Channel 1 Interrupt */
+#define ITLINE_DMA1_CH2       ((uint32_t) ((SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA1_CH2)) /* DMA1 Channel 2 Interrupt */
+#define ITLINE_DMA1_CH3       ((uint32_t) ((SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA1_CH3)) /* DMA1 Channel 3 Interrupt */
+#define ITLINE_DMA2_CH1       ((uint32_t) ((SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA2_CH1)) /* DMA2 Channel 1 Interrupt */
+#define ITLINE_DMA2_CH2       ((uint32_t) ((SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA2_CH2)) /* DMA2 Channel 2 Interrupt */
+#define ITLINE_DMA1_CH4       ((uint32_t) ((SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH4)) /* DMA1 Channel 4 Interrupt */
+#define ITLINE_DMA1_CH5       ((uint32_t) ((SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH5)) /* DMA1 Channel 5 Interrupt */
+#define ITLINE_DMA1_CH6       ((uint32_t) ((SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH6)) /* DMA1 Channel 6 Interrupt */
+#define ITLINE_DMA1_CH7       ((uint32_t) ((SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH7)) /* DMA1 Channel 7 Interrupt */
+#define ITLINE_DMA2_CH3       ((uint32_t) ((SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH3)) /* DMA2 Channel 3 Interrupt */
+#define ITLINE_DMA2_CH4       ((uint32_t) ((SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH4)) /* DMA2 Channel 4 Interrupt */
+#define ITLINE_DMA2_CH5       ((uint32_t) ((SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH5)) /* DMA2 Channel 5 Interrupt */
+#define ITLINE_ADC            ((uint32_t) ((SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_ADC)) /* ADC Interrupt */
+#define ITLINE_COMP1          ((uint32_t) ((SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_COMP1)) /* COMP1 Interrupt -> exti[21] */
+#define ITLINE_COMP2          ((uint32_t) ((SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_COMP2)) /* COMP2 Interrupt -> exti[21] */
+#define ITLINE_TIM1_BRK       ((uint32_t) ((SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_BRK)) /* TIM1 BRK Interrupt */
+#define ITLINE_TIM1_UPD       ((uint32_t) ((SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_UPD)) /* TIM1 UPD Interrupt */
+#define ITLINE_TIM1_TRG       ((uint32_t) ((SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_TRG)) /* TIM1 TRG Interrupt */
+#define ITLINE_TIM1_CCU       ((uint32_t) ((SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_CCU)) /* TIM1 CCU Interrupt */
+#define ITLINE_TIM1_CC        ((uint32_t) ((SYSCFG_ITLINE14 << 0x18) | SYSCFG_ITLINE14_SR_TIM1_CC)) /* TIM1 CC Interrupt */
+#define ITLINE_TIM2           ((uint32_t) ((SYSCFG_ITLINE15 << 0x18) | SYSCFG_ITLINE15_SR_TIM2_GLB)) /* TIM2 Interrupt */
+#define ITLINE_TIM3           ((uint32_t) ((SYSCFG_ITLINE16 << 0x18) | SYSCFG_ITLINE16_SR_TIM3_GLB)) /* TIM3 Interrupt */
+#define ITLINE_DAC            ((uint32_t) ((SYSCFG_ITLINE17 << 0x18) | SYSCFG_ITLINE17_SR_DAC)) /* DAC Interrupt */
+#define ITLINE_TIM6           ((uint32_t) ((SYSCFG_ITLINE17 << 0x18) | SYSCFG_ITLINE17_SR_TIM6_GLB)) /* TIM6 Interrupt */
+#define ITLINE_TIM7           ((uint32_t) ((SYSCFG_ITLINE18 << 0x18) | SYSCFG_ITLINE18_SR_TIM7_GLB)) /* TIM7 Interrupt */
+#define ITLINE_TIM14          ((uint32_t) ((SYSCFG_ITLINE19 << 0x18) | SYSCFG_ITLINE19_SR_TIM14_GLB)) /* TIM14 Interrupt */
+#define ITLINE_TIM15          ((uint32_t) ((SYSCFG_ITLINE20 << 0x18) | SYSCFG_ITLINE20_SR_TIM15_GLB)) /* TIM15 Interrupt */
+#define ITLINE_TIM16          ((uint32_t) ((SYSCFG_ITLINE21 << 0x18) | SYSCFG_ITLINE21_SR_TIM16_GLB)) /* TIM16 Interrupt */
+#define ITLINE_TIM17          ((uint32_t) ((SYSCFG_ITLINE22 << 0x18) | SYSCFG_ITLINE22_SR_TIM17_GLB)) /* TIM17 Interrupt */
+#define ITLINE_I2C1           ((uint32_t) ((SYSCFG_ITLINE23 << 0x18) | SYSCFG_ITLINE23_SR_I2C1_GLB)) /* I2C1 Interrupt -> exti[23] */
+#define ITLINE_I2C2           ((uint32_t) ((SYSCFG_ITLINE24 << 0x18) | SYSCFG_ITLINE24_SR_I2C2_GLB)) /* I2C2 Interrupt */
+#define ITLINE_SPI1           ((uint32_t) ((SYSCFG_ITLINE25 << 0x18) | SYSCFG_ITLINE25_SR_SPI1)) /* I2C1 Interrupt -> exti[23] */
+#define ITLINE_SPI2           ((uint32_t) ((SYSCFG_ITLINE26 << 0x18) | SYSCFG_ITLINE26_SR_SPI2)) /* SPI1 Interrupt */
+#define ITLINE_USART1         ((uint32_t) ((SYSCFG_ITLINE27 << 0x18) | SYSCFG_ITLINE27_SR_USART1_GLB)) /*!< USART1 GLB Interrupt -> exti[25] */
+#define ITLINE_USART2         ((uint32_t) ((SYSCFG_ITLINE28 << 0x18) | SYSCFG_ITLINE28_SR_USART2_GLB)) /*!< USART2 GLB Interrupt -> exti[26] */
+#define ITLINE_USART3         ((uint32_t) ((SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART3_GLB)) /* USART3 Interrupt */
+#define ITLINE_USART4         ((uint32_t) ((SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART4_GLB)) /* USART4 Interrupt */
+#define ITLINE_USART5         ((uint32_t) ((SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART5_GLB)) /* USART5 Interrupt */
+#define ITLINE_USART6         ((uint32_t) ((SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART6_GLB)) /* USART6 Interrupt */
+#define ITLINE_USART7         ((uint32_t) ((SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART7_GLB)) /* USART7 Interrupt */
+#define ITLINE_USART8         ((uint32_t) ((SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART8_GLB)) /* USART8 Interrupt */
+#define ITLINE_CAN            ((uint32_t) ((SYSCFG_ITLINE30 << 0x18) | SYSCFG_ITLINE30_SR_CAN)) /* CAN Interrupt */
+#define ITLINE_CEC            ((uint32_t) ((SYSCFG_ITLINE30 << 0x18) | SYSCFG_ITLINE30_SR_CEC)) /* CEC Interrupt -> exti[27] */
+
+#define IS_SYSCFG_ITLINE(LINE) (((LINE) == ITLINE_EWDG)       || \
+                                ((LINE) == ITLINE_PVDOUT)     || \
+                                ((LINE) == ITLINE_VDDIO2)     || \
+                                ((LINE) == ITLINE_RTC_WAKEUP) || \
+                                ((LINE) == ITLINE_RTC_TSTAMP) || \
+                                ((LINE) == ITLINE_RTC_ALRA)   || \
+                                ((LINE) == ITLINE_FLASH_ITF)  || \
+                                ((LINE) == ITLINE_CRS)        || \
+                                ((LINE) == ITLINE_CLK_CTRL)   || \
+                                ((LINE) == ITLINE_EXTI0)      || \
+                                ((LINE) == ITLINE_EXTI1)      || \
+                                ((LINE) == ITLINE_EXTI2)      || \
+                                ((LINE) == ITLINE_EXTI3)      || \
+                                ((LINE) == ITLINE_EXTI4)      || \
+                                ((LINE) == ITLINE_EXTI5)      || \
+                                ((LINE) == ITLINE_EXTI6)      || \
+                                ((LINE) == ITLINE_EXTI7)      || \
+                                ((LINE) == ITLINE_EXTI8)      || \
+                                ((LINE) == ITLINE_EXTI9)      || \
+                                ((LINE) == ITLINE_EXTI10)     || \
+                                ((LINE) == ITLINE_EXTI11)     || \
+                                ((LINE) == ITLINE_EXTI12)     || \
+                                ((LINE) == ITLINE_EXTI13)     || \
+                                ((LINE) == ITLINE_EXTI14)     || \
+                                ((LINE) == ITLINE_EXTI15)     || \
+                                ((LINE) == ITLINE_TSC_EOA)    || \
+                                ((LINE) == ITLINE_TSC_MCE)    || \
+                                ((LINE) == ITLINE_DMA1_CH1)   || \
+                                ((LINE) == ITLINE_DMA1_CH2)   || \
+                                ((LINE) == ITLINE_DMA1_CH3)   || \
+                                ((LINE) == ITLINE_DMA1_CH4)   || \
+                                ((LINE) == ITLINE_DMA1_CH5)   || \
+                                ((LINE) == ITLINE_DMA1_CH6)   || \
+                                ((LINE) == ITLINE_DMA1_CH7)   || \
+                                ((LINE) == ITLINE_DMA2_CH1)   || \
+                                ((LINE) == ITLINE_DMA2_CH2)   || \
+                                ((LINE) == ITLINE_DMA2_CH3)   || \
+                                ((LINE) == ITLINE_DMA2_CH4)   || \
+                                ((LINE) == ITLINE_DMA2_CH5)   || \
+                                ((LINE) == ITLINE_ADC)        || \
+                                ((LINE) == ITLINE_COMP1)      || \
+                                ((LINE) == ITLINE_COMP2)      || \
+                                ((LINE) == ITLINE_TIM1_BRK)   || \
+                                ((LINE) == ITLINE_TIM1_UPD)   || \
+                                ((LINE) == ITLINE_TIM1_TRG)   || \
+                                ((LINE) == ITLINE_TIM1_CCU)   || \
+                                ((LINE) == ITLINE_TIM1_CC)    || \
+                                ((LINE) == ITLINE_TIM2)       || \
+                                ((LINE) == ITLINE_TIM3)       || \
+                                ((LINE) == ITLINE_DAC)        || \
+                                ((LINE) == ITLINE_TIM6)       || \
+                                ((LINE) == ITLINE_TIM7)       || \
+                                ((LINE) == ITLINE_TIM14)      || \
+                                ((LINE) == ITLINE_TIM15)      || \
+                                ((LINE) == ITLINE_TIM16)      || \
+                                ((LINE) == ITLINE_TIM17)      || \
+                                ((LINE) == ITLINE_I2C1)       || \
+                                ((LINE) == ITLINE_I2C2)       || \
+                                ((LINE) == ITLINE_SPI1)       || \
+                                ((LINE) == ITLINE_SPI2)       || \
+                                ((LINE) == ITLINE_USART1)     || \
+                                ((LINE) == ITLINE_USART2)     || \
+                                ((LINE) == ITLINE_USART3)     || \
+                                ((LINE) == ITLINE_USART4)     || \
+                                ((LINE) == ITLINE_USART5)     || \
+                                ((LINE) == ITLINE_USART6)     || \
+                                ((LINE) == ITLINE_USART7)     || \
+                                ((LINE) == ITLINE_USART8)     || \
+                                ((LINE) == ITLINE_CAN)        || \
+                                ((LINE) == ITLINE_CEC))
+
+/**
+  * @}
+  */
+/** @defgroup IRDA_ENV_SEL
+  * @{
+  */
+#define SYSCFG_IRDA_ENV_SEL_TIM16     (SYSCFG_CFGR1_IRDA_ENV_SEL_0&SYSCFG_CFGR1_IRDA_ENV_SEL_1)    /* Timer16 is selected as IRDA Modulation envelope source */
+#define SYSCFG_IRDA_ENV_SEL_USART1    (SYSCFG_CFGR1_IRDA_ENV_SEL_0)  /* USART1 is selected as IRDA Modulation envelope source.*/
+#define SYSCFG_IRDA_ENV_SEL_USART4    (SYSCFG_CFGR1_IRDA_ENV_SEL_1)  /* USART4 is selected as IRDA Modulation envelope source.*/
+
+#define IS_SYSCFG_IRDA_ENV(ENV) (((ENV) == SYSCFG_IRDA_ENV_SEL_TIM16)      || \
+                                 ((ENV) == SYSCFG_IRDA_ENV_SEL_USART1)     || \
+                                 ((ENV) == SYSCFG_IRDA_ENV_SEL_USART4))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/*  Function used to set the SYSCFG configuration to the default reset state **/
+void SYSCFG_DeInit(void);
+
+/* SYSCFG configuration functions *********************************************/ 
+void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap);
+void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState);
+void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState);
+void SYSCFG_IRDAEnvSelection(uint32_t SYSCFG_IRDAEnv);
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
+uint32_t SYSCFG_GetPendingIT(uint32_t ITSourceLine);
+void SYSCFG_BreakConfig(uint32_t SYSCFG_Break);
+FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag);
+void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F0XX_SYSCFG_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_tim.h b/system/include/stm32f0-stdperiph/stm32f0xx_tim.h

new file mode 100644 (file)

index 0000000..47a509d
--- /dev/null
+++ b/system/include/stm32f0-stdperiph/stm32f0xx_tim.h
@@ -0,0 +1,1186 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_tim.h
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file contains all the functions prototypes for the TIM 
+  *          firmware library. 
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_TIM_H
+#define __STM32F0XX_TIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup TIM
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  TIM Time Base Init structure definition
+  * @note   This sturcture is used with all TIMx.
+  */
+
+typedef struct
+{
+  uint16_t TIM_Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+                                       This parameter can be a number between 0x0000 and 0xFFFF */
+
+  uint16_t TIM_CounterMode;       /*!< Specifies the counter mode.
+                                       This parameter can be a value of @ref TIM_Counter_Mode */
+
+  uint32_t TIM_Period;            /*!< Specifies the period value to be loaded into the active
+                                       Auto-Reload Register at the next update event.
+                                       This parameter must be a number between 0x0000 and 0xFFFF.  */ 
+
+  uint16_t TIM_ClockDivision;     /*!< Specifies the clock division.
+                                      This parameter can be a value of @ref TIM_Clock_Division_CKD */
+
+  uint8_t TIM_RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
+                                       reaches zero, an update event is generated and counting restarts
+                                       from the RCR value (N).
+                                       This means in PWM mode that (N+1) corresponds to:
+                                          - the number of PWM periods in edge-aligned mode
+                                          - the number of half PWM period in center-aligned mode
+                                       This parameter must be a number between 0x00 and 0xFF. 
+                                       @note This parameter is valid only for TIM1. */
+} TIM_TimeBaseInitTypeDef;       
+
+/** 
+  * @brief  TIM Output Compare Init structure definition  
+  */
+
+typedef struct
+{
+  uint16_t TIM_OCMode;        /*!< Specifies the TIM mode.
+                                   This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint16_t TIM_OutputState;   /*!< Specifies the TIM Output Compare state.
+                                   This parameter can be a value of @ref TIM_Output_Compare_state */
+
+  uint16_t TIM_OutputNState;  /*!< Specifies the TIM complementary Output Compare state.
+                                   This parameter can be a value of @ref TIM_Output_Compare_N_state
+                                   @note This parameter is valid only for TIM1. */
+
+  uint32_t TIM_Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 
+                                   This parameter can be a number between 0x0000 and 0xFFFF ( or 0xFFFFFFFF 
+                                   for TIM2) */
+
+  uint16_t TIM_OCPolarity;    /*!< Specifies the output polarity.
+                                   This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint16_t TIM_OCNPolarity;   /*!< Specifies the complementary output polarity.
+                                   This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                                   @note This parameter is valid only for TIM1. */
+
+  uint16_t TIM_OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                                   This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                                   @note This parameter is valid only for TIM1. */
+
+  uint16_t TIM_OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                                   This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                                   @note This parameter is valid only for TIM1. */
+} TIM_OCInitTypeDef;
+
+/** 
+  * @brief  TIM Input Capture Init structure definition  
+  */
+
+typedef struct
+{
+
+  uint16_t TIM_Channel;      /*!< Specifies the TIM channel.
+                                  This parameter can be a value of @ref TIM_Channel */
+
+  uint16_t TIM_ICPolarity;   /*!< Specifies the active edge of the input signal.
+                                  This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint16_t TIM_ICSelection;  /*!< Specifies the input.
+                                  This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint16_t TIM_ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
+                                  This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint16_t TIM_ICFilter;     /*!< Specifies the input capture filter.
+                                  This parameter can be a number between 0x0 and 0xF */
+} TIM_ICInitTypeDef;
+
+/** 
+  * @brief  TIM_BDTR structure definition 
+  * @note   This sturcture is used only with TIM1.    
+  */
+
+typedef struct
+{
+
+  uint16_t TIM_OSSRState;        /*!< Specifies the Off-State selection used in Run mode.
+                                      This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+
+  uint16_t TIM_OSSIState;        /*!< Specifies the Off-State used in Idle state.
+                                      This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+
+  uint16_t TIM_LOCKLevel;        /*!< Specifies the LOCK level parameters.
+                                      This parameter can be a value of @ref TIM_Lock_level */ 
+
+  uint16_t TIM_DeadTime;         /*!< Specifies the delay time between the switching-off and the
+                                      switching-on of the outputs.
+                                      This parameter can be a number between 0x00 and 0xFF  */
+
+  uint16_t TIM_Break;            /*!< Specifies whether the TIM Break input is enabled or not. 
+                                      This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+
+  uint16_t TIM_BreakPolarity;    /*!< Specifies the TIM Break Input pin polarity.
+                                      This parameter can be a value of @ref TIM_Break_Polarity */
+
+  uint16_t TIM_AutomaticOutput;  /*!< Specifies whether the TIM Automatic Output feature is enabled or not. 
+                                      This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BDTRInitTypeDef;
+
+/** 
+  * @brief  TIM Input Capture Init structure definition  
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+  
+/** @defgroup TIM_Exported_constants 
+  * @{
+  */
+
+#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                   ((PERIPH) == TIM2) || \
+                                   ((PERIPH) == TIM3) || \
+                                   ((PERIPH) == TIM6) || \
+                                   ((PERIPH) == TIM7) || \
+                                   ((PERIPH) == TIM14)|| \
+                                   ((PERIPH) == TIM15)|| \
+                                   ((PERIPH) == TIM16)|| \
+                                   ((PERIPH) == TIM17))
+
+/* LIST1: TIM 1 */
+#define IS_TIM_LIST1_PERIPH(PERIPH)  ((PERIPH) == TIM1)
+
+/* LIST2: TIM 1, 15, 16 and 17 */
+#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                     ((PERIPH) == TIM15)|| \
+                                     ((PERIPH) == TIM16)|| \
+                                     ((PERIPH) == TIM17)) 
+
+/* LIST3: TIM 1, 2 and 3 */
+#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                     ((PERIPH) == TIM2) || \
+                                     ((PERIPH) == TIM3)) 
+
+/* LIST4: TIM 1, 2, 3, 14, 15, 16 and 17 */
+#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                     ((PERIPH) == TIM2) || \
+                                     ((PERIPH) == TIM3) || \
+                                     ((PERIPH) == TIM14) || \
+                                     ((PERIPH) == TIM15)|| \
+                                     ((PERIPH) == TIM16)|| \
+                                     ((PERIPH) == TIM17))
+
+/* LIST5: TIM 1, 2, 3, 15, 16 and 17 */
+#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                     ((PERIPH) == TIM2) || \
+                                     ((PERIPH) == TIM3) || \
+                                     ((PERIPH) == TIM15)|| \
+                                     ((PERIPH) == TIM16)|| \
+                                     ((PERIPH) == TIM17))
+
+/* LIST6: TIM 1, 2, 3 and 15 */
+#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                     ((PERIPH) == TIM2) || \
+                                     ((PERIPH) == TIM3) || \
+                                     ((PERIPH) == TIM15)) 
+
+/* LIST7: TIM 1, 2, 3, 6, 7 and 14 */
+#define IS_TIM_LIST7_PERIPH(PERIPH)  (((PERIPH) == TIM1) || \
+                                      ((PERIPH) == TIM2) || \
+                                      ((PERIPH) == TIM3) || \
+                                      ((PERIPH) == TIM6) || \
+                                      ((PERIPH) == TIM7) || \
+                                      ((PERIPH) == TIM14))
+                                      
+/* LIST8: TIM 1, 2, 3 and 14 */
+#define IS_TIM_LIST8_PERIPH(PERIPH)  (((PERIPH) == TIM1) || \
+                                      ((PERIPH) == TIM2) || \
+                                      ((PERIPH) == TIM3) || \
+                                      ((PERIPH) == TIM14))
+
+/* LIST9: TIM 1, 2, 3, 6, 7 and 15 */
+#define IS_TIM_LIST9_PERIPH(PERIPH)  (((PERIPH) == TIM1) || \
+                                      ((PERIPH) == TIM2) || \
+                                      ((PERIPH) == TIM3) || \
+                                      ((PERIPH) == TIM6) || \
+                                      ((PERIPH) == TIM7) || \
+                                      ((PERIPH) == TIM15))
+
+/* LIST10: TIM 1, 2, 3, 6, 7, 15, 16 and 17 */
+#define IS_TIM_LIST10_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                     ((PERIPH) == TIM2) || \
+                                     ((PERIPH) == TIM3) || \
+                                     ((PERIPH) == TIM6) || \
+                                     ((PERIPH) == TIM7) || \
+                                     ((PERIPH) == TIM15)|| \
+                                     ((PERIPH) == TIM16)|| \
+                                     ((PERIPH) == TIM17))
+
+/* LIST1: TIM 11 */
+#define IS_TIM_LIST11_PERIPH(PERIPH)  ((PERIPH) == TIM14)
+                                     
+
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes 
+  * @{
+  */
+
+#define TIM_OCMode_Timing                  ((uint16_t)0x0000)
+#define TIM_OCMode_Active                  ((uint16_t)0x0010)
+#define TIM_OCMode_Inactive                ((uint16_t)0x0020)
+#define TIM_OCMode_Toggle                  ((uint16_t)0x0030)
+#define TIM_OCMode_PWM1                    ((uint16_t)0x0060)
+#define TIM_OCMode_PWM2                    ((uint16_t)0x0070)
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
+                              ((MODE) == TIM_OCMode_Active) || \
+                              ((MODE) == TIM_OCMode_Inactive) || \
+                              ((MODE) == TIM_OCMode_Toggle)|| \
+                              ((MODE) == TIM_OCMode_PWM1) || \
+                              ((MODE) == TIM_OCMode_PWM2))
+#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
+                          ((MODE) == TIM_OCMode_Active) || \
+                          ((MODE) == TIM_OCMode_Inactive) || \
+                          ((MODE) == TIM_OCMode_Toggle)|| \
+                          ((MODE) == TIM_OCMode_PWM1) || \
+                          ((MODE) == TIM_OCMode_PWM2) ||       \
+                          ((MODE) == TIM_ForcedAction_Active) || \
+                          ((MODE) == TIM_ForcedAction_InActive))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_One_Pulse_Mode 
+  * @{
+  */
+
+#define TIM_OPMode_Single                  ((uint16_t)0x0008)
+#define TIM_OPMode_Repetitive              ((uint16_t)0x0000)
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
+                               ((MODE) == TIM_OPMode_Repetitive))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Channel 
+  * @{
+  */
+
+#define TIM_Channel_1                      ((uint16_t)0x0000)
+#define TIM_Channel_2                      ((uint16_t)0x0004)
+#define TIM_Channel_3                      ((uint16_t)0x0008)
+#define TIM_Channel_4                      ((uint16_t)0x000C)
+
+#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+                                 ((CHANNEL) == TIM_Channel_2) || \
+                                 ((CHANNEL) == TIM_Channel_3) || \
+                                 ((CHANNEL) == TIM_Channel_4))
+#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+                                               ((CHANNEL) == TIM_Channel_2) || \
+                                               ((CHANNEL) == TIM_Channel_3))
+#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+                                      ((CHANNEL) == TIM_Channel_2))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Clock_Division_CKD 
+  * @{
+  */
+
+#define TIM_CKD_DIV1                       ((uint16_t)0x0000)
+#define TIM_CKD_DIV2                       ((uint16_t)0x0100)
+#define TIM_CKD_DIV4                       ((uint16_t)0x0200)
+#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
+                             ((DIV) == TIM_CKD_DIV2) || \
+                             ((DIV) == TIM_CKD_DIV4))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Counter_Mode 
+  * @{
+  */
+
+#define TIM_CounterMode_Up                 ((uint16_t)0x0000)
+#define TIM_CounterMode_Down               ((uint16_t)0x0010)
+#define TIM_CounterMode_CenterAligned1     ((uint16_t)0x0020)
+#define TIM_CounterMode_CenterAligned2     ((uint16_t)0x0040)
+#define TIM_CounterMode_CenterAligned3     ((uint16_t)0x0060)
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) ||  \
+                                   ((MODE) == TIM_CounterMode_Down) || \
+                                   ((MODE) == TIM_CounterMode_CenterAligned1) || \
+                                   ((MODE) == TIM_CounterMode_CenterAligned2) || \
+                                   ((MODE) == TIM_CounterMode_CenterAligned3))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_Polarity 
+  * @{
+  */
+
+#define TIM_OCPolarity_High                ((uint16_t)0x0000)
+#define TIM_OCPolarity_Low                 ((uint16_t)0x0002)
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
+                                      ((POLARITY) == TIM_OCPolarity_Low))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_Polarity 
+  * @{
+  */
+  
+#define TIM_OCNPolarity_High               ((uint16_t)0x0000)
+#define TIM_OCNPolarity_Low                ((uint16_t)0x0008)
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
+                                       ((POLARITY) == TIM_OCNPolarity_Low))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_state
+  * @{
+  */
+
+#define TIM_OutputState_Disable            ((uint16_t)0x0000)
+#define TIM_OutputState_Enable             ((uint16_t)0x0001)
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
+                                    ((STATE) == TIM_OutputState_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_N_state 
+  * @{
+  */
+
+#define TIM_OutputNState_Disable           ((uint16_t)0x0000)
+#define TIM_OutputNState_Enable            ((uint16_t)0x0004)
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
+                                     ((STATE) == TIM_OutputNState_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Capture_Compare_state 
+  * @{
+  */
+
+#define TIM_CCx_Enable                      ((uint16_t)0x0001)
+#define TIM_CCx_Disable                     ((uint16_t)0x0000)
+#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
+                         ((CCX) == TIM_CCx_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Capture_Compare_N_state 
+  * @{
+  */
+
+#define TIM_CCxN_Enable                     ((uint16_t)0x0004)
+#define TIM_CCxN_Disable                    ((uint16_t)0x0000)
+#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
+                           ((CCXN) == TIM_CCxN_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Break_Input_enable_disable 
+  * @{
+  */
+
+#define TIM_Break_Enable                   ((uint16_t)0x1000)
+#define TIM_Break_Disable                  ((uint16_t)0x0000)
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
+                                   ((STATE) == TIM_Break_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Break_Polarity 
+  * @{
+  */
+
+#define TIM_BreakPolarity_Low              ((uint16_t)0x0000)
+#define TIM_BreakPolarity_High             ((uint16_t)0x2000)
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
+                                         ((POLARITY) == TIM_BreakPolarity_High))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_AOE_Bit_Set_Reset 
+  * @{
+  */
+
+#define TIM_AutomaticOutput_Enable         ((uint16_t)0x4000)
+#define TIM_AutomaticOutput_Disable        ((uint16_t)0x0000)
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
+                                              ((STATE) == TIM_AutomaticOutput_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Lock_level 
+  * @{
+  */
+
+#define TIM_LOCKLevel_OFF                  ((uint16_t)0x0000)
+#define TIM_LOCKLevel_1                    ((uint16_t)0x0100)
+#define TIM_LOCKLevel_2                    ((uint16_t)0x0200)
+#define TIM_LOCKLevel_3                    ((uint16_t)0x0300)
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
+                                  ((LEVEL) == TIM_LOCKLevel_1) || \
+                                  ((LEVEL) == TIM_LOCKLevel_2) || \
+                                  ((LEVEL) == TIM_LOCKLevel_3))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state 
+  * @{
+  */
+
+#define TIM_OSSIState_Enable               ((uint16_t)0x0400)
+#define TIM_OSSIState_Disable              ((uint16_t)0x0000)
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
+                                  ((STATE) == TIM_OSSIState_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state 
+  * @{
+  */
+
+#define TIM_OSSRState_Enable               ((uint16_t)0x0800)
+#define TIM_OSSRState_Disable              ((uint16_t)0x0000)
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
+                                  ((STATE) == TIM_OSSRState_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_Idle_State 
+  * @{
+  */
+
+#define TIM_OCIdleState_Set                ((uint16_t)0x0100)
+#define TIM_OCIdleState_Reset              ((uint16_t)0x0000)
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
+                                    ((STATE) == TIM_OCIdleState_Reset))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_N_Idle_State 
+  * @{
+  */
+
+#define TIM_OCNIdleState_Set               ((uint16_t)0x0200)
+#define TIM_OCNIdleState_Reset             ((uint16_t)0x0000)
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
+                                     ((STATE) == TIM_OCNIdleState_Reset))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Input_Capture_Polarity 
+  * @{
+  */
+
+#define  TIM_ICPolarity_Rising             ((uint16_t)0x0000)
+#define  TIM_ICPolarity_Falling            ((uint16_t)0x0002)
+#define  TIM_ICPolarity_BothEdge           ((uint16_t)0x000A)
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
+                                      ((POLARITY) == TIM_ICPolarity_Falling)|| \
+                                      ((POLARITY) == TIM_ICPolarity_BothEdge)) 
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Input_Capture_Selection 
+  * @{
+  */
+
+#define TIM_ICSelection_DirectTI           ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be 
+                                                                   connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSelection_IndirectTI         ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+                                                                   connected to IC2, IC1, IC4 or IC3, respectively. */
+#define TIM_ICSelection_TRC                ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
+                                        ((SELECTION) == TIM_ICSelection_IndirectTI) || \
+                                        ((SELECTION) == TIM_ICSelection_TRC))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Input_Capture_Prescaler 
+  * @{
+  */
+
+#define TIM_ICPSC_DIV1                     ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
+#define TIM_ICPSC_DIV2                     ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
+#define TIM_ICPSC_DIV4                     ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
+#define TIM_ICPSC_DIV8                     ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
+                                        ((PRESCALER) == TIM_ICPSC_DIV2) || \
+                                        ((PRESCALER) == TIM_ICPSC_DIV4) || \
+                                        ((PRESCALER) == TIM_ICPSC_DIV8))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_interrupt_sources 
+  * @{
+  */
+
+#define TIM_IT_Update                      ((uint16_t)0x0001)
+#define TIM_IT_CC1                         ((uint16_t)0x0002)
+#define TIM_IT_CC2                         ((uint16_t)0x0004)
+#define TIM_IT_CC3                         ((uint16_t)0x0008)
+#define TIM_IT_CC4                         ((uint16_t)0x0010)
+#define TIM_IT_COM                         ((uint16_t)0x0020)
+#define TIM_IT_Trigger                     ((uint16_t)0x0040)
+#define TIM_IT_Break                       ((uint16_t)0x0080)
+#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
+
+#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
+                           ((IT) == TIM_IT_CC1) || \
+                           ((IT) == TIM_IT_CC2) || \
+                           ((IT) == TIM_IT_CC3) || \
+                           ((IT) == TIM_IT_CC4) || \
+                           ((IT) == TIM_IT_COM) || \
+                           ((IT) == TIM_IT_Trigger) || \
+                           ((IT) == TIM_IT_Break))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_DMA_Base_address 
+  * @{
+  */
+
+#define TIM_DMABase_CR1                    ((uint16_t)0x0000)
+#define TIM_DMABase_CR2                    ((uint16_t)0x0001)
+#define TIM_DMABase_SMCR                   ((uint16_t)0x0002)
+#define TIM_DMABase_DIER                   ((uint16_t)0x0003)
+#define TIM_DMABase_SR                     ((uint16_t)0x0004)
+#define TIM_DMABase_EGR                    ((uint16_t)0x0005)
+#define TIM_DMABase_CCMR1                  ((uint16_t)0x0006)
+#define TIM_DMABase_CCMR2                  ((uint16_t)0x0007)
+#define TIM_DMABase_CCER                   ((uint16_t)0x0008)
+#define TIM_DMABase_CNT                    ((uint16_t)0x0009)
+#define TIM_DMABase_PSC                    ((uint16_t)0x000A)
+#define TIM_DMABase_ARR                    ((uint16_t)0x000B)
+#define TIM_DMABase_RCR                    ((uint16_t)0x000C)
+#define TIM_DMABase_CCR1                   ((uint16_t)0x000D)
+#define TIM_DMABase_CCR2                   ((uint16_t)0x000E)
+#define TIM_DMABase_CCR3                   ((uint16_t)0x000F)
+#define TIM_DMABase_CCR4                   ((uint16_t)0x0010)
+#define TIM_DMABase_BDTR                   ((uint16_t)0x0011)
+#define TIM_DMABase_DCR                    ((uint16_t)0x0012)
+#define TIM_DMABase_OR                     ((uint16_t)0x0013)
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
+                               ((BASE) == TIM_DMABase_CR2) || \
+                               ((BASE) == TIM_DMABase_SMCR) || \
+                               ((BASE) == TIM_DMABase_DIER) || \
+                               ((BASE) == TIM_DMABase_SR) || \
+                               ((BASE) == TIM_DMABase_EGR) || \
+                               ((BASE) == TIM_DMABase_CCMR1) || \
+                               ((BASE) == TIM_DMABase_CCMR2) || \
+                               ((BASE) == TIM_DMABase_CCER) || \
+                               ((BASE) == TIM_DMABase_CNT) || \
+                               ((BASE) == TIM_DMABase_PSC) || \
+                               ((BASE) == TIM_DMABase_ARR) || \
+                               ((BASE) == TIM_DMABase_RCR) || \
+                               ((BASE) == TIM_DMABase_CCR1) || \
+                               ((BASE) == TIM_DMABase_CCR2) || \
+                               ((BASE) == TIM_DMABase_CCR3) || \
+                               ((BASE) == TIM_DMABase_CCR4) || \
+                               ((BASE) == TIM_DMABase_BDTR) || \
+                                                          ((BASE) == TIM_DMABase_DCR) || \
+                               ((BASE) == TIM_DMABase_OR))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup TIM_DMA_Burst_Length 
+  * @{
+  */
+
+#define TIM_DMABurstLength_1Transfer           ((uint16_t)0x0000)
+#define TIM_DMABurstLength_2Transfers          ((uint16_t)0x0100)
+#define TIM_DMABurstLength_3Transfers          ((uint16_t)0x0200)
+#define TIM_DMABurstLength_4Transfers          ((uint16_t)0x0300)
+#define TIM_DMABurstLength_5Transfers          ((uint16_t)0x0400)
+#define TIM_DMABurstLength_6Transfers          ((uint16_t)0x0500)
+#define TIM_DMABurstLength_7Transfers          ((uint16_t)0x0600)
+#define TIM_DMABurstLength_8Transfers          ((uint16_t)0x0700)
+#define TIM_DMABurstLength_9Transfers          ((uint16_t)0x0800)
+#define TIM_DMABurstLength_10Transfers         ((uint16_t)0x0900)
+#define TIM_DMABurstLength_11Transfers         ((uint16_t)0x0A00)
+#define TIM_DMABurstLength_12Transfers         ((uint16_t)0x0B00)
+#define TIM_DMABurstLength_13Transfers         ((uint16_t)0x0C00)
+#define TIM_DMABurstLength_14Transfers         ((uint16_t)0x0D00)
+#define TIM_DMABurstLength_15Transfers         ((uint16_t)0x0E00)
+#define TIM_DMABurstLength_16Transfers         ((uint16_t)0x0F00)
+#define TIM_DMABurstLength_17Transfers         ((uint16_t)0x1000)
+#define TIM_DMABurstLength_18Transfers         ((uint16_t)0x1100)
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
+                                   ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_18Transfers))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_DMA_sources 
+  * @{
+  */
+
+#define TIM_DMA_Update                     ((uint16_t)0x0100)
+#define TIM_DMA_CC1                        ((uint16_t)0x0200)
+#define TIM_DMA_CC2                        ((uint16_t)0x0400)
+#define TIM_DMA_CC3                        ((uint16_t)0x0800)
+#define TIM_DMA_CC4                        ((uint16_t)0x1000)
+#define TIM_DMA_COM                        ((uint16_t)0x2000)
+#define TIM_DMA_Trigger                    ((uint16_t)0x4000)
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_External_Trigger_Prescaler 
+  * @{
+  */
+
+#define TIM_ExtTRGPSC_OFF                  ((uint16_t)0x0000)
+#define TIM_ExtTRGPSC_DIV2                 ((uint16_t)0x1000)
+#define TIM_ExtTRGPSC_DIV4                 ((uint16_t)0x2000)
+#define TIM_ExtTRGPSC_DIV8                 ((uint16_t)0x3000)
+#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
+                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
+                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
+                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Internal_Trigger_Selection 
+  * @{
+  */
+
+#define TIM_TS_ITR0                        ((uint16_t)0x0000)
+#define TIM_TS_ITR1                        ((uint16_t)0x0010)
+#define TIM_TS_ITR2                        ((uint16_t)0x0020)
+#define TIM_TS_ITR3                        ((uint16_t)0x0030)
+#define TIM_TS_TI1F_ED                     ((uint16_t)0x0040)
+#define TIM_TS_TI1FP1                      ((uint16_t)0x0050)
+#define TIM_TS_TI2FP2                      ((uint16_t)0x0060)
+#define TIM_TS_ETRF                        ((uint16_t)0x0070)
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+                                             ((SELECTION) == TIM_TS_ITR1) || \
+                                             ((SELECTION) == TIM_TS_ITR2) || \
+                                             ((SELECTION) == TIM_TS_ITR3) || \
+                                             ((SELECTION) == TIM_TS_TI1F_ED) || \
+                                             ((SELECTION) == TIM_TS_TI1FP1) || \
+                                             ((SELECTION) == TIM_TS_TI2FP2) || \
+                                             ((SELECTION) == TIM_TS_ETRF))
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+                                                      ((SELECTION) == TIM_TS_ITR1) || \
+                                                      ((SELECTION) == TIM_TS_ITR2) || \
+                                                      ((SELECTION) == TIM_TS_ITR3))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_TIx_External_Clock_Source 
+  * @{
+  */
+
+#define TIM_TIxExternalCLK1Source_TI1      ((uint16_t)0x0050)
+#define TIM_TIxExternalCLK1Source_TI2      ((uint16_t)0x0060)
+#define TIM_TIxExternalCLK1Source_TI1ED    ((uint16_t)0x0040)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_External_Trigger_Polarity 
+  * @{
+  */ 
+#define TIM_ExtTRGPolarity_Inverted        ((uint16_t)0x8000)
+#define TIM_ExtTRGPolarity_NonInverted     ((uint16_t)0x0000)
+#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
+                                       ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Prescaler_Reload_Mode 
+  * @{
+  */
+
+#define TIM_PSCReloadMode_Update           ((uint16_t)0x0000)
+#define TIM_PSCReloadMode_Immediate        ((uint16_t)0x0001)
+#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
+                                         ((RELOAD) == TIM_PSCReloadMode_Immediate))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Forced_Action 
+  * @{
+  */
+
+#define TIM_ForcedAction_Active            ((uint16_t)0x0050)
+#define TIM_ForcedAction_InActive          ((uint16_t)0x0040)
+#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
+                                      ((ACTION) == TIM_ForcedAction_InActive))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Encoder_Mode 
+  * @{
+  */
+
+#define TIM_EncoderMode_TI1                ((uint16_t)0x0001)
+#define TIM_EncoderMode_TI2                ((uint16_t)0x0002)
+#define TIM_EncoderMode_TI12               ((uint16_t)0x0003)
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
+                                   ((MODE) == TIM_EncoderMode_TI2) || \
+                                   ((MODE) == TIM_EncoderMode_TI12))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup TIM_Event_Source 
+  * @{
+  */
+
+#define TIM_EventSource_Update             ((uint16_t)0x0001)
+#define TIM_EventSource_CC1                ((uint16_t)0x0002)
+#define TIM_EventSource_CC2                ((uint16_t)0x0004)
+#define TIM_EventSource_CC3                ((uint16_t)0x0008)
+#define TIM_EventSource_CC4                ((uint16_t)0x0010)
+#define TIM_EventSource_COM                ((uint16_t)0x0020)
+#define TIM_EventSource_Trigger            ((uint16_t)0x0040)
+#define TIM_EventSource_Break              ((uint16_t)0x0080)
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Update_Source 
+  * @{
+  */
+
+#define TIM_UpdateSource_Global            ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
+                                                                   or the setting of UG bit, or an update generation
+                                                                   through the slave mode controller. */
+#define TIM_UpdateSource_Regular           ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
+#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
+                                      ((SOURCE) == TIM_UpdateSource_Regular))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_Preload_State 
+  * @{
+  */
+
+#define TIM_OCPreload_Enable               ((uint16_t)0x0008)
+#define TIM_OCPreload_Disable              ((uint16_t)0x0000)
+#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
+                                       ((STATE) == TIM_OCPreload_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_Fast_State 
+  * @{
+  */
+
+#define TIM_OCFast_Enable                  ((uint16_t)0x0004)
+#define TIM_OCFast_Disable                 ((uint16_t)0x0000)
+#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
+                                    ((STATE) == TIM_OCFast_Disable))
+                                     
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_Clear_State 
+  * @{
+  */
+
+#define TIM_OCClear_Enable                 ((uint16_t)0x0080)
+#define TIM_OCClear_Disable                ((uint16_t)0x0000)
+#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
+                                     ((STATE) == TIM_OCClear_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Trigger_Output_Source 
+  * @{
+  */
+
+#define TIM_TRGOSource_Reset               ((uint16_t)0x0000)
+#define TIM_TRGOSource_Enable              ((uint16_t)0x0010)
+#define TIM_TRGOSource_Update              ((uint16_t)0x0020)
+#define TIM_TRGOSource_OC1                 ((uint16_t)0x0030)
+#define TIM_TRGOSource_OC1Ref              ((uint16_t)0x0040)
+#define TIM_TRGOSource_OC2Ref              ((uint16_t)0x0050)
+#define TIM_TRGOSource_OC3Ref              ((uint16_t)0x0060)
+#define TIM_TRGOSource_OC4Ref              ((uint16_t)0x0070)
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
+                                    ((SOURCE) == TIM_TRGOSource_Enable) || \
+                                    ((SOURCE) == TIM_TRGOSource_Update) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC1) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC4Ref))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Slave_Mode 
+  * @{
+  */
+
+#define TIM_SlaveMode_Reset                ((uint16_t)0x0004)
+#define TIM_SlaveMode_Gated                ((uint16_t)0x0005)
+#define TIM_SlaveMode_Trigger              ((uint16_t)0x0006)
+#define TIM_SlaveMode_External1            ((uint16_t)0x0007)
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
+                                 ((MODE) == TIM_SlaveMode_Gated) || \
+                                 ((MODE) == TIM_SlaveMode_Trigger) || \
+                                 ((MODE) == TIM_SlaveMode_External1))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Master_Slave_Mode 
+  * @{
+  */
+
+#define TIM_MasterSlaveMode_Enable         ((uint16_t)0x0080)
+#define TIM_MasterSlaveMode_Disable        ((uint16_t)0x0000)
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
+                                 ((STATE) == TIM_MasterSlaveMode_Disable))
+/**
+  * @}
+  */ 
+  
+/** @defgroup TIM_Flags 
+  * @{
+  */
+
+#define TIM_FLAG_Update                    ((uint16_t)0x0001)
+#define TIM_FLAG_CC1                       ((uint16_t)0x0002)
+#define TIM_FLAG_CC2                       ((uint16_t)0x0004)
+#define TIM_FLAG_CC3                       ((uint16_t)0x0008)
+#define TIM_FLAG_CC4                       ((uint16_t)0x0010)
+#define TIM_FLAG_COM                       ((uint16_t)0x0020)
+#define TIM_FLAG_Trigger                   ((uint16_t)0x0040)
+#define TIM_FLAG_Break                     ((uint16_t)0x0080)
+#define TIM_FLAG_CC1OF                     ((uint16_t)0x0200)
+#define TIM_FLAG_CC2OF                     ((uint16_t)0x0400)
+#define TIM_FLAG_CC3OF                     ((uint16_t)0x0800)
+#define TIM_FLAG_CC4OF                     ((uint16_t)0x1000)
+#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
+                               ((FLAG) == TIM_FLAG_CC1) || \
+                               ((FLAG) == TIM_FLAG_CC2) || \
+                               ((FLAG) == TIM_FLAG_CC3) || \
+                               ((FLAG) == TIM_FLAG_CC4) || \
+                               ((FLAG) == TIM_FLAG_COM) || \
+                               ((FLAG) == TIM_FLAG_Trigger) || \
+                               ((FLAG) == TIM_FLAG_Break) || \
+                               ((FLAG) == TIM_FLAG_CC1OF) || \
+                               ((FLAG) == TIM_FLAG_CC2OF) || \
+                               ((FLAG) == TIM_FLAG_CC3OF) || \
+                               ((FLAG) == TIM_FLAG_CC4OF))
+                               
+                               
+#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup TIM_Input_Capture_Filer_Value 
+  * @{
+  */
+
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) 
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_External_Trigger_Filter 
+  * @{
+  */
+
+#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_OCReferenceClear 
+  * @{
+  */
+#define TIM_OCReferenceClear_ETRF          ((uint16_t)0x0008)
+#define TIM_OCReferenceClear_OCREFCLR      ((uint16_t)0x0000)
+#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \
+                                              ((SOURCE) == TIM_OCReferenceClear_OCREFCLR)) 
+
+/**
+  * @}
+  */
+/** @defgroup TIM_Remap 
+  * @{
+  */
+#define TIM14_GPIO                      ((uint16_t)0x0000)
+#define TIM14_RTC_CLK                   ((uint16_t)0x0001)
+#define TIM14_HSEDiv32                  ((uint16_t)0x0002)
+#define TIM14_MCO                       ((uint16_t)0x0003)
+
+#define IS_TIM_REMAP(TIM_REMAP)  (((TIM_REMAP) == TIM14_GPIO)|| \
+                                  ((TIM_REMAP) == TIM14_RTC_CLK) || \
+                                  ((TIM_REMAP) == TIM14_HSEDiv32) || \
+                                  ((TIM_REMAP) == TIM14_MCO))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Legacy 
+  * @{
+  */
+
+#define TIM_DMABurstLength_1Byte           TIM_DMABurstLength_1Transfer
+#define TIM_DMABurstLength_2Bytes          TIM_DMABurstLength_2Transfers
+#define TIM_DMABurstLength_3Bytes          TIM_DMABurstLength_3Transfers
+#define TIM_DMABurstLength_4Bytes          TIM_DMABurstLength_4Transfers
+#define TIM_DMABurstLength_5Bytes          TIM_DMABurstLength_5Transfers
+#define TIM_DMABurstLength_6Bytes          TIM_DMABurstLength_6Transfers
+#define TIM_DMABurstLength_7Bytes          TIM_DMABurstLength_7Transfers
+#define TIM_DMABurstLength_8Bytes          TIM_DMABurstLength_8Transfers
+#define TIM_DMABurstLength_9Bytes          TIM_DMABurstLength_9Transfers
+#define TIM_DMABurstLength_10Bytes         TIM_DMABurstLength_10Transfers
+#define TIM_DMABurstLength_11Bytes         TIM_DMABurstLength_11Transfers
+#define TIM_DMABurstLength_12Bytes         TIM_DMABurstLength_12Transfers
+#define TIM_DMABurstLength_13Bytes         TIM_DMABurstLength_13Transfers
+#define TIM_DMABurstLength_14Bytes         TIM_DMABurstLength_14Transfers
+#define TIM_DMABurstLength_15Bytes         TIM_DMABurstLength_15Transfers
+#define TIM_DMABurstLength_16Bytes         TIM_DMABurstLength_16Transfers
+#define TIM_DMABurstLength_17Bytes         TIM_DMABurstLength_17Transfers
+#define TIM_DMABurstLength_18Bytes         TIM_DMABurstLength_18Transfers
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */ 
+
+/* TimeBase management ********************************************************/
+void TIM_DeInit(TIM_TypeDef* TIMx);
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
+uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Advanced-control timers (TIM1) specific features*******************/
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Output Compare management **************************************************/
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Input Capture management ***************************************************/
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
+uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
+uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
+uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+
+/* Interrupts, DMA and flags management ***************************************/
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Clocks management **********************************************************/
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
+                                uint16_t TIM_ICPolarity, uint16_t ICFilter);
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                             uint16_t ExtTRGFilter);
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 
+                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
+
+
+/* Synchronization management *************************************************/
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                   uint16_t ExtTRGFilter);
+
+/* Specific interface management **********************************************/                   
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
+                                uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Specific remapping management **********************************************/
+void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F0XX_TIM_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_usart.h b/system/include/stm32f0-stdperiph/stm32f0xx_usart.h

new file mode 100644 (file)

index 0000000..2e73252
--- /dev/null
+++ b/system/include/stm32f0-stdperiph/stm32f0xx_usart.h
@@ -0,0 +1,604 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_usart.h
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file contains all the functions prototypes for the USART 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_USART_H
+#define __STM32F0XX_USART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup USART
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+   
+   
+/** 
+  * @brief  USART Init Structure definition  
+  */ 
+
+typedef struct
+{
+  uint32_t USART_BaudRate;            /*!< This member configures the USART communication baud rate.
+                                           The baud rate is computed using the following formula:
+                                            - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
+                                            - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
+
+  uint32_t USART_WordLength;          /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref USART_Word_Length */
+
+  uint32_t USART_StopBits;            /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref USART_Stop_Bits */
+
+  uint32_t USART_Parity;              /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref USART_Parity
+                                           @note When parity is enabled, the computed parity is inserted
+                                                 at the MSB position of the transmitted data (9th bit when
+                                                 the word length is set to 9 data bits; 8th bit when the
+                                                 word length is set to 8 data bits). */
+ 
+  uint32_t USART_Mode;                /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_Mode */
+
+  uint32_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
+                                           or disabled.
+                                           This parameter can be a value of @ref USART_Hardware_Flow_Control*/
+} USART_InitTypeDef;
+
+/** 
+  * @brief  USART Clock Init Structure definition
+  */ 
+
+typedef struct
+{
+  uint32_t USART_Clock;             /*!< Specifies whether the USART clock is enabled or disabled.
+                                         This parameter can be a value of @ref USART_Clock */
+
+  uint32_t USART_CPOL;              /*!< Specifies the steady state of the serial clock.
+                                         This parameter can be a value of @ref USART_Clock_Polarity */
+
+  uint32_t USART_CPHA;              /*!< Specifies the clock transition on which the bit capture is made.
+                                         This parameter can be a value of @ref USART_Clock_Phase */
+
+  uint32_t USART_LastBit;           /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                                         data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                                         This parameter can be a value of @ref USART_Last_Bit */
+} USART_ClockInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup USART_Exported_Constants
+  * @{
+  */ 
+
+#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+                                     ((PERIPH) == USART2) || \
+                                     ((PERIPH) == USART3) || \
+                                     ((PERIPH) == USART4) || \
+                                     ((PERIPH) == USART5) || \
+                                     ((PERIPH) == USART6) || \
+                                     ((PERIPH) == USART7) || \
+                                     ((PERIPH) == USART8))
+
+#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+                                     ((PERIPH) == USART2) || \
+                                     ((PERIPH) == USART3))
+
+/** @defgroup USART_Word_Length 
+  * @{
+  */ 
+
+#define USART_WordLength_8b                  ((uint32_t)0x00000000)
+#define USART_WordLength_9b                  USART_CR1_M /* should be ((uint32_t)0x00001000) */
+#define USART_WordLength_7b                  ((uint32_t)0x10001000) /*!< only available for STM32F072 and STM32F030 devices */
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
+                                      ((LENGTH) == USART_WordLength_9b) || \
+                                      ((LENGTH) == USART_WordLength_7b))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Stop_Bits 
+  * @{
+  */ 
+
+#define USART_StopBits_1                     ((uint32_t)0x00000000)
+#define USART_StopBits_2                     USART_CR2_STOP_1
+#define USART_StopBits_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
+                                     ((STOPBITS) == USART_StopBits_2) || \
+                                     ((STOPBITS) == USART_StopBits_1_5))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Parity 
+  * @{
+  */ 
+
+#define USART_Parity_No                      ((uint32_t)0x00000000)
+#define USART_Parity_Even                    USART_CR1_PCE
+#define USART_Parity_Odd                     (USART_CR1_PCE | USART_CR1_PS) 
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
+                                 ((PARITY) == USART_Parity_Even) || \
+                                 ((PARITY) == USART_Parity_Odd))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Mode 
+  * @{
+  */ 
+
+#define USART_Mode_Rx                        USART_CR1_RE
+#define USART_Mode_Tx                        USART_CR1_TE
+#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFFFFFF3) == 0x00) && \
+                              ((MODE) != (uint32_t)0x00))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Hardware_Flow_Control 
+  * @{
+  */ 
+
+#define USART_HardwareFlowControl_None       ((uint32_t)0x00000000)
+#define USART_HardwareFlowControl_RTS        USART_CR3_RTSE
+#define USART_HardwareFlowControl_CTS        USART_CR3_CTSE
+#define USART_HardwareFlowControl_RTS_CTS    (USART_CR3_RTSE | USART_CR3_CTSE)
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
+                              (((CONTROL) == USART_HardwareFlowControl_None) || \
+                               ((CONTROL) == USART_HardwareFlowControl_RTS) || \
+                               ((CONTROL) == USART_HardwareFlowControl_CTS) || \
+                               ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Clock 
+  * @{
+  */ 
+  
+#define USART_Clock_Disable                  ((uint32_t)0x00000000)
+#define USART_Clock_Enable                   USART_CR2_CLKEN
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
+                               ((CLOCK) == USART_Clock_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Clock_Polarity 
+  * @{
+  */
+  
+#define USART_CPOL_Low                       ((uint32_t)0x00000000)
+#define USART_CPOL_High                      USART_CR2_CPOL
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Clock_Phase
+  * @{
+  */
+
+#define USART_CPHA_1Edge                     ((uint32_t)0x00000000)
+#define USART_CPHA_2Edge                     USART_CR2_CPHA
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Last_Bit
+  * @{
+  */
+
+#define USART_LastBit_Disable                ((uint32_t)0x00000000)
+#define USART_LastBit_Enable                 USART_CR2_LBCL
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
+                                   ((LASTBIT) == USART_LastBit_Enable))
+/**
+  * @}
+  */
+  
+/** @defgroup USART_DMA_Requests 
+  * @{
+  */
+
+#define USART_DMAReq_Tx                      USART_CR3_DMAT
+#define USART_DMAReq_Rx                      USART_CR3_DMAR
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint32_t)0xFFFFFF3F) == 0x00) && \
+                                  ((DMAREQ) != (uint32_t)0x00))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_DMA_Recception_Error
+  * @{
+  */
+
+#define USART_DMAOnError_Enable              ((uint32_t)0x00000000)
+#define USART_DMAOnError_Disable             USART_CR3_DDRE
+#define IS_USART_DMAONERROR(DMAERROR) (((DMAERROR) == USART_DMAOnError_Disable)|| \
+                                       ((DMAERROR) == USART_DMAOnError_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_MuteMode_WakeUp_methods
+  * @{
+  */
+
+#define USART_WakeUp_IdleLine                ((uint32_t)0x00000000)
+#define USART_WakeUp_AddressMark             USART_CR1_WAKE
+#define IS_USART_MUTEMODE_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
+                                          ((WAKEUP) == USART_WakeUp_AddressMark))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Address_Detection
+  * @{
+  */ 
+
+#define USART_AddressLength_4b               ((uint32_t)0x00000000)
+#define USART_AddressLength_7b               USART_CR2_ADDM7
+#define IS_USART_ADDRESS_DETECTION(ADDRESS) (((ADDRESS) == USART_AddressLength_4b) || \
+                                             ((ADDRESS) == USART_AddressLength_7b))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_StopMode_WakeUp_methods
+  * @note     These parameters are only available for STM32F051 and STM32F072 devices 
+  * @{
+  */ 
+
+#define USART_WakeUpSource_AddressMatch      ((uint32_t)0x00000000)
+#define USART_WakeUpSource_StartBit          USART_CR3_WUS_1
+#define USART_WakeUpSource_RXNE              (USART_CR3_WUS_0 | USART_CR3_WUS_1)
+#define IS_USART_STOPMODE_WAKEUPSOURCE(SOURCE) (((SOURCE) == USART_WakeUpSource_AddressMatch) || \
+                                                ((SOURCE) == USART_WakeUpSource_StartBit) || \
+                                                ((SOURCE) == USART_WakeUpSource_RXNE))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_LIN_Break_Detection_Length 
+  * @{
+  */
+  
+#define USART_LINBreakDetectLength_10b       ((uint32_t)0x00000000)
+#define USART_LINBreakDetectLength_11b       USART_CR2_LBDL
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
+                               (((LENGTH) == USART_LINBreakDetectLength_10b) || \
+                                ((LENGTH) == USART_LINBreakDetectLength_11b))
+/**
+  * @}
+  */
+
+/** @defgroup USART_IrDA_Low_Power 
+  * @{
+  */
+
+#define USART_IrDAMode_LowPower              USART_CR3_IRLP
+#define USART_IrDAMode_Normal                ((uint32_t)0x00000000)
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
+                                  ((MODE) == USART_IrDAMode_Normal))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_DE_Polarity 
+  * @{
+  */
+
+#define USART_DEPolarity_High                ((uint32_t)0x00000000)
+#define USART_DEPolarity_Low                 USART_CR3_DEP
+#define IS_USART_DE_POLARITY(POLARITY) (((POLARITY) == USART_DEPolarity_Low) || \
+                                        ((POLARITY) == USART_DEPolarity_High))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Inversion_Pins 
+  * @{
+  */
+
+#define USART_InvPin_Tx                      USART_CR2_TXINV
+#define USART_InvPin_Rx                      USART_CR2_RXINV
+#define IS_USART_INVERSTION_PIN(PIN) ((((PIN) & (uint32_t)0xFFFCFFFF) == 0x00) && \
+                                       ((PIN) != (uint32_t)0x00))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_AutoBaudRate_Mode 
+  * @{
+  */
+
+#define USART_AutoBaudRate_StartBit          ((uint32_t)0x00000000)
+#define USART_AutoBaudRate_FallingEdge       USART_CR2_ABRMODE_0
+#define IS_USART_AUTOBAUDRATE_MODE(MODE) (((MODE) == USART_AutoBaudRate_StartBit) || \
+                                          ((MODE) == USART_AutoBaudRate_FallingEdge))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_OVR_DETECTION
+  * @{
+  */
+
+#define USART_OVRDetection_Enable            ((uint32_t)0x00000000)
+#define USART_OVRDetection_Disable           USART_CR3_OVRDIS
+#define IS_USART_OVRDETECTION(OVR) (((OVR) == USART_OVRDetection_Enable)|| \
+                                    ((OVR) == USART_OVRDetection_Disable))
+/**
+  * @}
+  */ 
+/** @defgroup USART_Request 
+  * @{
+  */
+
+#define USART_Request_ABRRQ                  USART_RQR_ABRRQ
+#define USART_Request_SBKRQ                  USART_RQR_SBKRQ
+#define USART_Request_MMRQ                   USART_RQR_MMRQ
+#define USART_Request_RXFRQ                  USART_RQR_RXFRQ
+#define USART_Request_TXFRQ                  USART_RQR_TXFRQ
+
+#define IS_USART_REQUEST(REQUEST) (((REQUEST) == USART_Request_TXFRQ) || \
+                                   ((REQUEST) == USART_Request_RXFRQ) || \
+                                   ((REQUEST) == USART_Request_MMRQ) || \
+                                   ((REQUEST) == USART_Request_SBKRQ) || \
+                                   ((REQUEST) == USART_Request_ABRRQ))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Flags 
+  * @{
+  */
+#define USART_FLAG_REACK                     USART_ISR_REACK
+#define USART_FLAG_TEACK                     USART_ISR_TEACK
+#define USART_FLAG_WU                        USART_ISR_WUF /*!< Not available for  STM32F030 devices */
+#define USART_FLAG_RWU                       USART_ISR_RWU /*!< Not available for  STM32F030 devices */
+#define USART_FLAG_SBK                       USART_ISR_SBKF
+#define USART_FLAG_CM                        USART_ISR_CMF
+#define USART_FLAG_BUSY                      USART_ISR_BUSY
+#define USART_FLAG_ABRF                      USART_ISR_ABRF
+#define USART_FLAG_ABRE                      USART_ISR_ABRE
+#define USART_FLAG_EOB                       USART_ISR_EOBF /*!< Not available for  STM32F030 devices */
+#define USART_FLAG_RTO                       USART_ISR_RTOF
+#define USART_FLAG_nCTSS                     USART_ISR_CTS 
+#define USART_FLAG_CTS                       USART_ISR_CTSIF
+#define USART_FLAG_LBD                       USART_ISR_LBD /*!< Not available for  STM32F030 devices */
+#define USART_FLAG_TXE                       USART_ISR_TXE
+#define USART_FLAG_TC                        USART_ISR_TC
+#define USART_FLAG_RXNE                      USART_ISR_RXNE
+#define USART_FLAG_IDLE                      USART_ISR_IDLE
+#define USART_FLAG_ORE                       USART_ISR_ORE
+#define USART_FLAG_NE                        USART_ISR_NE
+#define USART_FLAG_FE                        USART_ISR_FE
+#define USART_FLAG_PE                        USART_ISR_PE
+#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
+                             ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
+                             ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
+                             ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
+                             ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
+                             ((FLAG) == USART_FLAG_nCTSS) || ((FLAG) == USART_FLAG_RTO) || \
+                             ((FLAG) == USART_FLAG_EOB) || ((FLAG) == USART_FLAG_ABRE) || \
+                             ((FLAG) == USART_FLAG_ABRF) || ((FLAG) == USART_FLAG_BUSY) || \
+                             ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_SBK) || \
+                             ((FLAG) == USART_FLAG_RWU) || ((FLAG) == USART_FLAG_WU) || \
+                             ((FLAG) == USART_FLAG_TEACK)|| ((FLAG) == USART_FLAG_REACK))
+
+#define IS_USART_CLEAR_FLAG(FLAG) (((FLAG) == USART_FLAG_WU) || ((FLAG) == USART_FLAG_TC) || \
+                                   ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_ORE) || \
+                                   ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
+                                   ((FLAG) == USART_FLAG_LBD) || ((FLAG) == USART_FLAG_CTS) || \
+                                   ((FLAG) == USART_FLAG_RTO) || ((FLAG) == USART_FLAG_EOB) || \
+                                   ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_PE))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Interrupt_definition 
+  * @brief USART Interrupt definition
+  * USART_IT possible values
+  * Elements values convention: 0xZZZZYYXX
+  *   XX: Position of the corresponding Interrupt
+  *   YY: Register index
+  *   ZZZZ: Flag position
+  * @{
+  */
+
+#define USART_IT_WU                          ((uint32_t)0x00140316) /*!< Not available for  STM32F030 devices */
+#define USART_IT_CM                          ((uint32_t)0x0011010E)
+#define USART_IT_EOB                         ((uint32_t)0x000C011B) /*!< Not available for  STM32F030 devices */
+#define USART_IT_RTO                         ((uint32_t)0x000B011A)
+#define USART_IT_PE                          ((uint32_t)0x00000108)
+#define USART_IT_TXE                         ((uint32_t)0x00070107)
+#define USART_IT_TC                          ((uint32_t)0x00060106)
+#define USART_IT_RXNE                        ((uint32_t)0x00050105)
+#define USART_IT_IDLE                        ((uint32_t)0x00040104)
+#define USART_IT_LBD                         ((uint32_t)0x00080206) /*!< Not available for  STM32F030 devices */
+#define USART_IT_CTS                         ((uint32_t)0x0009030A) 
+#define USART_IT_ERR                         ((uint32_t)0x00000300)
+#define USART_IT_ORE                         ((uint32_t)0x00030300)
+#define USART_IT_NE                          ((uint32_t)0x00020300)
+#define USART_IT_FE                          ((uint32_t)0x00010300)
+
+#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+                                ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+                                ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+                                ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR) || \
+                                ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
+                                ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
+
+#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+                             ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+                             ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+                             ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
+                             ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE) || \
+                             ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
+                             ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
+
+#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_PE) || \
+                               ((IT) == USART_IT_FE) || ((IT) == USART_IT_NE) || \
+                               ((IT) == USART_IT_ORE) || ((IT) == USART_IT_IDLE) || \
+                               ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || \
+                               ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
+                               ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Global_definition 
+  * @{
+  */
+
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x005B8D81))
+#define IS_USART_DE_ASSERTION_DEASSERTION_TIME(TIME) ((TIME) <= 0x1F)
+#define IS_USART_AUTO_RETRY_COUNTER(COUNTER) ((COUNTER) <= 0x7)
+#define IS_USART_TIMEOUT(TIMEOUT) ((TIMEOUT) <= 0x00FFFFFF)
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Initialization and Configuration functions *********************************/
+void USART_DeInit(USART_TypeDef* USARTx);
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState);
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); /* Not available for STM32F030 devices */
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState);
+void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut);
+
+/* STOP Mode functions ********************************************************/
+void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource); /* Not available for STM32F030 devices */
+
+/* AutoBaudRate functions *****************************************************/
+void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate);
+
+/* Data transfers functions ***************************************************/
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
+
+/* Multi-Processor Communication functions ************************************/
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
+void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp);
+void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength);
+
+/* LIN mode functions *********************************************************/
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength); /* Not available for STM32F030 devices */
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); /* Not available for STM32F030 devices */
+
+/* Half-duplex mode function **************************************************/
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
+/* Smartcard mode functions ***************************************************/
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); /* Not available for STM32F030 devices */
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); /* Not available for STM32F030 devices */
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); /* Not available for STM32F030 devices */
+void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount); /* Not available for STM32F030 devices */
+void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength); /* Not available for STM32F030 devices */
+
+/* IrDA mode functions ********************************************************/
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode); /* Not available for STM32F030 devices */
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); /* Not available for STM32F030 devices */
+
+/* RS485 mode functions *******************************************************/
+void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity);
+void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime);
+void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime);
+
+/* DMA transfers management functions *****************************************/
+void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState);
+void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError);
+
+/* Interrupts and flags management functions **********************************/
+void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState);
+void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState);
+void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection);
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG);
+void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG);
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT);
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0XX_USART_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h b/system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h

new file mode 100644 (file)

index 0000000..d32d006
--- /dev/null
+++ b/system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h
@@ -0,0 +1,109 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_wwdg.h
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file contains all the functions prototypes for the WWDG 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_WWDG_H
+#define __STM32F0XX_WWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup WWDG
+  * @{
+  */ 
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Constants
+  * @{
+  */ 
+  
+/** @defgroup WWDG_Prescaler 
+  * @{
+  */ 
+  
+#define WWDG_Prescaler_1    ((uint32_t)0x00000000)
+#define WWDG_Prescaler_2    ((uint32_t)0x00000080)
+#define WWDG_Prescaler_4    ((uint32_t)0x00000100)
+#define WWDG_Prescaler_8    ((uint32_t)0x00000180)
+#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
+                                      ((PRESCALER) == WWDG_Prescaler_2) || \
+                                      ((PRESCALER) == WWDG_Prescaler_4) || \
+                                      ((PRESCALER) == WWDG_Prescaler_8))
+#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
+#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/*  Function used to set the WWDG configuration to the default reset state ****/  
+void WWDG_DeInit(void);
+
+/* Prescaler, Refresh window and Counter configuration functions **************/
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
+void WWDG_SetWindowValue(uint8_t WindowValue);
+void WWDG_EnableIT(void);
+void WWDG_SetCounter(uint8_t Counter);
+
+/* WWDG activation functions **************************************************/
+void WWDG_Enable(uint8_t Counter);
+
+/* Interrupts and flags management functions **********************************/
+FlagStatus WWDG_GetFlagStatus(void);
+void WWDG_ClearFlag(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0XX_WWDG_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/src/cmsis/README_DEVICE.txt b/system/src/cmsis/README_DEVICE.txt

new file mode 100644 (file)

index 0000000..061dbe6
--- /dev/null
+++ b/system/src/cmsis/README_DEVICE.txt
@@ -0,0 +1,7 @@
+The system_stm32f0xx.c file is from 
+STM32F0xx_StdPeriph_Lib_V1.5.0.zip, the folder:
+
+       STM32F0xx_StdPeriph_Lib_V1.5.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates
+       
+The vectors_stm32f0xx.c file was created to conform with  
+the assembly files gcc_ride7/startup_stm32f0??.s.
+\ No newline at end of file
diff --git a/system/src/cmsis/system_stm32f0xx.c b/system/src/cmsis/system_stm32f0xx.c

new file mode 100644 (file)

index 0000000..9dd7b3d
--- /dev/null
+++ b/system/src/cmsis/system_stm32f0xx.c
@@ -0,0 +1,358 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f0xx.c
+  * @author  MCD Application Team
+  * @version V1.4.0
+  * @date    05-December-2014
+  * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32F0xx devices,
+  *          and is generated by the clock configuration tool  
+  *          STM32F0xx_Clock_Configuration_V1.0.0.xls
+  *
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool.
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f0xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz Range) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
+  *    in "stm32f0xx.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  *
+  * 5. This file configures the system clock as follows:
+  *=============================================================================
+  *                         System Clock Configuration
+  *=============================================================================
+  *        System Clock source          | PLL(HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK                       | 48000000 Hz
+  *-----------------------------------------------------------------------------
+  *        HCLK                         | 48000000 Hz
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler               | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler               | 1
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency                | 8000000 Hz
+  *-----------------------------------------------------------------------------
+  *        PLL MUL                      | 6
+  *-----------------------------------------------------------------------------
+  *        VDD                          | 3.3 V
+  *-----------------------------------------------------------------------------
+  *        Flash Latency                | 1 WS
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f0xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F0xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f0xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Private_Defines
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Private_Variables
+  * @{
+  */
+uint32_t SystemCoreClock    = 48000000;
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{    
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+#if defined(STM32F051)  
+  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
+  RCC->CFGR &= (uint32_t)0xF8FFB80C;
+#else
+  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
+  RCC->CFGR &= (uint32_t)0x08FFB80C;
+#endif /* STM32F051 */
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+  RCC->CFGR &= (uint32_t)0xFFC0FFFF;
+
+  /* Reset PREDIV1[3:0] bits */
+  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+  /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
+
+  /* Reset HSI14 bit */
+  RCC->CR2 &= (uint32_t)0xFFFFFFFE;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+  /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
+  SetSysClock();
+}
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        /* HSE oscillator clock selected as PREDIV1 clock entry */
+        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+      }      
+      break;
+    default: /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, AHB/APBx prescalers and Flash
+  *         settings.
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer and set Flash Latency */
+    FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
+
+    /* PLL configuration = HSE * 6 = 48 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6);
+            
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }  
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/src/cmsis/vectors_stm32f0xx.c b/system/src/cmsis/vectors_stm32f0xx.c

new file mode 100644 (file)

index 0000000..0eb5b5f
--- /dev/null
+++ b/system/src/cmsis/vectors_stm32f0xx.c
@@ -0,0 +1,525 @@
+/*
+ * This file is part of the ??OS++ distribution.
+ *   (https://github.com/micro-os-plus)
+ * Copyright (c) 2014 Liviu Ionescu.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+// ----------------------------------------------------------------------------
+
+#include "cortexm/ExceptionHandlers.h"
+
+// ----------------------------------------------------------------------------
+
+void __attribute__((weak))
+Default_Handler(void);
+
+// Forward declaration of the specific IRQ handlers. These are aliased
+// to the Default_Handler, which is a 'forever' loop. When the application
+// defines a handler (with the same name), this will automatically take
+// precedence over these weak definitions
+
+void __attribute__ ((weak, alias ("Default_Handler")))
+WWDG_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+PVD_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+RTC_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+FLASH_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+RCC_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+EXTI0_1_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+EXTI2_3_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+EXTI4_15_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+TS_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+DMA1_Channel1_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+DMA1_Channel2_3_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+DMA1_Channel4_5_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+ADC1_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+TIM1_BRK_UP_TRG_COM_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+TIM1_CC_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+TIM2_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+TIM3_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+TIM6_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+TIM6_DAC_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+TIM14_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+TIM15_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+TIM16_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+TIM17_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+I2C1_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+I2C2_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+SPI1_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+SPI2_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+USART1_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+USART2_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+CEC_IRQHandler(void);
+
+void __attribute__ ((weak, alias ("Default_Handler")))
+ADC1_COMP_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+PVD_VDDIO2_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+VDDIO2_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+RCC_CRS_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+TSC_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+TIM7_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+USART3_4_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+USART3_6_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+USART3_8_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+CEC_CAN_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+USB_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+DMA1_Channel4_5_6_7_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler(void);
+void __attribute__ ((weak, alias ("Default_Handler")))
+DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler(void);
+
+// ----------------------------------------------------------------------------
+
+extern unsigned int _estack;
+
+typedef void
+(* const pHandler)(void);
+
+// ----------------------------------------------------------------------------
+
+// The vector table.
+// This relies on the linker script to place at correct location in memory.
+
+__attribute__ ((section(".isr_vector"),used))
+pHandler g_pfnVectors[] =
+  {
+  // Core Level - CM0
+      (pHandler) &_estack, // The initial stack pointer
+      Reset_Handler, // The reset handler
+
+      NMI_Handler, // The NMI handler
+      HardFault_Handler, // The hard fault handler
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+      MemManage_Handler,                        // The MPU fault handler
+      BusFault_Handler,                        // The bus fault handler
+      UsageFault_Handler,                        // The usage fault handler
+#else
+      0, 0, 0,                                  // Reserved
+#endif
+      0,                                        // Reserved
+      0,                                        // Reserved
+      0,                                        // Reserved
+      0,                                        // Reserved
+      SVC_Handler,                              // SVCall handler
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+      DebugMon_Handler,                         // Debug monitor handler
+#else
+      0,                                        // Reserved
+#endif
+      0, // Reserved
+      PendSV_Handler, // The PendSV handler
+      SysTick_Handler, // The SysTick handler
+
+      // ----------------------------------------------------------------------
+
+#if defined(STM32F030)
+
+      // Chip Level - STM32F030
+      WWDG_IRQHandler, //
+      0, //
+      RTC_IRQHandler, //
+      FLASH_IRQHandler, //
+      RCC_IRQHandler, //
+      EXTI0_1_IRQHandler, //
+      EXTI2_3_IRQHandler, //
+      EXTI4_15_IRQHandler, //
+      0, //
+      DMA1_Channel1_IRQHandler, //
+      DMA1_Channel2_3_IRQHandler, //
+      DMA1_Channel4_5_IRQHandler, //
+      ADC1_IRQHandler, //
+      TIM1_BRK_UP_TRG_COM_IRQHandler, //
+      TIM1_CC_IRQHandler, //
+      0, //
+      TIM3_IRQHandler, //
+      0, //
+      0, //
+      TIM14_IRQHandler, //
+      TIM15_IRQHandler, //
+      TIM16_IRQHandler, //
+      TIM17_IRQHandler, //
+      I2C1_IRQHandler, //
+      I2C2_IRQHandler, //
+      SPI1_IRQHandler, //
+      SPI2_IRQHandler, //
+      USART1_IRQHandler, //
+      USART2_IRQHandler, //
+      0, //
+      0, //
+      0, //
+
+#elif defined(STM32F030xC)
+
+      // Chip Level - STM32F030
+      WWDG_IRQHandler, //
+      0, //
+      RTC_IRQHandler, //
+      FLASH_IRQHandler, //
+      RCC_IRQHandler, //
+      EXTI0_1_IRQHandler, //
+      EXTI2_3_IRQHandler, //
+      EXTI4_15_IRQHandler, //
+      0, //
+      DMA1_Channel1_IRQHandler, //
+      DMA1_Channel2_3_IRQHandler, //
+      DMA1_Channel4_5_IRQHandler, //
+      ADC1_IRQHandler, //
+      TIM1_BRK_UP_TRG_COM_IRQHandler, //
+      TIM1_CC_IRQHandler, //
+      0, //
+      TIM3_IRQHandler, //
+      TIM6_IRQHandler, //
+      TIM7_IRQHandler, //
+      TIM14_IRQHandler, //
+      TIM15_IRQHandler, //
+      TIM16_IRQHandler, //
+      TIM17_IRQHandler, //
+      I2C1_IRQHandler, //
+      I2C2_IRQHandler, //
+      SPI1_IRQHandler, //
+      SPI2_IRQHandler, //
+      USART1_IRQHandler, //
+      USART2_IRQHandler, //
+      USART3_6_IRQHandler, //
+      0, //
+      0, //
+
+#elif defined(STM32F031)
+
+      // Chip Level - STM32F031 (was STM32F0xx LD)
+      WWDG_IRQHandler, //
+      PVD_IRQHandler, //
+      RTC_IRQHandler, //
+      FLASH_IRQHandler, //
+      RCC_IRQHandler, //
+      EXTI0_1_IRQHandler, //
+      EXTI2_3_IRQHandler, //
+      EXTI4_15_IRQHandler, //
+      0, //
+      DMA1_Channel1_IRQHandler, //
+      DMA1_Channel2_3_IRQHandler, //
+      DMA1_Channel4_5_IRQHandler, //
+      ADC1_IRQHandler, //
+      TIM1_BRK_UP_TRG_COM_IRQHandler, //
+      TIM1_CC_IRQHandler, //
+      TIM2_IRQHandler, //
+      TIM3_IRQHandler, //
+      0, //
+      0, //
+      TIM14_IRQHandler, //
+      0, //
+      TIM16_IRQHandler, //
+      TIM17_IRQHandler, //
+      I2C1_IRQHandler, //
+      0, //
+      SPI1_IRQHandler, //
+      0, //
+      USART1_IRQHandler, //
+      0, //
+      0, //
+      0, //
+      0, //
+
+#elif defined(STM32F042)
+
+      // Chip Level - STM32F042 (was STM32F0xx MD)
+      WWDG_IRQHandler, //
+      PVD_VDDIO2_IRQHandler, //
+      RTC_IRQHandler, //
+      FLASH_IRQHandler, //
+      RCC_CRS_IRQHandler, //
+      EXTI0_1_IRQHandler, //
+      EXTI2_3_IRQHandler, //
+      EXTI4_15_IRQHandler, //
+      TSC_IRQHandler, //
+      DMA1_Channel1_IRQHandler, //
+      DMA1_Channel2_3_IRQHandler, //
+      DMA1_Channel4_5_IRQHandler, //
+      ADC1_IRQHandler, //
+      TIM1_BRK_UP_TRG_COM_IRQHandler, //
+      TIM1_CC_IRQHandler, //
+      TIM2_IRQHandler, //
+      TIM3_IRQHandler, //
+      0, //
+      0, //
+      TIM14_IRQHandler, //
+      0, //
+      TIM16_IRQHandler, //
+      TIM17_IRQHandler, //
+      I2C1_IRQHandler, //
+      0, //
+      SPI1_IRQHandler, //
+      SPI2_IRQHandler, //
+      USART1_IRQHandler, //
+      USART2_IRQHandler, //
+      0, //
+      CEC_CAN_IRQHandler, //
+      USB_IRQHandler, //
+
+#elif defined(STM32F051)
+
+      // Chip Level - STM32F051 (was STM32F0xx MD)
+      WWDG_IRQHandler, //
+      PVD_IRQHandler, //
+      RTC_IRQHandler, //
+      FLASH_IRQHandler, //
+      RCC_IRQHandler, //
+      EXTI0_1_IRQHandler, //
+      EXTI2_3_IRQHandler, //
+      EXTI4_15_IRQHandler, //
+      TS_IRQHandler, //
+      DMA1_Channel1_IRQHandler, //
+      DMA1_Channel2_3_IRQHandler, //
+      DMA1_Channel4_5_IRQHandler, //
+      ADC1_COMP_IRQHandler, //
+      TIM1_BRK_UP_TRG_COM_IRQHandler, //
+      TIM1_CC_IRQHandler, //
+      TIM2_IRQHandler, //
+      TIM3_IRQHandler, //
+      TIM6_DAC_IRQHandler, //
+      0, //
+      TIM14_IRQHandler, //
+      TIM15_IRQHandler, //
+      TIM16_IRQHandler, //
+      TIM17_IRQHandler, //
+      I2C1_IRQHandler, //
+      I2C2_IRQHandler, //
+      SPI1_IRQHandler, //
+      SPI2_IRQHandler, //
+      USART1_IRQHandler, //
+      USART2_IRQHandler, //
+      0, //
+      CEC_IRQHandler, //
+      0, //
+
+#elif defined (STM32F070x6)
+
+      // Chip Level - STM32F070
+      WWDG_IRQHandler, //
+      0, //
+      RTC_IRQHandler, //
+      FLASH_IRQHandler, //
+      RCC_IRQHandler, //
+      EXTI0_1_IRQHandler, //
+      EXTI2_3_IRQHandler, //
+      EXTI4_15_IRQHandler, //
+      0, //
+      DMA1_Channel1_IRQHandler, //
+      DMA1_Channel2_3_IRQHandler, //
+      DMA1_Channel4_5_IRQHandler, //
+      ADC1_IRQHandler, //
+      TIM1_BRK_UP_TRG_COM_IRQHandler, //
+      TIM1_CC_IRQHandler, //
+      0, //
+      TIM3_IRQHandler, //
+      0, //
+      0, //
+      TIM14_IRQHandler, //
+      0, //
+      TIM16_IRQHandler, //
+      TIM17_IRQHandler, //
+      I2C1_IRQHandler, //
+      0, //
+      SPI1_IRQHandler, //
+      0, //
+      USART1_IRQHandler, //
+      USART2_IRQHandler, //
+      0, //
+      0, //
+      USB_IRQHandler, //
+
+#elif defined (STM32F070xB)
+
+      // Chip Level - STM32F070
+      WWDG_IRQHandler, //
+      0, //
+      RTC_IRQHandler, //
+      FLASH_IRQHandler, //
+      RCC_IRQHandler, //
+      EXTI0_1_IRQHandler, //
+      EXTI2_3_IRQHandler, //
+      EXTI4_15_IRQHandler, //
+      0, //
+      DMA1_Channel1_IRQHandler, //
+      DMA1_Channel2_3_IRQHandler, //
+      DMA1_Channel4_5_IRQHandler, //
+      ADC1_IRQHandler, //
+      TIM1_BRK_UP_TRG_COM_IRQHandler, //
+      TIM1_CC_IRQHandler, //
+      0, //
+      TIM3_IRQHandler, //
+      TIM6_DAC_IRQHandler, //
+      TIM7_IRQHandler, //
+      TIM14_IRQHandler, //
+      TIM15_IRQHandler, //
+      TIM16_IRQHandler, //
+      TIM17_IRQHandler, //
+      I2C1_IRQHandler, //
+      I2C2_IRQHandler, //
+      SPI1_IRQHandler, //
+      SPI2_IRQHandler, //
+      USART1_IRQHandler, //
+      USART2_IRQHandler, //
+      USART3_4_IRQHandler, //
+      0, //
+      USB_IRQHandler, //
+
+#elif defined (STM32F072)
+
+      // Chip Level - STM32F051 (was STM32F0xx MD)
+      WWDG_IRQHandler, //
+      PVD_VDDIO2_IRQHandler, //
+      RTC_IRQHandler, //
+      FLASH_IRQHandler, //
+      RCC_CRS_IRQHandler, //
+      EXTI0_1_IRQHandler, //
+      EXTI2_3_IRQHandler, //
+      EXTI4_15_IRQHandler, //
+      TSC_IRQHandler, //
+      DMA1_Channel1_IRQHandler, //
+      DMA1_Channel2_3_IRQHandler, //
+      DMA1_Channel4_5_6_7_IRQHandler, //
+      ADC1_COMP_IRQHandler, //
+      TIM1_BRK_UP_TRG_COM_IRQHandler, //
+      TIM1_CC_IRQHandler, //
+      TIM2_IRQHandler, //
+      TIM3_IRQHandler, //
+      TIM6_DAC_IRQHandler, //
+      TIM7_IRQHandler, //
+      TIM14_IRQHandler, //
+      TIM15_IRQHandler, //
+      TIM16_IRQHandler, //
+      TIM17_IRQHandler, //
+      I2C1_IRQHandler, //
+      I2C2_IRQHandler, //
+      SPI1_IRQHandler, //
+      SPI2_IRQHandler, //
+      USART1_IRQHandler, //
+      USART2_IRQHandler, //
+      USART3_4_IRQHandler, //
+      CEC_CAN_IRQHandler, //
+      USB_IRQHandler, //
+
+#elif defined (STM32F091)
+
+      // Chip Level - STM32F091
+      WWDG_IRQHandler, //
+      PVD_VDDIO2_IRQHandler, //
+      RTC_IRQHandler, //
+      FLASH_IRQHandler, //
+      RCC_CRS_IRQHandler, //
+      EXTI0_1_IRQHandler, //
+      EXTI2_3_IRQHandler, //
+      EXTI4_15_IRQHandler, //
+      TSC_IRQHandler, //
+      DMA1_Channel1_IRQHandler, //
+      DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler, //
+      DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler, //
+      ADC1_COMP_IRQHandler, //
+      TIM1_BRK_UP_TRG_COM_IRQHandler, //
+      TIM1_CC_IRQHandler, //
+      TIM2_IRQHandler, //
+      TIM3_IRQHandler, //
+      TIM6_DAC_IRQHandler, //
+      TIM7_IRQHandler, //
+      TIM14_IRQHandler, //
+      TIM15_IRQHandler, //
+      TIM16_IRQHandler, //
+      TIM17_IRQHandler, //
+      I2C1_IRQHandler, //
+      I2C2_IRQHandler, //
+      SPI1_IRQHandler, //
+      SPI2_IRQHandler, //
+      USART1_IRQHandler, //
+      USART2_IRQHandler, //
+      USART3_8_IRQHandler, //
+      CEC_CAN_IRQHandler, //
+      0, //
+
+#else
+#error "missing vectors"
+#endif
+
+      // @0x108. This is for boot in RAM mode for STM32F0xx devices.
+      (pHandler) 0xF108F85F
+
+  };
+
+// ----------------------------------------------------------------------------
+
+// Processor ends up here if an unexpected interrupt occurs or a specific
+// handler is not present in the application code.
+
+void __attribute__ ((section(".after_vectors")))
+Default_Handler(void)
+{
+#if defined(DEBUG)
+  __DEBUG_BKPT();
+#endif
+  while (1)
+    {
+    }
+}
+
+// ----------------------------------------------------------------------------
diff --git a/system/src/cortexm/_initialize_hardware.c b/system/src/cortexm/_initialize_hardware.c

new file mode 100644 (file)

index 0000000..90a7772
--- /dev/null
+++ b/system/src/cortexm/_initialize_hardware.c
@@ -0,0 +1,109 @@
+/*
+ * This file is part of the ??OS++ distribution.
+ *   (https://github.com/micro-os-plus)
+ * Copyright (c) 2014 Liviu Ionescu.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+// ----------------------------------------------------------------------------
+
+#include "cmsis_device.h"
+
+// ----------------------------------------------------------------------------
+
+extern unsigned int __vectors_start;
+
+// Forward declarations.
+
+void
+__initialize_hardware_early(void);
+
+void
+__initialize_hardware(void);
+
+// ----------------------------------------------------------------------------
+
+// This is the early hardware initialisation routine, it can be
+// redefined in the application for more complex cases that
+// require early inits (before BSS init).
+//
+// Called early from _start(), right before data & bss init.
+//
+// After Reset the Cortex-M processor is in Thread mode,
+// priority is Privileged, and the Stack is set to Main.
+
+void
+__attribute__((weak))
+__initialize_hardware_early(void)
+{
+  // Call the CSMSIS system initialisation routine.
+  SystemInit();
+
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+  // Set VTOR to the actual address, provided by the linker script.
+  // Override the manual, possibly wrong, SystemInit() setting.
+  SCB->VTOR = (uint32_t)(&__vectors_start);
+#endif
+
+  // The current version of SystemInit() leaves the value of the clock
+  // in a RAM variable (SystemCoreClock), which will be cleared shortly,
+  // so it needs to be recomputed after the RAM initialisations
+  // are completed.
+
+#if defined(OS_INCLUDE_STARTUP_INIT_FP) || (defined (__VFP_FP__) && !defined (__SOFTFP__))
+
+  // Normally FP init is done by SystemInit(). In case this is not done
+  // there, it is possible to force its inclusion by defining
+  // OS_INCLUDE_STARTUP_INIT_FP.
+
+  // Enable the Cortex-M4 FPU only when -mfloat-abi=hard.
+  // Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
+
+  // Set bits 20-23 to enable CP10 and CP11 coprocessor
+  SCB->CPACR |= (0xF << 20);
+
+#endif // (__VFP_FP__) && !(__SOFTFP__)
+
+#if defined(OS_DEBUG_SEMIHOSTING_FAULTS)
+  SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk;
+#endif
+}
+
+// This is the second hardware initialisation routine, it can be
+// redefined in the application for more complex cases that
+// require custom inits (before constructors), otherwise these can
+// be done in main().
+//
+// Called from _start(), right after data & bss init, before
+// constructors.
+
+void
+__attribute__((weak))
+__initialize_hardware(void)
+{
+  // Call the CSMSIS system clock routine to store the clock frequency
+  // in the SystemCoreClock global RAM location.
+  SystemCoreClockUpdate();
+}
+
+// ----------------------------------------------------------------------------
diff --git a/system/src/cortexm/_reset_hardware.c b/system/src/cortexm/_reset_hardware.c

new file mode 100644 (file)

index 0000000..52f2e64
--- /dev/null
+++ b/system/src/cortexm/_reset_hardware.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the ??OS++ distribution.
+ *   (https://github.com/micro-os-plus)
+ * Copyright (c) 2014 Liviu Ionescu.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+// ----------------------------------------------------------------------------
+
+#include "cmsis_device.h"
+
+// ----------------------------------------------------------------------------
+
+extern void
+__attribute__((noreturn))
+NVIC_SystemReset(void);
+
+// ----------------------------------------------------------------------------
+
+// Forward declarations
+
+void
+__reset_hardware(void);
+
+// ----------------------------------------------------------------------------
+
+// This is the default hardware reset routine; it can be
+// redefined in the application for more complex applications.
+//
+// Called from _exit().
+
+void
+__attribute__((weak,noreturn))
+__reset_hardware()
+{
+  NVIC_SystemReset();
+}
+
+// ----------------------------------------------------------------------------
diff --git a/system/src/cortexm/exception_handlers.c b/system/src/cortexm/exception_handlers.c

new file mode 100644 (file)

index 0000000..e6bcf9c
--- /dev/null
+++ b/system/src/cortexm/exception_handlers.c
@@ -0,0 +1,621 @@
+/*
+ * This file is part of the ??OS++ distribution.
+ *   (https://github.com/micro-os-plus)
+ * Copyright (c) 2014 Liviu Ionescu.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+// ----------------------------------------------------------------------------
+
+#include "cortexm/ExceptionHandlers.h"
+#include "cmsis_device.h"
+#include "arm/semihosting.h"
+#include "diag/Trace.h"
+#include <string.h>
+
+// ----------------------------------------------------------------------------
+
+extern void
+__attribute__((noreturn,weak))
+_start (void);
+
+// ----------------------------------------------------------------------------
+// Default exception handlers. Override the ones here by defining your own
+// handler routines in your application code.
+// ----------------------------------------------------------------------------
+
+#if defined(DEBUG)
+
+// The DEBUG version is not naked, but has a proper stack frame,
+// to allow setting breakpoints at Reset_Handler.
+void __attribute__ ((section(".after_vectors"),noreturn))
+Reset_Handler (void)
+{
+  _start ();
+}
+
+#else
+
+// The Release version is optimised to a quick branch to _start.
+void __attribute__ ((section(".after_vectors"),naked))
+Reset_Handler(void)
+  {
+    asm volatile
+    (
+        " ldr     r0,=_start \n"
+        " bx      r0"
+        :
+        :
+        :
+    );
+  }
+
+#endif
+
+void __attribute__ ((section(".after_vectors"),weak))
+NMI_Handler (void)
+{
+#if defined(DEBUG)
+  __DEBUG_BKPT();
+#endif
+  while (1)
+    {
+    }
+}
+
+// ----------------------------------------------------------------------------
+
+#if defined(TRACE)
+
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+
+// The values of BFAR and MMFAR stay unchanged if the BFARVALID or
+// MMARVALID is set. However, if a new fault occurs during the
+// execution of this fault handler, the value of the BFAR and MMFAR
+// could potentially be erased. In order to ensure the fault addresses
+// accessed are valid, the following procedure should be used:
+// 1. Read BFAR/MMFAR.
+// 2. Read CFSR to get BFARVALID or MMARVALID. If the value is 0, the
+//    value of BFAR or MMFAR accessed can be invalid and can be discarded.
+// 3. Optionally clear BFARVALID or MMARVALID.
+// (See Joseph Yiu's book).
+
+void
+dumpExceptionStack (ExceptionStackFrame* frame,
+                uint32_t cfsr, uint32_t mmfar, uint32_t bfar,
+                                        uint32_t lr)
+{
+  trace_printf ("Stack frame:\n");
+  trace_printf (" R0 =  %08X\n", frame->r0);
+  trace_printf (" R1 =  %08X\n", frame->r1);
+  trace_printf (" R2 =  %08X\n", frame->r2);
+  trace_printf (" R3 =  %08X\n", frame->r3);
+  trace_printf (" R12 = %08X\n", frame->r12);
+  trace_printf (" LR =  %08X\n", frame->lr);
+  trace_printf (" PC =  %08X\n", frame->pc);
+  trace_printf (" PSR = %08X\n", frame->psr);
+  trace_printf ("FSR/FAR:\n");
+  trace_printf (" CFSR =  %08X\n", cfsr);
+  trace_printf (" HFSR =  %08X\n", SCB->HFSR);
+  trace_printf (" DFSR =  %08X\n", SCB->DFSR);
+  trace_printf (" AFSR =  %08X\n", SCB->AFSR);
+
+  if (cfsr & (1UL << 7))
+    {
+      trace_printf (" MMFAR = %08X\n", mmfar);
+    }
+  if (cfsr & (1UL << 15))
+    {
+      trace_printf (" BFAR =  %08X\n", bfar);
+    }
+  trace_printf ("Misc\n");
+  trace_printf (" LR/EXC_RETURN= %08X\n", lr);
+}
+
+#endif // defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+
+#if defined(__ARM_ARCH_6M__)
+
+void
+dumpExceptionStack (ExceptionStackFrame* frame, uint32_t lr)
+{
+  trace_printf ("Stack frame:\n");
+  trace_printf (" R0 =  %08X\n", frame->r0);
+  trace_printf (" R1 =  %08X\n", frame->r1);
+  trace_printf (" R2 =  %08X\n", frame->r2);
+  trace_printf (" R3 =  %08X\n", frame->r3);
+  trace_printf (" R12 = %08X\n", frame->r12);
+  trace_printf (" LR =  %08X\n", frame->lr);
+  trace_printf (" PC =  %08X\n", frame->pc);
+  trace_printf (" PSR = %08X\n", frame->psr);
+  trace_printf ("Misc\n");
+  trace_printf (" LR/EXC_RETURN= %08X\n", lr);
+}
+
+#endif // defined(__ARM_ARCH_6M__)
+
+#endif // defined(TRACE)
+
+// ----------------------------------------------------------------------------
+
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+
+#if defined(OS_USE_SEMIHOSTING) || defined(OS_USE_TRACE_SEMIHOSTING_STDOUT) || defined(OS_USE_TRACE_SEMIHOSTING_DEBUG)
+
+int
+isSemihosting (ExceptionStackFrame* frame, uint16_t opCode);
+
+/**
+ * This function provides the minimum functionality to make a semihosting program execute even without the debugger present.
+ * @param frame pointer to an exception stack frame.
+ * @param opCode the 16-bin word of the BKPT instruction.
+ * @return 1 if the instruction was a valid semihosting call; 0 otherwise.
+ */
+int
+isSemihosting (ExceptionStackFrame* frame, uint16_t opCode)
+{
+  uint16_t* pw = (uint16_t*) frame->pc;
+  if (*pw == opCode)
+    {
+      uint32_t r0 = frame->r0;
+#if defined(OS_DEBUG_SEMIHOSTING_FAULTS) || defined(OS_USE_SEMIHOSTING) || defined(OS_USE_TRACE_SEMIHOSTING_STDOUT)
+      uint32_t r1 = frame->r1;
+#endif
+#if defined(OS_USE_SEMIHOSTING) || defined(OS_USE_TRACE_SEMIHOSTING_STDOUT)
+      uint32_t* blk = (uint32_t*) r1;
+#endif
+
+#if defined(OS_DEBUG_SEMIHOSTING_FAULTS)
+      // trace_printf ("sh r0=%d\n", r0);
+#endif
+
+      switch (r0)
+        {
+
+#if defined(OS_USE_SEMIHOSTING)
+
+        case SEMIHOSTING_SYS_CLOCK:
+        case SEMIHOSTING_SYS_ELAPSED:
+        case SEMIHOSTING_SYS_FLEN:
+        case SEMIHOSTING_SYS_GET_CMDLINE:
+        case SEMIHOSTING_SYS_REMOVE:
+        case SEMIHOSTING_SYS_RENAME:
+        case SEMIHOSTING_SYS_SEEK:
+        case SEMIHOSTING_SYS_SYSTEM:
+        case SEMIHOSTING_SYS_TICKFREQ:
+        case SEMIHOSTING_SYS_TMPNAM:
+        case SEMIHOSTING_SYS_ISTTY:
+          frame->r0 = (uint32_t)-1; // the call is not successful or not supported
+          break;
+
+        case SEMIHOSTING_SYS_CLOSE:
+          frame->r0 = 0; // call is successful
+          break;
+
+        case SEMIHOSTING_SYS_ERRNO:
+          frame->r0 = 0; // the value of the C library errno variable.
+          break;
+
+        case SEMIHOSTING_SYS_HEAPINFO:
+          blk[0] = 0; // heap_base
+          blk[1] = 0; // heap_limit
+          blk[2] = 0; // stack_base
+          blk[3] = 0; // stack_limit
+          break;
+
+        case SEMIHOSTING_SYS_ISERROR:
+          frame->r0 = 0; // 0 if the status word is not an error indication
+          break;
+
+        case SEMIHOSTING_SYS_READ:
+          // If R0 contains the same value as word 3, the call has
+          // failed and EOF is assumed.
+          frame->r0 = blk[2];
+          break;
+
+        case SEMIHOSTING_SYS_READC:
+          frame->r0 = '\0'; // the byte read from the console.
+          break;
+
+        case SEMIHOSTING_SYS_TIME:
+          frame->r0 = 0; // the number of seconds since 00:00 January 1, 1970.
+          break;
+
+        case SEMIHOSTING_ReportException:
+
+          NVIC_SystemReset ();
+          // Should not reach here
+          return 0;
+
+#endif // defined(OS_USE_SEMIHOSTING)
+
+#if defined(OS_USE_SEMIHOSTING) || defined(OS_USE_TRACE_SEMIHOSTING_STDOUT)
+
+#define HANDLER_STDIN   (1)
+#define HANDLER_STDOUT  (2)
+#define HANDLER_STDERR  (3)
+
+        case SEMIHOSTING_SYS_OPEN:
+          // Process only standard io/out/err and return 1/2/3
+          if (strcmp ((char*) blk[0], ":tt") == 0)
+            {
+              if ((blk[1] == 0))
+                {
+                  frame->r0 = HANDLER_STDIN;
+                  break;
+                }
+              else if (blk[1] == 4)
+                {
+                  frame->r0 = HANDLER_STDOUT;
+                  break;
+                }
+              else if (blk[1] == 8)
+                {
+                  frame->r0 = HANDLER_STDERR;
+                  break;
+                }
+            }
+          frame->r0 = (uint32_t)-1; // the call is not successful or not supported
+          break;
+
+        case SEMIHOSTING_SYS_WRITE:
+          // Silently ignore writes to stdout/stderr, fail on all other handler.
+          if ((blk[0] == HANDLER_STDOUT) || (blk[0] == HANDLER_STDERR))
+            {
+#if defined(OS_DEBUG_SEMIHOSTING_FAULTS)
+              frame->r0 = (uint32_t) blk[2]
+                  - trace_write ((char*) blk[1], blk[2]);
+#else
+              frame->r0 = 0; // all sent, no more.
+#endif // defined(OS_DEBUG_SEMIHOSTING_FAULTS)
+            }
+          else
+            {
+              // If other handler, return the total number of bytes
+              // as the number of bytes that are not written.
+              frame->r0 = blk[2];
+            }
+          break;
+
+#endif // defined(OS_USE_SEMIHOSTING) || defined(OS_USE_TRACE_SEMIHOSTING_STDOUT)
+
+#if defined(OS_USE_SEMIHOSTING) || defined(OS_USE_TRACE_SEMIHOSTING_STDOUT) || defined(OS_USE_TRACE_SEMIHOSTING_DEBUG)
+
+        case SEMIHOSTING_SYS_WRITEC:
+#if defined(OS_DEBUG_SEMIHOSTING_FAULTS)
+          {
+            char ch = *((char*) r1);
+            trace_write (&ch, 1);
+          }
+#endif
+          // Register R0 is corrupted.
+          break;
+
+        case SEMIHOSTING_SYS_WRITE0:
+#if defined(OS_DEBUG_SEMIHOSTING_FAULTS)
+          {
+            char* p = ((char*) r1);
+            trace_write (p, strlen (p));
+          }
+#endif
+          // Register R0 is corrupted.
+          break;
+
+#endif
+
+        default:
+          return 0;
+        }
+
+      // Alter the PC to make the exception returns to
+      // the instruction after the faulty BKPT.
+      frame->pc += 2;
+      return 1;
+    }
+  return 0;
+}
+
+#endif
+
+// Hard Fault handler wrapper in assembly.
+// It extracts the location of stack frame and passes it to handler
+// in C as a pointer. We also pass the LR value as second
+// parameter.
+// (Based on Joseph Yiu's, The Definitive Guide to ARM Cortex-M3 and
+// Cortex-M4 Processors, Third Edition, Chap. 12.8, page 402).
+
+void __attribute__ ((section(".after_vectors"),weak,naked))
+HardFault_Handler (void)
+{
+  asm volatile(
+      " tst lr,#4       \n"
+      " ite eq          \n"
+      " mrseq r0,msp    \n"
+      " mrsne r0,psp    \n"
+      " mov r1,lr       \n"
+      " ldr r2,=HardFault_Handler_C \n"
+      " bx r2"
+
+      : /* Outputs */
+      : /* Inputs */
+      : /* Clobbers */
+  );
+}
+
+void __attribute__ ((section(".after_vectors"),weak,used))
+HardFault_Handler_C (ExceptionStackFrame* frame __attribute__((unused)),
+                     uint32_t lr __attribute__((unused)))
+{
+#if defined(TRACE)
+  uint32_t mmfar = SCB->MMFAR; // MemManage Fault Address
+  uint32_t bfar = SCB->BFAR; // Bus Fault Address
+  uint32_t cfsr = SCB->CFSR; // Configurable Fault Status Registers
+#endif
+
+#if defined(OS_USE_SEMIHOSTING) || defined(OS_USE_TRACE_SEMIHOSTING_STDOUT) || defined(OS_USE_TRACE_SEMIHOSTING_DEBUG)
+
+  // If the BKPT instruction is executed with C_DEBUGEN == 0 and MON_EN == 0,
+  // it will cause the processor to enter a HardFault exception, with DEBUGEVT
+  // in the Hard Fault Status register (HFSR) set to 1, and BKPT in the
+  // Debug Fault Status register (DFSR) also set to 1.
+
+  if (((SCB->DFSR & SCB_DFSR_BKPT_Msk) != 0)
+      && ((SCB->HFSR & SCB_HFSR_DEBUGEVT_Msk) != 0))
+    {
+      if (isSemihosting (frame, 0xBE00 + (AngelSWI & 0xFF)))
+        {
+          // Clear the exception cause in exception status.
+          SCB->HFSR = SCB_HFSR_DEBUGEVT_Msk;
+
+          // Continue after the BKPT
+          return;
+        }
+    }
+
+#endif
+
+#if defined(TRACE)
+  trace_printf ("[HardFault]\n");
+  dumpExceptionStack (frame, cfsr, mmfar, bfar, lr);
+#endif // defined(TRACE)
+
+#if defined(DEBUG)
+  __DEBUG_BKPT();
+#endif
+  while (1)
+    {
+    }
+}
+
+#endif // defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+
+
+#if defined(__ARM_ARCH_6M__)
+
+// Hard Fault handler wrapper in assembly.
+// It extracts the location of stack frame and passes it to handler
+// in C as a pointer. We also pass the LR value as second
+// parameter.
+// (Based on Joseph Yiu's, The Definitive Guide to ARM Cortex-M0
+// First Edition, Chap. 12.8, page 402).
+
+void __attribute__ ((section(".after_vectors"),weak,naked))
+HardFault_Handler (void)
+{
+  asm volatile(
+      " movs r0,#4      \n"
+      " mov r1,lr       \n"
+      " tst r0,r1       \n"
+      " beq 1f          \n"
+      " mrs r0,psp      \n"
+      " b   2f          \n"
+      "1:               \n"
+      " mrs r0,msp      \n"
+      "2:"
+      " mov r1,lr       \n"
+      " ldr r2,=HardFault_Handler_C \n"
+      " bx r2"
+
+      : /* Outputs */
+      : /* Inputs */
+      : /* Clobbers */
+  );
+}
+
+void __attribute__ ((section(".after_vectors"),weak,used))
+HardFault_Handler_C (ExceptionStackFrame* frame __attribute__((unused)),
+                     uint32_t lr __attribute__((unused)))
+{
+  // There is no semihosting support for Cortex-M0, since on ARMv6-M
+  // faults are fatal and it is not possible to return from the handler.
+
+#if defined(TRACE)
+  trace_printf ("[HardFault]\n");
+  dumpExceptionStack (frame, lr);
+#endif // defined(TRACE)
+
+#if defined(DEBUG)
+  __DEBUG_BKPT();
+#endif
+  while (1)
+    {
+    }
+}
+
+#endif // defined(__ARM_ARCH_6M__)
+
+
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+
+void __attribute__ ((section(".after_vectors"),weak))
+MemManage_Handler (void)
+{
+#if defined(DEBUG)
+  __DEBUG_BKPT();
+#endif
+  while (1)
+    {
+    }
+}
+
+void __attribute__ ((section(".after_vectors"),weak,naked))
+BusFault_Handler (void)
+{
+  asm volatile(
+      " tst lr,#4       \n"
+      " ite eq          \n"
+      " mrseq r0,msp    \n"
+      " mrsne r0,psp    \n"
+      " mov r1,lr       \n"
+      " ldr r2,=BusFault_Handler_C \n"
+      " bx r2"
+
+      : /* Outputs */
+      : /* Inputs */
+      : /* Clobbers */
+  );
+}
+
+void __attribute__ ((section(".after_vectors"),weak,used))
+BusFault_Handler_C (ExceptionStackFrame* frame __attribute__((unused)),
+                    uint32_t lr __attribute__((unused)))
+{
+#if defined(TRACE)
+  uint32_t mmfar = SCB->MMFAR; // MemManage Fault Address
+  uint32_t bfar = SCB->BFAR; // Bus Fault Address
+  uint32_t cfsr = SCB->CFSR; // Configurable Fault Status Registers
+
+  trace_printf ("[BusFault]\n");
+  dumpExceptionStack (frame, cfsr, mmfar, bfar, lr);
+#endif // defined(TRACE)
+
+#if defined(DEBUG)
+  __DEBUG_BKPT();
+#endif
+  while (1)
+    {
+    }
+}
+
+void __attribute__ ((section(".after_vectors"),weak,naked))
+UsageFault_Handler (void)
+{
+  asm volatile(
+      " tst lr,#4       \n"
+      " ite eq          \n"
+      " mrseq r0,msp    \n"
+      " mrsne r0,psp    \n"
+      " mov r1,lr       \n"
+      " ldr r2,=UsageFault_Handler_C \n"
+      " bx r2"
+
+      : /* Outputs */
+      : /* Inputs */
+      : /* Clobbers */
+  );
+}
+
+void __attribute__ ((section(".after_vectors"),weak,used))
+UsageFault_Handler_C (ExceptionStackFrame* frame __attribute__((unused)),
+                      uint32_t lr __attribute__((unused)))
+{
+#if defined(TRACE)
+  uint32_t mmfar = SCB->MMFAR; // MemManage Fault Address
+  uint32_t bfar = SCB->BFAR; // Bus Fault Address
+  uint32_t cfsr = SCB->CFSR; // Configurable Fault Status Registers
+#endif
+
+#if defined(OS_DEBUG_SEMIHOSTING_FAULTS)
+
+  if ((cfsr & (1UL << 16)) != 0) // UNDEFINSTR
+    {
+      // For testing purposes, instead of BKPT use 'setend be'.
+      if (isSemihosting (frame, AngelSWITestFaultOpCode))
+        {
+          return;
+        }
+    }
+
+#endif
+
+#if defined(TRACE)
+  trace_printf ("[UsageFault]\n");
+  dumpExceptionStack (frame, cfsr, mmfar, bfar, lr);
+#endif // defined(TRACE)
+
+#if defined(DEBUG)
+  __DEBUG_BKPT();
+#endif
+  while (1)
+    {
+    }
+}
+
+#endif
+
+void __attribute__ ((section(".after_vectors"),weak))
+SVC_Handler (void)
+{
+#if defined(DEBUG)
+  __DEBUG_BKPT();
+#endif
+  while (1)
+    {
+    }
+}
+
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+
+void __attribute__ ((section(".after_vectors"),weak))
+DebugMon_Handler (void)
+{
+#if defined(DEBUG)
+  __DEBUG_BKPT();
+#endif
+  while (1)
+    {
+    }
+}
+
+#endif
+
+void __attribute__ ((section(".after_vectors"),weak))
+PendSV_Handler (void)
+{
+#if defined(DEBUG)
+  __DEBUG_BKPT();
+#endif
+  while (1)
+    {
+    }
+}
+
+void __attribute__ ((section(".after_vectors"),weak))
+SysTick_Handler (void)
+{
+  // DO NOT loop, just return.
+  // Useful in case someone (like STM HAL) inadvertently enables SysTick.
+  ;
+}
+
+// ----------------------------------------------------------------------------
diff --git a/system/src/diag/Trace.c b/system/src/diag/Trace.c

new file mode 100644 (file)

index 0000000..2ed60da
--- /dev/null
+++ b/system/src/diag/Trace.c
@@ -0,0 +1,98 @@
+/*
+ * This file is part of the ??OS++ distribution.
+ *   (https://github.com/micro-os-plus)
+ * Copyright (c) 2014 Liviu Ionescu.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+// ----------------------------------------------------------------------------
+
+#if defined(TRACE)
+
+#include <stdio.h>
+#include <stdarg.h>
+#include "diag/Trace.h"
+#include "string.h"
+
+#ifndef OS_INTEGER_TRACE_PRINTF_TMP_ARRAY_SIZE
+#define OS_INTEGER_TRACE_PRINTF_TMP_ARRAY_SIZE (128)
+#endif
+
+// ----------------------------------------------------------------------------
+
+int
+trace_printf(const char* format, ...)
+{
+  int ret;
+  va_list ap;
+
+  va_start (ap, format);
+
+  // TODO: rewrite it to no longer use newlib, it is way too heavy
+
+  static char buf[OS_INTEGER_TRACE_PRINTF_TMP_ARRAY_SIZE];
+
+  // Print to the local buffer
+  ret = vsnprintf (buf, sizeof(buf), format, ap);
+  if (ret > 0)
+    {
+      // Transfer the buffer to the device
+      ret = trace_write (buf, (size_t)ret);
+    }
+
+  va_end (ap);
+  return ret;
+}
+
+int
+trace_puts(const char *s)
+{
+  trace_write(s, strlen(s));
+  return trace_write("\n", 1);
+}
+
+int
+trace_putchar(int c)
+{
+  trace_write((const char*)&c, 1);
+  return c;
+}
+
+void
+trace_dump_args(int argc, char* argv[])
+{
+  trace_printf("main(argc=%d, argv=[", argc);
+  for (int i = 0; i < argc; ++i)
+    {
+      if (i != 0)
+        {
+          trace_printf(", ");
+        }
+      trace_printf("\"%s\"", argv[i]);
+    }
+  trace_printf("]);\n");
+}
+
+// ----------------------------------------------------------------------------
+
+#endif // TRACE
diff --git a/system/src/diag/trace_impl.c b/system/src/diag/trace_impl.c

new file mode 100644 (file)

index 0000000..e89ee28
--- /dev/null
+++ b/system/src/diag/trace_impl.c
@@ -0,0 +1,274 @@
+/*
+ * This file is part of the ??OS++ distribution.
+ *   (https://github.com/micro-os-plus)
+ * Copyright (c) 2014 Liviu Ionescu.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+// ----------------------------------------------------------------------------
+
+#if defined(TRACE)
+
+#include "cmsis_device.h"
+#include "diag/Trace.h"
+
+// ----------------------------------------------------------------------------
+
+// One of these definitions must be passed via the compiler command line
+// Note: small Cortex-M0/M0+ might implement a simplified debug interface.
+
+//#define OS_USE_TRACE_ITM
+//#define OS_USE_TRACE_SEMIHOSTING_DEBUG
+//#define OS_USE_TRACE_SEMIHOSTING_STDOUT
+
+#if !(defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__))
+#if defined(OS_USE_TRACE_ITM)
+#undef OS_USE_TRACE_ITM
+#warning "ITM unavailable"
+#endif // defined(OS_USE_TRACE_ITM)
+#endif // !(defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__))
+
+#if defined(OS_DEBUG_SEMIHOSTING_FAULTS)
+#if defined(OS_USE_TRACE_SEMIHOSTING_STDOUT) || defined(OS_USE_TRACE_SEMIHOSTING_DEBUG)
+#error "Cannot debug semihosting using semihosting trace; use OS_USE_TRACE_ITM"
+#endif
+#endif
+
+// ----------------------------------------------------------------------------
+
+// Forward definitions.
+
+#if defined(OS_USE_TRACE_ITM)
+static ssize_t
+_trace_write_itm (const char* buf, size_t nbyte);
+#endif
+
+#if defined(OS_USE_TRACE_SEMIHOSTING_STDOUT)
+static ssize_t
+_trace_write_semihosting_stdout(const char* buf, size_t nbyte);
+#endif
+
+#if defined(OS_USE_TRACE_SEMIHOSTING_DEBUG)
+static ssize_t
+_trace_write_semihosting_debug(const char* buf, size_t nbyte);
+#endif
+
+// ----------------------------------------------------------------------------
+
+void
+trace_initialize(void)
+{
+  // For regular ITM / semihosting, no inits required.
+}
+
+// ----------------------------------------------------------------------------
+
+// This function is called from _write() for fd==1 or fd==2 and from some
+// of the trace_* functions.
+
+ssize_t
+trace_write (const char* buf __attribute__((unused)),
+            size_t nbyte __attribute__((unused)))
+{
+#if defined(OS_USE_TRACE_ITM)
+  return _trace_write_itm (buf, nbyte);
+#elif defined(OS_USE_TRACE_SEMIHOSTING_STDOUT)
+  return _trace_write_semihosting_stdout(buf, nbyte);
+#elif defined(OS_USE_TRACE_SEMIHOSTING_DEBUG)
+  return _trace_write_semihosting_debug(buf, nbyte);
+#endif
+
+  return -1;
+}
+
+// ----------------------------------------------------------------------------
+
+#if defined(OS_USE_TRACE_ITM)
+
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+
+// ITM is the ARM standard mechanism, running over SWD/SWO on Cortex-M3/M4
+// devices, and is the recommended setting, if available.
+//
+// The JLink probe and the GDB server fully support SWD/SWO
+// and the JLink Debugging plug-in enables it by default.
+// The current OpenOCD does not include support to parse the SWO stream,
+// so this configuration will not work on OpenOCD (will not crash, but
+// nothing will be displayed in the output console).
+
+#if !defined(OS_INTEGER_TRACE_ITM_STIMULUS_PORT)
+#define OS_INTEGER_TRACE_ITM_STIMULUS_PORT     (0)
+#endif
+
+static ssize_t
+_trace_write_itm (const char* buf, size_t nbyte)
+{
+  for (size_t i = 0; i < nbyte; i++)
+    {
+      // Check if ITM or the stimulus port are not enabled
+      if (((ITM->TCR & ITM_TCR_ITMENA_Msk) == 0)
+         || ((ITM->TER & (1UL << OS_INTEGER_TRACE_ITM_STIMULUS_PORT)) == 0))
+       {
+         return (ssize_t)i; // return the number of sent characters (may be 0)
+       }
+
+      // Wait until STIMx is ready...
+      while (ITM->PORT[OS_INTEGER_TRACE_ITM_STIMULUS_PORT].u32 == 0)
+       ;
+      // then send data, one byte at a time
+      ITM->PORT[OS_INTEGER_TRACE_ITM_STIMULUS_PORT].u8 = (uint8_t) (*buf++);
+    }
+
+  return (ssize_t)nbyte; // all characters successfully sent
+}
+
+#endif // defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+
+#endif // OS_USE_TRACE_ITM
+
+// ----------------------------------------------------------------------------
+
+#if defined(OS_USE_TRACE_SEMIHOSTING_DEBUG) || defined(OS_USE_TRACE_SEMIHOSTING_STDOUT)
+
+#include "arm/semihosting.h"
+
+// Semihosting is the other output channel that can be used for the trace
+// messages. It comes in two flavours: STDOUT and DEBUG. The STDOUT channel
+// is the equivalent of the stdout in POSIX and in most cases it is forwarded
+// to the GDB server stdout stream. The debug channel is a separate
+// channel. STDOUT is buffered, so nothing is displayed until a \n;
+// DEBUG is not buffered, but can be slow.
+//
+// Choosing between semihosting stdout and debug depends on the capabilities
+// of your GDB server, and also on specific needs. It is recommended to test
+// DEBUG first, and if too slow, try STDOUT.
+//
+// The JLink GDB server fully support semihosting, and both configurations
+// are available; to activate it, use "monitor semihosting enable" or check
+// the corresponding button in the JLink Debugging plug-in.
+// In OpenOCD, support for semihosting can be enabled using
+// "monitor arm semihosting enable".
+//
+// Note: Applications built with semihosting output active normally cannot
+// be executed without the debugger connected and active, since they use
+// BKPT to communicate with the host. However, with a carefully written
+// HardFault_Handler, the semihosting BKPT calls can be processed, making
+// possible to run semihosting applications as standalone, without being
+// terminated with hardware faults.
+
+#endif // OS_USE_TRACE_SEMIHOSTING_DEBUG_*
+
+// ----------------------------------------------------------------------------
+
+#if defined(OS_USE_TRACE_SEMIHOSTING_STDOUT)
+
+static ssize_t
+_trace_write_semihosting_stdout (const char* buf, size_t nbyte)
+{
+  static int handle;
+  void* block[3];
+  int ret;
+
+  if (handle == 0)
+    {
+      // On the first call get the file handle from the host
+      block[0] = ":tt"; // special filename to be used for stdin/out/err
+      block[1] = (void*) 4; // mode "w"
+      // length of ":tt", except null terminator
+      block[2] = (void*) (sizeof(":tt") - 1);
+
+      ret = call_host (SEMIHOSTING_SYS_OPEN, (void*) block);
+      if (ret == -1)
+        return -1;
+
+      handle = ret;
+    }
+
+  block[0] = (void*) handle;
+  block[1] = (void*) buf;
+  block[2] = (void*) nbyte;
+  // send character array to host file/device
+  ret = call_host (SEMIHOSTING_SYS_WRITE, (void*) block);
+  // this call returns the number of bytes NOT written (0 if all ok)
+
+  // -1 is not a legal value, but SEGGER seems to return it
+  if (ret == -1)
+    return -1;
+
+  // The compliant way of returning errors
+  if (ret == (int) nbyte)
+    return -1;
+
+  // Return the number of bytes written
+  return (ssize_t) (nbyte) - (ssize_t) ret;
+}
+
+#endif // OS_USE_TRACE_SEMIHOSTING_STDOUT
+
+// ----------------------------------------------------------------------------
+
+#if defined(OS_USE_TRACE_SEMIHOSTING_DEBUG)
+
+#define OS_INTEGER_TRACE_TMP_ARRAY_SIZE  (16)
+
+static ssize_t
+_trace_write_semihosting_debug (const char* buf, size_t nbyte)
+{
+  // Since the single character debug channel is quite slow, try to
+  // optimise and send a null terminated string, if possible.
+  if (buf[nbyte] == '\0')
+    {
+      // send string
+      call_host (SEMIHOSTING_SYS_WRITE0, (void*) buf);
+    }
+  else
+    {
+      // If not, use a local buffer to speed things up
+      char tmp[OS_INTEGER_TRACE_TMP_ARRAY_SIZE];
+      size_t togo = nbyte;
+      while (togo > 0)
+        {
+          unsigned int n = ((togo < sizeof(tmp)) ? togo : sizeof(tmp));
+          unsigned int i = 0;
+          for (; i < n; ++i, ++buf)
+            {
+              tmp[i] = *buf;
+            }
+          tmp[i] = '\0';
+
+          call_host (SEMIHOSTING_SYS_WRITE0, (void*) tmp);
+
+          togo -= n;
+        }
+    }
+
+  // All bytes written
+  return (ssize_t) nbyte;
+}
+
+#endif // OS_USE_TRACE_SEMIHOSTING_DEBUG
+
+#endif // TRACE
+
+// ----------------------------------------------------------------------------
+
diff --git a/system/src/newlib/README.txt b/system/src/newlib/README.txt

new file mode 100644 (file)

index 0000000..26256d8
--- /dev/null
+++ b/system/src/newlib/README.txt
@@ -0,0 +1,16 @@
+
+The following files extend or replace some of the the newlib functionality:
+
+_startup.c: a customised startup sequence, written in C
+
+_exit.c: a customised exit() implementation
+
+_syscalls.c: local versions of the libnosys/librdimon code
+
+_sbrk.c: a custom _sbrk() to match the actual linker scripts
+
+assert.c: implementation for the asserion macros
+
+_cxx.cpp: local versions of some C++ support, to avoid references to 
+       large functions.
+
diff --git a/system/src/newlib/_cxx.cpp b/system/src/newlib/_cxx.cpp

new file mode 100644 (file)

index 0000000..b296411
--- /dev/null
+++ b/system/src/newlib/_cxx.cpp
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the ??OS++ distribution.
+ *   (https://github.com/micro-os-plus)
+ * Copyright (c) 2014 Liviu Ionescu.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+// ----------------------------------------------------------------------------
+
+// These functions are redefined locally, to avoid references to some
+// heavy implementations in the standard C++ library.
+
+// ----------------------------------------------------------------------------
+
+#include <cstdlib>
+#include <sys/types.h>
+#include "diag/Trace.h"
+
+// ----------------------------------------------------------------------------
+
+namespace __gnu_cxx
+{
+  void
+  __attribute__((noreturn))
+  __verbose_terminate_handler();
+
+  void
+  __verbose_terminate_handler()
+  {
+    trace_puts(__func__);
+    abort();
+  }
+}
+
+// ----------------------------------------------------------------------------
+
+extern "C"
+{
+  void
+  __attribute__((noreturn))
+  __cxa_pure_virtual();
+
+  void
+  __cxa_pure_virtual()
+  {
+    trace_puts(__func__);
+    abort();
+  }
+}
+
+// ----------------------------------------------------------------------------
+
diff --git a/system/src/newlib/_exit.c b/system/src/newlib/_exit.c

new file mode 100644 (file)

index 0000000..551384f
--- /dev/null
+++ b/system/src/newlib/_exit.c
@@ -0,0 +1,81 @@
+/*
+ * This file is part of the ??OS++ distribution.
+ *   (https://github.com/micro-os-plus)
+ * Copyright (c) 2014 Liviu Ionescu.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+// ----------------------------------------------------------------------------
+
+#include <stdlib.h>
+#include "diag/Trace.h"
+
+// ----------------------------------------------------------------------------
+
+#if !defined(DEBUG)
+extern void
+__attribute__((noreturn))
+__reset_hardware(void);
+#endif
+
+// ----------------------------------------------------------------------------
+
+// Forward declaration
+
+void
+_exit(int code);
+
+// ----------------------------------------------------------------------------
+
+// On Release, call the hardware reset procedure.
+// On Debug we just enter an infinite loop, to be used as landmark when halting
+// the debugger.
+//
+// It can be redefined in the application, if more functionality
+// is required.
+
+void
+__attribute__((weak))
+_exit(int code __attribute__((unused)))
+{
+#if !defined(DEBUG)
+  __reset_hardware();
+#endif
+
+  // TODO: write on trace
+  while (1)
+    ;
+}
+
+// ----------------------------------------------------------------------------
+
+void
+__attribute__((weak,noreturn))
+abort(void)
+{
+  trace_puts("abort(), exiting...");
+
+  _exit(1);
+}
+
+// ----------------------------------------------------------------------------
diff --git a/system/src/newlib/_sbrk.c b/system/src/newlib/_sbrk.c

new file mode 100644 (file)

index 0000000..7445213
--- /dev/null
+++ b/system/src/newlib/_sbrk.c
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the ??OS++ distribution.
+ *   (https://github.com/micro-os-plus)
+ * Copyright (c) 2014 Liviu Ionescu.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+// ----------------------------------------------------------------------------
+
+#include <sys/types.h>
+#include <errno.h>
+
+// ----------------------------------------------------------------------------
+
+caddr_t
+_sbrk(int incr);
+
+// ----------------------------------------------------------------------------
+
+// The definitions used here should be kept in sync with the
+// stack definitions in the linker script.
+
+caddr_t
+_sbrk(int incr)
+{
+  extern char _Heap_Begin; // Defined by the linker.
+  extern char _Heap_Limit; // Defined by the linker.
+
+  static char* current_heap_end;
+  char* current_block_address;
+
+  if (current_heap_end == 0)
+    {
+      current_heap_end = &_Heap_Begin;
+    }
+
+  current_block_address = current_heap_end;
+
+  // Need to align heap to word boundary, else will get
+  // hard faults on Cortex-M0. So we assume that heap starts on
+  // word boundary, hence make sure we always add a multiple of
+  // 4 to it.
+  incr = (incr + 3) & (~3); // align value to 4
+  if (current_heap_end + incr > &_Heap_Limit)
+    {
+      // Some of the libstdc++-v3 tests rely upon detecting
+      // out of memory errors, so do not abort here.
+#if 0
+      extern void abort (void);
+
+      _write (1, "_sbrk: Heap and stack collision\n", 32);
+
+      abort ();
+#else
+      // Heap has overflowed
+      errno = ENOMEM;
+      return (caddr_t) - 1;
+#endif
+    }
+
+  current_heap_end += incr;
+
+  return (caddr_t) current_block_address;
+}
+
+// ----------------------------------------------------------------------------
+
diff --git a/system/src/newlib/_startup.c b/system/src/newlib/_startup.c

new file mode 100644 (file)

index 0000000..14038e6
--- /dev/null
+++ b/system/src/newlib/_startup.c
@@ -0,0 +1,349 @@
+/*
+ * This file is part of the ??OS++ distribution.
+ *   (https://github.com/micro-os-plus)
+ * Copyright (c) 2014 Liviu Ionescu.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+// ----------------------------------------------------------------------------
+
+// This module contains the startup code for a portable embedded
+// C/C++ application, built with newlib.
+//
+// Control reaches here from the reset handler via jump or call.
+//
+// The actual steps performed by _start are:
+// - copy the initialised data region(s)
+// - clear the BSS region(s)
+// - initialise the system
+// - run the preinit/init array (for the C++ static constructors)
+// - initialise the arc/argv
+// - branch to main()
+// - run the fini array (for the C++ static destructors)
+// - call _exit(), directly or via exit()
+//
+// If OS_INCLUDE_STARTUP_INIT_MULTIPLE_RAM_SECTIONS is defined, the
+// code is capable of initialising multiple regions.
+//
+// The normal configuration is standalone, with all support
+// functions implemented locally.
+//
+// For this to be called, the project linker must be configured without
+// the startup sequence (-nostartfiles).
+
+// ----------------------------------------------------------------------------
+
+#include <stdint.h>
+#include <sys/types.h>
+
+// ----------------------------------------------------------------------------
+
+#if !defined(OS_INCLUDE_STARTUP_GUARD_CHECKS)
+#define OS_INCLUDE_STARTUP_GUARD_CHECKS (1)
+#endif
+
+// ----------------------------------------------------------------------------
+
+#if !defined(OS_INCLUDE_STARTUP_INIT_MULTIPLE_RAM_SECTIONS)
+// Begin address for the initialisation values of the .data section.
+// defined in linker script
+extern unsigned int _sidata;
+// Begin address for the .data section; defined in linker script
+extern unsigned int _sdata;
+// End address for the .data section; defined in linker script
+extern unsigned int _edata;
+
+// Begin address for the .bss section; defined in linker script
+extern unsigned int __bss_start__;
+// End address for the .bss section; defined in linker script
+extern unsigned int __bss_end__;
+#else
+// The following symbols are constructs generated by the linker, indicating
+// the location of various points in the "Memory regions initialisation arrays".
+// These arrays are created by the linker via the managed linker script
+// of each RW data mechanism. It contains the load address, execution address
+// and length section and the execution and length of each BSS (zero
+// initialised) section.
+extern unsigned int __data_regions_array_start;
+extern unsigned int __data_regions_array_end;
+extern unsigned int __bss_regions_array_start;
+extern unsigned int __bss_regions_array_end;
+#endif
+
+extern void
+__initialize_args (int*, char***);
+
+// main() is the entry point for newlib based applications.
+// By default, there are no arguments, but this can be customised
+// by redefining __initialize_args(), which is done when the
+// semihosting configurations are used.
+extern int
+main (int argc, char* argv[]);
+
+// The implementation for the exit routine; for embedded
+// applications, a system reset will be performed.
+extern void
+__attribute__((noreturn))
+_exit (int);
+
+// ----------------------------------------------------------------------------
+
+// Forward declarations
+
+void
+_start (void);
+
+void
+__initialize_data (unsigned int* from, unsigned int* region_begin,
+                  unsigned int* region_end);
+
+void
+__initialize_bss (unsigned int* region_begin, unsigned int* region_end);
+
+void
+__run_init_array (void);
+
+void
+__run_fini_array (void);
+
+void
+__initialize_hardware_early (void);
+
+void
+__initialize_hardware (void);
+
+// ----------------------------------------------------------------------------
+
+inline void
+__attribute__((always_inline))
+__initialize_data (unsigned int* from, unsigned int* region_begin,
+                  unsigned int* region_end)
+{
+  // Iterate and copy word by word.
+  // It is assumed that the pointers are word aligned.
+  unsigned int *p = region_begin;
+  while (p < region_end)
+    *p++ = *from++;
+}
+
+inline void
+__attribute__((always_inline))
+__initialize_bss (unsigned int* region_begin, unsigned int* region_end)
+{
+  // Iterate and clear word by word.
+  // It is assumed that the pointers are word aligned.
+  unsigned int *p = region_begin;
+  while (p < region_end)
+    *p++ = 0;
+}
+
+// These magic symbols are provided by the linker.
+extern void
+(*__preinit_array_start[]) (void) __attribute__((weak));
+extern void
+(*__preinit_array_end[]) (void) __attribute__((weak));
+extern void
+(*__init_array_start[]) (void) __attribute__((weak));
+extern void
+(*__init_array_end[]) (void) __attribute__((weak));
+extern void
+(*__fini_array_start[]) (void) __attribute__((weak));
+extern void
+(*__fini_array_end[]) (void) __attribute__((weak));
+
+// Iterate over all the preinit/init routines (mainly static constructors).
+inline void
+__attribute__((always_inline))
+__run_init_array (void)
+{
+  int count;
+  int i;
+
+  count = __preinit_array_end - __preinit_array_start;
+  for (i = 0; i < count; i++)
+    __preinit_array_start[i] ();
+
+  // If you need to run the code in the .init section, please use
+  // the startup files, since this requires the code in crti.o and crtn.o
+  // to add the function prologue/epilogue.
+  //_init(); // DO NOT ENABE THIS!
+
+  count = __init_array_end - __init_array_start;
+  for (i = 0; i < count; i++)
+    __init_array_start[i] ();
+}
+
+// Run all the cleanup routines (mainly static destructors).
+inline void
+__attribute__((always_inline))
+__run_fini_array (void)
+{
+  int count;
+  int i;
+
+  count = __fini_array_end - __fini_array_start;
+  for (i = count; i > 0; i--)
+    __fini_array_start[i - 1] ();
+
+  // If you need to run the code in the .fini section, please use
+  // the startup files, since this requires the code in crti.o and crtn.o
+  // to add the function prologue/epilogue.
+  //_fini(); // DO NOT ENABE THIS!
+}
+
+#if defined(DEBUG) && (OS_INCLUDE_STARTUP_GUARD_CHECKS)
+
+// These definitions are used to check if the routines used to
+// clear the BSS and to copy the initialised DATA perform correctly.
+
+#define BSS_GUARD_BAD_VALUE (0xCADEBABA)
+
+static uint32_t volatile __attribute__ ((section(".bss_begin")))
+__bss_begin_guard;
+static uint32_t volatile __attribute__ ((section(".bss_end")))
+__bss_end_guard;
+
+#define DATA_GUARD_BAD_VALUE (0xCADEBABA)
+#define DATA_BEGIN_GUARD_VALUE (0x12345678)
+#define DATA_END_GUARD_VALUE (0x98765432)
+
+static uint32_t volatile __attribute__ ((section(".data_begin")))
+__data_begin_guard = DATA_BEGIN_GUARD_VALUE;
+
+static uint32_t volatile __attribute__ ((section(".data_end")))
+__data_end_guard = DATA_END_GUARD_VALUE;
+
+#endif // defined(DEBUG) && (OS_INCLUDE_STARTUP_GUARD_CHECKS)
+
+// This is the place where Cortex-M core will go immediately after reset,
+// via a call or jump from the Reset_Handler.
+//
+// For the call to work, and for the call to __initialize_hardware_early()
+// to work, the reset stack must point to a valid internal RAM area.
+
+void __attribute__ ((section(".after_vectors"),noreturn,weak))
+_start (void)
+{
+
+  // Initialise hardware right after reset, to switch clock to higher
+  // frequency and have the rest of the initialisations run faster.
+  //
+  // Mandatory on platforms like Kinetis, which start with the watch dog
+  // enabled and require an early sequence to disable it.
+  //
+  // Also useful on platform with external RAM, that need to be
+  // initialised before filling the BSS section.
+
+  __initialize_hardware_early ();
+
+  // Use Old Style DATA and BSS section initialisation,
+  // that will manage a single BSS sections.
+
+#if defined(DEBUG) && (OS_INCLUDE_STARTUP_GUARD_CHECKS)
+  __data_begin_guard = DATA_GUARD_BAD_VALUE;
+  __data_end_guard = DATA_GUARD_BAD_VALUE;
+#endif
+
+#if !defined(OS_INCLUDE_STARTUP_INIT_MULTIPLE_RAM_SECTIONS)
+  // Copy the DATA segment from Flash to RAM (inlined).
+  __initialize_data(&_sidata, &_sdata, &_edata);
+#else
+
+  // Copy the data sections from flash to SRAM.
+  for (unsigned int* p = &__data_regions_array_start;
+      p < &__data_regions_array_end;)
+    {
+      unsigned int* from = (unsigned int *) (*p++);
+      unsigned int* region_begin = (unsigned int *) (*p++);
+      unsigned int* region_end = (unsigned int *) (*p++);
+
+      __initialize_data (from, region_begin, region_end);
+    }
+
+#endif
+
+#if defined(DEBUG) && (OS_INCLUDE_STARTUP_GUARD_CHECKS)
+  if ((__data_begin_guard != DATA_BEGIN_GUARD_VALUE)
+      || (__data_end_guard != DATA_END_GUARD_VALUE))
+    {
+      for (;;)
+       ;
+    }
+#endif
+
+#if defined(DEBUG) && (OS_INCLUDE_STARTUP_GUARD_CHECKS)
+  __bss_begin_guard = BSS_GUARD_BAD_VALUE;
+  __bss_end_guard = BSS_GUARD_BAD_VALUE;
+#endif
+
+#if !defined(OS_INCLUDE_STARTUP_INIT_MULTIPLE_RAM_SECTIONS)
+  // Zero fill the BSS section (inlined).
+  __initialize_bss(&__bss_start__, &__bss_end__);
+#else
+
+  // Zero fill all bss segments
+  for (unsigned int *p = &__bss_regions_array_start;
+      p < &__bss_regions_array_end;)
+    {
+      unsigned int* region_begin = (unsigned int*) (*p++);
+      unsigned int* region_end = (unsigned int*) (*p++);
+      __initialize_bss (region_begin, region_end);
+    }
+#endif
+
+#if defined(DEBUG) && (OS_INCLUDE_STARTUP_GUARD_CHECKS)
+  if ((__bss_begin_guard != 0) || (__bss_end_guard != 0))
+    {
+      for (;;)
+       ;
+    }
+#endif
+
+  // Hook to continue the initialisations. Usually compute and store the
+  // clock frequency in the global CMSIS variable, cleared above.
+  __initialize_hardware ();
+
+  // Get the argc/argv (useful in semihosting configurations).
+  int argc;
+  char** argv;
+  __initialize_args (&argc, &argv);
+
+  // Call the standard library initialisation (mandatory for C++ to
+  // execute the constructors for the static objects).
+  __run_init_array ();
+
+  // Call the main entry point, and save the exit code.
+  int code = main (argc, argv);
+
+  // Run the C++ static destructors.
+  __run_fini_array ();
+
+  _exit (code);
+
+  // Should never reach this, _exit() should have already
+  // performed a reset.
+  for (;;)
+    ;
+}
+
+// ----------------------------------------------------------------------------
diff --git a/system/src/newlib/_syscalls.c b/system/src/newlib/_syscalls.c

new file mode 100644 (file)

index 0000000..973fa79
--- /dev/null
+++ b/system/src/newlib/_syscalls.c
@@ -0,0 +1,1240 @@
+/*
+ * This file is part of the ??OS++ distribution.
+ *   (https://github.com/micro-os-plus)
+ * Copyright (c) 2014 Liviu Ionescu.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+// ----------------------------------------------------------------------------
+
+int errno;
+void *__dso_handle __attribute__ ((weak));
+
+// ----------------------------------------------------------------------------
+
+#if !defined(OS_USE_SEMIHOSTING)
+
+#include <_ansi.h>
+#include <_syslist.h>
+#include <errno.h>
+//#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/time.h>
+#include <sys/times.h>
+#include <limits.h>
+#include <signal.h>
+
+void
+__initialize_args(int* p_argc, char*** p_argv);
+
+// This is the standard default implementation for the routine to
+// process args. It returns a single empty arg.
+// For semihosting applications, this is redefined to get the real
+// args from the debugger. You can also use it if you decide to keep
+// some args in a non-volatile memory.
+
+void __attribute__((weak))
+__initialize_args(int* p_argc, char*** p_argv)
+{
+  // By the time we reach this, the data and bss should have been initialised.
+
+  // The strings pointed to by the argv array shall be modifiable by the
+  // program, and retain their last-stored values between program startup
+  // and program termination. (static, no const)
+  static char name[] = "";
+
+  // The string pointed to by argv[0] represents the program name;
+  // argv[0][0] shall be the null character if the program name is not
+  // available from the host environment. argv[argc] shall be a null pointer.
+  // (static, no const)
+  static char* argv[2] =
+    { name, NULL };
+
+  *p_argc = 1;
+  *p_argv = &argv[0];
+  return;
+}
+
+// These functions are defined here to avoid linker errors in freestanding
+// applications. They might be called in some error cases from library
+// code.
+//
+// If you detect other functions to be needed, just let us know
+// and we'll add them.
+
+__attribute__((weak)) int
+raise(int sig __attribute__((unused)))
+{
+  errno = ENOSYS;
+  return -1;
+}
+
+int
+kill(pid_t pid, int sig);
+
+__attribute__((weak)) int
+kill(pid_t pid __attribute__((unused)), int sig __attribute__((unused)))
+{
+  errno = ENOSYS;
+  return -1;
+}
+
+#endif // !defined(OS_USE_SEMIHOSTING)
+
+// ----------------------------------------------------------------------------
+
+// If you need the empty definitions, remove the -ffreestanding option.
+
+#if __STDC_HOSTED__ == 1
+
+char* __env[1] =
+  { 0 };
+char** environ = __env;
+
+#if !defined(OS_USE_SEMIHOSTING)
+
+// Forward declarations
+
+int
+_chown(const char* path, uid_t owner, gid_t group);
+
+int
+_close(int fildes);
+
+int
+_execve(char* name, char** argv, char** env);
+
+int
+_fork(void);
+
+int
+_fstat(int fildes, struct stat* st);
+
+int
+_getpid(void);
+
+int
+_gettimeofday(struct timeval* ptimeval, void* ptimezone);
+
+int
+_isatty(int file);
+
+int
+_kill(int pid, int sig);
+
+int
+_link(char* existing, char* _new);
+
+int
+_lseek(int file, int ptr, int dir);
+
+int
+_open(char* file, int flags, int mode);
+
+int
+_read(int file, char* ptr, int len);
+
+int
+_readlink(const char* path, char* buf, size_t bufsize);
+
+int
+_stat(const char* file, struct stat* st);
+
+int
+_symlink(const char* path1, const char* path2);
+
+clock_t
+_times(struct tms* buf);
+
+int
+_unlink(char* name);
+
+int
+_wait(int* status);
+
+int
+_write(int file, char* ptr, int len);
+
+// Definitions
+
+int __attribute__((weak))
+_chown(const char* path __attribute__((unused)),
+    uid_t owner __attribute__((unused)), gid_t group __attribute__((unused)))
+{
+  errno = ENOSYS;
+  return -1;
+}
+
+int __attribute__((weak))
+_close(int fildes __attribute__((unused)))
+{
+  errno = ENOSYS;
+  return -1;
+}
+
+int __attribute__((weak))
+_execve(char* name __attribute__((unused)), char** argv __attribute__((unused)),
+    char** env __attribute__((unused)))
+{
+  errno = ENOSYS;
+  return -1;
+}
+
+int __attribute__((weak))
+_fork(void)
+{
+  errno = ENOSYS;
+  return -1;
+}
+
+int __attribute__((weak))
+_fstat(int fildes __attribute__((unused)),
+    struct stat* st __attribute__((unused)))
+{
+  errno = ENOSYS;
+  return -1;
+}
+
+int __attribute__((weak))
+_getpid(void)
+{
+  errno = ENOSYS;
+  return -1;
+}
+
+int __attribute__((weak))
+_gettimeofday(struct timeval* ptimeval __attribute__((unused)),
+    void* ptimezone __attribute__((unused)))
+{
+  errno = ENOSYS;
+  return -1;
+}
+
+int __attribute__((weak))
+_isatty(int file __attribute__((unused)))
+{
+  errno = ENOSYS;
+  return 0;
+}
+
+int __attribute__((weak))
+_kill(int pid __attribute__((unused)), int sig __attribute__((unused)))
+{
+  errno = ENOSYS;
+  return -1;
+}
+
+int __attribute__((weak))
+_link(char* existing __attribute__((unused)),
+    char* _new __attribute__((unused)))
+{
+  errno = ENOSYS;
+  return -1;
+}
+
+int __attribute__((weak))
+_lseek(int file __attribute__((unused)), int ptr __attribute__((unused)),
+    int dir __attribute__((unused)))
+{
+  errno = ENOSYS;
+  return -1;
+}
+
+int __attribute__((weak))
+_open(char* file __attribute__((unused)), int flags __attribute__((unused)),
+    int mode __attribute__((unused)))
+{
+  errno = ENOSYS;
+  return -1;
+}
+
+int __attribute__((weak))
+_read(int file __attribute__((unused)), char* ptr __attribute__((unused)),
+    int len __attribute__((unused)))
+{
+  errno = ENOSYS;
+  return -1;
+}
+
+int __attribute__((weak))
+_readlink(const char* path __attribute__((unused)),
+    char* buf __attribute__((unused)), size_t bufsize __attribute__((unused)))
+{
+  errno = ENOSYS;
+  return -1;
+}
+
+int __attribute__((weak))
+_stat(const char* file __attribute__((unused)),
+    struct stat* st __attribute__((unused)))
+{
+  errno = ENOSYS;
+  return -1;
+}
+
+int __attribute__((weak))
+_symlink(const char* path1 __attribute__((unused)),
+    const char* path2 __attribute__((unused)))
+{
+  errno = ENOSYS;
+  return -1;
+}
+
+clock_t __attribute__((weak))
+_times(struct tms* buf __attribute__((unused)))
+{
+  errno = ENOSYS;
+  return ((clock_t) -1);
+}
+
+int __attribute__((weak))
+_unlink(char* name __attribute__((unused)))
+{
+  errno = ENOSYS;
+  return -1;
+}
+
+int __attribute__((weak))
+_wait(int* status __attribute__((unused)))
+{
+  errno = ENOSYS;
+  return -1;
+}
+
+int __attribute__((weak))
+_write(int file __attribute__((unused)), char* ptr __attribute__((unused)),
+    int len __attribute__((unused)))
+{
+  errno = ENOSYS;
+  return -1;
+}
+
+// ----------------------------------------------------------------------------
+
+#else // defined(OS_USE_SEMIHOSTING)
+
+// ----------------------------------------------------------------------------
+
+/* Support files for GNU libc.  Files in the system namespace go here.
+ Files in the C namespace (ie those that do not start with an
+ underscore) go in .c.  */
+
+#include <_ansi.h>
+#include <stdint.h>
+//#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/fcntl.h>
+#include <stdio.h>
+#include <string.h>
+#include <time.h>
+#include <sys/time.h>
+#include <sys/times.h>
+#include <errno.h>
+#include <reent.h>
+#include <unistd.h>
+#include <sys/wait.h>
+#include <ctype.h>
+#include <signal.h>
+
+#include "arm/semihosting.h"
+
+int
+_kill (int pid, int sig);
+
+void
+__attribute__((noreturn))
+_exit (int status);
+
+// Forward declarations.
+int
+_system (const char*);
+int
+_rename (const char*, const char*);
+int
+_isatty (int);
+clock_t
+_times (struct tms*);
+int
+_gettimeofday (struct timeval *, void*);
+int
+_unlink (const char*);
+int
+_link (void);
+
+int
+_stat (const char*, struct stat*);
+
+int
+_fstat (int, struct stat*);
+int
+_swistat (int fd, struct stat* st);
+int
+_getpid (int);
+int
+_close (int);
+clock_t
+_clock (void);
+int
+_swiclose (int);
+int
+_open (const char*, int, ...);
+int
+_swiopen (const char*, int);
+int
+_write (int, char*, int);
+int
+_swiwrite (int, char*, int);
+int
+_lseek (int, int, int);
+int
+_swilseek (int, int, int);
+int
+_read (int, char*, int);
+int
+_swiread (int, char*, int);
+
+void
+initialise_monitor_handles (void);
+
+void
+__initialize_args (int* p_argc, char*** p_argv);
+
+static int
+checkerror (int);
+static int
+error (int);
+static int
+get_errno (void);
+
+// ----------------------------------------------------------------------------
+
+#define ARGS_BUF_ARRAY_SIZE 80
+#define ARGV_BUF_ARRAY_SIZE 10
+
+typedef struct
+{
+  char* pCommandLine;
+  int size;
+} CommandLineBlock;
+
+void
+__initialize_args (int* p_argc, char*** p_argv)
+{
+
+  // Array of chars to receive the command line from the host
+  static char args_buf[ARGS_BUF_ARRAY_SIZE];
+
+  // Array of pointers to store the final argv pointers (pointing
+  // in the above array).
+  static char* argv_buf[ARGV_BUF_ARRAY_SIZE];
+
+  int argc = 0;
+  int isInArgument = 0;
+
+  CommandLineBlock cmdBlock;
+  cmdBlock.pCommandLine = args_buf;
+  cmdBlock.size = sizeof(args_buf) - 1;
+
+  int ret = call_host (SEMIHOSTING_SYS_GET_CMDLINE, &cmdBlock);
+  if (ret == 0)
+    {
+
+      // In case the host send more than we can chew, limit the
+      // string to our buffer.
+      args_buf[ARGS_BUF_ARRAY_SIZE - 1] = '\0';
+
+      // The command line is a null terminated string
+      char* p = cmdBlock.pCommandLine;
+
+      int delim = '\0';
+      int ch;
+
+      while ((ch = *p) != '\0')
+       {
+         if (isInArgument == 0)
+           {
+             if (!isblank(ch))
+               {
+                 if (argc
+                     >= (int) ((sizeof(argv_buf) / sizeof(argv_buf[0])) - 1))
+                   break;
+
+                 if (ch == '"' || ch == '\'')
+                   {
+                     // Remember the delimiter to search for the
+                     // corresponding terminator
+                     delim = ch;
+                     ++p;                        // skip the delimiter
+                     ch = *p;
+                   }
+                 // Remember the arg beginning address
+                 argv_buf[argc++] = p;
+                 isInArgument = 1;
+               }
+           }
+         else if (delim != '\0')
+           {
+             if ((ch == delim))
+               {
+                 delim = '\0';
+                 *p = '\0';
+                 isInArgument = 0;
+               }
+           }
+         else if (isblank(ch))
+           {
+             delim = '\0';
+             *p = '\0';
+             isInArgument = 0;
+           }
+         ++p;
+       }
+    }
+
+  if (argc == 0)
+    {
+      // No args found in string, return a single empty name.
+      args_buf[0] = '\0';
+      argv_buf[0] = &args_buf[0];
+      ++argc;
+    }
+
+  // Must end the array with a null pointer.
+  argv_buf[argc] = NULL;
+
+  *p_argc = argc;
+  *p_argv = &argv_buf[0];
+
+  // temporary here
+  initialise_monitor_handles ();
+
+  return;
+}
+
+// ----------------------------------------------------------------------------
+
+void
+_exit (int status)
+{
+  /* There is only one SWI for both _exit and _kill. For _exit, call
+   the SWI with the second argument set to -1, an invalid value for
+   signum, so that the SWI handler can distinguish the two calls.
+   Note: The RDI implementation of _kill throws away both its
+   arguments.  */
+  report_exception (
+      status == 0 ? ADP_Stopped_ApplicationExit : ADP_Stopped_RunTimeError);
+}
+
+// ----------------------------------------------------------------------------
+
+int __attribute__((weak))
+_kill (int pid __attribute__((unused)), int sig __attribute__((unused)))
+{
+  errno = ENOSYS;
+  return -1;
+}
+
+// ----------------------------------------------------------------------------
+
+/* Struct used to keep track of the file position, just so we
+ can implement fseek(fh,x,SEEK_CUR).  */
+struct fdent
+{
+  int handle;
+  int pos;
+};
+
+#define MAX_OPEN_FILES 20
+
+/* User file descriptors (fd) are integer indexes into
+ the openfiles[] array. Error checking is done by using
+ findslot().
+
+ This openfiles array is manipulated directly by only
+ these 5 functions:
+
+ findslot() - Translate entry.
+ newslot() - Find empty entry.
+ initilise_monitor_handles() - Initialize entries.
+ _swiopen() - Initialize entry.
+ _close() - Handle stdout == stderr case.
+
+ Every other function must use findslot().  */
+
+static struct fdent openfiles[MAX_OPEN_FILES];
+
+static struct fdent*
+findslot (int);
+static int
+newslot (void);
+
+/* Register name faking - works in collusion with the linker.  */
+register char* stack_ptr asm ("sp");
+
+/* following is copied from libc/stdio/local.h to check std streams */
+extern void __sinit(struct _reent*);
+#define CHECK_INIT(ptr) \
+  do                                            \
+    {                                           \
+      if ((ptr) && !(ptr)->__sdidinit)          \
+        __sinit (ptr);                          \
+    }                                           \
+  while (0)
+
+static int monitor_stdin;
+static int monitor_stdout;
+static int monitor_stderr;
+
+/* Return a pointer to the structure associated with
+ the user file descriptor fd. */
+static struct fdent*
+findslot (int fd)
+{
+  CHECK_INIT(_REENT);
+
+  /* User file descriptor is out of range. */
+  if ((unsigned int) fd >= MAX_OPEN_FILES)
+    {
+      return NULL;
+    }
+
+  /* User file descriptor is open? */
+  if (openfiles[fd].handle == -1)
+    {
+      return NULL;
+    }
+
+  /* Valid. */
+  return &openfiles[fd];
+}
+
+/* Return the next lowest numbered free file
+ structure, or -1 if we can't find one. */
+static int
+newslot (void)
+{
+  int i;
+
+  for (i = 0; i < MAX_OPEN_FILES; i++)
+    {
+      if (openfiles[i].handle == -1)
+        {
+          break;
+        }
+    }
+
+  if (i == MAX_OPEN_FILES)
+    {
+      return -1;
+    }
+
+  return i;
+}
+
+void
+initialise_monitor_handles (void)
+{
+  int i;
+
+  /* Open the standard file descriptors by opening the special
+   * teletype device, ":tt", read-only to obtain a descriptor for
+   * standard input and write-only to obtain a descriptor for standard
+   * output. Finally, open ":tt" in append mode to obtain a descriptor
+   * for standard error. Since this is a write mode, most kernels will
+   * probably return the same value as for standard output, but the
+   * kernel can differentiate the two using the mode flag and return a
+   * different descriptor for standard error.
+   */
+
+  int volatile block[3];
+
+  block[0] = (int) ":tt";
+  block[2] = 3; /* length of filename */
+  block[1] = 0; /* mode "r" */
+  monitor_stdin = call_host (SEMIHOSTING_SYS_OPEN, (void*) block);
+
+  block[0] = (int) ":tt";
+  block[2] = 3; /* length of filename */
+  block[1] = 4; /* mode "w" */
+  monitor_stdout = call_host (SEMIHOSTING_SYS_OPEN, (void*) block);
+
+  block[0] = (int) ":tt";
+  block[2] = 3; /* length of filename */
+  block[1] = 8; /* mode "a" */
+  monitor_stderr = call_host (SEMIHOSTING_SYS_OPEN, (void*) block);
+
+  /* If we failed to open stderr, redirect to stdout. */
+  if (monitor_stderr == -1)
+    {
+      monitor_stderr = monitor_stdout;
+    }
+
+  for (i = 0; i < MAX_OPEN_FILES; i++)
+    {
+      openfiles[i].handle = -1;
+    }
+
+  openfiles[0].handle = monitor_stdin;
+  openfiles[0].pos = 0;
+  openfiles[1].handle = monitor_stdout;
+  openfiles[1].pos = 0;
+  openfiles[2].handle = monitor_stderr;
+  openfiles[2].pos = 0;
+}
+
+static int
+get_errno (void)
+{
+  return call_host (SEMIHOSTING_SYS_ERRNO, NULL);
+}
+
+/* Set errno and return result. */
+static int
+error (int result)
+{
+  errno = get_errno ();
+  return result;
+}
+
+/* Check the return and set errno appropriately. */
+static int
+checkerror (int result)
+{
+  if (result == -1)
+    {
+      return error (-1);
+    }
+
+  return result;
+}
+
+/* fh, is a valid internal file handle.
+ ptr, is a null terminated string.
+ len, is the length in bytes to read.
+ Returns the number of bytes *not* written. */
+int
+_swiread (int fh, char* ptr, int len)
+{
+  int block[3];
+
+  block[0] = fh;
+  block[1] = (int) ptr;
+  block[2] = len;
+
+  return checkerror (call_host (SEMIHOSTING_SYS_READ, block));
+}
+
+/* fd, is a valid user file handle.
+ Translates the return of _swiread into
+ bytes read. */
+int
+_read (int fd, char* ptr, int len)
+{
+  int res;
+  struct fdent *pfd;
+
+  pfd = findslot (fd);
+  if (pfd == NULL)
+    {
+      errno = EBADF;
+      return -1;
+    }
+
+  res = _swiread (pfd->handle, ptr, len);
+
+  if (res == -1)
+    {
+      return res;
+    }
+
+  pfd->pos += len - res;
+
+  /* res == len is not an error,
+   at least if we want feof() to work.  */
+  return len - res;
+}
+
+/* fd, is a user file descriptor. */
+int
+_swilseek (int fd, int ptr, int dir)
+{
+  int res;
+  struct fdent *pfd;
+
+  /* Valid file descriptor? */
+  pfd = findslot (fd);
+  if (pfd == NULL)
+    {
+      errno = EBADF;
+      return -1;
+    }
+
+  /* Valid whence? */
+  if ((dir != SEEK_CUR) && (dir != SEEK_SET) && (dir != SEEK_END))
+    {
+      errno = EINVAL;
+      return -1;
+    }
+
+  /* Convert SEEK_CUR to SEEK_SET */
+  if (dir == SEEK_CUR)
+    {
+      ptr = pfd->pos + ptr;
+      /* The resulting file offset would be negative. */
+      if (ptr < 0)
+        {
+          errno = EINVAL;
+          if ((pfd->pos > 0) && (ptr > 0))
+            {
+              errno = EOVERFLOW;
+            }
+          return -1;
+        }
+      dir = SEEK_SET;
+    }
+
+  int block[2];
+  if (dir == SEEK_END)
+    {
+      block[0] = pfd->handle;
+      res = checkerror (call_host (SEMIHOSTING_SYS_FLEN, block));
+      if (res == -1)
+        {
+          return -1;
+        }
+      ptr += res;
+    }
+
+  /* This code only does absolute seeks.  */
+  block[0] = pfd->handle;
+  block[1] = ptr;
+  res = checkerror (call_host (SEMIHOSTING_SYS_SEEK, block));
+
+  /* At this point ptr is the current file position. */
+  if (res >= 0)
+    {
+      pfd->pos = ptr;
+      return ptr;
+    }
+  else
+    {
+      return -1;
+    }
+}
+
+int
+_lseek (int fd, int ptr, int dir)
+{
+  return _swilseek (fd, ptr, dir);
+}
+
+/* fh, is a valid internal file handle.
+ Returns the number of bytes *not* written. */
+int
+_swiwrite (int fh, char* ptr, int len)
+{
+  int block[3];
+
+  block[0] = fh;
+  block[1] = (int) ptr;
+  block[2] = len;
+
+  return checkerror (call_host (SEMIHOSTING_SYS_WRITE, block));
+}
+
+/* fd, is a user file descriptor. */
+int
+_write (int fd, char* ptr, int len)
+{
+  int res;
+  struct fdent *pfd;
+
+  pfd = findslot (fd);
+  if (pfd == NULL)
+    {
+      errno = EBADF;
+      return -1;
+    }
+
+  res = _swiwrite (pfd->handle, ptr, len);
+
+  /* Clearly an error. */
+  if (res < 0)
+    {
+      return -1;
+    }
+
+  pfd->pos += len - res;
+
+  /* We wrote 0 bytes?
+   Retrieve errno just in case. */
+  if ((len - res) == 0)
+    {
+      return error (0);
+    }
+
+  return (len - res);
+}
+
+int
+_swiopen (const char* path, int flags)
+{
+  int aflags = 0, fh;
+  uint32_t block[3];
+
+  int fd = newslot ();
+
+  if (fd == -1)
+    {
+      errno = EMFILE;
+      return -1;
+    }
+
+  /* It is an error to open a file that already exists. */
+  if ((flags & O_CREAT) && (flags & O_EXCL))
+    {
+      struct stat st;
+      int res;
+      res = _stat (path, &st);
+      if (res != -1)
+        {
+          errno = EEXIST;
+          return -1;
+        }
+    }
+
+  /* The flags are Unix-style, so we need to convert them. */
+#ifdef O_BINARY
+  if (flags & O_BINARY)
+    {
+      aflags |= 1;
+    }
+#endif
+
+  /* In O_RDONLY we expect aflags == 0. */
+
+  if (flags & O_RDWR)
+    {
+      aflags |= 2;
+    }
+
+  if ((flags & O_CREAT) || (flags & O_TRUNC) || (flags & O_WRONLY))
+    {
+      aflags |= 4;
+    }
+
+  if (flags & O_APPEND)
+    {
+      /* Can't ask for w AND a; means just 'a'.  */
+      aflags &= ~4;
+      aflags |= 8;
+    }
+
+  block[0] = (uint32_t) path;
+  block[2] = strlen (path);
+  block[1] = (uint32_t) aflags;
+
+  fh = call_host (SEMIHOSTING_SYS_OPEN, block);
+
+  /* Return a user file descriptor or an error. */
+  if (fh >= 0)
+    {
+      openfiles[fd].handle = fh;
+      openfiles[fd].pos = 0;
+      return fd;
+    }
+  else
+    {
+      return error (fh);
+    }
+}
+
+int
+_open (const char* path, int flags, ...)
+{
+  return _swiopen (path, flags);
+}
+
+/* fh, is a valid internal file handle. */
+int
+_swiclose (int fh)
+{
+  return checkerror (call_host (SEMIHOSTING_SYS_CLOSE, &fh));
+}
+
+/* fd, is a user file descriptor. */
+int
+_close (int fd)
+{
+  int res;
+  struct fdent *pfd;
+
+  pfd = findslot (fd);
+  if (pfd == NULL)
+    {
+      errno = EBADF;
+      return -1;
+    }
+
+  /* Handle stderr == stdout. */
+  if ((fd == 1 || fd == 2) && (openfiles[1].handle == openfiles[2].handle))
+    {
+      pfd->handle = -1;
+      return 0;
+    }
+
+  /* Attempt to close the handle. */
+  res = _swiclose (pfd->handle);
+
+  /* Reclaim handle? */
+  if (res == 0)
+    {
+      pfd->handle = -1;
+    }
+
+  return res;
+}
+
+int __attribute__((weak))
+_getpid (int n __attribute__ ((unused)))
+{
+  return 1;
+}
+
+int
+_swistat (int fd, struct stat* st)
+{
+  struct fdent *pfd;
+  int res;
+
+  pfd = findslot (fd);
+  if (pfd == NULL)
+    {
+      errno = EBADF;
+      return -1;
+    }
+
+  /* Always assume a character device,
+   with 1024 byte blocks. */
+  st->st_mode |= S_IFCHR;
+  st->st_blksize = 1024;
+  res = checkerror (call_host (SEMIHOSTING_SYS_FLEN, &pfd->handle));
+  if (res == -1)
+    {
+      return -1;
+    }
+
+  /* Return the file size. */
+  st->st_size = res;
+  return 0;
+}
+
+int __attribute__((weak))
+_fstat (int fd, struct stat* st)
+{
+  memset (st, 0, sizeof(*st));
+  return _swistat (fd, st);
+}
+
+int __attribute__((weak))
+_stat (const char*fname, struct stat *st)
+{
+  int fd, res;
+  memset (st, 0, sizeof(*st));
+  /* The best we can do is try to open the file readonly.
+   If it exists, then we can guess a few things about it. */
+  if ((fd = _open (fname, O_RDONLY)) == -1)
+    {
+      return -1;
+    }
+  st->st_mode |= S_IFREG | S_IREAD;
+  res = _swistat (fd, st);
+  /* Not interested in the error. */
+  _close (fd);
+  return res;
+}
+
+int __attribute__((weak))
+_link (void)
+{
+  errno = ENOSYS;
+  return -1;
+}
+
+int
+_unlink (const char* path)
+{
+  int res;
+  uint32_t block[2];
+  block[0] = (uint32_t) path;
+  block[1] = strlen (path);
+  res = call_host (SEMIHOSTING_SYS_REMOVE, block);
+
+  if (res == -1)
+    {
+      return error (res);
+    }
+  return 0;
+}
+
+int
+_gettimeofday (struct timeval* tp, void* tzvp)
+{
+  struct timezone* tzp = tzvp;
+  if (tp)
+    {
+      /* Ask the host for the seconds since the Unix epoch.  */
+      tp->tv_sec = call_host (SEMIHOSTING_SYS_TIME, NULL);
+      tp->tv_usec = 0;
+    }
+
+  /* Return fixed data for the timezone.  */
+  if (tzp)
+    {
+      tzp->tz_minuteswest = 0;
+      tzp->tz_dsttime = 0;
+    }
+
+  return 0;
+}
+
+/* Return a clock that ticks at 100Hz.  */
+clock_t
+_clock (void)
+{
+  clock_t timeval;
+
+  timeval = (clock_t) call_host (SEMIHOSTING_SYS_CLOCK, NULL);
+  return timeval;
+}
+
+/* Return a clock that ticks at 100Hz.  */
+clock_t
+_times (struct tms* tp)
+{
+  clock_t timeval = _clock ();
+
+  if (tp)
+    {
+      tp->tms_utime = timeval; /* user time */
+      tp->tms_stime = 0; /* system time */
+      tp->tms_cutime = 0; /* user time, children */
+      tp->tms_cstime = 0; /* system time, children */
+    }
+
+  return timeval;
+}
+
+int
+_isatty (int fd)
+{
+  struct fdent *pfd;
+  int tty;
+
+  pfd = findslot (fd);
+  if (pfd == NULL)
+    {
+      errno = EBADF;
+      return 0;
+    }
+
+  tty = call_host (SEMIHOSTING_SYS_ISTTY, &pfd->handle);
+
+  if (tty == 1)
+    {
+      return 1;
+    }
+
+  errno = get_errno ();
+  return 0;
+}
+
+int
+_system (const char* s)
+{
+  uint32_t block[2];
+  int e;
+
+  /* Hmmm.  The ARM debug interface specification doesn't say whether
+   SYS_SYSTEM does the right thing with a null argument, or assign any
+   meaning to its return value.  Try to do something reasonable....  */
+  if (!s)
+    {
+      return 1; /* maybe there is a shell available? we can hope. :-P */
+    }
+  block[0] = (uint32_t) s;
+  block[1] = strlen (s);
+  e = checkerror (call_host (SEMIHOSTING_SYS_SYSTEM, block));
+  if ((e >= 0) && (e < 256))
+    {
+      /* We have to convert e, an exit status to the encoded status of
+       the command.  To avoid hard coding the exit status, we simply
+       loop until we find the right position.  */
+      int exit_code;
+
+      for (exit_code = e; e && WEXITSTATUS (e) != exit_code; e <<= 1)
+        {
+          continue;
+        }
+    }
+  return e;
+}
+
+int
+_rename (const char* oldpath, const char* newpath)
+{
+  uint32_t block[4];
+  block[0] = (uint32_t) oldpath;
+  block[1] = strlen (oldpath);
+  block[2] = (uint32_t) newpath;
+  block[3] = strlen (newpath);
+  return checkerror (call_host (SEMIHOSTING_SYS_RENAME, block)) ? -1 : 0;
+}
+
+// ----------------------------------------------------------------------------
+// Required by Google Tests
+
+int
+mkdir (const char *path __attribute__((unused)),
+       mode_t mode __attribute__((unused)))
+{
+#if 0
+  // always return true
+  return 0;
+#else
+  errno = ENOSYS;
+  return -1;
+#endif
+}
+
+char *
+getcwd (char *buf, size_t size)
+{
+  // no cwd available via semihosting, so we use the temporary folder
+  strncpy (buf, "/tmp", size);
+  return buf;
+}
+
+#endif // defined OS_USE_SEMIHOSTING
+
+#endif // __STDC_HOSTED__ == 1
diff --git a/system/src/newlib/assert.c b/system/src/newlib/assert.c

new file mode 100644 (file)

index 0000000..5bffcdc
--- /dev/null
+++ b/system/src/newlib/assert.c
@@ -0,0 +1,77 @@
+/*
+ * This file is part of the ??OS++ distribution.
+ *   (https://github.com/micro-os-plus)
+ * Copyright (c) 2014 Liviu Ionescu.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+#include <stdint.h>
+
+#include "diag/Trace.h"
+
+// ----------------------------------------------------------------------------
+
+void
+__attribute__((noreturn))
+__assert_func (const char *file, int line, const char *func,
+               const char *failedexpr)
+{
+  trace_printf ("assertion \"%s\" failed: file \"%s\", line %d%s%s\n",
+                failedexpr, file, line, func ? ", function: " : "",
+                func ? func : "");
+  abort ();
+  /* NOTREACHED */
+}
+
+// ----------------------------------------------------------------------------
+
+// This is STM32 specific, but can be used on other platforms too.
+// If you need it, add the following to your application header:
+
+//#ifdef  USE_FULL_ASSERT
+//#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+//void assert_failed(uint8_t* file, uint32_t line);
+//#else
+//#define assert_param(expr) ((void)0)
+//#endif // USE_FULL_ASSERT
+
+#if defined(USE_FULL_ASSERT)
+
+void
+assert_failed (uint8_t* file, uint32_t line);
+
+// Called from the assert_param() macro, usually defined in the stm32f*_conf.h
+void
+__attribute__((noreturn, weak))
+assert_failed (uint8_t* file, uint32_t line)
+{
+  trace_printf ("assert_param() failed: file \"%s\", line %d\n", file, line);
+  abort ();
+  /* NOTREACHED */
+}
+
+#endif // defined(USE_FULL_ASSERT)
+
+// ----------------------------------------------------------------------------
diff --git a/system/src/stm32f0-stdperiph/.stm32f0xx_i2c.c.swo b/system/src/stm32f0-stdperiph/.stm32f0xx_i2c.c.swo

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diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_adc.c b/system/src/stm32f0-stdperiph/stm32f0xx_adc.c

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index 0000000..59b88fe
--- /dev/null
+++ b/system/src/stm32f0-stdperiph/stm32f0xx_adc.c
@@ -0,0 +1,1240 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_adc.c
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Analog to Digital Convertor (ADC) peripheral:
+  *           + Initialization and Configuration
+  *           + Power saving
+  *           + Analog Watchdog configuration
+  *           + Temperature Sensor, Vrefint (Internal Reference Voltage) and 
+  *             Vbat (Voltage battery) management 
+  *           + ADC Channels Configuration
+  *           + ADC Channels DMA Configuration
+  *           + Interrupts and flags management
+  *
+  *  @verbatim
+================================================================================
+                      ##### How to use this driver #####
+================================================================================
+    [..]
+    (#) Enable the ADC interface clock using 
+        RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE); 
+    (#) ADC pins configuration
+       (++) Enable the clock for the ADC GPIOs using the following function:
+            RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE);   
+       (++) Configure these ADC pins in analog mode using GPIO_Init();  
+    (#) Configure the ADC conversion resolution, data alignment, external
+        trigger and edge, scan direction and Enable/Disable the continuous mode
+        using the ADC_Init() function.
+    (#) Activate the ADC peripheral using ADC_Cmd() function.
+
+    *** ADC channels group configuration ***
+    ============================================
+    [..] 
+    (+) To configure the ADC channels features, use ADC_Init() and 
+        ADC_ChannelConfig() functions.
+    (+) To activate the continuous mode, use the ADC_ContinuousModeCmd()
+        function.
+    (+) To activate the Discontinuous mode, use the ADC_DiscModeCmd() functions. 
+    (+) To activate the overrun mode, use the ADC_OverrunModeCmd() functions.
+    (+) To activate the calibration mode, use the ADC_GetCalibrationFactor() functions.
+    (+) To read the ADC converted values, use the ADC_GetConversionValue()
+        function.
+
+    *** DMA for ADC channels features configuration ***
+    =============================================================
+    [..] 
+    (+) To enable the DMA mode for ADC channels group, use the ADC_DMACmd() function.
+    (+) To configure the DMA transfer request, use ADC_DMARequestModeConfig() function.
+
+  *  @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_adc.h"
+#include "stm32f0xx_rcc.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup ADC 
+  * @brief ADC driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ADC CFGR mask */
+#define CFGR1_CLEAR_MASK           ((uint32_t)0xFFFFD203)
+
+/* Calibration time out */
+#define CALIBRATION_TIMEOUT       ((uint32_t)0x0000F000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Functions
+  * @{
+  */
+
+/** @defgroup ADC_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim
+ ===============================================================================
+          ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to:
+        (+) Initialize and configure the ADC Prescaler
+        (+) ADC Conversion Resolution (12bit..6bit)
+        (+) ADC Continuous Conversion Mode (Continuous or Single conversion)
+        (+) External trigger Edge and source 
+        (+) Converted data alignment (left or right)
+        (+) The direction in which the channels will be scanned in the sequence
+        (+) Enable or disable the ADC peripheral
+   
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes ADC1 peripheral registers to their default reset values.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @retval None
+  */
+void ADC_DeInit(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+  if(ADCx == ADC1)
+  {
+    /* Enable ADC1 reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
+
+    /* Release ADC1 from reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
+  }
+}
+
+/**
+  * @brief  Initializes the ADCx peripheral according to the specified parameters
+  *         in the ADC_InitStruct.
+  * @note   This function is used to configure the global features of the ADC ( 
+  *         Resolution, Data Alignment, continuous mode activation, External 
+  *         trigger source and edge, Sequence Scan Direction).   
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains 
+  *         the configuration information for the specified ADC peripheral.
+  * @retval None
+  */
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution));
+  assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
+  assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge));
+  assert_param(IS_ADC_EXTERNAL_TRIG_CONV(ADC_InitStruct->ADC_ExternalTrigConv));
+  assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
+  assert_param(IS_ADC_SCAN_DIRECTION(ADC_InitStruct->ADC_ScanDirection)); 
+
+  /* Get the ADCx CFGR value */
+  tmpreg = ADCx->CFGR1;
+
+  /* Clear SCANDIR, RES[1:0], ALIGN, EXTSEL[2:0], EXTEN[1:0] and CONT bits */
+  tmpreg &= CFGR1_CLEAR_MASK;
+
+  /*---------------------------- ADCx CFGR Configuration ---------------------*/
+
+  /* Set RES[1:0] bits according to ADC_Resolution value */
+  /* Set CONT bit according to ADC_ContinuousConvMode value */
+  /* Set EXTEN[1:0] bits according to ADC_ExternalTrigConvEdge value */
+  /* Set EXTSEL[2:0] bits according to ADC_ExternalTrigConv value */
+  /* Set ALIGN bit according to ADC_DataAlign value */
+  /* Set SCANDIR bit according to ADC_ScanDirection value */
+ 
+  tmpreg  |= (uint32_t)(ADC_InitStruct->ADC_Resolution | ((uint32_t)(ADC_InitStruct->ADC_ContinuousConvMode) << 13) |
+             ADC_InitStruct->ADC_ExternalTrigConvEdge | ADC_InitStruct->ADC_ExternalTrigConv |
+             ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ScanDirection);
+
+  /* Write to ADCx CFGR */
+  ADCx->CFGR1 = tmpreg;
+}
+
+/**
+  * @brief  Fills each ADC_InitStruct member with its default value.
+  * @note   This function is used to initialize the global features of the ADC ( 
+  *         Resolution, Data Alignment, continuous mode activation, External 
+  *         trigger source and edge, Sequence Scan Direction).
+  * @param  ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will 
+  *         be initialized.
+  * @retval None
+  */
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
+{
+  /* Reset ADC init structure parameters values */
+  /* Initialize the ADC_Resolution member */
+  ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;
+
+   /* Initialize the ADC_ContinuousConvMode member */
+  ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
+
+  /* Initialize the ADC_ExternalTrigConvEdge member */
+  ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
+
+  /* Initialize the ADC_ExternalTrigConv member */
+  ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_TRGO;
+
+  /* Initialize the ADC_DataAlign member */
+  ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
+
+  /* Initialize the ADC_ScanDirection member */
+  ADC_InitStruct->ADC_ScanDirection = ADC_ScanDirection_Upward;
+}
+
+/**
+  * @brief  Enables or disables the specified ADC peripheral.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  NewState: new state of the ADCx peripheral. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set the ADEN bit to Enable the ADC peripheral */
+    ADCx->CR |= (uint32_t)ADC_CR_ADEN;
+  }
+  else
+  {
+    /* Set the ADDIS to Disable the ADC peripheral */
+    ADCx->CR |= (uint32_t)ADC_CR_ADDIS;
+  }
+}
+
+/**
+  * @brief  Configure the ADC to either be clocked by the asynchronous clock(which is
+  *         independent, the dedicated 14MHz clock) or the synchronous clock derived from
+  *         the APB clock of the ADC bus interface divided by 2 or 4
+  * @note   This function can be called only when ADC is disabled.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  ADC_ClockMode: This parameter can be :
+  *            @arg ADC_ClockMode_AsynClk: ADC clocked by the dedicated 14MHz clock
+  *            @arg ADC_ClockMode_SynClkDiv2: ADC clocked by PCLK/2
+  *            @arg ADC_ClockMode_SynClkDiv4: ADC clocked by PCLK/4  
+  * @retval None
+  */
+void ADC_ClockModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ClockMode)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CLOCKMODE(ADC_ClockMode));
+
+    /* Configure the ADC Clock mode according to ADC_ClockMode */
+    ADCx->CFGR2 = (uint32_t)ADC_ClockMode;
+
+}
+
+/**
+  * @brief  Enables or disables the jitter when the ADC is clocked by PCLK div2
+  *         or div4
+  * @note   This function is obsolete and maintained for legacy purpose only. ADC_ClockModeConfig()
+  *         function should be used instead.  
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  ADC_JitterOff: This parameter can be :
+  *            @arg ADC_JitterOff_PCLKDiv2: Remove jitter when ADC is clocked by PLCK divided by 2
+  *            @arg ADC_JitterOff_PCLKDiv4: Remove jitter when ADC is clocked by PLCK divided by 4
+  * @param  NewState: new state of the ADCx jitter. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_JitterCmd(ADC_TypeDef* ADCx, uint32_t ADC_JitterOff, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_JITTEROFF(ADC_JitterOff));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Disable Jitter */
+    ADCx->CFGR2 |= (uint32_t)ADC_JitterOff;
+  }
+  else
+  {
+    /* Enable Jitter */
+    ADCx->CFGR2 &= (uint32_t)(~ADC_JitterOff);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Group2 Power saving functions
+ *  @brief   Power saving functions 
+ *
+@verbatim
+ ===============================================================================
+          ##### Power saving functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to reduce power consumption.
+    [..] The two function must be combined to get the maximal benefits:
+         When the ADC frequency is higher than the CPU one, it is recommended to 
+         (#) Enable the Auto Delayed Conversion mode : 
+             ==> using ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+         (#) Enable the power off in Delay phases :
+             ==> using ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the ADC Power Off.
+  * @note   ADC power-on and power-off can be managed by hardware to cut the 
+  *         consumption when the ADC is not converting. 
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @note   The ADC can be powered down: 
+  *         - During the Auto delay phase:  The ADC is powered on again at the end
+  *           of the delay (until the previous data is read from the ADC data register). 
+  *         - During the ADC is waiting for a trigger event: The ADC is powered up
+  *           at the next trigger event (when the conversion is started).
+  * @param  NewState: new state of the ADCx power Off. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the ADC Automatic Power-Off */
+    ADCx->CFGR1 |= ADC_CFGR1_AUTOFF;
+  }
+  else
+  {
+    /* Disable the ADC Automatic Power-Off */
+    ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AUTOFF;
+  }
+}
+
+/**
+  * @brief  Enables or disables the Wait conversion mode.
+  * @note   When the CPU clock is not fast enough to manage the data rate, a 
+  *         Hardware delay can be introduced between ADC conversions to reduce 
+  *         this data rate. 
+  * @note   The Hardware delay is inserted after each conversions and until the
+  *         previous data is read from the ADC data register
+  * @note   This is a way to automatically adapt the speed of the ADC to the speed 
+  *         of the system which will read the data.
+  * @note   Any hardware triggers wich occur while a conversion is on going or 
+  *         while the automatic Delay is applied are ignored 
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  NewState: new state of the ADCx Auto-Delay.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the ADC Automatic Delayed conversion */
+    ADCx->CFGR1 |= ADC_CFGR1_WAIT;
+  }
+  else
+  {
+    /* Disable the ADC Automatic Delayed conversion */
+    ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_WAIT;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Group3 Analog Watchdog configuration functions
+ *  @brief   Analog Watchdog configuration functions 
+ *
+@verbatim
+ ===============================================================================
+                   ##### Analog Watchdog configuration functions #####
+ ===============================================================================  
+    [..] This section provides functions allowing to configure the Analog Watchdog
+         (AWD) feature in the ADC.
+    [..] A typical configuration Analog Watchdog is done following these steps :
+         (#) the ADC guarded channel(s) is (are) selected using the 
+             ADC_AnalogWatchdogSingleChannelConfig() function.
+         (#) The Analog watchdog lower and higher threshold are configured using the  
+             ADC_AnalogWatchdogThresholdsConfig() function.
+         (#) The Analog watchdog is enabled and configured to enable the check, on one
+             or more channels, using the  ADC_AnalogWatchdogCmd() function.
+         (#) Enable the analog watchdog on the selected channel using
+             ADC_AnalogWatchdogSingleChannelCmd() function
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the analog watchdog 
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  NewState: new state of the ADCx Analog Watchdog.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the ADC Analog Watchdog */
+    ADCx->CFGR1 |= ADC_CFGR1_AWDEN;
+  }
+  else
+  {
+    /* Disable the ADC Analog Watchdog */
+    ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AWDEN;
+  }
+}
+
+/**
+  * @brief  Configures the high and low thresholds of the analog watchdog. 
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  HighThreshold: the ADC analog watchdog High threshold value.
+  *          This parameter must be a 12bit value.
+  * @param  LowThreshold: the ADC analog watchdog Low threshold value.
+  *          This parameter must be a 12bit value.
+  * @retval None
+  */
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
+                                        uint16_t LowThreshold)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_THRESHOLD(HighThreshold));
+  assert_param(IS_ADC_THRESHOLD(LowThreshold));
+
+  /* Set the ADCx high and low threshold */
+  ADCx->TR = LowThreshold | ((uint32_t)HighThreshold << 16);
+
+}
+
+/**
+  * @brief  Configures the analog watchdog guarded single channel
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  ADC_AnalogWatchdog_Channel: the ADC channel to configure for the analog watchdog.
+  *          This parameter can be one of the following values:
+  *            @arg ADC_AnalogWatchdog_Channel_0: ADC Channel0 selected
+  *            @arg ADC_AnalogWatchdog_Channel_1: ADC Channel1 selected
+  *            @arg ADC_AnalogWatchdog_Channel_2: ADC Channel2 selected
+  *            @arg ADC_AnalogWatchdog_Channel_3: ADC Channel3 selected
+  *            @arg ADC_AnalogWatchdog_Channel_4: ADC Channel4 selected
+  *            @arg ADC_AnalogWatchdog_Channel_5: ADC Channel5 selected
+  *            @arg ADC_AnalogWatchdog_Channel_6: ADC Channel6 selected
+  *            @arg ADC_AnalogWatchdog_Channel_7: ADC Channel7 selected
+  *            @arg ADC_AnalogWatchdog_Channel_8: ADC Channel8 selected
+  *            @arg ADC_AnalogWatchdog_Channel_9: ADC Channel9 selected
+  *            @arg ADC_AnalogWatchdog_Channel_10: ADC Channel10 selected, not available for STM32F031 devices
+  *            @arg ADC_AnalogWatchdog_Channel_11: ADC Channel11 selected, not available for STM32F031 devices
+  *            @arg ADC_AnalogWatchdog_Channel_12: ADC Channel12 selected, not available for STM32F031 devices
+  *            @arg ADC_AnalogWatchdog_Channel_13: ADC Channel13 selected, not available for STM32F031 devices
+  *            @arg ADC_AnalogWatchdog_Channel_14: ADC Channel14 selected, not available for STM32F031 devices
+  *            @arg ADC_AnalogWatchdog_Channel_15: ADC Channel15 selected, not available for STM32F031 devices
+  *            @arg ADC_AnalogWatchdog_Channel_16: ADC Channel16 selected
+  *            @arg ADC_AnalogWatchdog_Channel_17: ADC Channel17 selected
+  *            @arg ADC_AnalogWatchdog_Channel_18: ADC Channel18 selected, not available for STM32F030 devices
+  * @note   The channel selected on the AWDCH must be also set into the CHSELR 
+  *         register 
+  * @retval None
+  */
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog_Channel)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_ANALOG_WATCHDOG_CHANNEL(ADC_AnalogWatchdog_Channel));
+
+  /* Get the old register value */
+  tmpreg = ADCx->CFGR1;
+
+  /* Clear the Analog watchdog channel select bits */
+  tmpreg &= ~ADC_CFGR1_AWDCH;
+
+  /* Set the Analog watchdog channel */
+  tmpreg |= ADC_AnalogWatchdog_Channel;
+
+  /* Store the new register value */
+  ADCx->CFGR1 = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the ADC Analog Watchdog Single Channel.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  NewState: new state of the ADCx ADC Analog Watchdog Single Channel.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_AnalogWatchdogSingleChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the ADC Analog Watchdog Single Channel */
+    ADCx->CFGR1 |= ADC_CFGR1_AWDSGL;
+  }
+  else
+  {
+    /* Disable the ADC Analog Watchdog Single Channel */
+    ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AWDSGL;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Group4 Temperature Sensor, Vrefint  and Vbat management functions
+ *  @brief   Temperature Sensor, Vrefint  and Vbat management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Temperature Sensor, Vrefint  and Vbat management function #####
+ ===============================================================================
+    [..] This section provides a function allowing to enable/disable the internal 
+         connections between the ADC and the Temperature Sensor, the Vrefint and
+         Vbat source.
+     
+    [..] A typical configuration to get the Temperature sensor, Vrefint and Vbat channels 
+         voltages is done following these steps :
+         (#) Enable the internal connection of Temperature sensor, Vrefint or Vbat sources 
+             with the ADC channels using ADC_TempSensorCmd(), ADC_VrefintCmd() or ADC_VbatCmd()
+             functions. 
+         (#) select the ADC_Channel_16(Temperature sensor), ADC_Channel_17(Vrefint)
+             or ADC_Channel_18(Voltage battery) using ADC_ChannelConfig() function 
+         (#) Get the voltage values, using ADC_GetConversionValue() function
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the temperature sensor channel.
+  * @param  NewState: new state of the temperature sensor input channel.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_TempSensorCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the temperature sensor channel*/
+    ADC->CCR |= (uint32_t)ADC_CCR_TSEN;
+  }
+  else
+  {
+    /* Disable the temperature sensor channel*/
+    ADC->CCR &= (uint32_t)(~ADC_CCR_TSEN);
+  }
+}
+
+/**
+  * @brief  Enables or disables the Vrefint channel.
+  * @param  NewState: new state of the Vref input channel.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_VrefintCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Vrefint channel*/
+    ADC->CCR |= (uint32_t)ADC_CCR_VREFEN;
+  }
+  else
+  {
+    /* Disable the Vrefint channel*/
+    ADC->CCR &= (uint32_t)(~ADC_CCR_VREFEN);
+  }
+}
+
+/**
+  * @brief  Enables or disables the Vbat channel. 
+  * @note   This feature is not applicable for STM32F030 devices. 
+  * @param  NewState: new state of the Vbat input channel.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_VbatCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Vbat channel*/
+    ADC->CCR |= (uint32_t)ADC_CCR_VBATEN;
+  }
+  else
+  {
+    /* Disable the Vbat channel*/
+    ADC->CCR &= (uint32_t)(~ADC_CCR_VBATEN);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Group5 Channels Configuration functions
+ *  @brief    Channels Configuration functions 
+ *
+@verbatim
+ ===============================================================================
+            ##### Channels Configuration functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to manage the ADC channels,
+         it is composed of 3 sub sections :
+         (#) Configuration and management functions for ADC channels: This subsection 
+             provides functions allowing to configure the ADC channels :    
+             (++) Select the ADC channels
+             (++) Activate ADC Calibration
+             (++) Activate the Overrun Mode.
+             (++) Activate the Discontinuous Mode 
+             (++) Activate the Continuous Mode.
+             (++) Configure the sampling time for each channel
+             (++) Select the conversion Trigger and Edge for ADC channels
+             (++) Select the scan direction.
+             -@@- Please Note that the following features for ADC channels are configurated
+                  using the ADC_Init() function : 
+                  (+@@) Activate the Continuous Mode (can be also activated by ADC_OverrunModeCmd().
+                  (+@@) Select the conversion Trigger and Edge for ADC channels
+                  (+@@) Select the scan direction.
+         (#) Control the ADC peripheral : This subsection permits to command the ADC:
+             (++) Stop or discard an on-going conversion (ADSTP command)
+             (++) Start the ADC conversion .
+         (#) Get the conversion data: This subsection provides an important function in 
+             the ADC peripheral since it returns the converted data of the current 
+             ADC channel. When the Conversion value is read, the EOC Flag is 
+             automatically cleared.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures for the selected ADC and its sampling time.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  ADC_Channel: the ADC channel to configure. 
+  *          This parameter can be any combination of the following values:
+  *            @arg ADC_Channel_0: ADC Channel0 selected
+  *            @arg ADC_Channel_1: ADC Channel1 selected
+  *            @arg ADC_Channel_2: ADC Channel2 selected
+  *            @arg ADC_Channel_3: ADC Channel3 selected
+  *            @arg ADC_Channel_4: ADC Channel4 selected
+  *            @arg ADC_Channel_5: ADC Channel5 selected
+  *            @arg ADC_Channel_6: ADC Channel6 selected
+  *            @arg ADC_Channel_7: ADC Channel7 selected
+  *            @arg ADC_Channel_8: ADC Channel8 selected
+  *            @arg ADC_Channel_9: ADC Channel9 selected
+  *            @arg ADC_Channel_10: ADC Channel10 selected, not available for STM32F031 devices
+  *            @arg ADC_Channel_11: ADC Channel11 selected, not available for STM32F031 devices
+  *            @arg ADC_Channel_12: ADC Channel12 selected, not available for STM32F031 devices
+  *            @arg ADC_Channel_13: ADC Channel13 selected, not available for STM32F031 devices
+  *            @arg ADC_Channel_14: ADC Channel14 selected, not available for STM32F031 devices
+  *            @arg ADC_Channel_15: ADC Channel15 selected, not available for STM32F031 devices
+  *            @arg ADC_Channel_16: ADC Channel16 selected
+  *            @arg ADC_Channel_17: ADC Channel17 selected
+  *            @arg ADC_Channel_18: ADC Channel18 selected, not available for STM32F030 devices
+  * @param  ADC_SampleTime: The sample time value to be set for the selected channel. 
+  *          This parameter can be one of the following values:
+  *            @arg ADC_SampleTime_1_5Cycles: Sample time equal to 1.5 cycles  
+  *            @arg ADC_SampleTime_7_5Cycles: Sample time equal to 7.5 cycles
+  *            @arg ADC_SampleTime_13_5Cycles: Sample time equal to 13.5 cycles
+  *            @arg ADC_SampleTime_28_5Cycles: Sample time equal to 28.5 cycles
+  *            @arg ADC_SampleTime_41_5Cycles: Sample time equal to 41.5 cycles
+  *            @arg ADC_SampleTime_55_5Cycles: Sample time equal to 55.5 cycles
+  *            @arg ADC_SampleTime_71_5Cycles: Sample time equal to 71.5 cycles
+  *            @arg ADC_SampleTime_239_5Cycles: Sample time equal to 239.5 cycles
+  * @retval None
+  */
+void ADC_ChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_Channel, uint32_t ADC_SampleTime)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CHANNEL(ADC_Channel));
+  assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+
+  /* Configure the ADC Channel */
+  ADCx->CHSELR |= (uint32_t)ADC_Channel;
+
+  /* Clear the Sampling time Selection bits */
+  tmpreg &= ~ADC_SMPR1_SMPR;
+
+  /* Set the ADC Sampling Time register */
+  tmpreg |= (uint32_t)ADC_SampleTime;
+
+  /* Configure the ADC Sample time register */
+  ADCx->SMPR = tmpreg ;
+}
+
+/**
+  * @brief  Enable the Continuous mode for the selected ADCx channels.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  NewState: new state of the Continuous mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   It is not possible to have both discontinuous mode and continuous mode
+  *         enabled. In this case (If DISCEN and CONT are Set), the ADC behaves 
+  *         as if continuous mode was disabled
+  * @retval None
+  */
+void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+  {
+    /* Enable the Continuous mode*/
+    ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_CONT;
+  }
+  else
+  {
+    /* Disable the Continuous mode */
+    ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_CONT);
+  }
+}
+
+/**
+  * @brief  Enable the discontinuous mode for the selected ADC channels.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  NewState: new state of the discontinuous mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   It is not possible to have both discontinuous mode and continuous mode
+  *         enabled. In this case (If DISCEN and CONT are Set), the ADC behaves 
+  *         as if continuous mode was disabled
+  * @retval None
+  */
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+  {
+    /* Enable the Discontinuous mode */
+    ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_DISCEN;
+  }
+  else
+  {
+    /* Disable the Discontinuous mode */
+    ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_DISCEN);
+  }
+}
+
+/**
+  * @brief  Enable the Overrun mode for the selected ADC channels.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  NewState: new state of the Overrun mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_OverrunModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+  {
+    /* Enable the Overrun mode */
+    ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_OVRMOD;
+  }
+  else
+  {
+    /* Disable the Overrun mode */
+    ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_OVRMOD);
+  }
+}
+
+/**
+  * @brief  Active the Calibration operation for the selected ADC.
+  * @note   The Calibration can be initiated only when ADC is still in the 
+  *         reset configuration (ADEN must be equal to 0).
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @retval ADC Calibration factor 
+  */
+uint32_t ADC_GetCalibrationFactor(ADC_TypeDef* ADCx)
+{
+  uint32_t tmpreg = 0, calibrationcounter = 0, calibrationstatus = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  
+  /* Set the ADC calibartion */
+  ADCx->CR |= (uint32_t)ADC_CR_ADCAL;
+  
+  /* Wait until no ADC calibration is completed */
+  do
+  {
+    calibrationstatus = ADCx->CR & ADC_CR_ADCAL;
+    calibrationcounter++;  
+  } while((calibrationcounter != CALIBRATION_TIMEOUT) && (calibrationstatus != 0x00));
+    
+  if((uint32_t)(ADCx->CR & ADC_CR_ADCAL) == RESET)
+  {
+    /*Get the calibration factor from the ADC data register */
+    tmpreg = ADCx->DR;
+  }
+  else
+  {
+    /* Error factor */
+    tmpreg = 0x00000000;
+  }
+  return tmpreg;
+}
+
+/**
+  * @brief  Stop the on going conversions for the selected ADC.
+  * @note   When ADSTP is set, any on going conversion is aborted, and the ADC 
+  *         data register is not updated with current conversion. 
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @retval None
+  */
+void ADC_StopOfConversion(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  
+  ADCx->CR |= (uint32_t)ADC_CR_ADSTP;
+}
+
+/**
+  * @brief  Start Conversion for the selected ADC channels.
+  * @note   In continuous mode, ADSTART is not cleared by hardware with the 
+  *         assertion of EOSEQ because the sequence is automatic relaunched
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @retval None
+  */
+void ADC_StartOfConversion(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  
+  ADCx->CR |= (uint32_t)ADC_CR_ADSTART;
+}
+
+/**
+  * @brief  Returns the last ADCx conversion result data for ADC channel.  
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @retval The Data conversion value.
+  */
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+  /* Return the selected ADC conversion value */
+  return (uint16_t) ADCx->DR;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Group6 DMA Configuration functions
+ *  @brief   Regular Channels DMA Configuration functions 
+ *
+@verbatim
+ ===============================================================================
+          ##### DMA Configuration functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to configure the DMA for ADC hannels.
+         Since converted channel values are stored into a unique data register, 
+         it is useful to use DMA for conversion of more than one channel. This 
+         avoids the loss of the data already stored in the ADC Data register. 
+         When the DMA mode is enabled (using the ADC_DMACmd() function), after each
+         conversion of a channel, a DMA request is generated.
+  
+    [..] Depending on the "DMA disable selection" configuration (using the 
+         ADC_DMARequestModeConfig() function), at the end of the last DMA 
+         transfer, two possibilities are allowed:
+         (+) No new DMA request is issued to the DMA controller (One Shot Mode) 
+         (+) Requests can continue to be generated (Circular Mode).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified ADC DMA request.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  NewState: new state of the selected ADC DMA transfer.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC DMA request */
+    ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_DMAEN;
+  }
+  else
+  {
+    /* Disable the selected ADC DMA request */
+    ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_DMAEN);
+  }
+}
+
+/**
+  * @brief  Enables or disables the ADC DMA request after last transfer (Single-ADC mode)
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  ADC_DMARequestMode: the ADC channel to configure. 
+  *          This parameter can be one of the following values:
+  *            @arg ADC_DMAMode_OneShot: DMA One Shot Mode 
+  *            @arg ADC_DMAMode_Circular: DMA Circular Mode  
+  *  @retval None
+  */
+void ADC_DMARequestModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMARequestMode)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+  ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_DMACFG;
+  ADCx->CFGR1 |= (uint32_t)ADC_DMARequestMode;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Group7 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions.
+ *
+@verbatim   
+ ===============================================================================
+            ##### Interrupts and flags management functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to configure the ADC Interrupts 
+         and get the status and clear flags and Interrupts pending bits.
+  
+    [..] The ADC provide 6 Interrupts sources and 11 Flags which can be divided into 
+         3 groups:
+
+  *** Flags for ADC status ***
+  ======================================================
+    [..]
+        (+)Flags :
+           (##) ADC_FLAG_ADRDY : This flag is set after the ADC has been enabled (bit ADEN=1)
+               and when the ADC reaches a state where it is ready to accept conversion requests
+           (##) ADC_FLAG_ADEN : This flag is set by software to enable the ADC.
+                The ADC will be effectively ready to operate once the ADRDY flag has been set.
+           (##) ADC_FLAG_ADDIS : This flag is cleared once the ADC is effectively
+                disabled.
+           (##) ADC_FLAG_ADSTART : This flag is cleared after the execution of
+                ADC_StopOfConversion() function, at the same time as the ADSTP bit is
+                cleared by hardware
+           (##) ADC_FLAG_ADSTP : This flag is cleared by hardware when the conversion
+                is effectively discarded and the ADC is ready to accept a new start conversion
+           (##) ADC_FLAG_ADCAL : This flag is set once the calibration is complete.
+
+        (+)Interrupts 
+           (##) ADC_IT_ADRDY : specifies the interrupt source for ADC ready event.
+
+  *** Flags and Interrupts for ADC channel conversion ***
+  =====================================================
+    [..]
+        (+)Flags :
+           (##) ADC_FLAG_EOC : This flag is set by hardware at the end of each conversion
+                of a channel when a new data result is available in the data register
+           (##) ADC_FLAG_EOSEQ : This bit is set by hardware at the end of the conversion
+                of a sequence of channels selected by ADC_ChannelConfig() function.
+           (##) ADC_FLAG_EOSMP : This bit is set by hardware at the end of the sampling phase.
+           (##) ADC_FLAG_OVR : This flag is set by hardware when an overrun occurs,
+                meaning that a new conversion has complete while the EOC flag was already set.
+
+        (+)Interrupts :
+           (##) ADC_IT_EOC : specifies the interrupt source for end of conversion event.
+           (##) ADC_IT_EOSEQ : specifies the interrupt source for end of sequence event.
+           (##) ADC_IT_EOSMP : specifies the interrupt source for end of sampling event.
+           (##) ADC_IT_OVR : specifies the interrupt source for Overrun detection 
+                event.
+
+  *** Flags and Interrupts for the Analog Watchdog ***
+  ================================================
+    [..]
+        (+)Flags :
+           (##) ADC_FLAG_AWD: This flag is set by hardware when the converted
+                voltage crosses the values programmed thrsholds
+
+        (+)Interrupts :
+           (##) ADC_IT_AWD : specifies the interrupt source for Analog watchdog 
+                event.
+  
+    [..] The user should identify which mode will be used in his application to 
+         manage the ADC controller events: Polling mode or Interrupt mode.
+  
+    [..] In the Polling Mode it is advised to use the following functions:
+         (+) ADC_GetFlagStatus() : to check if flags events occur.
+         (+) ADC_ClearFlag()     : to clear the flags events.
+  
+    [..] In the Interrupt Mode it is advised to use the following functions:
+         (+) ADC_ITConfig()       : to enable or disable the interrupt source.
+         (+) ADC_GetITStatus()    : to check if Interrupt occurs.
+         (+) ADC_ClearITPendingBit() : to clear the Interrupt pending Bit 
+             (corresponding Flag).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified ADC interrupts.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  ADC_IT: specifies the ADC interrupt sources to be enabled or disabled.
+  *          This parameter can be one of the following values:
+  *            @arg ADC_IT_ADRDY: ADC ready interrupt 
+  *            @arg ADC_IT_EOSMP: End of sampling interrupt
+  *            @arg ADC_IT_EOC: End of conversion interrupt 
+  *            @arg ADC_IT_EOSEQ: End of sequence of conversion interrupt
+  *            @arg ADC_IT_OVR: overrun interrupt
+  *            @arg ADC_IT_AWD: Analog watchdog interrupt
+  * @param  NewState: new state of the specified ADC interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_ADC_CONFIG_IT(ADC_IT)); 
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC interrupts */
+    ADCx->IER |= ADC_IT;
+  }
+  else
+  {
+    /* Disable the selected ADC interrupts */
+    ADCx->IER &= (~(uint32_t)ADC_IT);
+  }
+}
+
+/**
+  * @brief  Checks whether the specified ADC flag is set or not.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  ADC_FLAG: specifies the flag to check. 
+  *          This parameter can be one of the following values:
+  *            @arg ADC_FLAG_AWD: Analog watchdog flag
+  *            @arg ADC_FLAG_OVR: Overrun flag 
+  *            @arg ADC_FLAG_EOSEQ: End of Sequence flag
+  *            @arg ADC_FLAG_EOC: End of conversion flag
+  *            @arg ADC_FLAG_EOSMP: End of sampling flag
+  *            @arg ADC_FLAG_ADRDY: ADC Ready flag
+  *            @arg ADC_FLAG_ADEN: ADC enable flag 
+  *            @arg ADC_FLAG_ADDIS: ADC disable flag 
+  *            @arg ADC_FLAG_ADSTART: ADC start flag 
+  *            @arg ADC_FLAG_ADSTP: ADC stop flag
+  *            @arg ADC_FLAG_ADCAL: ADC Calibration flag
+  * @retval The new state of ADC_FLAG (SET or RESET).
+  */
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
+
+  if((uint32_t)(ADC_FLAG & 0x01000000))
+  {
+    tmpreg = ADCx->CR & 0xFEFFFFFF;
+  }
+  else
+  {
+    tmpreg = ADCx->ISR;
+  }
+  
+  /* Check the status of the specified ADC flag */
+  if ((tmpreg & ADC_FLAG) != (uint32_t)RESET)
+  {
+    /* ADC_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* ADC_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the ADC_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the ADCx's pending flags.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  ADC_FLAG: specifies the flag to clear. 
+  *          This parameter can be any combination of the following values:
+  *            @arg ADC_FLAG_AWD: Analog watchdog flag
+  *            @arg ADC_FLAG_EOC: End of conversion flag
+  *            @arg ADC_FLAG_ADRDY: ADC Ready flag
+  *            @arg ADC_FLAG_EOSMP: End of sampling flag
+  *            @arg ADC_FLAG_EOSEQ: End of Sequence flag
+  *            @arg ADC_FLAG_OVR: Overrun flag 
+  * @retval None
+  */
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
+
+  /* Clear the selected ADC flags */
+  ADCx->ISR = (uint32_t)ADC_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified ADC interrupt has occurred or not.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral
+  * @param  ADC_IT: specifies the ADC interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg ADC_IT_ADRDY: ADC ready interrupt 
+  *            @arg ADC_IT_EOSMP: End of sampling interrupt
+  *            @arg ADC_IT_EOC: End of conversion interrupt 
+  *            @arg ADC_IT_EOSEQ: End of sequence of conversion interrupt
+  *            @arg ADC_IT_OVR: overrun interrupt
+  *            @arg ADC_IT_AWD: Analog watchdog interrupt
+  * @retval The new state of ADC_IT (SET or RESET).
+  */
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_GET_IT(ADC_IT));
+
+  /* Get the ADC_IT enable bit status */
+  enablestatus = (uint32_t)(ADCx->IER & ADC_IT); 
+
+  /* Check the status of the specified ADC interrupt */
+  if (((uint32_t)(ADCx->ISR & ADC_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+  {
+    /* ADC_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* ADC_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the ADC_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the ADCx's interrupt pending bits.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  ADC_IT: specifies the ADC interrupt pending bit to clear.
+  *          This parameter can be one of the following values:
+  *            @arg ADC_IT_ADRDY: ADC ready interrupt
+  *            @arg ADC_IT_EOSMP: End of sampling interrupt
+  *            @arg ADC_IT_EOC: End of conversion interrupt
+  *            @arg ADC_IT_EOSEQ: End of sequence of conversion interrupt
+  *            @arg ADC_IT_OVR: overrun interrupt
+  *            @arg ADC_IT_AWD: Analog watchdog interrupt
+  * @retval None
+  */
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CLEAR_IT(ADC_IT));
+
+  /* Clear the selected ADC interrupt pending bits */
+  ADCx->ISR = (uint32_t)ADC_IT; 
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_can.c b/system/src/stm32f0-stdperiph/stm32f0xx_can.c

new file mode 100644 (file)

index 0000000..e401e74
--- /dev/null
+++ b/system/src/stm32f0-stdperiph/stm32f0xx_can.c
@@ -0,0 +1,1631 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_can.c
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Controller area network (CAN) peripheral and 
+  *          applicable only for STM32F072 devices :           
+  *           + Initialization and Configuration 
+  *           + CAN Frames Transmission 
+  *           + CAN Frames Reception    
+  *           + Operation modes switch  
+  *           + Error management          
+  *           + Interrupts and flags        
+  *         
+  @verbatim
+                               
+ ===============================================================================      
+                      ##### How to use this driver #####
+ ===============================================================================                
+    [..]
+    (#) Enable the CAN controller interface clock using 
+        RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN, ENABLE);      
+    (#) CAN pins configuration:
+        (++) Enable the clock for the CAN GPIOs using the following function:
+             RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE);   
+        (++) Connect the involved CAN pins to AF0 using the following function 
+             GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx); 
+        (++) Configure these CAN pins in alternate function mode by calling
+             the function  GPIO_Init();
+    (#) Initialise and configure the CAN using CAN_Init() and 
+        CAN_FilterInit() functions.   
+    (#) Transmit the desired CAN frame using CAN_Transmit() function.
+    (#) Check the transmission of a CAN frame using CAN_TransmitStatus() function.
+    (#) Cancel the transmission of a CAN frame using CAN_CancelTransmit() function.  
+    (#) Receive a CAN frame using CAN_Recieve() function.
+    (#) Release the receive FIFOs using CAN_FIFORelease() function.
+    (#) Return the number of pending received frames using CAN_MessagePending() function.            
+    (#) To control CAN events you can use one of the following two methods:
+        (++) Check on CAN flags using the CAN_GetFlagStatus() function.  
+        (++) Use CAN interrupts through the function CAN_ITConfig() at initialization 
+             phase and CAN_GetITStatus() function into interrupt routines to check 
+             if the event has occurred or not.
+             After checking on a flag you should clear it using CAN_ClearFlag()
+             function. And after checking on an interrupt event you should clear it 
+             using CAN_ClearITPendingBit() function.            
+                 
+  @endverbatim
+  *       
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_can.h"
+#include "stm32f0xx_rcc.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CAN 
+  * @brief CAN driver modules
+  * @{
+  */ 
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* CAN Master Control Register bits */
+#define MCR_DBF           ((uint32_t)0x00010000) /* software master reset */
+
+/* CAN Mailbox Transmit Request */
+#define TMIDxR_TXRQ       ((uint32_t)0x00000001) /* Transmit mailbox request */
+
+/* CAN Filter Master Register bits */
+#define FMR_FINIT         ((uint32_t)0x00000001) /* Filter init mode */
+
+/* Time out for INAK bit */
+#define INAK_TIMEOUT      ((uint32_t)0x00FFFFFF)
+/* Time out for SLAK bit */
+#define SLAK_TIMEOUT      ((uint32_t)0x00FFFFFF)
+
+/* Flags in TSR register */
+#define CAN_FLAGS_TSR     ((uint32_t)0x08000000) 
+/* Flags in RF1R register */
+#define CAN_FLAGS_RF1R    ((uint32_t)0x04000000) 
+/* Flags in RF0R register */
+#define CAN_FLAGS_RF0R    ((uint32_t)0x02000000) 
+/* Flags in MSR register */
+#define CAN_FLAGS_MSR     ((uint32_t)0x01000000) 
+/* Flags in ESR register */
+#define CAN_FLAGS_ESR     ((uint32_t)0x00F00000) 
+
+/* Mailboxes definition */
+#define CAN_TXMAILBOX_0   ((uint8_t)0x00)
+#define CAN_TXMAILBOX_1   ((uint8_t)0x01)
+#define CAN_TXMAILBOX_2   ((uint8_t)0x02) 
+
+#define CAN_MODE_MASK     ((uint32_t) 0x00000003)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);
+
+/** @defgroup CAN_Private_Functions
+  * @{
+  */
+
+/** @defgroup CAN_Group1 Initialization and Configuration functions
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+              ##### Initialization and Configuration functions #####
+ ===============================================================================  
+    [..] This section provides functions allowing to: 
+         (+) Initialize the CAN peripherals : Prescaler, operating mode, the maximum 
+             number of time quanta to perform resynchronization, the number of time 
+             quanta in Bit Segment 1 and 2 and many other modes. 
+         (+) Configure the CAN reception filter.                                      
+         (+) Select the start bank filter for slave CAN.
+         (+) Enable or disable the Debug Freeze mode for CAN.
+         (+) Enable or disable the CAN Time Trigger Operation communication mode.
+   
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Deinitializes the CAN peripheral registers to their default reset values.
+  * @param  CANx: where x can be 1 to select the CAN peripheral.
+  * @retval None.
+  */
+void CAN_DeInit(CAN_TypeDef* CANx)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+ 
+  /* Enable CAN reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, ENABLE);
+  /* Release CAN from reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, DISABLE);
+}
+
+/**
+  * @brief  Initializes the CAN peripheral according to the specified
+  *         parameters in the CAN_InitStruct.
+  * @param  CANx: where x can be 1 to select the CAN peripheral.
+  * @param  CAN_InitStruct: pointer to a CAN_InitTypeDef structure that contains
+  *         the configuration information for the CAN peripheral.
+  * @retval Constant indicates initialization succeed which will be 
+  *         CAN_InitStatus_Failed or CAN_InitStatus_Success.
+  */
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)
+{
+  uint8_t InitStatus = CAN_InitStatus_Failed;
+  uint32_t wait_ack = 0x00000000;
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));
+  assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));
+  assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));
+  assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));
+  assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
+  assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
+
+  /* Exit from sleep mode */
+  CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
+
+  /* Request initialisation */
+  CANx->MCR |= CAN_MCR_INRQ ;
+
+  /* Wait the acknowledge */
+  while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
+  {
+    wait_ack++;
+  }
+
+  /* Check acknowledge */
+  if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+  {
+    InitStatus = CAN_InitStatus_Failed;
+  }
+  else 
+  {
+    /* Set the time triggered communication mode */
+    if (CAN_InitStruct->CAN_TTCM == ENABLE)
+    {
+      CANx->MCR |= CAN_MCR_TTCM;
+    }
+    else
+    {
+      CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM;
+    }
+
+    /* Set the automatic bus-off management */
+    if (CAN_InitStruct->CAN_ABOM == ENABLE)
+    {
+      CANx->MCR |= CAN_MCR_ABOM;
+    }
+    else
+    {
+      CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM;
+    }
+
+    /* Set the automatic wake-up mode */
+    if (CAN_InitStruct->CAN_AWUM == ENABLE)
+    {
+      CANx->MCR |= CAN_MCR_AWUM;
+    }
+    else
+    {
+      CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM;
+    }
+
+    /* Set the no automatic retransmission */
+    if (CAN_InitStruct->CAN_NART == ENABLE)
+    {
+      CANx->MCR |= CAN_MCR_NART;
+    }
+    else
+    {
+      CANx->MCR &= ~(uint32_t)CAN_MCR_NART;
+    }
+
+    /* Set the receive FIFO locked mode */
+    if (CAN_InitStruct->CAN_RFLM == ENABLE)
+    {
+      CANx->MCR |= CAN_MCR_RFLM;
+    }
+    else
+    {
+      CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM;
+    }
+
+    /* Set the transmit FIFO priority */
+    if (CAN_InitStruct->CAN_TXFP == ENABLE)
+    {
+      CANx->MCR |= CAN_MCR_TXFP;
+    }
+    else
+    {
+      CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP;
+    }
+
+    /* Set the bit timing register */
+    CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \
+                ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \
+                ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \
+                ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \
+               ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);
+
+    /* Request leave initialisation */
+    CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ;
+
+   /* Wait the acknowledge */
+   wait_ack = 0;
+
+   while (((CANx->MSR & CAN_MSR_INAK) == (uint16_t)CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
+   {
+     wait_ack++;
+   }
+
+    /* ...and check acknowledged */
+    if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
+    {
+      InitStatus = CAN_InitStatus_Failed;
+    }
+    else
+    {
+      InitStatus = CAN_InitStatus_Success ;
+    }
+  }
+
+  /* At this step, return the status of initialization */
+  return InitStatus;
+}
+
+/**
+  * @brief  Configures the CAN reception filter according to the specified
+  *         parameters in the CAN_FilterInitStruct.
+  * @param  CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef structure that
+  *         contains the configuration information.
+  * @retval None
+  */
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
+{
+  uint32_t filter_number_bit_pos = 0;
+  /* Check the parameters */
+  assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));
+  assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));
+  assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));
+  assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
+
+  filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber;
+
+  /* Initialisation mode for the filter */
+  CAN->FMR |= FMR_FINIT;
+
+  /* Filter Deactivation */
+  CAN->FA1R &= ~(uint32_t)filter_number_bit_pos;
+
+  /* Filter Scale */
+  if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
+  {
+    /* 16-bit scale for the filter */
+    CAN->FS1R &= ~(uint32_t)filter_number_bit_pos;
+
+    /* First 16-bit identifier and First 16-bit mask */
+    /* Or First 16-bit identifier and Second 16-bit identifier */
+    CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = 
+       ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
+        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
+
+    /* Second 16-bit identifier and Second 16-bit mask */
+    /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+    CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = 
+       ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
+        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);
+  }
+
+  if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
+  {
+    /* 32-bit scale for the filter */
+    CAN->FS1R |= filter_number_bit_pos;
+    /* 32-bit identifier or First 32-bit identifier */
+    CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = 
+       ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
+        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
+    /* 32-bit mask or Second 32-bit identifier */
+    CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = 
+       ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
+        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);
+  }
+
+  /* Filter Mode */
+  if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
+  {
+    /*Id/Mask mode for the filter*/
+    CAN->FM1R &= ~(uint32_t)filter_number_bit_pos;
+  }
+  else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
+  {
+    /*Identifier list mode for the filter*/
+    CAN->FM1R |= (uint32_t)filter_number_bit_pos;
+  }
+
+  /* Filter FIFO assignment */
+  if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0)
+  {
+    /* FIFO 0 assignation for the filter */
+    CAN->FFA1R &= ~(uint32_t)filter_number_bit_pos;
+  }
+
+  if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1)
+  {
+    /* FIFO 1 assignation for the filter */
+    CAN->FFA1R |= (uint32_t)filter_number_bit_pos;
+  }
+  
+  /* Filter activation */
+  if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
+  {
+    CAN->FA1R |= filter_number_bit_pos;
+  }
+
+  /* Leave the initialisation mode for the filter */
+  CAN->FMR &= ~FMR_FINIT;
+}
+
+/**
+  * @brief  Fills each CAN_InitStruct member with its default value.
+  * @param  CAN_InitStruct: pointer to a CAN_InitTypeDef structure which ill be initialized.
+  * @retval None
+  */
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
+{
+  /* Reset CAN init structure parameters values */
+  
+  /* Initialize the time triggered communication mode */
+  CAN_InitStruct->CAN_TTCM = DISABLE;
+  
+  /* Initialize the automatic bus-off management */
+  CAN_InitStruct->CAN_ABOM = DISABLE;
+  
+  /* Initialize the automatic wake-up mode */
+  CAN_InitStruct->CAN_AWUM = DISABLE;
+  
+  /* Initialize the no automatic retransmission */
+  CAN_InitStruct->CAN_NART = DISABLE;
+  
+  /* Initialize the receive FIFO locked mode */
+  CAN_InitStruct->CAN_RFLM = DISABLE;
+  
+  /* Initialize the transmit FIFO priority */
+  CAN_InitStruct->CAN_TXFP = DISABLE;
+  
+  /* Initialize the CAN_Mode member */
+  CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
+  
+  /* Initialize the CAN_SJW member */
+  CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;
+  
+  /* Initialize the CAN_BS1 member */
+  CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
+  
+  /* Initialize the CAN_BS2 member */
+  CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
+  
+  /* Initialize the CAN_Prescaler member */
+  CAN_InitStruct->CAN_Prescaler = 1;
+}
+
+/**
+  * @brief  Select the start bank filter for slave CAN.
+  * @param  CAN_BankNumber: Select the start slave bank filter from 1..27.
+  * @retval None
+  */
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber) 
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));
+  
+  /* Enter Initialisation mode for the filter */
+  CAN->FMR |= FMR_FINIT;
+  
+  /* Select the start slave bank */
+  CAN->FMR &= (uint32_t)0xFFFFC0F1 ;
+  CAN->FMR |= (uint32_t)(CAN_BankNumber)<<8;
+  
+  /* Leave Initialisation mode for the filter */
+  CAN->FMR &= ~FMR_FINIT;
+}
+
+/**
+  * @brief  Enables or disables the DBG Freeze for CAN.
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  NewState: new state of the CAN peripheral. 
+  *          This parameter can be: ENABLE (CAN reception/transmission is frozen
+  *          during debug. Reception FIFOs can still be accessed/controlled normally) 
+  *          or DISABLE (CAN is working during debug).
+  * @retval None
+  */
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable Debug Freeze  */
+    CANx->MCR |= MCR_DBF;
+  }
+  else
+  {
+    /* Disable Debug Freeze */
+    CANx->MCR &= ~MCR_DBF;
+  }
+}
+
+/**
+  * @brief  Enables or disables the CAN Time TriggerOperation communication mode.
+  * @note   DLC must be programmed as 8 in order Time Stamp (2 bytes) to be 
+  *         sent over the CAN bus.  
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  NewState: Mode new state. This parameter can be: ENABLE or DISABLE.
+  *         When enabled, Time stamp (TIME[15:0]) value is  sent in the last two
+  *         data bytes of the 8-byte message: TIME[7:0] in data byte 6 and TIME[15:8] 
+  *         in data byte 7. 
+  * @retval None
+  */
+void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the TTCM mode */
+    CANx->MCR |= CAN_MCR_TTCM;
+
+    /* Set TGT bits */
+    CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT);
+    CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT);
+    CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT);
+  }
+  else
+  {
+    /* Disable the TTCM mode */
+    CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM);
+
+    /* Reset TGT bits */
+    CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT);
+    CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT);
+    CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT);
+  }
+}
+/**
+  * @}
+  */
+
+
+/** @defgroup CAN_Group2 CAN Frames Transmission functions
+ *  @brief    CAN Frames Transmission functions 
+ *
+@verbatim    
+ ===============================================================================
+                ##### CAN Frames Transmission functions #####
+ ===============================================================================  
+    [..] This section provides functions allowing to 
+         (+) Initiate and transmit a CAN frame message (if there is an empty mailbox).
+         (+) Check the transmission status of a CAN Frame.
+         (+) Cancel a transmit request.
+   
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initiates and transmits a CAN frame message.
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data.
+  * @retval The number of the mailbox that is used for transmission or
+  *         CAN_TxStatus_NoMailBox if there is no empty mailbox.
+  */
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)
+{
+  uint8_t transmit_mailbox = 0;
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_IDTYPE(TxMessage->IDE));
+  assert_param(IS_CAN_RTR(TxMessage->RTR));
+  assert_param(IS_CAN_DLC(TxMessage->DLC));
+
+  /* Select one empty transmit mailbox */
+  if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
+  {
+    transmit_mailbox = 0;
+  }
+  else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
+  {
+    transmit_mailbox = 1;
+  }
+  else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
+  {
+    transmit_mailbox = 2;
+  }
+  else
+  {
+    transmit_mailbox = CAN_TxStatus_NoMailBox;
+  }
+
+  if (transmit_mailbox != CAN_TxStatus_NoMailBox)
+  {
+    /* Set up the Id */
+    CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ;
+    if (TxMessage->IDE == CAN_Id_Standard)
+    {
+      assert_param(IS_CAN_STDID(TxMessage->StdId));  
+      CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \
+                                                  TxMessage->RTR);
+    }
+    else
+    {
+      assert_param(IS_CAN_EXTID(TxMessage->ExtId));
+      CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \
+                                                  TxMessage->IDE | \
+                                                  TxMessage->RTR);
+    }
+    
+    /* Set up the DLC */
+    TxMessage->DLC &= (uint8_t)0x0000000F;
+    CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;
+    CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC;
+
+    /* Set up the data field */
+    CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | 
+                                             ((uint32_t)TxMessage->Data[2] << 16) |
+                                             ((uint32_t)TxMessage->Data[1] << 8) | 
+                                             ((uint32_t)TxMessage->Data[0]));
+    CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | 
+                                             ((uint32_t)TxMessage->Data[6] << 16) |
+                                             ((uint32_t)TxMessage->Data[5] << 8) |
+                                             ((uint32_t)TxMessage->Data[4]));
+    /* Request transmission */
+    CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ;
+  }
+  return transmit_mailbox;
+}
+
+/**
+  * @brief  Checks the transmission status of a CAN Frame.
+  * @param  CANx: where x can be 1 to select the CAN peripheral.
+  * @param  TransmitMailbox: the number of the mailbox that is used for transmission.
+  * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, 
+  *         CAN_TxStatus_Failed in an other case.
+  */
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)
+{
+  uint32_t state = 0;
+
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
+ 
+  switch (TransmitMailbox)
+  {
+    case (CAN_TXMAILBOX_0): 
+      state =   CANx->TSR &  (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0);
+      break;
+    case (CAN_TXMAILBOX_1): 
+      state =   CANx->TSR &  (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1);
+      break;
+    case (CAN_TXMAILBOX_2): 
+      state =   CANx->TSR &  (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2);
+      break;
+    default:
+      state = CAN_TxStatus_Failed;
+      break;
+  }
+  switch (state)
+  {
+      /* transmit pending  */
+    case (0x0): state = CAN_TxStatus_Pending;
+      break;
+      /* transmit failed  */
+     case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed;
+      break;
+     case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed;
+      break;
+     case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed;
+      break;
+      /* transmit succeeded  */
+    case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok;
+      break;
+    case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok;
+      break;
+    case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok;
+      break;
+    default: state = CAN_TxStatus_Failed;
+      break;
+  }
+  return (uint8_t) state;
+}
+
+/**
+  * @brief  Cancels a transmit request.
+  * @param  CANx: where x can be 1 to select the CAN peripheral.
+  * @param  Mailbox: Mailbox number.
+  * @retval None
+  */
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));
+  /* abort transmission */
+  switch (Mailbox)
+  {
+    case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0;
+      break;
+    case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1;
+      break;
+    case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2;
+      break;
+    default:
+      break;
+  }
+}
+/**
+  * @}
+  */
+
+
+/** @defgroup CAN_Group3 CAN Frames Reception functions
+ *  @brief    CAN Frames Reception functions 
+ *
+@verbatim    
+ ===============================================================================
+                  ##### CAN Frames Reception functions #####
+ ===============================================================================  
+    [..] This section provides functions allowing to 
+         (+) Receive a correct CAN frame.
+         (+) Release a specified receive FIFO (2 FIFOs are available).
+         (+) Return the number of the pending received CAN frames.
+   
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Receives a correct CAN frame.
+  * @param  CANx: where x can be 1 to select the CAN peripheral.
+  * @param  FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+  * @param  RxMessage: pointer to a structure receive frame which contains CAN Id,
+  *         CAN DLC, CAN data and FMI number.
+  * @retval None
+  */
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_FIFO(FIFONumber));
+  /* Get the Id */
+  RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;
+  if (RxMessage->IDE == CAN_Id_Standard)
+  {
+    RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);
+  }
+  else
+  {
+    RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);
+  }
+  
+  RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;
+  /* Get the DLC */
+  RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;
+  /* Get the FMI */
+  RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);
+  /* Get the data field */
+  RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;
+  RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);
+  RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);
+  RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);
+  RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;
+  RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);
+  RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);
+  RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);
+  /* Release the FIFO */
+  /* Release FIFO0 */
+  if (FIFONumber == CAN_FIFO0)
+  {
+    CANx->RF0R |= CAN_RF0R_RFOM0;
+  }
+  /* Release FIFO1 */
+  else /* FIFONumber == CAN_FIFO1 */
+  {
+    CANx->RF1R |= CAN_RF1R_RFOM1;
+  }
+}
+
+/**
+  * @brief  Releases the specified receive FIFO.
+  * @param  CANx: where x can be 1 to select the CAN peripheral.
+  * @param  FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
+  * @retval None
+  */
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_FIFO(FIFONumber));
+  /* Release FIFO0 */
+  if (FIFONumber == CAN_FIFO0)
+  {
+    CANx->RF0R |= CAN_RF0R_RFOM0;
+  }
+  /* Release FIFO1 */
+  else /* FIFONumber == CAN_FIFO1 */
+  {
+    CANx->RF1R |= CAN_RF1R_RFOM1;
+  }
+}
+
+/**
+  * @brief  Returns the number of pending received messages.
+  * @param  CANx: where x can be 1 to select the CAN peripheral.
+  * @param  FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+  * @retval NbMessage : which is the number of pending message.
+  */
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)
+{
+  uint8_t message_pending=0;
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_FIFO(FIFONumber));
+  if (FIFONumber == CAN_FIFO0)
+  {
+    message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03);
+  }
+  else if (FIFONumber == CAN_FIFO1)
+  {
+    message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03);
+  }
+  else
+  {
+    message_pending = 0;
+  }
+  return message_pending;
+}
+/**
+  * @}
+  */
+
+
+/** @defgroup CAN_Group4 CAN Operation modes functions
+ *  @brief    CAN Operation modes functions 
+ *
+@verbatim    
+ ===============================================================================
+                    ##### CAN Operation modes functions #####
+ ===============================================================================  
+    [..] This section provides functions allowing to select the CAN Operation modes:
+         (+) sleep mode.
+         (+) normal mode. 
+         (+) initialization mode.
+   
+@endverbatim
+  * @{
+  */
+  
+  
+/**
+  * @brief  Selects the CAN Operation mode.
+  * @param  CAN_OperatingMode: CAN Operating Mode.
+  *         This parameter can be one of @ref CAN_OperatingMode_TypeDef enumeration.
+  * @retval status of the requested mode which can be: 
+  *         - CAN_ModeStatus_Failed:  CAN failed entering the specific mode 
+  *         - CAN_ModeStatus_Success: CAN Succeed entering the specific mode 
+  */
+uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode)
+{
+  uint8_t status = CAN_ModeStatus_Failed;
+  
+  /* Timeout for INAK or also for SLAK bits*/
+  uint32_t timeout = INAK_TIMEOUT; 
+
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode));
+
+  if (CAN_OperatingMode == CAN_OperatingMode_Initialization)
+  {
+    /* Request initialisation */
+    CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ);
+
+    /* Wait the acknowledge */
+    while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0))
+    {
+      timeout--;
+    }
+    if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK)
+    {
+      status = CAN_ModeStatus_Failed;
+    }
+    else
+    {
+      status = CAN_ModeStatus_Success;
+    }
+  }
+  else  if (CAN_OperatingMode == CAN_OperatingMode_Normal)
+  {
+    /* Request leave initialisation and sleep mode  and enter Normal mode */
+    CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ));
+
+    /* Wait the acknowledge */
+    while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0))
+    {
+      timeout--;
+    }
+    if ((CANx->MSR & CAN_MODE_MASK) != 0)
+    {
+      status = CAN_ModeStatus_Failed;
+    }
+    else
+    {
+      status = CAN_ModeStatus_Success;
+    }
+  }
+  else  if (CAN_OperatingMode == CAN_OperatingMode_Sleep)
+  {
+    /* Request Sleep mode */
+    CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
+
+    /* Wait the acknowledge */
+    while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0))
+    {
+      timeout--;
+    }
+    if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK)
+    {
+      status = CAN_ModeStatus_Failed;
+    }
+    else
+    {
+      status = CAN_ModeStatus_Success;
+    }
+  }
+  else
+  {
+    status = CAN_ModeStatus_Failed;
+  }
+
+  return  (uint8_t) status;
+}
+
+/**
+  * @brief  Enters the Sleep (low power) mode.
+  * @param  CANx: where x can be 1 to select the CAN peripheral.
+  * @retval CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed otherwise.
+  */
+uint8_t CAN_Sleep(CAN_TypeDef* CANx)
+{
+  uint8_t sleepstatus = CAN_Sleep_Failed;
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+    
+  /* Request Sleep mode */
+   CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
+   
+  /* Sleep mode status */
+  if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)
+  {
+    /* Sleep mode not entered */
+    sleepstatus =  CAN_Sleep_Ok;
+  }
+  /* return sleep mode status */
+   return (uint8_t)sleepstatus;
+}
+
+/**
+  * @brief  Wakes up the CAN peripheral from sleep mode .
+  * @param  CANx: where x can be 1 to select the CAN peripheral.
+  * @retval CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed otherwise.
+  */
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
+{
+  uint32_t wait_slak = SLAK_TIMEOUT;
+  uint8_t wakeupstatus = CAN_WakeUp_Failed;
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+    
+  /* Wake up request */
+  CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
+    
+  /* Sleep mode status */
+  while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00))
+  {
+   wait_slak--;
+  }
+  if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)
+  {
+   /* wake up done : Sleep mode exited */
+    wakeupstatus = CAN_WakeUp_Ok;
+  }
+  /* return wakeup status */
+  return (uint8_t)wakeupstatus;
+}
+/**
+  * @}
+  */
+
+
+/** @defgroup CAN_Group5 CAN Bus Error management functions
+ *  @brief    CAN Bus Error management functions 
+ *
+@verbatim    
+ ===============================================================================
+                  ##### CAN Bus Error management functions #####
+ ===============================================================================  
+    [..] This section provides functions allowing to 
+         (+) Return the CANx's last error code (LEC).
+         (+) Return the CANx Receive Error Counter (REC).
+         (+) Return the LSB of the 9-bit CANx Transmit Error Counter(TEC).
+    [..]
+         (@) If TEC is greater than 255, The CAN is in bus-off state.
+         (@) If REC or TEC are greater than 96, an Error warning flag occurs.
+         (@) If REC or TEC are greater than 127, an Error Passive Flag occurs.
+                        
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Returns the CANx's last error code (LEC).
+  * @param  CANx: where x can be 1 to select the CAN peripheral.
+  * @retval Error code: 
+  *          - CAN_ERRORCODE_NoErr: No Error  
+  *          - CAN_ERRORCODE_StuffErr: Stuff Error
+  *          - CAN_ERRORCODE_FormErr: Form Error
+  *          - CAN_ERRORCODE_ACKErr : Acknowledgment Error
+  *          - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error
+  *          - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error
+  *          - CAN_ERRORCODE_CRCErr: CRC Error
+  *          - CAN_ERRORCODE_SoftwareSetErr: Software Set Error  
+  */
+uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx)
+{
+  uint8_t errorcode=0;
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  
+  /* Get the error code*/
+  errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC);
+  
+  /* Return the error code*/
+  return errorcode;
+}
+
+/**
+  * @brief  Returns the CANx Receive Error Counter (REC).
+  * @note   In case of an error during reception, this counter is incremented 
+  *         by 1 or by 8 depending on the error condition as defined by the CAN 
+  *         standard. After every successful reception, the counter is 
+  *         decremented by 1 or reset to 120 if its value was higher than 128. 
+  *         When the counter value exceeds 127, the CAN controller enters the 
+  *         error passive state.  
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.  
+  * @retval CAN Receive Error Counter. 
+  */
+uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx)
+{
+  uint8_t counter=0;
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  
+  /* Get the Receive Error Counter*/
+  counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24);
+  
+  /* Return the Receive Error Counter*/
+  return counter;
+}
+
+
+/**
+  * @brief  Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+  * @retval LSB of the 9-bit CAN Transmit Error Counter. 
+  */
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx)
+{
+  uint8_t counter=0;
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  
+  /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
+  counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16);
+  
+  /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
+  return counter;
+}
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Group6 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+ *
+@verbatim   
+ ===============================================================================
+              ##### Interrupts and flags management functions #####
+ ===============================================================================  
+    [..] This section provides functions allowing to configure the CAN Interrupts 
+         and to get the status and clear flags and Interrupts pending bits.
+    [..] The CAN provides 14 Interrupts sources and 15 Flags:
+   
+  *** Flags ***
+  =============
+    [..] The 15 flags can be divided on 4 groups: 
+         (+) Transmit Flags:
+             (++) CAN_FLAG_RQCP0. 
+             (++) CAN_FLAG_RQCP1. 
+             (++) CAN_FLAG_RQCP2: Request completed MailBoxes 0, 1 and 2  Flags
+                  Set when when the last request (transmit or abort) has 
+                  been performed. 
+         (+) Receive Flags:
+             (++) CAN_FLAG_FMP0.
+             (++) CAN_FLAG_FMP1: FIFO 0 and 1 Message Pending Flags; 
+                  Set to signal that messages are pending in the receive FIFO.
+                  These Flags are cleared only by hardware. 
+             (++) CAN_FLAG_FF0.
+             (++) CAN_FLAG_FF1: FIFO 0 and 1 Full Flags; 
+                  Set when three messages are stored in the selected FIFO.                        
+             (++) CAN_FLAG_FOV0.              
+             (++) CAN_FLAG_FOV1: FIFO 0 and 1 Overrun Flags; 
+                  Set when a new message has been received and passed the filter 
+                  while the FIFO was full.         
+         (+) Operating Mode Flags: 
+             (++) CAN_FLAG_WKU: Wake up Flag; 
+                  Set to signal that a SOF bit has been detected while the CAN 
+                  hardware was in Sleep mode. 
+             (++) CAN_FLAG_SLAK: Sleep acknowledge Flag;
+                  Set to signal that the CAN has entered Sleep Mode. 
+         (+) Error Flags:  
+             (++) CAN_FLAG_EWG: Error Warning Flag;
+                  Set when the warning limit has been reached (Receive Error Counter 
+                  or Transmit Error Counter greater than 96). 
+                  This Flag is cleared only by hardware.
+             (++) CAN_FLAG_EPV: Error Passive Flag;
+                  Set when the Error Passive limit has been reached (Receive Error 
+                  Counter or Transmit Error Counter greater than 127).
+                  This Flag is cleared only by hardware.
+             (++) CAN_FLAG_BOF: Bus-Off Flag;
+                  Set when CAN enters the bus-off state. The bus-off state is 
+                  entered on TEC overflow, greater than 255.
+                  This Flag is cleared only by hardware.
+             (++) CAN_FLAG_LEC: Last error code Flag;
+                  Set If a message has been transferred (reception or transmission) 
+                  with error, and the error code is hold.                      
+  
+  *** Interrupts ***
+  ==================
+    [..] The 14 interrupts can be divided on 4 groups: 
+         (+) Transmit interrupt:   
+             (++) CAN_IT_TME: Transmit mailbox empty Interrupt;
+                  If enabled, this interrupt source is pending when no transmit 
+                  request are pending for Tx mailboxes.      
+         (+) Receive Interrupts:   
+             (++) CAN_IT_FMP0.
+             (++) CAN_IT_FMP1: FIFO 0 and FIFO1 message pending Interrupts;
+                  If enabled, these interrupt sources are pending when messages 
+                  are pending in the receive FIFO.
+                  The corresponding interrupt pending bits are cleared only by hardware.
+             (++) CAN_IT_FF0.              
+             (++) CAN_IT_FF1: FIFO 0 and FIFO1 full Interrupts;
+                  If enabled, these interrupt sources are pending when three messages 
+                  are stored in the selected FIFO.
+             (++) CAN_IT_FOV0.        
+             (++) CAN_IT_FOV1: FIFO 0 and FIFO1 overrun Interrupts;        
+                  If enabled, these interrupt sources are pending when a new message 
+                  has been received and passed the filter while the FIFO was full.
+         (+) Operating Mode Interrupts:    
+             (++) CAN_IT_WKU: Wake-up Interrupt;
+                  If enabled, this interrupt source is pending when a SOF bit has 
+                  been detected while the CAN hardware was in Sleep mode.
+             (++) CAN_IT_SLK: Sleep acknowledge Interrupt:
+                  If enabled, this interrupt source is pending when the CAN has 
+                  entered Sleep Mode.       
+         (+) Error Interrupts:     
+             (++) CAN_IT_EWG: Error warning Interrupt; 
+                  If enabled, this interrupt source is pending when the warning limit 
+                  has been reached (Receive Error Counter or Transmit Error Counter=96). 
+             (++) CAN_IT_EPV: Error passive Interrupt;        
+                  If enabled, this interrupt source is pending when the Error Passive 
+                  limit has been reached (Receive Error Counter or Transmit Error Counter>127).
+             (++) CAN_IT_BOF: Bus-off Interrupt;
+                  If enabled, this interrupt source is pending when CAN enters 
+                  the bus-off state. The bus-off state is entered on TEC overflow, 
+                  greater than 255.
+                  This Flag is cleared only by hardware.
+             (++) CAN_IT_LEC: Last error code Interrupt;        
+                  If enabled, this interrupt source is pending when a message has 
+                  been transferred (reception or transmission) with error and the 
+                  error code is hold.
+             (++) CAN_IT_ERR: Error Interrupt;
+                  If enabled, this interrupt source is pending when an error condition 
+                  is pending.      
+    [..] Managing the CAN controller events: 
+         The user should identify which mode will be used in his application to manage 
+         the CAN controller events: Polling mode or Interrupt mode.
+         (+) In the Polling Mode it is advised to use the following functions:
+             (++) CAN_GetFlagStatus() : to check if flags events occur. 
+             (++) CAN_ClearFlag()     : to clear the flags events.
+         (+) In the Interrupt Mode it is advised to use the following functions:
+             (++) CAN_ITConfig()       : to enable or disable the interrupt source.
+             (++) CAN_GetITStatus()    : to check if Interrupt occurs.
+             (++) CAN_ClearITPendingBit() : to clear the Interrupt pending Bit 
+                  (corresponding Flag).
+                  This function has no impact on CAN_IT_FMP0 and CAN_IT_FMP1 Interrupts 
+                  pending bits since there are cleared only by hardware. 
+  
+@endverbatim
+  * @{
+  */ 
+/**
+  * @brief  Enables or disables the specified CANx interrupts.
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.
+  *          This parameter can be: 
+  *            @arg CAN_IT_TME: Transmit mailbox empty Interrupt 
+  *            @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt 
+  *            @arg CAN_IT_FF0: FIFO 0 full Interrupt
+  *            @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
+  *            @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt 
+  *            @arg CAN_IT_FF1: FIFO 1 full Interrupt
+  *            @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
+  *            @arg CAN_IT_WKU: Wake-up Interrupt
+  *            @arg CAN_IT_SLK: Sleep acknowledge Interrupt  
+  *            @arg CAN_IT_EWG: Error warning Interrupt
+  *            @arg CAN_IT_EPV: Error passive Interrupt
+  *            @arg CAN_IT_BOF: Bus-off Interrupt  
+  *            @arg CAN_IT_LEC: Last error code Interrupt
+  *            @arg CAN_IT_ERR: Error Interrupt
+  * @param  NewState: new state of the CAN interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_IT(CAN_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected CANx interrupt */
+    CANx->IER |= CAN_IT;
+  }
+  else
+  {
+    /* Disable the selected CANx interrupt */
+    CANx->IER &= ~CAN_IT;
+  }
+}
+/**
+  * @brief  Checks whether the specified CAN flag is set or not.
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  CAN_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg CAN_FLAG_RQCP0: Request MailBox0 Flag
+  *            @arg CAN_FLAG_RQCP1: Request MailBox1 Flag
+  *            @arg CAN_FLAG_RQCP2: Request MailBox2 Flag
+  *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag   
+  *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag       
+  *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag 
+  *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag   
+  *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag        
+  *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag     
+  *            @arg CAN_FLAG_WKU: Wake up Flag
+  *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag 
+  *            @arg CAN_FLAG_EWG: Error Warning Flag
+  *            @arg CAN_FLAG_EPV: Error Passive Flag  
+  *            @arg CAN_FLAG_BOF: Bus-Off Flag    
+  *            @arg CAN_FLAG_LEC: Last error code Flag      
+  * @retval The new state of CAN_FLAG (SET or RESET).
+  */
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_GET_FLAG(CAN_FLAG));
+  
+
+  if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET)
+  { 
+    /* Check the status of the specified CAN flag */
+    if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+    { 
+      /* CAN_FLAG is set */
+      bitstatus = SET;
+    }
+    else
+    { 
+      /* CAN_FLAG is reset */
+      bitstatus = RESET;
+    }
+  }
+  else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET)
+  { 
+    /* Check the status of the specified CAN flag */
+    if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+    { 
+      /* CAN_FLAG is set */
+      bitstatus = SET;
+    }
+    else
+    { 
+      /* CAN_FLAG is reset */
+      bitstatus = RESET;
+    }
+  }
+  else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET)
+  { 
+    /* Check the status of the specified CAN flag */
+    if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+    { 
+      /* CAN_FLAG is set */
+      bitstatus = SET;
+    }
+    else
+    { 
+      /* CAN_FLAG is reset */
+      bitstatus = RESET;
+    }
+  }
+  else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET)
+  { 
+    /* Check the status of the specified CAN flag */
+    if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+    { 
+      /* CAN_FLAG is set */
+      bitstatus = SET;
+    }
+    else
+    { 
+      /* CAN_FLAG is reset */
+      bitstatus = RESET;
+    }
+  }
+  else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */
+  { 
+    /* Check the status of the specified CAN flag */
+    if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+    { 
+      /* CAN_FLAG is set */
+      bitstatus = SET;
+    }
+    else
+    { 
+      /* CAN_FLAG is reset */
+      bitstatus = RESET;
+    }
+  }
+  /* Return the CAN_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the CAN's pending flags.
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  CAN_FLAG: specifies the flag to clear.
+  *          This parameter can be one of the following values:
+  *            @arg CAN_FLAG_RQCP0: Request MailBox0 Flag
+  *            @arg CAN_FLAG_RQCP1: Request MailBox1 Flag
+  *            @arg CAN_FLAG_RQCP2: Request MailBox2 Flag 
+  *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag       
+  *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag  
+  *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag        
+  *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag     
+  *            @arg CAN_FLAG_WKU: Wake up Flag
+  *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag    
+  *            @arg CAN_FLAG_LEC: Last error code Flag        
+  * @retval None
+  */
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
+{
+  uint32_t flagtmp=0;
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));
+  
+  if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */
+  {
+    /* Clear the selected CAN flags */
+    CANx->ESR = (uint32_t)RESET;
+  }
+  else /* MSR or TSR or RF0R or RF1R */
+  {
+    flagtmp = CAN_FLAG & 0x000FFFFF;
+
+    if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET)
+    {
+      /* Receive Flags */
+      CANx->RF0R = (uint32_t)(flagtmp);
+    }
+    else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET)
+    {
+      /* Receive Flags */
+      CANx->RF1R = (uint32_t)(flagtmp);
+    }
+    else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET)
+    {
+      /* Transmit Flags */
+      CANx->TSR = (uint32_t)(flagtmp);
+    }
+    else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */
+    {
+      /* Operating mode Flags */
+      CANx->MSR = (uint32_t)(flagtmp);
+    }
+  }
+}
+
+/**
+  * @brief  Checks whether the specified CANx interrupt has occurred or not.
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  CAN_IT: specifies the CAN interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg CAN_IT_TME: Transmit mailbox empty Interrupt 
+  *            @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt 
+  *            @arg CAN_IT_FF0: FIFO 0 full Interrupt
+  *            @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
+  *            @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt 
+  *            @arg CAN_IT_FF1: FIFO 1 full Interrupt
+  *            @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
+  *            @arg CAN_IT_WKU: Wake-up Interrupt
+  *            @arg CAN_IT_SLK: Sleep acknowledge Interrupt  
+  *            @arg CAN_IT_EWG: Error warning Interrupt
+  *            @arg CAN_IT_EPV: Error passive Interrupt
+  *            @arg CAN_IT_BOF: Bus-off Interrupt  
+  *            @arg CAN_IT_LEC: Last error code Interrupt
+  *            @arg CAN_IT_ERR: Error Interrupt
+  * @retval The current state of CAN_IT (SET or RESET).
+  */
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)
+{
+  ITStatus itstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_IT(CAN_IT));
+  
+  /* check the interrupt enable bit */
+ if((CANx->IER & CAN_IT) != RESET)
+ {
+   /* in case the Interrupt is enabled, .... */
+    switch (CAN_IT)
+    {
+      case CAN_IT_TME:
+        /* Check CAN_TSR_RQCPx bits */
+        itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2);  
+        break;
+      case CAN_IT_FMP0:
+        /* Check CAN_RF0R_FMP0 bit */
+        itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0);  
+        break;
+      case CAN_IT_FF0:
+        /* Check CAN_RF0R_FULL0 bit */
+        itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0);  
+        break;
+      case CAN_IT_FOV0:
+        /* Check CAN_RF0R_FOVR0 bit */
+        itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0);  
+        break;
+      case CAN_IT_FMP1:
+        /* Check CAN_RF1R_FMP1 bit */
+        itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1);  
+        break;
+      case CAN_IT_FF1:
+        /* Check CAN_RF1R_FULL1 bit */
+        itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1);  
+        break;
+      case CAN_IT_FOV1:
+        /* Check CAN_RF1R_FOVR1 bit */
+        itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1);  
+        break;
+      case CAN_IT_WKU:
+        /* Check CAN_MSR_WKUI bit */
+        itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI);  
+        break;
+      case CAN_IT_SLK:
+        /* Check CAN_MSR_SLAKI bit */
+        itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI);  
+        break;
+      case CAN_IT_EWG:
+        /* Check CAN_ESR_EWGF bit */
+        itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF);  
+        break;
+      case CAN_IT_EPV:
+        /* Check CAN_ESR_EPVF bit */
+        itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF);  
+        break;
+      case CAN_IT_BOF:
+        /* Check CAN_ESR_BOFF bit */
+        itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF);  
+        break;
+      case CAN_IT_LEC:
+        /* Check CAN_ESR_LEC bit */
+        itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC);  
+        break;
+      case CAN_IT_ERR:
+        /* Check CAN_MSR_ERRI bit */ 
+        itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI); 
+        break;
+      default:
+        /* in case of error, return RESET */
+        itstatus = RESET;
+        break;
+    }
+  }
+  else
+  {
+   /* in case the Interrupt is not enabled, return RESET */
+    itstatus  = RESET;
+  }
+  
+  /* Return the CAN_IT status */
+  return  itstatus;
+}
+
+/**
+  * @brief  Clears the CANx's interrupt pending bits.
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  CAN_IT: specifies the interrupt pending bit to clear.
+  *          This parameter can be one of the following values:
+  *            @arg CAN_IT_TME: Transmit mailbox empty Interrupt
+  *            @arg CAN_IT_FF0: FIFO 0 full Interrupt
+  *            @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
+  *            @arg CAN_IT_FF1: FIFO 1 full Interrupt
+  *            @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
+  *            @arg CAN_IT_WKU: Wake-up Interrupt
+  *            @arg CAN_IT_SLK: Sleep acknowledge Interrupt  
+  *            @arg CAN_IT_EWG: Error warning Interrupt
+  *            @arg CAN_IT_EPV: Error passive Interrupt
+  *            @arg CAN_IT_BOF: Bus-off Interrupt  
+  *            @arg CAN_IT_LEC: Last error code Interrupt
+  *            @arg CAN_IT_ERR: Error Interrupt 
+  * @retval None
+  */
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_CLEAR_IT(CAN_IT));
+
+  switch (CAN_IT)
+  {
+    case CAN_IT_TME:
+      /* Clear CAN_TSR_RQCPx (rc_w1)*/
+      CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2;  
+      break;
+    case CAN_IT_FF0:
+      /* Clear CAN_RF0R_FULL0 (rc_w1)*/
+      CANx->RF0R = CAN_RF0R_FULL0; 
+      break;
+    case CAN_IT_FOV0:
+      /* Clear CAN_RF0R_FOVR0 (rc_w1)*/
+      CANx->RF0R = CAN_RF0R_FOVR0; 
+      break;
+    case CAN_IT_FF1:
+      /* Clear CAN_RF1R_FULL1 (rc_w1)*/
+      CANx->RF1R = CAN_RF1R_FULL1;  
+      break;
+    case CAN_IT_FOV1:
+      /* Clear CAN_RF1R_FOVR1 (rc_w1)*/
+      CANx->RF1R = CAN_RF1R_FOVR1; 
+      break;
+    case CAN_IT_WKU:
+      /* Clear CAN_MSR_WKUI (rc_w1)*/
+      CANx->MSR = CAN_MSR_WKUI;  
+      break;
+    case CAN_IT_SLK:
+      /* Clear CAN_MSR_SLAKI (rc_w1)*/ 
+      CANx->MSR = CAN_MSR_SLAKI;   
+      break;
+    case CAN_IT_EWG:
+      /* Clear CAN_MSR_ERRI (rc_w1) */
+      CANx->MSR = CAN_MSR_ERRI;
+       /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ 
+      break;
+    case CAN_IT_EPV:
+      /* Clear CAN_MSR_ERRI (rc_w1) */
+      CANx->MSR = CAN_MSR_ERRI; 
+       /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
+      break;
+    case CAN_IT_BOF:
+      /* Clear CAN_MSR_ERRI (rc_w1) */ 
+      CANx->MSR = CAN_MSR_ERRI; 
+       /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
+       break;
+    case CAN_IT_LEC:
+      /*  Clear LEC bits */
+      CANx->ESR = RESET; 
+      /* Clear CAN_MSR_ERRI (rc_w1) */
+      CANx->MSR = CAN_MSR_ERRI; 
+      break;
+    case CAN_IT_ERR:
+      /*Clear LEC bits */
+      CANx->ESR = RESET; 
+      /* Clear CAN_MSR_ERRI (rc_w1) */
+      CANx->MSR = CAN_MSR_ERRI; 
+       /* @note BOFF, EPVF and EWGF Flags are cleared by hardware depending on the CAN Bus status*/
+       break;
+    default:
+       break;
+   }
+}
+ /**
+  * @}
+  */
+
+/**
+  * @brief  Checks whether the CAN interrupt has occurred or not.
+  * @param  CAN_Reg: specifies the CAN interrupt register to check.
+  * @param  It_Bit: specifies the interrupt source bit to check.
+  * @retval The new state of the CAN Interrupt (SET or RESET).
+  */
+static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
+{
+  ITStatus pendingbitstatus = RESET;
+  
+  if ((CAN_Reg & It_Bit) != (uint32_t)RESET)
+  {
+    /* CAN_IT is set */
+    pendingbitstatus = SET;
+  }
+  else
+  {
+    /* CAN_IT is reset */
+    pendingbitstatus = RESET;
+  }
+  return pendingbitstatus;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_cec.c b/system/src/stm32f0-stdperiph/stm32f0xx_cec.c

new file mode 100644 (file)

index 0000000..fc2b33f
--- /dev/null
+++ b/system/src/stm32f0-stdperiph/stm32f0xx_cec.c
@@ -0,0 +1,607 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_cec.c
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Consumer Electronics Control (CEC) peripheral
+  *          applicable only on STM32F051, STM32F042 and STM32F072 devices:
+  *            + Initialization and Configuration
+  *            + Data transfers functions
+  *            + Interrupts and flags management
+  *               
+  *  @verbatim
+  ==============================================================================
+                            ##### CEC features #####
+  ==============================================================================
+      [..] This device provides some features:
+           (#) Supports HDMI-CEC specification 1.4.
+           (#) Supports two source clocks(HSI/244 or LSE).
+           (#) Works in stop mode(without APB clock, but with CEC clock 32KHz).
+               It can genarate an interrupt in the CEC clock domain that the CPU 
+               wakes up from the low power mode.
+           (#) Configurable Signal Free Time before of transmission start. The 
+               number of nominal data bit periods waited before transmission can be
+               ruled by Hardware or Software.
+           (#) Configurable Peripheral Address (multi-addressing configuration).
+           (#) Supports listen mode.The CEC Messages addressed to different destination
+               can be received without interfering with CEC bus when Listen mode option is enabled.
+           (#) Configurable Rx-Tolerance(Standard and Extended tolerance margin).
+           (#) Error detection with configurable error bit generation.
+           (#) Arbitration lost error in the case of two CEC devices starting at the same time.
+
+                            ##### How to use this driver ##### 
+  ==============================================================================
+      [..] This driver provides functions to configure and program the CEC device,
+       follow steps below:
+           (#) The source clock can be configured using:
+               (++) RCC_CECCLKConfig(RCC_CECCLK_HSI_Div244) for HSI(Default) 
+               (++) RCC_CECCLKConfig(RCC_CECCLK_LSE) for LSE.
+           (#) Enable CEC peripheral clock using RCC_APBPeriphClockCmd(RCC_APBPeriph_CEC, ENABLE).
+           (#) Peripherals alternate function.
+               (++) Connect the pin to the desired peripherals' Alternate Function (AF) using 
+               GPIO_PinAFConfig() function.
+               (++) Configure the desired pin in alternate function by:
+               GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
+               (++) Select the type open-drain and output speed via GPIO_OType 
+               and GPIO_Speed members.
+               (++) Call GPIO_Init() function.
+           (#) Configure the Signal Free Time, Rx Tolerance, Stop reception generation 
+               and Bit error generation using the CEC_Init() function.
+               The function CEC_Init() must be called when the CEC peripheral is disabled.
+           (#) Configure the CEC own address by calling the fuction CEC_OwnAddressConfig().
+           (#) Optionally, you can configure the Listen mode using the function CEC_ListenModeCmd().
+           (#) Enable the NVIC and the corresponding interrupt using the function 
+               CEC_ITConfig() if you need to use interrupt mode.
+               CEC_ITConfig() must be called before enabling the CEC peripheral.
+           (#) Enable the CEC using the CEC_Cmd() function.
+           (#) Charge the first data byte in the TXDR register using CEC_SendDataByte().
+           (#) Enable the transmission of the Byte of a CEC message using CEC_StartOfMessage() 
+           (#) Transmit single data through the CEC peripheral using CEC_SendDataByte() 
+               and Receive the last transmitted byte using CEC_ReceiveDataByte().
+           (#) Enable the CEC_EndOfMessage() in order to indicate the last byte of the message.
+      [..]
+           (@) If the listen mode is enabled, Stop reception generation and Bit error generation 
+               must be in reset state.
+           (@) If the CEC message consists of only 1 byte, the function CEC_EndOfMessage()
+               must be called before CEC_StartOfMessage().
+  
+   @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_cec.h"
+#include "stm32f0xx_rcc.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CEC 
+  * @brief CEC driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define BROADCAST_ADDRESS      ((uint32_t)0x0000F)
+#define CFGR_CLEAR_MASK        ((uint32_t)0x7000FE00)   /* CFGR register Mask */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup CEC_Private_Functions 
+  * @{
+  */
+
+/** @defgroup CEC_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions
+ *
+@verbatim  
+ ===============================================================================
+                            ##### Initialization and Configuration functions #####
+ ===============================================================================
+      [..] This section provides functions allowing to initialize:
+            (+) CEC own addresses
+            (+) CEC Signal Free Time
+            (+) CEC Rx Tolerance
+            (+) CEC Stop Reception
+            (+) CEC Bit Rising Error
+            (+) CEC Long Bit Period Error
+      [..] This section provides also a function to configure the CEC peripheral in Listen Mode.
+           Messages addressed to different destination can be received when Listen mode is 
+           enabled without interfering with CEC bus.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the CEC peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void CEC_DeInit(void)
+{
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE);
+}
+
+/**
+  * @brief  Initializes the CEC peripheral according to the specified parameters
+  *         in the CEC_InitStruct.
+  * @note   The CEC parameters must be configured before enabling the CEC peripheral.
+  * @param  CEC_InitStruct: pointer to an CEC_InitTypeDef structure that contains
+  *         the configuration information for the specified CEC peripheral.
+  * @retval None
+  */
+void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_CEC_SIGNAL_FREE_TIME(CEC_InitStruct->CEC_SignalFreeTime));
+  assert_param(IS_CEC_RX_TOLERANCE(CEC_InitStruct->CEC_RxTolerance));
+  assert_param(IS_CEC_STOP_RECEPTION(CEC_InitStruct->CEC_StopReception));
+  assert_param(IS_CEC_BIT_RISING_ERROR(CEC_InitStruct->CEC_BitRisingError));
+  assert_param(IS_CEC_LONG_BIT_PERIOD_ERROR(CEC_InitStruct->CEC_LongBitPeriodError));
+  assert_param(IS_CEC_BDR_NO_GEN_ERROR(CEC_InitStruct->CEC_BRDNoGen));
+  assert_param(IS_CEC_SFT_OPTION(CEC_InitStruct->CEC_SFTOption));
+
+  /* Get the CEC CFGR value */
+  tmpreg = CEC->CFGR;
+
+  /* Clear CFGR bits */
+  tmpreg &= CFGR_CLEAR_MASK;
+
+  /* Configure the CEC peripheral */
+  tmpreg |= (CEC_InitStruct->CEC_SignalFreeTime | CEC_InitStruct->CEC_RxTolerance |
+             CEC_InitStruct->CEC_StopReception  | CEC_InitStruct->CEC_BitRisingError |
+             CEC_InitStruct->CEC_LongBitPeriodError| CEC_InitStruct->CEC_BRDNoGen |
+             CEC_InitStruct->CEC_SFTOption);
+
+  /* Write to CEC CFGR  register */
+  CEC->CFGR = tmpreg;
+}
+
+/**
+  * @brief  Fills each CEC_InitStruct member with its default value.
+  * @param  CEC_InitStruct: pointer to a CEC_InitTypeDef structure which will 
+  *         be initialized.
+  * @retval None
+  */
+void CEC_StructInit(CEC_InitTypeDef* CEC_InitStruct)
+{
+  CEC_InitStruct->CEC_SignalFreeTime = CEC_SignalFreeTime_Standard;
+  CEC_InitStruct->CEC_RxTolerance = CEC_RxTolerance_Standard;
+  CEC_InitStruct->CEC_StopReception = CEC_StopReception_Off;
+  CEC_InitStruct->CEC_BitRisingError = CEC_BitRisingError_Off;
+  CEC_InitStruct->CEC_LongBitPeriodError = CEC_LongBitPeriodError_Off;
+  CEC_InitStruct->CEC_BRDNoGen = CEC_BRDNoGen_Off;
+  CEC_InitStruct->CEC_SFTOption = CEC_SFTOption_Off;
+}
+
+/**
+  * @brief  Enables or disables the CEC peripheral.
+  * @param  NewState: new state of the CEC peripheral.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CEC_Cmd(FunctionalState NewState)
+{
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the CEC peripheral */
+    CEC->CR |= CEC_CR_CECEN;
+  }
+  else
+  {
+    /* Disable the CEC peripheral */
+    CEC->CR &= ~CEC_CR_CECEN;
+  }
+}
+
+/**
+  * @brief  Enables or disables the CEC Listen Mode.
+  * @param  NewState: new state of the Listen Mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CEC_ListenModeCmd(FunctionalState NewState)
+{
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Listen Mode */
+    CEC->CFGR |= CEC_CFGR_LSTN;
+  }
+  else
+  {
+    /* Disable the Listen Mode */
+    CEC->CFGR &= ~CEC_CFGR_LSTN;
+  }
+}
+
+/**
+  * @brief  Defines the Own Address of the CEC device.
+  * @param  CEC_OwnAddress: The CEC own address.
+  * @retval None
+  */
+void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
+{
+  uint32_t tmp =0x00;
+  /* Check the parameters */
+  assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));
+  tmp = 1 <<(CEC_OwnAddress + 16);
+  /* Set the CEC own address */
+  CEC->CFGR |= tmp;
+}
+
+/**
+  * @brief  Clears the Own Address of the CEC device.
+  * @param  CEC_OwnAddress: The CEC own address.
+  * @retval None
+  */
+void CEC_OwnAddressClear(void)
+{
+  /* Set the CEC own address */
+  CEC->CFGR = 0x0;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Group2 Data transfers functions
+ *  @brief    Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+                            ##### Data transfers functions #####
+ ===============================================================================
+    [..] This section provides functions allowing the CEC data transfers.The read 
+         access of the CEC_RXDR register can be done using the CEC_ReceiveData()function 
+         and returns the Rx buffered value. Whereas a write access to the CEC_TXDR can be 
+         done using CEC_SendData() function.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmits single data through the CEC peripheral.
+  * @param  Data: the data to transmit.
+  * @retval None
+  */
+void CEC_SendData(uint8_t Data)
+{
+  /* Transmit Data */
+  CEC->TXDR = Data;
+}
+
+/**
+  * @brief  Returns the most recent received data by the CEC peripheral.
+  * @param  None
+  * @retval The received data.
+  */
+uint8_t CEC_ReceiveData(void)
+{
+  /* Receive Data */
+  return (uint8_t)(CEC->RXDR);
+}
+
+/**
+  * @brief  Starts a new message.
+  * @param  None
+  * @retval None
+  */
+void CEC_StartOfMessage(void)
+{
+  /* Starts of new message */
+  CEC->CR |= CEC_CR_TXSOM; 
+}
+
+/**
+  * @brief  Transmits message with an EOM bit.
+  * @param  None
+  * @retval None
+  */
+void CEC_EndOfMessage(void)
+{
+  /* The data byte will be transmitted with an EOM bit */
+  CEC->CR |= CEC_CR_TXEOM;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Group3 Interrupts and flags management functions
+ *  @brief    Interrupts and flags management functions
+*
+@verbatim
+ ===============================================================================
+                            ##### Interrupts and flags management functions ##### 
+ ===============================================================================
+    [..] This section provides functions allowing to configure the CEC Interrupts
+         sources and check or clear the flags or pending bits status.
+    [..] The user should identify which mode will be used in his application to manage
+         the communication: Polling mode or Interrupt mode.
+  
+    [..] In polling mode, the CEC can be managed by the following flags:
+            (+) CEC_FLAG_TXACKE : to indicate a missing acknowledge in transmission mode.
+            (+) CEC_FLAG_TXERR  : to indicate an error occurs during transmission mode.
+                                  The initiator detects low impedance in the CEC line.
+            (+) CEC_FLAG_TXUDR  : to indicate if an underrun error occurs in transmission mode.
+                                  The transmission is enabled while the software has not yet 
+                                  loaded any value into the TXDR register.
+            (+) CEC_FLAG_TXEND  : to indicate the end of successful transmission.
+            (+) CEC_FLAG_TXBR   : to indicate the next transmission data has to be written to TXDR.
+            (+) CEC_FLAG_ARBLST : to indicate arbitration lost in the case of two CEC devices
+                                  starting at the same time.
+            (+) CEC_FLAG_RXACKE : to indicate a missing acknowledge in receive mode.
+            (+) CEC_FLAG_LBPE   : to indicate a long bit period error generated during receive mode.
+            (+) CEC_FLAG_SBPE   : to indicate a short bit period error generated during receive mode.
+            (+) CEC_FLAG_BRE    : to indicate a bit rising error generated during receive mode.
+            (+) CEC_FLAG_RXOVR  : to indicate if an overrun error occur while receiving a CEC message.
+                                  A byte is not yet received while a new byte is stored in the RXDR register.
+            (+) CEC_FLAG_RXEND  : to indicate the end Of reception
+            (+) CEC_FLAG_RXBR   : to indicate a new byte has been received from the CEC line and 
+                                  stored into the RXDR buffer.
+    [..]
+           (@)In this Mode, it is advised to use the following functions:
+              FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG);
+              void CEC_ClearFlag(uint16_t CEC_FLAG);
+
+    [..] In Interrupt mode, the CEC can be managed by the following interrupt sources:
+           (+) CEC_IT_TXACKE : to indicate a TX Missing acknowledge 
+           (+) CEC_IT_TXACKE : to indicate a missing acknowledge in transmission mode.
+           (+) CEC_IT_TXERR  : to indicate an error occurs during transmission mode.
+                               The initiator detects low impedance in the CEC line.
+           (+) CEC_IT_TXUDR  : to indicate if an underrun error occurs in transmission mode.
+                               The transmission is enabled while the software has not yet 
+                               loaded any value into the TXDR register.
+           (+) CEC_IT_TXEND  : to indicate the end of successful transmission.
+           (+) CEC_IT_TXBR   : to indicate the next transmission data has to be written to TXDR register.
+           (+) CEC_IT_ARBLST : to indicate arbitration lost in the case of two CEC devices
+                                starting at the same time.
+           (+) CEC_IT_RXACKE : to indicate a missing acknowledge in receive mode.
+           (+) CEC_IT_LBPE   : to indicate a long bit period error generated during receive mode.
+           (+) CEC_IT_SBPE   : to indicate a short bit period error generated during receive mode.
+           (+) CEC_IT_BRE    : to indicate a bit rising error generated during receive mode.
+           (+) CEC_IT_RXOVR  : to indicate if an overrun error occur while receiving a CEC message.
+                               A byte is not yet received while a new byte is stored in the RXDR register.
+           (+) CEC_IT_RXEND  : to indicate the end Of reception
+           (+) CEC_IT_RXBR   : to indicate a new byte has been received from the CEC line and 
+                                stored into the RXDR buffer.
+    [..]
+           (@)In this Mode it is advised to use the following functions:
+              void CEC_ITConfig( uint16_t CEC_IT, FunctionalState NewState);
+              ITStatus CEC_GetITStatus(uint16_t CEC_IT);
+              void CEC_ClearITPendingBit(uint16_t CEC_IT);
+              
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the selected CEC interrupts.
+  * @param  CEC_IT: specifies the CEC interrupt source to be enabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error
+  *            @arg CEC_IT_TXERR: Tx Error.
+  *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun.
+  *            @arg CEC_IT_TXEND: End of Transmission (successful transmission of the last byte).
+  *            @arg CEC_IT_TXBR: Tx-Byte Request.
+  *            @arg CEC_IT_ARBLST: Arbitration Lost
+  *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge
+  *            @arg CEC_IT_LBPE: Rx Long period Error
+  *            @arg CEC_IT_SBPE: Rx Short period Error
+  *            @arg CEC_IT_BRE: Rx Bit Rising Error
+  *            @arg CEC_IT_RXOVR: Rx Overrun.
+  *            @arg CEC_IT_RXEND: End Of Reception
+  *            @arg CEC_IT_RXBR: Rx-Byte Received
+  * @param  NewState: new state of the selected CEC interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CEC_ITConfig(uint16_t CEC_IT, FunctionalState NewState)
+{
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_CEC_IT(CEC_IT));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected CEC interrupt */
+    CEC->IER |= CEC_IT;
+  }
+  else
+  {
+    CEC_IT =~CEC_IT;
+    /* Disable the selected CEC interrupt */
+    CEC->IER &= CEC_IT;
+  }
+}
+
+/**
+  * @brief  Gets the CEC flag status.
+  * @param  CEC_FLAG: specifies the CEC flag to check.
+  *     This parameter can be one of the following values:
+  *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
+  *            @arg CEC_FLAG_TXERR: Tx Error.
+  *            @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
+  *            @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
+  *            @arg CEC_FLAG_TXBR: Tx-Byte Request.
+  *            @arg CEC_FLAG_ARBLST: Arbitration Lost
+  *            @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge 
+  *            @arg CEC_FLAG_LBPE: Rx Long period Error
+  *            @arg CEC_FLAG_SBPE: Rx Short period Error
+  *            @arg CEC_FLAG_BRE: Rx Bit Rissing Error
+  *            @arg CEC_FLAG_RXOVR: Rx Overrun.
+  *            @arg CEC_FLAG_RXEND: End Of Reception.
+  *            @arg CEC_FLAG_RXBR: Rx-Byte Received.
+  * @retval The new state of CEC_FLAG (SET or RESET)
+  */
+FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG) 
+{
+  FlagStatus bitstatus = RESET;
+  
+  assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
+  
+  /* Check the status of the specified CEC flag */
+  if ((CEC->ISR & CEC_FLAG) != (uint16_t)RESET)
+  {
+    /* CEC flag is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* CEC flag is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the CEC flag status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the CEC's pending flags.
+  * @param  CEC_FLAG: specifies the flag to clear. 
+  *          This parameter can be any combination of the following values:
+  *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
+  *            @arg CEC_FLAG_TXERR: Tx Error
+  *            @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun
+  *            @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
+  *            @arg CEC_FLAG_TXBR: Tx-Byte Request
+  *            @arg CEC_FLAG_ARBLST: Arbitration Lost
+  *            @arg CEC_FLAG_RXACKE: Rx Missing Acknowledge 
+  *            @arg CEC_FLAG_LBPE: Rx Long period Error
+  *            @arg CEC_FLAG_SBPE: Rx Short period Error
+  *            @arg CEC_FLAG_BRE: Rx Bit Rising Error
+  *            @arg CEC_FLAG_RXOVR: Rx Overrun
+  *            @arg CEC_FLAG_RXEND: End Of Reception
+  *            @arg CEC_FLAG_RXBR: Rx-Byte Received
+  * @retval None
+  */
+void CEC_ClearFlag(uint32_t CEC_FLAG)
+{
+  assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));
+
+  /* Clear the selected CEC flag */
+  CEC->ISR = CEC_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified CEC interrupt has occurred or not.
+  * @param  CEC_IT: specifies the CEC interrupt source to check. 
+  *          This parameter can be one of the following values:
+  *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error
+  *            @arg CEC_IT_TXERR: Tx Error.
+  *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun.
+  *            @arg CEC_IT_TXEND: End of transmission (successful transmission of the last byte).
+  *            @arg CEC_IT_TXBR: Tx-Byte Request.
+  *            @arg CEC_IT_ARBLST: Arbitration Lost.
+  *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge.
+  *            @arg CEC_IT_LBPE: Rx Long period Error.
+  *            @arg CEC_IT_SBPE: Rx Short period Error.
+  *            @arg CEC_IT_BRE: Rx Bit Rising Error.
+  *            @arg CEC_IT_RXOVR: Rx Overrun.
+  *            @arg CEC_IT_RXEND: End Of Reception.
+  *            @arg CEC_IT_RXBR: Rx-Byte Received 
+  * @retval The new state of CEC_IT (SET or RESET).
+  */
+ITStatus CEC_GetITStatus(uint16_t CEC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+
+  /* Check the parameters */
+  assert_param(IS_CEC_GET_IT(CEC_IT));
+
+  /* Get the CEC IT enable bit status */
+  enablestatus = (CEC->IER & CEC_IT);
+
+  /* Check the status of the specified CEC interrupt */
+  if (((CEC->ISR & CEC_IT) != (uint32_t)RESET) && enablestatus)
+  {
+    /* CEC interrupt is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* CEC interrupt is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the CEC interrupt status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the CEC's interrupt pending bits.
+  * @param  CEC_IT: specifies the CEC interrupt pending bit to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error
+  *            @arg CEC_IT_TXERR: Tx Error
+  *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun
+  *            @arg CEC_IT_TXEND: End of Transmission
+  *            @arg CEC_IT_TXBR: Tx-Byte Request
+  *            @arg CEC_IT_ARBLST: Arbitration Lost
+  *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge
+  *            @arg CEC_IT_LBPE: Rx Long period Error
+  *            @arg CEC_IT_SBPE: Rx Short period Error
+  *            @arg CEC_IT_BRE: Rx Bit Rising Error
+  *            @arg CEC_IT_RXOVR: Rx Overrun
+  *            @arg CEC_IT_RXEND: End Of Reception
+  *            @arg CEC_IT_RXBR: Rx-Byte Received
+  * @retval None
+  */
+void CEC_ClearITPendingBit(uint16_t CEC_IT)
+{
+  assert_param(IS_CEC_IT(CEC_IT));
+
+  /* Clear the selected CEC interrupt pending bits */
+  CEC->ISR = CEC_IT;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_comp.c b/system/src/stm32f0-stdperiph/stm32f0xx_comp.c

new file mode 100644 (file)

index 0000000..6154271
--- /dev/null
+++ b/system/src/stm32f0-stdperiph/stm32f0xx_comp.c
@@ -0,0 +1,408 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_comp.c
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the comparators (COMP1 and COMP2) peripheral
+  *          applicable only on STM32F051 and STM32F072 devices: 
+  *           + Comparators configuration
+  *           + Window mode control
+  *
+  *  @verbatim
+  *
+ ===============================================================================
+                     ##### How to use this driver #####
+ ===============================================================================
+    [..]           
+   
+         The device integrates two analog comparators COMP1 and COMP2:
+         (+) The non inverting input is set to PA1 for COMP1 and to PA3
+             for COMP2.
+  
+         (+) The inverting input can be selected among: DAC1_OUT, DAC2_OUT 
+             1/4 VREFINT, 1/2 VERFINT, 3/4 VREFINT, VREFINT,
+             I/O (PA0 for COMP1 and PA2 for COMP2)
+  
+         (+) The COMP output is internally is available using COMP_GetOutputLevel()
+             and can be set on GPIO pins: PA0, PA6, PA11 for COMP1
+             and PA2, PA7, PA12 for COMP2
+  
+         (+) The COMP output can be redirected to embedded timers (TIM1, TIM2
+             and TIM3)
+  
+         (+) The two comparators COMP1 and COMP2 can be combined in window
+             mode and only COMP1 non inverting (PA1) can be used as non-
+             inverting input.
+  
+         (+) The two comparators COMP1 and COMP2 have interrupt capability 
+             with wake-up from Sleep and Stop modes (through the EXTI controller).
+             COMP1 and COMP2 outputs are internally connected to EXTI Line 21
+             and EXTI Line 22 respectively.
+                   
+
+                     ##### How to configure the comparator #####
+ ===============================================================================
+    [..] 
+           This driver provides functions to configure and program the Comparators 
+           of all STM32F0xx devices.
+             
+    [..]   To use the comparator, perform the following steps:
+  
+         (#) Enable the SYSCFG APB clock to get write access to comparator
+             register using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+  
+         (#) Configure the comparator input in analog mode using GPIO_Init()
+  
+         (#) Configure the comparator output in alternate function mode
+             using GPIO_Init() and use GPIO_PinAFConfig() function to map the
+             comparator output to the GPIO pin
+  
+         (#) Configure the comparator using COMP_Init() function:
+                 (++)  Select the inverting input
+                 (++)  Select the output polarity  
+                 (++)  Select the output redirection
+                 (++)  Select the hysteresis level
+                 (++)  Select the power mode
+    
+         (#) Enable the comparator using COMP_Cmd() function
+  
+         (#) If required enable the COMP interrupt by configuring and enabling
+             EXTI line in Interrupt mode and selecting the desired sensitivity
+             level using EXTI_Init() function. After that enable the comparator
+             interrupt vector using NVIC_Init() function.
+  
+     @endverbatim
+  *    
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_comp.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup COMP 
+  * @brief COMP driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* CSR register Mask */
+#define COMP_CSR_CLEAR_MASK              ((uint32_t)0x00003FFE)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup COMP_Private_Functions
+  * @{
+  */
+
+/** @defgroup COMP_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+               ##### Initialization and Configuration functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+   
+/**
+  * @brief  Deinitializes COMP peripheral registers to their default reset values.
+  * @note   Deinitialization can't be performed if the COMP configuration is locked.
+  *         To unlock the configuration, perform a system reset.
+  * @param  None
+  * @retval None
+  */
+void COMP_DeInit(void)
+{
+  COMP->CSR = ((uint32_t)0x00000000);    /*!< Set COMP_CSR register to reset value */
+}
+
+/**
+  * @brief  Initializes the COMP peripheral according to the specified parameters
+  *         in COMP_InitStruct
+  * @note   If the selected comparator is locked, initialization can't be performed.
+  *         To unlock the configuration, perform a system reset.
+  * @note   By default, PA1 is selected as COMP1 non inverting input.
+  *         To use PA4 as COMP1 non inverting input call COMP_SwitchCmd() after COMP_Init()
+  * @param  COMP_Selection: the selected comparator. 
+  *          This parameter can be one of the following values:
+  *            @arg COMP_Selection_COMP1: COMP1 selected
+  *            @arg COMP_Selection_COMP2: COMP2 selected
+  * @param  COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains 
+  *         the configuration information for the specified COMP peripheral.
+  * @retval None
+  */
+void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+  assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_InvertingInput));
+  assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_Output));
+  assert_param(IS_COMP_OUTPUT_POL(COMP_InitStruct->COMP_OutputPol));
+  assert_param(IS_COMP_HYSTERESIS(COMP_InitStruct->COMP_Hysteresis));
+  assert_param(IS_COMP_MODE(COMP_InitStruct->COMP_Mode));
+
+  /*!< Get the COMP_CSR register value */
+  tmpreg = COMP->CSR;
+
+  /*!< Clear the COMP1SW1, COMPx_IN_SEL, COMPx_OUT_TIM_SEL, COMPx_POL, COMPx_HYST and COMPx_PWR_MODE bits */ 
+  tmpreg &= (uint32_t) ~(COMP_CSR_CLEAR_MASK<<COMP_Selection);
+
+  /*!< Configure COMP: inverting input, output redirection, hysteresis value and power mode */
+  /*!< Set COMPxINSEL bits according to COMP_InitStruct->COMP_InvertingInput value */
+  /*!< Set COMPxOUTSEL bits according to COMP_InitStruct->COMP_Output value */
+  /*!< Set COMPxPOL bit according to COMP_InitStruct->COMP_OutputPol value */
+  /*!< Set COMPxHYST bits according to COMP_InitStruct->COMP_Hysteresis value */
+  /*!< Set COMPxMODE bits according to COMP_InitStruct->COMP_Mode value */   
+  tmpreg |= (uint32_t)((COMP_InitStruct->COMP_InvertingInput | COMP_InitStruct->COMP_Output |
+                       COMP_InitStruct->COMP_OutputPol | COMP_InitStruct->COMP_Hysteresis |
+                       COMP_InitStruct->COMP_Mode)<<COMP_Selection);
+
+  /*!< Write to COMP_CSR register */
+  COMP->CSR = tmpreg;  
+}
+
+/**
+  * @brief  Fills each COMP_InitStruct member with its default value.
+  * @param  COMP_InitStruct: pointer to an COMP_InitTypeDef structure which will 
+  *         be initialized.
+  * @retval None
+  */
+void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct)
+{
+  COMP_InitStruct->COMP_InvertingInput = COMP_InvertingInput_1_4VREFINT;
+  COMP_InitStruct->COMP_Output = COMP_Output_None;
+  COMP_InitStruct->COMP_OutputPol = COMP_OutputPol_NonInverted;
+  COMP_InitStruct->COMP_Hysteresis = COMP_Hysteresis_No;
+  COMP_InitStruct->COMP_Mode = COMP_Mode_UltraLowPower;
+}
+
+/**
+  * @brief  Enable or disable the COMP peripheral.
+  * @note   If the selected comparator is locked, enable/disable can't be performed.
+  *         To unlock the configuration, perform a system reset.
+  * @param  COMP_Selection: the selected comparator.
+  *          This parameter can be one of the following values:
+  *            @arg COMP_Selection_COMP1: COMP1 selected
+  *            @arg COMP_Selection_COMP2: COMP2 selected
+  * @param  NewState: new state of the COMP peripheral.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   When enabled, the comparator compares the non inverting input with 
+  *         the inverting input and the comparison result is available on comparator output.
+  * @note   When disabled, the comparator doesn't perform comparison and the 
+  *         output level is low.
+  * @retval None
+  */
+void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected COMP peripheral */
+    COMP->CSR |= (uint32_t) (1<<COMP_Selection);
+  }
+  else
+  {
+    /* Disable the selected COMP peripheral  */
+    COMP->CSR &= (uint32_t)(~((uint32_t)1<<COMP_Selection));
+  }
+}
+
+/**
+  * @brief  Close or Open the SW1 switch.
+  * @note   This switch is solely intended to redirect signals onto high
+  *         impedance input, such as COMP1 non-inverting input (highly resistive switch)
+  * @param  NewState: New state of the analog switch.
+  *          This parameter can be: ENABLE or DISABLE. 
+  * @note   When enabled, the SW1 is closed; PA1 is connected to PA4
+  * @note   When disabled, the SW1 switch is open; PA1 is disconnected from PA4
+  * @retval None
+  */
+void COMP_SwitchCmd(FunctionalState NewState)
+{
+  /* Check the parameter */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Close SW1 switch */
+    COMP->CSR |= (uint32_t) (COMP_CSR_COMP1SW1);
+  }
+  else
+  {
+    /* Open SW1 switch */
+    COMP->CSR &= (uint32_t)(~COMP_CSR_COMP1SW1);
+  }
+}
+
+/**
+  * @brief  Return the output level (high or low) of the selected comparator. 
+  * @note   The output level depends on the selected polarity.
+  * @note   If the polarity is not inverted:
+  *          - Comparator output is low when the non-inverting input is at a lower
+  *            voltage than the inverting input
+  *          - Comparator output is high when the non-inverting input is at a higher
+  *            voltage than the inverting input
+  * @note   If the polarity is inverted:
+  *          - Comparator output is high when the non-inverting input is at a lower
+  *            voltage than the inverting input
+  *          - Comparator output is low when the non-inverting input is at a higher
+  *            voltage than the inverting input
+  * @param  COMP_Selection: the selected comparator. 
+  *          This parameter can be one of the following values:
+  *            @arg COMP_Selection_COMP1: COMP1 selected
+  *            @arg COMP_Selection_COMP2: COMP2 selected  
+  * @retval Returns the selected comparator output level: low or high.
+  *       
+  */
+uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection)
+{
+  uint32_t compout = 0x0;
+
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+
+  /* Check if selected comparator output is high */
+  if ((COMP->CSR & (COMP_CSR_COMP1OUT<<COMP_Selection)) != 0)
+  {
+    compout = COMP_OutputLevel_High;
+  }
+  else
+  {
+    compout = COMP_OutputLevel_Low;
+  }
+
+  /* Return the comparator output level */
+  return (uint32_t)(compout);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Group2 Window mode control function
+ *  @brief   Window mode control function 
+ *
+@verbatim   
+ ===============================================================================
+                     ##### Window mode control function #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the window mode.
+  * @note   In window mode, COMP1 and COMP2 non inverting inputs are connected
+  *         together and only COMP1 non inverting input (PA1) can be used.
+  * @param  NewState: new state of the window mode.
+  *          This parameter can be :
+  *           @arg ENABLE: COMP1 and COMP2 non inverting inputs are connected together.
+  *           @arg DISABLE: OMP1 and COMP2 non inverting inputs are disconnected.
+  * @retval None
+  */
+void COMP_WindowCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the window mode */
+    COMP->CSR |= (uint32_t) COMP_CSR_WNDWEN;
+  }
+  else
+  {
+    /* Disable the window mode */
+    COMP->CSR &= (uint32_t)(~COMP_CSR_WNDWEN);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Group3 COMP configuration locking function
+ *  @brief   COMP1 and COMP2 configuration locking function
+ *           COMP1 and COMP2 configuration can be locked each separately.
+ *           Unlocking is performed by system reset.
+ *
+@verbatim   
+ ===============================================================================
+                     ##### Configuration Lock function #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Lock the selected comparator (COMP1/COMP2) configuration.
+  * @note   Locking the configuration means that all control bits are read-only.
+  *         To unlock the comparator configuration, perform a system reset.
+  * @param  COMP_Selection: selects the comparator to be locked 
+  *          This parameter can be a value of the following values:
+  *            @arg COMP_Selection_COMP1: COMP1 configuration is locked.
+  *            @arg COMP_Selection_COMP2: COMP2 configuration is locked.  
+  * @retval None
+  */
+void COMP_LockConfig(uint32_t COMP_Selection)
+{
+  /* Check the parameter */
+  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+
+  /* Set the lock bit corresponding to selected comparator */
+  COMP->CSR |= (uint32_t) (COMP_CSR_COMP1LOCK<<COMP_Selection);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_crc.c b/system/src/stm32f0-stdperiph/stm32f0xx_crc.c

new file mode 100644 (file)

index 0000000..fac544b
--- /dev/null
+++ b/system/src/stm32f0-stdperiph/stm32f0xx_crc.c
@@ -0,0 +1,361 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_crc.c
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of CRC computation unit peripheral:
+  *            + Configuration of the CRC computation unit
+  *            + CRC computation of one/many 32-bit data
+  *            + CRC Independent register (IDR) access
+  *
+  *  @verbatim
+ ===============================================================================
+                     ##### How to use this driver #####
+ ===============================================================================
+    [..]
+    
+         (+) Enable CRC AHB clock using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_CRC, ENABLE)
+             function
+         (+) If required, select the reverse operation on input data 
+             using CRC_ReverseInputDataSelect()  
+         (+) If required, enable the reverse operation on output data
+             using CRC_ReverseOutputDataCmd(Enable)
+         (+) use CRC_CalcCRC() function to compute the CRC of a 32-bit data
+             or use CRC_CalcBlockCRC() function to compute the CRC if a 32-bit 
+             data buffer
+            (@) To compute the CRC of a new data use CRC_ResetDR() to reset
+                 the CRC computation unit before starting the computation
+                 otherwise you can get wrong CRC values.
+      
+     @endverbatim
+  *  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_crc.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CRC 
+  * @brief CRC driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup CRC_Private_Functions
+  * @{
+  */
+
+/** @defgroup CRC_Group1 Configuration of the CRC computation unit functions
+ *  @brief   Configuration of the CRC computation unit functions 
+ *
+@verbatim
+ ===============================================================================
+                     ##### CRC configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes CRC peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void CRC_DeInit(void)
+{
+  /* Set DR register to reset value */
+  CRC->DR = 0xFFFFFFFF;
+  
+  /* Set the POL register to the reset value: 0x04C11DB7 */
+  CRC->POL = 0x04C11DB7;
+  
+  /* Reset IDR register */
+  CRC->IDR = 0x00;
+  
+  /* Set INIT register to reset value */
+  CRC->INIT = 0xFFFFFFFF;
+  
+  /* Reset the CRC calculation unit */
+  CRC->CR = CRC_CR_RESET;
+}
+
+/**
+  * @brief  Resets the CRC calculation unit and sets INIT register content in DR register.
+  * @param  None
+  * @retval None
+  */
+void CRC_ResetDR(void)
+{
+  /* Reset CRC generator */
+  CRC->CR |= CRC_CR_RESET;
+}
+
+/**
+  * @brief  Selects the polynomial size. This function is only applicable for 
+  *         STM32F072 devices.
+  * @param  CRC_PolSize: Specifies the polynomial size.
+  *         This parameter can be:
+  *          @arg CRC_PolSize_7: 7-bit polynomial for CRC calculation
+  *          @arg CRC_PolSize_8: 8-bit polynomial for CRC calculation
+  *          @arg CRC_PolSize_16: 16-bit polynomial for CRC calculation
+  *          @arg CRC_PolSize_32: 32-bit polynomial for CRC calculation
+  * @retval None
+  */
+void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize)
+{
+  uint32_t tmpcr = 0;
+
+  /* Check the parameter */
+  assert_param(IS_CRC_POL_SIZE(CRC_PolSize));
+
+  /* Get CR register value */
+  tmpcr = CRC->CR;
+
+  /* Reset POL_SIZE bits */
+  tmpcr &= (uint32_t)~((uint32_t)CRC_CR_POLSIZE);
+  /* Set the polynomial size */
+  tmpcr |= (uint32_t)CRC_PolSize;
+
+  /* Write to CR register */
+  CRC->CR = (uint32_t)tmpcr;
+}
+
+/**
+  * @brief  Selects the reverse operation to be performed on input data.
+  * @param  CRC_ReverseInputData: Specifies the reverse operation on input data.
+  *          This parameter can be:
+  *            @arg CRC_ReverseInputData_No: No reverse operation is performed
+  *            @arg CRC_ReverseInputData_8bits: reverse operation performed on 8 bits
+  *            @arg CRC_ReverseInputData_16bits: reverse operation performed on 16 bits
+  *            @arg CRC_ReverseInputData_32bits: reverse operation performed on 32 bits
+  * @retval None
+  */
+void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData)
+{
+  uint32_t tmpcr = 0;
+
+  /* Check the parameter */
+  assert_param(IS_CRC_REVERSE_INPUT_DATA(CRC_ReverseInputData));
+
+  /* Get CR register value */
+  tmpcr = CRC->CR;
+
+  /* Reset REV_IN bits */
+  tmpcr &= (uint32_t)~((uint32_t)CRC_CR_REV_IN);
+  /* Set the reverse operation */
+  tmpcr |= (uint32_t)CRC_ReverseInputData;
+
+  /* Write to CR register */
+  CRC->CR = (uint32_t)tmpcr;
+}
+
+/**
+  * @brief  Enables or disable the reverse operation on output data.
+  *         The reverse operation on output data is performed on 32-bit.
+  * @param  NewState: new state of the reverse operation on output data.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CRC_ReverseOutputDataCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable reverse operation on output data */
+    CRC->CR |= CRC_CR_REV_OUT;
+  }
+  else
+  {
+    /* Disable reverse operation on output data */
+    CRC->CR &= (uint32_t)~((uint32_t)CRC_CR_REV_OUT);
+  }
+}
+
+/**
+  * @brief  Initializes the INIT register.
+  * @note   After resetting CRC calculation unit, CRC_InitValue is stored in DR register
+  * @param  CRC_InitValue: Programmable initial CRC value
+  * @retval None
+  */
+void CRC_SetInitRegister(uint32_t CRC_InitValue)
+{
+  CRC->INIT = CRC_InitValue;
+}
+
+/**
+  * @brief  Initializes the polynomail coefficients. This function is only 
+  *         applicable for STM32F072 devices.
+  * @param  CRC_Pol: Polynomial to be used for CRC calculation.
+  * @retval None
+  */
+void CRC_SetPolynomial(uint32_t CRC_Pol)
+{
+  CRC->POL = CRC_Pol;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Group2 CRC computation of one/many 32-bit data functions
+ *  @brief   CRC computation of one/many 32-bit data functions
+ *
+@verbatim
+ ===============================================================================
+                     ##### CRC computation functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Computes the 32-bit CRC of a given data word(32-bit).
+  * @param  CRC_Data: data word(32-bit) to compute its CRC
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_CalcCRC(uint32_t CRC_Data)
+{
+  CRC->DR = CRC_Data;
+  
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Computes the 16-bit CRC of a given 16-bit data. This function is only 
+  *         applicable for STM32F072 devices.
+  * @param  CRC_Data: data half-word(16-bit) to compute its CRC
+  * @retval 16-bit CRC
+  */
+uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data)
+{
+  *(uint16_t*)(CRC_BASE) = (uint16_t) CRC_Data;
+  
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Computes the 8-bit CRC of a given 8-bit data. This function is only 
+  *         applicable for STM32F072 devices.
+  * @param  CRC_Data: 8-bit data to compute its CRC
+  * @retval 8-bit CRC
+  */
+uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data)
+{
+  *(uint8_t*)(CRC_BASE) = (uint8_t) CRC_Data;
+
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Computes the 32-bit CRC of a given buffer of data word(32-bit).
+  * @param  pBuffer: pointer to the buffer containing the data to be computed
+  * @param  BufferLength: length of the buffer to be computed
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
+{
+  uint32_t index = 0;
+  
+  for(index = 0; index < BufferLength; index++)
+  {
+    CRC->DR = pBuffer[index];
+  }
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Returns the current CRC value.
+  * @param  None
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_GetCRC(void)
+{
+  return (CRC->DR);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Group3 CRC Independent Register (IDR) access functions
+ *  @brief   CRC Independent Register (IDR) access (write/read) functions
+ *
+@verbatim
+ ===============================================================================
+           ##### CRC Independent Register (IDR) access functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Stores an 8-bit data in the Independent Data(ID) register.
+  * @param  CRC_IDValue: 8-bit value to be stored in the ID register                                   
+  * @retval None
+  */
+void CRC_SetIDRegister(uint8_t CRC_IDValue)
+{
+  CRC->IDR = CRC_IDValue;
+}
+
+/**
+  * @brief  Returns the 8-bit data stored in the Independent Data(ID) register
+  * @param  None
+  * @retval 8-bit value of the ID register 
+  */
+uint8_t CRC_GetIDRegister(void)
+{
+  return (CRC->IDR);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_crs.c b/system/src/stm32f0-stdperiph/stm32f0xx_crs.c

new file mode 100644 (file)

index 0000000..2c21ba6
--- /dev/null
+++ b/system/src/stm32f0-stdperiph/stm32f0xx_crs.c
@@ -0,0 +1,466 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_crs.c
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of CRS peripheral applicable only on STM32F042 and 
+  *          STM32F072 devices:
+  *            + Configuration of the CRS peripheral
+  *            + Interrupts and flags management
+  *              
+  *
+  *  @verbatim
+ ===============================================================================
+                     ##### How to use this driver #####
+ ===============================================================================
+    [..]
+    
+         (+) Enable CRS AHB clock using RCC_APB1eriphClockCmd(RCC_APB1Periph_CRS, ENABLE)
+             function
+
+      
+     @endverbatim
+  *  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_crs.h"
+#include "stm32f0xx_rcc.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CRS 
+  * @brief CRS driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* CRS Flag Mask */
+#define FLAG_MASK                 ((uint32_t)0x700)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup CRS_Private_Functions
+  * @{
+  */
+
+/** @defgroup CRS_Group1 Configuration of the CRS functions
+ *  @brief   Configuration of the CRS  functions 
+ *
+@verbatim
+ ===============================================================================
+                     ##### CRS configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes CRS peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void CRS_DeInit(void)
+{
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_CRS, ENABLE);
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_CRS, DISABLE);
+}
+
+/**
+  * @brief  Adjusts the Internal High Speed 48 oscillator (HSI 48) calibration value.
+  * @note   The calibration is used to compensate for the variations in voltage
+  *         and temperature that influence the frequency of the internal HSI48 RC.
+  * @note   This function can be called only when the AUTOTRIMEN bit is reset.
+  * @param  CRS_HSI48CalibrationValue: 
+  * @retval None
+  */
+void CRS_AdjustHSI48CalibrationValue(uint8_t CRS_HSI48CalibrationValue)
+{
+  /* Clear TRIM[5:0] bits */
+  CRS->CR &= ~CRS_CR_TRIM;
+  
+  /* Set the TRIM[5:0] bits according to CRS_HSI48CalibrationValue value */
+  CRS->CR |= (uint32_t)((uint32_t)CRS_HSI48CalibrationValue << 8);
+
+}
+
+/**
+  * @brief  Enables or disables the oscillator clock for frequency error counter.
+  * @note   when the CEN bit is set the CRS_CFGR register becomes write-protected.
+  * @param  NewState: new state of the frequency error counter.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CRS_FrequencyErrorCounterCmd(FunctionalState NewState)
+{
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+     CRS->CR |= CRS_CR_CEN;
+  }
+  else
+  {
+    CRS->CR &= ~CRS_CR_CEN;
+  }
+}
+
+/**
+  * @brief  Enables or disables the automatic hardware adjustement of TRIM bits.
+  * @note   When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
+  * @param  NewState: new state of the automatic trimming.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CRS_AutomaticCalibrationCmd(FunctionalState NewState)
+{
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    CRS->CR |= CRS_CR_AUTOTRIMEN;
+  }
+else
+  {
+    CRS->CR &= ~CRS_CR_AUTOTRIMEN;
+  }
+}
+
+/**
+  * @brief  Generate the software synchronization event
+  * @param  None
+  * @retval None
+  */
+void CRS_SoftwareSynchronizationGenerate(void)
+{
+  CRS->CR |= CRS_CR_SWSYNC;
+}
+
+/**
+  * @brief  Adjusts the Internal High Speed 48 oscillator (HSI 48) calibration value.
+  * @note   The calibration is used to compensate for the variations in voltage
+  *         and temperature that influence the frequency of the internal HSI48 RC.
+  * @note   This function can be called only when the CEN bit is reset.
+  * @param  CRS_ReloadValue: specifies the HSI calibration trimming value.
+  *          This parameter must be a number between 0 and .
+  * @retval None
+  */
+void CRS_FrequencyErrorCounterReload(uint32_t CRS_ReloadValue)
+{
+ 
+  /* Clear RELOAD[15:0] bits */
+  CRS->CFGR &= ~CRS_CFGR_RELOAD;
+  
+  /* Set the RELOAD[15:0] bits according to CRS_ReloadValue value */
+  CRS->CFGR |= (uint32_t)CRS_ReloadValue;
+
+}
+
+/**
+  * @brief  
+  * @note   This function can be called only when the CEN bit is reset.
+  * @param  CRS_ErrorLimitValue: specifies the HSI calibration trimming value.
+  *          This parameter must be a number between 0 and .
+  * @retval None
+  */
+void CRS_FrequencyErrorLimitConfig(uint8_t CRS_ErrorLimitValue)
+{
+  /* Clear FELIM[7:0] bits */
+  CRS->CFGR &= ~CRS_CFGR_FELIM;
+  
+  /* Set the FELIM[7:0] bits according to CRS_ErrorLimitValue value */
+  CRS->CFGR |= (uint32_t)CRS_ErrorLimitValue;
+}
+
+/**
+  * @brief  
+  * @note   This function can be called only when the CEN bit is reset.
+  * @param  CRS_Prescaler: specifies the HSI calibration trimming value.
+  *          This parameter can be one of the following values:
+  *            @arg CRS_SYNC_Div1:   
+  *            @arg CRS_SYNC_Div2:   
+  *            @arg CRS_SYNC_Div4:   
+  *            @arg CRS_SYNC_Div8:   
+  *            @arg CRS_SYNC_Div16:  
+  *            @arg CRS_SYNC_Div32:  
+  *            @arg CRS_SYNC_Div64: 
+  *            @arg CRS_SYNC_Div128: 
+  * @retval None
+  */
+void CRS_SynchronizationPrescalerConfig(uint32_t CRS_Prescaler)
+{
+  /* Check the parameters */
+  assert_param(IS_CRS_SYNC_DIV(CRS_Prescaler));
+  
+  /* Clear SYNCDIV[2:0] bits */
+  CRS->CFGR &= ~CRS_CFGR_SYNCDIV;
+  
+  /* Set the CRS_CFGR_SYNCDIV[2:0] bits according to CRS_Prescaler value */
+  CRS->CFGR |= CRS_Prescaler;
+}
+
+/**
+  * @brief  
+  * @note   This function can be called only when the CEN bit is reset.
+  * @param  CRS_Source: .
+  *          This parameter can be one of the following values:
+  *            @arg CRS_SYNCSource_GPIO:   
+  *            @arg CRS_SYNCSource_LSE:   
+  *            @arg CRS_SYNCSource_USB:   
+  * @retval None
+  */
+void CRS_SynchronizationSourceConfig(uint32_t CRS_Source)
+{
+  /* Check the parameters */
+  assert_param(IS_CRS_SYNC_SOURCE(CRS_Source));
+  
+  /* Clear SYNCSRC[1:0] bits */
+  CRS->CFGR &= ~CRS_CFGR_SYNCSRC;
+  
+  /* Set the SYNCSRC[1:0] bits according to CRS_Source value */
+  CRS->CFGR |= CRS_Source;
+}
+
+/**
+  * @brief  
+  * @note   This function can be called only when the CEN bit is reset.
+  * @param  CRS_Polarity: .
+  *          This parameter can be one of the following values:
+  *            @arg CRS_SYNCPolarity_Rising:   
+  *            @arg CRS_SYNCPolarity_Falling:   
+  * @retval None
+  */
+void CRS_SynchronizationPolarityConfig(uint32_t CRS_Polarity)
+{
+  /* Check the parameters */
+  assert_param(IS_CRS_SYNC_POLARITY(CRS_Polarity));
+  
+  /* Clear SYNCSPOL bit */
+  CRS->CFGR &= ~CRS_CFGR_SYNCPOL;
+  
+  /* Set the SYNCSPOL bits according to CRS_Polarity value */
+  CRS->CFGR |= CRS_Polarity;
+}
+
+/**
+  * @brief  Returns the Relaod value.
+  * @param  None
+  * @retval The reload value 
+  */
+uint32_t CRS_GetReloadValue(void)
+{
+  return ((uint32_t)(CRS->CFGR & CRS_CFGR_RELOAD));
+}
+
+/**
+  * @brief  Returns the HSI48 Calibration value.
+  * @param  None
+  * @retval The reload value 
+  */
+uint32_t CRS_GetHSI48CalibrationValue(void)
+{
+  return (((uint32_t)(CRS->CR & CRS_CR_TRIM)) >> 8);
+}
+
+/**
+  * @brief  Returns the frequency error capture.
+  * @param  None
+  * @retval The frequency error capture value 
+  */
+uint32_t CRS_GetFrequencyErrorValue(void)
+{
+  return ((uint32_t)(CRS->ISR & CRS_ISR_FECAP));
+}
+
+/**
+  * @brief  Returns the frequency error direction.
+  * @param  None
+  * @retval The frequency error direction. The returned value can be one 
+  *         of the following values:
+  *           - 0x00: Up counting
+  *           - 0x8000: Down counting   
+  */
+uint32_t CRS_GetFrequencyErrorDirection(void)
+{
+  return ((uint32_t)(CRS->ISR & CRS_ISR_FEDIR));
+}
+
+/** @defgroup CRS_Group2 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions 
+ *
+@verbatim
+ ===============================================================================
+             ##### Interrupts and flags management functions #####
+ ===============================================================================
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Enables or disables the specified CRS interrupts.
+  * @param  CRS_IT: specifies the RCC interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *              @arg CRS_IT_SYNCOK: 
+  *              @arg CRS_IT_SYNCWARN: 
+  *              @arg CRS_IT_ERR: 
+  *              @arg CRS_IT_ESYNC: 
+  * @param  NewState: new state of the specified CRS interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CRS_ITConfig(uint32_t CRS_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_CRS_IT(CRS_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    CRS->CR |= CRS_IT;
+  }
+  else
+  {
+    CRS->CR &= ~CRS_IT;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified CRS flag is set or not.
+  * @param  CRS_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *              @arg CRS_FLAG_SYNCOK: 
+  *              @arg CRS_FLAG_SYNCWARN: 
+  *              @arg CRS_FLAG_ERR: 
+  *              @arg CRS_FLAG_ESYNC:   
+  *              @arg CRS_FLAG_TRIMOVF: 
+  *              @arg CRS_FLAG_SYNCERR: 
+  *              @arg CRS_FLAG_SYNCMISS: 
+  * @retval The new state of CRS_FLAG (SET or RESET).
+  */
+FlagStatus CRS_GetFlagStatus(uint32_t CRS_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_CRS_FLAG(CRS_FLAG));
+
+  return ((FlagStatus)(CRS->ISR & CRS_FLAG));
+}
+
+/**
+  * @brief  Clears the CRS specified FLAG.
+  * @param  CRS_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *              @arg CRS_FLAG_SYNCOK: 
+  *              @arg CRS_FLAG_SYNCWARN: 
+  *              @arg CRS_FLAG_ERR: 
+  *              @arg CRS_FLAG_ESYNC:   
+  *              @arg CRS_FLAG_TRIMOVF: 
+  *              @arg CRS_FLAG_SYNCERR: 
+  *              @arg CRS_FLAG_SYNCMISS: 
+  * @retval None
+  */
+void CRS_ClearFlag(uint32_t CRS_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_CRS_FLAG(CRS_FLAG));
+  
+  if ((CRS_FLAG & FLAG_MASK)!= 0)
+  {
+    CRS->ICR |= CRS_ICR_ERRC;  
+  }
+  else
+  {
+    CRS->ICR |= CRS_FLAG;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified CRS IT pending bit is set or not.
+  * @param  CRS_IT: specifies the IT pending bit to check.
+  *          This parameter can be one of the following values:
+  *              @arg CRS_IT_SYNCOK: 
+  *              @arg CRS_IT_SYNCWARN: 
+  *              @arg CRS_IT_ERR: 
+  *              @arg CRS_IT_ESYNC:   
+  *              @arg CRS_IT_TRIMOVF: 
+  *              @arg CRS_IT_SYNCERR: 
+  *              @arg CRS_IT_SYNCMISS: 
+  * @retval The new state of CRS_IT (SET or RESET).
+  */
+ITStatus CRS_GetITStatus(uint32_t CRS_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_CRS_GET_IT(CRS_IT));
+
+  return ((ITStatus)(CRS->ISR & CRS_IT));
+}
+
+/**
+  * @brief  Clears the CRS specified IT pending bi.
+  * @param  CRS_FLAG: specifies the IT pending bi to clear.
+  *          This parameter can be one of the following values:
+  *              @arg CRS_IT_SYNCOK: 
+  *              @arg CRS_IT_SYNCWARN: 
+  *              @arg CRS_IT_ERR: 
+  *              @arg CRS_IT_ESYNC:   
+  *              @arg CRS_IT_TRIMOVF: 
+  *              @arg CRS_IT_SYNCERR: 
+  *              @arg CRS_IT_SYNCMISS: 
+  * @retval None
+  */
+void CRS_ClearITPendingBit(uint32_t CRS_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_CRS_CLEAR_IT(CRS_IT));
+  
+  if ((CRS_IT & FLAG_MASK)!= 0)
+  {
+    CRS->ICR |= CRS_ICR_ERRC;  
+  }
+  else
+  {
+    CRS->ICR |= CRS_IT;
+  }
+}
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_dac.c b/system/src/stm32f0-stdperiph/stm32f0xx_dac.c

new file mode 100644 (file)

index 0000000..afb5b97
--- /dev/null
+++ b/system/src/stm32f0-stdperiph/stm32f0xx_dac.c
@@ -0,0 +1,692 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_dac.c
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Digital-to-Analog Converter (DAC) peripheral
+  *          applicable only on STM32F051 and STM32F072 devices:
+  *           + DAC channel configuration: trigger, output buffer, data format
+  *           + DMA management
+  *           + Interrupts and flags management
+  *
+  *  @verbatim
+  *
+ ===============================================================================
+                        ##### DAC Peripheral features #####
+ ===============================================================================
+    [..] The device integrates two 12-bit Digital Analog Converters refered as
+         DAC channel1 with DAC_OUT1 (PA4) and DAC_OUT2 (PA5) as outputs.
+  
+    [..] Digital to Analog conversion can be non-triggered using DAC_Trigger_None
+         and DAC_OUTx is available once writing to DHRx register using 
+         DAC_SetChannel1Data() or DAC_SetChannel2Data() 
+  
+    [..] Digital to Analog conversion can be triggered by:
+         (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
+             The used pin (GPIOx_Pin9) must be configured in input mode.
+  
+         (#) Timers TRGO: TIM2, TIM3,TIM7, TIM6 and TIM15 
+             (DAC_Trigger_T2_TRGO, DAC_Trigger_T3_TRGO...)
+             The timer TRGO event should be selected using TIM_SelectOutputTrigger()
+  
+         (#) Software using DAC_Trigger_Software
+  
+    [..] Each DAC integrates an output buffer that can be used to 
+         reduce the output impedance, and to drive external loads directly
+         without having to add an external operational amplifier.
+         To enable the output buffer use  
+         DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+  
+    [..] Refer to the device datasheet for more details about output impedance
+         value with and without output buffer.
+         
+    [..] DAC wave generation feature
+         Both DAC channels can be used to generate
+             1- Noise wave using DAC_WaveGeneration_Noise
+             2- Triangle wave using DAC_WaveGeneration_Triangle
+  
+    [..] The DAC data format can be:
+         (#) 8-bit right alignment using DAC_Align_8b_R
+         (#) 12-bit left alignment using DAC_Align_12b_L
+         (#) 12-bit right alignment using DAC_Align_12b_R
+  
+    [..] The analog output voltage on each DAC channel pin is determined
+         by the following equation: DAC_OUTx = VREF+ * DOR / 4095
+         with  DOR is the Data Output Register
+         VEF+ is the input voltage reference (refer to the device datasheet)
+         e.g. To set DAC_OUT1 to 0.7V, use
+         DAC_SetChannel1Data(DAC_Align_12b_R, 868);
+         Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
+  
+    [..] A DMA1 request can be generated when an external trigger (but not
+         a software trigger) occurs if DMA1 requests are enabled using
+         DAC_DMACmd()
+         DMA1 requests are mapped as following:
+         (+) DAC channel1 is mapped on DMA1 channel3 which must be already 
+             configured
+         (+) DAC channel2 is mapped on DMA1 channel4 which must be already 
+             configured
+    
+                      ##### How to use this driver #####
+ ===============================================================================
+    [..]
+         (+) Enable DAC APB1 clock to get write access to DAC registers
+             using RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)
+              
+         (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode
+             using GPIO_Init() function  
+              
+         (+) Configure the DAC channel using DAC_Init()
+              
+         (+) Enable the DAC channel using DAC_Cmd()
+  
+    @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_dac.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DAC 
+  * @brief DAC driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* CR register Mask */
+#define CR_CLEAR_MASK              ((uint32_t)0x00000FFE) /* check the value of the mask */
+
+/* DAC Dual Channels SWTRIG masks */
+#define DUAL_SWTRIG_SET            ((uint32_t)0x00000003) /*!< Only applicable for STM32F072 devices */
+#define DUAL_SWTRIG_RESET          ((uint32_t)0xFFFFFFFC) /*!< Only applicable for STM32F072 devices */
+
+/* DHR registers offsets */
+#define DHR12R1_OFFSET             ((uint32_t)0x00000008)
+#define DHR12R2_OFFSET             ((uint32_t)0x00000014) /*!< Only applicable for STM32F072 devices */
+#define DHR12RD_OFFSET             ((uint32_t)0x00000020) /*!< Only applicable for STM32F072 devices */
+
+/* DOR register offset */
+#define DOR_OFFSET                 ((uint32_t)0x0000002C)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DAC_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup DAC_Group1 DAC channels configuration
+ *  @brief   DAC channels configuration: trigger, output buffer, data format 
+ *
+@verbatim
+ ===============================================================================
+  ##### DAC channels configuration: trigger, output buffer, data format #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the DAC peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void DAC_DeInit(void)
+{
+  /* Enable DAC reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
+  /* Release DAC from reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
+}
+
+/**
+  * @brief  Initializes the DAC peripheral according to the specified parameters
+  *         in the DAC_InitStruct.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *          This parameter can be:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices
+  * @param  DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains
+  *         the configuration information for the  specified DAC channel.
+  * @retval None
+  */
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
+{
+  uint32_t tmpreg1 = 0, tmpreg2 = 0;
+
+  /* Check the DAC parameters */
+  assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
+  assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
+  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
+  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
+
+/*---------------------------- DAC CR Configuration --------------------------*/
+  /* Get the DAC CR value */
+  tmpreg1 = DAC->CR;
+  /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
+  tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
+  /* Configure for the selected DAC channel: buffer output, trigger, 
+     wave generation, mask/amplitude for wave generation */
+  /* Set TSELx and TENx bits according to DAC_Trigger value */
+  /* Set WAVEx bits according to DAC_WaveGeneration value */
+  /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ 
+  /* Set BOFFx bit according to DAC_OutputBuffer value */   
+  tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
+             DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | \
+             DAC_InitStruct->DAC_OutputBuffer);
+  /* Calculate CR register value depending on DAC_Channel */
+  tmpreg1 |= tmpreg2 << DAC_Channel;
+  /* Write to DAC CR */
+  DAC->CR = tmpreg1;
+}
+
+/**
+  * @brief  Fills each DAC_InitStruct member with its default value.
+  * @param  DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will 
+  *         be initialized.
+  * @retval None
+  */
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
+{
+/*--------------- Reset DAC init structure parameters values -----------------*/
+  /* Initialize the DAC_Trigger member */
+  DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
+  
+  /* Initialize the DAC_WaveGeneration member */
+  DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
+  
+  /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
+  DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
+  
+  /* Initialize the DAC_OutputBuffer member */
+  DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+}
+
+/**
+  * @brief  Enables or disables the specified DAC channel.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices
+  * @param  NewState: new state of the DAC channel. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   When the DAC channel is enabled the trigger source can no more be modified.
+  * @retval None
+  */
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC channel */
+    DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
+  }
+  else
+  {
+    /* Disable the selected DAC channel */
+    DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel));
+  }
+}
+
+/**
+  * @brief  Enables or disables the selected DAC channel software trigger.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices
+  * @param  NewState: new state of the selected DAC channel software trigger.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable software trigger for the selected DAC channel */
+    DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
+  }
+  else
+  {
+    /* Disable software trigger for the selected DAC channel */
+    DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
+  }
+}
+
+/**
+  * @brief  Enables or disables simultaneously the two DAC channels software triggers.
+  *         This function is applicable only for STM32F072 devices.  
+  * @param  NewState: new state of the DAC channels software triggers.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable software trigger for both DAC channels */
+    DAC->SWTRIGR |= DUAL_SWTRIG_SET;
+  }
+  else
+  {
+    /* Disable software trigger for both DAC channels */
+    DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
+  }
+}
+
+/**
+  * @brief  Enables or disables the selected DAC channel wave generation.
+  *         This function is applicable only for STM32F072 devices.  
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_Wave: specifies the wave type to enable or disable.
+  *          This parameter can be:
+  *            @arg DAC_Wave_Noise: noise wave generation
+  *            @arg DAC_Wave_Triangle: triangle wave generation
+  * @param  NewState: new state of the selected DAC channel wave generation.
+  *          This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_WAVE(DAC_Wave)); 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected wave generation for the selected DAC channel */
+    DAC->CR |= DAC_Wave << DAC_Channel;
+  }
+  else
+  {
+    /* Disable the selected wave generation for the selected DAC channel */
+    DAC->CR &= ~(DAC_Wave << DAC_Channel);
+  }
+}
+
+/**
+  * @brief  Set the specified data holding register value for DAC channel1.
+  * @param  DAC_Align: Specifies the data alignment for DAC channel1.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Align_8b_R: 8bit right data alignment selected
+  *            @arg DAC_Align_12b_L: 12bit left data alignment selected
+  *            @arg DAC_Align_12b_R: 12bit right data alignment selected
+  * @param  Data: Data to be loaded in the selected data holding register.
+  * @retval None
+  */
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
+{  
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data));
+  
+  tmp = (uint32_t)DAC_BASE; 
+  tmp += DHR12R1_OFFSET + DAC_Align;
+
+  /* Set the DAC channel1 selected data holding register */
+  *(__IO uint32_t *) tmp = Data;
+}
+
+/**
+  * @brief  Sets the specified data holding register value for DAC channel2.
+  *         This function is applicable only for STM32F072 devices.  
+  * @param  DAC_Align: Specifies the data alignment for DAC channel2.
+  *          This parameter can be:
+  *            @arg DAC_Align_8b_R: 8bit right data alignment selected
+  *            @arg DAC_Align_12b_L: 12bit left data alignment selected
+  *            @arg DAC_Align_12b_R: 12bit right data alignment selected
+  * @param  Data: Data to be loaded in the selected data holding register.
+  * @retval None
+  */
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data));
+  
+  tmp = (uint32_t)DAC_BASE;
+  tmp += DHR12R2_OFFSET + DAC_Align;
+
+  /* Set the DAC channel2 selected data holding register */
+  *(__IO uint32_t *)tmp = Data;
+}
+
+/**
+  * @brief  Sets the specified data holding register value for dual channel DAC.
+  *         This function is applicable only for STM32F072 devices.  
+  * @param  DAC_Align: Specifies the data alignment for dual channel DAC.
+  *          This parameter can be:
+  *            @arg DAC_Align_8b_R: 8bit right data alignment selected
+  *            @arg DAC_Align_12b_L: 12bit left data alignment selected
+  *            @arg DAC_Align_12b_R: 12bit right data alignment selected
+  * @param  Data2: Data for DAC Channel2 to be loaded in the selected data holding register.
+  * @param  Data1: Data for DAC Channel1 to be loaded in the selected data  holding register.
+  * @note   In dual mode, a unique register access is required to write in both
+  *          DAC channels at the same time.
+  * @retval None
+  */
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
+{
+  uint32_t data = 0, tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data1));
+  assert_param(IS_DAC_DATA(Data2));
+  
+  /* Calculate and set dual DAC data holding register value */
+  if (DAC_Align == DAC_Align_8b_R)
+  {
+    data = ((uint32_t)Data2 << 8) | Data1; 
+  }
+  else
+  {
+    data = ((uint32_t)Data2 << 16) | Data1;
+  }
+  
+  tmp = (uint32_t)DAC_BASE;
+  tmp += DHR12RD_OFFSET + DAC_Align;
+
+  /* Set the dual DAC selected data holding register */
+  *(__IO uint32_t *)tmp = data;
+}
+
+/**
+  * @brief  Returns the last data output value of the selected DAC channel.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices
+  * @retval The selected DAC channel data output value.
+  */
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  
+  tmp = (uint32_t) DAC_BASE ;
+  tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
+  
+  /* Returns the DAC channel data output register value */
+  return (uint16_t) (*(__IO uint32_t*) tmp);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Group2 DMA management functions
+ *  @brief   DMA management functions
+ *
+@verbatim   
+ ===============================================================================
+                    ##### DMA management functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified DAC channel DMA request.
+  *         When enabled DMA1 is generated when an external trigger (EXTI Line9,
+  *         TIM2, TIM3, TIM6 or TIM15  but not a software trigger) occurs
+  * @param  DAC_Channel: the selected DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices
+  * @param  NewState: new state of the selected DAC channel DMA request.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   The DAC channel1 is mapped on DMA1 channel3 which must be already configured. 
+  * @note   The DAC channel2 is mapped on DMA1 channel4 which must be already configured.  
+  * @retval None
+  */
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC channel DMA request */
+    DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
+  }
+  else
+  {
+    /* Disable the selected DAC channel DMA request */
+    DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Group3 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+ *
+@verbatim   
+ ===============================================================================
+            ##### Interrupts and flags management functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified DAC interrupts.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices
+  * @param  DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. 
+  *          This parameter can be the following values:
+  *            @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
+  * @note   The DMA underrun occurs when a second external trigger arrives before the 
+  *         acknowledgement for the first external trigger is received (first request).
+  * @param  NewState: new state of the specified DAC interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */ 
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)  
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_DAC_IT(DAC_IT)); 
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC interrupts */
+    DAC->CR |=  (DAC_IT << DAC_Channel);
+  }
+  else
+  {
+    /* Disable the selected DAC interrupts */
+    DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
+  }
+}
+
+/**
+  * @brief  Checks whether the specified DAC flag is set or not.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices
+  * @param  DAC_FLAG: specifies the flag to check. 
+  *          This parameter can be only of the following value:
+  *            @arg DAC_FLAG_DMAUDR: DMA underrun flag
+  * @note   The DMA underrun occurs when a second external trigger arrives before the 
+  *         acknowledgement for the first external trigger is received (first request).
+  * @retval The new state of DAC_FLAG (SET or RESET).
+  */
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_FLAG(DAC_FLAG));
+
+  /* Check the status of the specified DAC flag */
+  if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
+  {
+    /* DAC_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DAC_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the DAC_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DAC channel's pending flags.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices
+  * @param  DAC_FLAG: specifies the flag to clear. 
+  *          This parameter can be of the following value:
+  *            @arg DAC_FLAG_DMAUDR: DMA underrun flag                           
+  * @retval None
+  */
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_FLAG(DAC_FLAG));
+
+  /* Clear the selected DAC flags */
+  DAC->SR = (DAC_FLAG << DAC_Channel);
+}
+
+/**
+  * @brief  Checks whether the specified DAC interrupt has occurred or not.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices
+  * @param  DAC_IT: specifies the DAC interrupt source to check. 
+  *          This parameter can be the following values:
+  *            @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
+  * @note   The DMA underrun occurs when a second external trigger arrives before the 
+  *         acknowledgement for the first external trigger is received (first request).
+  * @retval The new state of DAC_IT (SET or RESET).
+  */
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_IT(DAC_IT));
+
+  /* Get the DAC_IT enable bit status */
+  enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
+  
+  /* Check the status of the specified DAC interrupt */
+  if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
+  {
+    /* DAC_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DAC_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the DAC_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DAC channel's interrupt pending bits.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices
+  * @param  DAC_IT: specifies the DAC interrupt pending bit to clear.
+  *          This parameter can be the following values:
+  *            @arg DAC_IT_DMAUDR: DMA underrun interrupt mask                                                    
+  * @retval None
+  */
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_IT(DAC_IT)); 
+
+  /* Clear the selected DAC interrupt pending bits */
+  DAC->SR = (DAC_IT << DAC_Channel);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_dbgmcu.c b/system/src/stm32f0-stdperiph/stm32f0xx_dbgmcu.c

new file mode 100644 (file)

index 0000000..223fdf6
--- /dev/null
+++ b/system/src/stm32f0-stdperiph/stm32f0xx_dbgmcu.c
@@ -0,0 +1,218 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_dbgmcu.c
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Debug MCU (DBGMCU) peripheral:
+  *           + Device and Revision ID management
+  *           + Peripherals Configuration
+  *  @verbatim
+  *  @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_dbgmcu.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DBGMCU 
+  * @brief DBGMCU driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DBGMCU_Private_Functions 
+  * @{
+  */
+  
+
+/** @defgroup DBGMCU_Group1 Device and Revision ID management functions
+ *  @brief   Device and Revision ID management functions
+ *
+@verbatim
+  ==============================================================================
+            ##### Device and Revision ID management functions #####
+  ==============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the device revision identifier.
+  * @param  None
+  * @retval Device revision identifier
+  */
+uint32_t DBGMCU_GetREVID(void)
+{
+   return(DBGMCU->IDCODE >> 16);
+}
+
+/**
+  * @brief  Returns the device identifier.
+  * @param  None
+  * @retval Device identifier
+  */
+uint32_t DBGMCU_GetDEVID(void)
+{
+   return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup DBGMCU_Group2 Peripherals Configuration functions
+ *  @brief   Peripherals Configuration
+ *
+@verbatim
+  ==============================================================================
+               ##### Peripherals Configuration functions #####
+  ==============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures low power mode behavior when the MCU is in Debug mode.
+  * @param  DBGMCU_Periph: specifies the low power mode.
+  *          This parameter can be any combination of the following values:
+  *             @arg DBGMCU_STOP: Keep debugger connection during STOP mode
+  *             @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
+  * @param  NewState: new state of the specified low power mode in Debug mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    DBGMCU->CR |= DBGMCU_Periph;
+  }
+  else
+  {
+    DBGMCU->CR &= ~DBGMCU_Periph;
+  }
+}
+
+
+/**
+  * @brief  Configures APB1 peripheral behavior when the MCU is in Debug mode.
+  * @param  DBGMCU_Periph: specifies the APB1 peripheral.
+  *          This parameter can be any combination of the following values:
+  *             @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted, 
+  *                  not applicable for STM32F030 devices   
+  *             @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
+  *             @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
+  *             @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted, 
+  *                  applicable only for STM32F072 devices               
+  *             @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
+  *             @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped 
+  *                                   when Core is halted.
+  *             @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
+  *             @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
+  *             @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped 
+  *                                             when Core is halted
+  *             @arg DBGMCU_CAN1_STOP: Debug CAN1 stopped when Core is halted, 
+  *                  applicable only for STM32F042 and STM32F072 devices               
+  * @param  NewState: new state of the specified APB1 peripheral in Debug mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    DBGMCU->APB1FZ |= DBGMCU_Periph;
+  }
+  else
+  {
+    DBGMCU->APB1FZ &= ~DBGMCU_Periph;
+  }
+}
+
+/**
+  * @brief  Configures APB2 peripheral behavior when the MCU is in Debug mode.
+  * @param  DBGMCU_Periph: specifies the APB2 peripheral.
+  *          This parameter can be any combination of the following values:
+  *             @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
+  *             @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted
+  *             @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted
+  *             @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted
+  * @param  NewState: new state of the specified APB2 peripheral in Debug mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    DBGMCU->APB2FZ |= DBGMCU_Periph;
+  }
+  else
+  {
+    DBGMCU->APB2FZ &= ~DBGMCU_Periph;
+  }
+}
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_dma.c b/system/src/stm32f0-stdperiph/stm32f0xx_dma.c

new file mode 100644 (file)

index 0000000..ef629e7
--- /dev/null
+++ b/system/src/stm32f0-stdperiph/stm32f0xx_dma.c
@@ -0,0 +1,891 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_dma.c
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Direct Memory Access controller (DMA):
+  *           + Initialization and Configuration
+  *           + Data Counter
+  *           + Interrupts and flags management
+  *
+  *  @verbatim
+  ==============================================================================
+                      ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    (#) Enable The DMA controller clock using 
+        RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) function for DMA1.
+    (#) Enable and configure the peripheral to be connected to the DMA channel
+       (except for internal SRAM / FLASH memories: no initialization is necessary).
+    (#) For a given Channel, program the Source and Destination addresses, 
+        the transfer Direction, the Buffer Size, the Peripheral and Memory 
+        Incrementation mode and Data Size, the Circular or Normal mode, 
+        the channel transfer Priority and the Memory-to-Memory transfer 
+        mode (if needed) using the DMA_Init() function.
+    (#) Enable the NVIC and the corresponding interrupt(s) using the function 
+        DMA_ITConfig() if you need to use DMA interrupts.
+    (#) Enable the DMA channel using the DMA_Cmd() function.
+    (#) Activate the needed channel Request using PPP_DMACmd() function for 
+        any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...) 
+        The function allowing this operation is provided in each PPP peripheral 
+        driver (ie. SPI_DMACmd for SPI peripheral).
+    (#) Optionally, you can configure the number of data to be transferred
+        when the channel is disabled (ie. after each Transfer Complete event
+        or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().
+        And you can get the number of remaining data to be transferred using 
+        the function DMA_GetCurrDataCounter() at run time (when the DMA channel is
+        enabled and running).
+    (#) To control DMA events you can use one of the following two methods:
+        (##) Check on DMA channel flags using the function DMA_GetFlagStatus().
+        (##) Use DMA interrupts through the function DMA_ITConfig() at initialization
+             phase and DMA_GetITStatus() function into interrupt routines in
+             communication phase.
+             After checking on a flag you should clear it using DMA_ClearFlag()
+             function. And after checking on an interrupt event you should 
+             clear it using DMA_ClearITPendingBit() function.
+    @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_dma.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DMA 
+  * @brief DMA driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define CCR_CLEAR_MASK   ((uint32_t)0xFFFF800F) /* DMA Channel config registers Masks */
+#define FLAG_Mask        ((uint32_t)0x10000000) /* DMA2 FLAG mask */
+
+/* DMA1 Channelx interrupt pending bit masks */
+#define DMA1_CHANNEL1_IT_MASK    ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
+#define DMA1_CHANNEL2_IT_MASK    ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
+#define DMA1_CHANNEL3_IT_MASK    ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
+#define DMA1_CHANNEL4_IT_MASK    ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
+#define DMA1_CHANNEL5_IT_MASK    ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
+#define DMA1_CHANNEL6_IT_MASK    ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6)) /*!< Only applicable for STM32F072 and STM32F091 devices */
+#define DMA1_CHANNEL7_IT_MASK    ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7)) /*!< Only applicable for STM32F072 and STM32F091 devices */
+    
+/* DMA2 Channelx interrupt pending bit masks: Only applicable for STM32F091 devices */
+#define DMA2_CHANNEL1_IT_MASK    ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
+#define DMA2_CHANNEL2_IT_MASK    ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
+#define DMA2_CHANNEL3_IT_MASK    ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
+#define DMA2_CHANNEL4_IT_MASK    ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
+#define DMA2_CHANNEL5_IT_MASK    ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DMA_Private_Functions 
+  * @{
+  */
+
+/** @defgroup DMA_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions
+ *
+@verbatim   
+ ===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..] This subsection provides functions allowing to initialize the DMA channel 
+         source and destination addresses, incrementation and data sizes, transfer 
+         direction, buffer size, circular/normal mode selection, memory-to-memory 
+         mode selection and channel priority value.
+    [..] The DMA_Init() function follows the DMA configuration procedures as described 
+         in reference manual (RM0091).
+@endverbatim
+  * @{
+  */
+    
+/**
+  * @brief  Deinitializes the DMAy Channelx registers to their default reset
+  *         values.
+  * @param  DMAy_Channelx: where y can be 1 to select the DMA and 
+  *         x can be 1 to 7 for DMA1 to select the DMA Channel.
+  * @note   Channel 6 and 7 are available only for STM32F072 devices.
+  * @retval None
+  */
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+
+  /* Disable the selected DMAy Channelx */
+  DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
+
+  /* Reset DMAy Channelx control register */
+  DMAy_Channelx->CCR  = 0;
+
+  /* Reset DMAy Channelx remaining bytes register */
+  DMAy_Channelx->CNDTR = 0;
+
+  /* Reset DMAy Channelx peripheral address register */
+  DMAy_Channelx->CPAR  = 0;
+
+  /* Reset DMAy Channelx memory address register */
+  DMAy_Channelx->CMAR = 0;
+
+  if (DMAy_Channelx == DMA1_Channel1)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel1 */
+    DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel2)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel2 */
+    DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel3)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel3 */
+    DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel4)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel4 */
+    DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel5)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel5 */
+    DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel6)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel6 */
+    DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel7)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel7 */
+    DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA2_Channel1)
+  {
+    /* Reset interrupt pending bits for DMA2 Channel1 */
+    DMA2->IFCR |= DMA2_CHANNEL1_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA2_Channel2)
+  {
+    /* Reset interrupt pending bits for DMA2 Channel2 */
+    DMA2->IFCR |= DMA2_CHANNEL2_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA2_Channel3)
+  {
+    /* Reset interrupt pending bits for DMA2 Channel3 */
+    DMA2->IFCR |= DMA2_CHANNEL3_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA2_Channel4)
+  {
+    /* Reset interrupt pending bits for DMA2 Channel4 */
+    DMA2->IFCR |= DMA2_CHANNEL4_IT_MASK;
+  }
+  else
+  { 
+    if (DMAy_Channelx == DMA2_Channel5)
+    {
+      /* Reset interrupt pending bits for DMA2 Channel5 */
+      DMA2->IFCR |= DMA2_CHANNEL5_IT_MASK;
+    }
+  }
+}
+
+/**
+  * @brief  Initializes the DMAy Channelx according to the specified parameters 
+  *         in the DMA_InitStruct.
+  * @param  DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7
+  *         for DMA1 to select the DMA Channel and 1 to 5 for DMA2 to select the DMA Channel.
+  * @note   DMA1 Channel 6 and 7 are available only for STM32F072 and STM32F091 devices. 
+  * @note   DMA2 Channel 1 to 5 are available only for STM32F091 devices.   
+  * @param  DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains
+  *         the configuration information for the specified DMA Channel.
+  * @retval None
+  */
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+  assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
+  assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
+  assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
+  assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
+  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
+  assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
+  assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
+  assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
+  assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
+
+/*--------------------------- DMAy Channelx CCR Configuration ----------------*/
+  /* Get the DMAy_Channelx CCR value */
+  tmpreg = DMAy_Channelx->CCR;
+
+  /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
+  tmpreg &= CCR_CLEAR_MASK;
+
+  /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
+  /* Set DIR bit according to DMA_DIR value */
+  /* Set CIRC bit according to DMA_Mode value */
+  /* Set PINC bit according to DMA_PeripheralInc value */
+  /* Set MINC bit according to DMA_MemoryInc value */
+  /* Set PSIZE bits according to DMA_PeripheralDataSize value */
+  /* Set MSIZE bits according to DMA_MemoryDataSize value */
+  /* Set PL bits according to DMA_Priority value */
+  /* Set the MEM2MEM bit according to DMA_M2M value */
+  tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
+            DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
+            DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
+            DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
+
+  /* Write to DMAy Channelx CCR */
+  DMAy_Channelx->CCR = tmpreg;
+
+/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
+  /* Write to DMAy Channelx CNDTR */
+  DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
+
+/*--------------------------- DMAy Channelx CPAR Configuration ---------------*/
+  /* Write to DMAy Channelx CPAR */
+  DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
+
+/*--------------------------- DMAy Channelx CMAR Configuration ---------------*/
+  /* Write to DMAy Channelx CMAR */
+  DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
+}
+
+/**
+  * @brief  Fills each DMA_InitStruct member with its default value.
+  * @param  DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
+{
+/*-------------- Reset DMA init structure parameters values ------------------*/
+  /* Initialize the DMA_PeripheralBaseAddr member */
+  DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
+  /* Initialize the DMA_MemoryBaseAddr member */
+  DMA_InitStruct->DMA_MemoryBaseAddr = 0;
+  /* Initialize the DMA_DIR member */
+  DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
+  /* Initialize the DMA_BufferSize member */
+  DMA_InitStruct->DMA_BufferSize = 0;
+  /* Initialize the DMA_PeripheralInc member */
+  DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+  /* Initialize the DMA_MemoryInc member */
+  DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
+  /* Initialize the DMA_PeripheralDataSize member */
+  DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+  /* Initialize the DMA_MemoryDataSize member */
+  DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+  /* Initialize the DMA_Mode member */
+  DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
+  /* Initialize the DMA_Priority member */
+  DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
+  /* Initialize the DMA_M2M member */
+  DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
+}
+
+/**
+  * @brief  Enables or disables the specified DMAy Channelx.
+  * @param  DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7
+  *         for DMA1 to select the DMA Channel and 1 to 5 for DMA2 to select the DMA Channel.
+  * @note   DMA1 Channel 6 and 7 are available only for STM32F072 and STM32F091 devices. 
+  * @note   DMA2 Channel 1 to 5 are available only for STM32F091 devices. 
+  * @param  NewState: new state of the DMAy Channelx. 
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMAy Channelx */
+    DMAy_Channelx->CCR |= DMA_CCR_EN;
+  }
+  else
+  {
+    /* Disable the selected DMAy Channelx */
+    DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
+  }
+}
+
+/**
+  * @brief  Configure the DMAx channels remapping.
+  * @param  DMAy: where x can be 1 or 2 to select the DMA peripheral.    
+  * @param  DMAy_CHx_RemapRequest: where y can be 1 or 2 to select the DMA and x can be 1 to 7
+  *         for DMA1 to select the DMA1 Channel and can be 1 to 5 for DMA2 to select the DMA2 Channel.
+  * @note   This function is available only for STM32F091 devices. 
+  * @retval None
+  */
+void DMA_RemapConfig(DMA_TypeDef* DMAy, uint32_t DMAx_CHy_RemapRequest)
+{
+  assert_param(IS_DMA_ALL_LIST(DMAy));
+  
+  if (DMAy == DMA1)
+  {
+    assert_param(IS_DMA1_REMAP(DMAx_CHy_RemapRequest));  
+  }
+  else
+  {
+    assert_param(IS_DMA2_REMAP(DMAx_CHy_RemapRequest)); 
+  }
+
+  DMAy->RMPCR &= ~((uint32_t)0x0F << (uint32_t)((DMAx_CHy_RemapRequest >> 28) * 4)); 
+  DMAy->RMPCR |= (uint32_t)(DMAx_CHy_RemapRequest & 0x0FFFFFFF);  
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Group2 Data Counter functions
+ *  @brief   Data Counter functions 
+ *
+@verbatim
+ ===============================================================================
+                      ##### Data Counter functions #####
+ ===============================================================================
+    [..] This subsection provides function allowing to configure and read the buffer 
+         size (number of data to be transferred).The DMA data counter can be written 
+         only when the DMA channel is disabled (ie. after transfer complete event).
+    [..] The following function can be used to write the Channel data counter value:
+         (+) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t 
+             DataNumber).
+    -@- It is advised to use this function rather than DMA_Init() in situations 
+        where only the Data buffer needs to be reloaded.
+    [..] The DMA data counter can be read to indicate the number of remaining transfers 
+         for the relative DMA channel. This counter is decremented at the end of each 
+         data transfer and when the transfer is complete: 
+         (+) If Normal mode is selected: the counter is set to 0.
+         (+) If Circular mode is selected: the counter is reloaded with the initial 
+         value(configured before enabling the DMA channel).
+    [..] The following function can be used to read the Channel data counter value:
+         (+) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Sets the number of data units in the current DMAy Channelx transfer.
+  * @param  DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7
+  *         for DMA1 to select the DMA Channel and 1 to 5 for DMA2 to select the DMA Channel.
+  * @note   DMA1 Channel 6 and 7 are available only for STM32F072 and STM32F091 devices. 
+  * @note   DMA2 Channel 1 to 5 are available only for STM32F091 devices. 
+  * @param  DataNumber: The number of data units in the current DMAy Channelx
+  *         transfer.
+  * @note   This function can only be used when the DMAy_Channelx is disabled.
+  * @retval None.
+  */
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+
+/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
+  /* Write to DMAy Channelx CNDTR */
+  DMAy_Channelx->CNDTR = DataNumber;
+}
+
+/**
+  * @brief  Returns the number of remaining data units in the current
+  *         DMAy Channelx transfer.
+  * @param  DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7
+  *         for DMA1 to select the DMA Channel and 1 to 5 for DMA2 to select the DMA Channel.
+  * @note   DMA1 Channel 6 and 7 are available only for STM32F072 and STM32F091 devices. 
+  * @note   DMA2 Channel 1 to 5 are available only for STM32F091 devices. 
+  * @retval The number of remaining data units in the current DMAy Channelx
+  *         transfer.
+  */
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+  /* Return the number of remaining data units for DMAy Channelx */
+  return ((uint16_t)(DMAy_Channelx->CNDTR));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Group3 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions 
+ *
+@verbatim
+ ===============================================================================
+          ##### Interrupts and flags management functions #####
+ ===============================================================================
+    [..] This subsection provides functions allowing to configure the DMA Interrupts 
+         sources and check or clear the flags or pending bits status.
+         The user should identify which mode will be used in his application to manage 
+         the DMA controller events: Polling mode or Interrupt mode. 
+  *** Polling Mode ***
+  ====================
+    [..] Each DMA channel can be managed through 4 event Flags:(y : DMA Controller 
+         number  x : DMA channel number ).
+         (#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred.
+         (#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred.
+         (#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred.
+         (#) DMAy_FLAG_GLx : to indicate that at least one of the events described 
+             above occurred.
+    -@- Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the 
+        same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
+    [..]In this Mode it is advised to use the following functions:
+        (+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
+        (+) void DMA_ClearFlag(uint32_t DMA_FLAG);
+
+  *** Interrupt Mode ***
+  ======================
+    [..] Each DMA channel can be managed through 4 Interrupts:
+    (+) Interrupt Source
+       (##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete 
+            event.
+       (##) DMA_IT_HT : specifies the interrupt source for the Half-transfer Complete 
+            event.
+       (##) DMA_IT_TE : specifies the interrupt source for the transfer errors event.
+       (##) DMA_IT_GL : to indicate that at least one of the interrupts described 
+            above occurred.
+    -@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of 
+        the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE).
+    [..]In this Mode it is advised to use the following functions:
+        (+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, 
+            FunctionalState NewState);
+        (+) ITStatus DMA_GetITStatus(uint32_t DMA_IT);
+        (+) void DMA_ClearITPendingBit(uint32_t DMA_IT);
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified DMAy Channelx interrupts.
+  * @param  DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7
+  *         for DMA1 to select the DMA Channel and 1 to 5 for DMA2 to select the DMA Channel.
+  * @note   DMA1 Channel 6 and 7 are available only for STM32F072 and STM32F091 devices. 
+  * @note   DMA2 Channel 1 to 5 are available only for STM32F091 devices.  
+  * @param  DMA_IT: specifies the DMA interrupts sources to be enabled
+  *         or disabled. 
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_IT_TC: Transfer complete interrupt mask
+  *            @arg DMA_IT_HT: Half transfer interrupt mask
+  *            @arg DMA_IT_TE: Transfer error interrupt mask
+  * @param  NewState: new state of the specified DMA interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+  assert_param(IS_DMA_CONFIG_IT(DMA_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA interrupts */
+    DMAy_Channelx->CCR |= DMA_IT;
+  }
+  else
+  {
+    /* Disable the selected DMA interrupts */
+    DMAy_Channelx->CCR &= ~DMA_IT;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified DMAy Channelx flag is set or not.
+  * @param  DMA_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
+  *            @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
+  *            @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
+  *            @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
+  *            @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
+  *            @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
+  *            @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
+  *            @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
+  *            @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
+  *            @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
+  *            @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
+  *            @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
+  *            @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
+  *            @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
+  *            @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
+  *            @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
+  *            @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
+  *            @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
+  *            @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
+  *            @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
+  *            @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag, applicable only for STM32F072 and STM32FO91 devices.
+  *            @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag, applicable only for STM32F072 and STM32FO91 devices.
+  *            @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag, applicable only for STM32F072 and STM32FO91 devices.
+  *            @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag, applicable only for STM32F072 and STM32FO91 devices.
+  *            @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag, applicable only for STM32F072 and STM32FO91 devices.
+  *            @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag, applicable only for STM32F072 and STM32FO91 devices.
+  *            @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag, applicable only for STM32F072 and STM32FO91 devices.
+  *            @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag, applicable only for STM32F072 and STM32FO91 devices.
+  *            @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag, applicable only for STM32FO91 devices.  
+  * @note   The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags 
+  *         relative to the same channel is set (Transfer Complete, Half-transfer 
+  *         Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or 
+  *         DMAy_FLAG_TEx). 
+  *      
+  * @retval The new state of DMA_FLAG (SET or RESET).
+  */
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
+
+  /* Calculate the used DMAy */
+  if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
+  {
+    /* Get DMA2 ISR register value */
+    tmpreg = DMA2->ISR ;
+  }
+  else
+  {
+    /* Get DMA1 ISR register value */
+    tmpreg = DMA1->ISR ;
+  }
+
+  /* Check the status of the specified DMAy flag */
+  if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
+  {
+    /* DMAy_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DMAy_FLAG is reset */
+    bitstatus = RESET;
+  }
+  
+  /* Return the DMAy_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DMAy Channelx's pending flags.
+  * @param  DMA_FLAG: specifies the flag to clear.
+  *          This parameter can be any combination (for the same DMA) of the following values:
+  *            @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
+  *            @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
+  *            @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
+  *            @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
+  *            @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
+  *            @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
+  *            @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
+  *            @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
+  *            @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
+  *            @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
+  *            @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
+  *            @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
+  *            @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
+  *            @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
+  *            @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
+  *            @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
+  *            @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
+  *            @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
+  *            @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
+  *            @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
+  *            @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag, applicable only for STM32F072 and STM32FO91 devices.
+  *            @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag, applicable only for STM32F072 and STM32FO91 devices.
+  *            @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag, applicable only for STM32F072 and STM32FO91 devices.
+  *            @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag, applicable only for STM32F072 and STM32FO91 devices.
+  *            @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag, applicable only for STM32F072 and STM32FO91 devices.
+  *            @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag, applicable only for STM32F072 and STM32FO91 devices.
+  *            @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag, applicable only for STM32F072 and STM32FO91 devices.
+  *            @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag, applicable only for STM32F072 and STM32FO91 devices.
+  *            @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag, applicable only for STM32FO91 devices.
+  *            @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag, applicable only for STM32FO91 devices. 
+  *              
+  * @note   Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags
+  *         relative to the same channel (Transfer Complete, Half-transfer Complete and
+  *         Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
+  *
+  * @retval None
+  */
+void DMA_ClearFlag(uint32_t DMAy_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
+
+/* Calculate the used DMAy */
+  if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
+  {
+    /* Clear the selected DMAy flags */
+    DMA2->IFCR = DMAy_FLAG;
+  }
+  else
+  {
+    /* Clear the selected DMAy flags */
+    DMA1->IFCR = DMAy_FLAG;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified DMAy Channelx interrupt has occurred or not.
+  * @param  DMA_IT: specifies the DMA interrupt source to check. 
+  *          This parameter can be one of the following values:
+  *            @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
+  *            @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
+  *            @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
+  *            @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
+  *            @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
+  *            @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
+  *            @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
+  *            @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
+  *            @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
+  *            @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
+  *            @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
+  *            @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
+  *            @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
+  *            @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
+  *            @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
+  *            @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
+  *            @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
+  *            @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
+  *            @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
+  *            @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
+  *            @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt, applicable only for STM32F072 and STM32FO91 devices.
+  *            @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt, applicable only for STM32F072 and STM32FO91 devices.
+  *            @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt, applicable only for STM32F072 and STM32FO91 devices.
+  *            @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt, applicable only for STM32F072 and STM32FO91 devices.
+  *            @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt, applicable only for STM32F072 and STM32FO91 devices.
+  *            @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt, applicable only for STM32F072 and STM32FO91 devices.
+  *            @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt, applicable only for STM32F072 and STM32FO91 devices.
+  *            @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt, applicable only for STM32F072 and STM32FO91 devices.  
+  *            @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt, applicable only for STM32FO91 devices.   
+  * @note   The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other 
+  *         interrupts relative to the same channel is set (Transfer Complete, 
+  *         Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx, 
+  *         DMAy_IT_HTx or DMAy_IT_TEx). 
+  *      
+  * @retval The new state of DMA_IT (SET or RESET).
+  */
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_GET_IT(DMAy_IT));
+
+  /* Calculate the used DMA */
+  if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
+  {
+    /* Get DMA2 ISR register value */
+    tmpreg = DMA2->ISR;
+  }
+  else
+  {
+    /* Get DMA1 ISR register value */
+    tmpreg = DMA1->ISR;
+  }
+
+  /* Check the status of the specified DMAy interrupt */
+  if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
+  {
+    /* DMAy_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DMAy_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the DMAy_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DMAy Channelx's interrupt pending bits.
+  * @param  DMA_IT: specifies the DMA interrupt pending bit to clear.
+  *          This parameter can be any combination (for the same DMA) of the following values:
+  *            @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
+  *            @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
+  *            @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
+  *            @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
+  *            @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
+  *            @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
+  *            @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
+  *            @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
+  *            @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
+  *            @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
+  *            @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
+  *            @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
+  *            @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
+  *            @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
+  *            @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
+  *            @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
+  *            @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
+  *            @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
+  *            @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
+  *            @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
+  *            @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt, applicable only for STM32F072 and STM32FO91 devices.
+  *            @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt, applicable only for STM32F072 and STM32FO91 devices.
+  *            @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt, applicable only for STM32F072 and STM32FO91 devices.
+  *            @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt, applicable only for STM32F072 and STM32FO91 devices.
+  *            @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt, applicable only for STM32F072 and STM32FO91 devices.
+  *            @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt, applicable only for STM32F072 and STM32FO91 devices.
+  *            @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt, applicable only for STM32F072 and STM32FO91 devices.
+  *            @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt, applicable only for STM32F072 and STM32FO91 devices.  
+  *            @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt, applicable only for STM32FO91 devices.
+  *            @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt, applicable only for STM32FO91 devices.  
+  *     
+  * @note   Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other 
+  *         interrupts relative to the same channel (Transfer Complete, Half-transfer 
+  *         Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and 
+  *         DMAy_IT_TEx).  
+  *        
+  * @retval None
+  */
+void DMA_ClearITPendingBit(uint32_t DMAy_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
+  
+  /* Calculate the used DMAy */
+  if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
+  {
+    /* Clear the selected DMAy interrupt pending bits */
+    DMA2->IFCR = DMAy_IT;
+  }
+  else
+  {
+    /* Clear the selected DMAy interrupt pending bits */
+    DMA1->IFCR = DMAy_IT;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_exti.c b/system/src/stm32f0-stdperiph/stm32f0xx_exti.c

new file mode 100644 (file)

index 0000000..16f2ea3
--- /dev/null
+++ b/system/src/stm32f0-stdperiph/stm32f0xx_exti.c
@@ -0,0 +1,314 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_exti.c
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the EXTI peripheral:
+  *           + Initialization and Configuration
+  *           + Interrupts and flags management
+  *
+  *  @verbatim
+  ==============================================================================
+                            ##### EXTI features ##### 
+  ==============================================================================
+    [..] External interrupt/event lines are mapped as following:
+         (#) All available GPIO pins are connected to the 16 external 
+             interrupt/event lines from EXTI0 to EXTI15.
+         (#) EXTI line 16 is connected to the PVD output, not applicable for STM32F030 devices.
+         (#) EXTI line 17 is connected to the RTC Alarm event.
+         (#) EXTI line 18 is connected to the RTC Alarm event, applicable only for STM32F072 devices.
+         (#) EXTI line 19 is connected to the RTC Tamper and TimeStamp events.
+         (#) EXTI line 20 is connected to the RTC wakeup event, applicable only for STM32F072 devices.
+         (#) EXTI line 21 is connected to the Comparator 1 wakeup event, applicable only for STM32F051 and STM32F072 devices. 
+         (#) EXTI line 22 is connected to the Comparator 2 wakeup event, applicable only for STM32F051 and STM32F072 devices.
+         (#) EXTI line 23 is connected to the I2C1 wakeup event, not applicable for STM32F030 devices.
+         (#) EXTI line 25 is connected to the USART1 wakeup event, not applicable for STM32F030 devices.
+         (#) EXTI line 26 is connected to the USART2 wakeup event, applicable only for STM32F072 devices.
+         (#) EXTI line 27 is connected to the CEC wakeup event, applicable only for STM32F051 and STM32F072 devices.
+         (#) EXTI line 31 is connected to the VDD USB monitor event, applicable only for STM32F072 devices.
+
+                       ##### How to use this driver ##### 
+  ==============================================================================
+    [..] In order to use an I/O pin as an external interrupt source, follow
+         steps below:
+    (#) Configure the I/O in input mode using GPIO_Init()
+    (#) Select the input source pin for the EXTI line using 
+        SYSCFG_EXTILineConfig().
+    (#) Select the mode(interrupt, event) and configure the trigger selection 
+       (Rising, falling or both) using EXTI_Init(). For the internal interrupt,
+       the trigger selection is not needed( the active edge is always the rising one).
+    (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init().
+    (#) Optionally, you can generate a software interrupt using the function EXTI_GenerateSWInterrupt().
+    [..]
+    (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
+      registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+    @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_exti.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup EXTI 
+  * @brief EXTI driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define EXTI_LINENONE     ((uint32_t)0x00000)        /* No interrupt selected */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup EXTI_Private_Functions
+  * @{
+  */
+
+/** @defgroup EXTI_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+  ==============================================================================
+            ##### Initialization and Configuration functions #####
+  ==============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the EXTI peripheral registers to their default reset 
+  *         values.
+  * @param  None
+  * @retval None
+  */
+void EXTI_DeInit(void)
+{
+  EXTI->IMR = 0x0F940000;
+  EXTI->EMR = 0x00000000;
+  EXTI->RTSR = 0x00000000;
+  EXTI->FTSR = 0x00000000;
+  EXTI->PR = 0x006BFFFF;
+}
+
+/**
+  * @brief  Initializes the EXTI peripheral according to the specified
+  *         parameters in the EXTI_InitStruct.
+  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure that 
+  *         contains the configuration information for the EXTI peripheral.
+  * @retval None
+  */
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+  uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
+  assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
+  assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
+  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
+
+  tmp = (uint32_t)EXTI_BASE;
+
+  if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
+  {
+    /* Clear EXTI line configuration */
+    EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
+    EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
+
+    tmp += EXTI_InitStruct->EXTI_Mode;
+
+    *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
+
+    /* Clear Rising Falling edge configuration */
+    EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
+    EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
+
+    /* Select the trigger for the selected interrupts */
+    if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
+    {
+      /* Rising Falling edge */
+      EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
+      EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
+    }
+    else
+    {
+      tmp = (uint32_t)EXTI_BASE;
+      tmp += EXTI_InitStruct->EXTI_Trigger;
+
+      *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
+    }
+  }
+  else
+  {
+    tmp += EXTI_InitStruct->EXTI_Mode;
+
+    /* Disable the selected external lines */
+    *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
+  }
+}
+
+/**
+  * @brief  Fills each EXTI_InitStruct member with its reset value.
+  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+  EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
+  EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+  EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
+  EXTI_InitStruct->EXTI_LineCmd = DISABLE;
+}
+
+/**
+  * @brief  Generates a Software interrupt on selected EXTI line.
+  * @param  EXTI_Line: specifies the EXTI line on which the software interrupt
+  *         will be generated.
+  *          This parameter can be any combination of EXTI_Linex where x can be (0..27).
+  * @retval None
+  */
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(EXTI_Line));
+
+  EXTI->SWIER |= EXTI_Line;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Group2 Interrupts and flags management functions
+ *  @brief    Interrupts and flags management functions 
+ *
+@verbatim   
+  ==============================================================================
+             ##### Interrupts and flags management functions #####
+  ==============================================================================
+  
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the specified EXTI line flag is set or not.
+  * @param  EXTI_Line: specifies the EXTI line flag to check.
+  *          This parameter can be EXTI_Linex where x can be (0..27).
+  * @retval The new state of EXTI_Line (SET or RESET).
+  */
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
+{
+   FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+  if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the EXTI's line pending flags.
+  * @param  EXTI_Line: specifies the EXTI lines flags to clear.
+  *          This parameter can be any combination of EXTI_Linex where x can be (0..27).
+  * @retval None
+  */
+void EXTI_ClearFlag(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(EXTI_Line));
+
+  EXTI->PR = EXTI_Line;
+}
+
+/**
+  * @brief  Checks whether the specified EXTI line is asserted or not.
+  * @param  EXTI_Line: specifies the EXTI line to check.
+  *          This parameter can be EXTI_Linex where x can be (0..27).
+  * @retval The new state of EXTI_Line (SET or RESET).
+  */
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
+{
+  ITStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+  if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the EXTI's line pending bits.
+  * @param  EXTI_Line: specifies the EXTI lines to clear.
+  *          This parameter can be any combination of EXTI_Linex where x can be (0..27).
+  * @retval None
+  */
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(EXTI_Line));
+
+  EXTI->PR = EXTI_Line;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_flash.c b/system/src/stm32f0-stdperiph/stm32f0xx_flash.c

new file mode 100644 (file)

index 0000000..54a8833
--- /dev/null
+++ b/system/src/stm32f0-stdperiph/stm32f0xx_flash.c
@@ -0,0 +1,1256 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_flash.c
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the FLASH peripheral:
+  *            - FLASH Interface configuration
+  *            - FLASH Memory Programming
+  *            - Option Bytes Programming
+  *            - Interrupts and flags management
+  *
+  *  @verbatim
+ ===============================================================================
+                    ##### How to use this driver #####
+ ===============================================================================
+    [..] This driver provides functions to configure and program the Flash 
+         memory of all STM32F0xx devices. These functions are split in 4 groups
+         (#) FLASH Interface configuration functions: this group includes the 
+             management of following features:
+             (++) Set the latency
+             (++) Enable/Disable the prefetch buffer
+
+         (#) FLASH Memory Programming functions: this group includes all needed 
+             functions to erase and program the main memory:
+             (++) Lock and Unlock the Flash interface.
+             (++) Erase function: Erase Page, erase all pages.
+             (++) Program functions: Half Word and Word write.
+
+         (#) FLASH Option Bytes Programming functions: this group includes all 
+             needed functions to:
+             (++) Lock and Unlock the Flash Option bytes.
+             (++) Launch the Option Bytes loader
+             (++) Erase the Option Bytes
+             (++)Set/Reset the write protection
+             (++) Set the Read protection Level
+             (++) Program the user option Bytes
+             (++) Set/Reset the BOOT1 bit
+             (++) Enable/Disable the VDDA Analog Monitoring
+             (++) Get the user option bytes
+             (++) Get the Write protection
+             (++) Get the read protection status
+
+         (#) FLASH Interrupts and flag management functions: this group includes 
+             all needed functions to:
+             (++) Enable/Disable the flash interrupt sources
+             (++) Get flags status
+             (++) Clear flags
+             (++) Get Flash operation status
+             (++) Wait for last flash operation
+
+ @endverbatim
+  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_flash.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup FLASH 
+  * @brief FLASH driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+ 
+/** @defgroup FLASH_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup FLASH_Group1 FLASH Interface configuration functions
+  *  @brief   FLASH Interface configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+               ##### FLASH Interface configuration functions #####
+ ===============================================================================
+
+    [..] FLASH_Interface configuration_Functions, includes the following functions:
+       (+) void FLASH_SetLatency(uint32_t FLASH_Latency):
+    [..] To correctly read data from Flash memory, the number of wait states (LATENCY) 
+     must be correctly programmed according to the frequency of the CPU clock (HCLK) 
+    [..]
+        +--------------------------------------------- +
+        |  Wait states  |   HCLK clock frequency (MHz) |
+        |---------------|------------------------------|
+        |0WS(1CPU cycle)|       0 < HCLK <= 24         |
+        |---------------|------------------------------|
+        |1WS(2CPU cycle)|       24 < HCLK <= 48        |
+        +----------------------------------------------+
+    [..]
+       (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState);
+    [..]
+     All these functions don't need the unlock sequence.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Sets the code latency value.
+  * @param  FLASH_Latency: specifies the FLASH Latency value.
+  *          This parameter can be one of the following values:
+  *             @arg FLASH_Latency_0: FLASH Zero Latency cycle
+  *             @arg FLASH_Latency_1: FLASH One Latency cycle
+  * @retval None
+  */
+void FLASH_SetLatency(uint32_t FLASH_Latency)
+{
+   uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_LATENCY(FLASH_Latency));
+
+  /* Read the ACR register */
+  tmpreg = FLASH->ACR;  
+
+  /* Sets the Latency value */
+  tmpreg &= (uint32_t) (~((uint32_t)FLASH_ACR_LATENCY));
+  tmpreg |= FLASH_Latency;
+
+  /* Write the ACR register */
+  FLASH->ACR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the Prefetch Buffer.
+  * @param  NewState: new state of the FLASH prefetch buffer.
+  *          This parameter can be: ENABLE or DISABLE. 
+  * @retval None
+  */
+void FLASH_PrefetchBufferCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if(NewState != DISABLE)
+  {
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+  }
+  else
+  {
+    FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_PRFTBE));
+  }
+}
+
+/**
+  * @brief  Checks whether the FLASH Prefetch Buffer status is set or not.
+  * @param  None
+  * @retval FLASH Prefetch Buffer Status (SET or RESET).
+  */
+FlagStatus FLASH_GetPrefetchBufferStatus(void)
+{
+  FlagStatus bitstatus = RESET;
+
+  if ((FLASH->ACR & FLASH_ACR_PRFTBS) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */
+  return bitstatus; 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Group2 FLASH Memory Programming functions
+ *  @brief   FLASH Memory Programming functions
+ *
+@verbatim   
+ ===============================================================================
+                ##### FLASH Memory Programming functions #####
+ ===============================================================================
+
+    [..] The FLASH Memory Programming functions, includes the following functions:
+       (+) void FLASH_Unlock(void);
+       (+) void FLASH_Lock(void);
+       (+) FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
+       (+) FLASH_Status FLASH_EraseAllPages(void);
+       (+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+       (+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
+
+    [..] Any operation of erase or program should follow these steps:
+       
+       (#) Call the FLASH_Unlock() function to enable the flash control register and 
+           program memory access
+       (#) Call the desired function to erase page or program data
+       (#) Call the FLASH_Lock() to disable the flash program memory access 
+      (recommended to protect the FLASH memory against possible unwanted operation)
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Unlocks the FLASH control register and program memory access.
+  * @param  None
+  * @retval None
+  */
+void FLASH_Unlock(void)
+{
+  if((FLASH->CR & FLASH_CR_LOCK) != RESET)
+  {
+    /* Unlocking the program memory access */
+    FLASH->KEYR = FLASH_FKEY1;
+    FLASH->KEYR = FLASH_FKEY2;
+  }
+}
+
+/**
+  * @brief  Locks the Program memory access.
+  * @param  None
+  * @retval None
+  */
+void FLASH_Lock(void)
+{
+  /* Set the LOCK Bit to lock the FLASH control register and program memory access */
+  FLASH->CR |= FLASH_CR_LOCK;
+}
+
+/**
+  * @brief  Erases a specified page in program memory.
+  * @note   To correctly run this function, the FLASH_Unlock() function must be called before.
+  * @note   Call the FLASH_Lock() to disable the flash memory access (recommended
+  *         to protect the FLASH memory against possible unwanted operation)
+  * @param  Page_Address: The page address in program memory to be erased.
+  * @note   A Page is erased in the Program memory only if the address to load 
+  *         is the start address of a page (multiple of 1024 bytes).
+  * @retval FLASH Status: The returned value can be: 
+  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_PROGRAM_ADDRESS(Page_Address));
+ 
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  { 
+    /* If the previous operation is completed, proceed to erase the page */
+    FLASH->CR |= FLASH_CR_PER;
+    FLASH->AR  = Page_Address;
+    FLASH->CR |= FLASH_CR_STRT;
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+    
+    /* Disable the PER Bit */
+    FLASH->CR &= ~FLASH_CR_PER;
+  }
+    
+  /* Return the Erase Status */
+  return status;
+}
+
+/**
+  * @brief  Erases all FLASH pages.
+  * @note   To correctly run this function, the FLASH_Unlock() function must be called before.
+  * @note   Call the FLASH_Lock() to disable the flash memory access (recommended
+  *         to protect the FLASH memory against possible unwanted operation)
+  * @param  None
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_EraseAllPages(void)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {
+    /* if the previous operation is completed, proceed to erase all pages */
+     FLASH->CR |= FLASH_CR_MER;
+     FLASH->CR |= FLASH_CR_STRT;
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    /* Disable the MER Bit */
+    FLASH->CR &= ~FLASH_CR_MER;
+  }
+
+  /* Return the Erase Status */
+  return status;
+}
+
+/**
+  * @brief  Programs a word at a specified address.
+  * @note   To correctly run this function, the FLASH_Unlock() function must be called before.
+  * @note   Call the FLASH_Lock() to disable the flash memory access (recommended
+  *         to protect the FLASH memory against possible unwanted operation)
+  * @param  Address: specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed.
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. 
+  */
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {
+    /* If the previous operation is completed, proceed to program the new first 
+    half word */
+    FLASH->CR |= FLASH_CR_PG;
+  
+    *(__IO uint16_t*)Address = (uint16_t)Data;
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+ 
+    if(status == FLASH_COMPLETE)
+    {
+      /* If the previous operation is completed, proceed to program the new second 
+      half word */
+      tmp = Address + 2;
+
+      *(__IO uint16_t*) tmp = Data >> 16;
+    
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+        
+      /* Disable the PG Bit */
+      FLASH->CR &= ~FLASH_CR_PG;
+    }
+    else
+    {
+      /* Disable the PG Bit */
+      FLASH->CR &= ~FLASH_CR_PG;
+    }
+  }
+   
+  /* Return the Program Status */
+  return status;
+}
+
+/**
+  * @brief  Programs a half word at a specified address.
+  * @note   To correctly run this function, the FLASH_Unlock() function must be called before.
+  * @note   Call the FLASH_Lock() to disable the flash memory access (recommended
+  *         to protect the FLASH memory against possible unwanted operation)
+  * @param  Address: specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed.
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. 
+  */
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {
+    /* If the previous operation is completed, proceed to program the new data */
+    FLASH->CR |= FLASH_CR_PG;
+  
+    *(__IO uint16_t*)Address = Data;
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+    
+    /* Disable the PG Bit */
+    FLASH->CR &= ~FLASH_CR_PG;
+  } 
+  
+  /* Return the Program Status */
+  return status;
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup FLASH_Group3 Option Bytes Programming functions
+ *  @brief   Option Bytes Programming functions 
+ *
+@verbatim   
+ ===============================================================================
+                ##### Option Bytes Programming functions #####
+ ===============================================================================
+
+    [..] The FLASH_Option Bytes Programming_functions, includes the following functions:
+       (+) void FLASH_OB_Unlock(void);
+       (+) void FLASH_OB_Lock(void);
+       (+) void FLASH_OB_Launch(void);
+       (+) FLASH_Status FLASH_OB_Erase(void);
+       (+) FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
+       (+) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
+       (+) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
+       (+) FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);
+       (+) FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);
+       (+) FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);
+       (+) FLASH_OB_ProgramData(uint32_t Address, uint8_t Data);
+       (+) uint8_t FLASH_OB_GetUser(void);
+       (+) uint32_t FLASH_OB_GetWRP(void);
+       (+) FlagStatus FLASH_OB_GetRDP(void);
+
+    [..] Any operation of erase or program should follow these steps:
+
+   (#) Call the FLASH_OB_Unlock() function to enable the Option Bytes registers access
+
+   (#) Call one or several functions to program the desired option bytes 
+      (++) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level
+      (++) FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) 
+           => to Enable/Disable the desired sector write protection
+      (++) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) 
+           => to configure the user option Bytes: IWDG, STOP and the Standby.
+      (++) FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1)
+           => to set or reset BOOT1 
+      (++) FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG) 
+           => to enable or disable the VDDA Analog Monitoring                   
+      (++) You can write all User Options bytes at once using a single function
+           by calling FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER)
+      (++) FLASH_OB_ProgramData(uint32_t Address, uint8_t Data) to program the 
+           two half word in the option bytes
+
+   (#) Once all needed option bytes to be programmed are correctly written, call the
+      FLASH_OB_Launch(void) function to launch the Option Bytes programming process.
+
+   (#) Call the FLASH_OB_Lock() to disable the Option Bytes registers access (recommended
+      to protect the option Bytes against possible unwanted operations)
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Unlocks the option bytes block access.
+  * @param  None
+  * @retval None
+  */
+void FLASH_OB_Unlock(void)
+{
+  if((FLASH->CR & FLASH_CR_OPTWRE) == RESET)
+  { 
+    /* Unlocking the option bytes block access */
+    FLASH->OPTKEYR = FLASH_OPTKEY1;
+    FLASH->OPTKEYR = FLASH_OPTKEY2;
+  }
+}
+
+/**
+  * @brief  Locks the option bytes block access.
+  * @param  None
+  * @retval None
+  */
+void FLASH_OB_Lock(void)
+{
+  /* Set the OPTWREN Bit to lock the option bytes block access */
+  FLASH->CR &= ~FLASH_CR_OPTWRE;
+}
+
+/**
+  * @brief  Launch the option byte loading.
+  * @param  None
+  * @retval None
+  */
+void FLASH_OB_Launch(void)
+{
+  /* Set the OBL_Launch bit to launch the option byte loading */
+  FLASH->CR |= FLASH_CR_OBL_LAUNCH;
+}
+
+/**
+  * @brief  Erases the FLASH option bytes.
+  * @note   To correctly run this function, the FLASH_OB_Unlock() function must be called before.
+  * @note   Call the FLASH_OB_Lock() to disable the flash control register access and the option
+  *         bytes (recommended to protect the FLASH memory against possible unwanted operation)
+  * @note   This functions erases all option bytes except the Read protection (RDP).
+  * @param  None
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_OB_Erase(void)
+{
+  uint16_t rdptmp = OB_RDP_Level_0;
+
+  FLASH_Status status = FLASH_COMPLETE;
+
+  /* Get the actual read protection Option Byte value */ 
+  if(FLASH_OB_GetRDP() != RESET)
+  {
+    rdptmp = 0x00;  
+  }
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+  if(status == FLASH_COMPLETE)
+  {   
+    /* If the previous operation is completed, proceed to erase the option bytes */
+    FLASH->CR |= FLASH_CR_OPTER;
+    FLASH->CR |= FLASH_CR_STRT;
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+    
+    if(status == FLASH_COMPLETE)
+    {
+      /* If the erase operation is completed, disable the OPTER Bit */
+      FLASH->CR &= ~FLASH_CR_OPTER;
+       
+      /* Enable the Option Bytes Programming operation */
+      FLASH->CR |= FLASH_CR_OPTPG;
+
+      /* Restore the last read protection Option Byte value */
+      OB->RDP = (uint16_t)rdptmp; 
+
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+ 
+      if(status != FLASH_TIMEOUT)
+      {
+        /* if the program operation is completed, disable the OPTPG Bit */
+        FLASH->CR &= ~FLASH_CR_OPTPG;
+      }
+    }
+    else
+    {
+      if (status != FLASH_TIMEOUT)
+      {
+        /* Disable the OPTPG Bit */
+        FLASH->CR &= ~FLASH_CR_OPTPG;
+      }
+    }  
+  }
+  /* Return the erase status */
+  return status;
+}
+
+/**
+  * @brief  Write protects the desired pages
+  * @note   To correctly run this function, the FLASH_OB_Unlock() function must be called before.
+  * @note   Call the FLASH_OB_Lock() to disable the flash control register access and the option
+  *         bytes (recommended to protect the FLASH memory against possible unwanted operation)
+  * @param  OB_WRP: specifies the address of the pages to be write protected.
+  *          This parameter can be:
+  *             @arg OB_WRP_Pages0to3..OB_WRP_Pages60to63
+  *             @arg OB_WRP_AllPages
+  * @retval FLASH Status: The returned value can be: 
+  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP)
+{
+ uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
+
+  FLASH_Status status = FLASH_COMPLETE;
+
+  /* Check the parameters */
+  assert_param(IS_OB_WRP(OB_WRP));
+
+  OB_WRP = (uint32_t)(~OB_WRP);
+  WRP0_Data = (uint16_t)(OB_WRP & OB_WRP0_WRP0);
+  WRP1_Data = (uint16_t)((OB_WRP >> 8) & OB_WRP0_WRP0);
+  WRP2_Data = (uint16_t)((OB_WRP >> 16) & OB_WRP0_WRP0) ;
+  WRP3_Data = (uint16_t)((OB_WRP >> 24) & OB_WRP0_WRP0) ;
+    
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+  if(status == FLASH_COMPLETE)
+  {
+    FLASH->CR |= FLASH_CR_OPTPG;
+
+    if(WRP0_Data != 0xFF)
+    {
+      OB->WRP0 = WRP0_Data;
+      
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+    }
+    if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))
+    {
+      OB->WRP1 = WRP1_Data;
+      
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+    }
+    if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF))
+    {
+      OB->WRP2 = WRP2_Data;
+      
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+    }    
+    if((status == FLASH_COMPLETE) && (WRP3_Data != 0xFF))
+    {
+      OB->WRP3 = WRP3_Data;
+      
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+    }  
+    if(status != FLASH_TIMEOUT)
+    {
+      /* if the program operation is completed, disable the OPTPG Bit */
+      FLASH->CR &= ~FLASH_CR_OPTPG;
+    }
+  } 
+  /* Return the write protection operation Status */
+  return status;
+}
+
+/**
+  * @brief  Enables or disables the read out protection.
+  * @note   To correctly run this function, the FLASH_OB_Unlock() function must be called before.
+  * @note   Call the FLASH_OB_Lock() to disable the flash control register access and the option
+  *         bytes (recommended to protect the FLASH memory against possible unwanted operation)
+  * @param  FLASH_ReadProtection_Level: specifies the read protection level. 
+  *          This parameter can be:
+  *             @arg OB_RDP_Level_0: No protection
+  *             @arg OB_RDP_Level_1: Read protection of the memory
+  *             @arg OB_RDP_Level_2: Chip protection
+  * @note   When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
+  * @retval FLASH Status: The returned value can be: 
+  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+  
+  /* Check the parameters */
+  assert_param(IS_OB_RDP(OB_RDP));
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {
+    FLASH->CR |= FLASH_CR_OPTER;
+    FLASH->CR |= FLASH_CR_STRT;
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+    
+    if(status == FLASH_COMPLETE)
+    {
+      /* If the erase operation is completed, disable the OPTER Bit */
+      FLASH->CR &= ~FLASH_CR_OPTER;
+      
+      /* Enable the Option Bytes Programming operation */
+      FLASH->CR |= FLASH_CR_OPTPG;
+       
+      OB->RDP = OB_RDP;
+
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); 
+    
+      if(status != FLASH_TIMEOUT)
+      {
+        /* if the program operation is completed, disable the OPTPG Bit */
+        FLASH->CR &= ~FLASH_CR_OPTPG;
+      }
+    }
+    else 
+    {
+      if(status != FLASH_TIMEOUT)
+      {
+        /* Disable the OPTER Bit */
+        FLASH->CR &= ~FLASH_CR_OPTER;
+      }
+    }
+  }
+  /* Return the protection operation Status */
+  return status;
+}
+
+/**
+  * @brief  Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
+  * @note   To correctly run this function, the FLASH_OB_Unlock() function must be called before.
+  * @note   Call the FLASH_OB_Lock() to disable the flash control register access and the option
+  *         bytes (recommended to protect the FLASH memory against possible unwanted operation)
+  * @param  OB_IWDG: Selects the WDG mode
+  *          This parameter can be one of the following values:
+  *             @arg OB_IWDG_SW: Software WDG selected
+  *             @arg OB_IWDG_HW: Hardware WDG selected
+  * @param  OB_STOP: Reset event when entering STOP mode.
+  *          This parameter can be one of the following values:
+  *             @arg OB_STOP_NoRST: No reset generated when entering in STOP
+  *             @arg OB_STOP_RST: Reset generated when entering in STOP
+  * @param  OB_STDBY: Reset event when entering Standby mode.
+  *          This parameter can be one of the following values:
+  *             @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
+  *             @arg OB_STDBY_RST: Reset generated when entering in STANDBY
+  * @retval FLASH Status: The returned value can be: 
+  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
+{
+  FLASH_Status status = FLASH_COMPLETE; 
+
+  /* Check the parameters */
+  assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
+  assert_param(IS_OB_STOP_SOURCE(OB_STOP));
+  assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {
+    /* Enable the Option Bytes Programming operation */
+    FLASH->CR |= FLASH_CR_OPTPG; 
+
+    OB->USER = (uint16_t)((uint16_t)(OB_IWDG | OB_STOP) | (uint16_t)(OB_STDBY | 0xF8));
+  
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    if(status != FLASH_TIMEOUT)
+    {
+      /* If the program operation is completed, disable the OPTPG Bit */
+      FLASH->CR &= ~FLASH_CR_OPTPG;
+    }
+  }    
+  /* Return the Option Byte program Status */
+  return status;
+}
+
+/**
+  * @brief  Sets or resets the BOOT1 option bit.
+  * @param  OB_BOOT1: Set or Reset the BOOT1 option bit.
+  *          This parameter can be one of the following values:
+  *             @arg OB_BOOT1_RESET: BOOT1 option bit reset
+  *             @arg OB_BOOT1_SET: BOOT1 option bit set
+  * @retval None
+  */
+FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1)
+{
+  FLASH_Status status = FLASH_COMPLETE; 
+
+  /* Check the parameters */
+  assert_param(IS_OB_BOOT1(OB_BOOT1));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {  
+    /* Enable the Option Bytes Programming operation */
+    FLASH->CR |= FLASH_CR_OPTPG;
+
+    OB->USER = OB_BOOT1 | 0xEF;
+  
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    if(status != FLASH_TIMEOUT)
+    {
+      /* If the program operation is completed, disable the OPTPG Bit */
+      FLASH->CR &= ~FLASH_CR_OPTPG;
+    }
+  }
+  /* Return the Option Byte program Status */
+  return status;
+}
+
+/**
+  * @brief  Sets or resets the BOOT0 option bit.
+  * @note   This function is applicable only for the STM32F042 devices.
+  * @param  OB_BOOT0: Set or Reset the BOOT0 option bit.
+  *          This parameter can be one of the following values:
+  *             @arg OB_BOOT0_RESET: BOOT0 option bit reset
+  *             @arg OB_BOOT0_SET: BOOT0 option bit set
+  * @retval None
+  */
+FLASH_Status FLASH_OB_BOOT0Config(uint8_t OB_BOOT0)
+{
+  FLASH_Status status = FLASH_COMPLETE; 
+
+  /* Check the parameters */
+  assert_param(IS_OB_BOOT0(OB_BOOT0));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {  
+    /* Enable the Option Bytes Programming operation */
+    FLASH->CR |= FLASH_CR_OPTPG;
+
+    OB->USER = OB_BOOT0 | 0xF7;
+  
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    if(status != FLASH_TIMEOUT)
+    {
+      /* If the program operation is completed, disable the OPTPG Bit */
+      FLASH->CR &= ~FLASH_CR_OPTPG;
+    }
+  }
+  /* Return the Option Byte program Status */
+  return status;
+}
+
+/**
+  * @brief  Sets or resets the BOOT0SW option bit.
+  * @note   This function is applicable only for the STM32F042 devices.   
+  * @param  OB_BOOT0SW: Set or Reset the BOOT0_SW option bit.
+  *          This parameter can be one of the following values:
+  *             @arg OB_BOOT0_SW: BOOT0_SW option bit reset
+  *             @arg OB_BOOT0_HW: BOOT0_SW option bit set
+  * @retval None
+  */
+FLASH_Status FLASH_OB_BOOT0SWConfig(uint8_t OB_BOOT0SW)
+{
+  FLASH_Status status = FLASH_COMPLETE; 
+
+  /* Check the parameters */
+  assert_param(IS_OB_BOOT0SW(OB_BOOT0SW));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {  
+    /* Enable the Option Bytes Programming operation */
+    FLASH->CR |= FLASH_CR_OPTPG;
+
+    OB->USER = OB_BOOT0SW | 0x7F;
+  
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    if(status != FLASH_TIMEOUT)
+    {
+      /* If the program operation is completed, disable the OPTPG Bit */
+      FLASH->CR &= ~FLASH_CR_OPTPG;
+    }
+  }
+  /* Return the Option Byte program Status */
+  return status;
+}
+
+/**
+  * @brief  Sets or resets the analogue monitoring on VDDA Power source.
+  * @param  OB_VDDA_ANALOG: Selects the analog monitoring on VDDA Power source.
+  *          This parameter can be one of the following values:
+  *             @arg OB_VDDA_ANALOG_ON: Analog monitoring on VDDA Power source ON
+  *             @arg OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source OFF
+  * @retval None
+  */
+FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG)
+{
+  FLASH_Status status = FLASH_COMPLETE; 
+
+  /* Check the parameters */
+  assert_param(IS_OB_VDDA_ANALOG(OB_VDDA_ANALOG));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {  
+    /* Enable the Option Bytes Programming operation */
+    FLASH->CR |= FLASH_CR_OPTPG; 
+
+    OB->USER = OB_VDDA_ANALOG | 0xDF;
+  
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    if(status != FLASH_TIMEOUT)
+    {
+      /* if the program operation is completed, disable the OPTPG Bit */
+      FLASH->CR &= ~FLASH_CR_OPTPG;
+    }
+  }
+  /* Return the Option Byte program Status */
+  return status;
+}
+
+/**
+  * @brief  Sets or resets the SRAM parity.
+  * @param  OB_SRAM_Parity: Set or Reset the SRAM parity enable bit.
+  *          This parameter can be one of the following values:
+  *             @arg OB_SRAM_PARITY_SET: Set SRAM parity.
+  *             @arg OB_SRAM_PARITY_RESET: Reset SRAM parity.
+  * @retval None
+  */
+FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity)
+{
+  FLASH_Status status = FLASH_COMPLETE; 
+
+  /* Check the parameters */
+  assert_param(IS_OB_SRAM_PARITY(OB_SRAM_Parity));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {  
+    /* Enable the Option Bytes Programming operation */
+    FLASH->CR |= FLASH_CR_OPTPG; 
+
+    OB->USER = OB_SRAM_Parity | 0xBF;
+  
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    if(status != FLASH_TIMEOUT)
+    {
+      /* if the program operation is completed, disable the OPTPG Bit */
+      FLASH->CR &= ~FLASH_CR_OPTPG;
+    }
+  }
+  /* Return the Option Byte program Status */
+  return status;
+}
+
+/**
+  * @brief  Programs the FLASH User Option Byte: IWDG_SW, RST_STOP, RST_STDBY,
+  *         BOOT1 and VDDA ANALOG monitoring.
+  * @note   To correctly run this function, the FLASH_OB_Unlock() function must be called before.
+  * @note   Call the FLASH_OB_Lock() to disable the flash control register access and the option
+  *         bytes (recommended to protect the FLASH memory against possible unwanted operation)
+  * @param  OB_USER: Selects all user option bytes
+  *          This parameter is a combination of the following values:
+  *             @arg OB_IWDG_SW / OB_IWDG_HW: Software / Hardware WDG selected
+  *             @arg OB_STOP_NoRST / OB_STOP_RST: No reset / Reset generated when entering in STOP
+  *             @arg OB_STDBY_NoRST / OB_STDBY_RST: No reset / Reset generated when entering in STANDBY
+  *             @arg OB_BOOT1_RESET / OB_BOOT1_SET: BOOT1 Reset / Set
+  *             @arg OB_VDDA_ANALOG_ON / OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source ON / OFF 
+  *             @arg OB_SRAM_PARITY_SET / OB_SRAM_PARITY_RESET: SRAM Parity SET / RESET
+  *             @arg OB_BOOT0_RESET / OB_BOOT0_SET: BOOT0 Reset / Set
+  *             @arg OB_BOOT0_SW / OB_BOOT0_SW: BOOT0 pin disabled / BOOT0 pin bonded with GPIO      
+  * @retval FLASH Status: The returned value can be: 
+  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER)
+{
+  FLASH_Status status = FLASH_COMPLETE; 
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {
+    /* Enable the Option Bytes Programming operation */
+    FLASH->CR |= FLASH_CR_OPTPG; 
+
+    OB->USER = OB_USER;
+  
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    if(status != FLASH_TIMEOUT)
+    {
+      /* If the program operation is completed, disable the OPTPG Bit */
+      FLASH->CR &= ~FLASH_CR_OPTPG;
+    }
+  }    
+  /* Return the Option Byte program Status */
+  return status;
+
+}
+
+/**
+  * @brief  Programs a half word at a specified Option Byte Data address.
+  * @note   To correctly run this function, the FLASH_OB_Unlock() function must be called before.
+  * @note   Call the FLASH_OB_Lock() to disable the flash control register access and the option
+  *         bytes (recommended to protect the FLASH memory against possible unwanted operation)
+  * @param  Address: specifies the address to be programmed.
+  *          This parameter can be 0x1FFFF804 or 0x1FFFF806. 
+  * @param  Data: specifies the data to be programmed.
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_OB_ProgramData(uint32_t Address, uint8_t Data)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+  /* Check the parameters */
+  assert_param(IS_OB_DATA_ADDRESS(Address));
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+  if(status == FLASH_COMPLETE)
+  {
+    /* Enables the Option Bytes Programming operation */
+    FLASH->CR |= FLASH_CR_OPTPG; 
+    *(__IO uint16_t*)Address = Data;
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+    
+    if(status != FLASH_TIMEOUT)
+    {
+      /* If the program operation is completed, disable the OPTPG Bit */
+      FLASH->CR &= ~FLASH_CR_OPTPG;
+    }
+  }
+  /* Return the Option Byte Data Program Status */
+  return status;
+}
+
+/**
+  * @brief  Returns the FLASH User Option Bytes values.
+  * @param  None
+  * @retval The FLASH User Option Bytes .
+  */
+uint8_t FLASH_OB_GetUser(void)
+{
+  /* Return the User Option Byte */
+  return (uint8_t)(FLASH->OBR >> 8);
+}
+
+/**
+  * @brief  Returns the FLASH Write Protection Option Bytes value.
+  * @param  None
+  * @retval The FLASH Write Protection Option Bytes value
+  */
+uint32_t FLASH_OB_GetWRP(void)
+{
+  /* Return the FLASH write protection Register value */
+  return (uint32_t)(FLASH->WRPR);
+}
+
+/**
+  * @brief  Checks whether the FLASH Read out Protection Status is set or not.
+  * @param  None
+  * @retval FLASH ReadOut Protection Status(SET or RESET)
+  */
+FlagStatus FLASH_OB_GetRDP(void)
+{
+  FlagStatus readstatus = RESET;
+  
+  if ((uint8_t)(FLASH->OBR & (FLASH_OBR_RDPRT1 | FLASH_OBR_RDPRT2)) != RESET)
+  {
+    readstatus = SET;
+  }
+  else
+  {
+    readstatus = RESET;
+  }
+  return readstatus;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Group4 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+ *
+@verbatim   
+ ===============================================================================
+             ##### Interrupts and flags management functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified FLASH interrupts.
+  * @param  FLASH_IT: specifies the FLASH interrupt sources to be enabled or 
+  *         disabled.
+  *          This parameter can be any combination of the following values:
+  *             @arg FLASH_IT_EOP: FLASH end of programming Interrupt
+  *             @arg FLASH_IT_ERR: FLASH Error Interrupt
+  * @retval None 
+  */
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_IT(FLASH_IT)); 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if(NewState != DISABLE)
+  {
+    /* Enable the interrupt sources */
+    FLASH->CR |= FLASH_IT;
+  }
+  else
+  {
+    /* Disable the interrupt sources */
+    FLASH->CR &= ~(uint32_t)FLASH_IT;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified FLASH flag is set or not.
+  * @param  FLASH_FLAG: specifies the FLASH flag to check.
+  *          This parameter can be one of the following values:
+  *             @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag 
+  *             @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag
+  *             @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
+  *             @arg FLASH_FLAG_EOP: FLASH End of Programming flag
+  * @retval The new state of FLASH_FLAG (SET or RESET).
+  */
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));
+
+  if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the new state of FLASH_FLAG (SET or RESET) */
+  return bitstatus; 
+}
+
+/**
+  * @brief  Clears the FLASH's pending flags.
+  * @param  FLASH_FLAG: specifies the FLASH flags to clear.
+  *          This parameter can be any combination of the following values:
+  *             @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag
+  *             @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
+  *             @arg FLASH_FLAG_EOP: FLASH End of Programming flag
+  * @retval None
+  */
+void FLASH_ClearFlag(uint32_t FLASH_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));
+  
+  /* Clear the flags */
+  FLASH->SR = FLASH_FLAG;
+}
+
+/**
+  * @brief  Returns the FLASH Status.
+  * @param  None
+  * @retval FLASH Status: The returned value can be: 
+  *         FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE.
+  */
+FLASH_Status FLASH_GetStatus(void)
+{
+  FLASH_Status FLASHstatus = FLASH_COMPLETE;
+  
+  if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) 
+  {
+    FLASHstatus = FLASH_BUSY;
+  }
+  else 
+  {  
+    if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00)
+    { 
+      FLASHstatus = FLASH_ERROR_WRP;
+    }
+    else 
+    {
+      if((FLASH->SR & (uint32_t)(FLASH_SR_PGERR)) != (uint32_t)0x00)
+      {
+        FLASHstatus = FLASH_ERROR_PROGRAM; 
+      }
+      else
+      {
+        FLASHstatus = FLASH_COMPLETE;
+      }
+    }
+  }
+  /* Return the FLASH Status */
+  return FLASHstatus;
+}
+
+
+/**
+  * @brief  Waits for a FLASH operation to complete or a TIMEOUT to occur.
+  * @param  Timeout: FLASH programming Timeout
+  * @retval FLASH Status: The returned value can be: FLASH_BUSY, 
+  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
+{ 
+  FLASH_Status status = FLASH_COMPLETE;
+   
+  /* Check for the FLASH Status */
+  status = FLASH_GetStatus();
+  
+  /* Wait for a FLASH operation to complete or a TIMEOUT to occur */
+  while((status == FLASH_BUSY) && (Timeout != 0x00))
+  {
+    status = FLASH_GetStatus();
+    Timeout--;
+  }
+  
+  if(Timeout == 0x00 )
+  {
+    status = FLASH_TIMEOUT;
+  }
+  /* Return the operation status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+   
+  /**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_gpio.c b/system/src/stm32f0-stdperiph/stm32f0xx_gpio.c

new file mode 100644 (file)

index 0000000..5b6eb23
--- /dev/null
+++ b/system/src/stm32f0-stdperiph/stm32f0xx_gpio.c
@@ -0,0 +1,542 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_gpio.c
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the GPIO peripheral:
+  *           + Initialization and Configuration functions
+  *           + GPIO Read and Write functions
+  *           + GPIO Alternate functions configuration functions
+  *
+  *  @verbatim
+  *
+  *
+    ===========================================================================
+                         ##### How to use this driver #####
+    ===========================================================================
+      [..]
+      (#) Enable the GPIO AHB clock using RCC_AHBPeriphClockCmd()
+      (#) Configure the GPIO pin(s) using GPIO_Init()
+          Four possible configuration are available for each pin:
+         (++) Input: Floating, Pull-up, Pull-down.
+         (++) Output: Push-Pull (Pull-up, Pull-down or no Pull)
+                      Open Drain (Pull-up, Pull-down or no Pull).
+              In output mode, the speed is configurable: Low, Medium, Fast or High.
+         (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull)
+                                  Open Drain (Pull-up, Pull-down or no Pull).
+         (++) Analog: required mode when a pin is to be used as ADC channel,
+              DAC output or comparator input.
+      (#) Peripherals alternate function:
+         (++) For ADC, DAC and comparators, configure the desired pin in analog 
+              mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN
+         (++) For other peripherals (TIM, USART...):
+              (+++) Connect the pin to the desired peripherals' Alternate 
+                    Function (AF) using GPIO_PinAFConfig() function. For PortC, 
+                    PortD and PortF, no configuration is needed.
+              (+++) Configure the desired pin in alternate function mode using
+                    GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+              (+++) Select the type, pull-up/pull-down and output speed via 
+                    GPIO_PuPd, GPIO_OType and GPIO_Speed members
+              (+++) Call GPIO_Init() function
+      (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
+      (#) To set/reset the level of a pin configured in output mode use
+          GPIO_SetBits()/GPIO_ResetBits()
+      (#) During and just after reset, the alternate functions are not active and 
+          the GPIO pins are configured in input floating mode (except JTAG pins).
+      (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as 
+          general-purpose (PC14 and PC15, respectively) when the LSE oscillator 
+          is off. The LSE has priority over the GPIO function.
+      (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose 
+          PD0 and PD1, respectively, when the HSE oscillator is off. The HSE has 
+          priority over the GPIO function.
+    @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_gpio.h"
+#include "stm32f0xx_rcc.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup GPIO 
+  * @brief GPIO driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup GPIO_Private_Functions 
+  * @{
+  */
+
+/** @defgroup GPIO_Group1 Initialization and Configuration
+ *  @brief   Initialization and Configuration
+ *
+@verbatim
+ ===============================================================================
+                    ##### Initialization and Configuration #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the GPIOx peripheral registers to their default reset 
+  *         values.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @note   GPIOE is available only for STM32F072.
+  * @note   GPIOD is not available for STM32F031.    
+  * @retval None
+  */
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  if(GPIOx == GPIOA)
+  {
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE);
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE);
+  }
+  else if(GPIOx == GPIOB)
+  {
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE);
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);
+  }
+  else if(GPIOx == GPIOC)
+  {
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE);
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE);
+  }
+  else if(GPIOx == GPIOD)
+  {
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE);
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE);
+  }
+  else if(GPIOx == GPIOE)
+  {
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE);
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE);
+  }
+  else
+  {
+    if(GPIOx == GPIOF)
+    {
+      RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, ENABLE);
+      RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, DISABLE);
+    }
+  }
+}
+
+/**
+  * @brief  Initializes the GPIOx peripheral according to the specified 
+  *         parameters in the GPIO_InitStruct.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @note   GPIOE is available only for STM32F072.
+  * @note   GPIOD is not available for STM32F031.   
+  * @param  GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains
+  *         the configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
+{
+  uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
+  assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
+  assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
+
+  /*-------------------------- Configure the port pins -----------------------*/
+  /*-- GPIO Mode Configuration --*/
+  for (pinpos = 0x00; pinpos < 0x10; pinpos++)
+  {
+    pos = ((uint32_t)0x01) << pinpos;
+
+    /* Get the port pins position */
+    currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
+
+    if (currentpin == pos)
+    {
+      if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
+      {
+        /* Check Speed mode parameters */
+        assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
+
+        /* Speed mode configuration */
+        GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
+        GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
+
+        /* Check Output mode parameters */
+        assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
+
+        /* Output mode configuration */
+        GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos));
+        GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
+      }
+
+      GPIOx->MODER  &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
+
+      GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
+
+      /* Pull-up Pull down resistor configuration */
+      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
+      GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
+    }
+  }
+}
+
+/**
+  * @brief  Fills each GPIO_InitStruct member with its default value.
+  * @param  GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure which will 
+  *         be initialized.
+  * @retval None
+  */
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
+{
+  /* Reset GPIO init structure parameters values */
+  GPIO_InitStruct->GPIO_Pin  = GPIO_Pin_All;
+  GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStruct->GPIO_Speed = GPIO_Speed_Level_2;
+  GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
+}
+
+/**
+  * @brief  Locks GPIO Pins configuration registers.
+  * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+  * @note   The configuration of the locked GPIO pins can no longer be modified
+  *         until the next device reset.
+  * @param  GPIOx: where x can be (A or B) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *          This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  __IO uint32_t tmp = 0x00010000;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_LIST_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  tmp |= GPIO_Pin;
+  /* Set LCKK bit */
+  GPIOx->LCKR = tmp;
+  /* Reset LCKK bit */
+  GPIOx->LCKR =  GPIO_Pin;
+  /* Set LCKK bit */
+  GPIOx->LCKR = tmp;
+  /* Read LCKK bit */
+  tmp = GPIOx->LCKR;
+  /* Read LCKK bit */
+  tmp = GPIOx->LCKR;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Group2 GPIO Read and Write
+ *  @brief   GPIO Read and Write
+ *
+@verbatim   
+ ===============================================================================
+                      ##### GPIO Read and Write #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Reads the specified input port pin.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @note   GPIOE is available only for STM32F072.
+  * @note   GPIOD is not available for STM32F031.   
+  * @param  GPIO_Pin: specifies the port bit to read.
+  * @note   This parameter can be GPIO_Pin_x where x can be:
+  *         For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF.
+  *         For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
+  *         For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF.  
+  * @retval The input port pin value.
+  */
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  uint8_t bitstatus = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+  if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
+  {
+    bitstatus = (uint8_t)Bit_SET;
+  }
+  else
+  {
+    bitstatus = (uint8_t)Bit_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Reads the specified input port pin.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @note   GPIOE is available only for STM32F072.
+  * @note   GPIOD is not available for STM32F031.   
+  * @retval The input port pin value.
+  */
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  return ((uint16_t)GPIOx->IDR);
+}
+
+/**
+  * @brief  Reads the specified output data port bit.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @note   GPIOE is available only for STM32F072.
+  * @note   GPIOD is not available for STM32F031.   
+  * @param  GPIO_Pin: Specifies the port bit to read.
+  * @note   This parameter can be GPIO_Pin_x where x can be:
+  *         For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF.
+  *         For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
+  *         For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF. 
+  * @retval The output port pin value.
+  */
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  uint8_t bitstatus = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+  if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
+  {
+    bitstatus = (uint8_t)Bit_SET;
+  }
+  else
+  {
+    bitstatus = (uint8_t)Bit_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Reads the specified GPIO output data port.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @note   GPIOE is available only for STM32F072.
+  * @note   GPIOD is not available for STM32F031.    
+  * @retval GPIO output data port value.
+  */
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  return ((uint16_t)GPIOx->ODR);
+}
+
+/**
+  * @brief  Sets the selected data port bits.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @note   GPIOE is available only for STM32F072.
+  * @note   GPIOD is not available for STM32F031.    
+  * @param  GPIO_Pin: specifies the port bits to be written.
+  * @note   This parameter can be GPIO_Pin_x where x can be:
+  *         For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF.
+  *         For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
+  *         For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF. 
+  * @retval None
+  */
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  GPIOx->BSRR = GPIO_Pin;
+}
+
+/**
+  * @brief  Clears the selected data port bits.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @note   GPIOE is available only for STM32F072.
+  * @note   GPIOD is not available for STM32F031.
+  * @param  GPIO_Pin: specifies the port bits to be written.
+  * @note   This parameter can be GPIO_Pin_x where x can be:
+  *         For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF.
+  *         For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
+  *         For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF. 
+  * @retval None
+  */
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  GPIOx->BRR = GPIO_Pin;
+}
+
+/**
+  * @brief  Sets or clears the selected data port bit.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @note   GPIOE is available only for STM32F072.
+  * @note   GPIOD is not available for STM32F031.  
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  * @param  BitVal: specifies the value to be written to the selected bit.
+  *          This parameter can be one of the BitAction enumeration values:
+  *            @arg Bit_RESET: to clear the port pin
+  *            @arg Bit_SET: to set the port pin
+  * @note   This parameter can be GPIO_Pin_x where x can be:
+  *         For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF.
+  *         For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
+  *         For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF.
+  * @retval None
+  */
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_BIT_ACTION(BitVal));
+
+  if (BitVal != Bit_RESET)
+  {
+    GPIOx->BSRR = GPIO_Pin;
+  }
+  else
+  {
+    GPIOx->BRR = GPIO_Pin ;
+  }
+}
+
+/**
+  * @brief  Writes data to the specified GPIO data port.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @note   GPIOE is available only for STM32F072.
+  * @note   GPIOD is not available for STM32F031.  
+  * @param  PortVal: specifies the value to be written to the port output data register.
+  * @retval None
+  */
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  GPIOx->ODR = PortVal;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Group3 GPIO Alternate functions configuration functions
+ *  @brief   GPIO Alternate functions configuration functions
+ *
+@verbatim   
+ ===============================================================================
+          ##### GPIO Alternate functions configuration functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Writes data to the specified GPIO data port.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @note   GPIOC, GPIOD, GPIOE and GPIOF  are available only for STM32F072 and STM32F091. 
+  * @param  GPIO_PinSource: specifies the pin for the Alternate function.
+  *          This parameter can be GPIO_PinSourcex where x can be (0..15) for GPIOA, GPIOB, GPIOD, GPIOE
+  *          and (0..12) for GPIOC and (0, 2..5, 9..10) for GPIOF.    
+  * @param  GPIO_AF: selects the pin to used as Alternate function.
+  *          This parameter can be one of the following value:
+  *            @arg GPIO_AF_0:  WKUP, EVENTOUT, TIM15, SPI1, TIM17, MCO, SWDAT, SWCLK,
+  *                             TIM14, BOOT, USART1, CEC, IR_OUT, SPI2, TIM3, USART4,
+  *                             CAN, USART2, CRS, TIM16, TIM1, TS, USART8 
+  *            @arg GPIO_AF_1: USART2, CEC, TIM3, USART1, USART2, EVENTOUT, I2C1,
+  *                            I2C2, TIM15, SPI2, USART3, TS, SPI1, USART7, USART8
+  *                            USART5, USART4, USART6, I2C1   
+  *            @arg GPIO_AF_2: TIM2, TIM1, EVENTOUT, TIM16, TIM17, USB, USART6, USART5,
+  *                            USART8, USART7, USART6  
+  *            @arg GPIO_AF_3: TS, I2C1, TIM15, EVENTOUT 
+  *            @arg GPIO_AF_4: TIM14, USART4, USART3, CRS, CAN, I2C1, USART5
+  *            @arg GPIO_AF_5: TIM16, TIM17, TIM15, SPI2, I2C2, USART6, MCO
+  *            @arg GPIO_AF_6: EVENTOUT
+  *            @arg GPIO_AF_7: COMP1 OUT, COMP2 OUT 
+  * @note   The pin should already been configured in Alternate Function mode(AF)
+  *         using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+  * @note   Refer to the Alternate function mapping table in the device datasheet 
+  *         for the detailed mapping of the system and peripherals'alternate 
+  *         function I/O pins.
+  * @retval None
+  */
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
+{
+  uint32_t temp = 0x00;
+  uint32_t temp_2 = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
+  assert_param(IS_GPIO_AF(GPIO_AF));
+
+  temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
+  GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
+  temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
+  GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_i2c.c b/system/src/stm32f0-stdperiph/stm32f0xx_i2c.c

new file mode 100644 (file)

index 0000000..c92c204
--- /dev/null
+++ b/system/src/stm32f0-stdperiph/stm32f0xx_i2c.c
@@ -0,0 +1,1585 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_i2c.c
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Inter-Integrated circuit (I2C):
+  *           + Initialization and Configuration
+  *           + Communications handling
+  *           + SMBUS management
+  *           + I2C registers management
+  *           + Data transfers management
+  *           + DMA transfers management
+  *           + Interrupts and flags management
+  *
+  *  @verbatim
+ ============================================================================
+                     ##### How to use this driver #####
+ ============================================================================
+   [..]
+   (#) Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE)
+       function for I2C1 or I2C2.
+   (#) Enable SDA, SCL  and SMBA (when used) GPIO clocks using 
+       RCC_AHBPeriphClockCmd() function. 
+   (#) Peripherals alternate function: 
+       (++) Connect the pin to the desired peripherals' Alternate 
+            Function (AF) using GPIO_PinAFConfig() function.
+       (++) Configure the desired pin in alternate function by:
+            GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+       (++) Select the type, OpenDrain and speed via  
+            GPIO_PuPd, GPIO_OType and GPIO_Speed members
+       (++) Call GPIO_Init() function.
+   (#) Program the Mode, Timing , Own address, Ack and Acknowledged Address 
+       using the I2C_Init() function.
+   (#) Optionally you can enable/configure the following parameters without
+       re-initialization (i.e there is no need to call again I2C_Init() function):
+       (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function.
+       (++) Enable the dual addressing mode using I2C_DualAddressCmd() function.
+       (++) Enable the general call using the I2C_GeneralCallCmd() function.
+       (++) Enable the clock stretching using I2C_StretchClockCmd() function.
+       (++) Enable the PEC Calculation using I2C_CalculatePEC() function.
+       (++) For SMBus Mode:
+            (+++) Enable the SMBusAlert pin using I2C_SMBusAlertCmd() function.
+   (#) Enable the NVIC and the corresponding interrupt using the function
+       I2C_ITConfig() if you need to use interrupt mode.
+   (#) When using the DMA mode 
+      (++) Configure the DMA using DMA_Init() function.
+      (++) Active the needed channel Request using I2C_DMACmd() function.
+   (#) Enable the I2C using the I2C_Cmd() function.
+   (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the 
+       transfers. 
+   [..]
+   (@) When using I2C in Fast Mode Plus, SCL and SDA pin 20mA current drive capability
+       must be enabled by setting the driving capability control bit in SYSCFG.
+
+    @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_i2c.h"
+#include "stm32f0xx_rcc.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup I2C 
+  * @brief I2C driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+#define CR1_CLEAR_MASK          ((uint32_t)0x00CFE0FF)  /*<! I2C CR1 clear register Mask */
+#define CR2_CLEAR_MASK          ((uint32_t)0x07FF7FFF)  /*<! I2C CR2 clear register Mask */
+#define TIMING_CLEAR_MASK       ((uint32_t)0xF0FFFFFF)  /*<! I2C TIMING clear register Mask */
+#define ERROR_IT_MASK           ((uint32_t)0x00003F00)  /*<! I2C Error interrupt register Mask */
+#define TC_IT_MASK              ((uint32_t)0x000000C0)  /*<! I2C TC interrupt register Mask */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup I2C_Private_Functions
+  * @{
+  */
+
+
+/** @defgroup I2C_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+           ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..] This section provides a set of functions allowing to initialize the I2C Mode,
+         I2C Timing, I2C filters, I2C Addressing mode, I2C OwnAddress1.
+
+    [..] The I2C_Init() function follows the I2C configuration procedures (these procedures 
+         are available in reference manual).
+
+    [..] When the Software Reset is performed using I2C_SoftwareResetCmd() function, the internal
+         states machines are reset and communication control bits, as well as status bits come 
+         back to their reset value.
+
+    [..] Before enabling Stop mode using I2C_StopModeCmd() I2C Clock source must be set to
+         HSI and Digital filters must be disabled.
+
+    [..] Before enabling Own Address 2 via I2C_DualAddressCmd() function, OA2 and mask should be
+         configured using I2C_OwnAddress2Config() function.
+
+    [..] I2C_SlaveByteControlCmd() enable Slave byte control that allow user to get control of 
+         each byte in slave mode when NBYTES is set to 0x01.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the I2Cx peripheral registers to their default reset values.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval None
+  */
+void I2C_DeInit(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+  if (I2Cx == I2C1)
+  {
+    /* Enable I2C1 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
+    /* Release I2C1 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
+  }
+  else
+  {
+    /* Enable I2C2 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
+    /* Release I2C2 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
+  }
+}
+
+/**
+  * @brief  Initializes the I2Cx peripheral according to the specified
+  *         parameters in the I2C_InitStruct.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
+  *         contains the configuration information for the specified I2C peripheral.
+  * @retval None
+  */
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_ANALOG_FILTER(I2C_InitStruct->I2C_AnalogFilter));
+  assert_param(IS_I2C_DIGITAL_FILTER(I2C_InitStruct->I2C_DigitalFilter));
+  assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
+  assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
+  assert_param(IS_I2C_ACK(I2C_InitStruct->I2C_Ack));
+  assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
+
+  /* Disable I2Cx Peripheral */
+  I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
+
+  /*---------------------------- I2Cx FILTERS Configuration ------------------*/
+  /* Get the I2Cx CR1 value */
+  tmpreg = I2Cx->CR1;
+  /* Clear I2Cx CR1 register */
+  tmpreg &= CR1_CLEAR_MASK;
+  /* Configure I2Cx: analog and digital filter */
+  /* Set ANFOFF bit according to I2C_AnalogFilter value */
+  /* Set DFN bits according to I2C_DigitalFilter value */
+  tmpreg |= (uint32_t)I2C_InitStruct->I2C_AnalogFilter |(I2C_InitStruct->I2C_DigitalFilter << 8);
+
+  /* Write to I2Cx CR1 */
+  I2Cx->CR1 = tmpreg;
+
+  /*---------------------------- I2Cx TIMING Configuration -------------------*/
+  /* Configure I2Cx: Timing */
+  /* Set TIMINGR bits according to I2C_Timing */
+  /* Write to I2Cx TIMING */
+  I2Cx->TIMINGR = I2C_InitStruct->I2C_Timing & TIMING_CLEAR_MASK;
+
+  /* Enable I2Cx Peripheral */
+  I2Cx->CR1 |= I2C_CR1_PE;
+
+  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
+  /* Clear tmpreg local variable */
+  tmpreg = 0;
+  /* Clear OAR1 register */
+  I2Cx->OAR1 = (uint32_t)tmpreg;
+  /* Clear OAR2 register */
+  I2Cx->OAR2 = (uint32_t)tmpreg;
+  /* Configure I2Cx: Own Address1 and acknowledged address */
+  /* Set OA1MODE bit according to I2C_AcknowledgedAddress value */
+  /* Set OA1 bits according to I2C_OwnAddress1 value */
+  tmpreg = (uint32_t)((uint32_t)I2C_InitStruct->I2C_AcknowledgedAddress | \
+                      (uint32_t)I2C_InitStruct->I2C_OwnAddress1);
+  /* Write to I2Cx OAR1 */
+  I2Cx->OAR1 = tmpreg;
+  /* Enable Own Address1 acknowledgement */
+  I2Cx->OAR1 |= I2C_OAR1_OA1EN;
+
+  /*---------------------------- I2Cx MODE Configuration ---------------------*/
+  /* Configure I2Cx: mode */
+  /* Set SMBDEN and SMBHEN bits according to I2C_Mode value */
+  tmpreg = I2C_InitStruct->I2C_Mode;
+  /* Write to I2Cx CR1 */
+  I2Cx->CR1 |= tmpreg;
+
+  /*---------------------------- I2Cx ACK Configuration ----------------------*/
+  /* Get the I2Cx CR2 value */
+  tmpreg = I2Cx->CR2;
+  /* Clear I2Cx CR2 register */
+  tmpreg &= CR2_CLEAR_MASK;
+  /* Configure I2Cx: acknowledgement */
+  /* Set NACK bit according to I2C_Ack value */
+  tmpreg |= I2C_InitStruct->I2C_Ack;
+  /* Write to I2Cx CR2 */
+  I2Cx->CR2 = tmpreg;
+}
+
+/**
+  * @brief  Fills each I2C_InitStruct member with its default value.
+  * @param  I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
+{
+  /*---------------- Reset I2C init structure parameters values --------------*/
+  /* Initialize the I2C_Timing member */
+  I2C_InitStruct->I2C_Timing = 0;
+  /* Initialize the I2C_AnalogFilter member */
+  I2C_InitStruct->I2C_AnalogFilter = I2C_AnalogFilter_Enable;
+  /* Initialize the I2C_DigitalFilter member */
+  I2C_InitStruct->I2C_DigitalFilter = 0;
+  /* Initialize the I2C_Mode member */
+  I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
+  /* Initialize the I2C_OwnAddress1 member */
+  I2C_InitStruct->I2C_OwnAddress1 = 0;
+  /* Initialize the I2C_Ack member */
+  I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
+  /* Initialize the I2C_AcknowledgedAddress member */
+  I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+}
+
+/**
+  * @brief  Enables or disables the specified I2C peripheral.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx peripheral. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C peripheral */
+    I2Cx->CR1 |= I2C_CR1_PE;
+  }
+  else
+  {
+    /* Disable the selected I2C peripheral */
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified I2C software reset.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval None
+  */
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+  /* Disable peripheral */
+  I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
+
+  /* Perform a dummy read to delay the disable of peripheral for minimum
+     3 APB clock cycles to perform the software reset functionality */
+  *(__IO uint32_t *)(uint32_t)I2Cx; 
+
+  /* Enable peripheral */
+  I2Cx->CR1 |= I2C_CR1_PE;
+}
+
+/**
+  * @brief  Enables or disables the specified I2C interrupts.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. 
+  *          This parameter can be any combination of the following values:
+  *            @arg I2C_IT_ERRI: Error interrupt mask
+  *            @arg I2C_IT_TCI: Transfer Complete interrupt mask
+  *            @arg I2C_IT_STOPI: Stop Detection interrupt mask
+  *            @arg I2C_IT_NACKI: Not Acknowledge received interrupt mask
+  *            @arg I2C_IT_ADDRI: Address Match interrupt mask  
+  *            @arg I2C_IT_RXI: RX interrupt mask
+  *            @arg I2C_IT_TXI: TX interrupt mask
+  * @param  NewState: new state of the specified I2C interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_I2C_CONFIG_IT(I2C_IT));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C interrupts */
+    I2Cx->CR1 |= I2C_IT;
+  }
+  else
+  {
+    /* Disable the selected I2C interrupts */
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_IT);
+  }
+}
+
+/**
+  * @brief  Enables or disables the I2C Clock stretching.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx Clock stretching.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable clock stretching */
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_NOSTRETCH);    
+  }
+  else
+  {
+    /* Disable clock stretching  */
+    I2Cx->CR1 |= I2C_CR1_NOSTRETCH;
+  }
+}
+
+/**
+  * @brief  Enables or disables I2C wakeup from stop mode.
+  *         This function is not applicable for  STM32F030 devices.  
+  * @param  I2Cx: where x can be 1 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx stop mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_1_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable wakeup from stop mode */
+    I2Cx->CR1 |= I2C_CR1_WUPEN;   
+  }
+  else
+  {
+    /* Disable wakeup from stop mode */    
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_WUPEN); 
+  }
+}
+
+/**
+  * @brief  Enables or disables the I2C own address 2.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C own address 2.
+  *          This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable own address 2 */
+    I2Cx->OAR2 |= I2C_OAR2_OA2EN;
+  }
+  else
+  {
+    /* Disable own address 2 */
+    I2Cx->OAR2 &= (uint32_t)~((uint32_t)I2C_OAR2_OA2EN);
+  }
+}    
+
+/**
+  * @brief  Configures the I2C slave own address 2 and mask.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Address: specifies the slave address to be programmed.
+  * @param  Mask: specifies own address 2 mask to be programmed.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_OA2_NoMask: no mask.
+  *            @arg I2C_OA2_Mask01: OA2[1] is masked and don't care.
+  *            @arg I2C_OA2_Mask02: OA2[2:1] are masked and don't care.
+  *            @arg I2C_OA2_Mask03: OA2[3:1] are masked and don't care.
+  *            @arg I2C_OA2_Mask04: OA2[4:1] are masked and don't care.
+  *            @arg I2C_OA2_Mask05: OA2[5:1] are masked and don't care.
+  *            @arg I2C_OA2_Mask06: OA2[6:1] are masked and don't care.
+  *            @arg I2C_OA2_Mask07: OA2[7:1] are masked and don't care.
+  * @retval None
+  */
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_OWN_ADDRESS2(Address));
+  assert_param(IS_I2C_OWN_ADDRESS2_MASK(Mask));
+  
+  /* Get the old register value */
+  tmpreg = I2Cx->OAR2;
+
+  /* Reset I2Cx OA2 bit [7:1] and OA2MSK bit [1:0]  */
+  tmpreg &= (uint32_t)~((uint32_t)(I2C_OAR2_OA2 | I2C_OAR2_OA2MSK));
+
+  /* Set I2Cx SADD */
+  tmpreg |= (uint32_t)(((uint32_t)Address & I2C_OAR2_OA2) | \
+            (((uint32_t)Mask << 8) & I2C_OAR2_OA2MSK)) ;
+
+  /* Store the new register value */
+  I2Cx->OAR2 = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the I2C general call mode.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C general call mode.
+  *          This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable general call mode */
+    I2Cx->CR1 |= I2C_CR1_GCEN;
+  }
+  else
+  {
+    /* Disable general call mode */
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_GCEN);
+  }
+} 
+
+/**
+  * @brief  Enables or disables the I2C slave byte control.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C slave byte control.
+  *          This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable slave byte control */
+    I2Cx->CR1 |= I2C_CR1_SBC;
+  }
+  else
+  {
+    /* Disable slave byte control */
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_SBC);
+  }
+}
+
+/**
+  * @brief  Configures the slave address to be transmitted after start generation.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Address: specifies the slave address to be programmed.
+  * @note   This function should be called before generating start condition.
+  * @retval None
+  */
+void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_SLAVE_ADDRESS(Address));
+               
+  /* Get the old register value */
+  tmpreg = I2Cx->CR2;
+
+  /* Reset I2Cx SADD bit [9:0] */
+  tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_SADD);
+
+  /* Set I2Cx SADD */
+  tmpreg |= (uint32_t)((uint32_t)Address & I2C_CR2_SADD);
+
+  /* Store the new register value */
+  I2Cx->CR2 = tmpreg;
+}
+  
+/**
+  * @brief  Enables or disables the I2C 10-bit addressing mode for the master.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C 10-bit addressing mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   This function should be called before generating start condition.
+  * @retval None
+  */
+void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable 10-bit addressing mode */
+    I2Cx->CR2 |= I2C_CR2_ADD10;
+  }
+  else
+  {
+    /* Disable 10-bit addressing mode */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_ADD10);
+  }
+} 
+
+/**
+  * @}
+  */
+
+
+/** @defgroup I2C_Group2 Communications handling functions
+ *  @brief   Communications handling functions 
+ *
+@verbatim
+ ===============================================================================
+                  ##### Communications handling functions #####
+ ===============================================================================  
+    [..] This section provides a set of functions that handles I2C communication.
+
+    [..] Automatic End mode is enabled using I2C_AutoEndCmd() function. When Reload
+         mode is enabled via I2C_ReloadCmd() AutoEnd bit has no effect.
+
+    [..] I2C_NumberOfBytesConfig() function set the number of bytes to be transferred,
+         this configuration should be done before generating start condition in master 
+         mode.
+
+    [..] When switching from master write operation to read operation in 10Bit addressing
+         mode, master can only sends the 1st 7 bits of the 10 bit address, followed by 
+         Read direction by enabling HEADR bit using I2C_10BitAddressHeader() function.
+
+    [..] In master mode, when transferring more than 255 bytes Reload mode should be used
+         to handle communication. In the first phase of transfer, Nbytes should be set to 
+         255. After transferring these bytes TCR flag is set and I2C_TransferHandling()
+         function should be called to handle remaining communication.
+
+    [..] In master mode, when software end mode is selected when all data is transferred
+         TC flag is set I2C_TransferHandling() function should be called to generate STOP
+         or generate ReStart.
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Enables or disables the I2C automatic end mode (stop condition is 
+  *         automatically sent when nbytes data are transferred).
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C automatic end mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   This function has effect if Reload mode is disabled.
+  * @retval None
+  */
+void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable Auto end mode */
+    I2Cx->CR2 |= I2C_CR2_AUTOEND;
+  }
+  else
+  {
+    /* Disable Auto end mode */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_AUTOEND);
+  }
+} 
+
+/**
+  * @brief  Enables or disables the I2C nbytes reload mode.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the nbytes reload mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable Auto Reload mode */
+    I2Cx->CR2 |= I2C_CR2_RELOAD;
+  }
+  else
+  {
+    /* Disable Auto Reload mode */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RELOAD);
+  }
+}
+
+/**
+  * @brief  Configures the number of bytes to be transmitted/received.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Number_Bytes: specifies the number of bytes to be programmed.
+  * @retval None
+  */
+void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+  /* Get the old register value */
+  tmpreg = I2Cx->CR2;
+
+  /* Reset I2Cx Nbytes bit [7:0] */
+  tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_NBYTES);
+
+  /* Set I2Cx Nbytes */
+  tmpreg |= (uint32_t)(((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES);
+
+  /* Store the new register value */
+  I2Cx->CR2 = tmpreg;
+}  
+  
+/**
+  * @brief  Configures the type of transfer request for the master.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_Direction: specifies the transfer request direction to be programmed.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_Direction_Transmitter: Master request a write transfer
+  *            @arg I2C_Direction_Receiver: Master request a read transfer  
+  * @retval None
+  */
+void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction)
+{
+/* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_DIRECTION(I2C_Direction));
+  
+  /* Test on the direction to set/reset the read/write bit */
+  if (I2C_Direction == I2C_Direction_Transmitter)
+  {
+    /* Request a write Transfer */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RD_WRN);
+  }
+  else
+  {
+    /* Request a read Transfer */
+    I2Cx->CR2 |= I2C_CR2_RD_WRN;
+  }
+}  
+  
+/**
+  * @brief  Generates I2Cx communication START condition.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C START condition generation.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Generate a START condition */
+    I2Cx->CR2 |= I2C_CR2_START;
+  }
+  else
+  {
+    /* Disable the START condition generation */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_START);
+  }
+}  
+  
+/**
+  * @brief  Generates I2Cx communication STOP condition.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C STOP condition generation.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Generate a STOP condition */
+    I2Cx->CR2 |= I2C_CR2_STOP;
+  }
+  else
+  {
+    /* Disable the STOP condition generation */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_STOP);
+  }
+}  
+
+/**
+  * @brief  Enables or disables the I2C 10-bit header only mode with read direction.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C 10-bit header only mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   This mode can be used only when switching from master transmitter mode 
+  *         to master receiver mode.
+  * @retval None
+  */
+void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable 10-bit header only mode */
+    I2Cx->CR2 |= I2C_CR2_HEAD10R;
+  }
+  else
+  {
+    /* Disable 10-bit header only mode */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_HEAD10R);
+  }
+}    
+
+/**
+  * @brief  Generates I2C communication Acknowledge.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the Acknowledge.
+  *          This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable ACK generation */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_NACK);    
+  }
+  else
+  {
+    /* Enable NACK generation */
+    I2Cx->CR2 |= I2C_CR2_NACK;
+  }
+}
+
+/**
+  * @brief  Returns the I2C slave matched address .
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval The value of the slave matched address .
+  */
+uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  
+  /* Return the slave matched address in the SR1 register */
+  return (uint8_t)(((uint32_t)I2Cx->ISR & I2C_ISR_ADDCODE) >> 16) ;
+}
+
+/**
+  * @brief  Returns the I2C slave received request.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval The value of the received request.
+  */
+uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx)
+{
+  uint32_t tmpreg = 0;
+  uint16_t direction = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  
+  /* Return the slave matched address in the SR1 register */
+  tmpreg = (uint32_t)(I2Cx->ISR & I2C_ISR_DIR);
+  
+  /* If write transfer is requested */
+  if (tmpreg == 0)
+  {
+    /* write transfer is requested */
+    direction = I2C_Direction_Transmitter;
+  }
+  else
+  {
+    /* Read transfer is requested */
+    direction = I2C_Direction_Receiver;
+  }  
+  return direction;
+}
+
+/**
+  * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Address: specifies the slave address to be programmed.
+  * @param  Number_Bytes: specifies the number of bytes to be programmed.
+  *          This parameter must be a value between 0 and 255.
+  * @param  ReloadEndMode: new state of the I2C START condition generation.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_Reload_Mode: Enable Reload mode .
+  *            @arg I2C_AutoEnd_Mode: Enable Automatic end mode.
+  *            @arg I2C_SoftEnd_Mode: Enable Software end mode.
+  * @param  StartStopMode: new state of the I2C START condition generation.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_No_StartStop: Don't Generate stop and start condition.
+  *            @arg I2C_Generate_Stop: Generate stop condition (Number_Bytes should be set to 0).
+  *            @arg I2C_Generate_Start_Read: Generate Restart for read request.
+  *            @arg I2C_Generate_Start_Write: Generate Restart for write request.
+  * @retval None
+  */
+void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_SLAVE_ADDRESS(Address));  
+  assert_param(IS_RELOAD_END_MODE(ReloadEndMode));
+  assert_param(IS_START_STOP_MODE(StartStopMode));
+    
+  /* Get the CR2 register value */
+  tmpreg = I2Cx->CR2;
+  
+  /* clear tmpreg specific bits */
+  tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
+  
+  /* update tmpreg */
+  tmpreg |= (uint32_t)(((uint32_t)Address & I2C_CR2_SADD) | (((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES) | \
+            (uint32_t)ReloadEndMode | (uint32_t)StartStopMode);
+  
+  /* update CR2 register */
+  I2Cx->CR2 = tmpreg;  
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup I2C_Group3 SMBUS management functions
+ *  @brief   SMBUS management functions 
+ *
+@verbatim
+ ===============================================================================
+                      ##### SMBUS management functions #####
+ ===============================================================================  
+    [..] This section provides a set of functions that handles SMBus communication
+         and timeouts detection.
+
+    [..] The SMBus Device default address (0b1100 001) is enabled by calling I2C_Init()
+         function and setting I2C_Mode member of I2C_InitTypeDef() structure to 
+         I2C_Mode_SMBusDevice.
+
+    [..] The SMBus Host address (0b0001 000) is enabled by calling I2C_Init()
+         function and setting I2C_Mode member of I2C_InitTypeDef() structure to 
+         I2C_Mode_SMBusHost.
+
+    [..] The Alert Response Address (0b0001 100) is enabled using I2C_SMBusAlertCmd()
+         function.
+
+    [..] To detect cumulative SCL stretch in master and slave mode, TIMEOUTB should be 
+         configured (in accordance to SMBus specification) using I2C_TimeoutBConfig() 
+         function then I2C_ExtendedClockTimeoutCmd() function should be called to enable
+         the detection.
+
+    [..] SCL low timeout is detected by configuring TIMEOUTB using I2C_TimeoutBConfig()
+         function followed by the call of I2C_ClockTimeoutCmd(). When adding to this 
+         procedure the call of I2C_IdleClockTimeoutCmd() function, Bus Idle condition 
+         (both SCL and SDA high) is detected also.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables I2C SMBus alert.
+  * @param  I2Cx: where x can be 1 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx SMBus alert.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_1_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable SMBus alert */
+    I2Cx->CR1 |= I2C_CR1_ALERTEN;   
+  }
+  else
+  {
+    /* Disable SMBus alert */    
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_ALERTEN); 
+  }
+}
+
+/**
+  * @brief  Enables or disables I2C Clock Timeout (SCL Timeout detection).
+  * @param  I2Cx: where x can be 1 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx clock Timeout.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_1_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable Clock Timeout */
+    I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIMOUTEN;   
+  }
+  else
+  {
+    /* Disable Clock Timeout */    
+    I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMOUTEN); 
+  }
+}
+
+/**
+  * @brief  Enables or disables I2C Extended Clock Timeout (SCL cumulative Timeout detection).
+  * @param  I2Cx: where x can be 1 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx Extended clock Timeout.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_1_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable Clock Timeout */
+    I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TEXTEN;   
+  }
+  else
+  {
+    /* Disable Clock Timeout */    
+    I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TEXTEN); 
+  }
+}
+
+/**
+  * @brief  Enables or disables I2C Idle Clock Timeout (Bus idle SCL and SDA 
+  *         high detection).
+  * @param  I2Cx: where x can be 1 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx Idle clock Timeout.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_1_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable Clock Timeout */
+    I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIDLE;   
+  }
+  else
+  {
+    /* Disable Clock Timeout */    
+    I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIDLE); 
+  }
+}
+
+/**
+  * @brief  Configures the I2C Bus Timeout A (SCL Timeout when TIDLE = 0 or Bus 
+  *         idle SCL and SDA high when TIDLE = 1).
+  * @param  I2Cx: where x can be 1 to select the I2C peripheral.
+  * @param  Timeout: specifies the TimeoutA to be programmed. 
+  * @retval None
+  */
+void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_1_PERIPH(I2Cx));
+  assert_param(IS_I2C_TIMEOUT(Timeout));
+    
+  /* Get the old register value */
+  tmpreg = I2Cx->TIMEOUTR;
+
+  /* Reset I2Cx TIMEOUTA bit [11:0] */
+  tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTA);
+
+  /* Set I2Cx TIMEOUTA */
+  tmpreg |= (uint32_t)((uint32_t)Timeout & I2C_TIMEOUTR_TIMEOUTA) ;
+
+  /* Store the new register value */
+  I2Cx->TIMEOUTR = tmpreg;
+}
+
+/**
+  * @brief  Configures the I2C Bus Timeout B (SCL cumulative Timeout).
+  * @param  I2Cx: where x can be 1 to select the I2C peripheral.
+  * @param  Timeout: specifies the TimeoutB to be programmed. 
+  * @retval None
+  */
+void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_1_PERIPH(I2Cx));
+  assert_param(IS_I2C_TIMEOUT(Timeout));
+
+  /* Get the old register value */
+  tmpreg = I2Cx->TIMEOUTR;
+
+  /* Reset I2Cx TIMEOUTB bit [11:0] */
+  tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTB);
+
+  /* Set I2Cx TIMEOUTB */
+  tmpreg |= (uint32_t)(((uint32_t)Timeout << 16) & I2C_TIMEOUTR_TIMEOUTB) ;
+
+  /* Store the new register value */
+  I2Cx->TIMEOUTR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables I2C PEC calculation.
+  * @param  I2Cx: where x can be 1 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx PEC calculation.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_1_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable PEC calculation */
+    I2Cx->CR1 |= I2C_CR1_PECEN;   
+  }
+  else
+  {
+    /* Disable PEC calculation */    
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PECEN); 
+  }
+}
+
+/**
+  * @brief  Enables or disables I2C PEC transmission/reception request.
+  * @param  I2Cx: where x can be 1 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx PEC request.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_1_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable PEC transmission/reception request */
+    I2Cx->CR2 |= I2C_CR2_PECBYTE;   
+  }
+  else
+  {
+    /* Disable PEC transmission/reception request */    
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_PECBYTE); 
+  }
+}
+
+/**
+  * @brief  Returns the I2C PEC.
+  * @param  I2Cx: where x can be 1 to select the I2C peripheral.
+  * @retval The value of the PEC .
+  */
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_1_PERIPH(I2Cx));
+  
+  /* Return the slave matched address in the SR1 register */
+  return (uint8_t)((uint32_t)I2Cx->PECR & I2C_PECR_PEC);
+}
+
+/**
+  * @}
+  */  
+
+
+/** @defgroup I2C_Group4 I2C registers management functions
+ *  @brief   I2C registers management functions 
+ *
+@verbatim
+ ===============================================================================
+                ##### I2C registers management functions #####
+ ===============================================================================  
+    [..] This section provides a functions that allow user the management of 
+         I2C registers.
+
+@endverbatim
+  * @{
+  */
+
+  /**
+  * @brief  Reads the specified I2C register and returns its value.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_Register: specifies the register to read.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_Register_CR1: CR1 register.
+  *            @arg I2C_Register_CR2: CR2 register.
+  *            @arg I2C_Register_OAR1: OAR1 register.
+  *            @arg I2C_Register_OAR2: OAR2 register.
+  *            @arg I2C_Register_TIMINGR: TIMING register.
+  *            @arg I2C_Register_TIMEOUTR: TIMEOUTR register.
+  *            @arg I2C_Register_ISR: ISR register.
+  *            @arg I2C_Register_ICR: ICR register.
+  *            @arg I2C_Register_PECR: PECR register.
+  *            @arg I2C_Register_RXDR: RXDR register.
+  *            @arg I2C_Register_TXDR: TXDR register.
+  * @retval The value of the read register.
+  */
+uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_REGISTER(I2C_Register));
+
+  tmp = (uint32_t)I2Cx;
+  tmp += I2C_Register;
+
+  /* Return the selected register value */
+  return (*(__IO uint32_t *) tmp);
+}
+
+/**
+  * @}
+  */  
+  
+/** @defgroup I2C_Group5 Data transfers management functions
+ *  @brief   Data transfers management functions 
+ *
+@verbatim
+ ===============================================================================
+                ##### Data transfers management functions #####
+ ===============================================================================  
+    [..] This subsection provides a set of functions allowing to manage 
+         the I2C data transfers.
+
+    [..] The read access of the I2C_RXDR register can be done using 
+         the I2C_ReceiveData() function and returns the received value.
+         Whereas a write access to the I2C_TXDR can be done using I2C_SendData()
+         function and stores the written data into TXDR.
+@endverbatim
+  * @{
+  */  
+  
+/**
+  * @brief  Sends a data byte through the I2Cx peripheral.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Data: Byte to be transmitted..
+  * @retval None
+  */
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  
+  /* Write in the DR register the data to be sent */
+  I2Cx->TXDR = (uint8_t)Data;
+}
+
+/**
+  * @brief  Returns the most recent received data by the I2Cx peripheral.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval The value of the received data.
+  */
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  
+  /* Return the data in the DR register */
+  return (uint8_t)I2Cx->RXDR;
+}  
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup I2C_Group6 DMA transfers management functions
+ *  @brief   DMA transfers management functions 
+ *
+@verbatim
+ ===============================================================================
+                ##### DMA transfers management functions #####
+ ===============================================================================  
+    [..] This section provides two functions that can be used only in DMA mode.
+    [..] In DMA Mode, the I2C communication can be managed by 2 DMA Channel 
+         requests:
+         (#) I2C_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
+         (#) I2C_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
+    [..] In this Mode it is advised to use the following function:
+         (+) I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState);
+@endverbatim
+  * @{
+  */  
+    
+/**
+  * @brief  Enables or disables the I2C DMA interface.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_DMAReq: specifies the I2C DMA transfer request to be enabled or disabled. 
+  *          This parameter can be any combination of the following values:
+  *            @arg I2C_DMAReq_Tx: Tx DMA transfer request
+  *            @arg I2C_DMAReq_Rx: Rx DMA transfer request
+  * @param  NewState: new state of the selected I2C DMA transfer request.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_I2C_DMA_REQ(I2C_DMAReq));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C DMA requests */
+    I2Cx->CR1 |= I2C_DMAReq;
+  }
+  else
+  {
+    /* Disable the selected I2C DMA requests */
+    I2Cx->CR1 &= (uint32_t)~I2C_DMAReq;
+  }
+}
+/**
+  * @}
+  */  
+
+
+/** @defgroup I2C_Group7 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions 
+ *
+@verbatim
+ ===============================================================================
+             ##### Interrupts and flags management functions  #####
+ ===============================================================================  
+    [..] This section provides functions allowing to configure the I2C Interrupts 
+         sources and check or clear the flags or pending bits status.
+         The user should identify which mode will be used in his application to manage 
+         the communication: Polling mode, Interrupt mode or DMA mode(refer I2C_Group6).
+
+  *** Polling Mode ***
+  ====================
+    [..] In Polling Mode, the I2C communication can be managed by 15 flags:
+        (#) I2C_FLAG_TXE: to indicate the status of Transmit data register empty flag.
+        (#) I2C_FLAG_TXIS: to indicate the status of Transmit interrupt status flag .
+        (#) I2C_FLAG_RXNE: to indicate the status of Receive data register not empty flag.
+        (#) I2C_FLAG_ADDR: to indicate the status of Address matched flag (slave mode).
+        (#) I2C_FLAG_NACKF: to indicate the status of NACK received flag.
+        (#) I2C_FLAG_STOPF: to indicate the status of STOP detection flag.
+        (#) I2C_FLAG_TC: to indicate the status of Transfer complete flag(master mode).
+        (#) I2C_FLAG_TCR: to indicate the status of Transfer complete reload flag.
+        (#) I2C_FLAG_BERR: to indicate the status of Bus error flag.
+        (#) I2C_FLAG_ARLO: to indicate the status of Arbitration lost flag.
+        (#) I2C_FLAG_OVR: to indicate the status of Overrun/Underrun flag.
+        (#) I2C_FLAG_PECERR: to indicate the status of PEC error in reception flag.
+        (#) I2C_FLAG_TIMEOUT: to indicate the status of Timeout or Tlow detection flag.
+        (#) I2C_FLAG_ALERT: to indicate the status of SMBus Alert flag.
+        (#) I2C_FLAG_BUSY: to indicate the status of Bus busy flag.
+
+    [..] In this Mode it is advised to use the following functions:
+        (+) FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+        (+) void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+
+    [..]
+        (@)Do not use the BUSY flag to handle each data transmission or reception.It is 
+           better to use the TXIS and RXNE flags instead.
+
+  *** Interrupt Mode ***
+  ======================
+    [..] In Interrupt Mode, the I2C communication can be managed by 7 interrupt sources
+         and 15 pending bits: 
+    [..] Interrupt Source:
+        (#) I2C_IT_ERRI: specifies the interrupt source for the Error interrupt.
+        (#) I2C_IT_TCI: specifies the interrupt source for the Transfer Complete interrupt.
+        (#) I2C_IT_STOPI: specifies the interrupt source for the Stop Detection interrupt.
+        (#) I2C_IT_NACKI: specifies the interrupt source for the Not Acknowledge received interrupt.
+        (#) I2C_IT_ADDRI: specifies the interrupt source for the Address Match interrupt.
+        (#) I2C_IT_RXI: specifies the interrupt source for the RX interrupt.
+        (#) I2C_IT_TXI: specifies the interrupt source for the TX interrupt.
+
+    [..] Pending Bits:
+        (#) I2C_IT_TXIS: to indicate the status of Transmit interrupt status flag.
+        (#) I2C_IT_RXNE: to indicate the status of Receive data register not empty flag.
+        (#) I2C_IT_ADDR: to indicate the status of Address matched flag (slave mode).
+        (#) I2C_IT_NACKF: to indicate the status of NACK received flag.
+        (#) I2C_IT_STOPF: to indicate the status of STOP detection flag.
+        (#) I2C_IT_TC: to indicate the status of Transfer complete flag (master mode).
+        (#) I2C_IT_TCR: to indicate the status of Transfer complete reload flag.
+        (#) I2C_IT_BERR: to indicate the status of Bus error flag.
+        (#) I2C_IT_ARLO: to indicate the status of Arbitration lost flag.
+        (#) I2C_IT_OVR: to indicate the status of Overrun/Underrun flag.
+        (#) I2C_IT_PECERR: to indicate the status of PEC error in reception flag.
+        (#) I2C_IT_TIMEOUT: to indicate the status of Timeout or Tlow detection flag.
+        (#) I2C_IT_ALERT: to indicate the status of SMBus Alert flag.
+
+    [..] In this Mode it is advised to use the following functions:
+        (+) void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+        (+) ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+
+@endverbatim
+  * @{
+  */  
+
+/**
+  * @brief  Checks whether the specified I2C flag is set or not.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_FLAG: specifies the flag to check. 
+  *          This parameter can be one of the following values:
+  *            @arg I2C_FLAG_TXE: Transmit data register empty
+  *            @arg I2C_FLAG_TXIS: Transmit interrupt status
+  *            @arg I2C_FLAG_RXNE: Receive data register not empty
+  *            @arg I2C_FLAG_ADDR: Address matched (slave mode)
+  *            @arg I2C_FLAG_NACKF: NACK received flag
+  *            @arg I2C_FLAG_STOPF: STOP detection flag
+  *            @arg I2C_FLAG_TC: Transfer complete (master mode)
+  *            @arg I2C_FLAG_TCR: Transfer complete reload
+  *            @arg I2C_FLAG_BERR: Bus error
+  *            @arg I2C_FLAG_ARLO: Arbitration lost
+  *            @arg I2C_FLAG_OVR: Overrun/Underrun
+  *            @arg I2C_FLAG_PECERR: PEC error in reception
+  *            @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
+  *            @arg I2C_FLAG_ALERT: SMBus Alert
+  *            @arg I2C_FLAG_BUSY: Bus busy
+  * @retval The new state of I2C_FLAG (SET or RESET).
+  */
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
+{
+  uint32_t tmpreg = 0;
+  FlagStatus bitstatus = RESET;
+  
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
+  
+  /* Get the ISR register value */
+  tmpreg = I2Cx->ISR;
+  
+  /* Get flag status */
+  tmpreg &= I2C_FLAG;
+  
+  if(tmpreg != 0)
+  {
+    /* I2C_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* I2C_FLAG is reset */
+    bitstatus = RESET;
+  }
+  return bitstatus;
+} 
+
+/**
+  * @brief  Clears the I2Cx's pending flags.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_FLAG: specifies the flag to clear. 
+  *          This parameter can be any combination of the following values:
+  *            @arg I2C_FLAG_ADDR: Address matched (slave mode)
+  *            @arg I2C_FLAG_NACKF: NACK received flag
+  *            @arg I2C_FLAG_STOPF: STOP detection flag
+  *            @arg I2C_FLAG_BERR: Bus error
+  *            @arg I2C_FLAG_ARLO: Arbitration lost
+  *            @arg I2C_FLAG_OVR: Overrun/Underrun
+  *            @arg I2C_FLAG_PECERR: PEC error in reception
+  *            @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
+  *            @arg I2C_FLAG_ALERT: SMBus Alert
+  * @retval The new state of I2C_FLAG (SET or RESET).
+  */
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
+{ 
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
+
+  /* Clear the selected flag */
+  I2Cx->ICR = I2C_FLAG;
+  }
+
+/**
+  * @brief  Checks whether the specified I2C interrupt has occurred or not.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_IT: specifies the interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_IT_TXIS: Transmit interrupt status
+  *            @arg I2C_IT_RXNE: Receive data register not empty
+  *            @arg I2C_IT_ADDR: Address matched (slave mode)
+  *            @arg I2C_IT_NACKF: NACK received flag
+  *            @arg I2C_IT_STOPF: STOP detection flag
+  *            @arg I2C_IT_TC: Transfer complete (master mode)
+  *            @arg I2C_IT_TCR: Transfer complete reload
+  *            @arg I2C_IT_BERR: Bus error
+  *            @arg I2C_IT_ARLO: Arbitration lost
+  *            @arg I2C_IT_OVR: Overrun/Underrun
+  *            @arg I2C_IT_PECERR: PEC error in reception
+  *            @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag
+  *            @arg I2C_IT_ALERT: SMBus Alert
+  * @retval The new state of I2C_IT (SET or RESET).
+  */
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
+{
+  uint32_t tmpreg = 0;
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_GET_IT(I2C_IT));
+
+  /* Check if the interrupt source is enabled or not */
+  /* If Error interrupt */
+  if ((uint32_t)(I2C_IT & ERROR_IT_MASK))
+  {
+    enablestatus = (uint32_t)((I2C_CR1_ERRIE) & (I2Cx->CR1));
+  }
+  /* If TC interrupt */
+  else if ((uint32_t)(I2C_IT & TC_IT_MASK))
+  {
+    enablestatus = (uint32_t)((I2C_CR1_TCIE) & (I2Cx->CR1));
+  }
+  else
+  {
+    enablestatus = (uint32_t)((I2C_IT) & (I2Cx->CR1));
+  }
+  
+  /* Get the ISR register value */
+  tmpreg = I2Cx->ISR;
+
+  /* Get flag status */
+  tmpreg &= I2C_IT;
+
+  /* Check the status of the specified I2C flag */
+  if((tmpreg != RESET) && enablestatus)
+  {
+    /* I2C_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* I2C_IT is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the I2C_IT status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the I2Cx's interrupt pending bits.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_IT: specifies the interrupt pending bit to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg I2C_IT_ADDR: Address matched (slave mode)
+  *            @arg I2C_IT_NACKF: NACK received flag
+  *            @arg I2C_IT_STOPF: STOP detection flag
+  *            @arg I2C_IT_BERR: Bus error
+  *            @arg I2C_IT_ARLO: Arbitration lost
+  *            @arg I2C_IT_OVR: Overrun/Underrun
+  *            @arg I2C_IT_PECERR: PEC error in reception
+  *            @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag
+  *            @arg I2C_IT_ALERT: SMBus Alert
+  * @retval The new state of I2C_IT (SET or RESET).
+  */
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_CLEAR_IT(I2C_IT));
+
+  /* Clear the selected flag */
+  I2Cx->ICR = I2C_IT;
+}
+
+/**
+  * @}
+  */  
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_iwdg.c b/system/src/stm32f0-stdperiph/stm32f0xx_iwdg.c

new file mode 100644 (file)

index 0000000..b864cb5
--- /dev/null
+++ b/system/src/stm32f0-stdperiph/stm32f0xx_iwdg.c
@@ -0,0 +1,293 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_iwdg.c
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Independent watchdog (IWDG) peripheral:           
+  *           + Prescaler and Counter configuration
+  *           + IWDG activation
+  *           + Flag management
+  *
+  *  @verbatim  
+  *  
+  ============================================================================== 
+                          ##### IWDG features #####
+  ============================================================================== 
+    [..] The IWDG can be started by either software or hardware (configurable
+         through option byte).
+             
+    [..] The IWDG is clocked by its own dedicated low-speed clock (LSI) and
+         thus stays active even if the main clock fails.
+         Once the IWDG is started, the LSI is forced ON and cannot be disabled
+         (LSI cannot be disabled too), and the counter starts counting down from 
+         the reset value of 0xFFF. When it reaches the end of count value (0x000)
+         a system reset is generated.
+         The IWDG counter should be reloaded at regular intervals to prevent
+         an MCU reset.
+                             
+    [..] The IWDG is implemented in the VDD voltage domain that is still functional
+         in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
+              
+    [..] IWDGRST flag in RCC_CSR register can be used to inform when a IWDG
+         reset occurs.
+              
+    [..] Min-max timeout value @40KHz (LSI): ~0.1ms / ~28.3s
+         The IWDG timeout may vary due to LSI frequency dispersion. STM32F0xx
+         devices provide the capability to measure the LSI frequency (LSI clock
+         should be seleted as RTC clock which is internally connected to TIM10 CH1
+         input capture). The measured value can be used to have an IWDG timeout with
+         an acceptable accuracy. 
+         For more information, please refer to the STM32F0xx Reference manual.
+            
+                          ##### How to use this driver ##### 
+  ============================================================================== 
+    [..] This driver allows to use IWDG peripheral with either window option enabled
+         or disabled. To do so follow one of the two procedures below.
+    (#) Window option is enabled:    
+        (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used
+             in software mode (no need to enable the LSI, it will be enabled
+             by hardware).        
+        (++) Enable write access to IWDG_PR and IWDG_RLR registers using
+             IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
+        (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function.
+        (++) Configure the IWDG counter value using IWDG_SetReload() function.
+             This value will be loaded in the IWDG counter each time the counter
+             is reloaded, then the IWDG will start counting down from this value.
+        (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function.
+        (++) Configure the IWDG refresh window using IWDG_SetWindowValue() function.
+
+    (#) Window option is disabled:    
+        (++) Enable write access to IWDG_PR and IWDG_RLR registers using
+             IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
+        (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function.
+        (++) Configure the IWDG counter value using IWDG_SetReload() function.
+             This value will be loaded in the IWDG counter each time the counter
+             is reloaded, then the IWDG will start counting down from this value.
+        (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function.
+        (++) reload the IWDG counter at regular intervals during normal operation 
+             to prevent an MCU reset, using IWDG_ReloadCounter() function.
+        (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used
+             in software mode (no need to enable the LSI, it will be enabled
+             by hardware).
+              
+    @endverbatim
+  *    
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_iwdg.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup IWDG 
+  * @brief IWDG driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ---------------------- IWDG registers bit mask ----------------------------*/
+/* KR register bit mask */
+#define KR_KEY_RELOAD    ((uint16_t)0xAAAA)
+#define KR_KEY_ENABLE    ((uint16_t)0xCCCC)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup IWDG_Private_Functions
+  * @{
+  */
+
+/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions
+ *  @brief   Prescaler and Counter configuration functions
+ *
+@verbatim   
+  ==============================================================================
+            ##### Prescaler and Counter configuration functions #####
+  ==============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables write access to IWDG_PR and IWDG_RLR registers.
+  * @param  IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
+  *          This parameter can be one of the following values:
+  *            @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
+  *            @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
+  * @retval None
+  */
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
+  IWDG->KR = IWDG_WriteAccess;
+}
+
+/**
+  * @brief  Sets IWDG Prescaler value.
+  * @param  IWDG_Prescaler: specifies the IWDG Prescaler value.
+  *          This parameter can be one of the following values:
+  *            @arg IWDG_Prescaler_4: IWDG prescaler set to 4
+  *            @arg IWDG_Prescaler_8: IWDG prescaler set to 8
+  *            @arg IWDG_Prescaler_16: IWDG prescaler set to 16
+  *            @arg IWDG_Prescaler_32: IWDG prescaler set to 32
+  *            @arg IWDG_Prescaler_64: IWDG prescaler set to 64
+  *            @arg IWDG_Prescaler_128: IWDG prescaler set to 128
+  *            @arg IWDG_Prescaler_256: IWDG prescaler set to 256
+  * @retval None
+  */
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
+  IWDG->PR = IWDG_Prescaler;
+}
+
+/**
+  * @brief  Sets IWDG Reload value.
+  * @param  Reload: specifies the IWDG Reload value.
+  *          This parameter must be a number between 0 and 0x0FFF.
+  * @retval None
+  */
+void IWDG_SetReload(uint16_t Reload)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_RELOAD(Reload));
+  IWDG->RLR = Reload;
+}
+
+/**
+  * @brief  Reloads IWDG counter with value defined in the reload register
+  *   (write access to IWDG_PR and IWDG_RLR registers disabled).
+  * @param  None
+  * @retval None
+  */
+void IWDG_ReloadCounter(void)
+{
+  IWDG->KR = KR_KEY_RELOAD;
+}
+
+
+/**
+  * @brief  Sets the IWDG window value.
+  * @param  WindowValue: specifies the window value to be compared to the downcounter.
+  * @retval None
+  */
+void IWDG_SetWindowValue(uint16_t WindowValue)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_WINDOW_VALUE(WindowValue));
+  IWDG->WINR = WindowValue;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Group2 IWDG activation function
+ *  @brief   IWDG activation function 
+ *
+@verbatim   
+ ==============================================================================
+                          ##### IWDG activation function #####
+ ==============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
+  * @param  None
+  * @retval None
+  */
+void IWDG_Enable(void)
+{
+  IWDG->KR = KR_KEY_ENABLE;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Group3 Flag management function 
+ *  @brief  Flag management function  
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Flag management function ##### 
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the specified IWDG flag is set or not.
+  * @param  IWDG_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg IWDG_FLAG_PVU: Prescaler Value Update on going
+  *            @arg IWDG_FLAG_RVU: Reload Value Update on going
+  *            @arg IWDG_FLAG_WVU: Counter Window Value Update on going
+  * @retval The new state of IWDG_FLAG (SET or RESET).
+  */
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_IWDG_FLAG(IWDG_FLAG));
+  if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_misc.c b/system/src/stm32f0-stdperiph/stm32f0xx_misc.c

new file mode 100644 (file)

index 0000000..d44d7fe
--- /dev/null
+++ b/system/src/stm32f0-stdperiph/stm32f0xx_misc.c
@@ -0,0 +1,167 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_misc.c
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file provides all the miscellaneous firmware functions (add-on
+  *          to CMSIS functions).
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_misc.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup MISC 
+  * @brief MISC driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup MISC_Private_Functions
+  * @{
+  */
+/**
+  *
+@verbatim
+ *******************************************************************************
+                   ##### Interrupts configuration functions #####
+ *******************************************************************************
+    [..] This section provide functions allowing to configure the NVIC interrupts
+        (IRQ). The Cortex-M0 exceptions are managed by CMSIS functions.
+         (#) Enable and Configure the priority of the selected IRQ Channels. 
+             The priority can be 0..3. 
+
+        -@- Lower priority values gives higher priority.
+        -@- Priority Order:
+            (#@) Lowest priority.
+            (#@) Lowest hardware priority (IRQn position).  
+  
+@endverbatim
+*/
+
+/**
+  * @brief  Initializes the NVIC peripheral according to the specified
+  *         parameters in the NVIC_InitStruct.
+  * @param  NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
+  *         the configuration information for the specified NVIC peripheral.
+  * @retval None
+  */
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
+{
+  uint32_t tmppriority = 0x00;
+  
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
+  assert_param(IS_NVIC_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPriority));  
+    
+  if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+  {
+    /* Compute the Corresponding IRQ Priority --------------------------------*/    
+    tmppriority = NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel >> 0x02];
+    tmppriority &= (uint32_t)(~(((uint32_t)0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8)));
+    tmppriority |= (uint32_t)((((uint32_t)NVIC_InitStruct->NVIC_IRQChannelPriority << 6) & 0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8));    
+    
+    NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel >> 0x02] = tmppriority;
+    
+    /* Enable the Selected IRQ Channels --------------------------------------*/
+    NVIC->ISER[0] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+  }
+  else
+  {
+    /* Disable the Selected IRQ Channels -------------------------------------*/
+    NVIC->ICER[0] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+  }
+}
+
+/**
+  * @brief  Selects the condition for the system to enter low power mode.
+  * @param  LowPowerMode: Specifies the new mode for the system to enter low power mode.
+  *          This parameter can be one of the following values:
+  *            @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.
+  *            @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
+  *            @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
+  * @param  NewState: new state of LP condition. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_LP(LowPowerMode));
+  
+  assert_param(IS_FUNCTIONAL_STATE(NewState));  
+  
+  if (NewState != DISABLE)
+  {
+    SCB->SCR |= LowPowerMode;
+  }
+  else
+  {
+    SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
+  }
+}
+
+/**
+  * @brief  Configures the SysTick clock source.
+  * @param  SysTick_CLKSource: specifies the SysTick clock source.
+  *          This parameter can be one of the following values:
+  *            @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
+  *            @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
+  * @retval None
+  */
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
+  
+  if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
+  {
+    SysTick->CTRL |= SysTick_CLKSource_HCLK;
+  }
+  else
+  {
+    SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_pwr.c b/system/src/stm32f0-stdperiph/stm32f0xx_pwr.c

new file mode 100644 (file)

index 0000000..e5779c6
--- /dev/null
+++ b/system/src/stm32f0-stdperiph/stm32f0xx_pwr.c
@@ -0,0 +1,566 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_pwr.c
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Power Controller (PWR) peripheral:
+  *           + Backup Domain Access
+  *           + PVD configuration
+  *           + WakeUp pins configuration
+  *           + Low Power modes configuration
+  *           + Flags management
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_pwr.h"
+#include "stm32f0xx_rcc.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup PWR 
+  * @brief PWR driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* ------------------ PWR registers bit mask ------------------------ */
+
+/* CR register bit mask */
+#define CR_DS_MASK               ((uint32_t)0xFFFFFFFC)
+#define CR_PLS_MASK              ((uint32_t)0xFFFFFF1F)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup PWR_Private_Functions
+  * @{
+  */
+
+/** @defgroup PWR_Group1 Backup Domain Access function 
+ *  @brief   Backup Domain Access function
+ *
+@verbatim
+  ==============================================================================
+                   ##### Backup Domain Access function #####
+  ==============================================================================
+
+    [..] After reset, the Backup Domain Registers (RCC BDCR Register, RTC registers
+         and RTC backup registers) are protected against possible stray write accesses.
+    [..] To enable access to Backup domain use the PWR_BackupAccessCmd(ENABLE) function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the PWR peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void PWR_DeInit(void)
+{
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
+}
+
+/**
+  * @brief  Enables or disables access to the Backup domain registers.
+  * @note   If the HSE divided by 32 is used as the RTC clock, the 
+  *         Backup Domain Access should be kept enabled.
+  * @param  NewState: new state of the access to the Backup domain registers.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_BackupAccessCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the Backup Domain Access */
+    PWR->CR |= PWR_CR_DBP;
+  }
+  else
+  {
+    /* Disable the Backup Domain Access */
+    PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_DBP);
+  } 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group2 PVD configuration functions
+ *  @brief   PVD configuration functions 
+ *
+@verbatim
+  ==============================================================================
+                    ##### PVD configuration functions #####
+  ==============================================================================
+  [..]
+  (+) The PVD is used to monitor the VDD power supply by comparing it to a threshold
+      selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
+  (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the 
+      PVD threshold. This event is internally connected to the EXTI line16
+      and can generate an interrupt if enabled through the EXTI registers.
+  (+) The PVD is stopped in Standby mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+  * @note   This function is not applicable for STM32F030 devices. 
+  * @param  PWR_PVDLevel: specifies the PVD detection level
+  *          This parameter can be one of the following values:
+  *             @arg PWR_PVDLevel_0
+  *             @arg PWR_PVDLevel_1
+  *             @arg PWR_PVDLevel_2
+  *             @arg PWR_PVDLevel_3
+  *             @arg PWR_PVDLevel_4
+  *             @arg PWR_PVDLevel_5
+  *             @arg PWR_PVDLevel_6
+  *             @arg PWR_PVDLevel_7
+  * @note   Refer to the electrical characteristics of your device datasheet for
+  *         more details about the voltage threshold corresponding to each 
+  *         detection level.
+  * @retval None
+  */
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
+  
+  tmpreg = PWR->CR;
+  
+  /* Clear PLS[7:5] bits */
+  tmpreg &= CR_PLS_MASK;
+  
+  /* Set PLS[7:5] bits according to PWR_PVDLevel value */
+  tmpreg |= PWR_PVDLevel;
+  
+  /* Store the new value */
+  PWR->CR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the Power Voltage Detector(PVD).
+  * @note   This function is not applicable for STM32F030 devices.    
+  * @param  NewState: new state of the PVD.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_PVDCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the PVD */
+    PWR->CR |= PWR_CR_PVDE;
+  }
+  else
+  {
+    /* Disable the PVD */
+    PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_PVDE);
+  } 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group3 WakeUp pins configuration functions
+ *  @brief   WakeUp pins configuration functions 
+ *
+@verbatim
+  ==============================================================================
+               ##### WakeUp pin configuration functions #####
+  ==============================================================================
+
+  (+) WakeUp pins are used to wakeup the system from Standby mode. These pins are 
+      forced in input pull down configuration and are active on rising edges.
+  (+) There are eight WakeUp pins: WakeUp Pin 1 on PA.00 and WakeUp Pin 2 on PC.13. 
+      The following WakeUp pins are only applicable for STM32F072 dvices:
+      WakeUp Pin 3 on PE.06, WakeUp Pin 4 on PA.02, WakeUp Pin 5 on PC.05, 
+      WakeUp Pin 6 on PB.05, WakeUp Pin 7 on PB.15 and WakeUp Pin 8 on PF.02.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the WakeUp Pin functionality.
+  * @param  PWR_WakeUpPin: specifies the WakeUpPin.
+  *          This parameter can be one of the following values
+  *             @arg PWR_WakeUpPin_1
+  *             @arg PWR_WakeUpPin_2
+  *             @arg PWR_WakeUpPin_3, only applicable for STM32F072 devices
+  *             @arg PWR_WakeUpPin_4, only applicable for STM32F072 devices
+  *             @arg PWR_WakeUpPin_5, only applicable for STM32F072 devices
+  *             @arg PWR_WakeUpPin_6, only applicable for STM32F072 devices
+  *             @arg PWR_WakeUpPin_7, only applicable for STM32F072 devices
+  *             @arg PWR_WakeUpPin_8, only applicable for STM32F072 devices            
+  * @param  NewState: new state of the WakeUp Pin functionality.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the EWUPx pin */
+    PWR->CSR |= PWR_WakeUpPin;
+  }
+  else
+  {
+    /* Disable the EWUPx pin */
+    PWR->CSR &= ~PWR_WakeUpPin;
+  }
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup PWR_Group4 Low Power modes configuration functions
+ *  @brief   Low Power modes configuration functions 
+ *
+@verbatim
+  ==============================================================================
+              ##### Low Power modes configuration functions #####
+  ==============================================================================
+
+    [..] The devices feature three low-power modes:
+    (+) Sleep mode: Cortex-M0 core stopped, peripherals kept running.
+    (+) Stop mode: all clocks are stopped, regulator running, regulator in low power mode
+    (+) Standby mode: VCORE domain powered off
+
+  *** Sleep mode *** 
+  ==================
+  [..] 
+    (+) Entry:
+        (++) The Sleep mode is entered by executing the WFE() or WFI() instructions.
+    (+) Exit:
+        (++) Any peripheral interrupt acknowledged by the nested vectored interrupt 
+             controller (NVIC) can wake up the device from Sleep mode.
+
+  *** Stop mode *** 
+  =================
+  [..] In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the HSI,
+       the HSI14 and the HSE RC oscillators are disabled. Internal SRAM and register 
+       contents are preserved.
+       The voltage regulator can be configured either in normal or low-power mode.
+
+    (+) Entry:
+        (++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,) 
+             function with regulator in LowPower or with Regulator ON.
+    (+) Exit:
+        (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode
+             or any internal IPs (I2C, UASRT or CEC) wakeup event.
+
+  *** Standby mode *** 
+  ====================
+  [..] The Standby mode allows to achieve the lowest power consumption. It is based 
+       on the Cortex-M0 deepsleep mode, with the voltage regulator disabled. 
+       The VCORE domain is consequently powered off. The PLL, the HSI, the HSI14 
+       oscillator and the HSE oscillator are also switched off. SRAM and register 
+       contents are lost except for the Backup domain (RTC registers, RTC backup 
+       registers and Standby circuitry).
+   
+  [..] The voltage regulator is OFF.
+
+    (+) Entry:
+        (++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
+    (+) Exit:
+        (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
+             tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
+
+  *** Auto-wakeup (AWU) from low-power mode *** 
+  =============================================
+  [..] The MCU can be woken up from low-power mode by an RTC Alarm event, a tamper 
+       event, a time-stamp event, or a comparator event, without depending on an 
+       external interrupt (Auto-wakeup mode).
+
+    (+) RTC auto-wakeup (AWU) from the Stop mode
+        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
+             (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt 
+                   or Event modes) using the EXTI_Init() function.
+             (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
+             (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() 
+                   and RTC_AlarmCmd() functions.
+        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it 
+             is necessary to:
+             (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt 
+                   or Event modes) using the EXTI_Init() function.
+             (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() 
+                   function.
+             (+++) Configure the RTC to detect the tamper or time stamp event using the
+                   RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
+                   functions.
+
+    (+) RTC auto-wakeup (AWU) from the Standby mode
+        (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
+             (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function.
+             (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() 
+                   and RTC_AlarmCmd() functions.
+        (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it 
+             is necessary to:
+             (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() 
+                   function.
+             (+++) Configure the RTC to detect the tamper or time stamp event using the
+                   RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
+                   functions.
+
+    (+) Comparator auto-wakeup (AWU) from the Stop mode
+        (++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup
+             event, it is necessary to:
+             (+++) Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2 
+                   to be sensitive to to the selected edges (falling, rising or falling 
+                   and rising) (Interrupt or Event modes) using the EXTI_Init() function.
+             (+++) Configure the comparator to generate the event.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enters Sleep mode.
+  * @note   In Sleep mode, all I/O pins keep the same state as in Run mode.
+  * @param  PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.
+  *          This parameter can be one of the following values:
+  *             @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
+  *             @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
+  * @retval None
+  */
+void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));
+
+  /* Clear SLEEPDEEP bit of Cortex-M0 System Control Register */
+  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+  
+  /* Select SLEEP mode entry -------------------------------------------------*/
+  if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __SEV();
+    __WFE(); 
+    __WFE();
+  }
+}
+
+/**
+  * @brief  Enters STOP mode.
+  * @note   In Stop mode, all I/O pins keep the same state as in Run mode.
+  * @note   When exiting Stop mode by issuing an interrupt or a wakeup event, 
+  *         the HSI RC oscillator is selected as system clock.
+  * @note   When the voltage regulator operates in low power mode, an additional 
+  *         startup delay is incurred when waking up from Stop mode. 
+  *         By keeping the internal regulator ON during Stop mode, the consumption 
+  *         is higher although the startup time is reduced.
+  * @param  PWR_Regulator: specifies the regulator state in STOP mode.
+  *         This parameter can be one of the following values:
+  *             @arg PWR_Regulator_ON: STOP mode with regulator ON
+  *             @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
+  * @param  PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
+  *         This parameter can be one of the following values:
+  *             @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
+  *             @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
+                @arg PWR_STOPEntry_SLEEPONEXIT: enter STOP mode with SLEEPONEXIT instruction
+  * @retval None
+  */
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR(PWR_Regulator));
+  assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
+  
+  /* Select the regulator state in STOP mode ---------------------------------*/
+  tmpreg = PWR->CR;
+  /* Clear PDDS and LPDSR bits */
+  tmpreg &= CR_DS_MASK;
+  
+  /* Set LPDSR bit according to PWR_Regulator value */
+  tmpreg |= PWR_Regulator;
+  
+  /* Store the new value */
+  PWR->CR = tmpreg;
+  
+  /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+  
+  /* Select STOP mode entry --------------------------------------------------*/
+  if(PWR_STOPEntry == PWR_STOPEntry_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI();
+    /* Reset SLEEPDEEP bit of Cortex System Control Register */
+    SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); 
+  }
+  else if (PWR_STOPEntry == PWR_STOPEntry_WFE)
+  {
+    /* Request Wait For Event */
+    __WFE();
+    /* Reset SLEEPDEEP bit of Cortex System Control Register */
+    SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);   
+  }
+  else
+  {
+    /* Set SLEEP on exit bit of Cortex-M0 System Control Register */
+    SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk;
+  }
+}
+
+/**
+  * @brief  Enters STANDBY mode.
+  * @note   In Standby mode, all I/O pins are high impedance except for:
+  *          - Reset pad (still available) 
+  *          - RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper, 
+  *             time-stamp, RTC Alarm out, or RTC clock calibration out.
+  *          - WKUP pin 1 (PA0) if enabled.
+  * @note The Wakeup flag (WUF) need to be cleared at application level before to call this function     
+  * @param  None
+  * @retval None
+  */
+void PWR_EnterSTANDBYMode(void)
+{
+  /* Select STANDBY mode */
+  PWR->CR |= PWR_CR_PDDS;
+
+  /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+  /* Request Wait For Interrupt */
+  __WFI();
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group5 Flags management functions
+ *  @brief   Flags management functions 
+ *
+@verbatim
+  ==============================================================================
+                       ##### Flags management functions #####
+  ==============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the specified PWR flag is set or not.
+  * @param  PWR_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *             @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup
+  *                  event was received from the WKUP pin or from the RTC alarm 
+  *                  (Alarm A or Alarm B), RTC Tamper event or RTC TimeStamp event.
+  *             @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the 
+  *                  system was resumed from StandBy mode.
+  *             @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD 
+  *                  is enabled by the PWR_PVDCmd() function.
+  *             @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag. 
+  *                  This flag indicates the state of the internal voltage 
+  *                  reference, VREFINT.
+  * @retval The new state of PWR_FLAG (SET or RESET).
+  */
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
+
+  if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the PWR's pending flags.
+  * @param  PWR_FLAG: specifies the flag to clear.
+  *          This parameter can be one of the following values:
+  *             @arg PWR_FLAG_WU: Wake Up flag
+  *             @arg PWR_FLAG_SB: StandBy flag
+  * @retval None
+  */
+void PWR_ClearFlag(uint32_t PWR_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
+
+  PWR->CR |=  PWR_FLAG << 2;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_rcc.c b/system/src/stm32f0-stdperiph/stm32f0xx_rcc.c

new file mode 100644 (file)

index 0000000..5b8af2c
--- /dev/null
+++ b/system/src/stm32f0-stdperiph/stm32f0xx_rcc.c
@@ -0,0 +1,1781 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_rcc.c
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Reset and clock control (RCC) peripheral:
+  *           + Internal/external clocks, PLL, CSS and MCO configuration
+  *           + System, AHB and APB busses clocks configuration
+  *           + Peripheral clocks configuration
+  *           + Interrupts and flags management
+  *
+ @verbatim
+
+ ===============================================================================
+                        ##### RCC specific features #####
+ ===============================================================================
+    [..] After reset the device is running from HSI (8 MHz) with Flash 0 WS, 
+         all peripherals are off except internal SRAM, Flash and SWD.
+         (#) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
+             all peripherals mapped on these busses are running at HSI speed.
+         (#) The clock for all peripherals is switched off, except the SRAM and FLASH.
+         (#) All GPIOs are in input floating state, except the SWD pins which
+             are assigned to be used for debug purpose.
+    [..] Once the device started from reset, the user application has to:
+         (#) Configure the clock source to be used to drive the System clock
+             (if the application needs higher frequency/performance)
+         (#) Configure the System clock frequency and Flash settings
+         (#) Configure the AHB and APB busses prescalers
+         (#) Enable the clock for the peripheral(s) to be used
+         (#) Configure the clock source(s) for peripherals which clocks are not
+             derived from the System clock (ADC, CEC, I2C, USART, RTC and IWDG)
+
+ @endverbatim
+  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_rcc.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup RCC 
+  * @brief RCC driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* ---------------------- RCC registers mask -------------------------------- */
+/* RCC Flag Mask */
+#define FLAG_MASK                 ((uint8_t)0x1F)
+
+/* CR register byte 2 (Bits[23:16]) base address */
+#define CR_BYTE2_ADDRESS          ((uint32_t)0x40021002)
+
+/* CFGR register byte 3 (Bits[31:23]) base address */
+#define CFGR_BYTE3_ADDRESS        ((uint32_t)0x40021007)
+
+/* CIR register byte 1 (Bits[15:8]) base address */
+#define CIR_BYTE1_ADDRESS         ((uint32_t)0x40021009)
+
+/* CIR register byte 2 (Bits[23:16]) base address */
+#define CIR_BYTE2_ADDRESS         ((uint32_t)0x4002100A)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RCC_Private_Functions
+  * @{
+  */
+
+/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
+ *  @brief   Internal and external clocks, PLL, CSS and MCO configuration functions 
+ *
+@verbatim
+ ===============================================================================
+ ##### Internal-external clocks, PLL, CSS and MCO configuration functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to configure the internal/external clocks,
+         PLL, CSS and MCO.
+         (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly 
+             or through the PLL as System clock source.
+             The HSI clock can be used also to clock the USART, I2C and CEC peripherals.
+         (#) HSI14 (high-speed internal for ADC), 14 MHz factory-trimmed RC used to clock
+             the ADC peripheral.
+         (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC
+             clock source.
+         (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
+             through the PLL as System clock source. Can be used also as RTC clock source.
+         (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. 
+             LSE can be used also to clock the USART and CEC peripherals.   
+         (#) PLL (clocked by HSI or HSE), for System clock.
+         (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs 
+             (HSE used directly or through PLL as System clock source), the System clock
+             is automatically switched to HSI and an interrupt is generated if enabled. 
+             The interrupt is linked to the Cortex-M0 NMI (Non-Maskable Interrupt) 
+             exception vector.   
+         (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSI14, LSI,
+             HSE, LSE or PLL (divided by 2) clock on PA8 pin.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Resets the RCC clock configuration to the default reset state.
+  * @note   The default reset state of the clock configuration is given below:
+  * @note      HSI ON and used as system clock source 
+  * @note      HSI14, HSE and PLL OFF
+  * @note      AHB, APB prescaler set to 1.
+  * @note      CSS and MCO OFF
+  * @note      All interrupts disabled
+  * @note   However, this function doesn't modify the configuration of the
+  * @note      Peripheral clocks
+  * @note      LSI, LSE and RTC clocks
+  * @param  None
+  * @retval None
+  */
+void RCC_DeInit(void)
+{
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+#if defined (STM32F051)
+  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */
+  RCC->CFGR &= (uint32_t)0xF8FFB80C;
+#else
+  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
+  RCC->CFGR &= (uint32_t)0x08FFB80C;
+#endif /* STM32F051 */
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+  RCC->CFGR &= (uint32_t)0xFFC0FFFF;
+
+  /* Reset PREDIV1[3:0] bits */
+  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+  /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFF0FEAC;
+  
+  /* Reset HSI14 bit */
+  RCC->CR2 &= (uint32_t)0xFFFFFFFE;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+}
+
+/**
+  * @brief  Configures the External High Speed oscillator (HSE).
+  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
+  *         software should wait on HSERDY flag to be set indicating that HSE clock
+  *         is stable and can be used to clock the PLL and/or system clock.
+  * @note   HSE state can not be changed if it is used directly or through the
+  *         PLL as system clock. In this case, you have to select another source
+  *         of the system clock then change the HSE state (ex. disable it).
+  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
+  * @note   This function resets the CSSON bit, so if the Clock security system(CSS)
+  *         was previously enabled you have to enable it again after calling this
+  *         function.
+  * @param  RCC_HSE: specifies the new state of the HSE.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
+  *                              6 HSE oscillator clock cycles.
+  *            @arg RCC_HSE_ON: turn ON the HSE oscillator
+  *            @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
+  * @retval None
+  */
+void RCC_HSEConfig(uint8_t RCC_HSE)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_HSE(RCC_HSE));
+
+  /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
+  *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE_OFF;
+
+  /* Set the new HSE configuration -------------------------------------------*/
+  *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE;
+
+}
+
+/**
+  * @brief  Waits for HSE start-up.
+  * @note   This function waits on HSERDY flag to be set and return SUCCESS if 
+  *         this flag is set, otherwise returns ERROR if the timeout is reached 
+  *         and this flag is not set. The timeout value is defined by the constant
+  *         HSE_STARTUP_TIMEOUT in stm32f0xx.h file. You can tailor it depending
+  *         on the HSE crystal used in your application.
+  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
+  * @param  None
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: HSE oscillator is stable and ready to use
+  *          - ERROR: HSE oscillator not yet ready
+  */
+ErrorStatus RCC_WaitForHSEStartUp(void)
+{
+  __IO uint32_t StartUpCounter = 0;
+  ErrorStatus status = ERROR;
+  FlagStatus HSEStatus = RESET;
+  
+  /* Wait till HSE is ready and if timeout is reached exit */
+  do
+  {
+    HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
+    StartUpCounter++;  
+  } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
+  
+  if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
+  {
+    status = SUCCESS;
+  }
+  else
+  {
+    status = ERROR;
+  }  
+  return (status);
+}
+
+/**
+  * @brief  Adjusts the Internal High Speed oscillator (HSI) calibration value.
+  * @note   The calibration is used to compensate for the variations in voltage
+  *         and temperature that influence the frequency of the internal HSI RC.
+  *         Refer to the Application Note AN4067 for more details on how to  
+  *         calibrate the HSI.
+  * @param  HSICalibrationValue: specifies the HSI calibration trimming value.
+  *          This parameter must be a number between 0 and 0x1F.
+  * @retval None
+  */
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));
+  
+  tmpreg = RCC->CR;
+  
+  /* Clear HSITRIM[4:0] bits */
+  tmpreg &= ~RCC_CR_HSITRIM;
+  
+  /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
+  tmpreg |= (uint32_t)HSICalibrationValue << 3;
+
+  /* Store the new value */
+  RCC->CR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the Internal High Speed oscillator (HSI).
+  * @note   After enabling the HSI, the application software should wait on 
+  *         HSIRDY flag to be set indicating that HSI clock is stable and can
+  *         be used to clock the PLL and/or system clock.
+  * @note   HSI can not be stopped if it is used directly or through the PLL
+  *         as system clock. In this case, you have to select another source 
+  *         of the system clock then stop the HSI.
+  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
+  * @param  NewState: new state of the HSI.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+  *         clock cycles.
+  * @retval None
+  */
+void RCC_HSICmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    RCC->CR |= RCC_CR_HSION;
+  }
+  else
+  {
+    RCC->CR &= ~RCC_CR_HSION;
+  }
+}
+
+/**
+  * @brief  Adjusts the Internal High Speed oscillator for ADC (HSI14) 
+  *         calibration value.
+  * @note   The calibration is used to compensate for the variations in voltage
+  *         and temperature that influence the frequency of the internal HSI RC.
+  *         Refer to the Application Note AN4067  for more details on how to  
+  *         calibrate the HSI14.
+  * @param  HSI14CalibrationValue: specifies the HSI14 calibration trimming value.
+  *          This parameter must be a number between 0 and 0x1F.
+  * @retval None
+  */
+void RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RCC_HSI14_CALIBRATION_VALUE(HSI14CalibrationValue));
+  
+  tmpreg = RCC->CR2;
+  
+  /* Clear HSI14TRIM[4:0] bits */
+  tmpreg &= ~RCC_CR2_HSI14TRIM;
+  
+  /* Set the HSITRIM14[4:0] bits according to HSI14CalibrationValue value */
+  tmpreg |= (uint32_t)HSI14CalibrationValue << 3;
+
+  /* Store the new value */
+  RCC->CR2 = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the Internal High Speed oscillator for ADC (HSI14).
+  * @note   After enabling the HSI14, the application software should wait on 
+  *         HSIRDY flag to be set indicating that HSI clock is stable and can
+  *         be used to clock the ADC.
+  * @note   The HSI14 is stopped by hardware when entering STOP and STANDBY modes.
+  * @param  NewState: new state of the HSI14.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator
+  *         clock cycles.
+  * @retval None
+  */
+void RCC_HSI14Cmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    RCC->CR2 |= RCC_CR2_HSI14ON;
+  }
+  else
+  {
+    RCC->CR2 &= ~RCC_CR2_HSI14ON;
+  }
+}
+
+/**
+  * @brief  Enables or disables the Internal High Speed oscillator request from ADC.
+  * @param  NewState: new state of the HSI14 ADC request.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_HSI14ADCRequestCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    RCC->CR2 &= ~RCC_CR2_HSI14DIS;
+  }
+  else
+  {
+    RCC->CR2 |= RCC_CR2_HSI14DIS;
+  }
+}
+
+/**
+  * @brief  Configures the External Low Speed oscillator (LSE).
+  * @note   As the LSE is in the Backup domain and write access is denied to this
+  *         domain after reset, you have to enable write access using 
+  *         PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
+  *         (to be done once after reset).
+  * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
+  *         software should wait on LSERDY flag to be set indicating that LSE clock
+  *         is stable and can be used to clock the RTC.
+  * @param  RCC_LSE: specifies the new state of the LSE.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
+  *                              6 LSE oscillator clock cycles.
+  *            @arg RCC_LSE_ON: turn ON the LSE oscillator
+  *            @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
+  * @retval None
+  */
+void RCC_LSEConfig(uint32_t RCC_LSE)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_LSE(RCC_LSE));
+
+  /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
+  /* Reset LSEON bit */
+  RCC->BDCR &= ~(RCC_BDCR_LSEON);
+
+  /* Reset LSEBYP bit */
+  RCC->BDCR &= ~(RCC_BDCR_LSEBYP);
+
+  /* Configure LSE */
+  RCC->BDCR |= RCC_LSE;
+}
+
+/**
+  * @brief  Configures the External Low Speed oscillator (LSE) drive capability.
+  * @param  RCC_LSEDrive: specifies the new state of the LSE drive capability.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LSEDrive_Low: LSE oscillator low drive capability.
+  *            @arg RCC_LSEDrive_MediumLow: LSE oscillator medium low drive capability.
+  *            @arg RCC_LSEDrive_MediumHigh: LSE oscillator medium high drive capability.
+  *            @arg RCC_LSEDrive_High: LSE oscillator high drive capability.
+  * @retval None
+  */
+void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_LSE_DRIVE(RCC_LSEDrive));
+  
+  /* Clear LSEDRV[1:0] bits */
+  RCC->BDCR &= ~(RCC_BDCR_LSEDRV);
+
+  /* Set the LSE Drive */
+  RCC->BDCR |= RCC_LSEDrive;
+}
+
+/**
+  * @brief  Enables or disables the Internal Low Speed oscillator (LSI).
+  * @note   After enabling the LSI, the application software should wait on 
+  *         LSIRDY flag to be set indicating that LSI clock is stable and can
+  *         be used to clock the IWDG and/or the RTC.
+  * @note   LSI can not be disabled if the IWDG is running.
+  * @param  NewState: new state of the LSI.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+  *         clock cycles.
+  * @retval None
+  */
+void RCC_LSICmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    RCC->CSR |= RCC_CSR_LSION;
+  }
+  else
+  {
+    RCC->CSR &= ~RCC_CSR_LSION;
+  }
+}
+
+/**
+  * @brief  Configures the PLL clock source and multiplication factor.
+  * @note   This function must be used only when the PLL is disabled.
+  *
+  * @param  RCC_PLLSource: specifies the PLL entry clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock selected as PLL clock source
+  *            @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
+  *            @arg RCC_PLLSource_HSI48 HSI48 oscillator clock selected as PLL clock source, applicable only for STM32F072 devices
+  *            @arg RCC_PLLSource_HSI: HSI clock selected as PLL clock entry, applicable only for STM32F072 devices
+  * @note   The minimum input clock frequency for PLL is 2 MHz (when using HSE as
+  *         PLL source).
+  *
+  * @param  RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock
+  *          This parameter can be RCC_PLLMul_x where x:[2,16] 
+  *
+  * @retval None
+  */
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
+  assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
+
+  /* Clear PLL Source [16] and Multiplier [21:18] bits */
+  RCC->CFGR &= ~(RCC_CFGR_PLLMULL | RCC_CFGR_PLLSRC);
+
+  /* Set the PLL Source and Multiplier */
+  RCC->CFGR |= (uint32_t)(RCC_PLLSource | RCC_PLLMul);
+}
+
+/**
+  * @brief  Enables or disables the PLL.
+  * @note   After enabling the PLL, the application software should wait on 
+  *         PLLRDY flag to be set indicating that PLL clock is stable and can
+  *         be used as system clock source.
+  * @note   The PLL can not be disabled if it is used as system clock source
+  * @note   The PLL is disabled by hardware when entering STOP and STANDBY modes.
+  * @param  NewState: new state of the PLL.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_PLLCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    RCC->CR |= RCC_CR_PLLON;
+  }
+  else
+  {
+    RCC->CR &= ~RCC_CR_PLLON;
+  }
+}
+
+/**
+  * @brief  Enables or disables the Internal High Speed oscillator for USB (HSI48).
+  *         This function is only applicable for STM32F072 devices.  
+  * @note   After enabling the HSI48, the application software should wait on 
+  *         HSI48RDY flag to be set indicating that HSI48 clock is stable and can
+  *         be used to clock the USB.
+  * @note   The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
+  * @param  NewState: new state of the HSI48.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_HSI48Cmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    RCC->CR2 |= RCC_CR2_HSI48ON;
+  }
+  else
+  {
+    RCC->CR2 &= ~RCC_CR2_HSI48ON;
+  }
+}
+
+/**
+  * @brief  Configures the PREDIV1 division factor.
+  * @note   This function must be used only when the PLL is disabled.
+  * @param  RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
+  *          This parameter can be RCC_PREDIV1_Divx where x:[1,16]
+  * @retval None
+  */
+void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));
+
+  tmpreg = RCC->CFGR2;
+  /* Clear PREDIV1[3:0] bits */
+  tmpreg &= ~(RCC_CFGR2_PREDIV1);
+  /* Set the PREDIV1 division factor */
+  tmpreg |= RCC_PREDIV1_Div;
+  /* Store the new value */
+  RCC->CFGR2 = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the Clock Security System.
+  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
+  *         is automatically disabled and an interrupt is generated to inform the
+  *         software about the failure (Clock Security System Interrupt, CSSI),
+  *         allowing the MCU to perform rescue operations. The CSSI is linked to 
+  *         the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector.
+  * @param  NewState: new state of the Clock Security System.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    RCC->CR |= RCC_CR_CSSON;
+  }
+  else
+  {
+    RCC->CR &= ~RCC_CR_CSSON;
+  }
+}
+
+#ifdef STM32F051
+/**
+  * @brief  Selects the clock source to output on MCO pin (PA8).
+  * @note   PA8 should be configured in alternate function mode.
+  * @param  RCC_MCOSource: specifies the clock source to output.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCOSource_NoClock: No clock selected.
+  *            @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected.
+  *            @arg RCC_MCOSource_LSI: LSI oscillator clock selected.
+  *            @arg RCC_MCOSource_LSE: LSE oscillator clock selected.
+  *            @arg RCC_MCOSource_SYSCLK: System clock selected.
+  *            @arg RCC_MCOSource_HSI: HSI oscillator clock selected.
+  *            @arg RCC_MCOSource_HSE: HSE oscillator clock selected.
+  *            @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected.
+  * @retval None
+  */
+void RCC_MCOConfig(uint8_t RCC_MCOSource)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
+
+  /* Select MCO clock source and prescaler */
+  *(__IO uint8_t *) CFGR_BYTE3_ADDRESS =  RCC_MCOSource;
+}
+#else
+
+/**
+  * @brief  Selects the clock source to output on MCO pin (PA8) and the corresponding
+  *         prescsaler.
+  * @note   PA8 should be configured in alternate function mode.
+  * @param  RCC_MCOSource: specifies the clock source to output.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCOSource_NoClock: No clock selected.
+  *            @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected.
+  *            @arg RCC_MCOSource_LSI: LSI oscillator clock selected.
+  *            @arg RCC_MCOSource_LSE: LSE oscillator clock selected.
+  *            @arg RCC_MCOSource_SYSCLK: System clock selected.
+  *            @arg RCC_MCOSource_HSI: HSI oscillator clock selected.
+  *            @arg RCC_MCOSource_HSE: HSE oscillator clock selected.
+  *            @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected.
+  *            @arg RCC_MCOSource_PLLCLK: PLL clock selected.
+  *            @arg RCC_MCOSource_HSI48: HSI48 clock selected.
+  * @param  RCC_MCOPrescaler: specifies the prescaler on MCO pin.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCOPrescaler_1: MCO clock is divided by 1.
+  *            @arg RCC_MCOPrescaler_2: MCO clock is divided by 2.
+  *            @arg RCC_MCOPrescaler_4: MCO clock is divided by 4.
+  *            @arg RCC_MCOPrescaler_8: MCO clock is divided by 8.
+  *            @arg RCC_MCOPrescaler_16: MCO clock is divided by 16.
+  *            @arg RCC_MCOPrescaler_32: MCO clock is divided by 32.
+  *            @arg RCC_MCOPrescaler_64: MCO clock is divided by 64.
+  *            @arg RCC_MCOPrescaler_128: MCO clock is divided by 128.    
+  * @retval None
+  */
+void RCC_MCOConfig(uint8_t RCC_MCOSource, uint32_t RCC_MCOPrescaler)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
+  assert_param(IS_RCC_MCO_PRESCALER(RCC_MCOPrescaler));
+    
+  /* Get CFGR value */  
+  tmpreg = RCC->CFGR;
+  /* Clear MCOPRE[2:0] bits */
+  tmpreg &= ~(RCC_CFGR_MCO_PRE | RCC_CFGR_MCO | RCC_CFGR_PLLNODIV);
+  /* Set the RCC_MCOSource and RCC_MCOPrescaler */
+  tmpreg |= (RCC_MCOPrescaler | ((uint32_t)RCC_MCOSource<<24));
+  /* Store the new value */
+  RCC->CFGR = tmpreg;
+}
+#endif /* STM32F072 */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions
+ *  @brief   System, AHB and APB busses clocks configuration functions
+ *
+@verbatim
+ ===============================================================================
+     ##### System, AHB and APB busses clocks configuration functions #####
+ ===============================================================================
+
+    [..] This section provide functions allowing to configure the System, AHB and 
+         APB busses clocks.
+         (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
+             HSE and PLL.
+             The AHB clock (HCLK) is derived from System clock through configurable prescaler
+             and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA and GPIO).
+             and APB (PCLK) clocks are derived from AHB clock through 
+             configurable prescalers and used to clock the peripherals mapped on these busses.
+             You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
+
+         -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
+             (+@) The ADC clock which is derived from HSI14 or APB (APB divided by a
+                  programmable prescaler: 2 or 4).
+             (+@) The CEC clock which is derived from LSE or HSI divided by 244.
+             (+@) The I2C clock which is derived from HSI or system clock (SYSCLK).
+             (+@) The USART clock which is derived from HSI, system clock (SYSCLK), APB or LSE.
+             (+@) The RTC/LCD clock which is derived from the LSE, LSI or 2 MHz HSE_RTC (HSE
+                  divided by a programmable prescaler).
+                  The System clock (SYSCLK) frequency must be higher or equal to the RTC/LCD
+                  clock frequency.
+             (+@) IWDG clock which is always the LSI clock.
+       
+         (#) The maximum frequency of the SYSCLK, HCLK and PCLK is 48 MHz.
+             Depending on the maximum frequency, the FLASH wait states (WS) should be 
+             adapted accordingly:
+        +--------------------------------------------- +
+        |  Wait states  |   HCLK clock frequency (MHz) |
+        |---------------|------------------------------|
+        |0WS(1CPU cycle)|       0 < HCLK <= 24         |
+        |---------------|------------------------------|
+        |1WS(2CPU cycle)|       24 < HCLK <= 48        |
+        +----------------------------------------------+
+
+         (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and 
+             prefetch is disabled.
+  
+    [..] It is recommended to use the following software sequences to tune the number
+         of wait states needed to access the Flash memory with the CPU frequency (HCLK).
+         (+) Increasing the CPU frequency
+         (++) Program the Flash Prefetch buffer, using "FLASH_PrefetchBufferCmd(ENABLE)" 
+              function
+         (++) Check that Flash Prefetch buffer activation is taken into account by 
+              reading FLASH_ACR using the FLASH_GetPrefetchBufferStatus() function
+         (++) Program Flash WS to 1, using "FLASH_SetLatency(FLASH_Latency_1)" function
+         (++) Check that the new number of WS is taken into account by reading FLASH_ACR
+         (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
+         (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
+         (++) Check that the new CPU clock source is taken into account by reading 
+              the clock source status, using "RCC_GetSYSCLKSource()" function 
+         (+) Decreasing the CPU frequency
+         (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
+         (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
+         (++) Check that the new CPU clock source is taken into account by reading 
+              the clock source status, using "RCC_GetSYSCLKSource()" function
+         (++) Program the new number of WS, using "FLASH_SetLatency()" function
+         (++) Check that the new number of WS is taken into account by reading FLASH_ACR
+         (++) Disable the Flash Prefetch buffer using "FLASH_PrefetchBufferCmd(DISABLE)" 
+              function
+         (++) Check that Flash Prefetch buffer deactivation is taken into account by reading FLASH_ACR
+              using the FLASH_GetPrefetchBufferStatus() function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the system clock (SYSCLK).
+  * @note   The HSI is used (enabled by hardware) as system clock source after
+  *         startup from Reset, wake-up from STOP and STANDBY mode, or in case
+  *         of failure of the HSE used directly or indirectly as system clock
+  *         (if the Clock Security System CSS is enabled).
+  * @note   A switch from one clock source to another occurs only if the target
+  *         clock source is ready (clock stable after startup delay or PLL locked). 
+  *         If a clock source which is not yet ready is selected, the switch will
+  *         occur when the clock source will be ready. 
+  *         You can use RCC_GetSYSCLKSource() function to know which clock is
+  *         currently used as system clock source.  
+  * @param  RCC_SYSCLKSource: specifies the clock source used as system clock source 
+  *          This parameter can be one of the following values:
+  *            @arg RCC_SYSCLKSource_HSI:    HSI selected as system clock source
+  *            @arg RCC_SYSCLKSource_HSE:    HSE selected as system clock source
+  *            @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
+  *            @arg RCC_SYSCLKSource_HSI48:  HSI48 selected as system clock source, applicable only for STM32F072 devices  
+  * @retval None
+  */
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
+  
+  tmpreg = RCC->CFGR;
+  
+  /* Clear SW[1:0] bits */
+  tmpreg &= ~RCC_CFGR_SW;
+  
+  /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
+  tmpreg |= RCC_SYSCLKSource;
+  
+  /* Store the new value */
+  RCC->CFGR = tmpreg;
+}
+
+/**
+  * @brief  Returns the clock source used as system clock.
+  * @param  None
+  * @retval The clock source used as system clock. The returned value can be one 
+  *         of the following values:
+  *           - 0x00: HSI used as system clock
+  *           - 0x04: HSE used as system clock  
+  *           - 0x08: PLL used as system clock
+  *           - 0x0C: HSI48 used as system clock, applicable only for STM32F072 devices  
+  */
+uint8_t RCC_GetSYSCLKSource(void)
+{
+  return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
+}
+
+/**
+  * @brief  Configures the AHB clock (HCLK).
+  * @param  RCC_SYSCLK: defines the AHB clock divider. This clock is derived from 
+  *         the system clock (SYSCLK).
+  *          This parameter can be one of the following values:
+  *            @arg RCC_SYSCLK_Div1:   AHB clock = SYSCLK
+  *            @arg RCC_SYSCLK_Div2:   AHB clock = SYSCLK/2
+  *            @arg RCC_SYSCLK_Div4:   AHB clock = SYSCLK/4
+  *            @arg RCC_SYSCLK_Div8:   AHB clock = SYSCLK/8
+  *            @arg RCC_SYSCLK_Div16:  AHB clock = SYSCLK/16
+  *            @arg RCC_SYSCLK_Div64:  AHB clock = SYSCLK/64
+  *            @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
+  *            @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
+  *            @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
+  * @retval None
+  */
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RCC_HCLK(RCC_SYSCLK));
+  
+  tmpreg = RCC->CFGR;
+  
+  /* Clear HPRE[3:0] bits */
+  tmpreg &= ~RCC_CFGR_HPRE;
+  
+  /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
+  tmpreg |= RCC_SYSCLK;
+  
+  /* Store the new value */
+  RCC->CFGR = tmpreg;
+}
+
+/**
+  * @brief  Configures the APB clock (PCLK).
+  * @param  RCC_HCLK: defines the APB clock divider. This clock is derived from 
+  *         the AHB clock (HCLK).
+  *          This parameter can be one of the following values:
+  *            @arg RCC_HCLK_Div1: APB clock = HCLK
+  *            @arg RCC_HCLK_Div2: APB clock = HCLK/2
+  *            @arg RCC_HCLK_Div4: APB clock = HCLK/4
+  *            @arg RCC_HCLK_Div8: APB clock = HCLK/8
+  *            @arg RCC_HCLK_Div16: APB clock = HCLK/16
+  * @retval None
+  */
+void RCC_PCLKConfig(uint32_t RCC_HCLK)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RCC_PCLK(RCC_HCLK));
+  
+  tmpreg = RCC->CFGR;
+  
+  /* Clear PPRE[2:0] bits */
+  tmpreg &= ~RCC_CFGR_PPRE;
+  
+  /* Set PPRE[2:0] bits according to RCC_HCLK value */
+  tmpreg |= RCC_HCLK;
+  
+  /* Store the new value */
+  RCC->CFGR = tmpreg;
+}
+
+/**
+  * @brief  Configures the ADC clock (ADCCLK).
+  * @note   This function is obsolete.
+  *         For proper ADC clock selection, refer to ADC_ClockModeConfig() in the ADC driver
+  * @param  RCC_ADCCLK: defines the ADC clock source. This clock is derived 
+  *         from the HSI14 or APB clock (PCLK).
+  *          This parameter can be one of the following values:
+  *             @arg RCC_ADCCLK_HSI14: ADC clock = HSI14 (14MHz)
+  *             @arg RCC_ADCCLK_PCLK_Div2: ADC clock = PCLK/2
+  *             @arg RCC_ADCCLK_PCLK_Div4: ADC clock = PCLK/4  
+  * @retval None
+  */
+void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK)
+{ 
+  /* Check the parameters */
+  assert_param(IS_RCC_ADCCLK(RCC_ADCCLK));
+
+  /* Clear ADCPRE bit */
+  RCC->CFGR &= ~RCC_CFGR_ADCPRE;
+  /* Set ADCPRE bits according to RCC_PCLK value */
+  RCC->CFGR |= RCC_ADCCLK & 0xFFFF;
+
+  /* Clear ADCSW bit */
+  RCC->CFGR3 &= ~RCC_CFGR3_ADCSW; 
+  /* Set ADCSW bits according to RCC_ADCCLK value */
+  RCC->CFGR3 |= RCC_ADCCLK >> 16;  
+}
+
+/**
+  * @brief  Configures the CEC clock (CECCLK).
+  * @param  RCC_CECCLK: defines the CEC clock source. This clock is derived 
+  *         from the HSI or LSE clock.
+  *          This parameter can be one of the following values:
+  *             @arg RCC_CECCLK_HSI_Div244: CEC clock = HSI/244 (32768Hz)
+  *             @arg RCC_CECCLK_LSE: CEC clock = LSE
+  * @retval None
+  */
+void RCC_CECCLKConfig(uint32_t RCC_CECCLK)
+{ 
+  /* Check the parameters */
+  assert_param(IS_RCC_CECCLK(RCC_CECCLK));
+
+  /* Clear CECSW bit */
+  RCC->CFGR3 &= ~RCC_CFGR3_CECSW;
+  /* Set CECSW bits according to RCC_CECCLK value */
+  RCC->CFGR3 |= RCC_CECCLK;
+}
+
+/**
+  * @brief  Configures the I2C1 clock (I2C1CLK).
+  * @param  RCC_I2CCLK: defines the I2C1 clock source. This clock is derived 
+  *         from the HSI or System clock.
+  *          This parameter can be one of the following values:
+  *             @arg RCC_I2C1CLK_HSI: I2C1 clock = HSI
+  *             @arg RCC_I2C1CLK_SYSCLK: I2C1 clock = System Clock
+  * @retval None
+  */
+void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK)
+{ 
+  /* Check the parameters */
+  assert_param(IS_RCC_I2CCLK(RCC_I2CCLK));
+
+  /* Clear I2CSW bit */
+  RCC->CFGR3 &= ~RCC_CFGR3_I2C1SW;
+  /* Set I2CSW bits according to RCC_I2CCLK value */
+  RCC->CFGR3 |= RCC_I2CCLK;
+}
+
+/**
+  * @brief  Configures the USART1 clock (USART1CLK).
+  * @param  RCC_USARTCLK: defines the USART clock source. This clock is derived 
+  *         from the HSI or System clock.
+  *          This parameter can be one of the following values:
+  *             @arg RCC_USART1CLK_PCLK: USART1 clock = APB Clock (PCLK)
+  *             @arg RCC_USART1CLK_SYSCLK: USART1 clock = System Clock
+  *             @arg RCC_USART1CLK_LSE: USART1 clock = LSE Clock
+  *             @arg RCC_USART1CLK_HSI: USART1 clock = HSI Clock
+  *             @arg RCC_USART2CLK_PCLK: USART2 clock = APB Clock (PCLK), applicable only for STM32F072 and STM32F091 devices
+  *             @arg RCC_USART2CLK_SYSCLK: USART2 clock = System Clock, applicable only for STM32F072 and STM32F091 devices
+  *             @arg RCC_USART2CLK_LSE: USART2 clock = LSE Clock, applicable only for STM32F072 and STM32F091 devices
+  *             @arg RCC_USART2CLK_HSI: USART2 clock = HSI Clock, applicable only for STM32F072 and STM32F091 devices  
+  *             @arg RCC_USART3CLK_PCLK: USART3 clock = APB Clock (PCLK), applicable only for STM32F091 devices
+  *             @arg RCC_USART3CLK_SYSCLK: USART3 clock = System Clock, applicable only for STM32F091 devices
+  *             @arg RCC_USART3CLK_LSE: USART3 clock = LSE Clock, applicable only for STM32F091 devices
+  *             @arg RCC_USART3CLK_HSI: USART3 clock = HSI Clock, applicable only for STM32F091 devices   
+  * @retval None
+  */
+void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK)
+{ 
+  uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RCC_USARTCLK(RCC_USARTCLK));
+
+  /* Get USART index */
+  tmp = (RCC_USARTCLK >> 28);
+
+  /* Clear USARTSW[1:0] bit */
+  if (tmp == (uint32_t)0x00000001)
+  {
+    /* Clear USART1SW[1:0] bit */  
+    RCC->CFGR3 &= ~RCC_CFGR3_USART1SW;
+  }
+  else if (tmp == (uint32_t)0x00000002)
+  {
+    /* Clear USART2SW[1:0] bit */
+    RCC->CFGR3 &= ~RCC_CFGR3_USART2SW;
+  }
+  else 
+  {
+    /* Clear USART3SW[1:0] bit */
+    RCC->CFGR3 &= ~RCC_CFGR3_USART3SW;
+  }
+
+  /* Set USARTxSW bits according to RCC_USARTCLK value */
+  RCC->CFGR3 |= RCC_USARTCLK;
+}
+
+/**
+  * @brief  Configures the USB clock (USBCLK).
+  *         This function is only applicable for STM32F072 devices.  
+  * @param  RCC_USBCLK: defines the USB clock source. This clock is derived 
+  *         from the HSI48 or system clock.
+  *          This parameter can be one of the following values:
+  *             @arg RCC_USBCLK_HSI48: USB clock = HSI48
+  *             @arg RCC_USBCLK_PLLCLK: USB clock = PLL clock
+  * @retval None
+  */
+void RCC_USBCLKConfig(uint32_t RCC_USBCLK)
+{ 
+  /* Check the parameters */
+  assert_param(IS_RCC_USBCLK(RCC_USBCLK));
+
+  /* Clear USBSW bit */
+  RCC->CFGR3 &= ~RCC_CFGR3_USBSW;
+  /* Set USBSW bits according to RCC_USBCLK value */
+  RCC->CFGR3 |= RCC_USBCLK;
+}
+
+/**
+  * @brief  Returns the frequencies of the System, AHB and APB busses clocks.
+  * @note    The frequency returned by this function is not the real frequency
+  *           in the chip. It is calculated based on the predefined constant and
+  *           the source selected by RCC_SYSCLKConfig():
+  *                                              
+  * @note     If SYSCLK source is HSI, function returns constant HSI_VALUE(*)
+  *                                              
+  * @note     If SYSCLK source is HSE, function returns constant HSE_VALUE(**)
+  *                          
+  * @note     If SYSCLK source is PLL, function returns constant HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *               
+  * @note     If SYSCLK source is HSI48, function returns constant HSI48_VALUE(***) 
+  *             
+  * @note     (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value
+  *               8 MHz) but the real value may vary depending on the variations
+  *               in voltage and temperature, refer to RCC_AdjustHSICalibrationValue().   
+  *    
+  * @note     (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value
+  *                8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *                frequency of the crystal used. Otherwise, this function may
+  *                return wrong result.
+  *
+  * @note     (***) HSI48_VALUE is a constant defined in stm32f0xx.h file (default value
+  *                 48 MHz) but the real value may vary depending on the variations
+  *                 in voltage and temperature.
+  *                                   
+  * @note   The result of this function could be not correct when using fractional
+  *         value for HSE crystal.   
+  *             
+  * @param  RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold 
+  *         the clocks frequencies. 
+  *     
+  * @note   This function can be used by the user application to compute the 
+  *         baudrate for the communication peripherals or configure other parameters.
+  * @note   Each time SYSCLK, HCLK and/or PCLK clock changes, this function
+  *         must be called to update the structure's field. Otherwise, any
+  *         configuration based on this function will be incorrect.
+  *    
+  * @retval None
+  */
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0, presc = 0, pllclk = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        pllclk = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        /* HSE oscillator clock selected as PREDIV1 clock entry */
+        pllclk = (HSE_VALUE / prediv1factor) * pllmull; 
+      }
+      RCC_Clocks->SYSCLK_Frequency = pllclk;      
+      break;
+    case 0x0C:  /* HSI48 used as system clock */
+      RCC_Clocks->SYSCLK_Frequency = HSI48_VALUE;
+      break;
+    default: /* HSI used as system clock */
+      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK, PCLK clocks frequencies -----------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = RCC->CFGR & RCC_CFGR_HPRE;
+  tmp = tmp >> 4;
+  presc = APBAHBPrescTable[tmp]; 
+  /* HCLK clock frequency */
+  RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
+
+  /* Get PCLK prescaler */
+  tmp = RCC->CFGR & RCC_CFGR_PPRE;
+  tmp = tmp >> 8;
+  presc = APBAHBPrescTable[tmp];
+  /* PCLK clock frequency */
+  RCC_Clocks->PCLK_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+
+  /* ADCCLK clock frequency */
+  if((RCC->CFGR3 & RCC_CFGR3_ADCSW) != RCC_CFGR3_ADCSW)
+  {
+    /* ADC Clock is HSI14 Osc. */
+    RCC_Clocks->ADCCLK_Frequency = HSI14_VALUE;
+  }
+  else
+  {
+    if((RCC->CFGR & RCC_CFGR_ADCPRE) != RCC_CFGR_ADCPRE)
+    {
+      /* ADC Clock is derived from PCLK/2 */
+      RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK_Frequency >> 1;
+    }
+    else
+    {
+      /* ADC Clock is derived from PCLK/4 */
+      RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK_Frequency >> 2;
+    }
+    
+  }
+
+  /* CECCLK clock frequency */
+  if((RCC->CFGR3 & RCC_CFGR3_CECSW) != RCC_CFGR3_CECSW)
+  {
+    /* CEC Clock is HSI/244 */
+    RCC_Clocks->CECCLK_Frequency = HSI_VALUE / 244;
+  }
+  else
+  {
+    /* CECC Clock is LSE Osc. */
+    RCC_Clocks->CECCLK_Frequency = LSE_VALUE;
+  }
+
+  /* I2C1CLK clock frequency */
+  if((RCC->CFGR3 & RCC_CFGR3_I2C1SW) != RCC_CFGR3_I2C1SW)
+  {
+    /* I2C1 Clock is HSI Osc. */
+    RCC_Clocks->I2C1CLK_Frequency = HSI_VALUE;
+  }
+  else
+  {
+    /* I2C1 Clock is System Clock */
+    RCC_Clocks->I2C1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+  }
+
+  /* USART1CLK clock frequency */
+  if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == 0x0)
+  {
+    /* USART1 Clock is PCLK */
+    RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->PCLK_Frequency;
+  }
+  else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_0)
+  {
+    /* USART1 Clock is System Clock */
+    RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+  }
+  else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_1)
+  {
+    /* USART1 Clock is LSE Osc. */
+    RCC_Clocks->USART1CLK_Frequency = LSE_VALUE;
+  }
+  else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW)
+  {
+    /* USART1 Clock is HSI Osc. */
+    RCC_Clocks->USART1CLK_Frequency = HSI_VALUE;
+  }
+  
+  /* USART2CLK clock frequency */
+  if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == 0x0)
+  {
+    /* USART Clock is PCLK */
+    RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->PCLK_Frequency;
+  }
+  else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_0)
+  {
+    /* USART Clock is System Clock */
+    RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+  }
+  else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_1)
+  {
+    /* USART Clock is LSE Osc. */
+    RCC_Clocks->USART2CLK_Frequency = LSE_VALUE;
+  }
+  else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW)
+  {
+    /* USART Clock is HSI Osc. */
+    RCC_Clocks->USART2CLK_Frequency = HSI_VALUE;
+  }
+  
+  /* USART3CLK clock frequency */
+  if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == 0x0)
+  {
+    /* USART Clock is PCLK */
+    RCC_Clocks->USART3CLK_Frequency = RCC_Clocks->PCLK_Frequency;
+  }
+  else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW_0)
+  {
+    /* USART Clock is System Clock */
+    RCC_Clocks->USART3CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+  }
+  else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW_1)
+  {
+    /* USART Clock is LSE Osc. */
+    RCC_Clocks->USART3CLK_Frequency = LSE_VALUE;
+  }
+  else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW)
+  {
+    /* USART Clock is HSI Osc. */
+    RCC_Clocks->USART3CLK_Frequency = HSI_VALUE;
+  }
+  
+  /* USBCLK clock frequency */
+  if((RCC->CFGR3 & RCC_CFGR3_USBSW) != RCC_CFGR3_USBSW)
+  {
+    /* USB Clock is HSI48 */
+    RCC_Clocks->USBCLK_Frequency = HSI48_VALUE;
+  }
+  else
+  {
+    /* USB Clock is PLL clock */
+    RCC_Clocks->USBCLK_Frequency = pllclk;
+  }   
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Group3 Peripheral clocks configuration functions
+ *  @brief   Peripheral clocks configuration functions 
+ *
+@verbatim
+ ===============================================================================
+             #####Peripheral clocks configuration functions #####
+ ===============================================================================  
+
+    [..] This section provide functions allowing to configure the Peripheral clocks. 
+         (#) The RTC clock which is derived from the LSE, LSI or  HSE_Div32 (HSE
+             divided by 32).
+         (#) After restart from Reset or wakeup from STANDBY, all peripherals are off
+             except internal SRAM, Flash and SWD. Before to start using a peripheral you
+             have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd(),
+             RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.
+         (#) To reset the peripherals configuration (to the default state after device reset)
+             you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and 
+             RCC_APB1PeriphResetCmd() functions.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the RTC clock (RTCCLK).
+  * @note   As the RTC clock configuration bits are in the Backup domain and write
+  *         access is denied to this domain after reset, you have to enable write
+  *         access using PWR_BackupAccessCmd(ENABLE) function before to configure
+  *         the RTC clock source (to be done once after reset).    
+  * @note   Once the RTC clock is configured it can't be changed unless the RTC
+  *         is reset using RCC_BackupResetCmd function, or by a Power On Reset (POR)
+  *             
+  * @param  RCC_RTCCLKSource: specifies the RTC clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
+  *            @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
+  *            @arg RCC_RTCCLKSource_HSE_Div32: HSE divided by 32 selected as RTC clock
+  *       
+  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
+  *         work in STOP and STANDBY modes, and can be used as wakeup source.
+  *         However, when the HSE clock is used as RTC clock source, the RTC
+  *         cannot be used in STOP and STANDBY modes.
+  *             
+  * @note   The maximum input clock frequency for RTC is 2MHz (when using HSE as
+  *         RTC clock source).
+  *                          
+  * @retval None
+  */
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
+  
+  /* Select the RTC clock source */
+  RCC->BDCR |= RCC_RTCCLKSource;
+}
+
+/**
+  * @brief  Enables or disables the RTC clock.
+  * @note   This function must be used only after the RTC clock source was selected
+  *         using the RCC_RTCCLKConfig function.
+  * @param  NewState: new state of the RTC clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_RTCCLKCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    RCC->BDCR |= RCC_BDCR_RTCEN;
+  }
+  else
+  {
+    RCC->BDCR &= ~RCC_BDCR_RTCEN;
+  }
+}
+
+/**
+  * @brief  Forces or releases the Backup domain reset.
+  * @note   This function resets the RTC peripheral (including the backup registers)
+  *         and the RTC clock source selection in RCC_BDCR register.
+  * @param  NewState: new state of the Backup domain reset.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_BackupResetCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    RCC->BDCR |= RCC_BDCR_BDRST;
+  }
+  else
+  {
+    RCC->BDCR &= ~RCC_BDCR_BDRST;
+  }
+}
+
+/**
+  * @brief  Enables or disables the AHB peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.    
+  * @param  RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
+  *          This parameter can be any combination of the following values:
+  *             @arg RCC_AHBPeriph_GPIOA: GPIOA clock
+  *             @arg RCC_AHBPeriph_GPIOB: GPIOB clock
+  *             @arg RCC_AHBPeriph_GPIOC: GPIOC clock
+  *             @arg RCC_AHBPeriph_GPIOD: GPIOD clock
+  *             @arg RCC_AHBPeriph_GPIOE: GPIOE clock, applicable only for STM32F072 devices  
+  *             @arg RCC_AHBPeriph_GPIOF: GPIOF clock
+  *             @arg RCC_AHBPeriph_TS:    TS clock
+  *             @arg RCC_AHBPeriph_CRC:   CRC clock
+  *             @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode)  
+  *             @arg RCC_AHBPeriph_SRAM:  SRAM clock
+  *             @arg RCC_AHBPeriph_DMA1:  DMA1 clock
+  *             @arg RCC_AHBPeriph_DMA2:  DMA2 clock  
+  * @param  NewState: new state of the specified peripheral clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    RCC->AHBENR |= RCC_AHBPeriph;
+  }
+  else
+  {
+    RCC->AHBENR &= ~RCC_AHBPeriph;
+  }
+}
+
+/**
+  * @brief  Enables or disables the High Speed APB (APB2) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @param  RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
+  *          This parameter can be any combination of the following values:
+  *             @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
+  *             @arg RCC_APB2Periph_USART6: USART6 clock  
+  *             @arg RCC_APB2Periph_USART7: USART7 clock
+  *             @arg RCC_APB2Periph_USART8: USART8 clock   
+  *             @arg RCC_APB2Periph_ADC1:   ADC1 clock
+  *             @arg RCC_APB2Periph_TIM1:   TIM1 clock
+  *             @arg RCC_APB2Periph_SPI1:   SPI1 clock
+  *             @arg RCC_APB2Periph_USART1: USART1 clock   
+  *             @arg RCC_APB2Periph_TIM15:  TIM15 clock
+  *             @arg RCC_APB2Periph_TIM16:  TIM16 clock
+  *             @arg RCC_APB2Periph_TIM17:  TIM17 clock
+  *             @arg RCC_APB2Periph_DBGMCU: DBGMCU clock
+  * @param  NewState: new state of the specified peripheral clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->APB2ENR |= RCC_APB2Periph;
+  }
+  else
+  {
+    RCC->APB2ENR &= ~RCC_APB2Periph;
+  }
+}
+
+/**
+  * @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @param  RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
+  *          This parameter can be any combination of the following values:
+  *           @arg RCC_APB1Periph_TIM2:   TIM2 clock, applicable only for STM32F051 and STM32F072 devices
+  *           @arg RCC_APB1Periph_TIM3:   TIM3 clock
+  *           @arg RCC_APB1Periph_TIM6:   TIM6 clock
+  *           @arg RCC_APB1Periph_TIM7:   TIM7 clock, applicable only for STM32F072 devices   
+  *           @arg RCC_APB1Periph_TIM14:  TIM14 clock
+  *           @arg RCC_APB1Periph_WWDG:   WWDG clock
+  *           @arg RCC_APB1Periph_SPI2:   SPI2 clock
+  *           @arg RCC_APB1Periph_USART2: USART2 clock
+  *           @arg RCC_APB1Periph_USART3: USART3 clock, applicable only for STM32F072 and STM32F091 devices 
+  *           @arg RCC_APB1Periph_USART4: USART4 clock, applicable only for STM32F072 and STM32F091 devices
+  *           @arg RCC_APB1Periph_USART5: USART5 clock, applicable only for STM32F091 devices         
+  *           @arg RCC_APB1Periph_I2C1:   I2C1 clock
+  *           @arg RCC_APB1Periph_I2C2:   I2C2 clock
+  *           @arg RCC_APB1Periph_USB:    USB clock, applicable only for STM32F042 and STM32F072 devices 
+  *           @arg RCC_APB1Periph_CAN:    CAN clock, applicable only for STM32F042 and STM32F072 devices 
+  *           @arg RCC_APB1Periph_CRS:    CRS clock , applicable only for STM32F042 and STM32F072 devices      
+  *           @arg RCC_APB1Periph_PWR:    PWR clock
+  *           @arg RCC_APB1Periph_DAC:    DAC clock, applicable only for STM32F051 and STM32F072 devices 
+  *           @arg RCC_APB1Periph_CEC:    CEC clock, applicable only for STM32F051, STM32F042 and STM32F072 devices                               
+  * @param  NewState: new state of the specified peripheral clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->APB1ENR |= RCC_APB1Periph;
+  }
+  else
+  {
+    RCC->APB1ENR &= ~RCC_APB1Periph;
+  }
+}
+
+/**
+  * @brief  Forces or releases AHB peripheral reset.
+  * @param  RCC_AHBPeriph: specifies the AHB peripheral to reset.
+  *          This parameter can be any combination of the following values:
+  *             @arg RCC_AHBPeriph_GPIOA: GPIOA clock
+  *             @arg RCC_AHBPeriph_GPIOB: GPIOB clock
+  *             @arg RCC_AHBPeriph_GPIOC: GPIOC clock
+  *             @arg RCC_AHBPeriph_GPIOD: GPIOD clock
+  *             @arg RCC_AHBPeriph_GPIOE: GPIOE clock, applicable only for STM32F072 devices  
+  *             @arg RCC_AHBPeriph_GPIOF: GPIOF clock
+  *             @arg RCC_AHBPeriph_TS:    TS clock
+  * @param  NewState: new state of the specified peripheral reset.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_AHB_RST_PERIPH(RCC_AHBPeriph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->AHBRSTR |= RCC_AHBPeriph;
+  }
+  else
+  {
+    RCC->AHBRSTR &= ~RCC_AHBPeriph;
+  }
+}
+
+/**
+  * @brief  Forces or releases High Speed APB (APB2) peripheral reset.
+  * @param  RCC_APB2Periph: specifies the APB2 peripheral to reset.
+  *          This parameter can be any combination of the following values:
+  *             @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
+  *             @arg RCC_APB2Periph_USART6: USART6 clock  
+  *             @arg RCC_APB2Periph_USART7: USART7 clock
+  *             @arg RCC_APB2Periph_USART8: USART8 clock   
+  *             @arg RCC_APB2Periph_ADC1:   ADC1 clock
+  *             @arg RCC_APB2Periph_TIM1:   TIM1 clock
+  *             @arg RCC_APB2Periph_SPI1:   SPI1 clock
+  *             @arg RCC_APB2Periph_USART1: USART1 clock
+  *             @arg RCC_APB2Periph_TIM15:  TIM15 clock
+  *             @arg RCC_APB2Periph_TIM16:  TIM16 clock
+  *             @arg RCC_APB2Periph_TIM17:  TIM17 clock
+  *             @arg RCC_APB2Periph_DBGMCU: DBGMCU clock
+  * @param  NewState: new state of the specified peripheral reset.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->APB2RSTR |= RCC_APB2Periph;
+  }
+  else
+  {
+    RCC->APB2RSTR &= ~RCC_APB2Periph;
+  }
+}
+
+/**
+  * @brief  Forces or releases Low Speed APB (APB1) peripheral reset.
+  * @param  RCC_APB1Periph: specifies the APB1 peripheral to reset.
+  *          This parameter can be any combination of the following values:
+  *           @arg RCC_APB1Periph_TIM2:   TIM2 clock, applicable only for STM32F051 and STM32F072 devices
+  *           @arg RCC_APB1Periph_TIM3:   TIM3 clock
+  *           @arg RCC_APB1Periph_TIM6:   TIM6 clock
+  *           @arg RCC_APB1Periph_TIM7:   TIM7 clock, applicable only for STM32F072 devices   
+  *           @arg RCC_APB1Periph_TIM14:  TIM14 clock
+  *           @arg RCC_APB1Periph_WWDG:   WWDG clock
+  *           @arg RCC_APB1Periph_SPI2:   SPI2 clock
+  *           @arg RCC_APB1Periph_USART2: USART2 clock
+  *           @arg RCC_APB1Periph_USART3: USART3 clock, applicable only for STM32F072 and STM32F091 devices 
+  *           @arg RCC_APB1Periph_USART4: USART4 clock, applicable only for STM32F072 and STM32F091 devices
+  *           @arg RCC_APB1Periph_USART5: USART5 clock, applicable only for STM32F091 devices         
+  *           @arg RCC_APB1Periph_I2C1:   I2C1 clock
+  *           @arg RCC_APB1Periph_I2C2:   I2C2 clock
+  *           @arg RCC_APB1Periph_USB:    USB clock, applicable only for STM32F042 and STM32F072 devices 
+  *           @arg RCC_APB1Periph_CAN:    CAN clock, applicable only for STM32F042 and STM32F072 devices 
+  *           @arg RCC_APB1Periph_CRS:    CRS clock , applicable only for STM32F042 and STM32F072 devices      
+  *           @arg RCC_APB1Periph_PWR:    PWR clock
+  *           @arg RCC_APB1Periph_DAC:    DAC clock, applicable only for STM32F051 and STM32F072 devices 
+  *           @arg RCC_APB1Periph_CEC:    CEC clock, applicable only for STM32F051, STM32F042 and STM32F072 devices    
+  * @param  NewState: new state of the specified peripheral clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->APB1RSTR |= RCC_APB1Periph;
+  }
+  else
+  {
+    RCC->APB1RSTR &= ~RCC_APB1Periph;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Group4 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions 
+ *
+@verbatim
+ ===============================================================================
+             ##### Interrupts and flags management functions #####
+ ===============================================================================
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified RCC interrupts.
+  * @note   The CSS interrupt doesn't have an enable bit; once the CSS is enabled
+  *         and if the HSE clock fails, the CSS interrupt occurs and an NMI is
+  *         automatically generated. The NMI will be executed indefinitely, and 
+  *         since NMI has higher priority than any other IRQ (and main program)
+  *         the application will be stacked in the NMI ISR unless the CSS interrupt
+  *         pending bit is cleared.
+  * @param  RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *              @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *              @arg RCC_IT_LSERDY: LSE ready interrupt
+  *              @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *              @arg RCC_IT_HSERDY: HSE ready interrupt
+  *              @arg RCC_IT_PLLRDY: PLL ready interrupt
+  *              @arg RCC_IT_HSI14RDY: HSI14 ready interrupt
+  *              @arg RCC_IT_HSI48RDY: HSI48 ready interrupt, applicable only for STM32F072 devices  
+  * @param  NewState: new state of the specified RCC interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_IT(RCC_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Perform Byte access to RCC_CIR[13:8] bits to enable the selected interrupts */
+    *(__IO uint8_t *) CIR_BYTE1_ADDRESS |= RCC_IT;
+  }
+  else
+  {
+    /* Perform Byte access to RCC_CIR[13:8] bits to disable the selected interrupts */
+    *(__IO uint8_t *) CIR_BYTE1_ADDRESS &= (uint8_t)~RCC_IT;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified RCC flag is set or not.
+  * @param  RCC_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *             @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready  
+  *             @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
+  *             @arg RCC_FLAG_PLLRDY: PLL clock ready
+  *             @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
+  *             @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+  *             @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset 
+  *             @arg RCC_FLAG_PINRST: Pin reset
+  *             @arg RCC_FLAG_V18PWRRSTF:  V1.8 power domain reset  
+  *             @arg RCC_FLAG_PORRST: POR/PDR reset
+  *             @arg RCC_FLAG_SFTRST: Software reset
+  *             @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
+  *             @arg RCC_FLAG_WWDGRST: Window Watchdog reset
+  *             @arg RCC_FLAG_LPWRRST: Low Power reset
+  *             @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready
+  *             @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready, applicable only for STM32F072 devices    
+  * @retval The new state of RCC_FLAG (SET or RESET).
+  */
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
+{
+  uint32_t tmp = 0;
+  uint32_t statusreg = 0;
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_FLAG(RCC_FLAG));
+
+  /* Get the RCC register index */
+  tmp = RCC_FLAG >> 5;
+
+  if (tmp == 0)               /* The flag to check is in CR register */
+  {
+    statusreg = RCC->CR;
+  }
+  else if (tmp == 1)          /* The flag to check is in BDCR register */
+  {
+    statusreg = RCC->BDCR;
+  }
+  else if (tmp == 2)          /* The flag to check is in CSR register */
+  {
+    statusreg = RCC->CSR;
+  }
+  else                        /* The flag to check is in CR2 register */
+  {
+    statusreg = RCC->CR2;
+  }    
+
+  /* Get the flag position */
+  tmp = RCC_FLAG & FLAG_MASK;
+
+  if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the RCC reset flags.
+  *         The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_V18PWRRSTF,
+  *         RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST,
+  *         RCC_FLAG_LPWRRST.
+  * @param  None
+  * @retval None
+  */
+void RCC_ClearFlag(void)
+{
+  /* Set RMVF bit to clear the reset flags */
+  RCC->CSR |= RCC_CSR_RMVF;
+}
+
+/**
+  * @brief  Checks whether the specified RCC interrupt has occurred or not.
+  * @param  RCC_IT: specifies the RCC interrupt source to check.
+  *          This parameter can be one of the following values:
+  *             @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *             @arg RCC_IT_LSERDY: LSE ready interrupt
+  *             @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *             @arg RCC_IT_HSERDY: HSE ready interrupt
+  *             @arg RCC_IT_PLLRDY: PLL ready interrupt
+  *             @arg RCC_IT_HSI14RDY: HSI14 ready interrupt
+  *             @arg RCC_IT_HSI48RDY: HSI48 ready interrupt, applicable only for STM32F072 devices    
+  *             @arg RCC_IT_CSS: Clock Security System interrupt
+  * @retval The new state of RCC_IT (SET or RESET).
+  */
+ITStatus RCC_GetITStatus(uint8_t RCC_IT)
+{
+  ITStatus bitstatus = RESET;
+  
+  /* Check the parameters */
+  assert_param(IS_RCC_GET_IT(RCC_IT));
+  
+  /* Check the status of the specified RCC interrupt */
+  if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the RCC_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the RCC's interrupt pending bits.
+  * @param  RCC_IT: specifies the interrupt pending bit to clear.
+  *          This parameter can be any combination of the following values:
+  *             @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *             @arg RCC_IT_LSERDY: LSE ready interrupt
+  *             @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *             @arg RCC_IT_HSERDY: HSE ready interrupt
+  *             @arg RCC_IT_PLLRDY: PLL ready interrupt
+  *             @arg RCC_IT_HSI48RDY: HSI48 ready interrupt, applicable only for STM32F072 devices 
+  *             @arg RCC_IT_HSI14RDY: HSI14 ready interrupt
+  *             @arg RCC_IT_CSS: Clock Security System interrupt
+  * @retval None
+  */
+void RCC_ClearITPendingBit(uint8_t RCC_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_CLEAR_IT(RCC_IT));
+  
+  /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
+     pending bits */
+  *(__IO uint8_t *) CIR_BYTE2_ADDRESS = RCC_IT;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_rtc.c b/system/src/stm32f0-stdperiph/stm32f0xx_rtc.c

new file mode 100644 (file)

index 0000000..1ca2c91
--- /dev/null
+++ b/system/src/stm32f0-stdperiph/stm32f0xx_rtc.c
@@ -0,0 +1,2518 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_rtc.c
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Real-Time Clock (RTC) peripheral:
+  *           + Initialization
+  *           + Calendar (Time and Date) configuration
+  *           + Alarms (Alarm A) configuration
+  *           + Daylight Saving configuration
+  *           + Output pin Configuration
+  *           + Digital Calibration configuration  
+  *           + TimeStamp configuration
+  *           + Tampers configuration
+  *           + Backup Data Registers configuration
+  *           + Output Type Config configuration
+  *           + Shift control synchronisation  
+  *           + Interrupts and flags management
+  *
+ @verbatim
+ ===============================================================================
+                    ##### Backup Domain Operating Condition #####
+ ===============================================================================
+    [..] The real-time clock (RTC) and the RTC backup registers can be powered
+         from the VBAT voltage when the main VDD supply is powered off.
+         To retain the content of the RTC backup registers and supply the RTC 
+         when VDD is turned off, VBAT pin can be connected to an optional
+         standby voltage supplied by a battery or by another source.
+  
+    [..] To allow the RTC to operate even when the main digital supply (VDD) 
+         is turned off, the VBAT pin powers the following blocks:
+           (#) The RTC
+           (#) The LSE oscillator
+           (#) PC13 to PC15 I/Os I/Os (when available)
+  
+    [..] When the backup domain is supplied by VDD (analog switch connected 
+         to VDD), the following functions are available:
+           (#) PC14 and PC15 can be used as either GPIO or LSE pins
+           (#) PC13 can be used as a GPIO or as the RTC_AF1 pin
+  
+    [..] When the backup domain is supplied by VBAT (analog switch connected 
+         to VBAT because VDD is not present), the following functions are available:
+           (#) PC14 and PC15 can be used as LSE pins only
+           (#) PC13 can be used as the RTC_AF1 pin 
+  
+                     ##### Backup Domain Reset #####
+ ===============================================================================
+    [..] The backup domain reset sets all RTC registers and the RCC_BDCR 
+         register to their reset values. 
+         A backup domain reset is generated when one of the following events
+         occurs:
+           (#) Software reset, triggered by setting the BDRST bit in the 
+               RCC Backup domain control register (RCC_BDCR). You can use the
+               RCC_BackupResetCmd().
+           (#) VDD or VBAT power on, if both supplies have previously been
+               powered off.
+  
+                     ##### Backup Domain Access #####
+ ===============================================================================
+    [..] After reset, the backup domain (RTC registers and RTC backup data 
+         registers) is protected against possible unwanted write accesses. 
+    [..] To enable access to the Backup Domain and RTC registers, proceed as follows:
+         (#) Enable the Power Controller (PWR) APB1 interface clock using the
+             RCC_APB1PeriphClockCmd() function.
+         (#) Enable access to Backup domain using the PWR_BackupAccessCmd() function.
+         (#) Select the RTC clock source using the RCC_RTCCLKConfig() function.
+         (#) Enable RTC Clock using the RCC_RTCCLKCmd() function.
+                                                                                           
+  
+                     ##### How to use this driver #####
+ ===============================================================================
+    [..]
+        (+) Enable the backup domain access (see description in the section above)
+        (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and
+            RTC hour format using the RTC_Init() function.
+  
+ ***Time and Date configuration ***
+ ==================================
+     [..]
+        (+) To configure the RTC Calendar (Time and Date) use the RTC_SetTime()
+            and RTC_SetDate() functions.
+        (+) To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate()
+            functions.
+        (+) To read the RTC subsecond, use the RTC_GetSubSecond() function.
+        (+) Use the RTC_DayLightSavingConfig() function to add or sub one
+            hour to the RTC Calendar.
+  
+ ***Alarm configuration ***
+ ========================== 
+     [..]  
+        (+) To configure the RTC Alarm use the RTC_SetAlarm() function.
+        (+) Enable the selected RTC Alarm using the RTC_AlarmCmd() function  
+        (+) To read the RTC Alarm, use the RTC_GetAlarm() function.
+        (+) To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function.
+
+ ***RTC Wakeup configuration***
+ ========================== 
+    [..]  
+        (+) Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig()
+            function.
+        (+) Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() 
+            function  
+        (+) Enable the RTC WakeUp using the RTC_WakeUpCmd() function  
+        (+) To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter() 
+            function.
+  
+ ***Outputs configuration ***
+ ============================
+    [..] The RTC has 2 different outputs:
+        (+) AFO_ALARM: this output is used to manage the RTC Alarm A.
+            To output the selected RTC signal on RTC_AF1 pin, use the 
+            RTC_OutputConfig() function.                
+        (+) AFO_CALIB: this output is 512Hz signal or 1Hz .
+            To output the RTC Clock on RTC_AF1 pin, use the RTC_CalibOutputCmd()
+            function.                
+  
+ ***Original Digital Calibration configuration ***
+ =================================    
+    [..] Configure the RTC Original Digital Calibration Value and the corresponding
+         calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig()
+         function.
+  
+ ***TimeStamp configuration ***
+ ==============================
+    [..]  
+        (+) Configure the RTC_AF1 trigger and enables the RTC TimeStamp 
+            using the RTC_TimeStampCmd() function.
+        (+) To read the RTC TimeStamp Time and Date register, use the 
+            RTC_GetTimeStamp() function.
+        (+) To read the RTC TimeStamp SubSecond register, use the 
+            RTC_GetTimeStampSubSecond() function.
+  
+ ***Tamper configuration ***
+ ===========================
+    [..]   
+        (+) Configure the Tamper filter count using RTC_TamperFilterConfig()
+            function. 
+        (+) Configure the RTC Tamper trigger Edge or Level according to the Tamper 
+            filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig() function
+        (+) Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig()
+            function.
+        (+) Configure the Tamper precharge or discharge duration using 
+            RTC_TamperPinsPrechargeDuration() function.
+        (+) Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function.
+        (+) Enable the RTC Tamper using the RTC_TamperCmd() function.
+        (+) Enable the Time stamp on Tamper detection event using  
+            RTC_TSOnTamperDetecCmd() function.     
+  
+ ***Backup Data Registers configuration ***
+ ==========================================
+    [..]  
+        (+) To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister()
+            function.  
+        (+) To read the RTC Backup Data registers, use the RTC_ReadBackupRegister()
+            function.  
+  
+                       ##### RTC and low power modes #####
+ ===============================================================================
+    [..] The MCU can be woken up from a low power mode by an RTC alternate 
+         function.
+    [..] The RTC alternate functions are the RTC alarm (Alarm A), RTC tamper 
+         event detection and RTC time stamp event detection.
+         These RTC alternate functions can wake up the system from the Stop 
+         and Standby lowpower modes.
+         The system can also wake up from low power modes without depending 
+         on an external interrupt (Auto-wakeup mode), by using the RTC alarm events.
+    [..] The RTC provides a programmable time base for waking up from the 
+         Stop or Standby mode at regular intervals.
+         Wakeup from STOP and Standby modes is possible only when the RTC 
+         clock source is LSE or LSI.
+  
+               ##### Selection of RTC_AF1 alternate functions #####
+ ===============================================================================
+    [..] The RTC_AF1 pin (PC13) can be used for the following purposes:
+         (+) AFO_ALARM output
+         (+) AFO_CALIB output
+         (+) AFI_TAMPER
+         (+) AFI_TIMESTAMP
+  
+   +------------------------------------------------------------------------------------------+
+   |     Pin         |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | WKUP2  |ALARMOUTTYPE  |
+   |  configuration  | ENABLED  | ENABLED  |  ENABLED  |   ENABLED    |ENABLED |  AFO_ALARM   |
+   |  and function   |          |          |           |              |        |Configuration |
+   |-----------------|----------|----------|-----------|--------------|--------|--------------|
+   |   Alarm out     |          |          |           |              | Don't  |              |
+   |   output OD     |     1    |    0     |Don't care | Don't care   | care   |      0       |
+   |-----------------|----------|----------|-----------|--------------|--------|--------------|
+   |   Alarm out     |          |          |           |              | Don't  |              |
+   |   output PP     |     1    |    0     |Don't care | Don't care   | care   |      1       |
+   |-----------------|----------|----------|-----------|--------------|--------|--------------|
+   | Calibration out |          |          |           |              | Don't  |              |
+   |   output PP     |     0    |    1     |Don't care | Don't care   | care   |  Don't care  |
+   |-----------------|----------|----------|-----------|--------------|--------|--------------|
+   |  TAMPER input   |          |          |           |              | Don't  |              |
+   |   floating      |     0    |    0     |     1     |      0       | care   |  Don't care  |
+   |-----------------|----------|----------|-----------|--------------|--------|--------------|
+   |  TIMESTAMP and  |          |          |           |              | Don't  |              |
+   |  TAMPER input   |     0    |    0     |     1     |      1       | care   |  Don't care  |
+   |   floating      |          |          |           |              |        |              |
+   |-----------------|----------|----------|-----------|--------------|--------|--------------|
+   | TIMESTAMP input |          |          |           |              | Don't  |              |
+   |    floating     |     0    |    0     |     0     |      1       | care   |  Don't care  |
+   |-----------------|----------|----------|-----------|--------------|--------|--------------|
+   |  Wakeup Pin 2   |     0    |    0     |     0     |      0       |   1    |  Don't care  |
+   |-----------------|----------|----------|-----------|--------------|--------|--------------|
+   |  Standard GPIO  |     0    |    0     |     0     |      0       |   0    |  Don't care  |
+   +------------------------------------------------------------------------------------------+
+  
+ @endverbatim
+ 
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_rtc.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup RTC 
+  * @brief RTC driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* Masks Definition */
+#define RTC_TR_RESERVED_MASK    ((uint32_t)0x007F7F7F)
+#define RTC_DR_RESERVED_MASK    ((uint32_t)0x00FFFF3F) 
+#define RTC_INIT_MASK           ((uint32_t)0xFFFFFFFF)  
+#define RTC_RSF_MASK            ((uint32_t)0xFFFFFF5F)
+#define RTC_FLAGS_MASK          ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_ALRAF | \
+                                            RTC_FLAG_RSF | RTC_FLAG_INITS |RTC_FLAG_INITF | \
+                                            RTC_FLAG_TAMP1F | RTC_FLAG_TAMP2F | RTC_FLAG_RECALPF | \
+                                            RTC_FLAG_SHPF))
+
+#define INITMODE_TIMEOUT         ((uint32_t) 0x00004000)
+#define SYNCHRO_TIMEOUT          ((uint32_t) 0x00008000)
+#define RECALPF_TIMEOUT          ((uint32_t) 0x00001000)
+#define SHPF_TIMEOUT             ((uint32_t) 0x00001000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static uint8_t RTC_ByteToBcd2(uint8_t Value);
+static uint8_t RTC_Bcd2ToByte(uint8_t Value);
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RTC_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup RTC_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================  
+
+    [..] This section provide functions allowing to initialize and configure the RTC
+         Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers
+         Write protection, enter and exit the RTC initialization mode, RTC registers
+         synchronization check and reference clock detection enable.
+  
+         (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
+             It is split into 2 programmable prescalers to minimize power consumption.
+             (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler.
+             (++) When both prescalers are used, it is recommended to configure the
+                  asynchronous prescaler to a high value to minimize consumption.
+         (#) All RTC registers are Write protected. Writing to the RTC registers
+             is enabled by writing a key into the Write Protection register, RTC_WPR.
+         (#) To Configure the RTC Calendar, user application should enter
+             initialization mode. In this mode, the calendar counter is stopped
+             and its value can be updated. When the initialization sequence is
+             complete, the calendar restarts counting after 4 RTCCLK cycles.
+         (#) To read the calendar through the shadow registers after Calendar
+             initialization, calendar update or after wakeup from low power modes
+             the software must first clear the RSF flag. The software must then
+             wait until it is set again before reading the calendar, which means
+             that the calendar registers have been correctly copied into the
+             RTC_TR and RTC_DR shadow registers.The RTC_WaitForSynchro() function
+             implements the above software sequence (RSF clear and RSF check).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the RTC registers to their default reset values.
+  * @note   This function doesn't reset the RTC Clock source and RTC Backup Data
+  *         registers.       
+  * @param  None
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC registers are deinitialized
+  *          - ERROR: RTC registers are not deinitialized
+  */
+ErrorStatus RTC_DeInit(void)
+{
+  ErrorStatus status = ERROR;
+  
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  }  
+  else
+  {
+    /* Reset TR, DR and CR registers */
+    RTC->TR        = (uint32_t)0x00000000;
+    RTC->WUTR      = (uint32_t)0x0000FFFF;
+    RTC->DR        = (uint32_t)0x00002101;
+    RTC->CR        &= (uint32_t)0x00000000;
+    RTC->PRER      = (uint32_t)0x007F00FF;
+    RTC->ALRMAR    = (uint32_t)0x00000000;
+    RTC->SHIFTR    = (uint32_t)0x00000000;
+    RTC->CALR       = (uint32_t)0x00000000;
+    RTC->ALRMASSR  = (uint32_t)0x00000000;
+
+    /* Reset ISR register and exit initialization mode */
+    RTC->ISR = (uint32_t)0x00000000;
+    
+    /* Reset Tamper and alternate functions configuration register */
+    RTC->TAFCR = 0x00000000;
+      
+    /* Wait till the RTC RSF flag is set */
+    if (RTC_WaitForSynchro() == ERROR)
+    {
+      status = ERROR;
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;  
+
+  return status;
+}
+
+/**
+  * @brief  Initializes the RTC registers according to the specified parameters 
+  *         in RTC_InitStruct.
+  * @param  RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains 
+  *         the configuration information for the RTC peripheral.
+  * @note   The RTC Prescaler register is write protected and can be written in 
+  *         initialization mode only.  
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC registers are initialized
+  *          - ERROR: RTC registers are not initialized  
+  */
+ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat));
+  assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv));
+  assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  }
+  else
+  {
+    /* Clear RTC CR FMT Bit */
+    RTC->CR &= ((uint32_t)~(RTC_CR_FMT));
+    /* Set RTC_CR register */
+    RTC->CR |=  ((uint32_t)(RTC_InitStruct->RTC_HourFormat));
+  
+    /* Configure the RTC PRER */
+    RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv);
+    RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16);
+
+    /* Exit Initialization mode */
+    RTC_ExitInitMode();
+
+    status = SUCCESS;
+  }
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+
+  return status;
+}
+
+/**
+  * @brief  Fills each RTC_InitStruct member with its default value.
+  * @param  RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be 
+  *         initialized.
+  * @retval None
+  */
+void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct)
+{
+  /* Initialize the RTC_HourFormat member */
+  RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24;
+
+  /* Initialize the RTC_AsynchPrediv member */
+  RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F;
+
+  /* Initialize the RTC_SynchPrediv member */
+  RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; 
+}
+
+/**
+  * @brief  Enables or disables the RTC registers write protection.
+  * @note   All the RTC registers are write protected except for RTC_ISR[13:8], 
+  *         RTC_TAFCR and RTC_BKPxR.
+  * @note   Writing a wrong key reactivates the write protection.
+  * @note   The protection mechanism is not affected by system reset.
+  * @param  NewState: new state of the write protection.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_WriteProtectionCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the write protection for RTC registers */
+    RTC->WPR = 0xFF;
+  }
+  else
+  {
+    /* Disable the write protection for RTC registers */
+    RTC->WPR = 0xCA;
+    RTC->WPR = 0x53;
+  }
+}
+
+/**
+  * @brief  Enters the RTC Initialization mode.
+  * @note   The RTC Initialization mode is write protected, use the 
+  *         RTC_WriteProtectionCmd(DISABLE) before calling this function.
+  * @param  None
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC is in Init mode
+  *          - ERROR: RTC is not in Init mode
+  */
+ErrorStatus RTC_EnterInitMode(void)
+{
+  __IO uint32_t initcounter = 0x00;
+  ErrorStatus status = ERROR;
+  uint32_t initstatus = 0x00;
+
+  /* Check if the Initialization mode is set */
+  if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+  {
+    /* Set the Initialization mode */
+    RTC->ISR = (uint32_t)RTC_INIT_MASK;
+    
+    /* Wait till RTC is in INIT state and if Time out is reached exit */
+    do
+    {
+      initstatus = RTC->ISR & RTC_ISR_INITF;
+      initcounter++;  
+    } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));
+    
+    if ((RTC->ISR & RTC_ISR_INITF) != RESET)
+    {
+      status = SUCCESS;
+    }
+    else
+    {
+      status = ERROR;
+    }
+  }
+  else
+  {
+    status = SUCCESS;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief  Exits the RTC Initialization mode.
+  * @note   When the initialization sequence is complete, the calendar restarts 
+  *         counting after 4 RTCCLK cycles.  
+  * @note   The RTC Initialization mode is write protected, use the 
+  *         RTC_WriteProtectionCmd(DISABLE) before calling this function.      
+  * @param  None
+  * @retval None
+  */
+void RTC_ExitInitMode(void)
+{
+  /* Exit Initialization mode */
+  RTC->ISR &= (uint32_t)~RTC_ISR_INIT;
+}
+
+/**
+  * @brief  Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are 
+  *         synchronized with RTC APB clock.
+  * @note   The RTC Resynchronization mode is write protected, use the 
+  *         RTC_WriteProtectionCmd(DISABLE) before calling this function. 
+  * @note   To read the calendar through the shadow registers after Calendar 
+  *         initialization, calendar update or after wakeup from low power modes 
+  *         the software must first clear the RSF flag. 
+  *         The software must then wait until it is set again before reading 
+  *         the calendar, which means that the calendar registers have been 
+  *         correctly copied into the RTC_TR and RTC_DR shadow registers.   
+  * @param  None
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC registers are synchronised
+  *          - ERROR: RTC registers are not synchronised
+  */
+ErrorStatus RTC_WaitForSynchro(void)
+{
+  __IO uint32_t synchrocounter = 0;
+  ErrorStatus status = ERROR;
+  uint32_t synchrostatus = 0x00;
+
+  if ((RTC->CR & RTC_CR_BYPSHAD) != RESET)
+  {
+    /* Bypass shadow mode */
+    status = SUCCESS;
+  }
+  else
+  {
+    /* Disable the write protection for RTC registers */
+    RTC->WPR = 0xCA;
+    RTC->WPR = 0x53;
+
+    /* Clear RSF flag */
+    RTC->ISR &= (uint32_t)RTC_RSF_MASK;
+
+    /* Wait the registers to be synchronised */
+    do
+    {
+      synchrostatus = RTC->ISR & RTC_ISR_RSF;
+      synchrocounter++;  
+    } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));
+
+    if ((RTC->ISR & RTC_ISR_RSF) != RESET)
+    {
+      status = SUCCESS;
+    }
+    else
+    {
+      status = ERROR;
+    }
+
+    /* Enable the write protection for RTC registers */
+    RTC->WPR = 0xFF;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief  Enables or disables the RTC reference clock detection.
+  * @param  NewState: new state of the RTC reference clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC reference clock detection is enabled
+  *          - ERROR: RTC reference clock detection is disabled  
+  */
+ErrorStatus RTC_RefClockCmd(FunctionalState NewState)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  }
+  else
+  {
+    if (NewState != DISABLE)
+    {
+      /* Enable the RTC reference clock detection */
+      RTC->CR |= RTC_CR_REFCKON;
+    }
+    else
+    {
+      /* Disable the RTC reference clock detection */
+      RTC->CR &= ~RTC_CR_REFCKON;
+    }
+    /* Exit Initialization mode */
+    RTC_ExitInitMode();
+
+    status = SUCCESS;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+
+  return status;
+}
+
+/**
+  * @brief  Enables or Disables the Bypass Shadow feature.
+  * @note   When the Bypass Shadow is enabled the calendar value are taken 
+  *         directly from the Calendar counter.
+  * @param  NewState: new state of the Bypass Shadow feature.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+*/
+void RTC_BypassShadowCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  if (NewState != DISABLE)
+  {
+    /* Set the BYPSHAD bit */
+    RTC->CR |= (uint8_t)RTC_CR_BYPSHAD;
+  }
+  else
+  {
+    /* Reset the BYPSHAD bit */
+    RTC->CR &= (uint8_t)~RTC_CR_BYPSHAD;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group2 Time and Date configuration functions
+ *  @brief   Time and Date configuration functions
+ *
+@verbatim
+ ===============================================================================
+               ##### Time and Date configuration functions #####
+ ===============================================================================
+    [..]  This section provide functions allowing to program and read the RTC
+          Calendar (Time and Date).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set the RTC current time.
+  * @param  RTC_Format: specifies the format of the entered parameters.
+  *          This parameter can be  one of the following values:
+  *            @arg RTC_Format_BIN:  Binary data format 
+  *            @arg RTC_Format_BCD:  BCD data format
+  * @param  RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains 
+  *                        the time configuration information for the RTC.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Time register is configured
+  *          - ERROR: RTC Time register is not configured
+  */
+ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
+{
+  uint32_t tmpreg = 0;
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+  
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours));
+      assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12));
+    }
+    else
+    {
+      RTC_TimeStruct->RTC_H12 = 0x00;
+      assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours));
+    }
+    assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes));
+    assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds));
+  }
+  else
+  {
+    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
+      assert_param(IS_RTC_HOUR12(tmpreg));
+      assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); 
+    } 
+    else
+    {
+      RTC_TimeStruct->RTC_H12 = 0x00;
+      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours)));
+    }
+    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes)));
+    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds)));
+  }
+  
+  /* Check the input parameters format */
+  if (RTC_Format != RTC_Format_BIN)
+  {
+    tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \
+             ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \
+             ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \
+             ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16)); 
+  }
+  else
+  {
+    tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \
+                   ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \
+                   ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \
+                   (((uint32_t)RTC_TimeStruct->RTC_H12) << 16));
+  } 
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  } 
+  else
+  {
+    /* Set the RTC_TR register */
+    RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
+
+    /* Exit Initialization mode */
+    RTC_ExitInitMode(); 
+
+    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+    if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)
+    {
+      if (RTC_WaitForSynchro() == ERROR)
+      {
+        status = ERROR;
+      }
+      else
+      {
+        status = SUCCESS;
+      }
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+  
+  }
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+    
+  return status;
+}
+
+/**
+  * @brief  Fills each RTC_TimeStruct member with its default value
+  *         (Time = 00h:00min:00sec).
+  * @param  RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be 
+  *         initialized.
+  * @retval None
+  */
+void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct)
+{
+  /* Time = 00h:00min:00sec */
+  RTC_TimeStruct->RTC_H12 = RTC_H12_AM;
+  RTC_TimeStruct->RTC_Hours = 0;
+  RTC_TimeStruct->RTC_Minutes = 0;
+  RTC_TimeStruct->RTC_Seconds = 0; 
+}
+
+/**
+  * @brief  Get the RTC current Time.
+  * @param  RTC_Format: specifies the format of the returned parameters.
+  *          This parameter can be  one of the following values:
+  *            @arg RTC_Format_BIN:  Binary data format 
+  *            @arg RTC_Format_BCD:  BCD data format
+  * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will 
+  *                        contain the returned current time configuration.
+  * @retval None
+  */
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+
+  /* Get the RTC_TR register */
+  tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); 
+  
+  /* Fill the structure fields with the read parameters */
+  RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
+  RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
+  RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
+  RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);  
+
+  /* Check the input parameters format */
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    /* Convert the structure parameters to Binary format */
+    RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
+    RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes);
+    RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds);
+  }
+}
+
+/**
+  * @brief  Gets the RTC current Calendar Subseconds value.
+  * @note   This function freeze the Time and Date registers after reading the 
+  *         SSR register.
+  * @param  None
+  * @retval RTC current Calendar Subseconds value.
+  */
+uint32_t RTC_GetSubSecond(void)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Get subseconds values from the correspondent registers*/
+  tmpreg = (uint32_t)(RTC->SSR);
+  
+  /* Read DR register to unfroze calendar registers */
+  (void) (RTC->DR);
+  
+  return (tmpreg);
+}
+
+/**
+  * @brief  Set the RTC current date.
+  * @param  RTC_Format: specifies the format of the entered parameters.
+  *          This parameter can be  one of the following values:
+  *            @arg RTC_Format_BIN:  Binary data format 
+  *            @arg RTC_Format_BCD:  BCD data format
+  * @param  RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains 
+  *                         the date configuration information for the RTC.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Date register is configured
+  *          - ERROR: RTC Date register is not configured
+  */
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
+{
+  uint32_t tmpreg = 0;
+  ErrorStatus status = ERROR;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+
+  if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10))
+  {
+    RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A;
+  }  
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year));
+    assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month));
+    assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date));
+  }
+  else
+  {
+    assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year)));
+    tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
+    assert_param(IS_RTC_MONTH(tmpreg));
+    tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
+    assert_param(IS_RTC_DATE(tmpreg));
+  }
+  assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay));
+
+  /* Check the input parameters format */
+  if (RTC_Format != RTC_Format_BIN)
+  {
+    tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \
+              (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \
+              ((uint32_t)RTC_DateStruct->RTC_Date) | \
+              (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); 
+  }  
+  else
+  {
+    tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \
+              ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \
+              ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \
+              ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13));
+  }
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  } 
+  else
+  {
+    /* Set the RTC_DR register */
+    RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK);
+
+    /* Exit Initialization mode */
+    RTC_ExitInitMode(); 
+
+    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+    if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)
+    {
+      if (RTC_WaitForSynchro() == ERROR)
+      {
+        status = ERROR;
+      }
+      else
+      {
+        status = SUCCESS;
+      }
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+  }
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+  
+  return status;
+}
+
+/**
+  * @brief  Fills each RTC_DateStruct member with its default value
+  *         (Monday, January 01 xx00).
+  * @param  RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be 
+  *         initialized.
+  * @retval None
+  */
+void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct)
+{
+  /* Monday, January 01 xx00 */
+  RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday;
+  RTC_DateStruct->RTC_Date = 1;
+  RTC_DateStruct->RTC_Month = RTC_Month_January;
+  RTC_DateStruct->RTC_Year = 0;
+}
+
+/**
+  * @brief  Get the RTC current date.
+  * @param  RTC_Format: specifies the format of the returned parameters.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Format_BIN: Binary data format 
+  *            @arg RTC_Format_BCD: BCD data format
+  * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will 
+  *                        contain the returned current date configuration.
+  * @retval None
+  */
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+  
+  /* Get the RTC_TR register */
+  tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); 
+
+  /* Fill the structure fields with the read parameters */
+  RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
+  RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
+  RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU));
+  RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13);  
+
+  /* Check the input parameters format */
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    /* Convert the structure parameters to Binary format */
+    RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year);
+    RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
+    RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
+    RTC_DateStruct->RTC_WeekDay = (uint8_t)(RTC_DateStruct->RTC_WeekDay);   
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group3 Alarms configuration functions
+ *  @brief   Alarms (Alarm A) configuration functions 
+ *
+@verbatim
+ ===============================================================================
+         ##### Alarms (Alarm A and Alarm B) configuration functions #####
+ ===============================================================================
+    [..] This section provide functions allowing to program and read the RTC 
+         Alarms.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set the specified RTC Alarm.
+  * @note   The Alarm register can only be written when the corresponding Alarm
+  *         is disabled (Use the RTC_AlarmCmd(DISABLE)).    
+  * @param  RTC_Format: specifies the format of the returned parameters.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Format_BIN: Binary data format 
+  *            @arg RTC_Format_BCD: BCD data format
+  * @param  RTC_Alarm: specifies the alarm to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Alarm_A: to select Alarm A
+  * @param  RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that 
+  *                          contains the alarm configuration parameters.
+  * @retval None
+  */
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+  assert_param(IS_RTC_ALARM(RTC_Alarm));
+  assert_param(IS_RTC_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask));
+  assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel));
+
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
+      assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
+    } 
+    else
+    {
+      RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;
+      assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
+    }
+    assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes));
+    assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds));
+    
+    if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)
+    {
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
+    }
+    else
+    {
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
+    }
+  }
+  else
+  {
+    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours);
+      assert_param(IS_RTC_HOUR12(tmpreg));
+      assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
+    } 
+    else
+    {
+      RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;
+      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)));
+    }
+    
+    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)));
+    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)));
+    
+    if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)
+    {
+      tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));    
+    }
+    else
+    {
+      tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));      
+    }    
+  }
+
+  /* Check the input parameters format */
+  if (RTC_Format != RTC_Format_BIN)
+  {
+    tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
+              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \
+              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \
+              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); 
+  }  
+  else
+  {
+    tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
+              ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
+              ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \
+              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \
+              ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); 
+  }
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Configure the Alarm register */
+  RTC->ALRMAR = (uint32_t)tmpreg;
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @brief  Fills each RTC_AlarmStruct member with its default value
+  *         (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask =
+  *         all fields are masked).
+  * @param  RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which
+  *         will be initialized.
+  * @retval None
+  */
+void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct)
+{
+  /* Alarm Time Settings : Time = 00h:00mn:00sec */
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM;
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0;
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0;
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0;
+
+  /* Alarm Date Settings : Date = 1st day of the month */
+  RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date;
+  RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1;
+
+  /* Alarm Masks Settings : Mask =  all fields are not masked */
+  RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None;
+}
+
+/**
+  * @brief  Get the RTC Alarm value and masks.
+  * @param  RTC_Format: specifies the format of the output parameters.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Format_BIN: Binary data format 
+  *            @arg RTC_Format_BCD: BCD data format
+  * @param  RTC_Alarm: specifies the alarm to be read.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Alarm_A: to select Alarm A
+  * @param  RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will 
+  *                          contains the output alarm configuration values.
+  * @retval None
+  */
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+  assert_param(IS_RTC_ALARM(RTC_Alarm)); 
+
+  /* Get the RTC_ALRMAR register */
+  tmpreg = (uint32_t)(RTC->ALRMAR);
+
+  /* Fill the structure with the read parameters */
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \
+                                                     RTC_ALRMAR_HU)) >> 16);
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \
+                                                     RTC_ALRMAR_MNU)) >> 8);
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \
+                                                     RTC_ALRMAR_SU));
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);
+  RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
+  RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
+  RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All);
+
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
+                                                        RTC_AlarmTime.RTC_Hours);
+    RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
+                                                        RTC_AlarmTime.RTC_Minutes);
+    RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
+                                                        RTC_AlarmTime.RTC_Seconds);
+    RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
+  }  
+}
+
+/**
+  * @brief  Enables or disables the specified RTC Alarm.
+  * @param  RTC_Alarm: specifies the alarm to be configured.
+  *          This parameter can be any combination of the following values:
+  *            @arg RTC_Alarm_A: to select Alarm A
+  * @param  NewState: new state of the specified alarm.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Alarm is enabled/disabled
+  *          - ERROR: RTC Alarm is not enabled/disabled  
+  */
+ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState)
+{
+  __IO uint32_t alarmcounter = 0x00;
+  uint32_t alarmstatus = 0x00;
+  ErrorStatus status = ERROR;
+    
+  /* Check the parameters */
+  assert_param(IS_RTC_CMD_ALARM(RTC_Alarm));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Configure the Alarm state */
+  if (NewState != DISABLE)
+  {
+    RTC->CR |= (uint32_t)RTC_Alarm;
+
+    status = SUCCESS;    
+  }
+  else
+  { 
+    /* Disable the Alarm in RTC_CR register */
+    RTC->CR &= (uint32_t)~RTC_Alarm;
+   
+    /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
+    do
+    {
+      alarmstatus = RTC->ISR & (RTC_Alarm >> 8);
+      alarmcounter++;  
+    } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00));
+    
+    if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET)
+    {
+      status = ERROR;
+    } 
+    else
+    {
+      status = SUCCESS;
+    }        
+  } 
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+  
+  return status;
+}
+
+/**
+  * @brief  Configure the RTC AlarmA/B Subseconds value and mask.
+  * @note   This function is performed only when the Alarm is disabled. 
+  * @param  RTC_Alarm: specifies the alarm to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Alarm_A: to select Alarm A
+  * @param  RTC_AlarmSubSecondValue: specifies the Subseconds value.
+  *          This parameter can be a value from 0 to 0x00007FFF.
+  * @param  RTC_AlarmSubSecondMask:  specifies the Subseconds Mask.
+  *          This parameter can be any combination of the following values:
+  *            @arg RTC_AlarmSubSecondMask_All: All Alarm SS fields are masked.
+  *                                             There is no comparison on sub seconds for Alarm.
+  *            @arg RTC_AlarmSubSecondMask_SS14_1: SS[14:1] are don't care in Alarm comparison.
+  *                                                Only SS[0] is compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_2: SS[14:2] are don't care in Alarm comparison.
+  *                                                Only SS[1:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_3: SS[14:3] are don't care in Alarm comparison.
+  *                                                Only SS[2:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_4: SS[14:4] are don't care in Alarm comparison.
+  *                                                Only SS[3:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_5: SS[14:5] are don't care in Alarm comparison.
+  *                                                Only SS[4:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_6: SS[14:6] are don't care in Alarm comparison.
+  *                                                Only SS[5:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_7: SS[14:7] are don't care in Alarm comparison.
+  *                                                Only SS[6:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_8: SS[14:8] are don't care in Alarm comparison.
+  *                                                Only SS[7:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_9: SS[14:9] are don't care in Alarm comparison.
+  *                                                Only SS[8:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison.
+  *                                                 Only SS[9:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison.
+  *                                                 Only SS[10:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison.
+  *                                                 Only SS[11:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison.
+  *                                                 Only SS[12:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14: SS[14] is don't care in Alarm comparison.
+  *                                              Only SS[13:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_None: SS[14:0] are compared and must match to activate alarm
+  * @retval None
+  */
+void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint8_t RTC_AlarmSubSecondMask)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_ALARM(RTC_Alarm));
+  assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue));
+  assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask));
+  
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  /* Configure the Alarm A or Alarm B SubSecond registers */
+  tmpreg = (uint32_t) (((uint32_t)(RTC_AlarmSubSecondValue)) | ((uint32_t)(RTC_AlarmSubSecondMask) << 24));
+  
+  /* Configure the AlarmA SubSecond register */
+  RTC->ALRMASSR = tmpreg;
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+
+}
+
+/**
+  * @brief  Gets the RTC Alarm Subseconds value.
+  * @param  RTC_Alarm: specifies the alarm to be read.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Alarm_A: to select Alarm A
+  * @param  None
+  * @retval RTC Alarm Subseconds value.
+  */
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Get the RTC_ALRMAR register */
+  tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS);
+
+  return (tmpreg);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group4 WakeUp Timer configuration functions
+ *  @brief   WakeUp Timer configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+            ##### WakeUp Timer configuration functions #####
+ ===============================================================================  
+
+    [..] This section provide functions allowing to program and read the RTC WakeUp.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the RTC Wakeup clock source.
+  *         This function is available for STM32F072 devices.  
+  * @note   The WakeUp Clock source can only be changed when the RTC WakeUp
+  *         is disabled (Use the RTC_WakeUpCmd(DISABLE)).
+  * @param  RTC_WakeUpClock: Wakeup Clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_WakeUpClock_RTCCLK_Div16
+  *            @arg RTC_WakeUpClock_RTCCLK_Div8
+  *            @arg RTC_WakeUpClock_RTCCLK_Div4
+  *            @arg RTC_WakeUpClock_RTCCLK_Div2
+  *            @arg RTC_WakeUpClock_CK_SPRE_16bits
+  *            @arg RTC_WakeUpClock_CK_SPRE_17bits
+  * @retval None
+  */
+void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Clear the Wakeup Timer clock source bits in CR register */
+  RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL;
+
+  /* Configure the clock source */
+  RTC->CR |= (uint32_t)RTC_WakeUpClock;
+  
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @brief  Configures the RTC Wakeup counter.
+  *         This function is available for STM32F072 devices.  
+  * @note   The RTC WakeUp counter can only be written when the RTC WakeUp
+  *         is disabled (Use the RTC_WakeUpCmd(DISABLE)).
+  * @param  RTC_WakeUpCounter: specifies the WakeUp counter.
+  *          This parameter can be a value from 0x0000 to 0xFFFF. 
+  * @retval None
+  */
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter));
+  
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  /* Configure the Wakeup Timer counter */
+  RTC->WUTR = (uint32_t)RTC_WakeUpCounter;
+  
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @brief  Returns the RTC WakeUp timer counter value.
+  *         This function is available for STM32F072 devices.  
+  * @param  None
+  * @retval The RTC WakeUp Counter value.
+  */
+uint32_t RTC_GetWakeUpCounter(void)
+{
+  /* Get the counter value */
+  return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT));
+}
+
+/**
+  * @brief  Enables or Disables the RTC WakeUp timer.
+  *         This function is available for STM32F072 devices.  
+  * @param  NewState: new state of the WakeUp timer.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+ErrorStatus RTC_WakeUpCmd(FunctionalState NewState)
+{
+  __IO uint32_t wutcounter = 0x00;
+  uint32_t wutwfstatus = 0x00;
+  ErrorStatus status = ERROR;
+  
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Wakeup Timer */
+    RTC->CR |= (uint32_t)RTC_CR_WUTE;
+    status = SUCCESS;    
+  }
+  else
+  {
+    /* Disable the Wakeup Timer */
+    RTC->CR &= (uint32_t)~RTC_CR_WUTE;
+    /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+    do
+    {
+      wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;
+      wutcounter++;  
+    } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
+    
+    if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)
+    {
+      status = ERROR;
+    }
+    else
+    {
+      status = SUCCESS;
+    }    
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+  
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group5 Daylight Saving configuration functions
+ *  @brief   Daylight Saving configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+               ##### WakeUp Timer configuration functions #####
+ ===============================================================================
+    [..] This section provide functions allowing to program and read the RTC WakeUp. 
+
+  This section provide functions allowing to configure the RTC DayLight Saving.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Adds or substract one hour from the current time.
+  * @param  RTC_DayLightSaveOperation: the value of hour adjustment. 
+  *          This parameter can be one of the following values:
+  *            @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time)
+  *            @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time)
+  * @param  RTC_StoreOperation: Specifies the value to be written in the BCK bit 
+  *                             in CR register to store the operation.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_StoreOperation_Reset: BCK Bit Reset
+  *            @arg RTC_StoreOperation_Set: BCK Bit Set
+  * @retval None
+  */
+void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving));
+  assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Clear the bits to be configured */
+  RTC->CR &= (uint32_t)~(RTC_CR_BCK);
+
+  /* Configure the RTC_CR register */
+  RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation);
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @brief  Returns the RTC Day Light Saving stored operation.
+  * @param  None
+  * @retval RTC Day Light Saving stored operation.
+  *          - RTC_StoreOperation_Reset
+  *          - RTC_StoreOperation_Set
+  */
+uint32_t RTC_GetStoreOperation(void)
+{
+  return (RTC->CR & RTC_CR_BCK);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group6 Output pin Configuration function
+ *  @brief   Output pin Configuration function 
+ *
+@verbatim   
+ ===============================================================================
+                  ##### Output pin Configuration function #####
+ ===============================================================================
+    [..] This section provide functions allowing to configure the RTC Output source.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the RTC output source (AFO_ALARM).
+  * @param  RTC_Output: Specifies which signal will be routed to the RTC output. 
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Output_Disable: No output selected
+  *            @arg RTC_Output_AlarmA: signal of AlarmA mapped to output
+  *            @arg RTC_Output_WakeUp: signal of WakeUp mapped to output, available only for STM32F072 devices  
+  * @param  RTC_OutputPolarity: Specifies the polarity of the output signal. 
+  *          This parameter can be one of the following:
+  *            @arg RTC_OutputPolarity_High: The output pin is high when the 
+  *                                          ALRAF is high (depending on OSEL)
+  *            @arg RTC_OutputPolarity_Low: The output pin is low when the 
+  *                                         ALRAF is high (depending on OSEL)
+  * @retval None
+  */
+void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_OUTPUT(RTC_Output));
+  assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Clear the bits to be configured */
+  RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL);
+
+  /* Configure the output selection and polarity */
+  RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity);
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group7 Digital Calibration configuration functions
+ *  @brief   Digital Calibration configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+          ##### Digital Calibration configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the RTC clock to be output through the relative pin.
+  * @param  NewState: new state of the digital calibration Output.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_CalibOutputCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the RTC clock output */
+    RTC->CR |= (uint32_t)RTC_CR_COE;
+  }
+  else
+  { 
+    /* Disable the RTC clock output */
+    RTC->CR &= (uint32_t)~RTC_CR_COE;
+  }
+  
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+}
+
+/**
+  * @brief  Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+  * @param  RTC_CalibOutput: Select the Calibration output Selection .
+  *          This parameter can be one of the following values:
+  *            @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz. 
+  *            @arg RTC_CalibOutput_1Hz: A signal has a regular waveform at 1Hz.
+  * @retval None
+*/
+void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  /*clear flags before config*/
+  RTC->CR &= (uint32_t)~(RTC_CR_CALSEL);
+
+  /* Configure the RTC_CR register */
+  RTC->CR |= (uint32_t)RTC_CalibOutput;
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @brief  Configures the Smooth Calibration Settings.
+  * @param  RTC_SmoothCalibPeriod: Select the Smooth Calibration Period.
+  *          This parameter can be can be one of the following values:
+  *            @arg RTC_SmoothCalibPeriod_32sec: The smooth calibration periode is 32s.
+  *            @arg RTC_SmoothCalibPeriod_16sec: The smooth calibration periode is 16s.
+  *            @arg RTC_SmoothCalibPeriod_8sec: The smooth calibartion periode is 8s.
+  * @param  RTC_SmoothCalibPlusPulses: Select to Set or reset the CALP bit.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_SmoothCalibPlusPulses_Set: Add one RTCCLK puls every 2**11 pulses.
+  *            @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added.
+  * @param  RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
+  *          This parameter can be one any value from 0 to 0x000001FF.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Calib registers are configured
+  *          - ERROR: RTC Calib registers are not configured
+*/
+ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
+                                  uint32_t RTC_SmoothCalibPlusPulses,
+                                  uint32_t RTC_SmouthCalibMinusPulsesValue)
+{
+  ErrorStatus status = ERROR;
+  uint32_t recalpfcount = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod));
+  assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses));
+  assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  /* check if a calibration is pending*/
+  if ((RTC->ISR & RTC_ISR_RECALPF) != RESET)
+  {
+    /* wait until the Calibration is completed*/
+    while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT))
+    {
+      recalpfcount++;
+    }
+  }
+
+  /* check if the calibration pending is completed or if there is no calibration operation at all*/
+  if ((RTC->ISR & RTC_ISR_RECALPF) == RESET)
+  {
+    /* Configure the Smooth calibration settings */
+    RTC->CALR = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses | (uint32_t)RTC_SmouthCalibMinusPulsesValue);
+
+    status = SUCCESS;
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+  
+  return (ErrorStatus)(status);
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RTC_Group8 TimeStamp configuration functions
+ *  @brief   TimeStamp configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+          ##### TimeStamp configuration functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or Disables the RTC TimeStamp functionality with the 
+  *         specified time stamp pin stimulating edge.
+  * @param  RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is 
+  *         activated.
+  *          This parameter can be one of the following:
+  *            @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising 
+  *                                           edge of the related pin.
+  *            @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the 
+  *                                            falling edge of the related pin.
+  * @param  NewState: new state of the TimeStamp.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Get the RTC_CR register and clear the bits to be configured */
+  tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
+
+  /* Get the new configuration */
+  if (NewState != DISABLE)
+  {
+    tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE);
+  }
+  else
+  {
+    tmpreg |= (uint32_t)(RTC_TimeStampEdge);
+  }
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Configure the Time Stamp TSEDGE and Enable bits */
+  RTC->CR = (uint32_t)tmpreg;
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @brief  Get the RTC TimeStamp value and masks.
+  * @param  RTC_Format: specifies the format of the output parameters.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Format_BIN: Binary data format 
+  *            @arg RTC_Format_BCD: BCD data format
+  * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will 
+  *                             contains the TimeStamp time values. 
+  * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will 
+  *                             contains the TimeStamp date values.     
+  * @retval None
+  */
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, 
+                                      RTC_DateTypeDef* RTC_StampDateStruct)
+{
+  uint32_t tmptime = 0, tmpdate = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+
+  /* Get the TimeStamp time and date registers values */
+  tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK);
+  tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK);
+
+  /* Fill the Time structure fields with the read parameters */
+  RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
+  RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
+  RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
+  RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);  
+
+  /* Fill the Date structure fields with the read parameters */
+  RTC_StampDateStruct->RTC_Year = 0;
+  RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
+  RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
+  RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
+
+  /* Check the input parameters format */
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    /* Convert the Time structure parameters to Binary format */
+    RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours);
+    RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes);
+    RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds);
+
+    /* Convert the Date structure parameters to Binary format */
+    RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month);
+    RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date);
+    RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay);
+  }
+}
+
+/**
+  * @brief  Get the RTC timestamp Subseconds value.
+  * @param  None
+  * @retval RTC current timestamp Subseconds value.
+  */
+uint32_t RTC_GetTimeStampSubSecond(void)
+{
+  /* Get timestamp subseconds values from the correspondent registers */
+  return (uint32_t)(RTC->TSSSR);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group9 Tampers configuration functions
+ *  @brief   Tampers configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+          ##### Tampers configuration functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the select Tamper pin edge.
+  * @param  RTC_Tamper: Selected tamper pin.
+  *          This parameter can be any combination of the following values:
+  *            @arg RTC_Tamper_1: Select Tamper 1.
+  *            @arg RTC_Tamper_2: Select Tamper 2.
+  * @param  RTC_TamperTrigger: Specifies the trigger on the tamper pin that 
+  *                            stimulates tamper event. 
+  *          This parameter can be one of the following values:
+  *            @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event.
+  *            @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event.
+  *            @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event.
+  *            @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event.
+  * @retval None
+  */
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER(RTC_Tamper)); 
+  assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger));
+ 
+  if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge)
+  {  
+    /* Configure the RTC_TAFCR register */
+    RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1));    
+  }
+  else
+  { 
+    /* Configure the RTC_TAFCR register */
+    RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1);  
+  }  
+}
+
+/**
+  * @brief  Enables or Disables the Tamper detection.
+  * @param  RTC_Tamper: Selected tamper pin.
+  *          This parameter can be any combination of the following values:
+  *            @arg RTC_Tamper_1: Select Tamper 1.
+  *            @arg RTC_Tamper_2: Select Tamper 2.
+  * @param  NewState: new state of the tamper pin.
+  *         This parameter can be: ENABLE or DISABLE.                   
+  * @retval None
+  */
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER(RTC_Tamper));  
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected Tamper pin */
+    RTC->TAFCR |= (uint32_t)RTC_Tamper;
+  }
+  else
+  {
+    /* Disable the selected Tamper pin */
+    RTC->TAFCR &= (uint32_t)~RTC_Tamper;    
+  }  
+}
+
+/**
+  * @brief  Configures the Tampers Filter.
+  * @param  RTC_TamperFilter: Specifies the tampers filter.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_TamperFilter_Disable: Tamper filter is disabled.
+  *            @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive 
+  *                                           samples at the active level 
+  *            @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive 
+  *                                           samples at the active level
+  *            @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive 
+  *                                           samples at the active level 
+  * @retval None
+  */
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter));
+   
+  /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT);
+
+  /* Configure the RTC_TAFCR register */
+  RTC->TAFCR |= (uint32_t)RTC_TamperFilter;
+}
+
+/**
+  * @brief  Configures the Tampers Sampling Frequency.
+  * @param  RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled
+  *                                                         with a frequency =  RTCCLK / 32768
+  *            @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled
+  *                                                         with a frequency =  RTCCLK / 16384
+  *            @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled
+  *                                                        with a frequency =  RTCCLK / 8192
+  *            @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled
+  *                                                        with a frequency =  RTCCLK / 4096
+  *            @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled
+  *                                                        with a frequency =  RTCCLK / 2048
+  *            @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled
+  *                                                        with a frequency =  RTCCLK / 1024
+  *            @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled
+  *                                                       with a frequency =  RTCCLK / 512  
+  *            @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled
+  *                                                       with a frequency =  RTCCLK / 256  
+  * @retval None
+  */
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq));
+ 
+  /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ);
+
+  /* Configure the RTC_TAFCR register */
+  RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq;
+}
+
+/**
+  * @brief  Configures the Tampers Pins input Precharge Duration.
+  * @param  RTC_TamperPrechargeDuration: Specifies the Tampers Pins input
+  *         Precharge Duration.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle
+  *            @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle
+  *            @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle    
+  *            @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle
+  * @retval None
+  */
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration));
+   
+  /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH);
+
+  /* Configure the RTC_TAFCR register */
+  RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration;
+}
+
+/**
+  * @brief  Enables or Disables the TimeStamp on Tamper Detection Event.
+  * @note   The timestamp is valid even the TSE bit in tamper control register 
+  *         is reset.   
+  * @param  NewState: new state of the timestamp on tamper event.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+   
+  if (NewState != DISABLE)
+  {
+    /* Save timestamp on tamper detection event */
+    RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS;
+  }
+  else
+  {
+    /* Tamper detection does not cause a timestamp to be saved */
+    RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS;    
+  }
+}
+
+/**
+  * @brief  Enables or Disables the Precharge of Tamper pin.
+  * @param  NewState: new state of tamper pull up.
+  *          This parameter can be: ENABLE or DISABLE.                   
+  * @retval None
+  */
+void RTC_TamperPullUpCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+ if (NewState != DISABLE)
+  {
+    /* Enable precharge of the selected Tamper pin */
+    RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS; 
+  }
+  else
+  {
+    /* Disable precharge of the selected Tamper pin */
+    RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS;    
+  } 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group10 Backup Data Registers configuration functions
+ *  @brief   Backup Data Registers configuration functions  
+ *
+@verbatim   
+ ===============================================================================
+          ##### Backup Data Registers configuration functions ##### 
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Writes a data in a specified RTC Backup data register.
+  * @param  RTC_BKP_DR: RTC Backup data Register number.
+  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 to 
+  *                                 specify the register.
+  * @param  Data: Data to be written in the specified RTC Backup data register.                     
+  * @retval None
+  */
+void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_BKP(RTC_BKP_DR));
+
+  tmp = RTC_BASE + 0x50;
+  tmp += (RTC_BKP_DR * 4);
+
+  /* Write the specified register */
+  *(__IO uint32_t *)tmp = (uint32_t)Data;
+}
+
+/**
+  * @brief  Reads data from the specified RTC Backup data Register.
+  * @param  RTC_BKP_DR: RTC Backup data Register number.
+  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to 
+  *                          specify the register.                   
+  * @retval None
+  */
+uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_BKP(RTC_BKP_DR));
+
+  tmp = RTC_BASE + 0x50;
+  tmp += (RTC_BKP_DR * 4);
+  
+  /* Read the specified register */
+  return (*(__IO uint32_t *)tmp);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group11 Output Type Config configuration functions
+ *  @brief   Output Type Config configuration functions  
+ *
+@verbatim   
+ ===============================================================================
+             ##### Output Type Config configuration functions ##### 
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the RTC Output Pin mode. 
+  * @param  RTC_OutputType: specifies the RTC Output (PC13) pin mode.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in 
+  *                                    Open Drain mode.
+  *            @arg RTC_OutputType_PushPull:  RTC Output (PC13) is configured in 
+  *                                    Push Pull mode.    
+  * @retval None
+  */
+void RTC_OutputTypeConfig(uint32_t RTC_OutputType)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType));
+  
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE);
+  RTC->TAFCR |= (uint32_t)(RTC_OutputType);  
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group12 Shift control synchronisation functions
+ *  @brief   Shift control synchronisation functions 
+ *
+@verbatim   
+ ===============================================================================
+            ##### Shift control synchronisation functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the Synchronization Shift Control Settings.
+  * @note   When REFCKON is set, firmware must not write to Shift control register 
+  * @param  RTC_ShiftAdd1S: Select to add or not 1 second to the time Calendar.
+  *          This parameter can be one of the following values :
+  *            @arg RTC_ShiftAdd1S_Set: Add one second to the clock calendar. 
+  *            @arg RTC_ShiftAdd1S_Reset: No effect.
+  * @param  RTC_ShiftSubFS: Select the number of Second Fractions to Substitute.
+  *         This parameter can be one any value from 0 to 0x7FFF.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Shift registers are configured
+  *          - ERROR: RTC Shift registers are not configured
+*/
+ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)
+{
+  ErrorStatus status = ERROR;
+  uint32_t shpfcount = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S));
+  assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  /* Check if a Shift is pending*/
+  if ((RTC->ISR & RTC_ISR_SHPF) != RESET)
+  {
+    /* Wait until the shift is completed*/
+    while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT))
+    {
+      shpfcount++;
+    }
+  }
+
+  /* Check if the Shift pending is completed or if there is no Shift operation at all*/
+  if ((RTC->ISR & RTC_ISR_SHPF) == RESET)
+  {
+    /* check if the reference clock detection is disabled */
+    if((RTC->CR & RTC_CR_REFCKON) == RESET)
+    {
+      /* Configure the Shift settings */
+      RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S);
+    
+      if(RTC_WaitForSynchro() == ERROR)
+      {
+        status = ERROR;
+      }
+      else
+      {
+        status = SUCCESS;
+      }
+    }
+    else
+    {
+      status = ERROR;
+    }
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+  
+  return (ErrorStatus)(status);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group13 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions  
+ *
+@verbatim   
+ ===============================================================================
+            ##### Interrupts and flags management functions #####
+ ===============================================================================  
+    [..] All RTC interrupts are connected to the EXTI controller.
+ 
+         (+) To enable the RTC Alarm interrupt, the following sequence is required:
+             (++) Configure and enable the EXTI Line 17 in interrupt mode and select the rising 
+                  edge sensitivity using the EXTI_Init() function.
+             (++) Configure and enable the RTC_Alarm IRQ channel in the NVIC using the NVIC_Init()
+                  function.
+             (++) Configure the RTC to generate RTC alarms (Alarm A) using
+                  the RTC_SetAlarm() and RTC_AlarmCmd() functions.
+
+         (+) To enable the RTC Tamper interrupt, the following sequence is required:
+             (++) Configure and enable the EXTI Line 19 in interrupt mode and select the rising 
+                  edge sensitivity using the EXTI_Init() function.
+             (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init()
+                  function.
+             (++) Configure the RTC to detect the RTC tamper event using the 
+                  RTC_TamperTriggerConfig() and RTC_TamperCmd() functions.
+
+         (+) To enable the RTC TimeStamp interrupt, the following sequence is required:
+             (++) Configure and enable the EXTI Line 19 in interrupt mode and select the rising 
+                  edge sensitivity using the EXTI_Init() function.
+             (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init()
+                  function.
+             (++) Configure the RTC to detect the RTC time-stamp event using the 
+                  RTC_TimeStampCmd() functions.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified RTC interrupts.
+  * @param  RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. 
+  *          This parameter can be any combination of the following values:
+  *            @arg RTC_IT_TS:  Time Stamp interrupt mask
+  *            @arg RTC_IT_WUT:  WakeUp Timer interrupt mask, available only for STM32F072 devices  
+  *            @arg RTC_IT_ALRA:  Alarm A interrupt mask
+  *            @arg RTC_IT_TAMP: Tamper event interrupt mask
+  * @param  NewState: new state of the specified RTC interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_CONFIG_IT(RTC_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  if (NewState != DISABLE)
+  {
+    /* Configure the Interrupts in the RTC_CR register */
+    RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE);
+    /* Configure the Tamper Interrupt in the RTC_TAFCR */
+    RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE);
+  }
+  else
+  {
+    /* Configure the Interrupts in the RTC_CR register */
+    RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE);
+    /* Configure the Tamper Interrupt in the RTC_TAFCR */
+    RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE);
+  }
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+}
+
+/**
+  * @brief  Checks whether the specified RTC flag is set or not.
+  * @param  RTC_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_FLAG_RECALPF: RECALPF event flag
+  *            @arg RTC_FLAG_TAMP2F: Tamper 2 event flag   
+  *            @arg RTC_FLAG_TAMP1F: Tamper 1 event flag
+  *            @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag
+  *            @arg RTC_FLAG_TSF: Time Stamp event flag
+  *            @arg RTC_FLAG_WUTF: WakeUp Timer flag, available only for STM32F072 devices  
+  *            @arg RTC_FLAG_ALRAF: Alarm A flag
+  *            @arg RTC_FLAG_INITF: Initialization mode flag
+  *            @arg RTC_FLAG_RSF: Registers Synchronized flag
+  *            @arg RTC_FLAG_INITS: Registers Configured flag
+  * @retval The new state of RTC_FLAG (SET or RESET).
+  */
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
+  
+  /* Get all the flags */
+  tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK);
+  
+  /* Return the status of the flag */
+  if ((tmpreg & RTC_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the RTC's pending flags.
+  * @param  RTC_FLAG: specifies the RTC flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg RTC_FLAG_TAMP2F: Tamper 2 event flag
+  *            @arg RTC_FLAG_TAMP1F: Tamper 1 event flag 
+  *            @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag 
+  *            @arg RTC_FLAG_TSF: Time Stamp event flag
+  *            @arg RTC_FLAG_WUTF: WakeUp Timer flag, available only for STM32F072 devices  
+  *            @arg RTC_FLAG_ALRAF: Alarm A flag
+  *            @arg RTC_FLAG_RSF: Registers Synchronized flag
+  * @retval None
+  */
+void RTC_ClearFlag(uint32_t RTC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
+
+  /* Clear the Flags in the RTC_ISR register */
+  RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0001FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT)));    
+}
+
+/**
+  * @brief  Checks whether the specified RTC interrupt has occurred or not.
+  * @param  RTC_IT: specifies the RTC interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_IT_TS: Time Stamp interrupt
+  *            @arg RTC_IT_WUT: WakeUp Timer interrupt, available only for STM32F072 devices
+  *            @arg RTC_IT_ALRA: Alarm A interrupt 
+  *            @arg RTC_IT_TAMP1: Tamper1 event interrupt 
+  *            @arg RTC_IT_TAMP2: Tamper2 event interrupt 
+  * @retval The new state of RTC_IT (SET or RESET).
+  */
+ITStatus RTC_GetITStatus(uint32_t RTC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t tmpreg = 0, enablestatus = 0;
+ 
+  /* Check the parameters */
+  assert_param(IS_RTC_GET_IT(RTC_IT));
+  
+  /* Get the TAMPER Interrupt enable bit and pending bit */
+  tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE));
+ 
+  /* Get the Interrupt enable Status */
+  enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & ((RTC_IT >> (RTC_IT >> 18)) >> 15)));
+  
+  /* Get the Interrupt pending bit */
+  tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4)));
+  
+  /* Get the status of the Interrupt */
+  if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the RTC's interrupt pending bits.
+  * @param  RTC_IT: specifies the RTC interrupt pending bit to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg RTC_IT_TS: Time Stamp interrupt 
+  *            @arg RTC_IT_WUT: WakeUp Timer interrupt, available only for STM32F072 devices
+  *            @arg RTC_IT_ALRA: Alarm A interrupt 
+  *            @arg RTC_IT_TAMP1: Tamper1 event interrupt
+  *            @arg RTC_IT_TAMP2: Tamper2 event interrupt
+  * @retval None
+  */
+void RTC_ClearITPendingBit(uint32_t RTC_IT)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_CLEAR_IT(RTC_IT));
+
+  /* Get the RTC_ISR Interrupt pending bits mask */
+  tmpreg = (uint32_t)(RTC_IT >> 4);
+
+  /* Clear the interrupt pending bits in the RTC_ISR register */
+  RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); 
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Converts a 2 digit decimal to BCD format.
+  * @param  Value: Byte to be converted.
+  * @retval Converted byte
+  */
+static uint8_t RTC_ByteToBcd2(uint8_t Value)
+{
+  uint8_t bcdhigh = 0;
+  
+  while (Value >= 10)
+  {
+    bcdhigh++;
+    Value -= 10;
+  }
+  
+  return  ((uint8_t)(bcdhigh << 4) | Value);
+}
+
+/**
+  * @brief  Convert from 2 digit BCD to Binary.
+  * @param  Value: BCD value to be converted.
+  * @retval Converted word
+  */
+static uint8_t RTC_Bcd2ToByte(uint8_t Value)
+{
+  uint8_t tmp = 0;
+  tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
+  return (tmp + (Value & (uint8_t)0x0F));
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_spi.c b/system/src/stm32f0-stdperiph/stm32f0xx_spi.c

new file mode 100644 (file)

index 0000000..949ef57
--- /dev/null
+++ b/system/src/stm32f0-stdperiph/stm32f0xx_spi.c
@@ -0,0 +1,1334 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_spi.c
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Serial peripheral interface (SPI):
+  *           + Initialization and Configuration
+  *           + Data transfers functions
+  *           + Hardware CRC Calculation
+  *           + DMA transfers management
+  *           + Interrupts and flags management
+  *
+  *  @verbatim
+
+ ===============================================================================
+                       ##### How to use this driver #####
+ ===============================================================================
+    [..]
+        (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE)
+            function for SPI1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE)
+            function for SPI2.
+  
+        (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using 
+            RCC_AHBPeriphClockCmd() function. 
+  
+        (#) Peripherals alternate function: 
+            (++) Connect the pin to the desired peripherals' Alternate 
+                 Function (AF) using GPIO_PinAFConfig() function.
+            (++) Configure the desired pin in alternate function by:
+                 GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
+            (++) Select the type, pull-up/pull-down and output speed via 
+                 GPIO_PuPd, GPIO_OType and GPIO_Speed members.
+            (++) Call GPIO_Init() function.
+  
+        (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave 
+            Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
+            function.In I2S mode, program the Mode, Standard, Data Format, MCLK 
+            Output, Audio frequency and Polarity using I2S_Init() function.
+  
+        (#) Configure the FIFO threshold using SPI_RxFIFOThresholdConfig() to select 
+            at which threshold the RXNE event is generated.
+            
+        (#) Enable the NVIC and the corresponding interrupt using the function 
+            SPI_ITConfig() if you need to use interrupt mode. 
+  
+        (#) When using the DMA mode 
+            (++) Configure the DMA using DMA_Init() function.
+            (++) Active the needed channel Request using SPI_I2S_DMACmd() function.
+   
+        (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using
+            I2S_Cmd().
+   
+        (#) Enable the DMA using the DMA_Cmd() function when using DMA mode. 
+  
+        (#) Optionally, you can enable/configure the following parameters without
+            re-initialization (i.e there is no need to call again SPI_Init() function):
+            (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)
+                 is programmed as Data direction parameter using the SPI_Init() 
+                 function it can be possible to switch between SPI_Direction_Tx 
+                 or SPI_Direction_Rx using the SPI_BiDirectionalLineConfig() function.
+            (++) When SPI_NSS_Soft is selected as Slave Select Management parameter 
+                 using the SPI_Init() function it can be possible to manage the 
+                 NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.
+            (++) Reconfigure the data size using the SPI_DataSizeConfig() function.
+            (++) Enable or disable the SS output using the SPI_SSOutputCmd() function.  
+  
+        (#) To use the CRC Hardware calculation feature refer to the Peripheral 
+            CRC hardware Calculation subsection.
+  
+    @endverbatim 
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_spi.h"
+#include "stm32f0xx_rcc.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup SPI
+  * @brief SPI driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* SPI registers Masks */
+#define CR1_CLEAR_MASK       ((uint16_t)0x3040)
+#define CR1_CLEAR_MASK2      ((uint16_t)0xFFFB)
+#define CR2_LDMA_MASK        ((uint16_t)0x9FFF)
+
+#define I2SCFGR_CLEAR_Mask   ((uint16_t)0xF040)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SPI_Private_Functions
+  * @{
+  */
+
+/** @defgroup SPI_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+           ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..] This section provides a set of functions allowing to initialize the SPI Direction,
+         SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud
+         Rate Prescaler, SPI First Bit and SPI CRC Polynomial.
+
+    [..] The SPI_Init() function follows the SPI configuration procedures for Master mode
+         and Slave mode (details for these procedures are available in reference manual).
+         
+    [..] When the Software NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Soft) is selected,
+         use the following function to manage the NSS bit:
+         void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
+
+    [..] In Master mode, when the Hardware NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Hard)
+         is selected, use the follwoing function to enable the NSS output feature.
+         void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+
+    [..] The NSS pulse mode can be managed by the SPI TI mode when enabling it using the following function:
+         void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+         And it can be managed by software in the SPI Motorola mode using this function: 
+         void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+
+    [..] This section provides also functions to initialize the I2S Mode, Standard, 
+         Data Format, MCLK Output, Audio frequency and Polarity.
+  
+    [..] The I2S_Init() function follows the I2S configuration procedures for Master mode
+         and Slave mode.
+  
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the SPIx peripheral registers to their default
+  *         reset values.
+  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
+  * @note   SPI2 is not available for STM32F031 devices.
+  *         I2S mode is not supported for STM32F030 devices.      
+  * @retval None
+  */
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+  if (SPIx == SPI1)
+  {
+    /* Enable SPI1 reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
+    /* Release SPI1 from reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
+  }
+  else
+  {
+    if (SPIx == SPI2)
+    {
+      /* Enable SPI2 reset state */
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
+      /* Release SPI2 from reset state */
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
+    }
+  }
+}
+
+/**
+  * @brief  Fills each SPI_InitStruct member with its default value.
+  * @param  SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
+{
+/*--------------- Reset SPI init structure parameters values -----------------*/
+  /* Initialize the SPI_Direction member */
+  SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+  /* Initialize the SPI_Mode member */
+  SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
+  /* Initialize the SPI_DataSize member */
+  SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
+  /* Initialize the SPI_CPOL member */
+  SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
+  /* Initialize the SPI_CPHA member */
+  SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
+  /* Initialize the SPI_NSS member */
+  SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
+  /* Initialize the SPI_BaudRatePrescaler member */
+  SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+  /* Initialize the SPI_FirstBit member */
+  SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
+  /* Initialize the SPI_CRCPolynomial member */
+  SPI_InitStruct->SPI_CRCPolynomial = 7;
+}
+
+/**
+  * @brief  Initializes the SPIx peripheral according to the specified 
+  *         parameters in the SPI_InitStruct.
+  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
+  * @note   SPI2 is not available for STM32F031 devices. 
+  * @param  SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
+  *         contains the configuration information for the specified SPI peripheral.
+  * @retval None
+  */
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
+{
+  uint16_t tmpreg = 0;
+
+  /* check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+  /* Check the SPI parameters */
+  assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
+  assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
+  assert_param(IS_SPI_DATA_SIZE(SPI_InitStruct->SPI_DataSize));
+  assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
+  assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
+  assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
+  assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
+  assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
+  assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
+
+  /*---------------------------- SPIx CR1 Configuration ------------------------*/
+  /* Get the SPIx CR1 value */
+  tmpreg = SPIx->CR1;
+  /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, CPOL and CPHA bits */
+  tmpreg &= CR1_CLEAR_MASK;
+  /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
+  master/slave mode, CPOL and CPHA */
+  /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
+  /* Set SSM, SSI bit according to SPI_NSS values */
+  /* Set LSBFirst bit according to SPI_FirstBit value */
+  /* Set BR bits according to SPI_BaudRatePrescaler value */
+  /* Set CPOL bit according to SPI_CPOL value */
+  /* Set CPHA bit according to SPI_CPHA value */
+  tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_FirstBit |
+                      SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA |
+                      SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler);  
+  /* Write to SPIx CR1 */
+  SPIx->CR1 = tmpreg;
+  /*-------------------------Data Size Configuration -----------------------*/
+  /* Get the SPIx CR2 value */
+  tmpreg = SPIx->CR2;
+  /* Clear DS[3:0] bits */
+  tmpreg &=(uint16_t)~SPI_CR2_DS;
+  /* Configure SPIx: Data Size */
+  tmpreg |= (uint16_t)(SPI_InitStruct->SPI_DataSize);
+  /* Write to SPIx CR2 */
+  SPIx->CR2 = tmpreg;
+  
+  /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
+  /* Write to SPIx CRCPOLY */
+  SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
+  
+  /*---------------------------- SPIx CR1 Configuration ------------------------*/
+  /* Get the SPIx CR1 value */
+  tmpreg = SPIx->CR1;
+  /* Clear MSTR bit */
+  tmpreg &= CR1_CLEAR_MASK2;
+  /* Configure SPIx: master/slave mode */  
+  /* Set MSTR bit according to SPI_Mode */
+  tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Mode);  
+  /* Write to SPIx CR1 */
+  SPIx->CR1 = tmpreg;  
+  
+  /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
+  SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD);
+}
+
+/**
+  * @brief  Fills each I2S_InitStruct member with its default value.
+  * @note   This mode is not supported for STM32F030 devices.  
+  * @param  I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
+{
+/*--------------- Reset I2S init structure parameters values -----------------*/
+  /* Initialize the I2S_Mode member */
+  I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
+
+  /* Initialize the I2S_Standard member */
+  I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
+
+  /* Initialize the I2S_DataFormat member */
+  I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
+
+  /* Initialize the I2S_MCLKOutput member */
+  I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
+
+  /* Initialize the I2S_AudioFreq member */
+  I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
+
+  /* Initialize the I2S_CPOL member */
+  I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
+}
+
+/**
+  * @brief  Initializes the SPIx peripheral according to the specified 
+  *         parameters in the I2S_InitStruct.
+  * @note   This mode is not supported for STM32F030 devices.  
+  * @param  SPIx: where x can be 1 to select the SPI peripheral (configured in I2S mode).  
+  * @param  I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
+  *         contains the configuration information for the specified SPI peripheral
+  *         configured in I2S mode.
+  * @note   This function calculates the optimal prescaler needed to obtain the most 
+  *         accurate audio frequency (depending on the I2S clock source, the PLL values 
+  *         and the product configuration). But in case the prescaler value is greater 
+  *         than 511, the default value (0x02) will be configured instead.
+  * @retval None
+  */
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
+{
+  uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
+  uint32_t tmp = 0;
+  RCC_ClocksTypeDef RCC_Clocks;
+  uint32_t sourceclock = 0;
+
+  /* Check the I2S parameters */
+  assert_param(IS_SPI_1_PERIPH(SPIx));
+  assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
+  assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
+  assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
+  assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
+  assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
+  assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));  
+
+/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
+  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+  SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; 
+  SPIx->I2SPR = 0x0002;
+
+  /* Get the I2SCFGR register value */
+  tmpreg = SPIx->I2SCFGR;
+
+  /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
+  if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
+  {
+    i2sodd = (uint16_t)0;
+    i2sdiv = (uint16_t)2;   
+  }
+  /* If the requested audio frequency is not the default, compute the prescaler */
+  else
+  {
+    /* Check the frame length (For the Prescaler computing) */
+    if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
+    {
+      /* Packet length is 16 bits */
+      packetlength = 1;
+    }
+    else
+    {
+      /* Packet length is 32 bits */
+      packetlength = 2;
+    }
+
+    /* I2S Clock source is System clock: Get System Clock frequency */
+    RCC_GetClocksFreq(&RCC_Clocks);      
+
+    /* Get the source clock value: based on System Clock value */
+    sourceclock = RCC_Clocks.SYSCLK_Frequency;    
+
+    /* Compute the Real divider depending on the MCLK output state with a floating point */
+    if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
+    {
+      /* MCLK output is enabled */
+      tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+    }
+    else
+    {
+      /* MCLK output is disabled */
+      tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+    }
+    
+    /* Remove the floating point */
+    tmp = tmp / 10;
+
+    /* Check the parity of the divider */
+    i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
+
+    /* Compute the i2sdiv prescaler */
+    i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
+
+    /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+    i2sodd = (uint16_t) (i2sodd << 8);
+  }
+
+  /* Test if the divider is 1 or 0 or greater than 0xFF */
+  if ((i2sdiv < 2) || (i2sdiv > 0xFF))
+  {
+    /* Set the default values */
+    i2sdiv = 2;
+    i2sodd = 0;
+  }
+
+  /* Write to SPIx I2SPR register the computed value */
+  SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
+
+  /* Configure the I2S with the SPI_InitStruct values */
+  tmpreg |= (uint16_t)(SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \
+                  (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
+                  (uint16_t)I2S_InitStruct->I2S_CPOL))));
+
+  /* Write to SPIx I2SCFGR */
+  SPIx->I2SCFGR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the specified SPI peripheral.
+  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
+  * @note   SPI2 is not available for STM32F031 devices.
+  * @param  NewState: new state of the SPIx peripheral. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI peripheral */
+    SPIx->CR1 |= SPI_CR1_SPE;
+  }
+  else
+  {
+    /* Disable the selected SPI peripheral */
+    SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);
+  }
+}
+
+/**
+  * @brief  Enables or disables the TI Mode.
+  *   
+  * @note   This function can be called only after the SPI_Init() function has 
+  *         been called. 
+  * @note   When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA 
+  *         are not taken into consideration and are configured by hardware 
+  *         respectively to the TI mode requirements.
+  *    
+  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
+  * @note   SPI2 is not available for STM32F031 devices.
+  * @param  NewState: new state of the selected SPI TI communication mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the TI mode for the selected SPI peripheral */
+    SPIx->CR2 |= SPI_CR2_FRF;
+  }
+  else
+  {
+    /* Disable the TI mode for the selected SPI peripheral */
+    SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRF);
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified SPI peripheral (in I2S mode).
+  * @note   This mode is not supported for STM32F030 devices.    
+  * @param  SPIx: where x can be 1 to select the SPI peripheral.
+  * @param  NewState: new state of the SPIx peripheral. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_1_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI peripheral in I2S mode */
+    SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE;
+  }
+  else
+  {
+    /* Disable the selected SPI peripheral in I2S mode */
+    SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE);
+  }
+}
+
+/**
+  * @brief  Configures the data size for the selected SPI.
+  * @param  SPIx: where x can be 1 or 2  to select the SPI peripheral.
+  * @note   SPI2 is not available for STM32F031 devices. 
+  * @param  SPI_DataSize: specifies the SPI data size.
+  *         For the SPIx peripheral this parameter can be one of the following values:
+  *            @arg SPI_DataSize_4b: Set data size to 4 bits
+  *            @arg SPI_DataSize_5b: Set data size to 5 bits
+  *            @arg SPI_DataSize_6b: Set data size to 6 bits
+  *            @arg SPI_DataSize_7b: Set data size to 7 bits
+  *            @arg SPI_DataSize_8b: Set data size to 8 bits
+  *            @arg SPI_DataSize_9b: Set data size to 9 bits
+  *            @arg SPI_DataSize_10b: Set data size to 10 bits
+  *            @arg SPI_DataSize_11b: Set data size to 11 bits
+  *            @arg SPI_DataSize_12b: Set data size to 12 bits
+  *            @arg SPI_DataSize_13b: Set data size to 13 bits
+  *            @arg SPI_DataSize_14b: Set data size to 14 bits
+  *            @arg SPI_DataSize_15b: Set data size to 15 bits
+  *            @arg SPI_DataSize_16b: Set data size to 16 bits
+  * @retval None
+  */
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
+{
+  uint16_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_DATA_SIZE(SPI_DataSize));
+  /* Read the CR2 register */
+  tmpreg = SPIx->CR2;
+  /* Clear DS[3:0] bits */
+  tmpreg &= (uint16_t)~SPI_CR2_DS;
+  /* Set new DS[3:0] bits value */
+  tmpreg |= SPI_DataSize;
+  SPIx->CR2 = tmpreg;
+}
+
+/**
+  * @brief  Configures the FIFO reception threshold for the selected SPI.
+  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
+  * @note   SPI2 is not available for STM32F031 devices. 
+  * @param  SPI_RxFIFOThreshold: specifies the FIFO reception threshold.
+  *          This parameter can be one of the following values:
+  *            @arg SPI_RxFIFOThreshold_HF: RXNE event is generated if the FIFO 
+  *                                         level is greater or equal to 1/2. 
+  *            @arg SPI_RxFIFOThreshold_QF: RXNE event is generated if the FIFO 
+  *                                         level is greater or equal to 1/4. 
+  * @retval None
+  */
+void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_RX_FIFO_THRESHOLD(SPI_RxFIFOThreshold));
+
+  /* Clear FRXTH bit */
+  SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRXTH);
+
+  /* Set new FRXTH bit value */
+  SPIx->CR2 |= SPI_RxFIFOThreshold;
+}
+
+/**
+  * @brief  Selects the data transfer direction in bidirectional mode for the specified SPI.
+  * @param  SPIx: where x can be 1 or 2  to select the SPI peripheral.
+  * @note   SPI2 is not available for STM32F031 devices. 
+  * @param  SPI_Direction: specifies the data transfer direction in bidirectional mode. 
+  *          This parameter can be one of the following values:
+  *            @arg SPI_Direction_Tx: Selects Tx transmission direction
+  *            @arg SPI_Direction_Rx: Selects Rx receive direction
+  * @retval None
+  */
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_DIRECTION(SPI_Direction));
+  if (SPI_Direction == SPI_Direction_Tx)
+  {
+    /* Set the Tx only mode */
+    SPIx->CR1 |= SPI_Direction_Tx;
+  }
+  else
+  {
+    /* Set the Rx only mode */
+    SPIx->CR1 &= SPI_Direction_Rx;
+  }
+}
+
+/**
+  * @brief  Configures internally by software the NSS pin for the selected SPI.
+  * @note   This function can be called only after the SPI_Init() function has 
+  *         been called.  
+  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
+  * @note   SPI2 is not available for STM32F031 devices.  
+  * @param  SPI_NSSInternalSoft: specifies the SPI NSS internal state.
+  *          This parameter can be one of the following values:
+  *            @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
+  *            @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
+  * @retval None
+  */
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
+
+  if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
+  {
+    /* Set NSS pin internally by software */
+    SPIx->CR1 |= SPI_NSSInternalSoft_Set;
+  }
+  else
+  {
+    /* Reset NSS pin internally by software */
+    SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the SS output for the selected SPI.
+  * @note   This function can be called only after the SPI_Init() function has 
+  *         been called and the NSS hardware management mode is selected. 
+  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
+  * @note   SPI2 is not available for STM32F031 devices.  
+  * @param  NewState: new state of the SPIx SS output. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI SS output */
+    SPIx->CR2 |= SPI_CR2_SSOE;
+  }
+  else
+  {
+    /* Disable the selected SPI SS output */
+    SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);
+  }
+}
+
+/**
+  * @brief  Enables or disables the NSS pulse management mode.
+  * @note   This function can be called only after the SPI_Init() function has 
+  *         been called. 
+  * @note   When TI mode is selected, the control bits NSSP is not taken into 
+  *         consideration and are configured by hardware respectively to the 
+  *         TI mode requirements. 
+  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
+  * @note   SPI2 is not available for STM32F031 devices.
+  * @param  NewState: new state of the NSS pulse management mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the NSS pulse management mode */
+    SPIx->CR2 |= SPI_CR2_NSSP;
+  }
+  else
+  {
+    /* Disable the NSS pulse management mode */
+    SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_NSSP);    
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Group2 Data transfers functions
+ *  @brief   Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+                    ##### Data transfers functions #####
+ ===============================================================================
+    [..] This section provides a set of functions allowing to manage the SPI or I2S
+         data transfers.
+
+    [..] In reception, data are received and then stored into an internal Rx buffer while 
+         In transmission, data are first stored into an internal Tx buffer before being 
+         transmitted.
+
+    [..] The read access of the SPI_DR register can be done using 
+         SPI_ReceiveData8() (when data size is equal or inferior than 8bits) and.
+         SPI_I2S_ReceiveData16() (when data size is superior than 8bits)function
+         and returns the Rx buffered value. Whereas a write access to the SPI_DR 
+         can be done using SPI_SendData8() (when data size is equal or inferior than 8bits)
+         and SPI_I2S_SendData16() (when data size is superior than 8bits) function 
+         and stores the written data into Tx buffer.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmits a Data through the SPIx/I2Sx peripheral.
+  * @param  SPIx: where x can be 1 or 2 in SPI mode to select the SPI peripheral.
+  * @note   SPI2 is not available for STM32F031 devices.
+  * @param  Data: Data to be transmitted.
+  * @retval None
+  */
+void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data)
+{
+  uint32_t spixbase = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+  spixbase = (uint32_t)SPIx; 
+  spixbase += 0x0C;
+  
+  *(__IO uint8_t *) spixbase = Data;
+}
+
+/**
+  * @brief  Transmits a Data through the SPIx/I2Sx peripheral.
+  * @param  SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select 
+  *         the SPI peripheral. 
+  * @note   SPI2 is not available for STM32F031 devices. 
+  * @param  Data: Data to be transmitted.
+  * @retval None
+  */
+void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  
+  SPIx->DR = (uint16_t)Data;
+}
+
+/**
+  * @brief  Returns the most recent received data by the SPIx/I2Sx peripheral. 
+  * @param  SPIx: where x can be 1 or 2 in SPI mode to select the SPI peripheral. 
+  * @note   SPI2 is not available for STM32F031 devices.
+  * @retval The value of the received data.
+  */
+uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx)
+{
+  uint32_t spixbase = 0x00;
+  
+  spixbase = (uint32_t)SPIx; 
+  spixbase += 0x0C;
+  
+  return *(__IO uint8_t *) spixbase;
+}
+
+/**
+  * @brief  Returns the most recent received data by the SPIx peripheral. 
+  * @param  SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select
+  * @note   SPI2 is not available for STM32F031 devices.
+  *         the SPI peripheral.  
+  * @retval The value of the received data.
+  */
+uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx)
+{
+  return SPIx->DR;
+}
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Group3 Hardware CRC Calculation functions
+ *  @brief   Hardware CRC Calculation functions
+ *
+@verbatim   
+ ===============================================================================
+                ##### Hardware CRC Calculation functions #####
+ ===============================================================================
+    [..] This section provides a set of functions allowing to manage the SPI CRC hardware 
+         calculation.SPI communication using CRC is possible through the following procedure:
+
+         (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler,
+             Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
+             function.
+         (#) Enable the CRC calculation using the SPI_CalculateCRC() function.
+         (#) Enable the SPI using the SPI_Cmd() function
+         (#) Before writing the last data to the TX buffer, set the CRCNext bit using the 
+             SPI_TransmitCRC() function to indicate that after transmission of the last 
+             data, the CRC should be transmitted.
+         (#) After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT
+             bit is reset. The CRC is also received and compared against the SPI_RXCRCR 
+             value. 
+             If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt
+             can be generated when the SPI_I2S_IT_ERR interrupt is enabled.
+
+    -@-
+       (+@) It is advised to don't read the calculate CRC values during the communication.
+       (+@) When the SPI is in slave mode, be careful to enable CRC calculation only
+       when the clock is stable, that is, when the clock is in the steady state. 
+       If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive 
+       to the SCK slave input clock as soon as CRCEN is set, and this, whatever 
+       the value of the SPE bit.
+       (+@) With high bitrate frequencies, be careful when transmitting the CRC.
+       As the number of used CPU cycles has to be as low as possible in the CRC 
+       transfer phase, it is forbidden to call software functions in the CRC 
+       transmission sequence to avoid errors in the last data and CRC reception. 
+       In fact, CRCNEXT bit has to be written before the end of the transmission/reception 
+       of the last data.
+       (+@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the
+       degradation of the SPI speed performance due to CPU accesses impacting the 
+       SPI bandwidth.
+       (+@) When the STM32F0xx are configured as slaves and the NSS hardware mode is 
+       used, the NSS pin needs to be kept low between the data phase and the CRC 
+       phase.
+       (+@) When the SPI is configured in slave mode with the CRC feature enabled, CRC
+       calculation takes place even if a high level is applied on the NSS pin. 
+       This may happen for example in case of a multislave environment where the 
+       communication master addresses slaves alternately.
+       (+@) Between a slave deselection (high level on NSS) and a new slave selection
+       (low level on NSS), the CRC value should be cleared on both master and slave
+       sides in order to resynchronize the master and slave for their respective 
+       CRC calculation.
+
+    -@- To clear the CRC, follow the procedure below:
+       (#@) Disable SPI using the SPI_Cmd() function
+       (#@) Disable the CRC calculation using the SPI_CalculateCRC() function.
+       (#@) Enable the CRC calculation using the SPI_CalculateCRC() function.
+       (#@) Enable SPI using the SPI_Cmd() function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the CRC calculation length for the selected SPI.
+  * @note   This function can be called only after the SPI_Init() function has 
+  *         been called.  
+  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
+  * @note   SPI2 is not available for STM32F031 devices.  
+  * @param  SPI_CRCLength: specifies the SPI CRC calculation length.
+  *          This parameter can be one of the following values:
+  *            @arg SPI_CRCLength_8b: Set CRC Calculation to 8 bits
+  *            @arg SPI_CRCLength_16b: Set CRC Calculation to 16 bits
+  * @retval None
+  */
+void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_CRC_LENGTH(SPI_CRCLength));
+
+  /* Clear CRCL bit */
+  SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCL);
+
+  /* Set new CRCL bit value */
+  SPIx->CR1 |= SPI_CRCLength;
+}
+
+/**
+  * @brief  Enables or disables the CRC value calculation of the transferred bytes.
+  * @note   This function can be called only after the SPI_Init() function has 
+  *         been called.   
+  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
+  * @note   SPI2 is not available for STM32F031 devices.
+  * @param  NewState: new state of the SPIx CRC value calculation.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI CRC calculation */
+    SPIx->CR1 |= SPI_CR1_CRCEN;
+  }
+  else
+  {
+    /* Disable the selected SPI CRC calculation */
+    SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);
+  }
+}
+
+/**
+  * @brief  Transmit the SPIx CRC value.
+  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
+  * @note   SPI2 is not available for STM32F031 devices. 
+  * @retval None
+  */
+void SPI_TransmitCRC(SPI_TypeDef* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+  /* Enable the selected SPI CRC transmission */
+  SPIx->CR1 |= SPI_CR1_CRCNEXT;
+}
+
+/**
+  * @brief  Returns the transmit or the receive CRC register value for the specified SPI.
+  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
+  * @note   SPI2 is not available for STM32F031 devices. 
+  * @param  SPI_CRC: specifies the CRC register to be read.
+  *          This parameter can be one of the following values:
+  *            @arg SPI_CRC_Tx: Selects Tx CRC register
+  *            @arg SPI_CRC_Rx: Selects Rx CRC register
+  * @retval The selected CRC register value..
+  */
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
+{
+  uint16_t crcreg = 0;
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_CRC(SPI_CRC));
+
+  if (SPI_CRC != SPI_CRC_Rx)
+  {
+    /* Get the Tx CRC register */
+    crcreg = SPIx->TXCRCR;
+  }
+  else
+  {
+    /* Get the Rx CRC register */
+    crcreg = SPIx->RXCRCR;
+  }
+  /* Return the selected CRC register */
+  return crcreg;
+}
+
+/**
+  * @brief  Returns the CRC Polynomial register value for the specified SPI.
+  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
+  * @note   SPI2 is not available for STM32F031 devices. 
+  * @retval The CRC Polynomial register value.
+  */
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+  /* Return the CRC polynomial register */
+  return SPIx->CRCPR;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Group4 DMA transfers management functions
+ *  @brief   DMA transfers management functions
+  *
+@verbatim   
+ ===============================================================================
+                ##### DMA transfers management functions #####
+ ===============================================================================
+    [..] This section provides two functions that can be used only in DMA mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the SPIx/I2Sx DMA interface.
+  * @param  SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select 
+  *         the SPI peripheral.
+  * @note   SPI2 is not available for STM32F031 devices.
+  *         I2S mode is not supported for STM32F030 devices.  
+  * @param  SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. 
+  *          This parameter can be any combination of the following values:
+  *            @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
+  *            @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
+  * @param  NewState: new state of the selected SPI DMA transfer request.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_SPI_I2S_DMA_REQ(SPI_I2S_DMAReq));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI DMA requests */
+    SPIx->CR2 |= SPI_I2S_DMAReq;
+  }
+  else
+  {
+    /* Disable the selected SPI DMA requests */
+    SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
+  }
+}
+
+/**
+  * @brief  Configures the number of data to transfer type(Even/Odd) for the DMA
+  *         last transfers and for the selected SPI.
+  * @note   This function have a meaning only if DMA mode is selected and if 
+  *         the packing mode is used (data length <= 8 and DMA transfer size halfword)  
+  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
+  * @note   SPI2 is not available for STM32F031 devices.
+  * @param  SPI_LastDMATransfer: specifies the SPI last DMA transfers state.
+  *          This parameter can be one of the following values:
+  *            @arg SPI_LastDMATransfer_TxEvenRxEven: Number of data for transmission Even
+  *                                                   and number of data for reception Even.
+  *            @arg SPI_LastDMATransfer_TxOddRxEven: Number of data for transmission Odd
+  *                                                  and number of data for reception Even.
+  *            @arg SPI_LastDMATransfer_TxEvenRxOdd: Number of data for transmission Even
+  *                                                  and number of data for reception Odd.
+  *            @arg SPI_LastDMATransfer_TxOddRxOdd: Number of data for transmission Odd
+  *                                                 and number of data for reception Odd.
+  * @retval None
+  */
+void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_LAST_DMA_TRANSFER(SPI_LastDMATransfer));
+
+  /* Clear LDMA_TX and LDMA_RX bits */
+  SPIx->CR2 &= CR2_LDMA_MASK;
+
+  /* Set new LDMA_TX and LDMA_RX bits value */
+  SPIx->CR2 |= SPI_LastDMATransfer; 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Group5 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+  *
+@verbatim   
+ ===============================================================================
+             ##### Interrupts and flags management functions #####
+ ===============================================================================
+    [..] This section provides a set of functions allowing to configure the SPI/I2S Interrupts 
+         sources and check or clear the flags or pending bits status.
+         The user should identify which mode will be used in his application to manage 
+         the communication: Polling mode, Interrupt mode or DMA mode. 
+
+  *** Polling Mode ***
+  ====================
+    [..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags:
+        (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register
+        (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register
+        (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI.
+        (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur              
+        (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur
+        (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur
+        (#) SPI_I2S_FLAG_FRE: to indicate a Frame Format error occurs.
+        (#) I2S_FLAG_UDR: to indicate an Underrun error occurs.
+        (#) I2S_FLAG_CHSIDE: to indicate Channel Side.
+
+    [..]
+        (@)Do not use the BSY flag to handle each data transmission or reception. It is better 
+           to use the TXE and RXNE flags instead.
+
+    [..] In this Mode it is advised to use the following functions:
+        (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+        (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+
+  *** Interrupt Mode ***
+  ======================
+    [..] In Interrupt Mode, the SPI/I2S communication can be managed by 3 interrupt sources
+         and 5 pending bits: 
+    [..] Pending Bits:
+        (#) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register
+        (#) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register
+        (#) SPI_I2S_IT_OVR : to indicate if an Overrun error occur
+        (#) I2S_IT_UDR : to indicate an Underrun Error occurs.
+        (#) SPI_I2S_FLAG_FRE : to indicate a Frame Format error occurs.
+
+    [..] Interrupt Source:
+        (#) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty 
+            interrupt.  
+        (#) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not 
+            empty interrupt.
+        (#) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.
+
+    [..] In this Mode it is advised to use the following functions:
+         (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
+         (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+
+  *** FIFO Status ***
+  ===================
+    [..] It is possible to monitor the FIFO status when a transfer is ongoing using the
+         following function:
+         (+) uint32_t SPI_GetFIFOStatus(uint8_t SPI_FIFO_Direction); 
+
+  *** DMA Mode ***
+  ================
+    [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel 
+         requests:
+        (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
+        (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
+
+    [..] In this Mode it is advised to use the following function:
+        (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified SPI/I2S interrupts.
+  * @param  SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select 
+  *         the SPI peripheral.  
+  * @note   SPI2 is not available for STM32F031 devices.
+  *         I2S mode is not supported for STM32F030 devices.  
+  * @param  SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. 
+  *          This parameter can be one of the following values:
+  *            @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
+  *            @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
+  *            @arg SPI_I2S_IT_ERR: Error interrupt mask
+  * @param  NewState: new state of the specified SPI interrupt.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
+{
+  uint16_t itpos = 0, itmask = 0 ;
+
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
+
+  /* Get the SPI IT index */
+  itpos = SPI_I2S_IT >> 4;
+
+  /* Set the IT mask */
+  itmask = (uint16_t)1 << (uint16_t)itpos;
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI interrupt */
+    SPIx->CR2 |= itmask;
+  }
+  else
+  {
+    /* Disable the selected SPI interrupt */
+    SPIx->CR2 &= (uint16_t)~itmask;
+  }
+}
+
+/**
+  * @brief  Returns the current SPIx Transmission FIFO filled level.
+  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
+  * @note   SPI2 is not available for STM32F031 devices.
+  * @retval The Transmission FIFO filling state.
+  *          - SPI_TransmissionFIFOStatus_Empty: when FIFO is empty
+  *          - SPI_TransmissionFIFOStatus_1QuarterFull: if more than 1 quarter-full.
+  *          - SPI_TransmissionFIFOStatus_HalfFull: if more than 1 half-full.
+  *          - SPI_TransmissionFIFOStatus_Full: when FIFO is full.
+  */
+uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx)
+{
+  /* Get the SPIx Transmission FIFO level bits */
+  return (uint16_t)((SPIx->SR & SPI_SR_FTLVL));
+}
+
+/**
+  * @brief  Returns the current SPIx Reception FIFO filled level.
+  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
+  * @note   SPI2 is not available for STM32F031 devices.
+  * @retval The Reception FIFO filling state.
+  *          - SPI_ReceptionFIFOStatus_Empty: when FIFO is empty
+  *          - SPI_ReceptionFIFOStatus_1QuarterFull: if more than 1 quarter-full.
+  *          - SPI_ReceptionFIFOStatus_HalfFull: if more than 1 half-full.
+  *          - SPI_ReceptionFIFOStatus_Full: when FIFO is full.
+  */
+uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx)
+{
+  /* Get the SPIx Reception FIFO level bits */
+  return (uint16_t)((SPIx->SR & SPI_SR_FRLVL));
+}
+
+/**
+  * @brief  Checks whether the specified SPI flag is set or not.
+  * @param  SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select 
+  *         the SPI peripheral.    
+  * @note   SPI2 is not available for STM32F031 devices.
+  *         I2S mode is not supported for STM32F030 devices.  
+  * @param  SPI_I2S_FLAG: specifies the SPI flag to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
+  *            @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
+  *            @arg SPI_I2S_FLAG_BSY: Busy flag.
+  *            @arg SPI_I2S_FLAG_OVR: Overrun flag.
+  *            @arg SPI_FLAG_MODF: Mode Fault flag.
+  *            @arg SPI_FLAG_CRCERR: CRC Error flag.
+  *            @arg SPI_I2S_FLAG_FRE: TI frame format error flag.
+  *            @arg I2S_FLAG_UDR: Underrun Error flag.
+  *            @arg I2S_FLAG_CHSIDE: Channel Side flag.   
+  * @retval The new state of SPI_I2S_FLAG (SET or RESET).
+  */
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
+
+  /* Check the status of the specified SPI flag */
+  if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
+  {
+    /* SPI_I2S_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* SPI_I2S_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the SPI_I2S_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the SPIx CRC Error (CRCERR) flag.
+  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
+  * @note   SPI2 is not available for STM32F031 devices.
+  *         I2S mode is not supported for STM32F030 devices.  
+  * @param  SPI_I2S_FLAG: specifies the SPI flag to clear. 
+  *         This function clears only CRCERR flag.
+  * @note   OVR (OverRun error) flag is cleared by software sequence: a read 
+  *         operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by  
+  *         a read operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
+  * @note   MODF (Mode Fault) flag is cleared by software sequence: a read/write 
+  *         operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by
+  *         a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
+  * @retval None
+  */
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_CLEAR_FLAG(SPI_I2S_FLAG));
+
+  /* Clear the selected SPI CRC Error (CRCERR) flag */
+  SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified SPI/I2S interrupt has occurred or not.
+  * @param  SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select 
+  *         the SPI peripheral.
+  * @param  SPI_I2S_IT: specifies the SPI interrupt source to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
+  *            @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
+  *            @arg SPI_IT_MODF: Mode Fault interrupt.
+  *            @arg SPI_I2S_IT_OVR: Overrun interrupt.
+  *            @arg I2S_IT_UDR: Underrun interrupt.  
+  *            @arg SPI_I2S_IT_FRE: Format Error interrupt.  
+  * @retval The new state of SPI_I2S_IT (SET or RESET).
+  */
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint16_t itpos = 0, itmask = 0, enablestatus = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
+
+  /* Get the SPI_I2S_IT index */
+  itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+
+  /* Get the SPI_I2S_IT IT mask */
+  itmask = SPI_I2S_IT >> 4;
+
+  /* Set the IT mask */
+  itmask = 0x01 << itmask;
+
+  /* Get the SPI_I2S_IT enable bit status */
+  enablestatus = (SPIx->CR2 & itmask) ;
+
+  /* Check the status of the specified SPI interrupt */
+  if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
+  {
+    /* SPI_I2S_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* SPI_I2S_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the SPI_I2S_IT status */
+  return bitstatus;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_syscfg.c b/system/src/stm32f0-stdperiph/stm32f0xx_syscfg.c

new file mode 100644 (file)

index 0000000..5c7cdd3
--- /dev/null
+++ b/system/src/stm32f0-stdperiph/stm32f0xx_syscfg.c
@@ -0,0 +1,420 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_syscfg.c
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the SYSCFG peripheral:
+  *           + Remapping the memory mapped at 0x00000000  
+  *           + Remapping the DMA channels
+  *           + Enabling I2C fast mode plus driving capability for I2C pins   
+  *           + Configuring the EXTI lines connection to the GPIO port
+  *           + Configuring the CFGR2 features (Connecting some internal signal
+  *             to the break input of TIM1)
+  *   
+  *  @verbatim
+ ===============================================================================
+                     ##### How to use this driver #####
+ ===============================================================================
+    [..] 
+               The SYSCFG registers can be accessed only when the SYSCFG 
+               interface APB clock is enabled.
+               To enable SYSCFG APB clock use:
+               RCC_APBPeriphClockCmd(RCC_APBPeriph_SYSCFG, ENABLE).
+  *  @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_syscfg.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup SYSCFG 
+  * @brief SYSCFG driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SYSCFG_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions
+ *  @brief   SYSCFG Initialization and Configuration functions 
+ *
+@verbatim
+ ===============================================================================
+        ##### SYSCFG Initialization and Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the SYSCFG registers to their default reset values.
+  * @param  None
+  * @retval None
+  * @note   MEM_MODE bits are not affected by APB reset.
+  * @note   MEM_MODE bits took the value from the user option bytes.
+  * @note   CFGR2 register is not affected by APB reset.
+  * @note   CLABBB configuration bits are locked when set.
+  * @note   To unlock the configuration, perform a system reset.
+  */
+void SYSCFG_DeInit(void)
+{
+  /* Set SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */
+  SYSCFG->CFGR1 &= SYSCFG_CFGR1_MEM_MODE;
+  /* Set EXTICRx registers to reset value */
+  SYSCFG->EXTICR[0] = 0;
+  SYSCFG->EXTICR[1] = 0;
+  SYSCFG->EXTICR[2] = 0;
+  SYSCFG->EXTICR[3] = 0;
+  /* Set CFGR2 register to reset value: clear SRAM parity error flag */
+  SYSCFG->CFGR2 |= (uint32_t) SYSCFG_CFGR2_SRAM_PE;
+}
+
+/**
+  * @brief  Configures the memory mapping at address 0x00000000.
+  * @param  SYSCFG_MemoryRemap: selects the memory remapping.
+  *          This parameter can be one of the following values:
+  *            @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000  
+  *            @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000
+  *            @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000
+  * @retval None
+  */
+void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap)
+{
+  uint32_t tmpctrl = 0;
+
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap));
+
+  /* Get CFGR1 register value */
+  tmpctrl = SYSCFG->CFGR1;
+
+  /* Clear MEM_MODE bits */
+  tmpctrl &= (uint32_t) (~SYSCFG_CFGR1_MEM_MODE);
+
+  /* Set the new MEM_MODE bits value */
+  tmpctrl |= (uint32_t) SYSCFG_MemoryRemap;
+
+  /* Set CFGR1 register with the new memory remap configuration */
+  SYSCFG->CFGR1 = tmpctrl;
+}
+
+/**
+  * @brief  Configure the DMA channels remapping.
+  * @param  SYSCFG_DMARemap: selects the DMA channels remap.
+  *          This parameter can be one of the following values:
+  *            @arg SYSCFG_DMARemap_TIM17: Remap TIM17 DMA requests from channel1 to channel2
+  *            @arg SYSCFG_DMARemap_TIM16: Remap TIM16 DMA requests from channel3 to channel4
+  *            @arg SYSCFG_DMARemap_USART1Rx: Remap USART1 Rx DMA requests from channel3 to channel5
+  *            @arg SYSCFG_DMARemap_USART1Tx: Remap USART1 Tx DMA requests from channel2 to channel4
+  *            @arg SYSCFG_DMARemap_ADC1: Remap ADC1 DMA requests from channel1 to channel2
+  * @param  NewState: new state of the DMA channel remapping. 
+  *         This parameter can be: ENABLE or DISABLE.
+  * @note   When enabled, DMA channel of the selected peripheral is remapped
+  * @note   When disabled, Default DMA channel is mapped to the selected peripheral
+  * @note   By default TIM17 DMA requests is mapped to channel 1, 
+  *         use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable) to remap
+  *         TIM17 DMA requests to channel 2 and use
+  *         SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable) to map
+  *         TIM17 DMA requests to channel 1 (default mapping)
+  * @note   This function is only used for STM32F030, STM32F031, STM32F042, STM32F072 and STM32F051 devices.   
+  * @retval None
+  */
+void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Remap the DMA channel */
+    SYSCFG->CFGR1 |= (uint32_t)SYSCFG_DMARemap;
+  }
+  else
+  {
+    /* use the default DMA channel mapping */
+    SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_DMARemap);
+  }
+}
+
+/**
+  * @brief  Configure the I2C fast mode plus driving capability.
+  * @param  SYSCFG_I2CFastModePlus: selects the pin.
+  *          This parameter can be one of the following values:
+  *            @arg SYSCFG_I2CFastModePlus_PB6: Configure fast mode plus driving capability for PB6
+  *            @arg SYSCFG_I2CFastModePlus_PB7: Configure fast mode plus driving capability for PB7
+  *            @arg SYSCFG_I2CFastModePlus_PB8: Configure fast mode plus driving capability for PB8
+  *            @arg SYSCFG_I2CFastModePlus_PB9: Configure fast mode plus driving capability for PB9
+  *            @arg SYSCFG_I2CFastModePlus_PA9: Configure fast mode plus driving capability for PA9 (only for STM32F031 and STM32F030 devices)
+  *            @arg SYSCFG_I2CFastModePlus_PA10: Configure fast mode plus driving capability for PA10 (only for STM32F031 and STM32F030 devices)
+  *            @arg SYSCFG_I2CFastModePlus_I2C1: Configure fast mode plus driving capability for PB10, PB11, PF6 and PF7(only for STM32F031 and STM32F030 devices)
+  *            @arg SYSCFG_I2CFastModePlus_I2C2: Configure fast mode plus driving capability for I2C2 pins, available only for STM32F072 devices
+  *                
+  * @param  NewState: new state of the DMA channel remapping. 
+  *         This parameter can be:  ENABLE or DISABLE.
+  * @note   ENABLE: Enable fast mode plus driving capability for selected I2C pin
+  * @note   DISABLE: Disable fast mode plus driving capability for selected I2C pin
+  * @note  For I2C1, fast mode plus driving capability can be enabled on all selected
+  *        I2C1 pins using SYSCFG_I2CFastModePlus_I2C1 parameter or independently
+  *        on each one of the following pins PB6, PB7, PB8 and PB9.
+  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+  *        can be enabled only by using SYSCFG_I2CFastModePlus_I2C1 parameter.
+  * @note  For all I2C2 pins fast mode plus driving capability can be enabled
+  *        only by using SYSCFG_I2CFastModePlus_I2C2 parameter.
+  * @retval None
+  */
+void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_I2C_FMP(SYSCFG_I2CFastModePlus));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable fast mode plus driving capability for selected pin */
+    SYSCFG->CFGR1 |= (uint32_t)SYSCFG_I2CFastModePlus;
+  }
+  else
+  {
+    /* Disable fast mode plus driving capability for selected pin */
+    SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_I2CFastModePlus);
+  }
+}
+
+/** @brief  select the modulation envelope source 
+  * @param SYSCFG_IRDAEnv: select the envelope source. 
+  *        This parameter can be a value 
+  *            @arg SYSCFG_IRDA_ENV_SEL_TIM16
+  *            @arg SYSCFG_IRDA_ENV_SEL_USART1
+  *            @arg SYSCFG_IRDA_ENV_SEL_USART4
+  * @retval None      
+  */
+void SYSCFG_IRDAEnvSelection(uint32_t SYSCFG_IRDAEnv)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_IRDA_ENV(SYSCFG_IRDAEnv));
+  
+  SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_IRDA_ENV_SEL);
+  SYSCFG->CFGR1 |= (SYSCFG_IRDAEnv);
+}
+
+/**
+  * @brief  Selects the GPIO pin used as EXTI Line.
+  * @param  EXTI_PortSourceGPIOx: selects the GPIO port to be used as source 
+  *                               for EXTI lines where x can be (A, B, C, D, E or F).
+  * @note   GPIOE is available only for STM32F072.
+  * @note   GPIOD is not available for STM32F031.    
+  * @param  EXTI_PinSourcex: specifies the EXTI line to be configured.
+  * @note   This parameter can be EXTI_PinSourcex where x can be:
+  *         For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF.
+  *         For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
+  *         For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF.
+  * @retval None
+  */
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
+{
+  uint32_t tmp = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
+  assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
+  
+  tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
+  SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
+  SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
+}
+
+/**
+  * @brief  check ISR wrapper: Allow to determine interrupt source per line .
+  * @param  IT_Source: specifies the interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg ITLINE_EWDG                       EWDG has expired 
+  *            @arg ITLINE_PVDOUT                     Power voltage detection Interrupt 
+  *            @arg ITLINE_VDDIO2                     VDDIO2 Interrupt
+  *            @arg ITLINE_RTC_WAKEUP                 RTC WAKEUP -> exti[20] Interrupt 
+  *            @arg ITLINE_RTC_TSTAMP                 RTC Time Stamp -> exti[19] interrupt 
+  *            @arg ITLINE_RTC_ALRA                   RTC Alarm -> exti[17] interrupt
+  *            @arg ITLINE_FLASH_ITF                  Flash ITF Interrupt
+  *            @arg ITLINE_CRS                        CRS Interrupt 
+  *            @arg ITLINE_CLK_CTRL                   CLK Control Interrupt 
+  *            @arg ITLINE_EXTI0                      External Interrupt 0 
+  *            @arg ITLINE_EXTI1                      External Interrupt 1 
+  *            @arg ITLINE_EXTI2                      External Interrupt 2 
+  *            @arg ITLINE_EXTI3                      External Interrupt 3 
+  *            @arg ITLINE_EXTI4                      External Interrupt 4 
+  *            @arg ITLINE_EXTI5                      External Interrupt 5 
+  *            @arg ITLINE_EXTI6                      External Interrupt 6 
+  *            @arg ITLINE_EXTI7                      External Interrupt 7 
+  *            @arg ITLINE_EXTI8                      External Interrupt 8 
+  *            @arg ITLINE_EXTI9                      External Interrupt 9 
+  *            @arg ITLINE_EXTI10                     External Interrupt 10 
+  *            @arg ITLINE_EXTI11                     External Interrupt 11 
+  *            @arg ITLINE_EXTI12                     External Interrupt 12 
+  *            @arg ITLINE_EXTI13                     External Interrupt 13 
+  *            @arg ITLINE_EXTI14                     External Interrupt 14 
+  *            @arg ITLINE_EXTI15                     External Interrupt 15 
+  *            @arg ITLINE_TSC_EOA                    Touch control EOA Interrupt 
+  *            @arg ITLINE_TSC_MCE                    Touch control MCE Interrupt 
+  *            @arg ITLINE_DMA1_CH1                   DMA1 Channel 1 Interrupt 
+  *            @arg ITLINE_DMA1_CH2                   DMA1 Channel 2 Interrupt 
+  *            @arg ITLINE_DMA1_CH3                   DMA1 Channel 3 Interrupt 
+  *            @arg ITLINE_DMA2_CH1                   DMA2 Channel 1 Interrupt 
+  *            @arg ITLINE_DMA2_CH2                   DMA2 Channel 2 Interrupt 
+  *            @arg ITLINE_DMA1_CH4                   DMA1 Channel 4 Interrupt  
+  *            @arg ITLINE_DMA1_CH5                   DMA1 Channel 5 Interrupt 
+  *            @arg ITLINE_DMA1_CH6                   DMA1 Channel 6 Interrupt 
+  *            @arg ITLINE_DMA1_CH7                   DMA1 Channel 7 Interrupt 
+  *            @arg ITLINE_DMA2_CH3                   DMA2 Channel 3 Interrupt 
+  *            @arg ITLINE_DMA2_CH4                   DMA2 Channel 4 Interrupt 
+  *            @arg ITLINE_DMA2_CH5                   DMA2 Channel 5 Interrupt 
+  *            @arg ITLINE_ADC                        ADC Interrupt 
+  *            @arg ITLINE_COMP1                      COMP1 Interrupt -> exti[21] 
+  *            @arg ITLINE_COMP2                      COMP2 Interrupt -> exti[21] 
+  *            @arg ITLINE_TIM1_BRK                   TIM1 BRK Interrupt 
+  *            @arg ITLINE_TIM1_UPD                   TIM1 UPD Interrupt 
+  *            @arg ITLINE_TIM1_TRG                   TIM1 TRG Interrupt 
+  *            @arg ITLINE_TIM1_CCU                   TIM1 CCU Interrupt 
+  *            @arg ITLINE_TIM1_CC                    TIM1 CC Interrupt 
+  *            @arg ITLINE_TIM2                       TIM2 Interrupt 
+  *            @arg ITLINE_TIM3                       TIM3 Interrupt 
+  *            @arg ITLINE_DAC                        DAC Interrupt 
+  *            @arg ITLINE_TIM6                       TIM6 Interrupt 
+  *            @arg ITLINE_TIM7                       TIM7 Interrupt 
+  *            @arg ITLINE_TIM14                      TIM14 Interrupt 
+  *            @arg ITLINE_TIM15                      TIM15 Interrupt 
+  *            @arg ITLINE_TIM16                      TIM16 Interrupt 
+  *            @arg ITLINE_TIM17                      TIM17 Interrupt 
+  *            @arg ITLINE_I2C1                       I2C1 Interrupt -> exti[23] 
+  *            @arg ITLINE_I2C2                       I2C2 Interrupt 
+  *            @arg ITLINE_SPI1                       I2C1 Interrupt -> exti[23] 
+  *            @arg ITLINE_SPI2                       SPI1 Interrupt 
+  *            @arg ITLINE_USART1                     USART1 GLB Interrupt -> exti[25] 
+  *            @arg ITLINE_USART2                     USART2 GLB Interrupt -> exti[26] 
+  *            @arg ITLINE_USART3                     USART3 Interrupt 
+  *            @arg ITLINE_USART4                     USART4 Interrupt 
+  *            @arg ITLINE_USART5                     USART5 Interrupt 
+  *            @arg ITLINE_USART6                     USART6 Interrupt 
+  *            @arg ITLINE_USART7                     USART7 Interrupt 
+  *            @arg ITLINE_USART8                     USART8 Interrupt 
+  *            @arg ITLINE_CAN                        CAN Interrupt 
+  *            @arg ITLINE_CEC                        CEC Interrupt 
+  * @retval The new state of IT_LINE_SR.
+  */
+uint32_t  SYSCFG_GetPendingIT(uint32_t ITSourceLine)
+{
+   assert_param(IS_SYSCFG_ITLINE(ITSourceLine));
+   return(SYSCFG->IT_LINE_SR[(ITSourceLine >> 0x18)] & (ITSourceLine & 0x00FFFFFF));
+}
+
+/**
+  * @brief  Connect the selected parameter to the break input of TIM1.
+  * @note   The selected configuration is locked and can be unlocked by system reset
+  * @param  SYSCFG_Break: selects the configuration to be connected to break
+  *         input of TIM1
+  *          This parameter can be any combination of the following values:
+  *            @arg SYSCFG_Break_PVD: Connects the PVD event to the Break Input of TIM1,, not available for  STM32F030 devices.
+  *            @arg SYSCFG_Break_SRAMParity: Connects the SRAM_PARITY error signal to the Break Input of TIM1 .
+  *            @arg SYSCFG_Break_Lockup: Connects Lockup output of CortexM0 to the break input of TIM1.
+  * @retval None
+  */
+void SYSCFG_BreakConfig(uint32_t SYSCFG_Break)
+{
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break));
+
+  SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break;
+}
+
+/**
+  * @brief  Checks whether the specified SYSCFG flag is set or not.
+  * @param  SYSCFG_Flag: specifies the SYSCFG flag to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SYSCFG_FLAG_PE: SRAM parity error flag.
+  * @retval The new state of SYSCFG_Flag (SET or RESET).
+  */
+FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
+
+  /* Check the status of the specified SPI flag */
+  if ((SYSCFG->CFGR2 & SYSCFG_CFGR2_SRAM_PE) != (uint32_t)RESET)
+  {
+    /* SYSCFG_Flag is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* SYSCFG_Flag is reset */
+    bitstatus = RESET;
+  }
+  /* Return the SYSCFG_Flag status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clear the selected SYSCFG flag.
+  * @param  SYSCFG_Flag: selects the flag to be cleared.
+  *          This parameter can be any combination of the following values:
+  *            @arg SYSCFG_FLAG_PE: SRAM parity error flag.
+  * @retval None
+  */
+void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag)
+{
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
+
+  SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Flag;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_tim.c b/system/src/stm32f0-stdperiph/stm32f0xx_tim.c

new file mode 100644 (file)

index 0000000..ddaab12
--- /dev/null
+++ b/system/src/stm32f0-stdperiph/stm32f0xx_tim.c
@@ -0,0 +1,3349 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_tim.c
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the TIM peripheral:
+  *            + TimeBase management
+  *            + Output Compare management
+  *            + Input Capture management
+  *            + Interrupts, DMA and flags management
+  *            + Clocks management
+  *            + Synchronization management
+  *            + Specific interface management
+  *            + Specific remapping management      
+  *              
+  *  @verbatim
+  
+ ===============================================================================
+                    ##### How to use this driver #####
+ ===============================================================================
+    [..] This driver provides functions to configure and program the TIM 
+         of all STM32F0xx devices These functions are split in 8 groups: 
+         (#) TIM TimeBase management: this group includes all needed functions 
+             to configure the TM Timebase unit:
+             (++) Set/Get Prescaler.
+             (++) Set/Get Autoreload.
+             (++) Counter modes configuration.
+             (++) Set Clock division.
+             (++) Select the One Pulse mode.
+             (++) Update Request Configuration.
+             (++) Update Disable Configuration.
+             (++) Auto-Preload Configuration.
+             (++) Enable/Disable the counter.
+  
+         (#) TIM Output Compare management: this group includes all needed 
+             functions to configure the Capture/Compare unit used in Output 
+             compare mode: 
+             (++) Configure each channel, independently, in Output Compare mode.
+             (++) Select the output compare modes.
+             (++) Select the Polarities of each channel.
+             (++) Set/Get the Capture/Compare register values.
+             (++) Select the Output Compare Fast mode. 
+             (++) Select the Output Compare Forced mode.  
+             (++) Output Compare-Preload Configuration. 
+             (++) Clear Output Compare Reference.
+             (++) Select the OCREF Clear signal.
+             (++) Enable/Disable the Capture/Compare Channels.    
+  
+         (#) TIM Input Capture management: this group includes all needed 
+             functions to configure the Capture/Compare unit used in 
+             Input Capture mode:
+             (++) Configure each channel in input capture mode.
+             (++) Configure Channel1/2 in PWM Input mode.
+             (++) Set the Input Capture Prescaler.
+             (++) Get the Capture/Compare values.  
+             
+        (#) Advanced-control timers (TIM1) specific features
+            (++) Configures the Break input, dead time, Lock level, the OSSI,
+                 the OSSR State and the AOE(automatic output enable)
+            (++) Enable/Disable the TIM peripheral Main Outputs
+            (++) Select the Commutation event
+            (++) Set/Reset the Capture Compare Preload Control bit     
+  
+         (#) TIM interrupts, DMA and flags management.
+             (++) Enable/Disable interrupt sources.
+             (++) Get flags status.
+             (++) Clear flags/ Pending bits.
+             (++) Enable/Disable DMA requests. 
+             (++) Configure DMA burst mode.
+             (++) Select CaptureCompare DMA request.  
+  
+         (#) TIM clocks management: this group includes all needed functions 
+             to configure the clock controller unit:
+             (++) Select internal/External clock.
+             (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx.
+  
+         (#) TIM synchronization management: this group includes all needed. 
+             functions to configure the Synchronization unit:
+             (++) Select Input Trigger.  
+             (++) Select Output Trigger.  
+             (++) Select Master Slave Mode. 
+             (++) ETR Configuration when used as external trigger.   
+  
+         (#) TIM specific interface management, this group includes all 
+             needed functions to use the specific TIM interface:
+             (++) Encoder Interface Configuration.
+             (++) Select Hall Sensor.   
+  
+         (#) TIM specific remapping management includes the Remapping 
+             configuration of specific timers
+  
+@endverbatim
+  *    
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_tim.h"
+#include "stm32f0xx_rcc.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup TIM 
+  * @brief TIM driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* ---------------------- TIM registers bit mask ------------------------ */
+#define SMCR_ETR_MASK               ((uint16_t)0x00FF) 
+#define CCMR_OFFSET                 ((uint16_t)0x0018)
+#define CCER_CCE_SET                ((uint16_t)0x0001)
+#define CCER_CCNE_SET               ((uint16_t)0x0004) 
+  
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup TIM_Private_Functions
+  * @{
+  */
+
+/** @defgroup TIM_Group1 TimeBase management functions
+ *  @brief   TimeBase management functions 
+ *
+@verbatim
+ ===============================================================================
+                 ##### TimeBase management functions #####
+ ===============================================================================
+  
+        *** TIM Driver: how to use it in Timing(Time base) Mode ***
+ ===============================================================================
+    [..] To use the Timer in Timing(Time base) mode, the following steps are 
+         mandatory:
+         (#) Enable TIM clock using 
+             RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function.
+         (#) Fill the TIM_TimeBaseInitStruct with the desired parameters.
+         (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure 
+             the Time Base unit with the corresponding configuration.
+         (#) Enable the NVIC if you need to generate the update interrupt. 
+         (#) Enable the corresponding interrupt using the function 
+             TIM_ITConfig(TIMx, TIM_IT_Update). 
+         (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
+    [..]
+        (@) All other functions can be used seperatly to modify, if needed,
+            a specific feature of the Timer. 
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the TIMx peripheral registers to their default reset values.
+  * @param  TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM peripheral.
+  * @note   TIM7 is applicable only for STM32F072 devices
+  * @note   TIM6 is not applivable for STM32F031 devices.
+  * @note   TIM2 is not applicable for STM32F030 devices.    
+  * @retval None
+  *   
+  */
+void TIM_DeInit(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
+
+  if (TIMx == TIM1)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);  
+  }     
+  else if (TIMx == TIM2)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
+  }
+  else if (TIMx == TIM3)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
+  }
+  else if (TIMx == TIM6)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
+  } 
+  else if (TIMx == TIM7)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
+  }
+  else if (TIMx == TIM14) 
+  {       
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE);  
+  }        
+  else if (TIMx == TIM15)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);
+  } 
+  else if (TIMx == TIM16)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);
+  } 
+  else
+  {
+    if (TIMx == TIM17)
+    {
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE);
+    }  
+  }
+     
+}
+
+/**
+  * @brief  Initializes the TIMx Time Base Unit peripheral according to 
+  *         the specified parameters in the TIM_TimeBaseInitStruct.
+  * @param  TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM 
+  *         peripheral.
+  * @note   TIM7 is applicable only for STM32F072 devices
+  * @note   TIM6 is not applivable for STM32F031 devices.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
+  *         structure that contains the configuration information for
+  *         the specified TIM peripheral.
+  * @retval None
+  */
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
+{
+  uint16_t tmpcr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
+  assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
+  assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
+
+  tmpcr1 = TIMx->CR1;  
+
+  if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3))
+  {
+    /* Select the Counter Mode */
+    tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
+    tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
+  }
+ 
+  if(TIMx != TIM6)
+  {
+    /* Set the clock division */
+    tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));
+    tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
+  }
+
+  TIMx->CR1 = tmpcr1;
+
+  /* Set the Autoreload value */
+  TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
+ 
+  /* Set the Prescaler value */
+  TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
+    
+  if ((TIMx == TIM1) || (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17))  
+  {
+    /* Set the Repetition Counter value */
+    TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
+  }
+
+  /* Generate an update event to reload the Prescaler and the Repetition counter
+     values immediately */
+  TIMx->EGR = TIM_PSCReloadMode_Immediate;           
+}
+
+/**
+  * @brief  Fills each TIM_TimeBaseInitStruct member with its default value.
+  * @param  TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure
+  *         which will be initialized.
+  * @retval None
+  */
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
+{
+  /* Set the default configuration */
+  TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF;
+  TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
+  TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
+  TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
+  TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
+}
+
+/**
+  * @brief  Configures the TIMx Prescaler.
+  * @param  TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM peripheral.
+  * @note   TIM7 is applicable only for STM32F072 devices
+  * @note   TIM6 is not applivable for STM32F031 devices.
+  * @note   TIM2 is not applicable for STM32F030 devices.    
+  * @param  Prescaler: specifies the Prescaler Register value
+  * @param  TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
+  *          This parameter can be one of the following values:
+  *            @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
+  *            @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
+  * @retval None
+  */
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
+  
+  /* Set the Prescaler value */
+  TIMx->PSC = Prescaler;
+  /* Set or reset the UG Bit */
+  TIMx->EGR = TIM_PSCReloadMode;
+}
+
+/**
+  * @brief  Specifies the TIMx Counter Mode to be used.
+  * @param  TIMx: where x can be 1, 2, or 3 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_CounterMode: specifies the Counter Mode to be used
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CounterMode_Up: TIM Up Counting Mode
+  *            @arg TIM_CounterMode_Down: TIM Down Counting Mode
+  *            @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
+  *            @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
+  *            @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
+  * @retval None
+  */
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
+{
+  uint16_t tmpcr1 = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
+  
+  tmpcr1 = TIMx->CR1;
+  /* Reset the CMS and DIR Bits */
+  tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
+  /* Set the Counter Mode */
+  tmpcr1 |= TIM_CounterMode;
+  /* Write to TIMx CR1 register */
+  TIMx->CR1 = tmpcr1;
+}
+
+/**
+  * @brief  Sets the TIMx Counter Register value
+  * @param  TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM 
+  *          peripheral.
+  * @note   TIM7 is applicable only for STM32F072 devices
+  * @note   TIM6 is not applivable for STM32F031 devices.
+  * @note   TIM2 is not applicable for STM32F030 devices.    
+  * @param  Counter: specifies the Counter register new value.
+  * @retval None
+  */
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)
+{
+  /* Check the parameters */
+   assert_param(IS_TIM_ALL_PERIPH(TIMx));
+   
+  /* Set the Counter Register value */
+  TIMx->CNT = Counter;
+}
+
+/**
+  * @brief  Sets the TIMx Autoreload Register value
+  * @param  TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM peripheral.
+  * @note   TIM7 is applicable only for STM32F072 devices
+  * @note   TIM6 is not applivable for STM32F031 devices.
+  * @note   TIM2 is not applicable for STM32F030 devices.    
+  * @param  Autoreload: specifies the Autoreload register new value.
+  * @retval None
+  */
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  
+  /* Set the Autoreload Register value */
+  TIMx->ARR = Autoreload;
+}
+
+/**
+  * @brief  Gets the TIMx Counter value.
+  * @param  TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM 
+  *         peripheral.
+  * @note   TIM7 is applicable only for STM32F072 devices
+  * @note   TIM6 is not applivable for STM32F031 devices.
+  * @note   TIM2 is not applicable for STM32F030 devices.    
+  * @retval Counter Register value.
+  */
+uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  
+  /* Get the Counter Register value */
+  return TIMx->CNT;
+}
+
+/**
+  * @brief  Gets the TIMx Prescaler value.
+  * @param  TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM 
+  *         peripheral.
+  * @note   TIM7 is applicable only for STM32F072 devices
+  * @note   TIM6 is not applivable for STM32F031 devices.
+  * @note   TIM2 is not applicable for STM32F030 devices.    
+  * @retval Prescaler Register value.
+  */
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  
+  /* Get the Prescaler Register value */
+  return TIMx->PSC;
+}
+
+/**
+  * @brief  Enables or Disables the TIMx Update event.
+  * @param  TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM 
+  *         peripheral.
+  * @note   TIM7 is applicable only for STM32F072 devices
+  * @note   TIM6 is not applivable for STM32F031 devices.
+  * @note   TIM2 is not applicable for STM32F030 devices.    
+  * @param  NewState: new state of the TIMx UDIS bit
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Set the Update Disable Bit */
+    TIMx->CR1 |= TIM_CR1_UDIS;
+  }
+  else
+  {
+    /* Reset the Update Disable Bit */
+    TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);
+  }
+}
+
+/**
+  * @brief  Configures the TIMx Update Request Interrupt source.
+  * @param  TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM 
+  *         peripheral.
+  * @note   TIM7 is applicable only for STM32F072 devices
+  * @note   TIM6 is not applivable for STM32F031 devices.
+  * @note   TIM2 is not applicable for STM32F030 devices.    
+  * @param  TIM_UpdateSource: specifies the Update source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_UpdateSource_Regular: Source of update is the counter
+  *                 overflow/underflow or the setting of UG bit, or an update
+  *                 generation through the slave mode controller.
+  *            @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
+  * @retval None
+  */
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
+  
+  if (TIM_UpdateSource != TIM_UpdateSource_Global)
+  {
+    /* Set the URS Bit */
+    TIMx->CR1 |= TIM_CR1_URS;
+  }
+  else
+  {
+    /* Reset the URS Bit */
+    TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);
+  }
+}
+
+/**
+  * @brief  Enables or disables TIMx peripheral Preload register on ARR.
+  * @param  TIMx: where x can be  1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM 
+  *         peripheral.
+  * @note   TIM7 is applicable only for STM32F072 devices
+  * @note   TIM6 is not applivable for STM32F031 devices.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  NewState: new state of the TIMx peripheral Preload register
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Set the ARR Preload Bit */
+    TIMx->CR1 |= TIM_CR1_ARPE;
+  }
+  else
+  {
+    /* Reset the ARR Preload Bit */
+    TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);
+  }
+}
+
+/**
+  * @brief  Selects the TIMx's One Pulse Mode.
+  * @param  TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM 
+  *         peripheral.
+  * @note   TIM7 is applicable only for STM32F072 devices
+  * @note   TIM6 is not applivable for STM32F031 devices.
+  * @note   TIM2 is not applicable for STM32F030 devices.    
+  * @param  TIM_OPMode: specifies the OPM Mode to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OPMode_Single
+  *            @arg TIM_OPMode_Repetitive
+  * @retval None
+  */
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
+  
+  /* Reset the OPM Bit */
+  TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);
+  /* Configure the OPM Mode */
+  TIMx->CR1 |= TIM_OPMode;
+}
+
+/**
+  * @brief  Sets the TIMx Clock Division value.
+  * @param  TIMx: where x can be  1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_CKD: specifies the clock division value.
+  *          This parameter can be one of the following value:
+  *            @arg TIM_CKD_DIV1: TDTS = Tck_tim
+  *            @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
+  *            @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
+  * @retval None
+  */
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_TIM_CKD_DIV(TIM_CKD));
+  
+  /* Reset the CKD Bits */
+  TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);
+  /* Set the CKD value */
+  TIMx->CR1 |= TIM_CKD;
+}
+
+/**
+  * @brief  Enables or disables the specified TIM peripheral.
+  * @param  TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17to select the TIMx
+  *         peripheral.
+  * @note   TIM7 is applicable only for STM32F072 devices
+  * @note   TIM6 is not applivable for STM32F031 devices.
+  * @note   TIM2 is not applicable for STM32F030 devices.    
+  * @param  NewState: new state of the TIMx peripheral.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the TIM Counter */
+    TIMx->CR1 |= TIM_CR1_CEN;
+  }
+  else
+  {
+    /* Disable the TIM Counter */
+    TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group2 Advanced-control timers (TIM1) specific features
+ *  @brief   Advanced-control timers (TIM1) specific features
+ *
+@verbatim   
+ ===============================================================================
+      ##### Advanced-control timers (TIM1) specific features #####
+ ===============================================================================  
+  
+       ===================================================================      
+              *** TIM Driver: how to use the Break feature ***
+       =================================================================== 
+       [..] After configuring the Timer channel(s) in the appropriate Output Compare mode: 
+                         
+           (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer
+               Break Polarity, dead time, Lock level, the OSSI/OSSR State and the 
+               AOE(automatic output enable).
+               
+           (#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer
+          
+           (#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) 
+          
+           (#) Once the break even occurs, the Timer's output signals are put in reset
+               state or in a known state (according to the configuration made in
+               TIM_BDTRConfig() function).
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Configures the: Break feature, dead time, Lock level, OSSI/OSSR State
+  *         and the AOE(automatic output enable).
+  * @param  TIMx: where x can be  1, 15, 16 or 17 to select the TIM 
+  * @param  TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
+  *         contains the BDTR Register configuration  information for the TIM peripheral.
+  * @retval None
+  */
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
+  assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
+  assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
+  assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
+  assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
+  assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
+  /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
+     the OSSI State, the dead time value and the Automatic Output Enable Bit */
+  TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
+             TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
+             TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
+             TIM_BDTRInitStruct->TIM_AutomaticOutput;
+}
+
+/**
+  * @brief  Fills each TIM_BDTRInitStruct member with its default value.
+  * @param  TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
+  *         will be initialized.
+  * @retval None
+  */
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
+{
+  /* Set the default configuration */
+  TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
+  TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
+  TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
+  TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
+  TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
+  TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
+  TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
+}
+
+/**
+  * @brief  Enables or disables the TIM peripheral Main Outputs.
+  * @param  TIMx: where x can be 1, 15, 16 or 17 to select the TIMx peripheral.
+  * @param  NewState: new state of the TIM peripheral Main Outputs.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the TIM Main Output */
+    TIMx->BDTR |= TIM_BDTR_MOE;
+  }
+  else
+  {
+    /* Disable the TIM Main Output */
+    TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE));
+  }  
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group3 Output Compare management functions
+ *  @brief    Output Compare management functions 
+ *
+@verbatim
+ ===============================================================================
+                ##### Output Compare management functions #####
+ ===============================================================================
+        *** TIM Driver: how to use it in Output Compare Mode ***
+ ===============================================================================
+    [..] To use the Timer in Output Compare mode, the following steps are mandatory:
+         (#) Enable TIM clock using 
+             RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function.
+         (#) Configure the TIM pins by configuring the corresponding GPIO pins
+         (#) Configure the Time base unit as described in the first part of this 
+             driver, if needed, else the Timer will run with the default 
+             configuration:
+             (++) Autoreload value = 0xFFFF.
+             (++) Prescaler value = 0x0000.
+             (++) Counter mode = Up counting.
+             (++) Clock Division = TIM_CKD_DIV1.
+         (#) Fill the TIM_OCInitStruct with the desired parameters including:
+             (++) The TIM Output Compare mode: TIM_OCMode.
+             (++) TIM Output State: TIM_OutputState.
+             (++) TIM Pulse value: TIM_Pulse.
+             (++) TIM Output Compare Polarity : TIM_OCPolarity.
+         (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired 
+             channel with the corresponding configuration.
+         (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
+    [..]
+        (@) All other functions can be used separately to modify, if needed,
+          a specific feature of the Timer.
+        (@) In case of PWM mode, this function is mandatory:
+            TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE).
+        (@) If the corresponding interrupt or DMA request are needed, the user should:
+            (#@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests).
+            (#@) Enable the corresponding interrupt (or DMA request) using the function
+                 TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the TIMx Channel1 according to the specified
+  *         parameters in the TIM_OCInitStruct.
+  * @param  TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+  *         that contains the configuration information for the specified TIM 
+  *         peripheral.
+  * @retval None
+  */
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+   
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
+ /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+    
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));
+  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+  
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));
+  /* Set the Output Compare Polarity */
+  tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
+  
+  /* Set the Output State */
+  tmpccer |= TIM_OCInitStruct->TIM_OutputState;
+    
+  if((TIMx == TIM1) || (TIMx == TIM15) || (TIMx == TIM16) || (TIMx == TIM17))
+  {
+    assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+    assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+    assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+    
+    /* Reset the Output N Polarity level */
+    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP));
+    /* Set the Output N Polarity */
+    tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
+    
+    /* Reset the Output N State */
+    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE));    
+    /* Set the Output N State */
+    tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
+    
+    /* Reset the Ouput Compare and Output Compare N IDLE State */
+    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));
+    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));
+    
+    /* Set the Output Idle state */
+    tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
+    /* Set the Output N Idle state */
+    tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+  
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; 
+ 
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Initializes the TIMx Channel2 according to the specified
+  *         parameters in the TIM_OCInitStruct.
+  * @param  TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+  *         that contains the configuration information for the specified TIM 
+  *         peripheral.
+  * @retval None
+  */
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+   
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 
+  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
+   /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));
+  
+  /* Get the TIMx CCER register value */  
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+    
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));
+  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S));
+  
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+  
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));
+  /* Set the Output Compare Polarity */
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
+  
+  /* Set the Output State */
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
+    
+  if((TIMx == TIM1) || (TIMx == TIM15))
+  {
+    /* Check the parameters */
+    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+    
+    /* Reset the Ouput Compare State */
+    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2));
+    
+    /* Set the Output Idle state */
+    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
+    
+    if (TIMx == TIM1)
+    {    
+      /* Check the parameters */
+      assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+      assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+      assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+      
+      /* Reset the Output N Polarity level */
+      tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP));
+      /* Set the Output N Polarity */
+      tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
+      
+      /* Reset the Output N State */
+      tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE));    
+      /* Set the Output N State */
+      tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
+      
+      /* Reset the Output Compare N IDLE State */
+      tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N));
+      
+      /* Set the Output N Idle state */
+      tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
+    }
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+  
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
+  
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Initializes the TIMx Channel3 according to the specified
+  *         parameters in the TIM_OCInitStruct.
+  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+  *         that contains the configuration information for the specified TIM 
+  *         peripheral.
+  * @retval None
+  */
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+   
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
+  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));
+  
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+    
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));
+  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S));  
+  /* Select the Output Compare Mode */
+  tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+  
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));
+  /* Set the Output Compare Polarity */
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
+  
+  /* Set the Output State */
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
+    
+  if(TIMx == TIM1)
+  {
+    assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+    assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+    assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+    
+    /* Reset the Output N Polarity level */
+    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP));
+    /* Set the Output N Polarity */
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
+    /* Reset the Output N State */
+    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE));
+    
+    /* Set the Output N State */
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
+    /* Reset the Ouput Compare and Output Compare N IDLE State */
+    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));
+    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));
+    /* Set the Output Idle state */
+    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+  
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
+  
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Initializes the TIMx Channel4 according to the specified
+  *         parameters in the TIM_OCInitStruct.
+  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+  *         that contains the configuration information for the specified TIM 
+  *         peripheral.
+  * @retval None
+  */
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+   
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
+  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
+  /* Disable the Channel 2: Reset the CC4E Bit */
+  TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));
+  
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+    
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));
+  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S));
+  
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+  
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));
+  /* Set the Output Compare Polarity */
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
+  
+  /* Set the Output State */
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
+    
+  if(TIMx == TIM1)
+  {
+    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+    /* Reset the Ouput Compare IDLE State */
+    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4));
+    /* Set the Output Idle state */
+    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+  
+  /* Write to TIMx CCMR2 */  
+  TIMx->CCMR2 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
+  
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Fills each TIM_OCInitStruct member with its default value.
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+  /* Set the default configuration */
+  TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
+  TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
+  TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
+  TIM_OCInitStruct->TIM_Pulse = 0x0000000;
+  TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
+  TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
+  TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
+  TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
+}
+
+/**
+  * @brief  Selects the TIM Output Compare Mode.
+  * @note   This function disables the selected channel before changing the Output
+  *         Compare Mode.
+  *         User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
+  * @param  TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_Channel: specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_Channel_1: TIM Channel 1
+  *            @arg TIM_Channel_2: TIM Channel 2
+  *            @arg TIM_Channel_3: TIM Channel 3
+  *            @arg TIM_Channel_4: TIM Channel 4
+  * @param  TIM_OCMode: specifies the TIM Output Compare Mode.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCMode_Timing
+  *            @arg TIM_OCMode_Active
+  *            @arg TIM_OCMode_Toggle
+  *            @arg TIM_OCMode_PWM1
+  *            @arg TIM_OCMode_PWM2
+  *            @arg TIM_ForcedAction_Active
+  *            @arg TIM_ForcedAction_InActive
+  * @retval None
+  */
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
+{
+  uint32_t tmp = 0;
+  uint16_t tmp1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));  
+  assert_param(IS_TIM_OCM(TIM_OCMode));
+  
+  tmp = (uint32_t) TIMx;
+  tmp += CCMR_OFFSET;
+
+  tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;
+
+  /* Disable the Channel: Reset the CCxE Bit */
+  TIMx->CCER &= (uint16_t) ~tmp1;
+
+  if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
+  {
+    tmp += (TIM_Channel>>1);
+
+    /* Reset the OCxM bits in the CCMRx register */
+    *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);
+   
+    /* Configure the OCxM bits in the CCMRx register */
+    *(__IO uint32_t *) tmp |= TIM_OCMode;
+  }
+  else
+  {
+    tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
+
+    /* Reset the OCxM bits in the CCMRx register */
+    *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);
+    
+    /* Configure the OCxM bits in the CCMRx register */
+    *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
+  }
+}
+
+/**
+  * @brief  Sets the TIMx Capture Compare1 Register value
+  * @param  TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  Compare1: specifies the Capture Compare1 register new value.
+  * @retval None
+  */
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  
+  /* Set the Capture Compare1 Register value */
+  TIMx->CCR1 = Compare1;
+}
+
+/**
+  * @brief  Sets the TIMx Capture Compare2 Register value
+  * @param  TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  Compare2: specifies the Capture Compare2 register new value.
+  * @retval None
+  */
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  
+  /* Set the Capture Compare2 Register value */
+  TIMx->CCR2 = Compare2;
+}
+
+/**
+  * @brief  Sets the TIMx Capture Compare3 Register value
+  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
+  * @param  Compare3: specifies the Capture Compare3 register new value.
+  * @retval None
+  */
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  
+  /* Set the Capture Compare3 Register value */
+  TIMx->CCR3 = Compare3;
+}
+
+/**
+  * @brief  Sets the TIMx Capture Compare4 Register value
+  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.    
+  * @param  Compare4: specifies the Capture Compare4 register new value.
+  * @retval None
+  */
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  
+  /* Set the Capture Compare4 Register value */
+  TIMx->CCR4 = Compare4;
+}
+
+/**
+  * @brief  Forces the TIMx output 1 waveform to active or inactive level.
+  * @param  TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ForcedAction_Active: Force active level on OC1REF
+  *            @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
+  * @retval None
+  */
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+  uint16_t tmpccmr1 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+  tmpccmr1 = TIMx->CCMR1;
+  /* Reset the OC1M Bits */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);
+  /* Configure The Forced output Mode */
+  tmpccmr1 |= TIM_ForcedAction;
+  /* Write to TIMx CCMR1 register */
+  TIMx->CCMR1 = tmpccmr1;
+}
+ 
+/**
+  * @brief  Forces the TIMx output 2 waveform to active or inactive level.
+  * @param  TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ForcedAction_Active: Force active level on OC2REF
+  *            @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
+  * @retval None
+  */
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+  uint16_t tmpccmr1 = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+  
+  tmpccmr1 = TIMx->CCMR1;
+  /* Reset the OC2M Bits */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);
+  /* Configure The Forced output Mode */
+  tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
+  /* Write to TIMx CCMR1 register */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Forces the TIMx output 3 waveform to active or inactive level.
+  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ForcedAction_Active: Force active level on OC3REF
+  *            @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
+  * @retval None
+  */
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+  uint16_t tmpccmr2 = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+  
+  tmpccmr2 = TIMx->CCMR2;
+  /* Reset the OC1M Bits */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);
+  /* Configure The Forced output Mode */
+  tmpccmr2 |= TIM_ForcedAction;
+  /* Write to TIMx CCMR2 register */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Forces the TIMx output 4 waveform to active or inactive level.
+  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ForcedAction_Active: Force active level on OC4REF
+  *            @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
+  * @retval None
+  */
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+  uint16_t tmpccmr2 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+  
+  tmpccmr2 = TIMx->CCMR2;
+  /* Reset the OC2M Bits */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);
+  /* Configure The Forced output Mode */
+  tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
+  /* Write to TIMx CCMR2 register */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
+  * @param  TIMx: where x can be 1, 2, 3 or 15 to select the TIMx peripheral
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  NewState: new state of the Capture Compare Preload Control bit
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Set the CCPC Bit */
+    TIMx->CR2 |= TIM_CR2_CCPC;
+  }
+  else
+  {
+    /* Reset the CCPC Bit */
+    TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC);
+  }
+}
+
+
+/**
+  * @brief  Enables or disables the TIMx peripheral Preload register on CCR1.
+  * @param  TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCPreload_Enable
+  *            @arg TIM_OCPreload_Disable
+  * @retval None
+  */
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+  uint16_t tmpccmr1 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+  
+  tmpccmr1 = TIMx->CCMR1;
+  /* Reset the OC1PE Bit */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);
+  /* Enable or Disable the Output Compare Preload feature */
+  tmpccmr1 |= TIM_OCPreload;
+  /* Write to TIMx CCMR1 register */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Enables or disables the TIMx peripheral Preload register on CCR2.
+  * @param  TIMx: where x can be 1, 2, 3 and 15 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCPreload_Enable
+  *            @arg TIM_OCPreload_Disable
+  * @retval None
+  */
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+  uint16_t tmpccmr1 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+  
+  tmpccmr1 = TIMx->CCMR1;
+  /* Reset the OC2PE Bit */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);
+  /* Enable or Disable the Output Compare Preload feature */
+  tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
+  /* Write to TIMx CCMR1 register */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Enables or disables the TIMx peripheral Preload register on CCR3.
+  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCPreload_Enable
+  *            @arg TIM_OCPreload_Disable
+  * @retval None
+  */
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+  uint16_t tmpccmr2 = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+  
+  tmpccmr2 = TIMx->CCMR2;
+  /* Reset the OC3PE Bit */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);
+  /* Enable or Disable the Output Compare Preload feature */
+  tmpccmr2 |= TIM_OCPreload;
+  /* Write to TIMx CCMR2 register */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Enables or disables the TIMx peripheral Preload register on CCR4.
+  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCPreload_Enable
+  *            @arg TIM_OCPreload_Disable
+  * @retval None
+  */
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+  uint16_t tmpccmr2 = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+  
+  tmpccmr2 = TIMx->CCMR2;
+  /* Reset the OC4PE Bit */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);
+  /* Enable or Disable the Output Compare Preload feature */
+  tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
+  /* Write to TIMx CCMR2 register */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Configures the TIMx Output Compare 1 Fast feature.
+  * @param  TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.
+  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCFast_Enable: TIM output compare fast enable
+  *            @arg TIM_OCFast_Disable: TIM output compare fast disable
+  * @retval None
+  */
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+  uint16_t tmpccmr1 = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+  
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = TIMx->CCMR1;
+  /* Reset the OC1FE Bit */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);
+  /* Enable or Disable the Output Compare Fast Bit */
+  tmpccmr1 |= TIM_OCFast;
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Configures the TIMx Output Compare 2 Fast feature.
+  * @param  TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCFast_Enable: TIM output compare fast enable
+  *            @arg TIM_OCFast_Disable: TIM output compare fast disable
+  * @retval None
+  */
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+  uint16_t tmpccmr1 = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+  
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = TIMx->CCMR1;
+  /* Reset the OC2FE Bit */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);
+  /* Enable or Disable the Output Compare Fast Bit */
+  tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Configures the TIMx Output Compare 3 Fast feature.
+  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCFast_Enable: TIM output compare fast enable
+  *            @arg TIM_OCFast_Disable: TIM output compare fast disable
+  * @retval None
+  */
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+  uint16_t tmpccmr2 = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+  
+  /* Get the TIMx CCMR2 register value */
+  tmpccmr2 = TIMx->CCMR2;
+  /* Reset the OC3FE Bit */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);
+  /* Enable or Disable the Output Compare Fast Bit */
+  tmpccmr2 |= TIM_OCFast;
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Configures the TIMx Output Compare 4 Fast feature.
+  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCFast_Enable: TIM output compare fast enable
+  *            @arg TIM_OCFast_Disable: TIM output compare fast disable
+  * @retval None
+  */
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+  uint16_t tmpccmr2 = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+  
+  /* Get the TIMx CCMR2 register value */
+  tmpccmr2 = TIMx->CCMR2;
+  /* Reset the OC4FE Bit */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);
+  /* Enable or Disable the Output Compare Fast Bit */
+  tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Clears or safeguards the OCREF1 signal on an external event
+  * @param  TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCClear_Enable: TIM Output clear enable
+  *            @arg TIM_OCClear_Disable: TIM Output clear disable
+  * @retval None
+  */
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+  uint16_t tmpccmr1 = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+  
+  tmpccmr1 = TIMx->CCMR1;
+  /* Reset the OC1CE Bit */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);
+  /* Enable or Disable the Output Compare Clear Bit */
+  tmpccmr1 |= TIM_OCClear;
+  /* Write to TIMx CCMR1 register */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Clears or safeguards the OCREF2 signal on an external event
+  * @param  TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCClear_Enable: TIM Output clear enable
+  *            @arg TIM_OCClear_Disable: TIM Output clear disable
+  * @retval None
+  */
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+  uint16_t tmpccmr1 = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+  
+  tmpccmr1 = TIMx->CCMR1;
+  /* Reset the OC2CE Bit */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);
+  /* Enable or Disable the Output Compare Clear Bit */
+  tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
+  /* Write to TIMx CCMR1 register */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Clears or safeguards the OCREF3 signal on an external event
+  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCClear_Enable: TIM Output clear enable
+  *            @arg TIM_OCClear_Disable: TIM Output clear disable
+  * @retval None
+  */
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+  uint16_t tmpccmr2 = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+  
+  tmpccmr2 = TIMx->CCMR2;
+  /* Reset the OC3CE Bit */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);
+  /* Enable or Disable the Output Compare Clear Bit */
+  tmpccmr2 |= TIM_OCClear;
+  /* Write to TIMx CCMR2 register */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Clears or safeguards the OCREF4 signal on an external event
+  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCClear_Enable: TIM Output clear enable
+  *            @arg TIM_OCClear_Disable: TIM Output clear disable
+  * @retval None
+  */
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+  uint16_t tmpccmr2 = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+  
+  tmpccmr2 = TIMx->CCMR2;
+  /* Reset the OC4CE Bit */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);
+  /* Enable or Disable the Output Compare Clear Bit */
+  tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
+  /* Write to TIMx CCMR2 register */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Configures the TIMx channel 1 polarity.
+  * @param  TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_OCPolarity: specifies the OC1 Polarity
+  *          This parmeter can be one of the following values:
+  *            @arg TIM_OCPolarity_High: Output Compare active high
+  *            @arg TIM_OCPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+  uint16_t tmpccer = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+  
+  tmpccer = TIMx->CCER;
+  /* Set or Reset the CC1P Bit */
+  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);
+  tmpccer |= TIM_OCPolarity;
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx Channel 1N polarity.
+  * @param  TIMx: where x can be 1, 15, 16 or 17 to select the TIM peripheral.
+  * @param  TIM_OCNPolarity: specifies the OC1N Polarity
+  *          This parmeter can be one of the following values:
+  *            @arg TIM_OCNPolarity_High: Output Compare active high
+  *            @arg TIM_OCNPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+  uint16_t tmpccer = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+   
+  tmpccer = TIMx->CCER;
+  /* Set or Reset the CC1NP Bit */
+  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP);
+  tmpccer |= TIM_OCNPolarity;
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx channel 2 polarity.
+  * @param  TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_OCPolarity: specifies the OC2 Polarity
+  *          This parmeter can be one of the following values:
+  *            @arg TIM_OCPolarity_High: Output Compare active high
+  *            @arg TIM_OCPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+  uint16_t tmpccer = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+  
+  tmpccer = TIMx->CCER;
+  /* Set or Reset the CC2P Bit */
+  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);
+  tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx Channel 2N polarity.
+  * @param  TIMx: where x can be 1 to select the TIM peripheral.
+  * @param  TIM_OCNPolarity: specifies the OC2N Polarity
+  *          This parmeter can be one of the following values:
+  *            @arg TIM_OCNPolarity_High: Output Compare active high
+  *            @arg TIM_OCNPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+  uint16_t tmpccer = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+  
+  tmpccer = TIMx->CCER;
+  /* Set or Reset the CC2NP Bit */
+  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP);
+  tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx channel 3 polarity.
+  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_OCPolarity: specifies the OC3 Polarity
+  *          This parmeter can be one of the following values:
+  *            @arg TIM_OCPolarity_High: Output Compare active high
+  *            @arg TIM_OCPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+  uint16_t tmpccer = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+  
+  tmpccer = TIMx->CCER;
+  /* Set or Reset the CC3P Bit */
+  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);
+  tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx Channel 3N polarity.
+  * @param  TIMx: where x can be 1 to select the TIM peripheral.
+  * @param  TIM_OCNPolarity: specifies the OC3N Polarity
+  *          This parmeter can be one of the following values:
+  *            @arg TIM_OCNPolarity_High: Output Compare active high
+  *            @arg TIM_OCNPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+  uint16_t tmpccer = 0;
+ 
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+    
+  tmpccer = TIMx->CCER;
+  /* Set or Reset the CC3NP Bit */
+  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP);
+  tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx channel 4 polarity.
+  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_OCPolarity: specifies the OC4 Polarity
+  *          This parmeter can be one of the following values:
+  *            @arg TIM_OCPolarity_High: Output Compare active high
+  *            @arg TIM_OCPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+  uint16_t tmpccer = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+  
+  tmpccer = TIMx->CCER;
+  /* Set or Reset the CC4P Bit */
+  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);
+  tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Selects the OCReference Clear source.
+  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_OCReferenceClear: specifies the OCReference Clear source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF.
+  *            @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input.  
+  * @retval None
+  */
+void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear));
+
+  /* Set the TIM_OCReferenceClear source */
+  TIMx->SMCR &=  (uint16_t)~((uint16_t)TIM_SMCR_OCCS);
+  TIMx->SMCR |=  TIM_OCReferenceClear;
+}
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel x.
+  * @param  TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.
+  * @param  TIM_Channel: specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_Channel_1: TIM Channel 1
+  *            @arg TIM_Channel_2: TIM Channel 2
+  *            @arg TIM_Channel_3: TIM Channel 3
+  *            @arg TIM_Channel_4: TIM Channel 4
+  * @param  TIM_CCx: specifies the TIM Channel CCxE bit new state.
+  *          This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. 
+  * @retval None
+  */
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
+{
+  uint16_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx)); 
+  assert_param(IS_TIM_CCX(TIM_CCx));
+
+  tmp = CCER_CCE_SET << TIM_Channel;
+
+  /* Reset the CCxE Bit */
+  TIMx->CCER &= (uint16_t)~ tmp;
+
+  /* Set or reset the CCxE Bit */ 
+  TIMx->CCER |=  (uint16_t)(TIM_CCx << TIM_Channel);
+}
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel xN.
+  * @param  TIMx: where x can be 1, 15, 16 or 17 to select the TIM peripheral.
+  * @param  TIM_Channel: specifies the TIM Channel
+  *          This parmeter can be one of the following values:
+  *            @arg TIM_Channel_1: TIM Channel 1
+  *            @arg TIM_Channel_2: TIM Channel 2
+  *            @arg TIM_Channel_3: TIM Channel 3
+  * @param  TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
+  *          This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. 
+  * @retval None
+  */
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
+{
+  uint16_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
+  assert_param(IS_TIM_CCXN(TIM_CCxN));
+
+  tmp = CCER_CCNE_SET << TIM_Channel;
+
+  /* Reset the CCxNE Bit */
+  TIMx->CCER &= (uint16_t) ~tmp;
+
+  /* Set or reset the CCxNE Bit */ 
+  TIMx->CCER |=  (uint16_t)(TIM_CCxN << TIM_Channel);
+}
+
+/**
+  * @brief  Selects the TIM peripheral Commutation event.
+  * @param  TIMx: where x can be  1, 15, 16 or 17 to select the TIMx peripheral
+  * @param  NewState: new state of the Commutation event.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Set the COM Bit */
+    TIMx->CR2 |= TIM_CR2_CCUS;
+  }
+  else
+  {
+    /* Reset the COM Bit */
+    TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group4 Input Capture management functions
+ *  @brief    Input Capture management functions 
+ *
+@verbatim
+ ===============================================================================
+               ##### Input Capture management functions #####
+ ===============================================================================
+   
+          *** TIM Driver: how to use it in Input Capture Mode ***
+ ===============================================================================
+    [..] To use the Timer in Input Capture mode, the following steps are mandatory:
+         (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) 
+             function.
+         (#) Configure the TIM pins by configuring the corresponding GPIO pins.
+         (#) Configure the Time base unit as described in the first part of this 
+             driver, if needed, else the Timer will run with the default configuration:
+             (++) Autoreload value = 0xFFFF.
+             (++) Prescaler value = 0x0000.
+             (++) Counter mode = Up counting.
+             (++) Clock Division = TIM_CKD_DIV1.
+         (#) Fill the TIM_ICInitStruct with the desired parameters including:
+             (++) TIM Channel: TIM_Channel.
+             (++) TIM Input Capture polarity: TIM_ICPolarity.
+             (++) TIM Input Capture selection: TIM_ICSelection.
+             (++) TIM Input Capture Prescaler: TIM_ICPrescaler.
+             (++) TIM Input CApture filter value: TIM_ICFilter.
+         (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired 
+             channel with the corresponding configuration and to measure only 
+             frequency or duty cycle of the input signal,or, Call 
+             TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired 
+             channels with the corresponding configuration and to measure the 
+             frequency and the duty cycle of the input signal.
+         (#) Enable the NVIC or the DMA to read the measured frequency.
+         (#) Enable the corresponding interrupt (or DMA request) to read 
+             the Captured value, using the function TIM_ITConfig(TIMx, TIM_IT_CCx)
+             (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)).
+         (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
+         (#) Use TIM_GetCapturex(TIMx); to read the captured value.
+    [..]
+        (@) All other functions can be used separately to modify, if needed,
+            a specific feature of the Timer. 
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the TIM peripheral according to the specified
+  *         parameters in the TIM_ICInitStruct.
+  * @param  TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.
+  * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
+  *         that contains the configuration information for the specified TIM 
+  *         peripheral.
+  * @retval None
+  */
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));  
+  assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
+  assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
+  assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
+
+  if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+  {
+    assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+    /* TI1 Configuration */
+    TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+               TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+  else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
+  {
+    assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+    /* TI2 Configuration */
+    TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+               TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+  else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
+  {
+    assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+    /* TI3 Configuration */
+    TI3_Config(TIMx,  TIM_ICInitStruct->TIM_ICPolarity,
+               TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+  else
+  {
+    assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+    /* TI4 Configuration */
+    TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+               TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+}
+
+/**
+  * @brief  Fills each TIM_ICInitStruct member with its default value.
+  * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+  /* Set the default configuration */
+  TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
+  TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
+  TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
+  TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
+  TIM_ICInitStruct->TIM_ICFilter = 0x00;
+}
+
+/**
+  * @brief  Configures the TIM peripheral according to the specified
+  *         parameters in the TIM_ICInitStruct to measure an external PWM signal.
+  * @param  TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
+  *         that contains the configuration information for the specified TIM 
+  *         peripheral.
+  * @retval None
+  */
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+  uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
+  uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  /* Select the Opposite Input Polarity */
+  if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
+  {
+    icoppositepolarity = TIM_ICPolarity_Falling;
+  }
+  else
+  {
+    icoppositepolarity = TIM_ICPolarity_Rising;
+  }
+  /* Select the Opposite Input */
+  if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
+  {
+    icoppositeselection = TIM_ICSelection_IndirectTI;
+  }
+  else
+  {
+    icoppositeselection = TIM_ICSelection_DirectTI;
+  }
+  if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+  {
+    /* TI1 Configuration */
+    TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    /* TI2 Configuration */
+    TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+  else
+  { 
+    /* TI2 Configuration */
+    TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    /* TI1 Configuration */
+    TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+}
+
+/**
+  * @brief  Gets the TIMx Input Capture 1 value.
+  * @param  TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @retval Capture Compare 1 Register value.
+  */
+uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  
+  /* Get the Capture 1 Register value */
+  return TIMx->CCR1;
+}
+
+/**
+  * @brief  Gets the TIMx Input Capture 2 value.
+  * @param  TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
+  * @retval Capture Compare 2 Register value.
+  */
+uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  
+  /* Get the Capture 2 Register value */
+  return TIMx->CCR2;
+}
+
+/**
+  * @brief  Gets the TIMx Input Capture 3 value.
+  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @retval Capture Compare 3 Register value.
+  */
+uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
+  
+  /* Get the Capture 3 Register value */
+  return TIMx->CCR3;
+}
+
+/**
+  * @brief  Gets the TIMx Input Capture 4 value.
+  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @retval Capture Compare 4 Register value.
+  */
+uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  
+  /* Get the Capture 4 Register value */
+  return TIMx->CCR4;
+}
+
+/**
+  * @brief  Sets the TIMx Input Capture 1 prescaler.
+  * @param  TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_ICPSC: specifies the Input Capture1 prescaler new value.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+  
+  /* Reset the IC1PSC Bits */
+  TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);
+  /* Set the IC1PSC value */
+  TIMx->CCMR1 |= TIM_ICPSC;
+}
+
+/**
+  * @brief  Sets the TIMx Input Capture 2 prescaler.
+  * @param  TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_ICPSC: specifies the Input Capture2 prescaler new value.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+  
+  /* Reset the IC2PSC Bits */
+  TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);
+  /* Set the IC2PSC value */
+  TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/**
+  * @brief  Sets the TIMx Input Capture 3 prescaler.
+  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_ICPSC: specifies the Input Capture3 prescaler new value.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+  
+  /* Reset the IC3PSC Bits */
+  TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);
+  /* Set the IC3PSC value */
+  TIMx->CCMR2 |= TIM_ICPSC;
+}
+
+/**
+  * @brief  Sets the TIMx Input Capture 4 prescaler.
+  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_ICPSC: specifies the Input Capture4 prescaler new value.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{  
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+  
+  /* Reset the IC4PSC Bits */
+  TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);
+  /* Set the IC4PSC value */
+  TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group5 Interrupts DMA and flags management functions
+ *  @brief    Interrupts, DMA and flags management functions 
+ *
+@verbatim
+ ===============================================================================
+          ##### Interrupts, DMA and flags management functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified TIM interrupts.
+  * @param  TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIMx peripheral.
+  * @note   TIM7 is applicable only for STM32F072 devices
+  * @note   TIM6 is not applivable for STM32F031 devices.
+  * @note   TIM2 is not applicable for STM32F030 devices.
+  * @param  TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM_IT_Update: TIM update Interrupt source
+  *            @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+  *            @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+  *            @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+  *            @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+  *            @arg TIM_IT_COM: TIM Commutation Interrupt source
+  *            @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+  *            @arg TIM_IT_Break: TIM Break Interrupt source
+  * 
+  * @note   TIM6 and TIM7 can only generate an update interrupt.
+  * @note   TIM15 can have only TIM_IT_Update, TIM_IT_CC1,TIM_IT_CC2 or TIM_IT_Trigger. 
+  * @note   TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.   
+  * @note   TIM_IT_Break is used only with TIM1 and TIM15. 
+  * @note   TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17.
+  *       
+  * @param  NewState: new state of the TIM interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
+{  
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_IT(TIM_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the Interrupt sources */
+    TIMx->DIER |= TIM_IT;
+  }
+  else
+  {
+    /* Disable the Interrupt sources */
+    TIMx->DIER &= (uint16_t)~TIM_IT;
+  }
+}
+
+/**
+  * @brief  Configures the TIMx event to be generate by software.
+  * @param  TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the 
+  *         TIM peripheral.
+  * @note   TIM7 is applicable only for STM32F072 devices
+  * @note   TIM6 is not applivable for STM32F031 devices.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_EventSource: specifies the event source.
+  *          This parameter can be one or more of the following values:  
+  *            @arg TIM_EventSource_Update: Timer update Event source
+  *            @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
+  *            @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
+  *            @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
+  *            @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
+  *            @arg TIM_EventSource_COM: Timer COM event source  
+  *            @arg TIM_EventSource_Trigger: Timer Trigger Event source
+  *            @arg TIM_EventSource_Break: Timer Break event source
+  *
+  * @note   TIM6 and TIM7 can only generate an update event.  
+  * @note   TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1.
+  *             
+  * @retval None
+  */
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
+{ 
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); 
+  /* Set the event sources */
+  TIMx->EGR = TIM_EventSource;
+}
+
+/**
+  * @brief  Checks whether the specified TIM flag is set or not.
+  * @param  TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral.
+  * @note   TIM7 is applicable only for STM32F072 devices
+  * @note   TIM6 is not applivable for STM32F031 devices.
+  * @note   TIM2 is not applicable for STM32F030 devices.
+  * @param  TIM_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_FLAG_Update: TIM update Flag
+  *            @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
+  *            @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
+  *            @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
+  *            @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
+  *            @arg TIM_FLAG_COM: TIM Commutation Flag
+  *            @arg TIM_FLAG_Trigger: TIM Trigger Flag
+  *            @arg TIM_FLAG_Break: TIM Break Flag
+  *            @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
+  *            @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
+  *            @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
+  *            @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
+  *
+  * @note   TIM6 and TIM7 can have only one update flag. 
+  * @note   TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, TIM_FLAG_CC2 or TIM_FLAG_Trigger.
+  * @note   TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.   
+  * @note   TIM_FLAG_Break is used only with TIM1 and TIM15. 
+  * @note   TIM_FLAG_COM is used only with TIM1 TIM15, TIM16 and TIM17.
+  *
+  * @retval The new state of TIM_FLAG (SET or RESET).
+  */
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
+{ 
+  ITStatus bitstatus = RESET; 
+   
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
+  
+  if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the TIMx's pending flags.
+  * @param  TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral.
+  * @note   TIM7 is applicable only for STM32F072 devices
+  * @note   TIM6 is not applivable for STM32F031 devices.
+  * @note   TIM2 is not applicable for STM32F030 devices.
+  * @param  TIM_FLAG: specifies the flag bit to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM_FLAG_Update: TIM update Flag
+  *            @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
+  *            @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
+  *            @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
+  *            @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
+  *            @arg TIM_FLAG_COM: TIM Commutation Flag
+  *            @arg TIM_FLAG_Trigger: TIM Trigger Flag
+  *            @arg TIM_FLAG_Break: TIM Break Flag
+  *            @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
+  *            @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
+  *            @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
+  *            @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
+  *
+  * @note   TIM6 and TIM7 can have only one update flag. 
+  * @note   TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,TIM_FLAG_CC2 or 
+  *         TIM_FLAG_Trigger. 
+  * @note   TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.   
+  * @note   TIM_FLAG_Break is used only with TIM1 and TIM15. 
+  * @note   TIM_FLAG_COM is used only with TIM1, TIM15, TIM16 and TIM17.
+  *
+  * @retval None
+  */
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
+{  
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
+   
+  /* Clear the flags */
+  TIMx->SR = (uint16_t)~TIM_FLAG;
+}
+
+/**
+  * @brief  Checks whether the TIM interrupt has occurred or not.
+  * @param  TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral.
+  * @note   TIM7 is applicable only for STM32F072 devices
+  * @note   TIM6 is not applivable for STM32F031 devices.
+  * @note   TIM2 is not applicable for STM32F030 devices.
+  * @param  TIM_IT: specifies the TIM interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_Update: TIM update Interrupt source
+  *            @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+  *            @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+  *            @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+  *            @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+  *            @arg TIM_IT_COM: TIM Commutation Interrupt source
+  *            @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+  *            @arg TIM_IT_Break: TIM Break Interrupt source
+  *
+  * @note   TIM6 and TIM7 can generate only an update interrupt.
+  * @note   TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. 
+  * @note   TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.   
+  * @note   TIM_IT_Break is used only with TIM1 and TIM15. 
+  * @note   TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17.
+  *
+  * @retval The new state of the TIM_IT(SET or RESET).
+  */
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
+{
+  ITStatus bitstatus = RESET;  
+  uint16_t itstatus = 0x0, itenable = 0x0;
+  
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_GET_IT(TIM_IT));
+   
+  itstatus = TIMx->SR & TIM_IT;
+  
+  itenable = TIMx->DIER & TIM_IT;
+  if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the TIMx's interrupt pending bits.
+  * @param  TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral.
+  * @note   TIM7 is applicable only for STM32F072 devices
+  * @note   TIM6 is not applivable for STM32F031 devices.
+  * @note   TIM2 is not applicable for STM32F030 devices.
+  * @param  TIM_IT: specifies the pending bit to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM_IT_Update: TIM1 update Interrupt source
+  *            @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+  *            @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+  *            @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+  *            @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+  *            @arg TIM_IT_COM: TIM Commutation Interrupt source
+  *            @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+  *            @arg TIM_IT_Break: TIM Break Interrupt source
+  *
+  * @note   TIM6 and TIM7 can generate only an update interrupt.
+  * @note   TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. 
+  * @note   TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.   
+  * @note   TIM_IT_Break is used only with TIM1 and TIM15. 
+  * @note   TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17.
+  *
+  * @retval None
+  */
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_IT(TIM_IT));
+   
+  /* Clear the IT pending Bit */
+  TIMx->SR = (uint16_t)~TIM_IT;
+}
+
+/**
+  * @brief  Configures the TIMx's DMA interface.
+  * @param  TIMx: where x can be 1, 2, 3, 15, 16 or 17  to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.
+  * @param  TIM_DMABase: DMA Base address.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_DMABase_CR1
+  *            @arg TIM_DMABase_CR2
+  *            @arg TIM_DMABase_SMCR
+  *            @arg TIM_DMABase_DIER
+  *            @arg TIM_DMABase_SR
+  *            @arg TIM_DMABase_EGR
+  *            @arg TIM_DMABase_CCMR1
+  *            @arg TIM_DMABase_CCMR2
+  *            @arg TIM_DMABase_CCER
+  *            @arg TIM_DMABase_CNT
+  *            @arg TIM_DMABase_PSC
+  *            @arg TIM_DMABase_ARR
+  *            @arg TIM_DMABase_CCR1
+  *            @arg TIM_DMABase_CCR2
+  *            @arg TIM_DMABase_CCR3 
+  *            @arg TIM_DMABase_CCR4
+  *            @arg TIM_DMABase_DCR
+  *            @arg TIM_DMABase_OR
+  * @param  TIM_DMABurstLength: DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
+  * @retval None
+  */
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); 
+  assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
+  /* Set the DMA Base and the DMA Burst Length */
+  TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
+}
+
+/**
+  * @brief  Enables or disables the TIMx's DMA Requests.
+  * @param  TIMx: where x can be 1, 2, 3, 6, 7, 15, 16 or 17 to select the TIM peripheral. 
+  * @note   TIM7 is applicable only for STM32F072 devices
+  * @note   TIM6 is not applivable for STM32F031 devices.
+  * @note   TIM2 is not applicable for STM32F030 devices.
+  * @param  TIM_DMASource: specifies the DMA Request sources.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM_DMA_Update: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_Trigger: TIM Trigger DMA source
+  * @param  NewState: new state of the DMA Request sources.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST10_PERIPH(TIMx));
+  assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA sources */
+    TIMx->DIER |= TIM_DMASource; 
+  }
+  else
+  {
+    /* Disable the DMA sources */
+    TIMx->DIER &= (uint16_t)~TIM_DMASource;
+  }
+}
+
+/**
+  * @brief  Selects the TIMx peripheral Capture Compare DMA source.
+  * @param  TIMx: where x can be 1, 2, 3, 15, 16 or 17  to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.
+  * @param  NewState: new state of the Capture Compare DMA source
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST5_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Set the CCDS Bit */
+    TIMx->CR2 |= TIM_CR2_CCDS;
+  }
+  else
+  {
+    /* Reset the CCDS Bit */
+    TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group6 Clocks management functions
+ *  @brief    Clocks management functions
+ *
+@verbatim
+ ===============================================================================
+                     ##### Clocks management functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the TIMx internal Clock
+  * @param  TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @retval None
+  */
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  /* Disable slave mode to clock the prescaler directly with the internal clock */
+  TIMx->SMCR &=  (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
+}
+
+/**
+  * @brief  Configures the TIMx Internal Trigger as External Clock
+  * @param  TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_ITRSource: Trigger source.
+  *          This parameter can be one of the following values:
+  *            @arg  TIM_TS_ITR0: Internal Trigger 0
+  *            @arg  TIM_TS_ITR1: Internal Trigger 1
+  *            @arg  TIM_TS_ITR2: Internal Trigger 2
+  *            @arg  TIM_TS_ITR3: Internal Trigger 3
+  * @retval None
+  */
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
+  /* Select the Internal Trigger */
+  TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
+  /* Select the External clock mode1 */
+  TIMx->SMCR |= TIM_SlaveMode_External1;
+}
+
+/**
+  * @brief  Configures the TIMx Trigger as External Clock
+  * @param  TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_TIxExternalCLKSource: Trigger source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
+  *            @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
+  *            @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
+  * @param  TIM_ICPolarity: specifies the TIx Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Rising
+  *            @arg TIM_ICPolarity_Falling
+  * @param  ICFilter: specifies the filter value.
+  *          This parameter must be a value between 0x0 and 0xF.
+  * @retval None
+  */
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
+                                uint16_t TIM_ICPolarity, uint16_t ICFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
+  assert_param(IS_TIM_IC_FILTER(ICFilter));
+  
+  /* Configure the Timer Input Clock Source */
+  if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
+  {
+    TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+  }
+  else
+  {
+    TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+  }
+  /* Select the Trigger source */
+  TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
+  /* Select the External clock mode1 */
+  TIMx->SMCR |= TIM_SlaveMode_External1;
+}
+
+/**
+  * @brief  Configures the External clock Mode1
+  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+  *            @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+  *            @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+  *            @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+  *            @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+  * @param  ExtTRGFilter: External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                             uint16_t ExtTRGFilter)
+{
+  uint16_t tmpsmcr = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+  
+  /* Configure the ETR Clock source */
+  TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+  
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = TIMx->SMCR;
+  /* Reset the SMS Bits */
+  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
+  /* Select the External clock mode1 */
+  tmpsmcr |= TIM_SlaveMode_External1;
+  /* Select the Trigger selection : ETRF */
+  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
+  tmpsmcr |= TIM_TS_ETRF;
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+
+/**
+  * @brief  Configures the External clock Mode2
+  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+  *            @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+  *            @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+  *            @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+  *            @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+  * @param  ExtTRGFilter: External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 
+                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+  
+  /* Configure the ETR Clock source */
+  TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+  /* Enable the External clock mode2 */
+  TIMx->SMCR |= TIM_SMCR_ECE;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group7 Synchronization management functions
+ *  @brief    Synchronization management functions 
+ *
+@verbatim
+ ===============================================================================
+               ##### Synchronization management functions #####
+ ===============================================================================
+        *** TIM Driver: how to use it in synchronization Mode ***
+ ===============================================================================
+    [..] Case of two/several Timers
+         (#) Configure the Master Timers using the following functions:
+             (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx,
+                  uint16_t TIM_TRGOSource).
+             (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx,
+                  uint16_t TIM_MasterSlaveMode);  
+         (#) Configure the Slave Timers using the following functions: 
+             (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, 
+                  uint16_t TIM_InputTriggerSource);  
+             (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
+    [..] Case of Timers and external trigger(ETR pin)
+         (#) Configure the Etrenal trigger using this function:
+             (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
+                  uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
+         (#) Configure the Slave Timers using the following functions:
+             (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx,
+                  uint16_t TIM_InputTriggerSource);
+             (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Selects the Input Trigger source
+  * @param  TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_InputTriggerSource: The Input Trigger source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal Trigger 0
+  *            @arg TIM_TS_ITR1: Internal Trigger 1
+  *            @arg TIM_TS_ITR2: Internal Trigger 2
+  *            @arg TIM_TS_ITR3: Internal Trigger 3
+  *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+  *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+  *            @arg TIM_TS_ETRF: External Trigger input
+  * @retval None
+  */
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
+{
+  uint16_t tmpsmcr = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 
+  assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = TIMx->SMCR;
+  /* Reset the TS Bits */
+  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
+  /* Set the Input Trigger source */
+  tmpsmcr |= TIM_InputTriggerSource;
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+
+/**
+  * @brief  Selects the TIMx Trigger Output Mode.
+  * @param  TIMx: where x can be 1, 2, 3, 6, 7, or 15 to select the TIM peripheral.
+  * @note   TIM7 is applicable only for STM32F072 devices
+  * @note   TIM6 is not applivable for STM32F031 devices.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_TRGOSource: specifies the Trigger Output source.
+  *          This parameter can be one of the following values:
+  *
+  *   - For all TIMx
+  *            @arg TIM_TRGOSource_Reset:  The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
+  *            @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
+  *            @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
+  *
+  *   - For all TIMx except TIM6 and TIM7
+  *            @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
+  *                                     is to be set, as soon as a capture or compare match occurs (TRGO).
+  *            @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
+  *            @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
+  *            @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
+  *            @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
+  *
+  * @retval None
+  */
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST9_PERIPH(TIMx));
+  assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
+
+  /* Reset the MMS Bits */
+  TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);
+  /* Select the TRGO source */
+  TIMx->CR2 |=  TIM_TRGOSource;
+}
+
+/**
+  * @brief  Selects the TIMx Slave Mode.
+  * @param  TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_SlaveMode: specifies the Timer Slave Mode.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
+  *                                      the counter and triggers an update of the registers.
+  *            @arg TIM_SlaveMode_Gated:     The counter clock is enabled when the trigger signal (TRGI) is high.
+  *            @arg TIM_SlaveMode_Trigger:   The counter starts at a rising edge of the trigger TRGI.
+  *            @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
+  * @retval None
+  */
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 
+  assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
+  
+  /* Reset the SMS Bits */
+  TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);
+  /* Select the Slave Mode */
+  TIMx->SMCR |= TIM_SlaveMode;
+}
+
+/**
+  * @brief  Sets or Resets the TIMx Master/Slave Mode.
+  * @param  TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
+  *                                             and its slaves (through TRGO).
+  *            @arg TIM_MasterSlaveMode_Disable: No action
+  * @retval None
+  */
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
+  
+  /* Reset the MSM Bit */
+  TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);
+  
+  /* Set or Reset the MSM Bit */
+  TIMx->SMCR |= TIM_MasterSlaveMode;
+}
+
+/**
+  * @brief  Configures the TIMx External Trigger (ETR).
+  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.   
+  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+  *            @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+  *            @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+  *            @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+  *            @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+  * @param  ExtTRGFilter: External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                   uint16_t ExtTRGFilter)
+{
+  uint16_t tmpsmcr = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+  
+  tmpsmcr = TIMx->SMCR;
+  /* Reset the ETR Bits */
+  tmpsmcr &= SMCR_ETR_MASK;
+  /* Set the Prescaler, the Filter value and the Polarity */
+  tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group8 Specific interface management functions
+ *  @brief    Specific interface management functions 
+ *
+@verbatim
+ ===============================================================================
+             ##### Specific interface management functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the TIMx Encoder Interface.
+  * @param  TIMx: where x can be  1, 2 or 3 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.   
+  * @param  TIM_EncoderMode: specifies the TIMx Encoder Mode.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
+  *            @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
+  *            @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
+  *                                       on the level of the other input.
+  * @param  TIM_IC1Polarity: specifies the IC1 Polarity
+  *          This parmeter can be one of the following values:
+  *            @arg TIM_ICPolarity_Falling: IC Falling edge.
+  *            @arg TIM_ICPolarity_Rising: IC Rising edge.
+  * @param  TIM_IC2Polarity: specifies the IC2 Polarity
+  *          This parmeter can be one of the following values:
+  *            @arg TIM_ICPolarity_Falling: IC Falling edge.
+  *            @arg TIM_ICPolarity_Rising: IC Rising edge.
+  * @retval None
+  */
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
+                                uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
+{
+  uint16_t tmpsmcr = 0;
+  uint16_t tmpccmr1 = 0;
+  uint16_t tmpccer = 0;
+    
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
+  assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
+  assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
+  
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = TIMx->SMCR;
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = TIMx->CCMR1;
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Set the encoder Mode */
+  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
+  tmpsmcr |= TIM_EncoderMode;
+  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+  tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));
+  tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
+  /* Set the TI1 and the TI2 Polarities */
+  tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)) & (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));
+  tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmr1;
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Enables or disables the TIMx's Hall sensor interface.
+  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.   
+  * @param  NewState: new state of the TIMx Hall sensor interface.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Set the TI1S Bit */
+    TIMx->CR2 |= TIM_CR2_TI1S;
+  }
+  else
+  {
+    /* Reset the TI1S Bit */
+    TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group9 Specific remapping management function
+ *  @brief   Specific remapping management function
+ *
+@verbatim
+ ===============================================================================
+               ##### Specific remapping management function #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Configures the TIM14 Remapping input Capabilities.
+  * @param  TIMx: where x can be 14 to select the TIM peripheral.
+  * @param  TIM_Remap: specifies the TIM input reampping source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM14_GPIO: TIM14 Channel 1 is connected to GPIO.
+  *            @arg TIM14_RTC_CLK: TIM14 Channel 1 is connected to RTC input clock.
+  *                                RTC input clock can be LSE, LSI or HSE/div128.
+  *            @arg TIM14_HSE_DIV32: TIM14 Channel 1 is connected to HSE/32 clock.  
+  *            @arg TIM14_MCO: TIM14 Channel 1 is connected to MCO clock.  
+  *                            MCO clock can be HSI14, SYSCLK, HSI, HSE or PLL/2.  
+  * @retval None
+  */
+void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)
+{
+ /* Check the parameters */
+  assert_param(IS_TIM_LIST11_PERIPH(TIMx));
+  assert_param(IS_TIM_REMAP(TIM_Remap));
+
+  /* Set the Timer remapping configuration */
+  TIMx->OR =  TIM_Remap;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Configure the TI1 as Input.
+  * @param  TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.   
+  * @param  TIM_ICPolarity: The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Rising
+  *            @arg TIM_ICPolarity_Falling
+  * @param  TIM_ICSelection: specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
+  *            @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
+  *            @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+  uint16_t tmpccmr1 = 0, tmpccer = 0;
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+  /* Select the Input and set the filter */
+  tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));
+  tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
+ 
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));
+  tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI2 as Input.
+  * @param  TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_ICPolarity: The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Rising
+  *            @arg TIM_ICPolarity_Falling
+  * @param  TIM_ICSelection: specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
+  *            @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
+  *            @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+  uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+  tmp = (uint16_t)(TIM_ICPolarity << 4);
+  /* Select the Input and set the filter */
+  tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));
+  tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
+  tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); 
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));
+  tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);  
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI3 as Input.
+  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.   
+  * @param  TIM_ICPolarity: The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Rising
+  *            @arg TIM_ICPolarity_Falling
+  * @param  TIM_ICSelection: specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
+  *            @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
+  *            @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+  uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+  /* Disable the Channel 3: Reset the CC3E Bit */
+  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);
+  tmpccmr2 = TIMx->CCMR2;
+  tmpccer = TIMx->CCER;
+  tmp = (uint16_t)(TIM_ICPolarity << 8);
+  /* Select the Input and set the filter */
+  tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));
+  tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
+  /* Select the Polarity and set the CC3E Bit */
+  tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));
+  tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);  
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI4 as Input.
+  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
+  * @note   TIM2 is not applicable for STM32F030 devices.  
+  * @param  TIM_ICPolarity: The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Rising
+  *            @arg TIM_ICPolarity_Falling
+  * @param  TIM_ICSelection: specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
+  *            @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
+  *            @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+  uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+
+   /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);
+  tmpccmr2 = TIMx->CCMR2;
+  tmpccer = TIMx->CCER;
+  tmp = (uint16_t)(TIM_ICPolarity << 12);
+  /* Select the Input and set the filter */
+  tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));
+  tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
+  tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);  
+  /* Select the Polarity and set the CC4E Bit */
+  tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P | TIM_CCER_CC4NP));
+  tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_usart.c b/system/src/stm32f0-stdperiph/stm32f0xx_usart.c

new file mode 100644 (file)

index 0000000..5c05899
--- /dev/null
+++ b/system/src/stm32f0-stdperiph/stm32f0xx_usart.c
@@ -0,0 +1,2168 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_usart.c
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Universal synchronous asynchronous receiver
+  *          transmitter (USART):
+  *           + Initialization and Configuration
+  *           + STOP Mode
+  *           + AutoBaudRate
+  *           + Data transfers
+  *           + Multi-Processor Communication
+  *           + LIN mode
+  *           + Half-duplex mode
+  *           + Smartcard mode
+  *           + IrDA mode
+  *           + RS485 mode  
+  *           + DMA transfers management
+  *           + Interrupts and flags management
+  *           
+  *  @verbatim
+ ===============================================================================
+                       ##### How to use this driver #####
+ ===============================================================================
+    [..]
+        (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE)
+            function for USART1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE)
+            function for USART2 and USART3.
+        (#) According to the USART mode, enable the GPIO clocks using 
+            RCC_AHBPeriphClockCmd() function. (The I/O can be TX, RX, CTS, 
+            or and SCLK). 
+        (#) Peripheral's alternate function: 
+            (++) Connect the pin to the desired peripherals' Alternate 
+                 Function (AF) using GPIO_PinAFConfig() function.
+            (++) Configure the desired pin in alternate function by:
+                 GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
+            (++) Select the type, pull-up/pull-down and output speed via 
+                 GPIO_PuPd, GPIO_OType and GPIO_Speed members.
+            (++) Call GPIO_Init() function.        
+        (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware 
+            flow control and Mode(Receiver/Transmitter) using the SPI_Init()
+            function.  
+        (#) For synchronous mode, enable the clock and program the polarity,
+            phase and last bit using the USART_ClockInit() function.  
+        (#) Enable the NVIC and the corresponding interrupt using the function 
+            USART_ITConfig() if you need to use interrupt mode.   
+        (#) When using the DMA mode: 
+            (++) Configure the DMA using DMA_Init() function.
+            (++) Active the needed channel Request using USART_DMACmd() function.   
+        (#) Enable the USART using the USART_Cmd() function.   
+        (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode.   
+    [..]
+            Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections
+            for more details.
+            
+@endverbatim
+       
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_usart.h"
+#include "stm32f0xx_rcc.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup USART 
+  * @brief USART driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/*!< USART CR1 register clear Mask ((~(uint32_t)0xFFFFE6F3)) */
+#define CR1_CLEAR_MASK            ((uint32_t)(USART_CR1_M | USART_CR1_PCE | \
+                                              USART_CR1_PS | USART_CR1_TE | \
+                                              USART_CR1_RE))
+
+/*!< USART CR2 register clock bits clear Mask ((~(uint32_t)0xFFFFF0FF)) */
+#define CR2_CLOCK_CLEAR_MASK      ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
+                                              USART_CR2_CPHA | USART_CR2_LBCL))
+
+/*!< USART CR3 register clear Mask ((~(uint32_t)0xFFFFFCFF)) */
+#define CR3_CLEAR_MASK            ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
+
+/*!< USART Interrupts mask */
+#define IT_MASK                   ((uint32_t)0x000000FF)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup USART_Private_Functions
+  * @{
+  */
+
+/** @defgroup USART_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+          ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+        This subsection provides a set of functions allowing to initialize the USART 
+        in asynchronous and in synchronous modes.
+        (+) For the asynchronous mode only these parameters can be configured: 
+          (++) Baud Rate.
+          (++) Word Length.
+          (++) Stop Bit.
+          (++) Parity: If the parity is enabled, then the MSB bit of the data written
+               in the data register is transmitted but is changed by the parity bit.
+               Depending on the frame length defined by the M bit (8-bits or 9-bits),
+               the possible USART frame formats are as listed in the following table:
+
+   +-------------------------------------------------------------+     
+   |   M bit |  PCE bit  |            USART frame                |
+   |---------------------|---------------------------------------|             
+   |    0    |    0      |    | SB | 8 bit data | STB |          |
+   |---------|-----------|---------------------------------------|  
+   |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+   |---------|-----------|---------------------------------------|  
+   |    1    |    0      |    | SB | 9 bit data | STB |          |
+   |---------|-----------|---------------------------------------|  
+   |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+   +-------------------------------------------------------------+            
+
+          (++) Hardware flow control.
+          (++) Receiver/transmitter modes.
+    [..] The USART_Init() function follows the USART  asynchronous configuration 
+         procedure(details for the procedure are available in reference manual.
+        (+) For the synchronous mode in addition to the asynchronous mode parameters
+            these parameters should be also configured:
+            (++) USART Clock Enabled.
+            (++) USART polarity.
+            (++) USART phase.
+            (++) USART LastBit.
+    [..] These parameters can be configured using the USART_ClockInit() function.
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Deinitializes the USARTx peripheral registers to their default reset values.
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices.  
+  * @note   USART2 is not available for STM32F031 devices.
+  * @retval None
+  */
+void USART_DeInit(USART_TypeDef* USARTx)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+  if (USARTx == USART1)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
+  }
+  else if (USARTx == USART2)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
+  }
+  else if (USARTx == USART3)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
+  }
+    else if (USARTx == USART4)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART4, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART4, DISABLE);
+  }
+  else if (USARTx == USART5)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART5, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART5, DISABLE);
+  }
+    else if (USARTx == USART6)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE);
+  }
+  else if (USARTx == USART7)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART7, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART7, DISABLE);
+  }
+  else 
+  {
+    if  (USARTx == USART8)
+    {
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART8, ENABLE);
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART8, DISABLE);
+    }
+  }
+}
+
+/**
+  * @brief  Initializes the USARTx peripheral according to the specified
+  *         parameters in the USART_InitStruct .
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. 
+  * @note   USART2 is not available for STM32F031 devices.    
+  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure that contains
+  *         the configuration information for the specified USART peripheral.
+  * @retval None
+  */
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
+{
+  uint32_t divider = 0, apbclock = 0, tmpreg = 0;
+  RCC_ClocksTypeDef RCC_ClocksStatus;
+  
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));  
+  assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
+  assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
+  assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
+  assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
+  assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
+  
+  /* Disable USART */
+  USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UE);
+  
+  /*---------------------------- USART CR2 Configuration -----------------------*/
+  tmpreg = USARTx->CR2;
+  /* Clear STOP[13:12] bits */
+  tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
+  
+  /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
+  /* Set STOP[13:12] bits according to USART_StopBits value */
+  tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
+  
+  /* Write to USART CR2 */
+  USARTx->CR2 = tmpreg;
+  
+  /*---------------------------- USART CR1 Configuration -----------------------*/
+  tmpreg = USARTx->CR1;
+  /* Clear M, PCE, PS, TE and RE bits */
+  tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK);
+  
+  /* Configure the USART Word Length, Parity and mode ----------------------- */
+  /* Set the M bits according to USART_WordLength value */
+  /* Set PCE and PS bits according to USART_Parity value */
+  /* Set TE and RE bits according to USART_Mode value */
+  tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
+    USART_InitStruct->USART_Mode;
+  
+  /* Write to USART CR1 */
+  USARTx->CR1 = tmpreg;
+  
+  /*---------------------------- USART CR3 Configuration -----------------------*/  
+  tmpreg = USARTx->CR3;
+  /* Clear CTSE and RTSE bits */
+  tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK);
+  
+  /* Configure the USART HFC -------------------------------------------------*/
+  /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
+  tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
+  
+  /* Write to USART CR3 */
+  USARTx->CR3 = tmpreg;
+  
+  /*---------------------------- USART BRR Configuration -----------------------*/
+  /* Configure the USART Baud Rate -------------------------------------------*/
+  RCC_GetClocksFreq(&RCC_ClocksStatus);
+  
+  if (USARTx == USART1)
+  {
+    apbclock = RCC_ClocksStatus.USART1CLK_Frequency;
+  }
+  else if (USARTx == USART2)
+  {
+    apbclock = RCC_ClocksStatus.USART2CLK_Frequency;
+  }
+   else if (USARTx == USART3)
+  {
+    apbclock = RCC_ClocksStatus.USART3CLK_Frequency;
+  }
+  else
+  {
+    apbclock = RCC_ClocksStatus.PCLK_Frequency;
+  }
+  
+  /* Determine the integer part */
+  if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
+  {
+    /* (divider * 10) computing in case Oversampling mode is 8 Samples */
+    divider = (uint32_t)((2 * apbclock) / (USART_InitStruct->USART_BaudRate));
+    tmpreg  = (uint32_t)((2 * apbclock) % (USART_InitStruct->USART_BaudRate));
+  }
+  else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
+  {
+    /* (divider * 10) computing in case Oversampling mode is 16 Samples */
+    divider = (uint32_t)((apbclock) / (USART_InitStruct->USART_BaudRate));
+    tmpreg  = (uint32_t)((apbclock) % (USART_InitStruct->USART_BaudRate));
+  }
+  
+  /* round the divider : if fractional part i greater than 0.5 increment divider */
+  if (tmpreg >=  (USART_InitStruct->USART_BaudRate) / 2)
+  {
+    divider++;
+  } 
+  
+  /* Implement the divider in case Oversampling mode is 8 Samples */
+  if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
+  {
+    /* get the LSB of divider and shift it to the right by 1 bit */
+    tmpreg = (divider & (uint16_t)0x000F) >> 1;
+    
+    /* update the divider value */
+    divider = (divider & (uint16_t)0xFFF0) | tmpreg;
+  }
+  
+  /* Write to USART BRR */
+  USARTx->BRR = (uint16_t)divider;
+}
+
+/**
+  * @brief  Fills each USART_InitStruct member with its default value.
+  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure
+  *         which will be initialized.
+  * @retval None
+  */
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
+{
+  /* USART_InitStruct members default value */
+  USART_InitStruct->USART_BaudRate = 9600;
+  USART_InitStruct->USART_WordLength = USART_WordLength_8b;
+  USART_InitStruct->USART_StopBits = USART_StopBits_1;
+  USART_InitStruct->USART_Parity = USART_Parity_No ;
+  USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+  USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;  
+}
+
+/**
+  * @brief  Initializes the USARTx peripheral Clock according to the 
+  *         specified parameters in the USART_ClockInitStruct.
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. 
+  * @note   USART2 is not available for STM32F031 devices.   
+  * @param  USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
+  *         structure that contains the configuration information for the specified 
+  *         USART peripheral.  
+  * @retval None
+  */
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
+  assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
+  assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
+  assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
+/*---------------------------- USART CR2 Configuration -----------------------*/
+  tmpreg = USARTx->CR2;
+  /* Clear CLKEN, CPOL, CPHA, LBCL and SSM bits */
+  tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK);
+  /* Configure the USART Clock, CPOL, CPHA, LastBit and SSM ------------*/
+  /* Set CLKEN bit according to USART_Clock value */
+  /* Set CPOL bit according to USART_CPOL value */
+  /* Set CPHA bit according to USART_CPHA value */
+  /* Set LBCL bit according to USART_LastBit value */
+  tmpreg |= (uint32_t)(USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | 
+                       USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit);
+  /* Write to USART CR2 */
+  USARTx->CR2 = tmpreg;
+}
+
+/**
+  * @brief  Fills each USART_ClockInitStruct member with its default value.
+  * @param  USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
+  *         structure which will be initialized.
+  * @retval None
+  */
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
+{
+  /* USART_ClockInitStruct members default value */
+  USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
+  USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
+  USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
+  USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
+}
+
+/**
+  * @brief  Enables or disables the specified USART peripheral.
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. 
+  * @note   USART2 is not available for STM32F031 devices.    
+  * @param  NewState: new state of the USARTx peripheral.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected USART by setting the UE bit in the CR1 register */
+    USARTx->CR1 |= USART_CR1_UE;
+  }
+  else
+  {
+    /* Disable the selected USART by clearing the UE bit in the CR1 register */
+    USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UE);
+  }
+}
+
+/**
+  * @brief  Enables or disables the USART's transmitter or receiver.
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. 
+  * @note   USART2 is not available for STM32F031 devices.  
+  * @param  USART_Direction: specifies the USART direction.
+  *          This parameter can be any combination of the following values:
+  *            @arg USART_Mode_Tx: USART Transmitter
+  *            @arg USART_Mode_Rx: USART Receiver
+  * @param  NewState: new state of the USART transfer direction.
+  *          This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_MODE(USART_DirectionMode));
+  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the USART's transfer interface by setting the TE and/or RE bits 
+       in the USART CR1 register */
+    USARTx->CR1 |= USART_DirectionMode;
+  }
+  else
+  {
+    /* Disable the USART's transfer interface by clearing the TE and/or RE bits
+       in the USART CR3 register */
+    USARTx->CR1 &= (uint32_t)~USART_DirectionMode;
+  }
+}
+
+/**
+  * @brief  Enables or disables the USART's 8x oversampling mode.
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. 
+  * @note   USART2 is not available for STM32F031 devices.  
+  * @param  NewState: new state of the USART 8x oversampling mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   This function has to be called before calling USART_Init() function
+  *         in order to have correct baudrate Divider value.
+  * @retval None
+  */
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */
+    USARTx->CR1 |= USART_CR1_OVER8;
+  }
+  else
+  {
+    /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */
+    USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_OVER8);
+  }
+}  
+
+/**
+  * @brief  Enables or disables the USART's one bit sampling method.
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. 
+  * @note   USART2 is not available for STM32F031 devices.  
+  * @param  NewState: new state of the USART one bit sampling method.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   This function has to be called before calling USART_Cmd() function.  
+  * @retval None
+  */
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */
+    USARTx->CR3 |= USART_CR3_ONEBIT;
+  }
+  else
+  {
+    /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */
+    USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT);
+  }
+}
+
+/**
+  * @brief  Enables or disables the USART's most significant bit first 
+  *         transmitted/received following the start bit.
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. 
+  * @note   USART2 is not available for STM32F031 devices.  
+  * @param  NewState: new state of the USART most significant bit first
+  *         transmitted/received following the start bit.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   This function has to be called before calling USART_Cmd() function.  
+  * @retval None
+  */
+void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the most significant bit first transmitted/received following the 
+       start bit by setting the MSBFIRST bit in the CR2 register */
+    USARTx->CR2 |= USART_CR2_MSBFIRST;
+  }
+  else
+  {
+    /* Disable the most significant bit first transmitted/received following the 
+       start bit by clearing the MSBFIRST bit in the CR2 register */
+    USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_MSBFIRST);
+  }
+}
+
+/**
+  * @brief  Enables or disables the binary data inversion.
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. 
+  * @note   USART2 is not available for STM32F031 devices.  
+  * @param  NewState: new defined levels for the USART data.
+  *          This parameter can be:
+  *            @arg ENABLE: Logical data from the data register are send/received in negative
+  *                          logic (1=L, 0=H). The parity bit is also inverted.
+  *            @arg DISABLE: Logical data from the data register are send/received in positive
+  *                          logic (1=H, 0=L) 
+  * @note   This function has to be called before calling USART_Cmd() function.  
+  * @retval None
+  */
+void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the binary data inversion feature by setting the DATAINV bit in 
+       the CR2 register */
+    USARTx->CR2 |= USART_CR2_DATAINV;
+  }
+  else
+  {
+    /* Disable the binary data inversion feature by clearing the DATAINV bit in 
+       the CR2 register */
+    USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_DATAINV);
+  }
+}
+
+/**
+  * @brief  Enables or disables the Pin(s) active level inversion.
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. 
+  * @note   USART2 is not available for STM32F031 devices.  
+  * @param  USART_InvPin: specifies the USART pin(s) to invert.
+  *          This parameter can be any combination of the following values:
+  *            @arg USART_InvPin_Tx: USART Tx pin active level inversion.
+  *            @arg USART_InvPin_Rx: USART Rx pin active level inversion.
+  * @param  NewState: new active level status for the USART pin(s).
+  *          This parameter can be:
+  *            @arg ENABLE: pin(s) signal values are inverted (Vdd =0, Gnd =1).
+  *            @arg DISABLE: pin(s) signal works using the standard logic levels (Vdd =1, Gnd =0).
+  * @note   This function has to be called before calling USART_Cmd() function.  
+  * @retval None
+  */
+void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_INVERSTION_PIN(USART_InvPin));  
+  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the active level inversion for selected pins by setting the TXINV 
+       and/or RXINV bits in the USART CR2 register */
+    USARTx->CR2 |= USART_InvPin;
+  }
+  else
+  {
+    /* Disable the active level inversion for selected requests by clearing the 
+       TXINV and/or RXINV bits in the USART CR2 register */
+    USARTx->CR2 &= (uint32_t)~USART_InvPin;
+  }
+}
+
+/**
+  * @brief  Enables or disables the swap Tx/Rx pins.
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. 
+  * @note   USART2 is not available for STM32F031 devices.  
+  * @param  NewState: new state of the USARTx TX/RX pins pinout.
+  *          This parameter can be:
+  *            @arg ENABLE: The TX and RX pins functions are swapped.
+  *            @arg DISABLE: TX/RX pins are used as defined in standard pinout
+  * @note   This function has to be called before calling USART_Cmd() function.  
+  * @retval None
+  */
+void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the SWAP feature by setting the SWAP bit in the CR2 register */
+    USARTx->CR2 |= USART_CR2_SWAP;
+  }
+  else
+  {
+    /* Disable the SWAP feature by clearing the SWAP bit in the CR2 register */
+    USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_SWAP);
+  }
+}
+
+/**
+  * @brief  Enables or disables the receiver Time Out feature.
+  * @param  USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
+  * @note   USART2 is available only for STM32F072 and STM32F091 devices. 
+  * @note   USART3 is available only for STM32F091 devices.  
+  * @param  NewState: new state of the USARTx receiver Time Out.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the receiver time out feature by setting the RTOEN bit in the CR2 
+       register */
+    USARTx->CR2 |= USART_CR2_RTOEN;
+  }
+  else
+  {
+    /* Disable the receiver time out feature by clearing the RTOEN bit in the CR2 
+       register */
+    USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_RTOEN);
+  }
+}
+
+/**
+  * @brief  Sets the receiver Time Out value.
+  * @param  USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
+  * @note   USART2 is available only for STM32F072 and STM32F091 devices. 
+  * @note   USART3 is available only for STM32F091 devices.   
+  * @param  USART_ReceiverTimeOut: specifies the Receiver Time Out value.
+  * @retval None
+  */
+void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut)
+{    
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+  assert_param(IS_USART_TIMEOUT(USART_ReceiverTimeOut));
+
+  /* Clear the receiver Time Out value by clearing the RTO[23:0] bits in the RTOR
+     register  */
+  USARTx->RTOR &= (uint32_t)~((uint32_t)USART_RTOR_RTO);
+  /* Set the receiver Time Out value by setting the RTO[23:0] bits in the RTOR
+     register  */
+  USARTx->RTOR |= USART_ReceiverTimeOut;
+}
+
+/**
+  * @brief  Sets the system clock prescaler.
+  * @note   This function is not available for STM32F030 devices.    
+  * @param  USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
+  * @note   USART2 is available only for STM32F072 and STM32F091 devices. 
+  * @note   USART3 is available only for STM32F091 devices. 
+  * @param  USART_Prescaler: specifies the prescaler clock.
+  * @note   This function has to be called before calling USART_Cmd() function.    
+  * @retval None
+  */
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
+{ 
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+  
+  /* Clear the USART prescaler */
+  USARTx->GTPR &= USART_GTPR_GT;
+  /* Set the USART prescaler */
+  USARTx->GTPR |= USART_Prescaler;
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USART_Group2 STOP Mode functions
+ *  @brief   STOP Mode functions
+ *
+@verbatim
+ ===============================================================================
+                        ##### STOP Mode functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage 
+         WakeUp from STOP mode.
+
+    [..] The USART is able to WakeUp from Stop Mode if USART clock is set to HSI
+         or LSI.
+         
+    [..] The WakeUp source is configured by calling USART_StopModeWakeUpSourceConfig()
+         function.
+         
+    [..] After configuring the source of WakeUp and before entering in Stop Mode 
+         USART_STOPModeCmd() function should be called to allow USART WakeUp.
+                           
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified USART peripheral in STOP Mode.
+  * @param  USARTx: where x can be 1 or 2 or 3  to select the USART peripheral.
+  * @note   USART2 is available only for STM32F072 and STM32F091 devices.  
+  * @note   USART3 is available only for STM32F091 devices.   
+  * @param  NewState: new state of the USARTx peripheral state in stop mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   This function has to be called when USART clock is set to HSI or LSE. 
+  * @retval None
+  */
+void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected USART in STOP mode by setting the UESM bit in the CR1
+       register */
+    USARTx->CR1 |= USART_CR1_UESM;
+  }
+  else
+  {
+    /* Disable the selected USART in STOP mode by clearing the UE bit in the CR1
+       register */
+    USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UESM);
+  }
+}
+
+/**
+  * @brief  Selects the USART WakeUp method form stop mode.
+  * @note   This function is not available for STM32F030 devices.   
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @note   USART2 is available only for STM32F072 and STM32F091 devices. 
+  * @note   USART3 is available only for STM32F091 devices.     
+  * @param  USART_WakeUp: specifies the selected USART wakeup method.
+  *          This parameter can be one of the following values:
+  *            @arg USART_WakeUpSource_AddressMatch: WUF active on address match.
+  *            @arg USART_WakeUpSource_StartBit: WUF active on Start bit detection.
+  *            @arg USART_WakeUpSource_RXNE: WUF active on RXNE.
+  * @note   This function has to be called before calling USART_Cmd() function.   
+  * @retval None
+  */
+void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+  assert_param(IS_USART_STOPMODE_WAKEUPSOURCE(USART_WakeUpSource));
+
+  USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_WUS);
+  USARTx->CR3 |= USART_WakeUpSource;
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USART_Group3 AutoBaudRate functions
+ *  @brief   AutoBaudRate functions 
+ *
+@verbatim
+ ===============================================================================
+                       ##### AutoBaudRate functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage 
+         the AutoBaudRate detections.
+         
+    [..] Before Enabling AutoBaudRate detection using USART_AutoBaudRateCmd ()
+         The character patterns used to calculate baudrate must be chosen by calling 
+         USART_AutoBaudRateConfig() function. These function take as parameter :
+        (#)USART_AutoBaudRate_StartBit : any character starting with a bit 1.
+        (#)USART_AutoBaudRate_FallingEdge : any character starting with a 10xx bit pattern. 
+                          
+    [..] At any later time, another request for AutoBaudRate detection can be performed
+         using USART_RequestCmd() function.
+         
+    [..] The AutoBaudRate detection is monitored by the status of ABRF flag which indicate
+         that the AutoBaudRate detection is completed. In addition to ABRF flag, the ABRE flag
+         indicate that this procedure is completed without success. USART_GetFlagStatus () 
+         function should be used to monitor the status of these flags.  
+             
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the Auto Baud Rate.
+  * @param  USARTx: where x can be 1or 2  to select the USART peripheral.
+  * @note   USART2 is available only for STM32F072 and STM32F091 devices. 
+  * @note   USART3 is available only for STM32F091 devices.  
+  * @param  NewState: new state of the USARTx auto baud rate.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the auto baud rate feature by setting the ABREN bit in the CR2 
+       register */
+    USARTx->CR2 |= USART_CR2_ABREN;
+  }
+  else
+  {
+    /* Disable the auto baud rate feature by clearing the ABREN bit in the CR2 
+       register */
+    USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ABREN);
+  }
+}
+
+/**
+  * @brief  Selects the USART auto baud rate method.
+  * @param  USARTx: where x can be 1or 2  to select the USART peripheral.
+  * @note   USART2 is available only for STM32F072 and STM32F091 devices. 
+  * @note   USART3 is available only for STM32F091 devices.  
+  * @param  USART_AutoBaudRate: specifies the selected USART auto baud rate method.
+  *          This parameter can be one of the following values:
+  *            @arg USART_AutoBaudRate_StartBit: Start Bit duration measurement.
+  *            @arg USART_AutoBaudRate_FallingEdge: Falling edge to falling edge measurement.
+  * @note   This function has to be called before calling USART_Cmd() function.  
+  * @retval None
+  */
+void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+  assert_param(IS_USART_AUTOBAUDRATE_MODE(USART_AutoBaudRate));
+
+  USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ABRMODE);
+  USARTx->CR2 |= USART_AutoBaudRate;
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USART_Group4 Data transfers functions
+ *  @brief   Data transfers functions 
+ *
+@verbatim   
+ ===============================================================================
+                    ##### Data transfers functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage 
+         the USART data transfers.
+    [..] During an USART reception, data shifts in least significant bit first 
+         through the RX pin. When a transmission is taking place, a write instruction to 
+         the USART_TDR register stores the data in the shift register.
+    [..] The read access of the USART_RDR register can be done using 
+         the USART_ReceiveData() function and returns the RDR value.
+         Whereas a write access to the USART_TDR can be done using USART_SendData()
+         function and stores the written data into TDR.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmits single data through the USARTx peripheral.
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. 
+  * @note   USART2 is not available for STM32F031 devices.  
+  * @param  Data: the data to transmit.
+  * @retval None
+  */
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_DATA(Data)); 
+    
+  /* Transmit Data */
+  USARTx->TDR = (Data & (uint16_t)0x01FF);
+}
+
+/**
+  * @brief  Returns the most recent received data by the USARTx peripheral.
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. 
+  * @note   USART2 is not available for STM32F031 devices.   
+  * @retval The received data.
+  */
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  
+  /* Receive Data */
+  return (uint16_t)(USARTx->RDR & (uint16_t)0x01FF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group5 MultiProcessor Communication functions
+ *  @brief   Multi-Processor Communication functions 
+ *
+@verbatim   
+ ===============================================================================
+             ##### Multi-Processor Communication functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage the USART
+         multiprocessor communication.
+    [..] For instance one of the USARTs can be the master, its TX output is
+         connected to the RX input of the other USART. The others are slaves,
+         their respective TX outputs are logically ANDed together and connected 
+         to the RX input of the master. USART multiprocessor communication is 
+         possible through the following procedure:
+         (#) Program the Baud rate, Word length = 9 bits, Stop bits, Parity, 
+             Mode transmitter or Mode receiver and hardware flow control values 
+             using the USART_Init() function.
+         (#) Configures the USART address using the USART_SetAddress() function.
+         (#) Configures the wake up methode (USART_WakeUp_IdleLine or 
+             USART_WakeUp_AddressMark) using USART_WakeUpConfig() function only 
+             for the slaves.
+         (#) Enable the USART using the USART_Cmd() function.
+         (#) Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() 
+             function.
+    [..] The USART Slave exit from mute mode when receive the wake up condition.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Sets the address of the USART node.
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. 
+  * @note   USART2 is not available for STM32F031 devices.   
+  * @param  USART_Address: Indicates the address of the USART node.
+  * @retval None
+  */
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  
+  /* Clear the USART address */
+  USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ADD);
+  /* Set the USART address node */
+  USARTx->CR2 |=((uint32_t)USART_Address << (uint32_t)0x18);
+}
+
+/**
+  * @brief  Enables or disables the USART's mute mode.
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. 
+  * @note   USART2 is not available for STM32F031 devices.  
+  * @param  NewState: new state of the USART mute mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the USART mute mode by setting the MME bit in the CR1 register */
+    USARTx->CR1 |= USART_CR1_MME;
+  }
+  else
+  {
+    /* Disable the USART mute mode by clearing the MME bit in the CR1 register */
+    USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_MME);
+  }
+}
+
+/**
+  * @brief  Selects the USART WakeUp method from mute mode.
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. 
+  * @note   USART2 is not available for STM32F031 devices.   
+  * @param  USART_WakeUp: specifies the USART wakeup method.
+  *          This parameter can be one of the following values:
+  *            @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection
+  *            @arg USART_WakeUp_AddressMark: WakeUp by an address mark
+  * @retval None
+  */
+void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_MUTEMODE_WAKEUP(USART_WakeUp));
+
+  USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_WAKE);
+  USARTx->CR1 |= USART_WakeUp;
+}
+
+/**
+  * @brief  Configure the the USART Address detection length.
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. 
+  * @note   USART2 is not available for STM32F031 devices.  
+  * @param  USART_AddressLength: specifies the USART address length detection.
+  *          This parameter can be one of the following values:
+  *            @arg USART_AddressLength_4b: 4-bit address length detection 
+  *            @arg USART_AddressLength_7b: 7-bit address length detection 
+  * @retval None
+  */
+void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_ADDRESS_DETECTION(USART_AddressLength));
+
+  USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ADDM7);
+  USARTx->CR2 |= USART_AddressLength;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group6 LIN mode functions
+ *  @brief   LIN mode functions 
+ *
+@verbatim   
+ ===============================================================================
+                       ##### LIN mode functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage the USART 
+         LIN Mode communication.
+    [..] In LIN mode, 8-bit data format with 1 stop bit is required in accordance 
+         with the LIN standard.
+    [..] Only this LIN Feature is supported by the USART IP:
+         (+) LIN Master Synchronous Break send capability and LIN slave break 
+             detection capability :  13-bit break generation and 10/11 bit break 
+             detection.
+    [..] USART LIN Master transmitter communication is possible through the 
+         following procedure:
+         (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, 
+             Mode transmitter or Mode receiver and hardware flow control values 
+             using the USART_Init() function.
+         (#) Enable the LIN mode using the USART_LINCmd() function.
+         (#) Enable the USART using the USART_Cmd() function.
+         (#) Send the break character using USART_SendBreak() function.
+    [..] USART LIN Master receiver communication is possible through the 
+         following procedure:
+         (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, 
+             Mode transmitter or Mode receiver and hardware flow control values 
+             using the USART_Init() function.
+         (#) Configures the break detection length 
+             using the USART_LINBreakDetectLengthConfig() function.
+         (#) Enable the LIN mode using the USART_LINCmd() function.
+         -@- In LIN mode, the following bits must be kept cleared:
+             (+@) CLKEN in the USART_CR2 register.
+             (+@) STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register.
+         (#) Enable the USART using the USART_Cmd() function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Sets the USART LIN Break detection length.
+  * @note   This function is not available for STM32F030 devices.  
+  * @param  USARTx: where x can be 1or 2  to select the USART peripheral.
+  * @note   USART2 is available only for STM32F072 and STM32F091 devices. 
+  * @note   USART3 is available only for STM32F091 devices.
+  * @param  USART_LINBreakDetectLength: specifies the LIN break detection length.
+  *          This parameter can be one of the following values:
+  *            @arg USART_LINBreakDetectLength_10b: 10-bit break detection
+  *            @arg USART_LINBreakDetectLength_11b: 11-bit break detection
+  * @retval None
+  */
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+  assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
+
+  USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_LBDL);
+  USARTx->CR2 |= USART_LINBreakDetectLength;  
+}
+
+/**
+  * @brief  Enables or disables the USART's LIN mode.
+  * @note   This function is not available for STM32F030 devices.
+  * @param  USARTx: where x can be 1or 2  to select the USART peripheral.
+  * @note   USART2 is available only for STM32F072 and STM32F091 devices. 
+  * @note   USART3 is available only for STM32F091 devices.  
+  * @param  NewState: new state of the USART LIN mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+    USARTx->CR2 |= USART_CR2_LINEN;
+  }
+  else
+  {
+    /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
+    USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_LINEN);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group7 Halfduplex mode function
+ *  @brief   Half-duplex mode function 
+ *
+@verbatim   
+ ===============================================================================
+                   ##### Half-duplex mode function #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage the USART
+         Half-duplex communication.
+    [..] The USART can be configured to follow a single-wire half-duplex protocol 
+         where the TX and RX lines are internally connected.
+    [..] USART Half duplex communication is possible through the following procedure:
+         (#) Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter 
+             or Mode receiver and hardware flow control values using the USART_Init()
+            function.
+         (#) Configures the USART address using the USART_SetAddress() function.
+         (#) Enable the half duplex mode using USART_HalfDuplexCmd() function.
+         (#) Enable the USART using the USART_Cmd() function.
+         -@- The RX pin is no longer used.
+         -@- In Half-duplex mode the following bits must be kept cleared:
+             (+@) LINEN and CLKEN bits in the USART_CR2 register.
+             (+@) SCEN and IREN bits in the USART_CR3 register.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the USART's Half Duplex communication.
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. 
+  * @note   USART2 is not available for STM32F031 devices.    
+  * @param  NewState: new state of the USART Communication.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+    USARTx->CR3 |= USART_CR3_HDSEL;
+  }
+  else
+  {
+    /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
+    USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_HDSEL);
+  }
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USART_Group8 Smartcard mode functions
+ *  @brief   Smartcard mode functions 
+ *
+@verbatim   
+ ===============================================================================
+                     ##### Smartcard mode functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage the USART
+         Smartcard communication.
+    [..] The Smartcard interface is designed to support asynchronous protocol 
+         Smartcards as defined in the ISO 7816-3 standard. The USART can provide 
+         a clock to the smartcard through the SCLK output. In smartcard mode, 
+         SCLK is not associated to the communication but is simply derived from 
+         the internal peripheral input clock through a 5-bit prescaler.
+    [..] Smartcard communication is possible through the following procedure:
+         (#) Configures the Smartcard Prsecaler using the USART_SetPrescaler() 
+             function.
+         (#) Configures the Smartcard Guard Time using the USART_SetGuardTime() 
+             function.
+         (#) Program the USART clock using the USART_ClockInit() function as following:
+             (++) USART Clock enabled.
+             (++) USART CPOL Low.
+             (++) USART CPHA on first edge.
+             (++) USART Last Bit Clock Enabled.
+         (#) Program the Smartcard interface using the USART_Init() function as 
+             following:
+             (++) Word Length = 9 Bits.
+             (++) 1.5 Stop Bit.
+             (++) Even parity.
+             (++) BaudRate = 12096 baud.
+             (++) Hardware flow control disabled (RTS and CTS signals).
+             (++) Tx and Rx enabled
+         (#) Optionally you can enable the parity error interrupt using 
+             the USART_ITConfig() function.
+         (#) Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function.
+         (#) Enable the Smartcard interface using the USART_SmartCardCmd() function.
+         (#) Enable the USART using the USART_Cmd() function.
+    [..] 
+  Please refer to the ISO 7816-3 specification for more details.
+    [..] 
+         (@) It is also possible to choose 0.5 stop bit for receiving but it is 
+             recommended to use 1.5 stop bits for both transmitting and receiving 
+             to avoid switching between the two configurations.
+         (@) In smartcard mode, the following bits must be kept cleared:
+             (+@) LINEN bit in the USART_CR2 register.
+             (+@) HDSEL and IREN bits in the USART_CR3 register.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Sets the specified USART guard time.
+  * @note   This function is not available for STM32F030 devices.  
+  * @param  USARTx: where x can be 1or 2  to select the USART peripheral.
+  * @note   USART2 is available only for STM32F072 and STM32F091 devices. 
+  * @note   USART3 is available only for STM32F091 devices. 
+  * @param  USART_GuardTime: specifies the guard time.
+  * @retval None
+  */
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
+{    
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+
+  /* Clear the USART Guard time */
+  USARTx->GTPR &= USART_GTPR_PSC;
+  /* Set the USART guard time */
+  USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
+}
+
+/**
+  * @brief  Enables or disables the USART's Smart Card mode.
+  * @note   This function is not available for STM32F030 devices.  
+  * @param  USARTx: where x can be 1or 2  to select the USART peripheral.
+  * @note   USART2 is available only for STM32F072 and STM32F091 devices. 
+  * @note   USART3 is available only for STM32F091 devices. 
+  * @param  NewState: new state of the Smart Card mode.
+  *          This parameter can be: ENABLE or DISABLE.      
+  * @retval None
+  */
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the SC mode by setting the SCEN bit in the CR3 register */
+    USARTx->CR3 |= USART_CR3_SCEN;
+  }
+  else
+  {
+    /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
+    USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_SCEN);
+  }
+}
+
+/**
+  * @brief  Enables or disables NACK transmission.
+  * @note   This function is not available for STM32F030 devices.  
+  * @param  USARTx: where x can be 1or 2  to select the USART peripheral.
+  * @note   USART2 is available only for STM32F072 and STM32F091 devices. 
+  * @note   USART3 is available only for STM32F091 devices.
+  * @param  NewState: new state of the NACK transmission.
+  *          This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx)); 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
+    USARTx->CR3 |= USART_CR3_NACK;
+  }
+  else
+  {
+    /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
+    USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_NACK);
+  }
+}
+
+/**
+  * @brief  Sets the Smart Card number of retries in transmit and receive.
+  * @note   This function is not available for STM32F030 devices.  
+  * @param  USARTx: where x can be 1or 3  to select the USART peripheral.
+  * @note   USART2 is available only for STM32F072 and STM32F091 devices. 
+  * @note   USART3 is available only for STM32F091 devices.
+  * @param  USART_AutoCount: specifies the Smart Card auto retry count.
+  * @retval None
+  */
+void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount)
+{    
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+  assert_param(IS_USART_AUTO_RETRY_COUNTER(USART_AutoCount));
+  /* Clear the USART auto retry count */
+  USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_SCARCNT);
+  /* Set the USART auto retry count*/
+  USARTx->CR3 |= (uint32_t)((uint32_t)USART_AutoCount << 0x11);
+}
+
+/**
+  * @brief  Sets the Smart Card Block length.
+  * @note   This function is not available for STM32F030 devices.  
+  * @param  USARTx: where x can be 1or 3  to select the USART peripheral.
+  * @note   USART2 is available only for STM32F072 and STM32F091 devices. 
+  * @note   USART3 is available only for STM32F091 devices.
+  * @param  USART_BlockLength: specifies the Smart Card block length.
+  * @retval None
+  */
+void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength)
+{    
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+
+  /* Clear the Smart card block length */
+  USARTx->RTOR &= (uint32_t)~((uint32_t)USART_RTOR_BLEN);
+  /* Set the Smart Card block length */
+  USARTx->RTOR |= (uint32_t)((uint32_t)USART_BlockLength << 0x18);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group9 IrDA mode functions
+ *  @brief   IrDA mode functions 
+ *
+@verbatim   
+ ===============================================================================
+                        ##### IrDA mode functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage the USART
+         IrDA communication.
+    [..] IrDA is a half duplex communication protocol. If the Transmitter is busy, 
+         any data on the IrDA receive line will be ignored by the IrDA decoder 
+         and if the Receiver is busy, data on the TX from the USART to IrDA will 
+         not be encoded by IrDA. While receiving data, transmission should be 
+         avoided as the data to be transmitted could be corrupted.
+    [..] IrDA communication is possible through the following procedure:
+         (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, 
+             Transmitter/Receiver modes and hardware flow control values using 
+             the USART_Init() function.
+         (#) Configures the IrDA pulse width by configuring the prescaler using  
+             the USART_SetPrescaler() function.
+         (#) Configures the IrDA  USART_IrDAMode_LowPower or USART_IrDAMode_Normal 
+             mode using the USART_IrDAConfig() function.
+         (#) Enable the IrDA using the USART_IrDACmd() function.
+         (#) Enable the USART using the USART_Cmd() function.         
+    [..]
+    (@) A pulse of width less than two and greater than one PSC period(s) may or 
+        may not be rejected.
+    (@) The receiver set up time should be managed by software. The IrDA physical 
+        layer specification specifies a minimum of 10 ms delay between 
+        transmission and reception (IrDA is a half duplex protocol).
+    (@) In IrDA mode, the following bits must be kept cleared:
+        (+@) LINEN, STOP and CLKEN bits in the USART_CR2 register.
+        (+@) SCEN and HDSEL bits in the USART_CR3 register.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the USART's IrDA interface.
+  * @note   This function is not available for STM32F030 devices.  
+  * @param  USARTx: where x can be 1or 2  to select the USART peripheral.
+  * @note   USART2 is available only for STM32F072 and STM32F091 devices. 
+  * @note   USART3 is available only for STM32F091 devices.
+  * @param  USART_IrDAMode: specifies the IrDA mode.
+  *          This parameter can be one of the following values:
+  *            @arg USART_IrDAMode_LowPower
+  *            @arg USART_IrDAMode_Normal
+  * @retval None
+  */
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+  assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
+
+  USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_IRLP);
+  USARTx->CR3 |= USART_IrDAMode;
+}
+
+/**
+  * @brief  Enables or disables the USART's IrDA interface.
+  * @note   This function is not available for STM32F030 devices.  
+  * @param  USARTx: where x can be 1or 2  to select the USART peripheral.
+  * @note   USART2 is available only for STM32F072 and STM32F091 devices. 
+  * @note   USART3 is available only for STM32F091 devices. 
+  * @param  NewState: new state of the IrDA mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
+    USARTx->CR3 |= USART_CR3_IREN;
+  }
+  else
+  {
+    /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
+    USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_IREN);
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group10 RS485 mode function
+ *  @brief  RS485 mode function 
+ *
+@verbatim  
+ ===============================================================================
+                        ##### RS485 mode functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage the USART
+         RS485 flow control.
+    [..] RS485 flow control (Driver enable feature) handling is possible through
+         the following procedure:
+         (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, 
+             Transmitter/Receiver modes and hardware flow control values using 
+             the USART_Init() function.
+         (#) Enable the Driver Enable using the USART_DECmd() function.
+         (#) Configures the Driver Enable polarity using the USART_DEPolarityConfig()
+             function.
+         (#) Configures the Driver Enable assertion time using USART_SetDEAssertionTime() 
+             function and deassertion time using the USART_SetDEDeassertionTime()
+             function.    
+         (#) Enable the USART using the USART_Cmd() function.
+      -@-  
+       (+@) The assertion and dessertion times are expressed in sample time units (1/8 or 
+            1/16 bit time, depending on the oversampling rate).
+       
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the USART's DE functionality.
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. 
+  * @note   USART2 is not available for STM32F031 devices.  
+  * @param  NewState: new state of the driver enable mode.
+  *          This parameter can be: ENABLE or DISABLE.      
+  * @retval None
+  */
+void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the DE functionality by setting the DEM bit in the CR3 register */
+    USARTx->CR3 |= USART_CR3_DEM;
+  }
+  else
+  {
+    /* Disable the DE functionality by clearing the DEM bit in the CR3 register */
+    USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DEM);
+  }
+}
+
+/**
+  * @brief  Configures the USART's DE polarity
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. 
+  * @note   USART2 is not available for STM32F031 devices.  
+  * @param  USART_DEPolarity: specifies the DE polarity.
+  *          This parameter can be one of the following values:
+  *            @arg USART_DEPolarity_Low
+  *            @arg USART_DEPolarity_High
+  * @retval None
+  */
+void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_DE_POLARITY(USART_DEPolarity));
+
+  USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DEP);
+  USARTx->CR3 |= USART_DEPolarity;
+}
+
+/**
+  * @brief  Sets the specified RS485 DE assertion time
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. 
+  * @note   USART2 is not available for STM32F031 devices.  
+  * @param  USART_DEAssertionTime: specifies the time between the activation of
+  *         the DE signal and the beginning of the start bit
+  * @retval None
+  */
+void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_DE_ASSERTION_DEASSERTION_TIME(USART_DEAssertionTime)); 
+
+  /* Clear the DE assertion time */
+  USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_DEAT);
+  /* Set the new value for the DE assertion time */
+  USARTx->CR1 |=((uint32_t)USART_DEAssertionTime << (uint32_t)0x15);
+}
+
+/**
+  * @brief  Sets the specified RS485 DE deassertion time
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. 
+  * @note   USART2 is not available for STM32F031 devices.  
+  * @param  USART_DeassertionTime: specifies the time between the middle of the last 
+  *         stop bit in a transmitted message and the de-activation of the DE signal
+  * @retval None
+  */
+void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_DE_ASSERTION_DEASSERTION_TIME(USART_DEDeassertionTime)); 
+
+  /* Clear the DE deassertion time */
+  USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_DEDT);
+  /* Set the new value for the DE deassertion time */
+  USARTx->CR1 |=((uint32_t)USART_DEDeassertionTime << (uint32_t)0x10);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group11 DMA transfers management functions
+ *  @brief   DMA transfers management functions
+ *
+@verbatim   
+ ===============================================================================
+               ##### DMA transfers management functions #####
+ ===============================================================================
+    [..] This section provides two functions that can be used only in DMA mode.
+    [..] In DMA Mode, the USART communication can be managed by 2 DMA Channel 
+         requests:
+         (#) USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
+         (#) USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
+    [..] In this Mode it is advised to use the following function:
+         (+) void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, 
+             FunctionalState NewState).
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the USART's DMA interface.
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. 
+  * @note   USART2 is not available for STM32F031 devices.  
+  * @param  USART_DMAReq: specifies the DMA request.
+  *          This parameter can be any combination of the following values:
+  *            @arg USART_DMAReq_Tx: USART DMA transmit request
+  *            @arg USART_DMAReq_Rx: USART DMA receive request
+  * @param  NewState: new state of the DMA Request sources.
+  *          This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_DMAREQ(USART_DMAReq));  
+  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA transfer for selected requests by setting the DMAT and/or
+       DMAR bits in the USART CR3 register */
+    USARTx->CR3 |= USART_DMAReq;
+  }
+  else
+  {
+    /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
+       DMAR bits in the USART CR3 register */
+    USARTx->CR3 &= (uint32_t)~USART_DMAReq;
+  }
+}
+
+/**
+  * @brief  Enables or disables the USART's DMA interface when reception error occurs.
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. 
+  * @note   USART2 is not available for STM32F031 devices.  
+  * @param  USART_DMAOnError: specifies the DMA status in case of reception error.
+  *          This parameter can be any combination of the following values:
+  *            @arg USART_DMAOnError_Enable: DMA receive request enabled when the USART DMA  
+  *                                          reception error is asserted.
+  *            @arg USART_DMAOnError_Disable: DMA receive request disabled when the USART DMA 
+  *                                           reception error is asserted.
+  * @retval None
+  */
+void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_DMAONERROR(USART_DMAOnError)); 
+  
+  /* Clear the DMA Reception error detection bit */
+  USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DDRE);
+  /* Set the new value for the DMA Reception error detection bit */
+  USARTx->CR3 |= USART_DMAOnError;
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup USART_Group12 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions 
+ *
+@verbatim   
+ ===============================================================================
+            ##### Interrupts and flags management functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to configure the 
+         USART Interrupts sources, Requests and check or clear the flags or pending bits status. 
+         The user should identify which mode will be used in his application to 
+         manage the communication: Polling mode, Interrupt mode.
+
+ *** Polling Mode ***
+ ====================
+    [..] In Polling Mode, the SPI communication can be managed by these flags:
+         (#) USART_FLAG_REACK: to indicate the status of the Receive Enable 
+             acknowledge flag
+         (#) USART_FLAG_TEACK: to indicate the status of the Transmit Enable 
+             acknowledge flag.
+         (#) USART_FLAG_WU: to indicate the status of the Wake up flag.
+         (#) USART_FLAG_RWU: to indicate the status of the Receive Wake up flag.
+         (#) USART_FLAG_SBK: to indicate the status of the Send Break flag.
+         (#) USART_FLAG_CM: to indicate the status of the Character match flag.
+         (#) USART_FLAG_BUSY: to indicate the status of the Busy flag.
+         (#) USART_FLAG_ABRF: to indicate the status of the Auto baud rate flag.
+         (#) USART_FLAG_ABRE: to indicate the status of the Auto baud rate error flag.
+         (#) USART_FLAG_EOB: to indicate the status of the End of block flag.
+         (#) USART_FLAG_RTO: to indicate the status of the Receive time out flag.
+         (#) USART_FLAG_nCTSS: to indicate the status of the Inverted nCTS input 
+             bit status.
+         (#) USART_FLAG_TXE: to indicate the status of the transmit buffer register.
+         (#) USART_FLAG_RXNE: to indicate the status of the receive buffer register.
+         (#) USART_FLAG_TC: to indicate the status of the transmit operation.
+         (#) USART_FLAG_IDLE: to indicate the status of the Idle Line.
+         (#) USART_FLAG_CTS: to indicate the status of the nCTS input.
+         (#) USART_FLAG_LBD: to indicate the status of the LIN break detection.
+         (#) USART_FLAG_NE: to indicate if a noise error occur.
+         (#) USART_FLAG_FE: to indicate if a frame error occur.
+         (#) USART_FLAG_PE: to indicate if a parity error occur.
+         (#) USART_FLAG_ORE: to indicate if an Overrun error occur.
+    [..] In this Mode it is advised to use the following functions:
+         (+) FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG).
+         (+) void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG).
+
+ *** Interrupt Mode ***
+ ======================
+    [..] In Interrupt Mode, the USART communication can be managed by 8 interrupt 
+         sources and 10 pending bits:
+         (+) Pending Bits:
+             (##) USART_IT_WU: to indicate the status of the Wake up interrupt.
+             (##) USART_IT_CM: to indicate the status of Character match interrupt.
+             (##) USART_IT_EOB: to indicate the status of End of block interrupt.
+             (##) USART_IT_RTO: to indicate the status of Receive time out interrupt.
+             (##) USART_IT_CTS: to indicate the status of CTS change interrupt.
+             (##) USART_IT_LBD: to indicate the status of LIN Break detection interrupt.
+             (##) USART_IT_TC: to indicate the status of Transmission complete interrupt.
+             (##) USART_IT_IDLE: to indicate the status of IDLE line detected interrupt.
+             (##) USART_IT_ORE: to indicate the status of OverRun Error interrupt.
+             (##) USART_IT_NE: to indicate the status of Noise Error interrupt.
+             (##) USART_IT_FE: to indicate the status of Framing Error interrupt.
+             (##) USART_IT_PE: to indicate the status of Parity Error interrupt.  
+
+         (+) Interrupt Source:
+             (##) USART_IT_WU: specifies the interrupt source for Wake up interrupt.
+             (##) USART_IT_CM: specifies the interrupt source for Character match 
+                  interrupt.
+             (##) USART_IT_EOB: specifies the interrupt source for End of block
+                  interrupt.
+             (##) USART_IT_RTO: specifies the interrupt source for Receive time-out
+                  interrupt.
+             (##) USART_IT_CTS: specifies the interrupt source for CTS change interrupt.
+             (##) USART_IT_LBD: specifies the interrupt source for LIN Break 
+                  detection interrupt.
+             (##) USART_IT_TXE: specifies the interrupt source for Tansmit Data 
+                  Register empty interrupt.
+             (##) USART_IT_TC: specifies the interrupt source for Transmission 
+                  complete interrupt.
+             (##) USART_IT_RXNE: specifies the interrupt source for Receive Data 
+                  register not empty interrupt.
+             (##) USART_IT_IDLE: specifies the interrupt source for Idle line 
+                  detection interrupt.
+             (##) USART_IT_PE: specifies the interrupt source for Parity Error interrupt.
+             (##) USART_IT_ERR: specifies the interrupt source for Error interrupt
+                  (Frame error, noise error, overrun error)
+             -@@- Some parameters are coded in order to use them as interrupt 
+                 source or as pending bits.
+    [..] In this Mode it is advised to use the following functions:
+         (+) void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState).
+         (+) ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT).
+         (+) void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified USART interrupts.
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. 
+  * @note   USART2 is not available for STM32F031 devices.  
+  * @param  USART_IT: specifies the USART interrupt sources to be enabled or disabled.
+  *          This parameter can be one of the following values:
+  *            @arg USART_IT_WU:  Wake up interrupt, not available for  STM32F030 devices.
+  *            @arg USART_IT_CM:  Character match interrupt.
+  *            @arg USART_IT_EOB:  End of block interrupt, not available for  STM32F030 devices.
+  *            @arg USART_IT_RTO:  Receive time out interrupt.
+  *            @arg USART_IT_CTS:  CTS change interrupt.
+  *            @arg USART_IT_LBD:  LIN Break detection interrupt, not available for  STM32F030 devices.
+  *            @arg USART_IT_TXE:  Tansmit Data Register empty interrupt.
+  *            @arg USART_IT_TC:  Transmission complete interrupt.
+  *            @arg USART_IT_RXNE:  Receive Data register not empty interrupt.
+  *            @arg USART_IT_IDLE:  Idle line detection interrupt.
+  *            @arg USART_IT_PE:  Parity Error interrupt.
+  *            @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
+  * @param  NewState: new state of the specified USARTx interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState)
+{
+  uint32_t usartreg = 0, itpos = 0, itmask = 0;
+  uint32_t usartxbase = 0;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_CONFIG_IT(USART_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  usartxbase = (uint32_t)USARTx;
+  
+  /* Get the USART register index */
+  usartreg = (((uint16_t)USART_IT) >> 0x08);
+  
+  /* Get the interrupt position */
+  itpos = USART_IT & IT_MASK;
+  itmask = (((uint32_t)0x01) << itpos);
+  
+  if (usartreg == 0x02) /* The IT is in CR2 register */
+  {
+    usartxbase += 0x04;
+  }
+  else if (usartreg == 0x03) /* The IT is in CR3 register */
+  {
+    usartxbase += 0x08;
+  }
+  else /* The IT is in CR1 register */
+  {
+  }
+  if (NewState != DISABLE)
+  {
+    *(__IO uint32_t*)usartxbase  |= itmask;
+  }
+  else
+  {
+    *(__IO uint32_t*)usartxbase &= ~itmask;
+  }
+}
+
+/**
+  * @brief  Enables the specified USART's Request.
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. 
+  * @note   USART2 is not available for STM32F031 devices.  
+  * @param  USART_Request: specifies the USART request.
+  *          This parameter can be any combination of the following values:
+  *            @arg USART_Request_TXFRQ: Transmit data flush ReQuest
+  *            @arg USART_Request_RXFRQ: Receive data flush ReQuest
+  *            @arg USART_Request_MMRQ: Mute Mode ReQuest
+  *            @arg USART_Request_SBKRQ: Send Break ReQuest
+  *            @arg USART_Request_ABRRQ: Auto Baud Rate ReQuest
+  * @param  NewState: new state of the DMA interface when reception error occurs.
+  *          This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_REQUEST(USART_Request));
+  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the USART ReQuest by setting the dedicated request bit in the RQR
+       register.*/
+      USARTx->RQR |= USART_Request;
+  }
+  else
+  {
+    /* Disable the USART ReQuest by clearing the dedicated request bit in the RQR
+       register.*/
+    USARTx->RQR &= (uint32_t)~USART_Request;
+  }
+}
+
+/**
+  * @brief  Enables or disables the USART's Overrun detection.
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. 
+  * @note   USART2 is not available for STM32F031 devices.  
+  * @param  USART_OVRDetection: specifies the OVR detection status in case of OVR error.
+  *          This parameter can be any combination of the following values:
+  *            @arg USART_OVRDetection_Enable: OVR error detection enabled when
+  *                                            the USART OVR error is asserted.
+  *            @arg USART_OVRDetection_Disable: OVR error detection disabled when
+  *                                             the USART OVR error is asserted.
+  * @retval None
+  */
+void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_OVRDETECTION(USART_OVRDetection));
+  
+  /* Clear the OVR detection bit */
+  USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_OVRDIS);
+  /* Set the new value for the OVR detection bit */
+  USARTx->CR3 |= USART_OVRDetection;
+}
+
+/**
+  * @brief  Checks whether the specified USART flag is set or not.
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. 
+  * @note   USART2 is not available for STM32F031 devices.  
+  * @param  USART_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg USART_FLAG_REACK:  Receive Enable acknowledge flag.
+  *            @arg USART_FLAG_TEACK:  Transmit Enable acknowledge flag.
+  *            @arg USART_FLAG_WU:  Wake up flag, not available for  STM32F030 devices.
+  *            @arg USART_FLAG_RWU:  Receive Wake up flag, not available for  STM32F030 devices.
+  *            @arg USART_FLAG_SBK:  Send Break flag.
+  *            @arg USART_FLAG_CM:  Character match flag.
+  *            @arg USART_FLAG_BUSY:  Busy flag.
+  *            @arg USART_FLAG_ABRF:  Auto baud rate flag.
+  *            @arg USART_FLAG_ABRE:  Auto baud rate error flag.
+  *            @arg USART_FLAG_EOB:  End of block flag, not available for  STM32F030 devices.
+  *            @arg USART_FLAG_RTO:  Receive time out flag.
+  *            @arg USART_FLAG_nCTSS:  Inverted nCTS input bit status.
+  *            @arg USART_FLAG_CTS:  CTS Change flag.
+  *            @arg USART_FLAG_LBD:  LIN Break detection flag, not available for  STM32F030 devices.
+  *            @arg USART_FLAG_TXE:  Transmit data register empty flag.
+  *            @arg USART_FLAG_TC:  Transmission Complete flag.
+  *            @arg USART_FLAG_RXNE:  Receive data register not empty flag.
+  *            @arg USART_FLAG_IDLE:  Idle Line detection flag.
+  *            @arg USART_FLAG_ORE:  OverRun Error flag.
+  *            @arg USART_FLAG_NE:  Noise Error flag.
+  *            @arg USART_FLAG_FE:  Framing Error flag.
+  *            @arg USART_FLAG_PE:  Parity Error flag.
+  * @retval The new state of USART_FLAG (SET or RESET).
+  */
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_FLAG(USART_FLAG));
+  
+  if ((USARTx->ISR & USART_FLAG) != (uint16_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the USARTx's pending flags.
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. 
+  * @note   USART2 is not available for STM32F031 devices.  
+  * @param  USART_FLAG: specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg USART_FLAG_WU:  Wake up flag, not available for  STM32F030 devices.
+  *            @arg USART_FLAG_CM:  Character match flag.
+  *            @arg USART_FLAG_EOB:  End of block flag, not available for  STM32F030 devices.
+  *            @arg USART_FLAG_RTO:  Receive time out flag.
+  *            @arg USART_FLAG_CTS:  CTS Change flag.
+  *            @arg USART_FLAG_LBD:  LIN Break detection flag, not available for  STM32F030 devices.
+  *            @arg USART_FLAG_TC:  Transmission Complete flag.
+  *            @arg USART_FLAG_IDLE:  IDLE line detected flag.
+  *            @arg USART_FLAG_ORE:  OverRun Error flag.
+  *            @arg USART_FLAG_NE: Noise Error flag.
+  *            @arg USART_FLAG_FE: Framing Error flag.
+  *            @arg USART_FLAG_PE:   Parity Errorflag.
+  *   
+  * @note     RXNE pending bit is cleared by a read to the USART_RDR register 
+  *           (USART_ReceiveData()) or by writing 1 to the RXFRQ in the register
+  *           USART_RQR (USART_RequestCmd()).
+  * @note     TC flag can be also cleared by software sequence: a read operation
+  *           to USART_SR register (USART_GetFlagStatus()) followed by a write 
+  *           operation to USART_TDR register (USART_SendData()).
+  * @note     TXE flag is cleared by a write to the USART_TDR register (USART_SendData())
+  *           or by writing 1 to the TXFRQ in the register USART_RQR (USART_RequestCmd()).
+  * @note     SBKF flag is cleared by 1 to the SBKRQ in the register USART_RQR
+  *           (USART_RequestCmd()).
+  * @retval None
+  */
+void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
+     
+  USARTx->ICR = USART_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified USART interrupt has occurred or not.
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. 
+  * @note   USART2 is not available for STM32F031 devices.  
+  * @param  USART_IT: specifies the USART interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg USART_IT_WU:  Wake up interrupt, not available for  STM32F030 devices.
+  *            @arg USART_IT_CM:  Character match interrupt.
+  *            @arg USART_IT_EOB:  End of block interrupt, not available for  STM32F030 devices.
+  *            @arg USART_IT_RTO:  Receive time out interrupt.
+  *            @arg USART_IT_CTS:  CTS change interrupt.
+  *            @arg USART_IT_LBD:  LIN Break detection interrupt, not available for  STM32F030 devices.
+  *            @arg USART_IT_TXE:  Tansmit Data Register empty interrupt.
+  *            @arg USART_IT_TC:  Transmission complete interrupt.
+  *            @arg USART_IT_RXNE:  Receive Data register not empty interrupt.
+  *            @arg USART_IT_IDLE:  Idle line detection interrupt.
+  *            @arg USART_IT_ORE:  OverRun Error interrupt.
+  *            @arg USART_IT_NE:  Noise Error interrupt.
+  *            @arg USART_IT_FE:  Framing Error interrupt.
+  *            @arg USART_IT_PE:  Parity Error interrupt.
+  * @retval The new state of USART_IT (SET or RESET).
+  */
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT)
+{
+  uint32_t bitpos = 0, itmask = 0, usartreg = 0;
+  ITStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_GET_IT(USART_IT)); 
+  
+  /* Get the USART register index */
+  usartreg = (((uint16_t)USART_IT) >> 0x08);
+  /* Get the interrupt position */
+  itmask = USART_IT & IT_MASK;
+  itmask = (uint32_t)0x01 << itmask;
+  
+  if (usartreg == 0x01) /* The IT  is in CR1 register */
+  {
+    itmask &= USARTx->CR1;
+  }
+  else if (usartreg == 0x02) /* The IT  is in CR2 register */
+  {
+    itmask &= USARTx->CR2;
+  }
+  else /* The IT  is in CR3 register */
+  {
+    itmask &= USARTx->CR3;
+  }
+  
+  bitpos = USART_IT >> 0x10;
+  bitpos = (uint32_t)0x01 << bitpos;
+  bitpos &= USARTx->ISR;
+  if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  
+  return bitstatus;  
+}
+
+/**
+  * @brief  Clears the USARTx's interrupt pending bits.
+  * @param  USARTx: where x can be from 1 to 8 to select the USART peripheral.
+  * @note   USART3 and USART4 are available only for STM32F072 and STM32F091 devices.
+  * @note   USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. 
+  * @note   USART2 is not available for STM32F031 devices.  
+  * @param  USART_IT: specifies the interrupt pending bit to clear.
+  *          This parameter can be one of the following values:
+  *            @arg USART_IT_WU:  Wake up interrupt, not available for  STM32F030 devices.
+  *            @arg USART_IT_CM:  Character match interrupt.
+  *            @arg USART_IT_EOB:  End of block interrupt, not available for  STM32F030 devices.
+  *            @arg USART_IT_RTO:  Receive time out interrupt.
+  *            @arg USART_IT_CTS:  CTS change interrupt.
+  *            @arg USART_IT_LBD:  LIN Break detection interrupt, not available for  STM32F030 devices.
+  *            @arg USART_IT_TC:  Transmission complete interrupt.
+  *            @arg USART_IT_IDLE:  IDLE line detected interrupt.
+  *            @arg USART_IT_ORE:  OverRun Error interrupt.
+  *            @arg USART_IT_NE:  Noise Error interrupt.
+  *            @arg USART_IT_FE:  Framing Error interrupt.
+  *            @arg USART_IT_PE:  Parity Error interrupt.
+  *
+  * @note     RXNE pending bit is cleared by a read to the USART_RDR register 
+  *           (USART_ReceiveData()) or by writing 1 to the RXFRQ in the register 
+  *           USART_RQR (USART_RequestCmd()).
+  * @note     TC pending bit can be also cleared by software sequence: a read 
+  *           operation to USART_SR register (USART_GetITStatus()) followed by  
+  *           a write operation to USART_TDR register (USART_SendData()).
+  * @note     TXE pending bit is cleared by a write to the USART_TDR register 
+  *           (USART_SendData()) or by writing 1 to the TXFRQ in the register 
+  *           USART_RQR (USART_RequestCmd()).
+  * @retval None
+  */
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT)
+{
+  uint32_t bitpos = 0, itmask = 0;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_CLEAR_IT(USART_IT)); 
+  
+  bitpos = USART_IT >> 0x10;
+  itmask = ((uint32_t)0x01 << (uint32_t)bitpos);
+  USARTx->ICR = (uint32_t)itmask;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_wwdg.c b/system/src/stm32f0-stdperiph/stm32f0xx_wwdg.c

new file mode 100644 (file)

index 0000000..3b04fb4
--- /dev/null
+++ b/system/src/stm32f0-stdperiph/stm32f0xx_wwdg.c
@@ -0,0 +1,303 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_wwdg.c
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    05-December-2014
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Window watchdog (WWDG) peripheral:
+  *           + Prescaler, Refresh window and Counter configuration
+  *           + WWDG activation
+  *           + Interrupts and flags management
+  *             
+  *  @verbatim
+  *    
+  ============================================================================== 
+                           ##### WWDG features ##### 
+  ============================================================================== 
+    [..] Once enabled the WWDG generates a system reset on expiry of a programmed
+        time period, unless the program refreshes the counter (downcounter) 
+        before to reach 0x3F value (i.e. a reset is generated when the counter
+        value rolls over from 0x40 to 0x3F). 
+    [..] An MCU reset is also generated if the counter value is refreshed
+         before the counter has reached the refresh window value. This 
+         implies that the counter must be refreshed in a limited window.
+
+    [..] Once enabled the WWDG cannot be disabled except by a system reset.
+
+    [..] WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
+         reset occurs.
+
+    [..] The WWDG counter input clock is derived from the APB clock divided 
+         by a programmable prescaler.
+
+    [..] WWDG counter clock = PCLK1 / Prescaler.
+    [..] WWDG timeout = (WWDG counter clock) * (counter value).
+
+    [..] Min-max timeout value @32MHz (PCLK1): ~85us / ~43ms.
+
+                       ##### How to use this driver ##### 
+  ==============================================================================
+    [..]
+        (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) 
+            function.
+              
+        (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function.
+                             
+        (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function.
+              
+        (#) Set the WWDG counter value and start it using WWDG_Enable() function.
+            When the WWDG is enabled the counter value should be configured to 
+            a value greater than 0x40 to prevent generating an immediate reset.
+              
+        (#) Optionally you can enable the Early wakeup interrupt which is 
+            generated when the counter reach 0x40.
+            Once enabled this interrupt cannot be disabled except by a system reset.
+                   
+        (#) Then the application program must refresh the WWDG counter at regular
+            intervals during normal operation to prevent an MCU reset, using
+            WWDG_SetCounter() function. This operation must occur only when
+            the counter value is lower than the refresh window value, 
+            programmed using WWDG_SetWindowValue().
+  
+  *  @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_wwdg.h"
+#include "stm32f0xx_rcc.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup WWDG 
+  * @brief WWDG driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* --------------------- WWDG registers bit mask ---------------------------- */
+/* CFR register bit mask */
+#define CFR_WDGTB_MASK    ((uint32_t)0xFFFFFE7F)
+#define CFR_W_MASK        ((uint32_t)0xFFFFFF80)
+#define BIT_MASK          ((uint8_t)0x7F)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup WWDG_Private_Functions
+  * @{
+  */
+
+/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions
+ *  @brief   Prescaler, Refresh window and Counter configuration functions 
+ *
+@verbatim   
+  ==============================================================================
+    ##### Prescaler, Refresh window and Counter configuration functions #####
+  ==============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the WWDG peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void WWDG_DeInit(void)
+{
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
+}
+
+/**
+  * @brief  Sets the WWDG Prescaler.
+  * @param  WWDG_Prescaler: specifies the WWDG Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
+  *            @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
+  *            @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
+  *            @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
+  * @retval None
+  */
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
+  /* Clear WDGTB[1:0] bits */
+  tmpreg = WWDG->CFR & CFR_WDGTB_MASK;
+  /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
+  tmpreg |= WWDG_Prescaler;
+  /* Store the new value */
+  WWDG->CFR = tmpreg;
+}
+
+/**
+  * @brief  Sets the WWDG window value.
+  * @param  WindowValue: specifies the window value to be compared to the downcounter.
+  *          This parameter value must be lower than 0x80.
+  * @retval None
+  */
+void WWDG_SetWindowValue(uint8_t WindowValue)
+{
+  __IO uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
+  /* Clear W[6:0] bits */
+
+  tmpreg = WWDG->CFR & CFR_W_MASK;
+
+  /* Set W[6:0] bits according to WindowValue value */
+  tmpreg |= WindowValue & (uint32_t) BIT_MASK;
+
+  /* Store the new value */
+  WWDG->CFR = tmpreg;
+}
+
+/**
+  * @brief  Enables the WWDG Early Wakeup interrupt(EWI).
+  * @note   Once enabled this interrupt cannot be disabled except by a system reset. 
+  * @param  None
+  * @retval None
+  */
+void WWDG_EnableIT(void)
+{
+  WWDG->CFR |= WWDG_CFR_EWI;
+}
+
+/**
+  * @brief  Sets the WWDG counter value.
+  * @param  Counter: specifies the watchdog counter value.
+  *          This parameter must be a number between 0x40 and 0x7F (to prevent 
+  *          generating an immediate reset).
+  * @retval None
+  */
+void WWDG_SetCounter(uint8_t Counter)
+{
+  /* Check the parameters */
+  assert_param(IS_WWDG_COUNTER(Counter));
+  /* Write to T[6:0] bits to configure the counter value, no need to do
+     a read-modify-write; writing a 0 to WDGA bit does nothing */
+  WWDG->CR = Counter & BIT_MASK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Group2 WWDG activation functions
+ *  @brief   WWDG activation functions 
+ *
+@verbatim   
+  ==============================================================================
+                     ##### WWDG activation function #####
+  ==============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables WWDG and load the counter value.                  
+  * @param  Counter: specifies the watchdog counter value.
+  *          This parameter must be a number between 0x40 and 0x7F (to prevent 
+  *          generating an immediate reset).
+  * @retval None
+  */
+void WWDG_Enable(uint8_t Counter)
+{
+  /* Check the parameters */
+  assert_param(IS_WWDG_COUNTER(Counter));
+  WWDG->CR = WWDG_CR_WDGA | Counter;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Group3 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions 
+ *
+@verbatim   
+  ==============================================================================
+                ##### Interrupts and flags management functions #####
+  ==============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the Early Wakeup interrupt flag is set or not.
+  * @param  None
+  * @retval The new state of the Early Wakeup interrupt flag (SET or RESET).
+  */
+FlagStatus WWDG_GetFlagStatus(void)
+{
+  FlagStatus bitstatus = RESET;
+    
+  if ((WWDG->SR) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears Early Wakeup interrupt flag.
+  * @param  None
+  * @retval None
+  */
+void WWDG_ClearFlag(void)
+{
+  WWDG->SR = (uint32_t)RESET;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
author	Pascal Spring <pascal.spring@palladium>
	Wed, 15 Jun 2022 21:48:18 +0000 (23:48 +0200)
committer	Pascal Spring <pascal.spring@palladium>
	Wed, 15 Jun 2022 21:48:18 +0000 (23:48 +0200)
.cproject	[new file with mode: 0644]	patch \| blob
.project	[new file with mode: 0644]	patch \| blob
.settings/language.settings.xml	[new file with mode: 0644]	patch \| blob
Release/arm-electronicload-rework.map	[new file with mode: 0644]	patch \| blob
Release/arm-electronicload.elf	[new file with mode: 0755]	patch \| blob
Release/arm-electronicload.hex	[new file with mode: 0644]	patch \| blob
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