From c45758892bb284f5cfdf2b99ca2cce1a12f23bfd Mon Sep 17 00:00:00 2001 From: Pascal Spring Date: Thu, 16 Jun 2022 22:47:56 +0200 Subject: [PATCH] Initial commit --- Debug/bak/subdir.mk | 27 + Debug/makefile | 101 + Debug/objects.mk | 8 + Debug/sources.mk | 37 + Debug/src/subdir.mk | 54 + Debug/system/src/cmsis/subdir.mk | 27 + Debug/system/src/cortexm/subdir.mk | 30 + Debug/system/src/diag/subdir.mk | 27 + Debug/system/src/newlib/subdir.mk | 50 + Debug/system/src/stm32f0-stdperiph/subdir.mk | 90 + How to calculate your 8-digit grid square.pdf | Bin 0 -> 77957 bytes Release/arm-gps_freqref-030.elf | Bin 0 -> 302212 bytes Release/arm-gps_freqref-030.hex | 1673 ++ Release/arm-gps_freqref-030.map | 1846 +++ Release/makefile | 100 + Release/objects.mk | 8 + Release/sources.mk | 36 + Release/src/24aaxx.d | 93 + Release/src/24aaxx.o | Bin 0 -> 6412 bytes Release/src/_write.d | 1 + Release/src/_write.o | Bin 0 -> 1176 bytes Release/src/delay.d | 91 + Release/src/delay.o | Bin 0 -> 7144 bytes Release/src/font_Arial.d | 6 + Release/src/font_Arial.o | Bin 0 -> 137696 bytes Release/src/glcdfont.d | 6 + Release/src/glcdfont.o | Bin 0 -> 4044 bytes Release/src/i2c.d | 91 + Release/src/i2c.o | Bin 0 -> 8992 bytes Release/src/ili9341.d | 93 + Release/src/ili9341.o | Bin 0 -> 62584 bytes Release/src/ili9341gfx.d | 98 + Release/src/ili9341gfx.o | Bin 0 -> 36428 bytes Release/src/main.d | 115 + Release/src/main.o | Bin 0 -> 75888 bytes Release/src/si5351a.d | 95 + Release/src/si5351a.o | Bin 0 -> 14664 bytes Release/src/subdir.mk | 51 + Release/system/src/cmsis/subdir.mk | 27 + Release/system/src/cmsis/system_stm32f0xx.d | 90 + Release/system/src/cmsis/system_stm32f0xx.o | Bin 0 -> 6080 bytes Release/system/src/cmsis/vectors_stm32f0xx.d | 5 + Release/system/src/cmsis/vectors_stm32f0xx.o | Bin 0 -> 5176 bytes .../system/src/cortexm/_initialize_hardware.d | 96 + .../system/src/cortexm/_initialize_hardware.o | Bin 0 -> 3548 bytes Release/system/src/cortexm/_reset_hardware.d | 96 + Release/system/src/cortexm/_reset_hardware.o | Bin 0 -> 3520 bytes .../system/src/cortexm/exception_handlers.d | 104 + .../system/src/cortexm/exception_handlers.o | Bin 0 -> 8812 bytes Release/system/src/cortexm/subdir.mk | 30 + Release/system/src/diag/Trace.d | 1 + Release/system/src/diag/Trace.o | Bin 0 -> 1188 bytes Release/system/src/diag/subdir.mk | 27 + Release/system/src/diag/trace_impl.d | 1 + Release/system/src/diag/trace_impl.o | Bin 0 -> 1196 bytes Release/system/src/newlib/_cxx.d | 4 + Release/system/src/newlib/_cxx.o | Bin 0 -> 10984 bytes Release/system/src/newlib/_exit.d | 4 + Release/system/src/newlib/_exit.o | Bin 0 -> 8164 bytes Release/system/src/newlib/_sbrk.d | 1 + Release/system/src/newlib/_sbrk.o | Bin 0 -> 8212 bytes Release/system/src/newlib/_startup.d | 1 + Release/system/src/newlib/_startup.o | Bin 0 -> 8048 bytes Release/system/src/newlib/_syscalls.d | 1 + Release/system/src/newlib/_syscalls.o | Bin 0 -> 9404 bytes Release/system/src/newlib/assert.d | 4 + Release/system/src/newlib/assert.o | Bin 0 -> 8156 bytes Release/system/src/newlib/subdir.mk | 50 + .../src/stm32f0-stdperiph/stm32f0xx_gpio.d | 90 + .../src/stm32f0-stdperiph/stm32f0xx_gpio.o | Bin 0 -> 11796 bytes .../src/stm32f0-stdperiph/stm32f0xx_rcc.d | 90 + .../src/stm32f0-stdperiph/stm32f0xx_rcc.o | Bin 0 -> 26260 bytes .../system/src/stm32f0-stdperiph/subdir.mk | 27 + bak/ili9341.c | 363 + bak/ili9341.h | 63 + bak/ili9341gfx.c | 410 + bak/ili9341gfx.h | 27 + include/24aaxx.h | 18 + include/delay.h | 26 + include/font_Arial.h | 28 + include/font_courier.h | 7 + include/font_typedef.h | 24 + include/glcdfont.h | 9 + include/i2c.h | 35 + include/ili9341.h | 102 + include/ili9341gfx.h | 29 + include/si5351a.h | 70 + include/stm32f0xx_conf.h | 83 + ldscripts/libs.ld | 8 + ldscripts/mem.ld | 59 + ldscripts/sections.ld | 473 + maidenhead-calc.bas | 64 + src/.si5351a.c.swp | Bin 0 -> 16384 bytes src/24aaxx.c | 60 + src/_write.c | 72 + src/delay.c | 57 + src/font_Arial.c | 12993 ++++++++++++++++ src/glcdfont.c | 286 + src/i2c.c | 152 + src/ili9341.c | 919 ++ src/ili9341gfx.c | 675 + src/main.c | 1996 +++ src/main.c.bak | 1359 ++ src/si5351a.c | 396 + src/timezone.c | 235 + system/include/arm/semihosting.h | 142 + system/include/cmsis/.stm32f0xx.h.swp | Bin 0 -> 16384 bytes system/include/cmsis/README_DEVICE.txt | 7 + system/include/cmsis/arm_common_tables.h | 136 + system/include/cmsis/arm_const_structs.h | 79 + system/include/cmsis/arm_math.h | 7154 +++++++++ system/include/cmsis/cmsis_armcc.h | 734 + system/include/cmsis/cmsis_armcc_V6.h | 1800 +++ system/include/cmsis/cmsis_device.h | 33 + system/include/cmsis/cmsis_gcc.h | 1373 ++ system/include/cmsis/core_cm0.h | 811 + system/include/cmsis/core_cm0plus.h | 927 ++ system/include/cmsis/core_cm3.h | 1776 +++ system/include/cmsis/core_cm4.h | 1950 +++ system/include/cmsis/core_cm7.h | 2525 +++ system/include/cmsis/core_cmFunc.h | 87 + system/include/cmsis/core_cmInstr.h | 87 + system/include/cmsis/core_cmSimd.h | 96 + system/include/cmsis/core_sc000.h | 926 ++ system/include/cmsis/core_sc300.h | 1745 +++ system/include/cmsis/stm32f030xc.h | 2761 ++++ system/include/cmsis/stm32f0xx.h | 5710 +++++++ system/include/cmsis/system_stm32f0xx.h | 104 + system/include/cortexm/ExceptionHandlers.h | 116 + system/include/diag/Trace.h | 168 + .../include/stm32f0-stdperiph/stm32f0xx_adc.h | 450 + .../include/stm32f0-stdperiph/stm32f0xx_can.h | 643 + .../include/stm32f0-stdperiph/stm32f0xx_cec.h | 300 + .../stm32f0-stdperiph/stm32f0xx_comp.h | 245 + .../include/stm32f0-stdperiph/stm32f0xx_crc.h | 122 + .../include/stm32f0-stdperiph/stm32f0xx_crs.h | 183 + .../include/stm32f0-stdperiph/stm32f0xx_dac.h | 312 + .../stm32f0-stdperiph/stm32f0xx_dbgmcu.h | 107 + .../include/stm32f0-stdperiph/stm32f0xx_dma.h | 804 + .../stm32f0-stdperiph/stm32f0xx_exti.h | 216 + .../stm32f0-stdperiph/stm32f0xx_flash.h | 435 + .../stm32f0-stdperiph/stm32f0xx_gpio.h | 358 + .../include/stm32f0-stdperiph/stm32f0xx_i2c.h | 478 + .../stm32f0-stdperiph/stm32f0xx_iwdg.h | 140 + .../stm32f0-stdperiph/stm32f0xx_misc.h | 143 + .../include/stm32f0-stdperiph/stm32f0xx_pwr.h | 197 + .../include/stm32f0-stdperiph/stm32f0xx_rcc.h | 624 + .../include/stm32f0-stdperiph/stm32f0xx_rtc.h | 807 + .../include/stm32f0-stdperiph/stm32f0xx_spi.h | 588 + .../stm32f0-stdperiph/stm32f0xx_syscfg.h | 459 + .../include/stm32f0-stdperiph/stm32f0xx_tim.h | 1186 ++ .../stm32f0-stdperiph/stm32f0xx_usart.h | 604 + .../stm32f0-stdperiph/stm32f0xx_wwdg.h | 109 + system/src/cmsis/README_DEVICE.txt | 7 + system/src/cmsis/system_stm32f0xx.c | 358 + system/src/cmsis/vectors_stm32f0xx.c | 525 + system/src/cortexm/_initialize_hardware.c | 109 + system/src/cortexm/_reset_hardware.c | 59 + system/src/cortexm/exception_handlers.c | 621 + system/src/diag/Trace.c | 98 + system/src/diag/trace_impl.c | 274 + system/src/newlib/README.txt | 16 + system/src/newlib/_cxx.cpp | 72 + system/src/newlib/_exit.c | 81 + system/src/newlib/_sbrk.c | 87 + system/src/newlib/_startup.c | 349 + system/src/newlib/_syscalls.c | 1240 ++ system/src/newlib/assert.c | 77 + system/src/stm32f0-stdperiph/stm32f0xx_adc.c | 1240 ++ system/src/stm32f0-stdperiph/stm32f0xx_can.c | 1631 ++ system/src/stm32f0-stdperiph/stm32f0xx_cec.c | 607 + system/src/stm32f0-stdperiph/stm32f0xx_comp.c | 408 + system/src/stm32f0-stdperiph/stm32f0xx_crc.c | 361 + system/src/stm32f0-stdperiph/stm32f0xx_crs.c | 466 + system/src/stm32f0-stdperiph/stm32f0xx_dac.c | 692 + .../src/stm32f0-stdperiph/stm32f0xx_dbgmcu.c | 218 + system/src/stm32f0-stdperiph/stm32f0xx_dma.c | 891 ++ system/src/stm32f0-stdperiph/stm32f0xx_exti.c | 314 + .../src/stm32f0-stdperiph/stm32f0xx_flash.c | 1256 ++ system/src/stm32f0-stdperiph/stm32f0xx_gpio.c | 542 + system/src/stm32f0-stdperiph/stm32f0xx_i2c.c | 1585 ++ system/src/stm32f0-stdperiph/stm32f0xx_iwdg.c | 293 + system/src/stm32f0-stdperiph/stm32f0xx_misc.c | 167 + system/src/stm32f0-stdperiph/stm32f0xx_pwr.c | 566 + system/src/stm32f0-stdperiph/stm32f0xx_rcc.c | 1781 +++ system/src/stm32f0-stdperiph/stm32f0xx_rtc.c | 2518 +++ system/src/stm32f0-stdperiph/stm32f0xx_spi.c | 1334 ++ .../src/stm32f0-stdperiph/stm32f0xx_syscfg.c | 420 + system/src/stm32f0-stdperiph/stm32f0xx_tim.c | 3349 ++++ .../src/stm32f0-stdperiph/stm32f0xx_usart.c | 2168 +++ system/src/stm32f0-stdperiph/stm32f0xx_wwdg.c | 303 + 191 files changed, 94541 insertions(+) create mode 100644 Debug/bak/subdir.mk create mode 100644 Debug/makefile create mode 100644 Debug/objects.mk create mode 100644 Debug/sources.mk create mode 100644 Debug/src/subdir.mk create mode 100644 Debug/system/src/cmsis/subdir.mk create mode 100644 Debug/system/src/cortexm/subdir.mk create mode 100644 Debug/system/src/diag/subdir.mk create mode 100644 Debug/system/src/newlib/subdir.mk create mode 100644 Debug/system/src/stm32f0-stdperiph/subdir.mk create mode 100644 How to calculate your 8-digit grid square.pdf create mode 100755 Release/arm-gps_freqref-030.elf create mode 100644 Release/arm-gps_freqref-030.hex create mode 100644 Release/arm-gps_freqref-030.map create mode 100644 Release/makefile create mode 100644 Release/objects.mk create mode 100644 Release/sources.mk create mode 100644 Release/src/24aaxx.d create mode 100644 Release/src/24aaxx.o create mode 100644 Release/src/_write.d create mode 100644 Release/src/_write.o create mode 100644 Release/src/delay.d create mode 100644 Release/src/delay.o create mode 100644 Release/src/font_Arial.d create mode 100644 Release/src/font_Arial.o create mode 100644 Release/src/glcdfont.d create mode 100644 Release/src/glcdfont.o create mode 100644 Release/src/i2c.d create mode 100644 Release/src/i2c.o create mode 100644 Release/src/ili9341.d create mode 100644 Release/src/ili9341.o create mode 100644 Release/src/ili9341gfx.d create mode 100644 Release/src/ili9341gfx.o create mode 100644 Release/src/main.d create mode 100644 Release/src/main.o create mode 100644 Release/src/si5351a.d create mode 100644 Release/src/si5351a.o create mode 100644 Release/src/subdir.mk create mode 100644 Release/system/src/cmsis/subdir.mk create mode 100644 Release/system/src/cmsis/system_stm32f0xx.d create mode 100644 Release/system/src/cmsis/system_stm32f0xx.o create mode 100644 Release/system/src/cmsis/vectors_stm32f0xx.d create mode 100644 Release/system/src/cmsis/vectors_stm32f0xx.o create mode 100644 Release/system/src/cortexm/_initialize_hardware.d create mode 100644 Release/system/src/cortexm/_initialize_hardware.o create mode 100644 Release/system/src/cortexm/_reset_hardware.d create mode 100644 Release/system/src/cortexm/_reset_hardware.o create mode 100644 Release/system/src/cortexm/exception_handlers.d create mode 100644 Release/system/src/cortexm/exception_handlers.o create mode 100644 Release/system/src/cortexm/subdir.mk create mode 100644 Release/system/src/diag/Trace.d create mode 100644 Release/system/src/diag/Trace.o create mode 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Release/system/src/stm32f0-stdperiph/stm32f0xx_gpio.o create mode 100644 Release/system/src/stm32f0-stdperiph/stm32f0xx_rcc.d create mode 100644 Release/system/src/stm32f0-stdperiph/stm32f0xx_rcc.o create mode 100644 Release/system/src/stm32f0-stdperiph/subdir.mk create mode 100644 bak/ili9341.c create mode 100644 bak/ili9341.h create mode 100644 bak/ili9341gfx.c create mode 100644 bak/ili9341gfx.h create mode 100644 include/24aaxx.h create mode 100644 include/delay.h create mode 100644 include/font_Arial.h create mode 100644 include/font_courier.h create mode 100644 include/font_typedef.h create mode 100644 include/glcdfont.h create mode 100644 include/i2c.h create mode 100644 include/ili9341.h create mode 100644 include/ili9341gfx.h create mode 100644 include/si5351a.h create mode 100644 include/stm32f0xx_conf.h create mode 100644 ldscripts/libs.ld create mode 100644 ldscripts/mem.ld create mode 100644 ldscripts/sections.ld create mode 100644 maidenhead-calc.bas create mode 100644 src/.si5351a.c.swp create mode 100644 src/24aaxx.c create mode 100644 src/_write.c create mode 100644 src/delay.c create mode 100644 src/font_Arial.c create mode 100644 src/glcdfont.c create mode 100644 src/i2c.c create mode 100644 src/ili9341.c create mode 100644 src/ili9341gfx.c create mode 100644 src/main.c create mode 100644 src/main.c.bak create mode 100644 src/si5351a.c create mode 100644 src/timezone.c create mode 100644 system/include/arm/semihosting.h create mode 100644 system/include/cmsis/.stm32f0xx.h.swp create mode 100644 system/include/cmsis/README_DEVICE.txt create mode 100644 system/include/cmsis/arm_common_tables.h create mode 100644 system/include/cmsis/arm_const_structs.h create mode 100644 system/include/cmsis/arm_math.h create mode 100644 system/include/cmsis/cmsis_armcc.h create mode 100644 system/include/cmsis/cmsis_armcc_V6.h create mode 100644 system/include/cmsis/cmsis_device.h create mode 100644 system/include/cmsis/cmsis_gcc.h create mode 100644 system/include/cmsis/core_cm0.h create mode 100644 system/include/cmsis/core_cm0plus.h create mode 100644 system/include/cmsis/core_cm3.h create mode 100644 system/include/cmsis/core_cm4.h create mode 100644 system/include/cmsis/core_cm7.h create mode 100644 system/include/cmsis/core_cmFunc.h create mode 100644 system/include/cmsis/core_cmInstr.h create mode 100644 system/include/cmsis/core_cmSimd.h create mode 100644 system/include/cmsis/core_sc000.h create mode 100644 system/include/cmsis/core_sc300.h create mode 100644 system/include/cmsis/stm32f030xc.h create mode 100644 system/include/cmsis/stm32f0xx.h create mode 100644 system/include/cmsis/system_stm32f0xx.h create mode 100644 system/include/cortexm/ExceptionHandlers.h create mode 100644 system/include/diag/Trace.h create mode 100644 system/include/stm32f0-stdperiph/stm32f0xx_adc.h create mode 100644 system/include/stm32f0-stdperiph/stm32f0xx_can.h create mode 100644 system/include/stm32f0-stdperiph/stm32f0xx_cec.h create mode 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system/include/stm32f0-stdperiph/stm32f0xx_rtc.h create mode 100644 system/include/stm32f0-stdperiph/stm32f0xx_spi.h create mode 100644 system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h create mode 100644 system/include/stm32f0-stdperiph/stm32f0xx_tim.h create mode 100644 system/include/stm32f0-stdperiph/stm32f0xx_usart.h create mode 100644 system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h create mode 100644 system/src/cmsis/README_DEVICE.txt create mode 100644 system/src/cmsis/system_stm32f0xx.c create mode 100644 system/src/cmsis/vectors_stm32f0xx.c create mode 100644 system/src/cortexm/_initialize_hardware.c create mode 100644 system/src/cortexm/_reset_hardware.c create mode 100644 system/src/cortexm/exception_handlers.c create mode 100644 system/src/diag/Trace.c create mode 100644 system/src/diag/trace_impl.c create mode 100644 system/src/newlib/README.txt create mode 100644 system/src/newlib/_cxx.cpp create mode 100644 system/src/newlib/_exit.c create mode 100644 system/src/newlib/_sbrk.c create mode 100644 system/src/newlib/_startup.c create mode 100644 system/src/newlib/_syscalls.c create mode 100644 system/src/newlib/assert.c create mode 100644 system/src/stm32f0-stdperiph/stm32f0xx_adc.c create mode 100644 system/src/stm32f0-stdperiph/stm32f0xx_can.c create mode 100644 system/src/stm32f0-stdperiph/stm32f0xx_cec.c create mode 100644 system/src/stm32f0-stdperiph/stm32f0xx_comp.c create mode 100644 system/src/stm32f0-stdperiph/stm32f0xx_crc.c create mode 100644 system/src/stm32f0-stdperiph/stm32f0xx_crs.c create mode 100644 system/src/stm32f0-stdperiph/stm32f0xx_dac.c create mode 100644 system/src/stm32f0-stdperiph/stm32f0xx_dbgmcu.c create mode 100644 system/src/stm32f0-stdperiph/stm32f0xx_dma.c create mode 100644 system/src/stm32f0-stdperiph/stm32f0xx_exti.c create mode 100644 system/src/stm32f0-stdperiph/stm32f0xx_flash.c create mode 100644 system/src/stm32f0-stdperiph/stm32f0xx_gpio.c create mode 100644 system/src/stm32f0-stdperiph/stm32f0xx_i2c.c create mode 100644 system/src/stm32f0-stdperiph/stm32f0xx_iwdg.c create mode 100644 system/src/stm32f0-stdperiph/stm32f0xx_misc.c create mode 100644 system/src/stm32f0-stdperiph/stm32f0xx_pwr.c create mode 100644 system/src/stm32f0-stdperiph/stm32f0xx_rcc.c create mode 100644 system/src/stm32f0-stdperiph/stm32f0xx_rtc.c create mode 100644 system/src/stm32f0-stdperiph/stm32f0xx_spi.c create mode 100644 system/src/stm32f0-stdperiph/stm32f0xx_syscfg.c create mode 100644 system/src/stm32f0-stdperiph/stm32f0xx_tim.c create mode 100644 system/src/stm32f0-stdperiph/stm32f0xx_usart.c create mode 100644 system/src/stm32f0-stdperiph/stm32f0xx_wwdg.c diff --git a/Debug/bak/subdir.mk b/Debug/bak/subdir.mk new file mode 100644 index 0000000..26b86b0 --- /dev/null +++ b/Debug/bak/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../bak/ili9341.c \ +../bak/ili9341gfx.c + +OBJS += \ +./bak/ili9341.o \ +./bak/ili9341gfx.o + +C_DEPS += \ +./bak/ili9341.d \ +./bak/ili9341gfx.d + + +# Each subdirectory must supply rules for building sources it contributes +bak/%.o: ../bak/%.c bak/subdir.mk + @echo 'Building file: $<' + @echo 'Invoking: GNU Arm Cross C Compiler' + echo -mcpu=cortex-m3 -mthumb -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -g3 -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/Debug/makefile b/Debug/makefile new file mode 100644 index 0000000..0986ca6 --- /dev/null +++ b/Debug/makefile @@ -0,0 +1,101 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +-include ../makefile.init + +RM := -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include system/src/stm32f0-stdperiph/subdir.mk +-include system/src/newlib/subdir.mk +-include system/src/diag/subdir.mk +-include system/src/cortexm/subdir.mk +-include system/src/cmsis/subdir.mk +-include src/subdir.mk +-include bak/subdir.mk +-include subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(ASM_DEPS)),) +-include $(ASM_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +endif + +-include ../makefile.defs + +OPTIONAL_TOOL_DEPS := \ +$(wildcard ../makefile.defs) \ +$(wildcard ../makefile.init) \ +$(wildcard ../makefile.targets) \ + + +BUILD_ARTIFACT_NAME := arm-gps_freqref-030 +BUILD_ARTIFACT_EXTENSION := elf +BUILD_ARTIFACT_PREFIX := +BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),) + +# Add inputs and outputs from these tool invocations to the build variables +SECONDARY_FLASH += \ +arm-gps_freqref-030.hex \ + +SECONDARY_SIZE += \ +arm-gps_freqref-030.siz \ + + +# All Target +all: arm-gps_freqref-030.elf secondary-outputs + +# Tool invocations +arm-gps_freqref-030.elf: $(OBJS) $(USER_OBJS) makefile objects.mk $(OPTIONAL_TOOL_DEPS) + @echo 'Building target: $@' + @echo 'Invoking: GNU Arm Cross C++ Linker' + echo -mcpu=cortex-m3 -mthumb -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -g3 -Xlinker --gc-sections -Wl,-Map,"arm-gps_freqref-030.map" -o "arm-gps_freqref-030.elf" $(OBJS) $(USER_OBJS) $(LIBS) + @echo 'Finished building target: $@' + @echo ' ' + +arm-gps_freqref-030.hex: arm-gps_freqref-030.elf makefile objects.mk $(OPTIONAL_TOOL_DEPS) + @echo 'Invoking: GNU Arm Cross Create Flash Image' + -O ihex "arm-gps_freqref-030.elf" "arm-gps_freqref-030.hex" + @echo 'Finished building: $@' + @echo ' ' + +arm-gps_freqref-030.siz: arm-gps_freqref-030.elf makefile objects.mk $(OPTIONAL_TOOL_DEPS) + @echo 'Invoking: GNU Arm Cross Print Size' + --format=berkeley "arm-gps_freqref-030.elf" + @echo 'Finished building: $@' + @echo ' ' + +# Other Targets +clean: + -$(RM) $(CC_DEPS)$(C++_DEPS)$(OBJS)$(C_UPPER_DEPS)$(CXX_DEPS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS) arm-gps_freqref-030.elf + -@echo ' ' + +secondary-outputs: $(SECONDARY_FLASH) $(SECONDARY_SIZE) + +.PHONY: all clean dependents + +-include ../makefile.targets diff --git a/Debug/objects.mk b/Debug/objects.mk new file mode 100644 index 0000000..742c2da --- /dev/null +++ b/Debug/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/Debug/sources.mk b/Debug/sources.mk new file mode 100644 index 0000000..eca1e17 --- /dev/null +++ b/Debug/sources.mk @@ -0,0 +1,37 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +ELF_SRCS := +C_UPPER_SRCS := +CXX_SRCS := +C++_SRCS := +OBJ_SRCS := +CC_SRCS := +ASM_SRCS := +C_SRCS := +CPP_SRCS := +S_UPPER_SRCS := +O_SRCS := +CC_DEPS := +C++_DEPS := +OBJS := +C_UPPER_DEPS := +CXX_DEPS := +SECONDARY_FLASH := +SECONDARY_SIZE := +ASM_DEPS := +S_UPPER_DEPS := +C_DEPS := +CPP_DEPS := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +bak \ +src \ +system/src/cmsis \ +system/src/cortexm \ +system/src/diag \ +system/src/newlib \ +system/src/stm32f0-stdperiph \ + diff --git a/Debug/src/subdir.mk b/Debug/src/subdir.mk new file mode 100644 index 0000000..020d037 --- /dev/null +++ b/Debug/src/subdir.mk @@ -0,0 +1,54 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../src/_write.c \ +../src/delay.c \ +../src/font_Arial.c \ +../src/glcdfont.c \ +../src/i2c.c \ +../src/ili9341.c \ +../src/ili9341gfx.c \ +../src/main.c \ +../src/mcp24aaxx.c \ +../src/si5351a.c \ +../src/timezone.c + +OBJS += \ +./src/_write.o \ +./src/delay.o \ +./src/font_Arial.o \ +./src/glcdfont.o \ +./src/i2c.o \ +./src/ili9341.o \ +./src/ili9341gfx.o \ +./src/main.o \ +./src/mcp24aaxx.o \ +./src/si5351a.o \ +./src/timezone.o + +C_DEPS += \ +./src/_write.d \ +./src/delay.d \ +./src/font_Arial.d \ +./src/glcdfont.d \ +./src/i2c.d \ +./src/ili9341.d \ +./src/ili9341gfx.d \ +./src/main.d \ +./src/mcp24aaxx.d \ +./src/si5351a.d \ +./src/timezone.d + + +# Each subdirectory must supply rules for building sources it contributes +src/%.o: ../src/%.c src/subdir.mk + @echo 'Building file: $<' + @echo 'Invoking: GNU Arm Cross C Compiler' + echo -mcpu=cortex-m3 -mthumb -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -g3 -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/Debug/system/src/cmsis/subdir.mk b/Debug/system/src/cmsis/subdir.mk new file mode 100644 index 0000000..d164e85 --- /dev/null +++ b/Debug/system/src/cmsis/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../system/src/cmsis/system_stm32f0xx.c \ +../system/src/cmsis/vectors_stm32f0xx.c + +OBJS += \ +./system/src/cmsis/system_stm32f0xx.o \ +./system/src/cmsis/vectors_stm32f0xx.o + +C_DEPS += \ +./system/src/cmsis/system_stm32f0xx.d \ +./system/src/cmsis/vectors_stm32f0xx.d + + +# Each subdirectory must supply rules for building sources it contributes +system/src/cmsis/%.o: ../system/src/cmsis/%.c system/src/cmsis/subdir.mk + @echo 'Building file: $<' + @echo 'Invoking: GNU Arm Cross C Compiler' + echo -mcpu=cortex-m3 -mthumb -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -g3 -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/Debug/system/src/cortexm/subdir.mk b/Debug/system/src/cortexm/subdir.mk new file mode 100644 index 0000000..d2b035a --- /dev/null +++ b/Debug/system/src/cortexm/subdir.mk @@ -0,0 +1,30 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../system/src/cortexm/_initialize_hardware.c \ +../system/src/cortexm/_reset_hardware.c \ +../system/src/cortexm/exception_handlers.c + +OBJS += \ +./system/src/cortexm/_initialize_hardware.o \ +./system/src/cortexm/_reset_hardware.o \ +./system/src/cortexm/exception_handlers.o + +C_DEPS += \ +./system/src/cortexm/_initialize_hardware.d \ +./system/src/cortexm/_reset_hardware.d \ +./system/src/cortexm/exception_handlers.d + + +# Each subdirectory must supply rules for building sources it contributes +system/src/cortexm/%.o: ../system/src/cortexm/%.c system/src/cortexm/subdir.mk + @echo 'Building file: $<' + @echo 'Invoking: GNU Arm Cross C Compiler' + echo -mcpu=cortex-m3 -mthumb -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -g3 -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/Debug/system/src/diag/subdir.mk b/Debug/system/src/diag/subdir.mk new file mode 100644 index 0000000..ef9df48 --- /dev/null +++ b/Debug/system/src/diag/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../system/src/diag/Trace.c \ +../system/src/diag/trace_impl.c + +OBJS += \ +./system/src/diag/Trace.o \ +./system/src/diag/trace_impl.o + +C_DEPS += \ +./system/src/diag/Trace.d \ +./system/src/diag/trace_impl.d + + +# Each subdirectory must supply rules for building sources it contributes +system/src/diag/%.o: ../system/src/diag/%.c system/src/diag/subdir.mk + @echo 'Building file: $<' + @echo 'Invoking: GNU Arm Cross C Compiler' + echo -mcpu=cortex-m3 -mthumb -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -g3 -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/Debug/system/src/newlib/subdir.mk b/Debug/system/src/newlib/subdir.mk new file mode 100644 index 0000000..ebba29e --- /dev/null +++ b/Debug/system/src/newlib/subdir.mk @@ -0,0 +1,50 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../system/src/newlib/_exit.c \ +../system/src/newlib/_sbrk.c \ +../system/src/newlib/_startup.c \ +../system/src/newlib/_syscalls.c \ +../system/src/newlib/assert.c + +CPP_SRCS += \ +../system/src/newlib/_cxx.cpp + +OBJS += \ +./system/src/newlib/_cxx.o \ +./system/src/newlib/_exit.o \ +./system/src/newlib/_sbrk.o \ +./system/src/newlib/_startup.o \ +./system/src/newlib/_syscalls.o \ +./system/src/newlib/assert.o + +C_DEPS += \ +./system/src/newlib/_exit.d \ +./system/src/newlib/_sbrk.d \ +./system/src/newlib/_startup.d \ +./system/src/newlib/_syscalls.d \ +./system/src/newlib/assert.d + +CPP_DEPS += \ +./system/src/newlib/_cxx.d + + +# Each subdirectory must supply rules for building sources it contributes +system/src/newlib/%.o: ../system/src/newlib/%.cpp system/src/newlib/subdir.mk + @echo 'Building file: $<' + @echo 'Invoking: GNU Arm Cross C++ Compiler' + echo -mcpu=cortex-m3 -mthumb -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -g3 -std=gnu++11 -fabi-version=0 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + +system/src/newlib/%.o: ../system/src/newlib/%.c system/src/newlib/subdir.mk + @echo 'Building file: $<' + @echo 'Invoking: GNU Arm Cross C Compiler' + echo -mcpu=cortex-m3 -mthumb -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -g3 -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/Debug/system/src/stm32f0-stdperiph/subdir.mk b/Debug/system/src/stm32f0-stdperiph/subdir.mk new file mode 100644 index 0000000..9e61d0b --- /dev/null +++ b/Debug/system/src/stm32f0-stdperiph/subdir.mk @@ -0,0 +1,90 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../system/src/stm32f0-stdperiph/stm32f0xx_adc.c \ +../system/src/stm32f0-stdperiph/stm32f0xx_can.c \ +../system/src/stm32f0-stdperiph/stm32f0xx_cec.c \ +../system/src/stm32f0-stdperiph/stm32f0xx_comp.c \ +../system/src/stm32f0-stdperiph/stm32f0xx_crc.c \ +../system/src/stm32f0-stdperiph/stm32f0xx_crs.c \ +../system/src/stm32f0-stdperiph/stm32f0xx_dac.c \ +../system/src/stm32f0-stdperiph/stm32f0xx_dbgmcu.c \ +../system/src/stm32f0-stdperiph/stm32f0xx_dma.c \ +../system/src/stm32f0-stdperiph/stm32f0xx_exti.c \ +../system/src/stm32f0-stdperiph/stm32f0xx_flash.c \ +../system/src/stm32f0-stdperiph/stm32f0xx_gpio.c \ +../system/src/stm32f0-stdperiph/stm32f0xx_i2c.c \ +../system/src/stm32f0-stdperiph/stm32f0xx_iwdg.c \ +../system/src/stm32f0-stdperiph/stm32f0xx_misc.c \ +../system/src/stm32f0-stdperiph/stm32f0xx_pwr.c \ +../system/src/stm32f0-stdperiph/stm32f0xx_rcc.c \ +../system/src/stm32f0-stdperiph/stm32f0xx_rtc.c \ +../system/src/stm32f0-stdperiph/stm32f0xx_spi.c \ +../system/src/stm32f0-stdperiph/stm32f0xx_syscfg.c \ +../system/src/stm32f0-stdperiph/stm32f0xx_tim.c \ +../system/src/stm32f0-stdperiph/stm32f0xx_usart.c \ +../system/src/stm32f0-stdperiph/stm32f0xx_wwdg.c + +OBJS += \ +./system/src/stm32f0-stdperiph/stm32f0xx_adc.o \ +./system/src/stm32f0-stdperiph/stm32f0xx_can.o \ +./system/src/stm32f0-stdperiph/stm32f0xx_cec.o \ +./system/src/stm32f0-stdperiph/stm32f0xx_comp.o \ +./system/src/stm32f0-stdperiph/stm32f0xx_crc.o \ +./system/src/stm32f0-stdperiph/stm32f0xx_crs.o \ +./system/src/stm32f0-stdperiph/stm32f0xx_dac.o \ +./system/src/stm32f0-stdperiph/stm32f0xx_dbgmcu.o \ +./system/src/stm32f0-stdperiph/stm32f0xx_dma.o \ +./system/src/stm32f0-stdperiph/stm32f0xx_exti.o \ +./system/src/stm32f0-stdperiph/stm32f0xx_flash.o \ +./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o \ +./system/src/stm32f0-stdperiph/stm32f0xx_i2c.o \ +./system/src/stm32f0-stdperiph/stm32f0xx_iwdg.o \ +./system/src/stm32f0-stdperiph/stm32f0xx_misc.o \ +./system/src/stm32f0-stdperiph/stm32f0xx_pwr.o \ +./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o \ +./system/src/stm32f0-stdperiph/stm32f0xx_rtc.o \ +./system/src/stm32f0-stdperiph/stm32f0xx_spi.o \ +./system/src/stm32f0-stdperiph/stm32f0xx_syscfg.o \ +./system/src/stm32f0-stdperiph/stm32f0xx_tim.o \ +./system/src/stm32f0-stdperiph/stm32f0xx_usart.o \ +./system/src/stm32f0-stdperiph/stm32f0xx_wwdg.o + +C_DEPS += \ +./system/src/stm32f0-stdperiph/stm32f0xx_adc.d \ +./system/src/stm32f0-stdperiph/stm32f0xx_can.d \ +./system/src/stm32f0-stdperiph/stm32f0xx_cec.d \ +./system/src/stm32f0-stdperiph/stm32f0xx_comp.d \ +./system/src/stm32f0-stdperiph/stm32f0xx_crc.d \ +./system/src/stm32f0-stdperiph/stm32f0xx_crs.d \ +./system/src/stm32f0-stdperiph/stm32f0xx_dac.d \ +./system/src/stm32f0-stdperiph/stm32f0xx_dbgmcu.d \ +./system/src/stm32f0-stdperiph/stm32f0xx_dma.d \ +./system/src/stm32f0-stdperiph/stm32f0xx_exti.d \ +./system/src/stm32f0-stdperiph/stm32f0xx_flash.d \ +./system/src/stm32f0-stdperiph/stm32f0xx_gpio.d \ +./system/src/stm32f0-stdperiph/stm32f0xx_i2c.d \ +./system/src/stm32f0-stdperiph/stm32f0xx_iwdg.d \ +./system/src/stm32f0-stdperiph/stm32f0xx_misc.d \ +./system/src/stm32f0-stdperiph/stm32f0xx_pwr.d \ +./system/src/stm32f0-stdperiph/stm32f0xx_rcc.d \ +./system/src/stm32f0-stdperiph/stm32f0xx_rtc.d \ +./system/src/stm32f0-stdperiph/stm32f0xx_spi.d \ +./system/src/stm32f0-stdperiph/stm32f0xx_syscfg.d \ +./system/src/stm32f0-stdperiph/stm32f0xx_tim.d \ +./system/src/stm32f0-stdperiph/stm32f0xx_usart.d \ +./system/src/stm32f0-stdperiph/stm32f0xx_wwdg.d + + +# Each subdirectory must supply rules for building sources it contributes +system/src/stm32f0-stdperiph/%.o: ../system/src/stm32f0-stdperiph/%.c system/src/stm32f0-stdperiph/subdir.mk + @echo 'Building file: $<' + @echo 'Invoking: GNU Arm Cross C Compiler' + echo -mcpu=cortex-m3 -mthumb -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -g3 -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/How to calculate your 8-digit grid square.pdf b/How to calculate your 8-digit grid square.pdf new file mode 100644 index 0000000000000000000000000000000000000000..6124e2686da6241f1fed8e5b0419151ae54f406c GIT binary patch literal 77957 zcmce-1yo$iv+#>U2G^iL0t6r2-Q9x*XK)|fonXN|xN8U=T!Xv2TYx}-;PQZ+bN=VM z_r34CZ@snNS~IivuI{ScyX#lAYc&mpqNq4M69Wr?qW3T=2f#+cNMdVf0pR5Y%7Sc6 z9nDDCpCrmaadRt2kOK)&+{(ZaBnmRJH3sqX1Hg_BAOmZF>*wVUno&eO*onUwO>ppr z1i$-s7+J09>Zew;&JF?YFD--N`Q*DW$}Z9{9F;e7BaZSHF8F_2iGpJ2PFO^&U^orZa8t z0xrT*`ngIgY#zM0Z)uHA5uCSo%uzOn=_osfr-w%iSFLTVzw~Scf<4a`)a0aT$~o%m zXCoBU7{78Yoc7~Z^z1nKfK$tTCZf)hWcNdcZhIb;5YBS9e zl{Z!u>a3JgS?ABi5 zyvAeqf>)DJ**OEh&CC3e$>AeIXOi(1#lFFyvQC$^0U7B+VfoH+pxgNKv^s~6K+E-A z(=gAXB^Px^3IOpcPWmY2!FkSa-Q-hK#(itqS^esAqZIzW6gs;RrAZBf@j9lu__WJ$ ze!oertO>i1Ab8ykSpT40saZ69@9C_NcUd<(UfiT#hTn;j08|5&d!>GHmtz6#2G z;mtHy`2GkF)rNCP01g#+%_A!Kb-*zvs`cr1`ip2A}CdIQd1mtiim~9BKiy zRoBMVmPk%pndUYxwGiM;erOEqy2NP_jl-U}avIk;pL)dx$7M z3F9m0_!7P!hi96Jmb+689i4RS+s?e@TASao~QL1*xRSPC@9$ZIFDUXj=^hW#@= zhK*=9GurpxR+ZSO`o;zA5lunul0P*qIdgZtd_0ccFWTqxYB024>C@gz79flJp$g&s zLL%-k%Edz~z)WUcbN1QLLi3wFVaWje-CG|h6+&uq>I>IUBWXMobo+DMIl2X; zqlMWn`R!j$v2p{izzGGbGCydqv5fMl_+JsuAKoV=84H=i!y`9noToW*(m=e8HXKDJ zCtJ>L$3C`$q0L|v-(%BwrSa8*(9x|Arz7enLw)zbdp-lx0u~PA(E^K;Qs-z8#S#h* z%b#1~D{I7DaaK~iN}3VC8n-c29EJ7H@KrgL?6hpGsDQ0VNNT?1<0y$RzV9o1PbgDd ztJmxz7BtpnjBx4WvGZrr>QxGs#5g(>m!9)0vA>zw6SRfBuXEuxYeyniDWUjE+52 zwl#G_^ulEFu$A;Lmw0;R(U+qo5klG&(Y{S6ZPy8fF6!aVg(!Xb_y? zqfm2Ior7jlViQRw`c6=O=kC}?KZHo$*gDOAz$ajam$C4R*g9rNjl8G~gZdb4-+sN} zheTe$%ZibFNL~XKa505|B;kCD!C?EzPqfUdPa;?`{| zryn}NV?OPTBd&Y69m9g?n+@FbXblY5_cRpdfQSTlGM|8M-%EXXX-8H$%UD?JI zjzy8Jjv|Z4FeL=3j!$DtU7UXBThn7dIMJfJ;H5Z=3l~@&3bGez0`#Rklaw@ z!V`>@n#d)8J9KwOJI9^t$GU!3Yy zECcIqEtWuaF@6;Xdynn9xwrBV&-JohBX1J=bwz!BI1jtFC95Bk!QopBx4vYqWmRER zFG#X0QQx2(C-kYi+u@DZUTs0|1VRRZsb(U>{8{s!ub?Z;wNw}N^buK^pg*HS2-NJ1 z7o?UsjCYWyGnL8O`=ho=Np1ZA#srK*n2ltas)A)=NWXig)S+Y6tyPwdC*mEW8j2H2 zejuA$$!yGxH$Xu;lcW5$6q09@I~RzrK!TgCa=S)Ho^MEr!5v^=s71uke0aJf${$!D ztjH`Gr}VpQBpcBpRJBPO`(k>FH6}S_B_>v*V$ed*nk&RolS5mx%3=y&@T*sJu01gyBQ~+$#~+w zyH_MY4uo}WuK*CAud+JP8~@VNILE)Hor}{G?sG&jkItq+XI>0&v})fz9ojO89)h5_fy*# zRs`vGLw=SkG8ii4x6YpW5r7F)-h1Vi({2q9ZaWcEOA4uB+P<6O=m z114I=vJ=$tGEE~)$SBwZFqUk3LY8QN&H&krI0|s)Zx1~gzK8sLE0tG2p!UA$YzgvR z3tz36DSGWyR)xX^%K3OgMVL+&;=xSvgl`RgH2*KqrRt`&YG5SsQ!GBcDrW z=4u@G6k8BO!yV;SroT5@AeMiDgy%lzCT((kZ9R zK<&IBk^eR~-Hn;~^;{@Sq?EP2X6p%^m=31I5uMzuLAJe?OqCtq9(UN}D}#AoWL2%` zI-^KuQ_4tg^(JPfAG+Wi=suOPJ5V@8-IjFh<1XJ<+gy#H5bQg#ueTOfW5bMFUx};p=lAk zn27ZB{cWMHk|*NL69#AKJrk@x_J*uOy0}-v=IRIDW)VI*&gX>P!y!IY;rslPH5|nU zwmIp0?@y+wtdz}ypm*!CQ%GAh*R(yF=N}T!C=+&v2F~B8(BwA@y_YU24=RzWLMV2? zvY^w(iU3zmp)xK@uB+nVZkO_cjV-!ACw zjuv%rV579=yeuXygTMM4V4UqglRzL|2YH>A_uzMB{jDnPQ`Jt$Az?K!UQxWt0;Lh#)N zLI&cvA3uC>Q?PgVT&TboXl;J%7_9DUqmCKLPt_iDX=?iTr8e%f+qGffB}qcGXtmWO zJD?Gh-fwE$vzH`TiVL>j{9Z0HN&59I-0}W7cI3@A!4_hj>u`{=&DlAZS4v@?7XQ(d zLj_;On|FP8#>;c#Vted>{?gooUq>I1Ch38Jz5BbHJ#_Oc&5XkZZRP<9B$PT1OfH}n z?x~f<`qkKn74Ch4kb7#`uj1|vU%}t>1Wz1zNt43yXJ*(3kMSu zCCa}1<>dDFqp3b3mzxh;P?B_o?|{?v*(Jx1cAM>d1lF-x&})-7B+ zb$q-g3>R}IAKmkQ;B$uzxz|+HB@g*r98QBs!ND4yCrPgJfYjAeeaM^N`?J+3fK$gy z2R+46MS@ouKiK3lT~KGOGhN(&%D5A^Q22?fP2-kKEqtfUK5}Pz*k%oksdYcC)hA~! zxs{G_3ZKpNzx1MBsKu+_CRW`x&F659Uw-`wk2%r8V;4vVom`9q1M@xc zeEQyz`oRlNF*bep<+iE|b~8KwlGbaCP_hH{g^BdJdRu

EFY>6K21aQ1yRh*?JqW zEm>=UG-#?+Y`ay0j((5!U4aiY`Vemoon5*v#45@U%xwhr>mEudl{01iItocYx*VZ; zPPX+FrXN9Jkx$i}ODI{@UK%7=Y^wX5Zqrx^y>mYNc)%{j+D-8=MZ|JnNNxctCv2=e zmVj;P3g{o@C0d!ccdeI`I7_feqoWOBT|69e#-L|cm5`WaIc+8)LXh@8OTq^9WT$U( zm)0SyBGNaOOSu(*e8%P=Z$oOyAvBwW>wNXO`jJR&)=AKEQ!S3t({V_pG2vCbFhgQR zQ6;8%SkA*Nwvn)$BiD~~6wBco#@U@kds)|cXU{MM9=CVSi64$1AzVW(i9j~Sf2}w? zojtEoJg-eWA6c0h83BLEm^l915(X3J|6~p0NL$-hrw3cj5R>N}x&^*jL<5oJ!cWZI z!;$+5npY&Gd0|O8XFKPwRLS#5gdW?b*pm3FcdDZ5iQ>LP#Ecp9dYBA1dRflw-qldP z1zB!9$OhQzRXkio>iRscCS>aRoV_Q!ySx8Un1J`~c2r^QS3Pi6?{G~-dM5tU%);-V z0<=)j-TvXwsOHK%!#j0UFuZ=-pNdh-H|k+XK}CA+q8y7!a_Ckm25Y$G zXcw!xM}GfQzm%uP0Bc5rTW6)OL-cDA%Sp`vF^4u|TfCtw$5lwBl`GnXYTfkb8GmFT z`*q&veKdOIJhH8$sU+RHn-Pksp7A}fMS<_a#_%Jx>6bpa4ZH7h{6lp;KYTXSF-yIt zY3iqv4KLjEq_`MRWWLn-D+hhJr?NbAUMZ2pL<>`;mESC2fGCvoM{2OP`Z+wl(9CRZ z3GQRFhujo>ge&VKC-)JDros(;6&4}ReFqji$%gg^uue%*6;hT_VV@gHs=1F1`@6&) zRli;fbep>W;f(UZ6Q8c2GIjWiYh6qr`4S667fw5GE^j2`C~k4OpTE zdXc0hYD+KzbG3q^`K-i+cCj=_h5|L&SmE#a_ji|kw#->QGot3$t34cSAcwiC$w4c} z>rOEYIQn2MjJmNQ*}cPoQog;iZ>gTk#V(}0(5iO!!_`B&Np@hW2G%>-Hw_0l_BP5_=FiAMD%8x(wpexUq{6CEi+5Rf53lEP5Nh&#@?X<0 zN#&HT>4?IedflVzVerKhk-hS@WsI-;IxLZ*ErP90*~m@nm)=rT3R}GVDs6VxrN6AgMN#tQB=)CM16X7EAWc-{;u-UP~pq@oQt3rg3Ez`+jTaYB1Qs~3uXb)`I))va_7Nm zQHXKh`lqIqv9p%NX{l~B`gQN)?E(oEGu-4MRBP4rE#p9)n=JKeEH_JxlZMKk^ZR$p z^EMQY9}eU&EdWm0xAM%5`vn6C#NX}MQ#bK{a9w<)xxeAw(DbQKKE&gQ6V)FeL0eaB z$-t`O`eF#Bro;_O^&IzD=?G%X;pFT)xOd+f4k|!5yVNsG&t^a@z=^Ao9i~KeYu%aT z^q5N0kL?$an!;C{3z!i63LhYwtS|uRF|npK-4aXSSxQ~t+nYkeSg?aaBq7J`4m5GR z>VnfHfgqnowC0&dH0`YJ4;QTaglW&N(;9e^l6tR6{7P$fAgi6qwO{Js(k6%l&Il8$ z-7-L4cPmc&K&-gctW@v=zj}}{o%onl!$)5$tq*yNo}PvBOeRqh-x_=i!AD9H7#&}& zweRRLX;WJo2(mpt-%*+PA=E$^Q;Y?>azyL)d}szkIgx!bX$F28OzTU9Z%LwkIPspq zYE&8-rIL=3J~78rM`2HwH(&Xo)_Sv?abf9dXCi*$tBj=Vy0R}nD=XJJ4pKqe4Hs8m zss{|Bp;C4#+*Jp*h*D6KR4&Ro*+93_Hk*LTXM&F5ZWrp$g%oIAnZh!gvr5hUk`+#PjGB z83qu}7^Y9Y7A})hv;XMsLl+QBq9y>fLNCV*VZ^Mv?xoE``+k;LDHruDZJYJ|6loWW zm~u!H8N}es#=#b=Qnrq9vZ^)=C1zdACs7lnrK$3-;Z@k@AIK($!AyHriK%^bX<|v{ zi8qzs%oIOQ(jmuOki%ykCp69gn|6?M?jv(k)zhdyC2@y=D+d)*Zbxh~U8bo$f=^CN ze{g`>ITCP}o#Ozp7sta;uY=c}e)BMeeN<|XtMj3iFe%1LI$Wg;*UjpvS>Vo_eOe(YWtzZd711)cv`WPr7pD77*wl&!*D*AY}u^JJ8h^;qWsqNBbZn?qk;nVNd@7$1aZ>JDpvRkZfarqm{F` zW(Z_~-(Gm; zlq+l2Wv_x7!X-UZ*btJ5;<=y`-h_RL@mngwx;Q%M$n15G6S#)di69F=dvpAy*KHF_ zJayHK!$|}=VW;(81&e-oc5ia{e#TIQ-%i{E#A@NzR7%u4LB$f<$FbzET`Z=B_JIvq zy6mtsVRwudwQXbMcVC)yfqy;GwsZ=(#5oz&yeFsZ@V?F(^JaMpa9Vzt@&U990NS?t6oE* zH6xiFW-ix8+yVye`d^W@SBREAxwR+5Zm~|iUA-p#^TuS%H)FW-MCI&SIH7zQKFng?XazD#-Fhp9_ zL%b%4^keAOD$yiE^9fOe0L97@cf0qD!}HO!ooq;LrbsLWHzX-u?(Qrh<<9-S3$8Bf z@9<2VBY%^}pG}1UWx8K1X|QvZ0yE`wSpWIAvi}a?pNiK3bO;j zsGCcjUT>6|H6j#RW1A{_sc%40<}>^B>Cqj?t3XpS2gbC7e~}J%`~!<-=F`$y1m)N5RM2 zy3KuEoWcm2X@^xeY%WE|%6lwfzv=S30!p35!|~p7F&k`FtwEjG&AR1l`aUMa z{{D?iBEIJ?pp~E;$uO#DqT?k{k)K!Y1CaYp6@tzW)lB>A&1`MQ0DR)DmL83nMumYwCey@=pfsu$+*oXB=v55rprFs~9GjijFcR z>?T7Jn+vDtvwzyt8&gUrac=uq($s&+1z?1*eQl~Ul+jh%p%0gPef}}GKq;P5zBUj5 z??8enV40E$h75Mi&nFW<>AUklrufW7nZEj#BUqy&3?@Fu`SXg=BW5;%FS?(1#)1j)+So@yq|w}^q0o+ z?OJjfzpOO*i+L!TGz;ao zf<6l2MtC(}2}-MrL+3B{b$N&5OFP1T_O38BiyeWb7;lpLZ{&cfm2HSC*mOj;@g~8Q19wE%Zkvz946xZ@PIzfVDbu|+ z?{sV;W@am*8z!T$a~WR|2&uY7(?AS3X)VOHGyb2)^r$SF!SCLzmaK{+FyS3rdB~8Y?tWl$Q8Y<0@#(Fl@m&rS7 zmb=JM(?8cs!MNm}U{vd7xKxi6qVW-&4g24KsaG$e2LqiTRK=u@=nlx8?)!Q-Hn;Dt zmmppVDywB_Q$YF+1Zr70tiZv@ya4YGVuGs2;32zWz{Xu)Dd zBX8T5_tnT-Ds3g?F?J_J#@zShgX-{J8eT!g9FFWF41=yZ|A5rT?jE6^VmoNgHFQG| zl+4a+G|X{*u8F;V%Ao2bOiYzG?AqOQytqUgrUFp`?Arx*=~QLCL2)RneQE=)R`q#p zET_5e+XjT9-VA&H(tL{>ROb5m`j?EV7w^6ogxqpc^|t_DAU?*uRPIMd*#T_#sY^K} z(LOfh4skgevDvW6#c!>TGkTCP7>@!DELxyzLve@6C^1CB9CK^2A~PNhMrb8)3*;wq z8mcya1PBcgO%2Ef#fBScF*MHckfVLac;!x5sn4J2=@1@2teu;8K|vS4O1PoaC#9kC z)ny;&rTak>2tl)n`MMMXBBT(9x8uA|JH~Qc)X2_8#()TSq{`~c-esUknsS| z+sc@qMS)Xoope_%)!zp{Jl;S#_1X?Y`48FWZ=4l5RbAFYY};Ov-1QcdvhFdd*b}!T zT2rwF7Kq{ocR8JXBPE1pMI$D*l^Q3gRuV=Mm@bo;NAJ3nY`Q=CSe^Sjl;GP$vTu$d zA&ueyCQ54hZ5!4i)&_KJ6DG0jh#r9iQ~XTpcA;UR0T$@23m^irYS^Gd=GjQU*M25CV!k zT|Zd_ll&w4dztRt6$8et!J_GQgL0!x!0KBV=ZJ>hwIV|38h8`QKB> z{Lg&-X9{16+JBGm*-d{2_~el%CzHH*8B79{F*gR2XaoKjWO~`b1$cQJWq=OJlR>9v zAOFYgPmcQAEB{#h%bED+BfbpOH|5|H(apFHf0DuaLawJUr{C^w%7mvyu zfM-4B|Co6J=C7$%<^=p%u2p7Y1Teig3aHG)40wX|f7N+*=-)d3&EkuP|8D&sT6}T9 z-#Y)@;=i`W{ZGgE{2+fB6gB{Zo`VA@t1PD?rcA49ZVdvfi)=X6!%Iyma_$djHV(mn!givj4X8G(9##HemCAu0_pF zOh8X*?kTTn1DJr4KwF>-5Nu~)1Ohq&jerI~E1(k)1at#}%uUT4fo5)YW*{4&G0+@n z3II9)!9aVUEKm_>WNU400F(#X+JJy6KsBJKKwA1t43Jb#}t zd_k4{PbmDi^QXTZv2s4)|MYzsD=X8>7@nW!S@&7?Z0E`Tzwu=GlbZgY@qFp<{~6Ce zV5$Pmo{*G#g46toM4Kl7ZJ$tee8N!$=mvOV()tM=(7Wy2xwyN{Pgo2 zD~1kF;rC+U1EILRNk<2aOga5CpQI?umgZX zV58^4^GWzrGaA@QzCifr^7&TJZO@tj;2*yU*_c{A)vExYiX+Hcjf9DX69AMm2ZNv9 z8!vCeCs#Zf()h~^E5}pMXLmmBVh24XoR@;=KRNd0`maF!v(NqC+uQ+vZG>lfN<^%z zjDK&7XJ%q&<>cr8X9s+Dvzw>t^fIIO$hYb*E*D-uhn6&Bzop1BryP=gGZv~7RGfkd z4WzH4eno=7AS$X<6Qo8ykis(nec~4uTxNksDEf%FW9*ChTQz3UG2QTA?#)+AUoiFzmW!q1k_x}ex&B! zLk|C{|%v$>kd zVkqRj_^SS{tcXse1gW79zQ6ZKN<@9WPmUdN`tRgOC?X6CIkRGWAs_W7$=$tL{7{^p#KodiXTH97MNOxvitT6Pts%-j>1HhZNNk}&5llWdKt zkjs7j>Ng_h7ljBioErhSTyJ5R`I=CLn2-F4>!H|!uW(dhR|&>8_ZV*=c1D2X^vsSvr!{|hRt6Cj3b1lNdPF0|UAM7LqNHZRdf=|C_)Kxo1r zozTahR+Q$7Os$A{miPE405o^_d!M9N@ zfNt)SbFOWcE!0q^#Br7$)N*=!YvK5=ZvgNsR8c=H3&7w_uN_|5Pm85Uj`j2_?>iW8 z%txHe@4E9nPQ2tF{O`a$<{;7E z7vH=#iFcH|K@S~wt)UiKVz7!Cu&xY|T7EkwP>D&|LRS?c1ml#x<2b%oZw0yFm2ike zY_sbjFM7vsNwW7m_b(NELs`rSx0xV42fhMYgTARlm@N2e-JCeITd#YttOOr-pmw+r zKj3&Ht=+QRf$tdjLw%y!eA!52NmTkll{pL!$ooOZWL5D?@;@m?yDkg2)VI7&c}{`B zAX%i|?qrl5?j0MGcX0+8rrsTQ$~Xyf335s0iT8>ZEE?C2*GSi7*UHx|r@dRNiET8G zU+-!>h3(rm?8W4NeO1maQ*x%>r9D>S&*d$+6XePcgXDASJd_y^8oj^5*Ni>?GKKy-%>fe1UM@eX(+-ZT~-fh?B%t{*K$eif6#B^+pAGlqYshG^jqc9SmeV)ie7(a= zjR@Rf^O7*LuChL)69;6BLKC+}6>NHp+j-;RL$+*mqko37z>l+yKTZ^&_0fIsy5W{Mhit~u|7CiPn)O?4ErWS2vzRe_KdWmd`pph#DtOrp!dU-R-;tVc z2UPo(J1&Tz5%p?cYK&AsEYk=FD7q@~&KFGBzALkSPlIcU(}+>o`i2N%-xdB%a4M)T zY6GIs#{jzGEy0?X>IgrAgEP#|Iphrjd2b-=7v`mpi;x~N;{sH`E&>b1*ZeTt*Ni3b za`Pk2kq^F|SvuN&5}CfcH@@sheIY-#+j?OVws&QxViJZ1=TH{LAXM3iS#Pm;5vmzG zxxdFCkBUuS59-(K3MM-BXJQqOyw*-FWMyNYnw?fFELBdx?mrbxK?BlJ+sDjuL)I9>E!I_Sf9w1@%jD|0VD*&5*6@YBh{cV;PiNZ8@PlD$Eg zEQ^JFFJ?dfV(qnw46^gX$NCJz>_XSpcP7wsMbt_-duz}sE(_O!D8S@dS4hQYi{R56*G3O= zUipd4jYs4o**mfll1b)=NP(6-JtV&O)KB6WCrkEjfKn>lmWhrs^ef*fC3aZLTvOn6 z*PBH6Pr=qoed(uKV3yuz^Gk4K+goYRu8K*&+}5bcQy8P)OrqDFOE4O8od+uA{;UybgFMkt2>;#JRLWRub;SJS$1TLi z>I#JR#lCdDWjxP!&CG)8!s_oeRvlUcX3on2##5fOZHBug{DP4lrf@o~T**#NJ-L{L z(M@kF!QLFiLp82f89hfUB5E~fr^8(gOlyrb6iUt?*{~rz`t<2c9B;x|21o0qxQcm( zha2yBjhWKX1)vegFf{;m=iAG?WyPPw2M@+Z@}0(z`T1}&2I!z8%7%&-Z=9=;YclvV zVjCbWdA(QJJi0ywq78D)=!B1)NZ+>~|tJW`ljk;YZR7 z%&hYc55M@|P+hx;5@BhJWAirgUDVKEknd8;jx|9AK zhY5HTARdtOl+TQfMU28OOfg4epy$w4ZZ&pqOh=N{z@ez#0nU9>0ZT2iMho(|$ZtYV zI$s=p_?(8T)d{cRy{p8iZpZ`AeM8BVn&$dTSHWb#i?8w{b^~NlLe`83Z>z@&Df+5c zkN?kHx&|GW(c=*e*@YV|50s$n@>??qQl%1#T}yLnL76p9$b8dKX^T@r?2fcJEs%1M zs%~nRWQmI0j6n^n1i-0G6+RQDr-eEBSWvxsZ_wjZDH%yT$s1<^zeoO@V=8dQpI)l{ zK+69@cz~z?Nh4`XjMc|b^gEJ^V_r95p76JL6B%h033HK|Be@nN8hs!qGok8Q+49@k zEGtV(CKVO+KBQjE;y4vH=0N@cLE|-gfA@q8doM+2y zOWMLZ`Yt%q$^v2K(t7W~+JuEBXy;uDJr(T!xX-cWD z1WCD8af^qN-^wYEljJ*`xzzjkjufqSCHnR@oaAh2e^-lSHt0~Gk@7^1N)c+OHv%34 zv!F4cu@EALx^h`%qRLWVj?D}T3L2qIC{u()Q7=@BBY{t34gaUuc0yfpKWYzR}Fd5_mN!DG>PT zq}|!&#$V=q>vPIoY3B#5608$!LG`JshE92O6css2T#?cwB}Xc#MIlqNL0YOV#dvB& zig8Qbl4|pcu%TvZtg80~XQSzlKa7WJo3NV_wyso(*t6r%_ygLrHuc>y15fZwdWeR8 z?Zgddva$5?C^&o1^b->Qs9Ag9tMVX1cdoKqz3R^ZS3#O^ zG#4qZHyeP|fc7qpHa~9>wBumG+i_-8dsuprHKD*q{2y>6E69G)df_XIVj4)8?1TuI zCrbRNo8u=>{~jDD(P?aK0nJ4^d`;`FiKfkP( znLlnw-b6c)b?Yd93Tg1)>GRNRo#C7oy6E^APU4N#DTRO}ExZI}P_DXRhFXPc7{kj; zNGpT9-Pbiwg&-^`9Mr8R*{sZb=un6w#}*r6(D(8|)7l`Z8Jp-vm`}4V^tv=D#EK0r ziBqu@dOuNoCcTH=Epm5cpf4AudQk%H{4ba zQd4s6Ea&hdiar~7Ia~JPA+A$H=lqnxnB8g$I`Xa{a+$bdoKA?t-&ZQs4;fejG(D)2 zzowO~uxgthGMgWebsw?5WR{S!DB+d}By9*t{h}F1oADu>X~UcG;VJXsEfWa#i4q<| z!&)Z2ClZTkvq*}_%c-tCwd~1sH=DiQTL3> za3W1+LI0Y+0*{3bUL*-`j9$11Ze%NT=F#=krz%ymQme4bdwiXD^}Xev$?-N9MGo5t zK?QFz{!AL?@_e6oo0P1wPInoFA&COcbYxh6m`H)HPP}EQJOPJ%iyQmhWzrX>^)ukg z{OA1x+T|waIU3(m)W-Ib<@oT2iY;7@rTtx$j&A0AnTCM-353<~P9x2q`>})_C+80j z^GhQ3ev6pH<6NFZ+{anRzJ5O=YS?L?;4;-Qo$)QbH{deXP?Jp_BXThwG|S_HB%9PY~^1S~7DE63xAI=|Gv`d$Y(vA$%zO`5i`*lPc6na z*^b9dGW`*#i3gfxTMl7-ut3d7z|#yfp?_sOqT8`s3FpblwHn5kBXaO8`t8TZl1m-BOy+wVB0;os&}1;at= z6nZ-yn(B_G8NYuUE3>k!AEYEu=cm1s=*O=r$-Sr2l#9#wnd=IxIcd*T-b=gSk)@qG zh0GQ=J%;Qw0n->0RFvWza1->}sVgL_@m>)O&Yt|>`Oz7wAcfXROL1??+5X**?h>Vw zh0)IhZm-glPR=1{U8*O|{@JXC^Uem($f;qeCZaHLgS-c-BL^z%Ae4|C>SDK*pq*IZ zGZ)0+)%;N5;7$$4c&-3a)_1Y`19k(d=XVyys8q+mV|YhFH?+s$OnV2Mue4D!kqK-9QQKYbZ=lN3 zgMyKTL#9xO*ad9@&iyi?3k_OSwXIftZJJNe1BLZ!bj=R&Pzxj1GahOD(c-1&PxToc!IkKD=!aV>g%^V*5V>;@qX;24EM zCxkRqdA_2bLbk5EysuK=*(l&O^8sQchjbK{#jGBQesrmB;Fd0ztJj)TEx*EvB>?nE zDHMl1spUIKr1Ay6I75Q)1HOT7r%DXI#L4?U>PpkJ?`b=grm5V$X^Mzj^I)|1YA|v_ zDllY+3E5ysldaEG5_&nlR)Jx^2G8!d4o;{0A{x76iGtsXE7N*>zisE2lS-Q*i^l|H*g1rRUK{IqDNyQBw zoB_9eq6=rK6)nAi-gxTc9*{ZvnJ~2ZcrDf$*^_-H^X={!wGCk`hMTIpE^Wev;~plS zNR)OaNNGO~Xle7Pr&J4#l=$;hPqNLN8VhJZ^_tlC1Zp%1(m^BdSan+tt4ixUIoj&! ze(zyZ)=Hae%`G(^jvzPj=dnnx*BY~!!*Sb(bKBiSYk$&VzNz9mG{1Noe;8Q1q3;xJ z^+rINq02HVU`CwfojeP$Po0DZ<3x5m|ALBBOjPHGA~#>1FZ~AHd)oJ|aRcxR+?I*G zBzS6j!=DIq(celUNlZ#&4Um?U_!ZepYl-TZ38ag3S|Qn!V&w24H=Sz$wXDorN)N-^ zCSIju&p3VhUFQ`3DH``vzKCNq8WFiDye2_sK>UqIR&M-0VXm4lbReXovtl;HeLmKk z?0v)&)y&*0RrD{`X+0F2Zx9@Wa{e#Q?kTvlDB2Tn(6Mc!V>=z&wr$(CZ9D(iNyoNr z+jge!t(mHOr)K71s`kSRRd+Eu@^_O}?Y)j<`4-yr2sHFHGEmMff@LZ)n+Q9>rp zTs^a+1NFft7>dGSN_caSG945i{1;5mVXWEGiNA~E<{ ziv<3JS4)Bd(}1u7lUrF)(BZjqN==~l^+Le^?V*2^a!6GIPsJ(C;I2+=#o&y!f{lQUg$}uT#Ntg5&5P!N!WjXYmux&` z5zo@qC6jaMPM^X?d;Cs6JiSN%Ym*viE~Bb$nM$j!g9?nrR#J=-))1*-hPOHirxr?& zXThchR(Xoypl3qO`)#ut&m=*7tcmD;ym?HY&|9<6R(+17j+p*k9d<{iTdaG4fpLo+ zvvAI`33H6+`0M%PYVewj;dhMc(bQh|z;Q9j0bwjIyh*)=$e0K~4&W&L`Y(IGNXO+R z@r=(-L3x8Xc8k&djKuKT@+BFr)sNQc#&BTYjv@U%!}}G%xawir`NCppfmO6F)>JP1 zw_Aja3l_0G8u9Fc>>ZTwU#Xs_evCgw<&vlfOPQ})StNeqf!nlWS}}s`D)n^YL0uzI zaPapG>a#Sik(H`TgoG>(Pz(qH8d#?)z1Y0DUAMFS`@Ba@!b))2eZAJ5G4Zg|m%yrY zP*8{0<3Hh6+xcSfC0=t=f#tUC#PSoUahm_B3ugaG*Q*fpXkL42J$FDAjYUc#*(_Q! ze-STTvSQWD*(q;~)BfX77*9u7WS^GE zaRlMgsI?h}Xl@!)BY#o3FB&{<2<{-R}+ z;!Nda^w*jnaeAMpLDdL99?xgM^`e3=_L(=?wwtPNE<#)a+7ipPWU6ko_c@MJQT07ytYp_;qtF^X1sNz*%^k2e@^CV}( zPv;nH$)_0*D)LlM7VXZAuc+FC(g3*Huml4;Kx)b%1o*K-h+u$n=JAB>JLW?}ok5YO z__h7m2Lf}yP|C?VKoft4S@1NoQN9IN)TB*~Tx`7&vW_C6L?r1^Y~@s6IIm@-`=)N| z%oGLjoPU5`;AfQ;RBR;?#=L`6-3F|JI%p(tjv6eYZBI`BqQaK6C7MXSqI;%|D)9g^ zKa6J|xMcy=lH+b1_n#>>wLhQJ>v=U>k5L=jW3~MynQhExR1zLW)&0@wD>y#8?0Rr* zyq|qKzwNrY^Zf4B-m->Aw?NhKzmJznTnp~_zv-zr5}d!o4zc|85JMb7-2K9rGPT~< zVlK&jA-phts=grs-tv4^zd0sRQ1{>Rhx4B-a0SX{3c&V>sq)rs8{RJK$Wa?=Phzb7 z#RS;I1OGsgOIIx!8+!CZNJR9RvtmXY7Xjn2Xi0OJ8^$nk6R=?Ehrn-RLZ|sN^u4lB zH;95K=ZO}nVqL9%6K{vQYt!8W#{h`A5b+|f<6=eSM9`4fu)`zg=*rjdri4@e)<9Up zHFTM2Ur#&KZD-RaQm)J&mTH>e7LR#=Ux8UrA^n9ehAx)PJoC}X?{Deej#y=!j78nw zj)IYFsgPJ(R6Ya(h5#l}wX6m2;{bpuSkR-E@2AG2gDz+1AuM}M@Br?WOtm)xe)RkN zGE*U0;}G1B!7rirb)F6sI&HiF@;3%53E{41ycz>(a(;m1Br#&wWxJMgt)JMPsfC3t z50su1Jvek*%#T>&kHOhG&7|jJ=!(Mhb0Rb^!XhUC4{NIIi_Wvx*55xb?kWHoz*Lq@ z*3?USuHv76RNbA>h}<9S5Im8MOQkNMXKp+|VZY|| zZ6%g;MeQBW@z=9>Y5=<~>yjO?Itl zcvNkoq#OTB;fB!NYB3UIw}E0@RH6w*L&GX0rG6Pm9C$RWCRm&`VSTIra_qT0ZDB$oO}%ggl@!vNE7@OGS=*yRrM^b@UD)%(Kxn z=qmNzE4^0h=*1l05PyEt&MVVHvj|e1+uBe?ZOK%$#()J|kxbKt7GV@$fsg1T_uXHm zW;H4XAI zv{r~te^H=hTTnB?s@n$EU#%(-x%u*wN8ue@*fvFx`}pvpQSGjvMMGTewBli90i${& zBbg-6uGahwF#S$BL~dPa@+eqpdT36AItGuzk0GQhMNyRagkE*cJet)SDYrtnBVJ}@zpW!s?SS2G!t=o?w?u* za5(to<90aWU`#V7CnDCN@r`-yCIvANg%h=1exr8apQ)g}2td9Q_VSm?Dt2rRP)3%I=y1@C*~^y?Z74u>6{)nOJ(RkS0iaJ!j+(ff6q%e&rSOwX zn*T_)PclA5KNL6)#5Z#q$oD)+#z+xZ3e%)d9khxK?H2kdZZ)o0Rz%xp?!%7q$b||9 zh9b#c)Z>;I1MqA(oh_`UV%^u#&XwExr;+Oz$Q0L(CO?v?^s-cO;Qb;CA40fGi`n_> zb&0QyvnRdbfHc*d*YAO6gGaP?4h^LY)!+?VIbb0sdZKG{4Zvl`yobK(T@P6eZ)7Ex3FE_(NbVd4x= z)=XTNmf`(89y>!Fg^|^$=Wix&?Q;E@rBej8&KGhwh`kFauZRQdiL{y4i$PJQ5(;Zd zYuI9S5Rzjunyc?lyg#w8MkHj{-BuH9eR$QpSS%O3kdxXKPPd=m! zG*)_wb8CQzGA@SmZcakWXNDNT``u^Ajd#g?2ey|OncQ{W(r9Jt(NEh61WN6a>_Gl~ z>I}8lz-4t^pdf75_p{Sm9`Cc}H#@hD>gBbhCWS2ZG|9FnfY=H2W2)~^EUdSan45$Y)U2P{RK&ZaxVr# z2)216*gI?Z?8s^_E3UP^CTKVKsS`(WF$u*?T)uJ2M+z+bYqImNZPa{o`W)N>W$c1v zY996RTf&lpICok-wA-bySNXbPIE7`K0(BSEidVO3a=Y11g($i8jf;uV3lo_? z$>zSD74g4cjxfHt0T}mhM1PzMoNYfs{`i8RIWxW`e{aKHp`r*x0?G7>2@<*Wn!$(s z0VaUITlb$q-Jc>CtQ)s^w8!7KShl2C&R%#;Rl?RTKw<^WM2fLS5*9vy{$)`#av+rl zy&teE9t8kUJBYViKlQI~v?uVV%iqr! z_SM?Jh~<4wLoUAOLY80ZS3PTTROeil9p|}%c0?Y7T0!guGTSoUe`n!u;CFO)7P|R9 zzK<5*7IP{|vNIa(RoNy*4@Dd244VoWBFn8%F;HYYg6OfS1QV=oMFhQ>b^-7KyzN@n zLcDfBB+C0w>Rq}Bl@$UMdkB1zuwQI$K@$HgWj+5s(eVJ8R>0q2fwm$H?( zo@9lfCbU&3Uif_V;~wElyQsaMQo}@cl5F~g4Te0zXJQLl z1)ei8WAitBW276^*e>rv{aCzNm^fYPck>DZObsAXgu?Hm7iSBU17W|fY7N%=ZAZh0 zM`lo_!*lt9wLv#;rra)ne_LqCA)MtknTRU$sxivzm%bmEMlC3gPxo=ZZQ%@xAbAn6 zQ632-vU)`LKn+tR;}+lSfrw{SPjl4BA1kUmVub5^{X-3yO9!iR3P%X9isTaH7i%K1 z7=VO^)}~Cb`1)z$);m|Aq*>ogS^iER+t&L#{IiR6J%1ePtgt95&C=*7w$)rmFTXtn z1L`OCy3HouDxNn!55eLDNQ1sM`a&p;Lu=rajCNA9vXCRtBYYSBfF|R__3%d*7TbXe zktLY_aH&}XeH|5`ETn{;V$swLMiGmKmV*7xqu#iw1=9(|4>y!I{+ry&zG=5Vfq=(* zaB)`^gdHb*N_Z@vAItgW54dJG_Q@FgTcp4rM-?LmXWOUqSpHm`(`Tsasr$8)*!YPS zNH|jDxqGLN?oARckLx=edWc{2>I0p)HBbqVU9C{7U)tT+X9)y+zg4UC)ztClJI#D& zT>5?bKXPy4Oq=H`9=XGnPVBim8QDxDG^94M`CL5kSQ^k`xDG^cP*_wHS~NwgdDmeU zMmr(+#Gk32EAbbv<_HKOocWS}Vi0&;k&lVuHBxz>=Nzf zZJcc$uNd)N@t?a+-n2`)#`ViZqq{UK*sOFm;kJ-D{p-m);={m@&rq=@+mZrOfuJy_ zvNO{Ae2Y|{2%8Ut56JK)bBsbt>&F&|EnB9FOtny+8ChRzfD@MQi0z3w}yWrls;XIQP5M1~zKBu5_;k~|}g zkc4$&g~3k*?L4x(^q}_h`@XRAfw>uQp{L9Jdo+9Oe zh~6(R(^n;X6dyVNmx{=VIk$=yroGB2Z_2K#IrkK)DL#Rjxy`#Lx|)6A+PQG!(LpHO zF6$#Z*@g?Y*ds&Wev@uRfFYu{(whq;HucJ$$Q4xv0bAH<^`%2=t?e?Vcygh~&UCd* z9a!9e#W7_28NTfEfy-#M*!2WGp4@a7@S;ZCy09~Vvar98{`*xYdq4YXaNivEyeUQ` zULC3j`pYA^mpy`3tz)H~pn;KUdu+y0@3@PmY4tBlF$)Q&Vx6NZ5kOq`WbJSbwIj=K z;{nB&rDEOcC*&hu4Kab>q-+p|MOYey=?xfYnENNGOOf0Vy!^1MYvdoEEtgEe=MkzF{DCtRUV=HT_PX9lI=G71Yotfb z<>cH4L7u0>azB{{GO-2!_n@cQ&{9cOV06F#l4wbOxjiDN9qMDZ?QYyXR91hGDZ`NzP85r)iTSIF1K@nZbS`(4aX@R4bIf9 zsC=mmCx!|hR;AoC7eM32dT9SuP&moMvn<79s6V;@mWC-kzb$YUAJH+`Wj5>?h11PK zZxUr@11vg$DN)QqRW)D3VmoKcwyok>b_;jl)-=+@xBR_YF4h$^|F%H5+LGE&SK9g%DTa<>SzXuz2eTNbHH|4`Yo`0{b}m1WJ#_;y*Qrk(pUva#O*pyF@~ z;zXwWxVHjzQ>|Y0eY^wk`4lvBwhtUUU-UiLcs{>ArIEcFd)R-+P^)e}U1D62X_qDC%d^lowOUIV>PE1+g#V!3uK5LpVbH5@w=l7dXc z1RJBp6TS8%k30Dbne~o@3ZDDVKrUbTwQrq#^2(mk2>|zFtC#~Rk&X<-SJu7FUK-|b z>|Q!vyE07!P3!@!4A~sHIx$^~;EKuKckL0X1YT-%*ucV5@Tl`BIfo5rk-L48w|@4X z7IQy+o0cB(smX?Db|ppB5g)wuBD43-$47I?6pP#g==!ep_j+fKTatzXd{3 zHnLB8A=Z{4R-|)~`GF8B#$w$umd&9N%gWH8p4c7t7`{^dD`H`JyG!#S3gF)6{Y;?x z{kF|^F1W0nDvpJR2gpI$tyrt_gqTOvK`?^jYC(FphyHtY0m>E0i#f0k^DWkYhpknP?Rh7fhbkIQ2KBy1Ts6167D6*ua{_b=5S~<@9 z&~K{6H%;jGrQ%XU(itcch6IvX7LjAeU=pu~Q$-k(dFFy`AuEqKOBlln2n%eIqUII| zTG-=->KB-H6`C(%gvilo-p)V|^YSzRX~`x^jzixg^R>>YcxmmxeQ*_Z4<5ayZNIOP z`%GlGG5fexIYg_*<*&G;tBMB4EP;dj*Y z2A2TZ^|wsOHn!YQ@Ay;TuI)XOM^qYk*!u6=rUNeUsPSev9N{yz_Ubrw=-y{^yhp(T zw@h!(T&Sw$Fq{M4=#I&+QLJz!MfgS74Z;;O?17}XtQ|uN2loQACrTBmjJeujQ0rvK z(x`(x@j$9;!Fy~D#SKL>-8eQ+MYLma-LuT$Pld}b77TKz2Wz3OJH7**$l7#r4i2U{ z@g_F-kVyq?EemnhA0O8hdWssg^VbDs@u-5Fb5FVtDQ*%$yYQ+CB0>WXIrm}9r7h~1 z`UJ~Bz~g`6r^~k`gZrX4SHQ%k!+n}Yllk!9kXX&OFbZ5 zR#^qjw#UjBSxM!3Kf=-akQcZRKl!2JH6_8#pFrBXo2 zpj=0#(V~Z`d!nqb;PJ70`Wp9Hl4eH3k1|sss2ORcL?G>6a3;Mo-50*?8jLuPLq4}O z33DtpDK!#xX)V%wf@`XMm+;0UP(7%HYlCRm4x>$NhOdwGUW)`MAD&mpWDMy#|w{%el%2>_A z%m72~6c^_YGsR~<#^5Q|?NkM)Q|fsOx>HwtuxmV&*=gz5YsP}Lz(#eFtX?FB`uQ3` z#VWaw5{f*Au3CQEiHmGr5}{{K;5FC^tGfr>#Ax)c<}Z?UbDzas_O}GO{O1G2o!-TF zq>H7Gdh%ZiIaPCdoqY1~)QRTpU#^|Dbr=G@K_G={Tf{?vUkT^^DO3__xjoGaZBDAm z{LS!Z+X9ot6pxjX30N~*Tg_Bq06fF7#kLKcoViuUqmEX)HmAIS{QC1Pd_PMUuN9D~ z<6-sL6!ELgM#t;(lWxze%5}xOHH(Ab#PQfQm4%yhwpHw%q@PesW0L6%o5t>d3;HZI zC9P?%a@gV5rbwuJadenqv0B4=3@f4``!iq?bF>ky1x0AzHlH% zLF*4RyIJH4@b3^<6`1JJ=I;9E)r#*dIq$3X*p6Y@=Kj51D#5ciW=k^_*PkVi3DZm8 zhm=~p&-cLhXU+*t?V8GIvDTkv1&T67lj}hX4G3`$K6gwl;cud^h4-R&64#71ZGfQf zvK+3qV6`Lf^xMuZ3^qd;pASA?%`TzS6jDl^4uoUw_q~`iCmTeODj94DbXv#0^Gq(s z0WuIA5D`gklmvJ*s$1f=UY3eX(%vxTS+O%V=qqos&J2O`gjW3D}lvs{wAucM6>tsr2Hx`zNj=8K(|$BdcQyi&ba^VUgB+|H8<^~$8$v;`ssGlC8B`AxgRrK`jz z5*0hz;zei{5th#UvPJr29f2b7$*wo2V6@{wf&397h|nt&Gto*(SJF2Yli%ibb$I&s zAH*S7K(!eUB&|!=Bfd!^ad>RuksH9yR-*ah_=9~Q?C8d%BKcUiWzup?fS5D9JbC(4 z_06VYIu`C$59cS9gBjl^v%GsGoIH58eR^GOCy|Y%XP?%ap05->qm4X#zf1CI?WM-J zvX_1&L(RSqDSZKL3iA5?{*VZTfaL5zmGOO${TNs z*=0imxW7zNBW)Y^g7;#XPC<~hlZsnqVHuhO2&4w zrFREw5vgcFcxrH14G(HX1q8n(YuVGzBiWTKsK}+1&irka#rP@DsGNm5wmQDJz_xPF zk{XISW?Uq5sN<`|6Yme>g6Q{6)CF2Cz)!@(7zxp{Ru_WGAOt)l+v8Rn`!fiDp36B` zxGiP^GT;)EA{7{>PuJ2CONY`M+MH_yG%C?MlT1N!C0tZoXnX|16(hJjz~&494SPw; zy($MiwiPYgKJ30PZ&~b9*@?Lz;FK4)L!+{#M&1j}(~v0eMsh>ejx&j|ht~-qE)mO_ z`Ri6p>ny{O=RsMivpZ_e$7PH+pubh}Db3k@wX!h`nuk*xM&X~fB0i+_;_+0>q!7~l z@V^UniYgSTD`Hk^u*$PA?VL(KkwbDejdr)UpVz;7=v8=!|gVbJQ5~ii)Pt$^_lG%XlRp1 zAKb;%2(pqhCQC!CiRIKQDx;2Z(FyUjQdx$&(`iIjC0TX_??$7p-k~A)PPbd!+0k@m zT2#8qTnlWBVi;tj#d9i61=R$Y(vVz6fkYs|f@ccLP!lmAZ)N0%82>&z;U|N!o#dKhqn2B z?T>Nkp^m}i_2Zjw@9W)2YCFI8mN_uI6ug5mx{Rf{fHhvamn>_i#Tyog*)vSWLH zO*oaYC=YZ2lk80BDpSZ?{vI0WoxU-YQz)*79!rR!0o`EOqJiwp!!`rPWWr9k)LSBh z+VI0FXdJQqT}pxetp2Q(ayB;LKs5?8d)*L;n@&n=ka7vV9!}5)6qSmKC^Chgl#~!U zgb3ukCA^B#XEQJc9k&j*74hG7n?-l_xMZW6KT5KRN1&+4Q%lZ70}RQ@{pO0$ppul) zq$MUtid5MCoZ||8(NSrG#Z>95Cyd$AF@vH;u+`W#HsVs0x3S6n#ljpH5bT12>pRJB}a!97Q$ zsWdJc4n-!T8#X@zn7NA?bWfI z=||#h%wd;Z51S{niBveMAXn9x!_-Pt9-S%RkICruf|^F7wlS{0iIR$j%mqykkEE+I zo~UpQrln)X;&~@C%tPHmId2%xdf+HdB`iD0edGhsi2J!}`>p58DPcS1wQjeCOO?y0 zH|?Xi@rYsRzo-feG~W}1{pmm3M)uqO!?`!8q4Gf1dwr-a^Hb~hpI|(7fb?c5SyQFRa$b?jp( z=+tjrJ+yS!E?ZMu$5+JB3f*P89X1=ARMFv+;*BVw1lSbY5QO@Bb7%sGGAS3|CpnCU zML87-Q94NH_285Qq!dBKucx>MVlUOiv?>0lFl`yh>B?WL&*msoHezA5oJX1 z`IG1Nbu^=!s#4AEjwe5+u$YrrTGQP!#3suo9htB6GGrGX?F;|dBmxOTeIi53=oV4T z?&dp-J5q9l()$}cr{T=d=XzK{>3A!!Ed_p~hDVQ=#_7#21JF1GPBhp79n=9wglWXk z$18_wlk{8BG750WQEzCxXGEq&z+efzSgVB8xGdd<$_8;O*vHXeoM>QcgJCR$t)!f2 z`HthmL66ApyqJ)fG2k%(z3I_p{C^$AVrQ!7gE0Fl)0UlBn?NC=iP~&gDUo#4;X$U?wbq0h9`p;|s+4@lDeg!qw~ zzM?M{86at#o+L$Y*e^{l-*!d83tOAZv$@Z84t=l$S^AAH{G$16!%WX9DJ6#W#ApeA znWn8a6ALgsLV7p!r`coLWWsETFV{~$hP0cwro{c{y>xfV<7%9%gtT)RQ59KtXom$K zm}{|!FqfXo?{t_Ek4>+dN%#qq5>KH-v*anFL1IRgTr{LfA=JdSdv{H8%p{~(L^AZE ztk{AoR4Vupl5ZSkFv^=iuF)~UFZs9k-lzudlA+C9V}c@PW@%Vo!Cc3wOlrZuPjd-+ zbZ+$T3`EdgWPV(U%`qzX&oAw_!`yI)kBNsoL3oYmx2)F)7esn;-_lJ>EBL*@*fDW2 z;@Z3xmo2Fmohv<3m&f>8FLH28QoD)t_f#!XFk80_!mq92*UABwJNRFX-vsj3OExAD z+Cq^!9Xgls7qs`}Wownc;?~-h+NC&)37D=OD^CN~^$~c2>F^6AHgHTKwoY1Pzq9K_ z*H4GvX!&}4-%?+;dA`aHRG4wWuO9D%`AS%T4i|a`HnhSH0(K6QyTa_1u z3&Z5B-6&*CXSpK9lNYFx!CO$%BJo?>8~k_1_oqcl4w->5TvcLK6C)+-8vu^^imDcL zk$PQN)>qIuH^#fp`FG(B#5+5?>b0C=TXDNCe!nnvF}8Ye^D5<_hYhmPU4>-foo$7 z>W>;&F=#$I)BcvRp6fRlkmNIe0Cpp#0W)Qqh8cYi$;2rtcIZm?+?v=}GwCI$& zaKR3{&{!#A$B@Sg@h*#bJ0!h*lBasqWcc&4{iTL3mRBGRiG0XXM=L@L&c#lEuKAS~ zPBm6v7*}~)4h?CBV^0#FN0oqOzBhD#xQXYz|*g=8wlIM3P~_gaivG z##a$0UQfi_f66Ani4OeyvAS6gD&m;-e(8K>>YZKu;c2QCntkxM^5aHwTezWT9)Aue9U8V?E67mZ18bxm{^KopG z@%hDVW!j1iS4g1$>T|o;$N_53HsyBbn`R89h#Bg!Pmc!Hq_$vA=yRF8Zi;Rc`P592 zQIT*5F`=;!hK>_GSiY>=!J)~M+fDc-3PmYE=9`35XWvi~5wP0k>GFDSVzD`|0x-5gK!RdZ zB27O|_)}wHQwmVGiLcH|v#JRWh&M@W`ZGM9IPyM#^l3nW*8 z+ND>0h8?09Ulh5)mon9a!*BLS^gQOVwgjPAj#Nuk@`$VCc@y|MIG#+^&tn4iFiuKs7A9(K`rz*U5>~-FsVLq>I;0aY1lAV0oynoMOV1 zEtn$2lsaGeYT})>axcVUlhUc)A_)c38IA00xfHY2 zpg!#BQP)}T?e{i!KgOi?tXYEq{@FWDc4)1%)d?k7KnI#h+&C&OYYY_b?*N2utj%E) z7i4P;9f|naYx|1hb-BckT&NEnX@Ab@5)u7D@NdTNz`KFbCP-8oEJV|68?dj;v^Od? zgOd4xbOBakZl*0|kL{*)U$}k|C9GRrA7}zw%}}~xcAm50c9ldGlh{-51z|g zHL7KNvO7^G+LWgm5{zaO#(4v@vN2lu(EEkT=z7?m_txBiHWK}L=)yt~4m=WZ8@ghQ za)V`ppDfzmVm^T$X0u|O@+`TM$SifiW6PeubR}e^sipO~ToGX^A)a3hYz-V?W2w&m zuB25@tRM*U(c4vdd1Gvz$mEU?lt~Kp; zdo9yPS=T%n$RdVUGIBoRc&6m?zwj70Ec59Y*@M28WUA{&QXa$8$#N zZ}=$OSf`&!h43VfNRof)EfQ%tu;YT|s0@IJtvYm7+>^=-FEq6o+n%HX2{`4hGgRdY zEoQzMDQ5oD5(vVPIDxuow(f7}#wP3LaSJx{P%Ogk1{(YF*2xyeW)pWJZh9^}vl!3< zxJ%L2S#6a(gRu6ua}3n(FC{WUc%{L716gx_Vnwl=Y?I9crM%WNJn zxgP%Nw;Bu&`+&Ak{FnEMa8X!-Lm}iu^N9L0U!L+X&rhDd+}V6T1`bTkiJGSx)s{v# z&YQzl&l{+1ln$kKDIb2%)xYeo;{UoW<-OgGE9MhEYuk2;cG~$UKEZUHbPxC(_2`Q^ ze~&oXiW>4n8zzTJwx;1?D(TjaoCwKAsO98S01U{3nBT}*jWjYb|DHp>?c1An=VMEb zC|Ry!W_ju_3Mu(pxna2h$`NNUpnWViYbzZH90_GhX2Deg3j1f_u@`WvT&{cl!p|Sv ziEdIbGYxUUhE9gUA8s8!M_!*e&}PgQy|qREd@E=7BSAoW_(W$l_7wa((Kq)}LZq~p5Wqx9B<6qCLD^YSGLq7{Sm?vb<5W^Bj%ZD$+Iex6sa0PRhc!i zRVfcI52r4asROi#ORJJ-GL~3grNB3T;f8TeR%&BDPTMQWl#j7>Rkfs`vKw+R%Zlc% z$ek{FenEYGa8-|V)8&?X_XyV3{!w^SFJ1|U7(AhNu9B;I6{%OO(x4^$s<`8zkh{US zi`+LFLK$j}l1B0hAwLzQf!{^lj(9P8&c8K!GD^{{xK`>Z?Jj28LET2V7ODbJ`? zP-V|s6_#m-O!HsQVa*EjXFHwL;TTk9&m#=^`lBfq;|n(`q@3f}d@{pEyaCeqGW`|i z?ul`7k6n@$gmk!F4-wh|#>P6#PKn8d4E2TGCDR#<%gsx^$*IxMn0byW*V>nXf08I^ zoYbJq`)M>kDu8@K`7+TC_Ig}|gJ>vymmwR{C~*F&$5TPZdqNA94Wgg>j^nfDL^QBW4(?!uqJE^st~ zTxZhl4c5gvih^1?(yLqUM9L5Tv2|N7`{SwQymt<6G~Lz#(`!C4A!B7HH*GJe7~l|@ zlysUcjn2jno)j8`Ut1fV71v{VJ@E(%{)BG0Ob~6GdF|nWnKkY2DLKC zWLe(`S1)KFjBF`|=-VQmIc5!U-LPG`?s8L8GvF!`74v3CrNgSe~ zwjwx0pe%e2K)ww+9&=>cx3gtwH1!Q^+p zew+%XrDm<6ZhJMnYKt*2SNhE2^4=~&Xj37~!Nc^%66@>ZTFGCcX#D~}`AYiH&}nzj zHK|~vpL(d@G`NS4dY*y(nA;%jZCsJaH?}13@PY6dg`Oy(DGLER_i!?%Wx}^d;WTE6x0{e7m|mRD2UoyXrR@M_)ZKCRe=K- zilu}t@!UaRW03h~XjeX2eN{YU@W}i%>z7W4Vm2V349;LcG5yb%y&wEZw-1Hp)~`1t z8Dttzhxjr2o)p~$c0c>8!Y2iby?HW#YVD#~1nu`T9WM@a)h%lqv<;r7QU|M()=9(A z)EDRD&&5DKeFme@^-M}?1!Xv6#8{Lh;dIf_scM^Y(%JBlbl3V&5X0!w~6WqzA-P>XV?5(Vn<{0;fvnxW`Lri*gk zWP5p?hbn9F2l-%4_t#fhZbJ}ke3*K^KhNCP)Q{VKH#w%X!3adpem*A8Sy5`UDHU1W z;=7{riXGor9NSDm9@&#O>iPpyuQX zfz6E&=LOnYbYHL0DP9zGDBM7gpb~DTtad_}_(5;8d^vhdZn+)td4lt85EkbWAcz16 zzS9s|F1kKPhwU+jPnkT1Jd+qZb{8aPYkoXkukU>kze$blf;wW~8$an$LKlzz!*l=d zqcZ=~gZ{4?@qc)z|0l)u|B6fhC*VrU&h|eES7tUsHcpoR1L4Za^8ZD+GW@>@SGNC7 zxc+Z|Jkx)H=>K1YD=Pyt8^`}5T>p8l4DA1faINZu`bW5~{RiRdcHPyulQDLAkuyd! zMw&4O4VAD7WB`*+0ST2!ehEkn7Lku{0}%-6s6_-&K&R3Kf~pGux|=Oa?5b7%B7PJO zS!%8;YQbc@@tsTqt-tv6?EHLub+`X9>p98&xSVPKO&EfCD0` zL5I&zs0=@fFZj-xCjjSIuZN?R*RyA_-E(T)`YXnysi)D);pD6yp;t2+A1LZvH&~fD zo}hQ&kN+m52`?B2oIN=YkCQ+%a>zV2(?B%XwJ#$CWXPP5Il{P@nFFOKUJn1lTw^&t zYZ1gO>LV{#IIKB|FGM{>FnNIwMf6vA{@7@&%BjL5V+XuT(abDEWP#`-w{@row*2pg zg7Zm?c(y{D3=#&(Ao4T**j#+}uuPCy+G-ng`uul5(C1-hsCaU=}pV zJQ9@1LfX@h(P-8DJW~qM`#F$D-0k2Ve&ln0?p5d(_D19wp|Dwc2a;sd!kEgq#jshb zwhIgEk>5;ZOn&^e4Vbi{8MZe1Eqf8Y7G`NsYf7cN=|U(Cw%s>y*o z=L$j0B56lTMdYjkYq=`>*93IunA899gUlI>X+z8Ft!4C58FSVlr#G7VBuWwpDF;(+ zgXjXE;Rs7&0MG6HmC;-krvsqE=|bDKNAd*85#|eX`Gmjyc6*f5hFmE-L~kHtW^bf_ zz^W4A_hmuX2|4~(D|tGQzJSW#xjaF?!18`uV!rWyl%A6>txfv)Z$M@OS=j~7HR@mE z@s|iB2VMxdOQFE`YDEvJ?E~%oYTQJMrHhrHoDxyC5X+%V;7Zycp7^Bovr^?57Gb`5%JY&7W;_j5*!217U zh>F69X^HuziCU<=uRjW%t<3w4PL5dzKZPkUQU#>ghN$pD|7pXh!SF{xC~BSkms^i( z{zO8l0*`RpL$(z_maB%9?ONDR4XX9Iz-c?({b@Ts0CUIE*0M+FhTDm~>3!LSNV!0A zZ|!>Z@W!l3yHjZMjgZ@$xg)sKgJNJb@Xs0`l|(Ma-gYL=5X>B1vZo~j?46Tt8S}`W zaxw|W#v@?CpqNHxyh&p`P&^17yBvca{oYYCJZLGbl{SN?7K(N1`vmdeN zRen{2YME-c>UGY|RdCmEE4W9vgWMVJ0?+Zy`~rRx{{f#7!l14G1K#@(`t~ouy^q(Z z^4JaJ6v%~x=~QjS*8s*iGMib&+{^r@Y6(8e1n?)gms!rN%skCZCjVqs<2mFw4l;gK z4YLH@jWT#Y`IMX^e_*Y6Hu(a_*ze<)$!caI;pjtDzhJHG?W!{fkzb)2vKgNsZ!)(t zw`YEYYE--NDb;TBa};2Qi3ObksoqK+hMRsymXjT*g{@GXN6P{4&#N{7zQ>boxRCjP z-HkqDLga7wEPe>I#(Q`=n@_$+s_}l%xTDyIMsOGE#1A4FAH%=JDTMJp<~clr=zv=N zM32XS5qgi2@CS?rwbC`>2(jX3a+X}fyuzJiDlrBv@t^1>%-|&O&c$CE-2f8s0EvQ5 zYXEKX3tWaA=wZ%^1>J?p&{5#QZ74|| zL7Or?coFFRnV>%jO5qhKfwiD5?Xb2jU@vSW2)eKxp88MF|33w---!Q&Zo~nQtP?24 z(w@872GC3$pnrG3wFtFA?Fn=rcS!XM)P(H_v4Qk%;PT&~?}5$vFL=HS)x!Gbp{Lj) zSakq2a~It4M0zTc;kpaGg9+LUYaS1B-poz~&HGSh1-#*Muu(I>Cccf9XC6iqfp%AC zZqMvM?U|=C*P*3oR%RdQ-}RY6RE4&xTFD$$oUH&I`!;?9?9s3B4$#|E(I=pf!q|cS z2p8CCG+uQK^|HSL-C38pJM&9q1$+bnLkqx)o<`TBKLOsRGAB@Z`bsj8nap&8g*t_< z$~>3xV+~rCSp}N+6||REf$r%+KGj~}T_jJqX0}{6{)*ahHPvIsR8>}#mz5?HCB;SY z!h%>d63!0=rGVe(^|)P5huxNEF`GoAL9f$l)B?|`ScYI!)DW875$KO}^s|xB)Tza^ z9-0pg^S{;5(I0@O$=@B*ALvkq1-?5{hLKDDZKRwXDPJ0i#Xv2pEiMW)gaZBVO$r54 zc-~blP`+nUs5Q_(qLgPU9_k#x_VHLL5PL(-06~Ht7S-$abajdKMGCgH^!AAXrl6%er{qvuRJEOoW2d(5f~^s(R+7FL<>6Nx<#Qy z^RH{^XXdxkXPDyf+)4fRn@&3}S7CDV#Fnk!?sYT04UXjjTJ7!K8tCu4s^#0g5=~oM zVUB(hp4`zp86JE$ps;aP0G>teY;Ebscftb$^gZZ1W#4XbsDZY0tO)e0LlZ*FdRKG+ zVO+ia=<1Eqpvxs6$qXY`L!ftdOGxUkbB9{zPx1`pq28-E4mst3^SeF8MFXNKi`D^y zF;~#(zg<{-sZS{>!)dAU>PvXVbVZ?Qzz+R^g#lPeO9?z#_>wMvbbn{iu8v%#QiYe5REUa{X*o@Kci@~G%Ty>$F~1N_u_1S z*1LLM3vGaZs_^7c!}5-) zAZoD2e#^ub#!XtYCE{k3sepg4yEHScwCLzuY?xE{e^H7TfPs}39GKiMc1+Ettr|)C z|9Mj?bC%wvWS4Kty;FZp{JZsW->H9RdAeQ(7R*LS>EhMAQ6=D?jtfnJxVXDG${3j zDU6gh;bI#`3sWT9CSGhK(8gxlWTlP%sHT`WyXD(Fpa@oLvEl$gges*Q&|DFnUz?7I zO3QbCZ_*a77yT71=z8$82@)X|n*;vMPmLCchsjYiJ9C2hbf}@BOin=_FH!QrSV7ql z+A-+zl>LbLlpFwe+7At<25oMo=XZk>CgciLW3z>!!s4=1^%~}P=+6Lz`5ki#Orvtw zP^_fvY`q>DFmnqsf~Vp~eavrBKL9~8^T|+tq-@V|=3VIjDf2dX1@yMJ2lb{hnD9TC zmm${hgExIB*K=sdU@AlPYnXfB1y4YF5?~nMEC7pEGtZ$d06PH=0Ry>$5qaYxAHKQfRb!$nGrb1C(wC)NcmN zZ3fJ3Ml5t~x;SQ2c1$s|3C3)KF`Hn_CcsLPSp&~o0|Y~miU0us2JpTH@J`$NAw2f(p><3w8q>Bcr1WbZD&>t#{9r!ONXlEvbtm7jboU0$&k}qw)1jLt)YwvxgnPu z>Da|e@8Th~j2gA0SL;2G#{V>U=je!EF8>F_>VGIqU!}D8~j_y z7G?{(Ma3p3Ve@gO3^fY~SklZCqgohH;BT+RV>;BG>K-*CssrkzT2?o!RjVPe+sQC~ zCc)G(O-wtZN@Y$A@-^j<$y2zR@?F|KZNK(}_M}$T&z;~-a>LwNP8HyioXjq2$mx>(&_HW5mM6S2fz)*teR{W1SucIS+PGmg)Ae+Jt=WA%(JGng?z zx}m{%vP{W?VVWNrbh^sM80*K8gYY`-knRCE1;8LbqzQmJfYksjIS8qrya=r?LhFmD z37{Q71$Vqi)eEHlTpw-Uqx8`d?I+*qXW+#T4Azu4)lUbN+YYb?fPuLWK>q<{bhdO* zY43-0SZQy{jqg+1{g7U~hXDmQPf>I8K>X&RI)HY7P5>2ppP7qJ0l>_V`T;rt4g#>u zJhkI1jFq<7oNKdRv%Fz^msiapbX_1^K>A#Wm zf0Oiok@QbW`YuU-g+%Z3fb8l?o|0;53L!R4rz>eh*825t`So-C`Z0cey&mtz@N_gm zNqtJ{rYZjGOU6k?q&|lKiYCEKc(As>4|ZC~aAvT!9BrBaS{#P_nZepy>G-GN{>PyH z0~8eK_@^L@rTHE_O=*8Jci$6(MGN4mj}I1Ygr`1+ij=25JXmxZTJIk$+78)$gGH+# z+c_Af3tTZ+Tj;Mh;iV{_(6I|qn9!BX$USi?%)AQnDcPGF28-xjljs9dc;aBF6tXB? z zjf1=W|Md#I-yEp^9#0$G@BjG`impNb`$Z`nKJ5Ql=$QY_{1l!u=s!`E5}@OFQHtP0 z{sBO8Ka3^#u>WAuQvZt~rFU-#dV$n?YK#4khvxYo4MTm zKcjZPe{wj5p_6-;geOKq%2KWwbCgsf z9>Y z)cVOba4%=K0E5z|JKZ!WJ%TV!+G?d=u$vxSF=(n&l>|*}3xJ5inOX&0rYup?qboeBz_SfFH7x8NWT54q>A*nNf$7$vkw> zKsXFTio$frz?d)$7zmG1y7yo14u!MJX+>e>IbqzYJO|^;V`AAczy-N6M1V2z|ChhT z6aFs-6z|J* ziO_5cO+azvXjne!(!Vup)~uzlZe1MGwd)*8+gcD>X;x$ZWE$kw_SZJ_%N>(iF(t>k z+;3uwEFQ0Yzm}}7-BP==c2DiWTGhIBtf9(+GY+JmcuTY@`-dx8gp9PPNS<*;14 zC-~~(0uTZy z2bcw*LO+J|7XbeS@HYS!-45yf08ax9(H5qdDQ<8qpG2S78mCIf!ITXpE6c{FAfLY^ zo6nk;%^R-F=C$=@4#)@V$~E;yaJ(@(3h7S)J^}b6z`p=gOc_(AOujD5wXJK=nmC5# zBdDyU$(s0D9ESp?=w7=f9!C@?g98O%XdHi+?-5?J4go5FAdtZzrF9LxZ5_=o4+I_T zfe6_{y=91*XATg2jJyhNDo>6NA{Cn=ufD_}4NnV)Fmei<>NxZh#NYy?#w+pnkRvXB zT{~KPrFgD(=4dUdgR*!5lG3DPl1yPpu!lt#0?dgEvI?C?0rmu7Vs?5u*`&G`Sx}7} zddT#giQJ{zZX%jT)F$)@wt#iesP`Fy%^c=>@@9XJKBR4Aw6<1+CydmMlqOLdZo}3{ zG(svxG{(wt#F}UK5whvw#k-!sWnbUC`%1|*eRFzsc*c_NScCb3EZ+G<`u%_0yl1B5Y}}+;RM@!WzVwa1O#d{EZwNPhiC4b)%l_VH zA5*@4-NRnX{upV|9@&*32__%})NBF;AdX6CSEJQh2&6Cv+;bJ;nJCggt_3!ZLJ)El z{Spc#HFMQrtrm5tuPPd`N$Z7F(n^-HJ8&Up^o^H#cI&6|EB~!UcvPvdmPaE)GoAJ4{?jHQN ztMOmb#;enMYSM2=?+4fTC&-Rw$CE5HoW`rs>p+{h>_IZ8Wn{HnQ>m8gD%;g~kNTjRsPELRxQWiy)g6!1cPmYX zmDOk81fzspUs6(E|GJWvBxE`-lQ~Vs1BWu`YFUj`@A#Ki0b^2v>Isua2rL^USc_8F zFXsiAB-6okGJVW2!!gJ3i{u?Pg;x)pqE8(;M-f_ESG!eJ65lMoQJRcn9KvLL+S-i2 zRNecpIjR?6E;K!JhIv`F42dWo9UYu61i+geRH>{q)9YO+Y?RGv7mCOcB1bwReUae^ z8!^#lLpxfHwxFG;4|J+Cd=&ctwK-~zTq(A7eLZs|CpHr|$}@0&C_k7_ID#2WI6mxg zd)+=a!&xH6ur}gw+MR@xSknUJ=UfYLo&icW9hCBMU;%aukeEg50_4;{qS$(x6e>_y zc&nwtJO;SKZZqW(z;HA&Mzq_?%c{mynSg<^EJUW?y>?#56Pq62_KO9t-+KKU4b@#$ zYkeij{OW?5NtIJ8$nG<^>FWADZ>A4^l|KC7XRrMueP-an`P~O_^_j=lB&926rJn#A zodtp80An`vu$(75IvjnDVF!yGvV*KgcOhb^x8UUvbE$D33WDCGWdX_|An-qt5idtJ zXhHa|GDH(bq9$0S7IcI`NAW*k_%zvUFc@W1Wzx9CxXajQWQ|VyQId~O=a3t(ohgFU z)+*FBQGuyOe;>Jk{~nJkqTAJG374DlY&N@9svJ)$DFW#GpT*N9OYL=O(lOSi;lr-* z1ol6kI={7htdE4l#9Mk3`OO1`0iU1pVG+FJet1V8UMAnhJG9kyhv$k4hYX36CPtsl zR>0Tt)A;9kP7Ykl&J(V+&vUF4)|%FupU^&Oc+_-2d%*Cv>TUZ^93R_1b_@r;VZX6k zA+lnfD!0{XbK1QQUTxPpwB8Em6z6vP&H(Rl5@L5bbxuytIEjjL*g;-+3#(7TGSq50 zPgmEY#_AMPF6%^cICOTgV-y`c0_xmPGyJfXyi-onMFfUu^ zzO)Mkqg?|W-Nb%*ry3tuzpo~!t*bSDnyN5`GUn=PB4&rYwAp!&6Z%^X zwOd8i<~Ix=lDMn84Jbwpa~v~LB|?=IKq`(8Rb^Ej&+&wp%BrfyF#Fpt4CDDYu=|EZ zdm>@y`;YJaZF2gv-;Bo#R?VI4!m9N7FrI)PdH&XC*L59v>w{fOm;T^T`s`S-lsZDQ zK+5L;JAqgAuDV{`pqZ>~46^U5aY4b@0=c52;{A%@ihpQ$RDtW& zTS7OLypVq+|7gkEC8t8C!oM#0WAKZxZkkY#!gmkFVj@bB(?chdIGJK94lydxhHWXl z=a5&9Cn~%UXb*|{g4i*<4CNs;`7c@93^X9S6dC{}hx&C`m%_WCy||~C>?-anCdJTx zsGZ*e@17!`$r`x=_f?#zAQhnZ#=k6Ej$4SuSxyzsnM(vxs53$h8ziT}Hv!cXAL*_e zX&W(DC$c)IswClyXpAfultNOz6qZ;{6*fd78c;3?ws-;d8KER;qYJP`UBV?7V87l= zwT)Pt^SBCcg`Xm0-KZ-bw^S)Q2k2x|h$ZEWlpTbRYM)9)_e4S=DuyP0lz#r7&J+fYfIkmuX zf{NAY*kcflE=a;ttSP!$!u)$vozrhHuGGSFJ*! zS`Z*8elAkav93A+o=2@XB93;~nyO8Tz-%pvvtX}i(P%V+M(YM|q^lcSL#7b;B)A+h z%p5tqcl33#?uNbTe0=WS^kaBQ4|CgvyUA0d?Nom)0Dj-7nt>$jlP5mIVsoo+xo?YV z3%A94H+zqluOyYyHOw`Exzb9{deuhHR?_S0^*qh&Q}>02Lq-(BM$u%pSZ#J84=gW3 zQDq89U~<`jBAX$!rCUGzp8E}e!kI3&O3B0nScsz3BDTjLaKFY`V z@4&|)EQdNmBm@HT&0&%BNm!zj$m)PB_K8Gv29M$g@fQllPPc)Y7uzUy6xKcsN(ahd zPZfp+txvVgR-q)W0(2o-$toII-;KLTci=XB8@VmOfySYV2J{SsRkC&^yV|_S*Qx6C zs@ht?$>JrRr5wz0-}13?%nQ65#mvSl)5}`1`tdvG-f`8MjW?|>3Av()#+mB|cJH|U z70jw;yl^x%rnh#XK=m?rZ^C3;=gJPz+s=3)iXFYi=~$ zrv5nmMVR9lyqUR)y~%c`ovjsOoQerKV@{3k#0aEzKqM4w49qG3JO7g6nVmGv)AME5Y80VN5bk5Xb92007(WY85vg%zyPhZ2afS(Ra;LCYMi}yM5c{$XwO3u)gUB|FM1HaQ_Q;zi{0U_8!Jl(=DTu zw$AGKbVA~pNA~|K08%g`bDG%;QlLez9YJhnc*x=&uTpmFpx_j+iYZi2K(f9=->3g6 zew%!RKO)0=Kq=N@q?h#!QL*4r-Y>ftlE*NFW%Md}N~P-en1hV_Jq9*U;YSbmX|dL+ zQynE|5JUbT>kuolGTY4du`2cz@;TDw@J^$t(~7!2M=fYv9EoTB)2)WhZ{(O)y;ilB zyF+yc$L1IpEMzy}5j=2kUnOwk_~_5buhO-h_`&p!uH@`;uWCl*U$3%nx=T8=G^*VM z{MHNn=0p)xj&G8WwnAuE?k_Klt}eeR*rV;y^|*T6w}pEmz2(n4_PU-659wZVy&O3f zeN*$M_E&lvk2ILm6PG$_)7xEPeb~^5@5Z<5?=(D*4C7D@ZbXfETC5#k8@;Z41zLfZ zlckXr(PiZ~<4w`^MVrcZvO85he2;LO={EDuyq&g3*oTA%Ob?kKw>=wqG5TV8iajiR zq5Y%o3&R)DFUksdy*gThs`1z|)g%GwTv1j@M7!dPbE;yRS@hm|HRyFUa6W}3lts|R zBC3=tiCo!H*;hGS$ySD5fer>_pb%t0leEkBU3SLqtT>AQlv6C!JwK-?m66luvK~5R zcub=%VDhqf!WT5zSiu^WR3UK3dG7*TlvlU_m6*XI23atXKI)FgZN&>v!c?4P^&GEL z`$&~d7o}R{a>&Np?Ah2SO54I!IbNrnZ{cW`vzB=KQ*G})|IANT?eDLi@yWnztLALP zr5oh+OP2IhmR8MbzUTT?w?(Fq{de@ux#Rd?_l(^uw_UlUYv(%~=dYPJ@ZqY>P0Mdw z-&C;T?LY`4|u|kqF5)F-yHo|^{e2=QFa--QMFmPNqwVk zgMOps#=s8Yc8f+W>?|PT1Xa`_MI9=}7iJN!I*Jz}2bN!oHiKmY%_OT6;niXAoRN=` z$Djfob@xklJJLI-26AEJ%g8L617^mY!izy0703lW1&mzKQP5W~T)-A!s>380CToss zh{hTFjz2S!b!bMjTE8x*oFGI8vuMidsOl`e3f=jFNf!~ro=7O-*GmhK*GR)A0ZIX_ z4`L@1Btdof+bW3?O0fxcx{EO;tNF*|oEZYz2~z@PDWs^TRkscQyx_?#JKtS$^IOl| zc;D~ddg@hDZl17lX6s$8_3b6Mc*0~I&Of;Lw=WOwc)oZ4`QN8E-nxPux$VmNpKj>e z{fist6w#;~qUK#pKjDLLbereS%XCDNAGU9ch(2cScg6WD~);=q-zJkMG zH~tf&toAsk_};mlm^l7cIBofMXf4rz8lWgqKY`{TQ0sUNjW$d)Eh%M`}HX0KB| z=ksXO0LMd|eOT4RwzGtNm6<^|y_hKdZjtGc$JKyy-h)UpBz@>48itsc<5Vg_M2t^j zoWwHj!wkYA4nTl=otkG^2-dF?vKub7il6g!8#ppb5!JPI#cM}vziv}D&gk|6y~6C6 z^KVmN)?9t=YFNN^na`MUs+AB&mY_3-)PgZd2vy)?la&>TWL>f;*`C~_-l5*B+v|GT zt&Rvfy@3&Jj7sve*l4h5=ueW_(luY64UyjIuqGS;%I!5#;0V-$Ako3enM?4OU`MI)P)YU~9G66&x z{kj%BlQx_UeeBhUGN{RZaXSYX)n)exI(Jy>(0h^E#e1>NuJK~Q0}0CVCGaFrwF^V^ zGv-?w;u2xA>UR*&7WF-?f2`gIr?Mymc93P zZ5+Slp{tYORi6CPS<}0IxS?g`w8xe`v;ACsLfL<*N6HBzr0NHJdytP3xD?QfPitI;C5OfI+Eeps|r=#5&KyxKV3I9Z(LYm!=xbH!`&T6`;v zOT}fr^mIjUKJtYRLM^TiXmJ zj`&uH!Q&1jj$rY`e^0lHo8PGAYvG^bJYW98)D2#<#4Co&DpdlXj=|+PyVs&@R%!|J z{OI4V3yxcmzUCTd`FQ->5dNsTZPw@)S5?Pu`1~vU)`v||e}WH(jgI8~>~-fK*>;sG z9A-0WWd|B&%f-_ypY&4-OIo3(-u+w9;z z-)!AryNBtuJ;^-eI=~!b)H=q%67N)|l~E-G(Uk87Crx#TxG_G8QcUCFz+X0ekFJdvp)F0ZZ-=in`6qAq>d1`V1VT{Yf0|!mmZ>lp9lS>9iTwNP*V57tDAPxw1 z$Tf~>;YAA-gB5SS_DzHEI z`^SI&)YeZnuOE5jj-PJyFG-(0mOgl-_b{&e(fvCM&F(yxR<$x+{{G?Z=?_k&(tq96 zwJ-0`zJDFP@D84RY^u%TPErjJ0u4YTM;q8?MsC%*wcfkL2gP5Cs`cXfyshFRmPf5` zyWjSHAPNqXInV23cq`uO+U6rMf%Cf&c&L82UJBVIr$1&e=!r9CvmwD#+hoRBhahQ| z%_?&$^Si?ohvsP^Dx>4;Dj_-ygm7nwMxabcvU3&-xyG(D8fi+0+QIqNi6Xg%QyMuJ zZRB7)8*ky&pYx2** zZi{oyMfB5rm8C<^zcU;Rb;vsXV@;K7rz9Xs(PFXi<@gxHq= zvOqTnQMK?fugv-I03h=avcbOwm#)%+_Rc1JHhE@Dv_v= zN>r#KDx?yF;e3Tu`ATEHLaO}T6~jmHR>hT}WKw7aGSfD4uI==*nx8DmkSE3S7ZVD-zO%mPvEm!uw$CNXYLchxdq_PAh zd;k}&jaG2su)$!y`kM5IVr=Z^YnCO)*T>eK|1z132kfr=*-6%Fj9SafVvAK|^h~H^ zZ92Bl6N;tl=SA&-#Q4qW17W);FJ!uI^~J*JU#)Dm8Yx93peX&T&0<_Q5KE-6PaYFq zRHbIsn*IdyNc?F0t@y{xFXCUYUue#==QZk1RVTLvXxyXf;dTOz1zw{rB)p{4rEo;n z3vS-)ciW{P2SlYU1u8dZ@VjkN$me%Qq)@ylrV(^3IAb^j=(iW6Pz1%q7>Q9zhojL5 zvDt-aJazyTU{sIU8wm7j~yH(3Ls!CkVRh?CLvoEs4RjiJ=OM9Y<=D-2)$9BSo&Cz-Qfswu_DG03#xJ4@6%Dt`xGSmIErM5LQT!) zU1nl5H<=05omZN2XOS z>dny#6e7r3BCe21q1tIBoS;+^FIuXcmaGWGc~J<*q6N{yD8uO@`C+4E8ixaZ(Zt6! z#Yi85L<|_lA$621#@euS(wnztczgQBcORXzWbnav zrf*z5)?#rpVB%)?UA6AL7ytZv`ox2gFy6MLPKrb-!q=zgkFUA#qkjxN^W)`n9R=1< zIZ&QjyC*?X8}N-;Z};UXGDR8+r!rq3q7(^Nq%s#|Gc8sqykDV^sKNpRWD9M!;Gjag zpdv59ROXDV2ux5J7wNT@yjoJMu%xh#B*!Y9(tOjRD#7n2QqbXdo28)B@5WL{?RT4` zkl6%^T5vcCHw(FiGagd89cH=cO3UA!kgl_Igs8e<|+`g>x@ae9(d{QJi>! zYIRbOg`L74;h>;8E}RlFfHjgs(;wwL1x+>uf3EN;@cM`I!zofaBn|%nBKj*&w<%6Z zTNikbIUGSa-&I$e{VH?OcNAT2jn1X>jKf-uTk9N$z>d`_dX9d{?6O?O9CvwBDYv_w z!|uBZ0v!{dS^K?JPN^tR9<}GY6AC_6Q3Z*k%O8F9p0?Ujr@!#pstL21-Is7$0G`Fm zfYSi#m)#-~aR3Fd9Gpv*k{d~H;L*VIfg=GO4yN$Ea=Bqq)ivZg9|5joq@Zn#+jK=x z<9CZvDBusEB$5$>{@^i*#1kTnfDYhQBt_nk6Sn`!^;WAjidNGotr~?9HM^zxZI|7E zEZ)wYQ$7!a%%5(fXrq$e4U&%SjPzY!+8W6TyW*`?u@6aW&wpM%Cu~)m=_RY?21H%i z?F*l{Wf{JaPwxtk4XkBWQb#(B3+0U$4$Sgf^GenMR)Pp|e+8^0@!RqlqXQd|U^h7R zF=K(TkWKRDEASPGR>x|*%yE5UqvK)xSmGVWCyq1tONUO6(-GtUVHagcPd(n2soykYh!^!8-v&p`) z{<3%NZ#zzu{l@;W<7C;0{f~}6I)}@?M*p(^BN?8Gr`abb=HXWRoWu(I2IpIjHjkV2y3opz!Y1cZ{wXiP|63tGyVCQLQj6anf$N43}X-r_hVW zfYC&*G43u^)CJIz>hPJ=FQ*0I|3n%Hn%%+6sdBolb?MU^4A++9FpJrTm@0vw=!Lo-}J3M_ea z3aca~gZM-c{1U|vQJldbbqh6$hvJOQ|G`D6&FZ^L5i>ME`E%vtbe7g5BU^J{Siym> zR!Gd#Lt&_`dt!?mQ=6UU0$hix%}r>!xgE_juSP4(H<=&D&*NkGkog__FKqrZ!PEzA zMd0OkO{9mpNoL=W&s<07rkzb+2hQx7!@yLsr?c*by%RnBi`Ctdi_CB`|}P-IafqC^!NAga(I zHyV&jA2#pfpVvGuvNz(5{8qe;XD15!7-Fn3PVK0re|AO?BQo?*o6M+~XzT zrN2y{N#FjPisp9iIR1WweGc^O|j0B2R-~o$IJOgW50I)+Ve?1 z=ZuOau}F2eIyx?vESVQw9_=jYDbc=#u**~6Y4rTc`D?doUkv{=|6}_n`5#9=ihY^S zdE}5cCK#wH4Pw8WmqMUutx^bi14V`2SY4b6EsWW0RwD3%8M#DP(j~h(T`JeK zlHAS|D#3C|e+k)Ba-!s92~$#p6$6PCQ-~D@ z|9yw5Z6-Zh9bt;Ua4XqJYc_ONJ}S_IJJsf_1*N-I`2}{5BOHqq*dygQ-vde1Sy+z4 zZir+q?^;cp4Ni&=)K6#}8}tRn0SWyGD-jurXFpALLon7xz3>07VX0`8*>c|&qPE;e zd3taMKjVqatQb88_BqcD_8I@>@PF?5^-oH>>npGJE_-&cSha}y;;mm%YUwz zIQ;gKCHagRtHY7-6x4!Olhye*1EPpS4hCG{pu=sfKN69}IXNvV^WWz3EjsbN`Yf5U8OY)Z|G=&23c(B#)HcCMh zj=2$dq6Y9mY5WwDNl`dIKS*#Mxa;``NPzH#1$&h(HalG|FY?WN2hZ$M4!9uq0Z&B= ze_uA1#k^h*F&YdQBf+eEh-k@vh-hf4MAAWtG=VWD(jl=5%T=9KC##sM3PIs0LBWHd zaFh_VSrv}5Dvef!qpZ6t=O4jN^ly7FVjGRP;>tn&M3$QpIc~}s?U4}?*r}~M5r_D! z*69*Qw$hIP^q`Ts+6COH?E1%*lX;~{2j#coQeVg)E)FHiaj6fIl3-Ce3gssQW#t%M zJQ4<;Z+CW=TG8ua&@_^nadLlC_6{b|2M*OFb-rM=~e(dPzU47vSi%0$Xn|p4r zSx9ao7^l~Nmo@92U$;3GN#A@|i;g^i_uaN-kA-^JJ(*8g6=?0TWUlNqKUjo~*hsVt zGO{sLpo%x)CZaagr0`_ z6P?NJ!d=>}`mKgLj9cUT*nQ=qSzoTN&{ulPy%pX{`f;O}4fq27f`a1m@pwF`W0TIL zFX>N8S5#b4IaNQkaJF`iey%vDU{2iY$A022_gA{BW;1MVSs;62|ix(=aLMl zRC!9JT=G6t7*rA{NrIwfOJ2c~Q8k{79l1jRZSgKJbKU3Y(bMkH?&?H5Yx5L+nfua8 zzi}C;FN!YhXDOvNEOtRTdkiu^$y;I(ZIQYh6&R^9wLrorp{gm?l_RaLC>|9-wHgft zg<&(OS0TYsp3iP?~bu=_~vR7m#NtEt>aE*?G0k6irbOSi$8{b6(4f$NrSi;w@})g6t0 zeq~&R|Hm$;mk)0@m^q>@p$u2>y=sC5b($tEcQwQxff80m)qk-Ome4?-2*XLt>M@bCXGGEDBss(L| z{=38y zme61$yX~Z`bW&ZVn8cmQzGQ!LILRjc0fm?Wg_r?_n1P_#yv2f7Td+m3T^0lFv-oJA z#hEyFIqqn?xL-g|Au5qayzTNPf^s4;w~Y+$Pvcb^2gV2>x)CX+G11e@gfoVt;e11& z7>TBcuAmreHIf)EMlo%edb3y&)a>Cy+y=6Ux~RzFf7_plM!?p5XTwX8znlePevXIB zo8#82M&AA1=gC0B%yKflVs^gMJ7edvJO6VgSRA@xGtu8Q`pLVWKK0mbt$!!x%~yuQ zmHFMH15NLCPhWfJBNE;cC;~n(Lp1P1DqY0aB^&mM`V{l~mkoYm;|<_Q z(B0oUarETL6F5PSM(E6>e{#0hGY_joOK;U`shVsB0P;ne(;7XgF{(*HA|ycv04x;)!;UMbl6g@iCJjt zM+3&{i_umqJ%w!LctB4GQzaAyW~4^~?HK3IAXln>I5k{ZkdB7aY*chk8&3+qH?{<~ zVmVRMpwg*kg!NMC;`6t#-=CM~52?aobxD5NiVL4HrnSZ1N-Zb_s)^j0Px;Njfz^yJ z%X^2_cx*u=&jj2@18Wi`9(B^qYRyC|Ao>x)UR|d!;w4sesyRKc6EtdGqe*hryxHKe zRO`+6_dqV6fkKtKGBI7<%C@MVQ*#k6E);2Fx|k*ADsUIZqNP<_wW}gI zg`31TYNxtqb1i&}(5h+CwYXZ6vrCtAi}+RAWv*rJmF4T%_1t=Xy=H^k1bK?De#x_)mn9q>%GW4uEw2IdswY0i&?i>;I&vQ zR7cH}?Sb!W6~?EmpF6|omW$LLkDyj-Jm7cvd;;P?5G<}dwMOF-D1&tnhc8aGR;^;Xg zNQsYrekm@=?J8b81FcBj<$|#JTeA4S3*)y_UNqDSaPeYotFjT9{ek|cAu`Au70|p` z%%-pN(Ik+B#P2X`>#{L)EBz#84d%o#Cy`n6popX;O84-Uef-OfIXMkg@|!Cs`10cE zyJG2g((mP`uP@f+HH^bwJ1WN(VeO}}07P*Xr_)kE#Qd=p#hAsU$ZLyS0TLXk2;Fi1 z7_;!glkAdP?2&LdoD7C;8Rf~=?rX~;7QI>EpsApI%c!4xxhZLn35GD;Ntu=zVYV{| zQ5m{|nU*`T7pPOdMAgaEJX_s-Nm$ToX_QS{!$?<7_X4$MGr6YRMu$NCcZ$1EPW=EY zHQD9L*z#&#$@yYsD_E*nbG7nS^S#6<6@w4r@8JYg6qR`5#BbyAH^dL#qo1eT@@lQ8 zx15+~Rbg|$U)@u;PkmU!nB(TnXmj~pXoq%3CFeEUYQ(ypI#%tOp_;)p1R8=fYUH}@ zUO{8v11LBRH)^J7r&TtNnOHOJin-dQ+B?;EXztJ&XWMSK5r18K9qACtQAKS@L2<<~ z5I`N$WlkJcSL}CJVIHO^$ZQY6p{WY;h3B zEq)QxH%`{dwFF+flm2m6aV6j_#Y~n>thVGtF)r>1qjJ4YS5X0ozW@~At|>o8|2r3m zqv45$Y83W|d&0ZItQp=jfKv}=a4h9XWaz0yOA^kHm-2MNx_vYbo z6ldaaRree{JxBN4-E;P6?t3K7NE%u8w6T22783ZBjj#Z71&Aeqxq@RQ1dId0N=U-F zk#j+gUt-x9Bf|oMID{MyPBvkad`lo%F9{1uyjh2j4M_g#t)7wP?D6IKzCV7??|IOu zx~i+IkLrHwz3VMJLYTIZQ6fieK2&qSz#PmXps+FUH-#DHQpO?L3?)$edav7~% z9iQ*M4-a<9xuNQ+ZDi!1dGE|g_Ne||JJv;gDW0`0BP-eQrwNXM9*zz*15s);mnxsg9^GDijoTMCkP?bWO%YSVH0YIa(D zkqlbG8Pq9Yf?R?nmmufCIdE=BuTR7g_)8i#NDM$PJkGm^VV@NK@FY}OEQz?CA_Ow< zr=fJbe!t_I`?O!ZMNHtY7>*d8F#c;;r%x=i4z?+Yo$QUeJJ~(DN7-+3#+63g$+?o& zrOuG6Tk=|v&hJ5lb)J8c=CFQT&kX6u^au2;{w<3KAt`3Dh}M4Vuyx$38zY-ZD~qh6 zRk4;xaoT#qYP6Ek|72IiIuw6lP2JZM?C2us(Zt!oQB4OiTC;nrbQUrl8Yx*}&Blbn zh7|1Mr2vv8vn9Zhy|6B#VA<>sprFC8)TboWC7q9bi~v0Kml-8o;n|r|1hzCKY%<vh$wfA@FWE0q-U&e4DS$?4CHb#}5( zJhI9sMu%rpv;Wl6`qFcg&-h)0CtN{bsE1IG2>$aSPKO)xgYli?Xh~^+!4nru#-Ye? zgaL7bI>$tU1mhoe61kBSesBaRO0bzFD4wA2>|pKK3k5#_!2*awh}-s+`7>f$4ETnt6VA`FU%M0x?2iQ&lj0vqY6h&6IW@HGJo-}A&x#vmA)Tvf=_ z4o8)A(j56w*n;~k`z(y5C{krE6B?i<6Qo=d;@mG_nvZXvzzK66s1Cm1S>^30k#Y$b}+S0-(cC{S@4fKgyW zO3*_QmdC76g#^HpLKPAUZB1(5RW)sc1ZOCLr@*xe2sJn;h8=*qM5k)9F&msNMC2f2 zF2_=i129*SBwXh(UM2j+GzCs@rmDZ&3mxPvq?lP2P7MqPu^Jo-GQqH!T*mC7ILxC1 zghigv1-YUV1hQq|h@un=Y1)Q%&alB?C>AJIJD$~$8@O;~0bRU0IC#7^1M=0YfIW|* zA`zcft}GW}h@6)#l!uD9>2A}1Qa4sSP@FCr)#6x@K}Ao-o!y|{z^%`I-e_E9#7eQ9 zU&(LeAJ9FP*iXV}97ESsRSsj;*C%CkN zvO2O!8RH7h=yM91pAv%xI{?DLa0R9Y5SZh2-x>!Y#Fev{Q6tA*eY9c+1#2CKneQzd z>-qfa?|$c&K7t{ASu3{Zg^0(WH_x3a7`iSiZeG51^4hIeu2}rucfX5Q_I~~ED58At z)i16L*rOxg$G_+vuJ&E^(hvTTKs3xKUB^x$7Yeew>JXjcJcQm^1OkG{Mzgx-th=Nl z430JoLL!9JKQm2nB@|RU*!2-I`{Q;acw94JSUL=68!2`r?TosqGq2DyNZ|)h!f4Pn zo6Qt400&L|HbIp(NWq$rUEhy z*>8|do1GVXwt2TmTYW~%nhZu0XVJS?8}>5y81`5`Dc%wMGV@L83Fpt4UkbkxPc#3{ zIvqpCA#RxTZm;Qi<4eLRBcXIg>n9l21mna&#z{|`X$7;=)E8dQtT$cCj52$jd*uh6 zUom}!pW>b{P4eGke#g9SInBGc6Gn`TCydMph=Mt#iBm|DeMH`%+3Rw%g87VMua*# zz)ySG=EDYr8D?aF3I|l}HA*diMshcEv}#fFRVzsxP@EK~y&wY|amcUj`L$#9Jzm@6 zwLKHvQ*EZITa>G^Vy{{i>dZl-fh}Os2L_x5Z+$L|M!_6F!QzpGW=Z)K-oAa$mOJuc z_YWTU>RbPIr2p3?k$ zRi2B*Ltcc0v@nJJha3i&88eoU zAx5smr7<0d*Z?CCQ@)x$#xGPe9gVb}?Ei}L*EU-|*C0W!!iL=b_;Jl&#IG*7TY1p^ zV1n&tyDh8aJJ>rc`iFG5nBN_NNX8S~gy{?77wnUHlV~7#YFlPomI-jS!y)c7P55xg zIK^^mI2xJ=Jr`m^_E_ADv;9Q)EoIUUyMZ(EA_4FzeBtB!h`>9=ymJU=vQt=8t*JD2 z2zK!^f`DTHtd9>3m1*ADspYkrmdBcDu6hEI^0*BHh;OqE+oo+NYzCX0dx|x%#=416 z1IpeR0=iVP?IPJ5gC|F+&8MqtcC@QDOC;N3-KWA4Pr5vbxH}Q|qyi}EiUsgrS+xn1 zw7?_;hJk3Mm56|ixtN3wQHF^~e(qK`el!qYvTpX(bm~0$(4oywj9k6BvmEla_JqTU zf*N?6T|4{eSW_+*OLbq$Y+2Q{_t~A@`HoN}a-GxJeB~?Wt%CXci|1Cb{}SohThZ0p`?l_A-aZ)gSgAmcC#9{+j8nC$_%6_0(3sPjR=36<1q$tNt;rr>*8k z9=0vg<45wcvulr-oKBaC8;fH{9P~pDLWkn;Ib4<+|l_p7#>`Pmrb$FszvVMi!$z)$7Du+hWRNnkipf9y2v5kV3aSw7vyq6@3U-)(7O=X zR#7ioQo~{i?0XUQo584TBaKQd8F_M)d2`2wNu$z+Ny5dPu{tHE1ViI zTgqE)`#!${ub^6-70rqV3!Y)m%LLg^o%xe$r*=*YFa{p_jGigx8P)k<4cD4WY(LBN zvlv{&7#3co94ynET$P2}1DgzmC!vq*)myecg>NQu9e;2y=wPXRjYt)vv$Qai9X%;# zM>LP;>?mOW?1*@hP7#?AXX->@_6;BrH4!G>!|be45!#c+gi0KKIr3VBA#`H&^bD9k zpeFuWoYaiMz^g}qnvVk2&>7vjW>e?#SS1kjN?4zWw=}mlmz!C`(nMdP5YHqw#@7dM zU{NT5)>L{GbRMoLXtBN)K>hjN0J<={UcueciU8h_+!VkYHw8QWq`7|)THD;C;59v! zHkDZhkw2E`x&rw8;spV;E`5Q5mV1{4v?vV?`+a?LZXn4F4c`ER9|Abw5lY%rz9149 zt%wfLHJv)>s9W(H)_LmQ4RX368m-Gv1}&lq{N`hwXtP?{=~;L_tN;!9U|6_E_ABeR z9N&NY&?sEUy zOP9CKy<04GZhz+RH(SdO{RW?(zHi{JW2)X@^7?qaVb$>15m%z>vMWX%t2bGPFC4k- zGn-o4Bq@HL>9TNhIC?R&=f+#Vu<5+fTPL=h_x{IPH^)n{CA(LZJsuq)`p8O<)4vmG zu8rAOr;Wi56$Y-z+j&X|c_{|_5;fIJpyh!vA%Q-QN_dhDfK*BVwG2Z=B2um-^Ejfj zSeOkFdW}e4f@|c#*B@$0;T@{7$~VRsDZH%;lql2dlp-mK%3#*2 zP(4FoaU)OZes=Dq=>S)IiS{>ucoAT*UvZskphs2&}Bppgju{O03tt1Oe%b`j)R+4Rq_L8tw zcDu;SQp_~Y<4GP1{4hVkzs&1+KvMBMio^=xe1Co@Kb+T%<;U~PWFEtG)9L()ye>b~ z{^)KxL0y{|1RUtX2|_b4&!Sq7;#VimE?+>;8RGs#KraWdk@FdYK%VQGGO8Gcd4r(G zu(xTmEb6lfG+Isl$TYtiDjJg7`b^Ne#E5%$e0=Ho!+xiYFR61&+-eKYhPzA6AL?;e zSIl)Tj=Cfv>~j}w*rC67_R?FIZ@ftT#@yd;QlvmEmQ0A}!qZ7LKjv9b7O{Q4XO2>nh0kF5y@c=#3#)AX{pN=0= z^Q1O}V$lU-K$9`av%h-0c3d-7)Q5sR9>YVi;n;X=f9zCDuf+Oej0&3=5X_dAGR-?W zwLD+a@@SmqYC-mu$pCToG+EOj2N@Pgd8rbLbX#PLbDVUgicpiq=ydSoCTyw#4L-E2 z0+}k*D(p2Di&eJ9BsE)=sNJZovpg>0ehCjr!_v64Upgh}r9;s}U)BQALU2?V1BCR> zXlyE>yfD{!KBT2aq6nyKYT<=JU*_Sut!+NcC4uX7X3?Tdrfbnh<>sYx%a#@VCS%AK zNZGJUe=i*9%48PJMP`+aRRYMqt_}E-&*cyriD6qzTN=OU#LzEJ~i0pq1sBM_c?kBDZEWjA%%aUr-b1Y6Pyx8hIA6( z)sj*{nU_j?{67{^appK^?Zj7(*TFKIZ2)HWMIyT#dBleeGS0%AuC-UJ*+T^VsoDPQ zc=l_yuLbvK4GP&A%d#S=Igw?3Tq>z7O@>n4GIYtX!Ra$)WWSQO7(G+irdmaWEJku? zVS)yWxl--QXrEbKSz!xVuh&PuuLiYL^#?sA+gLa}u3$mI5L@$jk8I^asOcoZ!@C<5W=7yAJCDl zhdb5gqXj}XAs7z`;Q$WV{J`blhWtXv1QB5V3SbtPusp4Q1vjZ|S67yR$Jk5zw{C8Z z`26-uB2vL~7JBy4!NzzF$1rgiBx&-g_#Z&Y~z_LG0xP=6&5ZH6HQEs8F9VKLo zMYEH!zdd5ISSfh3zdgtsXjsi`or##uPESvtHHg*e^os;*g2O^{NmE)-oOD#EhO3Oj zAY$@=pXqb_xOv?2u<(%mVaG$^iR$A#UzMxAZQ?fjw(zy$4*QPq!;I;z&`g*aGkwhV zBKxB7CiA8+WB;RrtJ!N(E!?5hsw;$1ey6|{nT)8!l|-@HfjdN_Tik#z6xS=dsJIDl z65bI1Eb3R=SA}0Ny}+}QSdi#2( zK^B6+Pu!GOf$vf zr0^Gt#|wpO$63CHvNgcZ947>5-rz^bjk-Y;Fk^Q(ouVA}h2#QZRgz6SV+!%WsU)Lq z$>P#VsI40nk(uC~m=bm=m{G!nH!NYsg)sxuBg0OtOELm4iW1+Bkar5dt*(_UKQfzn z1A%;5mUwf?GG<{;S?~$V>lS9%G7UBzuXjSik}q7vRl?e!Sh0u-Vqua_0nzst@K|BI zz!Zi$s#Eyp$0Lt^m=5icQSfUd+~xV=D9oP&4cg$yf_cyoz_Lq*E`v}+07vZVqMrD+ z#!Nb!7R|CM)hU4Hn6Cxpfn&#vM(}JI9UTFa&uHDn1&ttWW|c^Wjf==D;S`a)ND8V1 z@KORyj+#DXu9_jUR|PFIX&E>;9JE*Ke))Cl5ZK%8AhUpP3w22|8l6<8X>G*%!Hp=( zE$wHyEkGoFZ}wQYNCMw`;dM*jdh61rQcPYlw=CgL&HYX;^v)GlMBQe=ruf_$I~Mi# zzCZl)ZimI<3Nnhq6c+t*?jJuADcbm047;7)R($2$iGdCY$6|J~H*x`c-o#43Jqnm+ zG2yTTf@$3N(+&R0OV|s_U%4y>Y^>|&D9*qXXJ8Ak*>zj^zfuXq(qN%1z-UoZ_|%zS zKS8bI`ez7o;2_c!a>6`)=e%7U{4`(9w#=*VG@j%bXz&(D4M`{El3dhS1ZHuBjCIYO zrn93&1RhFbdMq09q6LlVu~@vGa~S^`wHX0Ud2-x4?LFmXy;NDYq71p(SzT1d-b2>y zZT()Xdi%XY-eK>!cRy)pw4_7Eo+g|Q8IsY4p`1LD(ZC}dvs&tx(cE1si^}5`+;71{ zmSM}dWxwT=MQ=IeS-`ev?0c>2ETck1W~x7G5krYRfHtxJP^Ti^0V-_{P#vt-PCu=E!`e~<-Qb1X{)&+N4+cFL>a>SF~J?KBKWJNQOXPxkfzT)3SI!O*mwp~vY|^>#bGhMiu+ z4h}8aHI!1_{`rD-4JAWuqf=*orJA9s!qktyPhb@6r5?H1vV0XVRLaWr8&qgh+<^Nw z?AWk-1G{0PVP&%v&zX%~IlboDQ3Q%MI7k?)*=hJ|5VU!Y>zra8)IpzeOw7{!MJgrC zE3MToa(Qxfvr%tczhR?MYF=rl5N}tg0aeLTAvjCxvh7Rh-cq`^bS>$}zdos%R5!PS z8Ud=?HGKjt{D~fIZ{NHYXgpM|ZHypNc$XesyLMo6ec;&Vw<39Rnn)KA?ep_y7^A zm2^m&V%|U8)SeDClY(k)TAL27>}j&6LtY|RAC6|zq0$sKEZ@peIkmh0_BX=ma$PpddXtNG}wmmk6e*b}daA=X8TXPHQY0 zExc2oB|>l;4`-xNfQgj=k(ipPWY*kbh47CM)TT+(x2dL>5Nk2|a+;S|v8Y9^p}u0( zb6MjB_(KE)B5F#uvuNYuqK9hdss6i}mgxgDYu6WI9HpKd#S|RH8k~o^UwCMhhl47Q zr&2~i+A>Hhg7jdJc9eQ(G|)vFkO{O%rz_>ZRoO;()6R;Tsc;n-|D{TQWvDV-8L#N` zI;_(27}=Yw7$z$xD$HaB50Q%L3LE4+>5!l)-qPt%tfz@fhipC3U^*1l6mQMR%+gY* zxjTTOEv>Z2v1n8fY`oVKGmdk3lEVTw%uR4Fb2<(bZ~k;^FqR3Y`_n@Z(`zg}o}Nsz zC@rQL8X&+#27G#`tSR5Jf4lO{A<3*k7nfOY0P78s-q#q$bUF>4QG-XR?(M(Typa*P zu<|Su(2Cc5@iS|#RXjFx^LcZNoN6ntTiScmjb0^;GcT;!*mc|7Et|qJ z)wv0M_@-SWAD;^jdV*x6t=x{+e|43QYAy)UKFJ;><4iz7#!???0m24q&W)6v(_}gk zoS`i~9gH0~2nE#%l{(r?=Z$k_F^)9KsJXCdT8FdF6(%?i?R;>uA7IL-b5V$MSwzag ziIjcQQ9b~QI$g+O(VQeGDFWakvTUz!Y#-|={rX}M>U z`wo1MX|M20zcH+~RCLriVj_%RbbsH+sA0UCYdnoZ2Om94`2RiviaLA(w*9&x-LP(4 zH>oq|-i8pvHPtdfM4WlQ0PqV2#cX!XWNO`-$^Hwr9JGX19}MeOU$|xSGvEmgs|dqt z!$1O;ZT@@YV_T38x!9IB#W(#6b_sPDI2(tc4F?@@TY`xP5`5f{unR5)1+h=T9up}^ zMpANGMFsm=vT>We3X=6?QUUTEiyI;Qb%3VKNSGnfA ziH~3M(W_Uo2fnc9z(?L6`|91_`sjb$w6ykx+g_Uc_5SaizGn!0Z~tSihkc5`S`t;6 zraG*p7g2xv7Cr+Rm;=Bf;*^oXrkxZAI~D3~uYhf%!LL!gtIT`hDr_q2(Af;Wr?e2e zs+q7Kg}AM4z+j~MF%zO#7-0gP1j7=}ZH6M;bKG*L#TN-;EuQ1ub`-UodH)Fj#19@6`-gJZbGO)U$$f(Rs_{+kKTOur zqRp)XSi3-6ss$UZ5W<}F~T#+lC7mV z%#ZWT5I@Er;934Hg`p}uzoPVm+v->ZgS)5Z;;D}eb%H}L6=opJWZjn+&>?7Gz4IDa z)+Pe~qlIrRR*Y6IUQSpNrFg~IqTr&HY+6li3T`$Rl)nn!O6`aQ1lf42dw!`D3Wv!C z1JmkRV3W{m2ot8B))^fJ`w}bn^?mZ9k-LV!(bJY{@mAN&DRO(#=@z3QDUQn~+jZ-< zFS+0%b#tj0W2>XD+;YjapZM9#!@J!=e(ueSTSM_U_L!TuvzHE(B-`$}Z|sP6Za)8t zqdy%vUvhw*qI<4KhX^bOQ5OHK4$Hm-MU@FR4VdL7qI9S(OWQyup`Mxb7#EZev4Ikp z@-YyDg*w0JpVCBURWt?-LdX$~ONR7-!)&x^a6>?*worJUrVy(E&9pxQDAb<;IP_-# z27Q7rv{7Vnp0eDElG8zpwzaNFe zHUPUK3gdCi4B;_+0JE5*^8Q4$IPxS|ANvqk)ELa(2F{^)co(k#ZzlLWF-_=$$EWQO8ML)dFi zQsy)%g>hY!Unu#88+>iJ!I6dm8&MC5Fcr+hl!XmbiI+CSA}e`hQ07V~LBP(|m)w!u zon(_Kqhw(TvN{eD?hKJ{{}WdVRxa^eb8i$bmmufvFzq%mCUODEK%SH$N;{Qc;Tiuz z5oH)O0sya2p#E0ja3;M#!zmu4{#JwYJfvUULBuzqg=rB~MioA;GpZT9ErY{=<*2-P zXEd2qmL@{UZp522c9$Yzodk=2RYeQ746rOR5{Yn|0jmaVD1a|J2 zyv00Jp1N%R;s7vk1YWkEIm!H-z)Q2PT!)urD}|R<6}U47Q(Gyfwo)wkeO%H4^~s3P zKtBQy(iS)_G#k035YaiZdVGr>U#rLZcoAcqG0HcE@MR$!iYq=m7>`;PzYxcD=TlFma%OGHR=x{N2}DCn6?vr)T@>{z46*XTc@XY}!m zu{(sfhi(Wlp}510;R*kw`T$x4p|!=w*{BqgbU>C&wzkwM<}ocl27a@Hki=uh25aIm zI_s)F6DDoS$vMX1D5&OYE@iGtt^v!I#KYoeV|w1mr}*?x>u~E>t3ha;!iu_wpvxax ze`q@vI~M=P=qs^b=HAe~5q%@}X3p%W6{EP<HQ!l2wwWB$Ip!E2sr42iG(P2gDYk!qF^v!JdiW!GUU# z@Rf(oU{a*ZbDpM)k$~8AazW4$!j(`BSP|_8W7r-EU_+V3IjUtAnD*|h z=IZmp4>`1J2@Y}#2f2l#no}Hb&M8$8NHd|zidJ$TD_r1|>addgSV+KGc)%NTmxaFZ;BIUApIyAI~;Ch=Zzw;IJSyp_?sK0b_AHvEE6GPD;p}4R0xD!>;ax zccBH*FmpM<&hPs&a;3Nr9> z)I2e4#%95f-B-KtY8R%rQwb=Ndz<}OPlW?LRi@}E71TR5^^t)-DW!kThK0}R3GUyIzY~u+F)Wrg>6~_+aK7#|IEMn?+}jWhX0<7@gLL6b zSV;rbW>0FCJaXtHw!>O4z@2H4%;|bv)F-Lc9ko-Qs=bwRTnX?UZlfz^^t|#)YbvtD zo{Wxl7dB@;-F|)Eo7O!)_YW&(zdf)dox1e0)@_$DS4BKmuS#4Fl#w}elAUEgi{ebF z4pp8c)gf|qw%n|w>K1`IKcs}}66Q(GCqwbkhCTB(bFcy z4Q9nA8G<>R*$AHbPk`vj@u>J}7QDwb7XIyqYlar3`qk`0K5COuo3g-iyjd|zwpiRt zuBu(qT<3{-%?3uTVv3Ji#C(*+^6^x!;^4T1LLpBvXjXxQ1FU$^#L@5)f&zs-ha;I- zsP`uuk?I>^Gff>V2oO?6jPQeWK1u~AL8?%aKp!TPy0W=F+^MVzuTu0r&e;c&XQVF_ zPe!>UUTO?+-HJILf72P7BnCyJo!AQ1}-4}fM5>@z5o*K zelZwmge0ah{u+ijZC+FZ4hi38tVHV2X$Si*dzldNgp;EP{G7?u6d~uCT~zt&avJPZ{H~3o|K>RJ?)=v`nmKD|Bm#YFF#?zP1MJ1s7&*0vzCX_TE23nmM4>19*t_b z-A;2=l>=p=={5u_SPtuNQ$D7@!@jS{)XA0kvQ+iIXqb-t!e_jT-z)8r*>=Y&iE&D< zkQ4cp5OVPL5E%t`syUNSRwP+2nRu7U#QS}|n294L&S=o-k+KKLD|)8jAb5quh_l=-p+KclsbOf`Uxsc?Cz=RChwBJ_Icl z$ey%RkZGETOH=r{BVrRCYtr5ZX$AQa!C8&~VwJ^g7GlH$zVOXTZ^#7ZrPIC{$VVk@ z*=`Ni0lV(`8=~@Pp*}_$903J=EgH`gyyCIe2=e;Q=z;Jbc6=a^OuK*nikCAtm2tN0iU#JMPR||nq{8+V z_OtPX5-rUc7;8t+W)jTtxXvD0@%|rJeOpm9aUdI?IjKKPMoW%8ULP%qNXTwua-ih1 zAyY!)bg6jQAQ%A5Yqet0TU{87r=iqK5bD`Yy(0ruq@Y`gsuehGD{BNcN_B({~xi#4-D);&-L)N{@iW`%rlp$U5E)$p8`}G$ZH%b?#_nP;KcS(EYz0tekcO}LO z-aV!}y?YX@)ii)_5^u8W$e18sGal!$k&Ft_YY&M^G!jx!Iu}9$Zwm=wITRvd{hg14 zFOvYF`(Ond;!-X>@ry3bSV1s=wGTzAk`^l-P z{YI)#?N8$|SV=}qD`_=7nVwFcNE_2b`FXBs1}w_5Z)Wx+5qd`IW1Cd@NCi18o%9h_ z3Q}W{GN0xd1uRx0D2Y~{(d4Z8*j(T%#Wm0Yx3K1Kjt~U#fwUmyH1r?n$OyUsT#$FW=5XFAG9BRJi1H!3hG>dK8hVayG@AmD(mjslJl<#BXWM7rlh{*!#r%r*SIJ+s znuJ1vkDFtbQGTcSjTU2|vmk6~(-ms^npm@UBx}a0hhc#v(2j5@m_kp#t+vMZGSPie9F^mR zLbWyjr*t~m+E3p0t_rT`^~ShtG{!1%SEUlSc#_FdtHssYY9U`$+&FpC?+JH zwUmt&A%Fv6@+FD|_zZ-A+wDM=3%Wec=R=_&Zy_w^6FWTEQ;1Jt+vAFiWx%Tzv7*Y8 z^6T;`SqBwBjpe7AHq?rY_{u|-LXzNv$5AV8eVTb5RZ%C?`*`H|UM&>YY4BPd%#O^Q zZY&Tu*r2vBVPB;DCXLER1)F+ERT`7aRu9gFB}a8vQF>cEISB9gBz@72>R@q@)QEIf zyzOmLGIC;?Amqg7-Yw|V@8s3q?Y5c_NHqoQHLL0uYZBCw9mrLu*H+VmP16WLyxO4D39Jao(wjVl5W{9har zV50HsBx`}VK~{3WN^3wnkx(GnNu3?egUIs0Bph;RnO$QU{MM>SUVxn>uj;6ZqENMy zlvCXhjvlarN6Q>^2};m?oKl_cY8&USrb@1Anj|~t0pCkZ;3p?jS)+Qq$;T zb5pl8v$2@V=JgI9JGRv>C7D=E?+V^@=KX8i!6RmF1$&xcrj~izDdA4D85Z4~#K|C$ z7^t4t1&GN`ix8sl2t$hu6kBMqWvU@eWM{H(lV7cPe6WGC>X;&A%A%ml&fMC9TabgG zhv=e}x5zj7Zt&ln+sp5jA3zV7?)QB@`!qUH{ue`(@Fdx6E|cLg<q_@GjCIm(5bfKARz@WPBza&*exi6HbGR)>-@{olj4mHd%~TgF@Ns^~u03`1kSn zHU1PBONaSC@+`lrX6iF-GqI*!9881=W?vCtLc@f@DEqeMa4}cQF*&)l{B>{}1DCPE z(cY7TBPVB14?>iH*}AJ(@9fEJeYvMbL}qRQ<%W3U;M@HFPMq-wpoZ*!$BI*4+^}FW z14y#%Sc}bP!QXV}^O4t%+l^dP7H8rq$t2I+-FD!DMQhtjk!p$$t&A<5ds2wVqPLa6 za59)&KG%Z(l1@2HW-DRVrHHNe{)g|lt2>uz^$1G_CYZ;=g{VceXlwAW*AnP;=bGF#~;z-e*KW1(U&ZSZUNsQ;BCSVfe}g!k7~07Nz%>PHT0@Pv_}IM^jmSss#=GwtkqZa*1UaQ)@v!4D~Q32?D2k4BO&LX9_c-O5|%n80C0Nnq)2{* zj=;=%*fgH8KKGZ%ZhLkelj zi%G_gNW|9RUt;f&9(R*Vxm=1{i&8u6*1Mm=al&k0bMRKmKx_2)G$GbqlnI_a-PKsA z9@d4Z*4Mps)7iw7t)$CElbv?TeQGPt!_?QfA+rd`}5b$ zT^;rQX78%!Dyw$c(ze@HSDsyc*Ka-1!0xq+p6|Z=*>dHD%e$Xnw01WEjDvG4nAd2Z z$JCyi95~LUP0V_BtK)L!a`r}MC;M*D7~-!|%=m;Eo6RoLZ9C~c={k84x7q(w=Uo^f zm&-kcTd*x|zG?i+ug zaGm~|sOLAIT=lHh;a#gL&#k)ax87**qrHosUv|ZU4pYhNUfm|>B^l85$b<3(N>dowbdopj52uB9C!QL9Z@oGUHAVZ-)sB@&$%EeY6c;-YNx zs?iNse+!*C(|8M*MaK}*eHoEHL-1PiQJ4&yMnvL+Fa11wIsOxQS3cCI22C=dn0nFV zLPxBsiw%&Mqwf^FVec5svA~(fMcE(tdz?WL^i#YT(f80hJ2-Qe^wm2K^vhXkJL|=B zb|pCQ|M|m}ai7^@Gdq0t)RJ(fbJ;Zmi`dJHiz|srSP+b+u6#=%F|z)~OCW;WvbkgI zI`k5O#Ui>}UHpjuk;2!DQ^l8xZx#)=+ID(BX}iO#ljJ}WVVw}+G8XAbMva-#5r=9q zH`fB4{dp|p!}+m1o2Q?6KjDAAqw5shVfUDubwj@dxzxPy<3gw283cbQSRV8w`ENLQ zHNNQx^zYp6)jy;Dzp20e@)~cp@*a;T)79I4-ZgvhWt)0=-eUE5?c`IpbzghO+_6k` za54Fi9M_dCts32Q^|xc0{N;+1$(B~^Bp(~mzeWG$Zx?zNJ&O}~C;k%tF=J%* zvkvwzx;OQsh7QA@jl_rdRj-v__{9X~1;5%HGhE(rHa1Y92ihe3qc_BE?Y-D_7~P`q%( zrVVWuZR}s&vo6)Qd3iOPc68Wd1Fc&I#m*yUm*3)co}X*Z2J}c4nfq-cC-eqLM7CV)}oc@0wQf+h*qFY zXaj0P7om-)AFW0`XdOzSKC~GvM^%(XY2-j1$c|!Y0JWkmXb_306CFWj^8R575jS$8 z^HB~pqYM(zdK5s9qr<3zwju@jkc@1|gCru^UyO!O5M6>=P#z^vFKR+b`eY9BJsDCm zkh9VHtFOEKdgc7fZ&EJYaor^!MzjUO<4FHEzXk5x-Bak)nR6;M*g=LW4m1+n{(ns0 zK#!q*Em2NLojdLeixqZ6;|gNw<-70cktgNN^oU z?5EI0ko4a}B261n56Ppte?}SI^(aEht6-npuaym=3?yGmMsIF(PGN0jFIG-kQCLhXRB3Hxb53PMsIF(MrmwiG9WTIATS_OK0XR%Ze(v_ zY6>zqATS_rVrmLJJTFFRY;b^1E_ic6es2`Ts0>}Z<_^>X_z;=ch>9E zw_O0Jj!2Wv!w&76Dm6fQ3AWwy7Ohx0wB8Fi|B{7^XZEJrMJsUr$%}edE>S&_wg%~? z{Wz}gT{L@$z5qetlEuqcq}tWF5`M|D*-N^fUt~vm>{p*v+=sim1_aEx>;cFDNPdd> z4Cc=VMrz9uU0BFC&` z0#L9(0!~5)oC8<#W%vaC4i(8ifsr17k?fAo`>zpB;-L6{EFm~ z6LlMgXAawiZWgYzo!AkI4FS@*aGJ{!o8i` zlYAxlAr#^c!%&N(uY>LI3?#^L>SPVcO;Cq@)8S!w7G5SA@*8Gno0D^qJB6KPP+ZTp z_6hDJxHGuJ3=A^3ySux)1&0I=4uiY9yORWWmk=ZnJi*=ba!#H5-a7ezxczC@Q)~BL z>*?;=Uw*Z^WCmlo{|ztZX}|1%M?#SYLQlpE_Ou2{jdx*1J>f|(#TPBoE;OT$gruQG zF4-={P>n>o3mATv!<(-RX9;1}nEkjr+rQ5kpF(s##p6QV=7QIL(@C$uw27&fmMe<6 zk(7(XbFv51jx_k0P#=YAZ<3I5##Ae@$vY834Ou-XC)IYwkJIA{H3H=)XmGsl#V^o0 z!?)Ylb|yDPY{A<~tEL5OI(qWf)OdCazEYZLm82&8{=(M;zG$dO%v2DCuyi>BZjtblE0+%4CePpX4X=ynI3cvG773&MP z!86R*IrSYO!~^l=BmW)hR3ZF}Y;rpqH615Pl3sFMb3CI3zOKRvmHvp4+b4e!A=(cB z>xy6|TcMg_Q$6|LHdsB0LNSM`55&(=mOu)$`dtSc{s|*X;q9xn^(ckpzznnELhT04 z4#SS<+w+Ix z@p))yxePI=K&U)gd0q*+aBgq@= zN62HsbMAA-bL^#AXYS)i{+bb$W=1CsffC+wZ_RToOC5-0hDzWR^S#5yq}SQ>x$u4x z6NSHcw|AWSSx)@AG1SJJ3@J*{2rF*Fk3dXq`DErPN?08 z_P327-^0?L9niw>k{KDPxh|7Om79D;@N9(3Qrn?SZKA^_amk`hB_0m}KWJ{@X$WFq z&=R7G)Pjw&--u#zQPrsV723{Sng{sOP5qnp(Qq~aW+PGgp!t`yr>OQVQEr03QKx+U z^faFmL8x&bYG(1Y3fj7;R?*kp!Ztw}SPSweEC$*x8H^*U(@n+A0^IES?CuH+aKr)* zf?Z>l=8UBU&a%jh$SJ^=?~^}~q_Om9Txs9~x)0W~m2gh~&*~(LzJTH^Avg;3m$(6y z2)d@4gMyc-AERz2)XNyk2~yqR6dwaZhQE=VLHyEKtn(7Lz_4}(T~(jOWTaz#$vFjP1&SOduPWO$_*ymZhD}m1<&eKKGFJuoDMHX++XYhcMdU&2i?8hnsa9M+$C}z!` z5;O)lm9>=&Sg9$gxLE8==ywr#cirS|%s&p_9{F@YR&=?mXy>y{If$qEAM8BjwQeIPac(Sx{`; zOW$@t7B*t~EY8f7+vKmD??mQ3hI7P2Ftw|MO|?SikFAkOS;TzH9|*GgA2J;-$<&(a zoO`Hm?!HZ(n&n_0{py3buv~+0uei47vS{eON4ZkZ-INp+V{)x7(p+D$xC|`R`Yw0( zA_y|XAN3N(=XL$Sc6i*6jEk&?U}6-fEwCWwzb z@DwP^eus!lbJC#Yq>YQWk)B^>Adim8k`OR68`)Z8V%A=sUG(obix_QZmq<-Mkk4)V1K@1ny8Wfk@q_?&%OCHKx>u3uJchJkz9p z*Lq&t+K|LgrWhb7-tCy>qRAXq*BeYyImkiGr;ABeIZH}su8LD;M43vQ^PO=2t8hv6 zXcKlfs;24*W!zqRK^Yf97g%ZkGlU^gfIb!)?HqyO$f-Z$;Q8>7X&ATHo7=k~;dYFk*1!3Se;}^0C_p~bmrWj=D9{a}U+S(v!ve)G z&JEYGL4HFg?l=W8qh;4uErVXQdQljl!k}7UjKq0Ld zubvV!2BCqiPHD(qqinOLLmmmJ91noEqO+--2Hb9G!@C)vcDvW3)N0P7@v~u8<_(rd z{c+L=N@SX=CjeSSeSuZkBpHPnB&3B~E*6STBs|WmZ&m7#>&Kk%1AdOkkSDhuzU6-H zFpRoR3H*RD$e5k((_lDmnPT$R9LjL^Wp+L^^eP!dav4$t={s)vP zvrCfpFB74# z3`%w(Q6qoY=-nmE2kx8Cu>y0{xIk%;^6-SI&Lc_y$-Mpu7v~!>5yi7HxGFrZVGE7O z_fnm40^!P7WJHwW(eQ_6=rivZm_!?YZsv4;Ua#mnS2E0r(=wr{EaE2OK!F+&S$)!K zJJD@(s?zt0&~N)zll60ntLy!}lkJR5J+)6K{3tVrzg#%;pg`9NN!JOx=lbbUr}9y! z*KsGwQ75hEx46+P9RV`0@CI*= zlk9MLfj4*;*gW!R6tq?OhPn4rws7w=cET4{M%)a1C{yLbwG3iP7CspMQm_aV@a}59 zB6S&i=A>jvV?Dp|x829kNjvC!Tin%99hAR@IT*6ro-x+$&Ra_kUnZchE6`1n1@2u2G%+bjk+I&$+3~kU(Cks zAq+8lnp!XP;l@>r%uO79gF2Ln0JT4dR*W((t_~Y^1k+X>p}bhgmfqFWY*E#h_3Tb= zbJW+B_m6%c!5>25$hzI}d+b2M(_O*t5S}W9yHsUuTTS8=xe^Umrb^fpNTL8MzFb?Z zu5AJ;Exo8xElD}N?Jtf(2}x7jBk#ysaqAw;I8&7$=dM^qCBRtnI)$L`}vY zxkvNh#LvB$!|k@m&=9`N7&DcmsI|OeiO|mJi6Gw^8L{`-A*f17AHaTNvU)f5?b64v zfujOC@!Kx?eu%%+lf01RptE#H+@nXs<2^Z*Q)hu~_JZpAn_)RYuq>-~%OOT=f-rMAh0Xs`bpaQ##d1)TtQbbu(#?nrlWO6K_^%rwa$2 z*56i^*On`Z6)eh>dmQHQhBnrq@Vg!xiZj4@lDInR&p$~$B}MJt)gXhpYIR)uXOOUU zf{u5`;qI^{6i~--gJ49|&6B_mgBWj-S%!0WwFzCtMH*F`H4*60F}-b0%XW}wL$JL& zSuj!AM6VtRZM-WQ^F&hRDtN=aQDeYn-kX3oBE9}N9k@h}ycD*daf29^FbLiyr}D-s z6(POhLux-T8D@_{ZHK`;;pL0KHaH6$6c`C7ko0R6uVHl#vl8pkMQSP+qBhK_?a0@9 z_Yy2O!6)VmOlVP!NKc(jN>obkgqb7_SPi;DclY%TKL&P|uy80(j7}j+2I-Y3PBV@G zkq-wCZ_7?)_vdO3A({P0q8B`C%&4FlvQO~n!>(mP3=-)3NK0i{SPV{F-S|K~aT>pt zt-RKsoGT`T02!M8>%+EQEj`%vVt$cN9P&fZ-8& z;~5@&6!a{GFpHg;FQ-a>M!`Q(*fBgYu@cu`41Ya=BDHP0D<_6DNq&!qpuAZF)v41_|0(BeeiFJ0R@#WyDX!>M) z7#TImpq;PYNg2@9(#0#LFl3_CtrLI*-WSJm3hr*F2{+!CRAkjr#Jn5KTnQT_?+fVu zqjQ>Uxf+Yr%>L;I@b)-D3q6oHGgNw1F4we!gm&d~m?pV-FI6#az`K zGveIBwW>c3e)*Wy#3=vND>hXc4zEcDQ2k*=aZNk&^BGf&6!F+pLx?P+?bek`m40NZ zT~syQB>vcI(>?NwsTC5d=CS+1rzzH^8Uq$eS_*=F>=D`ylvc%sXt~0tZ;9_F({sOa zG%_coSe&6Ur{x-d7pz}6({;W5lHv3TQ-b|{o^S{{3pct42_j8krbW0MDJ$!t6h?Jr z_XG#+#S!Ybcl4FANB3OH>7`b(dE25HO6us?Aua0qP~`ZYqJ3?qmL_nk#Ew%-z97a>0`%VW!Z=rvy0B+dpsz6(^ThR==a>5sdbqdroSJnZ@4qT9_dkYf3d|M z6}ox$X$Z*ky~lQT-h2kBJ;|CE^S)XXlNHBWvA9@EK6#>u*|fxHmy&8d|A4FNt-2Q*4a z?x9e4_oHPS)CE0>Z<5y@xwx17-edGStu}L%q_j7DeBnrThlFIWDNpG*$=UN`J!ae%IFQp0_T0}D-EMaUg=Z|dm%of!$PT@`E`g^|!4CaxF`8m50I0}w-m?PwxJHF`< zY;J4gpbZfW6mID&sF_<-HmySZG$o6S(VIzih&x$BcrDRW8H;8*KJR)ozk(##d0B$|(lUy(aau@lHZ z6p`=_<>rY_YB64G!e?>vq8{uk{YWz)uOtmhzkQM0Im-hl*f)K_P#!C`(X_j6HiCY% znW(A3*qkY*0n3qeCVF?ujp#eaeypSFbAcVT<&=G6o(IgL!P%B9bYsZT1{!mVd#O)S zMv9=V!GRu6+V+n-afFVm<=n-zDNWw0%^hLTTjWte9W*8)$G3AZAB?W?3jNr;Yf z^0~43>3Z*X{y)^ zS0C(mo!2=F$v2oqpEl^#ip0y4zGmf^l-LODF2W zE%0-Uh1kd#6zkXl_NvZZ&Lr&wmGV2G65Qj*1i1T;wjSO>C8Nuh6gwf@OF5QxWZhkL zh3)f9?x-`N@Jc=9;1hlZt23s>DRRkRjp&T;;6>S%^ipQ+4+WF-_muN` zXbk{ANv<1R{5#tMa(%y?y>gAH2Uz#3^xW(voF4mh`ydbMZOa(cA3`6!-1DX{sI=5UOztb!B?q%?A)TBMWYz_1zA5)zW_+yq>XLIIbhWRc#Kh*4JK zwQlUepH-F>Z)IeO7nkE4dfQfepSHU^YXzmGg!oONpXpj{b{eNPPNcqSVRz)NY3w^^ zt?`1aw`1d{KV&xd&VtM==9_mtn~b%=?)m|>MW!vds(iEK&Kd?0wfpuB?PYXzjKrcA<)<{KOIvLu`()LVcv_vj!|Z?Ko3N5jr&yuP zUy;ab#kDfVRk%UA_({)QW5Hobpf=K$S1~x!3~l^+f2X>hX108e*#LIy`Miu>Sm6$50&yc{$U*#ERDdZE`XwRdr8Qt*OLv;ULL; z$pbz<-$6lTScKF{&2tm2uA~D(T04u|UdT4vvU1(dyr# zrZB!SdOzy=XZjiU6!N*ec4ahd^c;vH&nka8l?r;9HI9jDvxvRc?_a{N`cQ4PM9F>O zMnglS^>}}2jShG4SnPjDbt8YMzlB)nh9ornR?chLQnjdf+1xhClFitvqH^a?DrSDH z>{r(>-Yf5ZHo+w}63es^WY(86&k>4K9}UegG*K=|5$HP+ncKmC|);bLgB~lP^!ZX0maux3Pf1g;kelX~Nt?U`xBo??=h4 zR=SVlX$U=%aEX@^J5c9+d80_u*jLq~vhpT22Kti#{BAn~sG!#`amN_2wZd4s#bNzM za@WR_3F7qHE+U*IqF2YP%y@{?P|DrdI^vLO(V}yMziIP*Q{%=M!sqd8Npdb?X7|ep zA879G-d=}NAF-GXic$JwvfP+?I}QPJ07hqXbrScuY!;VbTOojbSw*8fRjQoUt5aN& z^cQwZ`H3pK>Z!`9DusI0!X?w8sT=%-&hM8f1A8Zg&h(`h=Q@=Y@gnmS|Mw;`u{1T2 zMi1g(DkPzctU!h{${!e>Y!L!W2~R-7Jf}|*RBgROayfyrYIK7B<0=Z(ym4YNJoPG z$orkfH7c)!N+g)#ZZ=L3|~mLlOV1mRn1w_gT>P72DT z;D3C6M{QJmfF?6GK&k0LqHa3H0hw_1DbcQ{A&kBvPW;h3*YqvrU9)<(iP<|0MzhG$9yPqnGy5aUEWTi}`JdH=6F!;1pah&mT(~bZl!5vhIZrxqV*s?<}dY`zgz11KHT- ziHfM#9D6~FtD6xU()PKxLfQcfe$5Y#r^sk`g8`#eYCTJ4w zdK$Vs79R{Hl80ZPk zld@a}fyIR}sh%OYik99iOUxUZ9JDJs3QJWdR(0$-r5jN3V5k6F%J#g|oZvc7QT5jM zxk{Jz8PLY&ZK^RR$cCWtwfF1E6pC35Z$s}vco+ZpnDhdY`^7kmkJjVaT5Imu(*-F- z7ST$lm;B_xPnmj)&_yAK_08$u0i6>l8MlkLVNRc&e+$0I$kuO|%>Nn>U9r$|Pec`Y z={f$KWJGysOaA=W7Mb#=YC!S9SUzg3;A;PrZkPLoT}>?~8Tt@8F59&Acopy<6p+`e z{G;p-LDJJBC(|E^cVEyIUcTyaThVHvmV!NFDCWl|e3Cd=weJ3$Yy+som3~flTv=dK zCgxxDqlO{?5r_-mhWZI@BsVfBvFJqUbO3`a!R&rae~!dZM&?m22_}tB2n8SMhT8|D zee2k(jk{fzM(}#j_NSBg=(9@xoILXgFD_2HyRi9aO3UTuqbIJ7>wX{l<1{3mW};;} z)pzuwogsv^{jy%2o-A}N99U*91QPii9C_Ui6r~tX5|C(hs*rWJmcfN zvyd#?Ra3`vgJ4A2Z))SJMzvsnIo^k6jgt?LKDS|HY1|cgnv2^8zsB93l#Nnw{*Cth zH_pWIzciDIo3q7xb4xb{C0h?SXMl=?6hOtz*3tR(f$^0-dWE1oY@MAXUI`!u2|f-W zhy%z81cP`$+#qgdAQwFlNdFq9=xp(SL}=K0I9M_$+M2sLyE|KX0JNRmEC8$k8D}qm zhcm$3)WQ7yzbGSskMnys057YBt+lNOz}n5$0^siY-qg*K&BEFIfAVp5WB8vG0X7~U zE`03lUS3{oF8@l~#lnis+}ZIpRP?=v&1smssjW9bN`(mHxHQi?|Oj{ zUe3S2@v3qEQ{&|Pdp;nT^PgUE^MWCN9TZeE_hy#hi& z|M1{-KFHs`yn4#<5AAh(|E+OyLjJKHuV^0V?|MN%FvmaF=+&*iY6F2@P558!b!WbU zcy6y`A%I=o*4OfNPXgH0oSi)YuOx;uPoQ68gU*3{hW+KX(sPH;;cGgnw1TiAqZ=sVs&1{{Rb4 Bp~e6J literal 0 HcmV?d00001 diff --git a/Release/arm-gps_freqref-030.elf b/Release/arm-gps_freqref-030.elf new file mode 100755 index 0000000000000000000000000000000000000000..367274f29681dfeb149ba262a99533fe87747475 GIT binary patch literal 302212 zcmeFZdwf$x8b3Vel6%@DZGqfqb7`@63k56};WR0sX#l&RD;HPN!fF67L0l|~_COKB zMQs~&+XfJUT@}>DXuYjy0GErpZUV9b1r5RyZ@3Xw652H9ede^d?C$UL`|JI@|GcMg z=FB`Z^E@-(dFDAYbDoptDbpMTL7?k@Bq~HW^%sPsqv4*@Nh3re(P(5s6yyy>L->3& z5K5tll)V=rd`WmF#9%&&QzoEGKZOXs#FzrPnE$816lf-VVe03if9K=0@FyT3ARr(h zARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(h zARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(h zARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(h zARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(h zARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(h zARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(h zARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(h zARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(h zARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(hARr(h zARr(hARr(hARr(hARr(hARr(hARr(hARr(hAn^Y&0w!d7oIui5aJ9hof0MrThWzIt zE)pT>tAjLr|L^OsqX+o?H~o4V%fj*NGI4y!7$hx&>v|b{*8m@U{~g@N4f4ERXMR%p z)3R<9_a~9nRBLvcr|GpDY$J{%v&m(u^V@V>Vqm#2tx|2T#QIpewUG zrV?Y$#@;~RCDZA7`*Qp@~|MN~o=r0IK1HdB<+%ex9Wn9PMx~%JIHDIDiB1BjzH{nva zy;DODTo2Q;lj?o=z7g&pUb*cV%0<_mcH>yc(I10ymr#^Oy`t=H!aUkFrdIEf+x70b z9+H{s)_X?Pl8heiBl-JWPX*jnrn&CZi&xuEH|m#^Vfuo(OIXte``iV{(&a|&L_2HI zd1jKB4@+*h(C8SU^AHTthB}Fns12|$A|t4?&2}ZC_gEMdCM-ld(M1%Gh-l2ZIt@tI zIp;!%FFCZsXPM)fNy+VV-8^TS=WJ=Gbsmi^6{gH{Js{mpLMgdjX&$I0E$)kC?}PrS zNk;h&C*`=SX^!jTI4;D!0x@JF8Lm0RDJ|aaoasYmEb(MBbcr%7g)7Td>0aW=sxycU zs^fQ!@|Tt}8K>HDtNZv&gecX=G-Srp(2Cib}wgk-m(WH&K_MnjMaQ66M|!%n$T+;B~7Hi7O9zgBNX791R?l#I0dRdasdcfI;V_H? z=netCFDGG!LD|Den!g`S5`(o*CNbR)EeVjtd^_ZInxC%FZqT*De8)nfSTC6Hc#U^dy^R0C@z7xjp;?Nmc6#0&(E z$smUBgq8Hb9b~YUV}o2oJeRNV+yWgyw{IBhrh5b0H`=z9@izTos7D>#-nF0$S;sJ?i!ETUJYRziSMYGjzIgNPYS@9 zs?&HB(7tQXm+SQt-IcCN=jd9P>vyAqDf1P+SG9)VRvS7y9Q|m&I;`AP&WsJ_vI<|B z(-1@^>D{ch19G+KpuK09mML^ef_ZGAtFR84=iFWBLisuKw>S*Gg}`MClry69P|jLs zWemY=w$Xw7**?N=av@9L?kx@?&`_ffwm~@!`q+MKn8BrCAlFh)h0h9smt=MwuvKKZ1fq0%ix=*p9^I&>$1IxeP4ra^2a#U&mFjS4w1FI*2CwD}mg1xk8|P#$5=01GJAh6XFtw`S2sI6!Kr@lKlMI%C%b6`8}d7 z4FpiPai2gK;Ko6?moN7!SYIx&n;Q+`iyR5zF79s-uIK67xcv|ha1{`CaNj`qIQJxk z?R@StToc4Mao<6>l&7ra!xrumP(0j12p{Jt2p{FLAbf;d1>wV70>U|*3Bm`s5QMWh zD})|i)^xrPjoe>=GL@SI;ayxIgmbvV5KiLOLO6>X3t<&k3*mHbJcOgTJ0P6Oy$)e1 z--c>V3-L+ZTM$|~DTGzrY6!=0H$gaxyA0tlzGNvk0^%AD<1>PbLa5+W5SqA=5Dw?j z)^kdT592Z+%;C9dxET=7z z=W{QmbAa+)8lx0TYaqOk#(d7DvGgy~82_F$?&--i?!}2TZriamZqMKNGM}a~8b^8h zA)dpYbP-TqN@EL4BLsT#UOEa|@-|Qs-N>AIn`*{*U!{*2PfQ?M1Hty76mf}A8s$&$ z?X)RQCiW2>&;pJa^J=itx5t(^NsQhVjK@$xB9;qt1J4f`JShym9Mob{o|3>k-e{Aa zvKd`Q%#BNQrA?S4%&zO@z1_o+%9Vo*z82e%Q<*RmH`p|%^uA2pb2jp<(YH{)E9lBS zuMGrAsQGA`m?(Db!d58a-B$>dF7D@FWP=Sw*ZJwengBnrDg*q)gZ%P=pDlNXwmqnT z+B5%$-$Vb!FVUTe@LGWIOZVjYCP1CfI3iGt=HxEbP5?8q9(wf`ZUP#Kh%Vf>-*cW^ z6Xc9UY>?>U63=i6z;+1I)fo}ykPZFJJvGdg>wDU!KQ+`xJm=88=^(bfIfXns#8;+& zHTd6sw?XfBL;o>;z5S?E9!c!00!hO;V$xedRGy3w6L$qK$I4L>o&o>Hl}32{U+>>O zf--5Qo0#QDJ&i0J7N+1L3YB53JMZ`d1EBjN- zXZkMojp^qbc&ocVksj3E)ue68Cuw^}6QXJR$tEN=*(LetJu{;l?PC_|H{0lA(tN{; z2EC$MYd2ZD^kGK5Z_Qq?$!$`n$geHG9vE!fK>*jZRJ zu%t`J+s}Nkn>ldZNGpYOF}A0L^hs2RB18q@(t5p9M*uC}{mfpo{leJ6zL-y#K zhVC&msSxcy>LObWJ_2>vrk_3x8v4A=d0K4MqI&xlheC@=Y-i~}54xsBMYo=%I;C4) zu%WR0oX9HcblHhw6uuOtJBcC`{x*s%qV~7z0$Q;jS%)KW7u|X6F1d|>wek@A{fMZ% z6cm+QiJ<)ZrAr*!HlQ*^cvmp5EGHtekb$3c7qnDheQ-OB>L1c{fEYUu^#tDv(*DYz z$S*BF5mD`p@5?QdLmv}IJDM*d}A@;pkapDFJU9Uo(8S=={U&ii7mx9FT(=kPt_?I3H zwJ(PrT^;CA!Ez}o&j`O7%qurWerqQKlCDe8o0o#fPY1>Ur?qKu0QX1i7X^q30q7AO z_(~@Vd>BL}DAE=~)?DkZza4h)c$c+sDJGEBt}jI48M9=9B5x z2bDq5=CRXI!Efh_w*0|{&g8{LPaEM&=-v-XHs9wkj@UJy+*~mYjrikya?2kfUll8# zhHknrU-W#Hb~~gcv65PJ)8YAK$3g9%AHXz75o6dP8tV?v&gszu1j0`#^uY=Gv)B+Ao=) zY?t^m_|+QOSko3y~n7b$p>ql4@;`sMxB)nEgpfALP9?*4E@?K=aMRb$N zrR)-IJFd;}OS>`xvi6?eNV>9NCQ$*IUmVz~do@@ZeA6~8Lfj&{`BFq2xTGx${=s%M zoXzvzX_K7M493W_Qg}u^lOkXqT#6}p>Kl+R8;p@>Wsu*TBF2slo&cMM`+@s}`-%I7 z`x)S$go-jFs8AjrZ;K12;%x7T}FV_qs^EH3p4+63gr`^%c2fccsBBZ z4s66(oohFg9S*Yg>Icf9XJNgULZyd!ejkNZt^sZtfw%Y)dxLMs$StR1s4VlW3}g+| zAC&d%by@GH=&cx)BQb0Fn!9!U}w8*SQl%Go^Qeb__^H@SA{zI@z_1|;lDt*^_5r|CQ$*q9S=Hw0iWf~;cy8kY#{mcchu+hxl> zyUJx~!ZznZ^l=v|L#LkytF31ruWNE<`(#hdgXii%t){vaE{)IN>$IWcpG7Nmq~8na zc~7vxd0I(lX6rotSB9l7x=rU>3eOBE6$wTkbb4TKq?~W?X?*wB8Fa{$bvK}`T_5~H zm)W(+A@1C!g>8cNt>8?pxGe~H?u;&kJ=L%7e%gk5o(|qwC+Wy~BBX1qX%AwwR|oH| z#rw70kh?obOxhciw9c(XBi7EBbgZ>Ken#BU0;MR_5nN?kewG;D9?WQ;Rfl(H8C{!g z_n&ESybJl`(1zf%wtLP7f@;6?xwSBw($*!8+)bMymILdR46xSfj$NRA$FIE)G*6Ts zu*+vxM>D!4+u&$x6fyP-!&Utw_A#yxgId_x5I3V!x#zgV`QGu-`)#iVhqJ$lkpZe} zj>%<vfwfQp^xlbW28r-5oDVvu+?BHLuX9|WM?t25oi0v zaD*1n5u4HPi(%c!C2G=SV7YD{ATJ8MVf)8PIxtyhFwkHtP|1-q8LrGOXo;2$YT0a< zb(m`5WyT?io=j^OFIxbD)26hBa%d<%lrL+w?YBSk^hv$4C2GjB+SPL+MFK9#HvZ z0n)Du%*|D`i;mF&c~?MB`#;o9kJ$$8&*-yD9L9~vs^CkC0*bD!dO+rssh}8IH znt&24vOGLwu*R3ylmTM&JgL&ZE7%>w=Wf?+ZRo5du+z5hIGhuW*7|nwqjUJ$zhYeC zqie+E6Bqw&bFbUm>*EpcCegaR@$G;c5k=Rbq0Fi#0E|da!@U& zf?W%ZYFjOEYOn!WWfF9Ps?6HZE+I}3mRSr5Cm_f|!a0d|>gOPHGzDj8R;o_j!~`iO z+smrGQ!$OO$jwAmD99BO5jFBot+OX$$!=uL1R?U9p466jiHR42Tq%kq_f?>Ah>WYR z5w}*1Ebfri$^$g0f|~rww&=trg`Wx(q1kpK-pf&~M`M|=YnT_D zF=1}5zq%(V^@n0|UfN==0;Cb~7*{?hO$40p0cj;pB7TM|;-!g!b{8)#-zB+08WI15 z!_t&~$)L1@oTRmVP}-D1X)^!%7|BbkIIyDZVfTDyrg{;V5 zh^WA#r6pcEu*540?D3L;@4YBcvXlsX&no^)AErc5sU$2dwS-~ZM_&jMW3L8Zi;2x* z(1sV&3(XRczMHE;p9B}0DL)a<jH?%18EI5R>7#4o#8m?hqgEEO0!>Jt{f;X2)qIx_yN z&m$wKEIX_zEjVd{-o21ksjN5r$%YtJl(_y|K-6{ z4x}jm_n=F-PDWb1$Dr$2dOk*!(viyXci8Tzz7+f_W=5Ig$Rf!}R3-|S7k?4H%78*Ow1l}IBRC(xp(ND@)ia)}CfgGH2xBN@&sF``Hu zL1uaFl^6*Wne)3C$x|e?-^Hks?;>L7xfoS+5z0`t=VDPfyWu1VQ!>M@pQ+q{z z%8K%3?V>InqpZ|3(pE_u-9FTU3dAqZ)DB?}*D3bsS(By9d&srOp+{RB>QT;*o%oe(uz z%Pl;o&FO@MGozigX*g>|n@_=9MBzU~NswC@7Hu2KpvY6vtuu_)(ou8Gg$O;DPW&@H z60B7^(Z=Okf3(aQq#j7m<0Y@;Mh!|noXRkhrcHI(O$r9iAQ(9J_ip5St{&C!al?Mx z=Pth2(>U^G6!|7fLHJ`7S`g`pPB2@cA9rxbyb{_rk9z{fYg>v0+I&vhwG;h)_M>%y z*>Bj!gyjV*Tw<_HvaUjSQsA>oaVMVRiGIS8i3p^CnHNdn@QIY%EbbuU3;T&%#jTfu z$c*LgeC#0ZUCDKv=nUGxClL>5}r`aF;O6wF^B5`&vMJ7gUC%C#Pi!UuCrp0 zs!u=0Rjm)U5=qo*8{`Wi2_b5QD6{Q+KTXL|IY)C+wQi-DI)jQa8-mfAHa_51#jC>NwY zH7K={mpYFhw-sq*R@GW!$UFo}tc1Sc(R?6n0Ez}E%hCb!&oN1DZ7ieK0ap#oSGxxx z-!vqB1=bDM=a>3dNV@X3NLmXtbna)-7Km?y>-xOQ>&`Tz)+q31(m75n%aLB^hgdlTJa`$j)44FUqwaKo6pk@r?dr&?3u{Kx8gL^bT1vw$KQj}MZh84=dtUZ zVu*c$>n$C|=k6KI-4AjDAXfu?|BP!t^qH9gz4$4ma;iW(6Dj=M84sv)iCcO_d*g#B zA6bZ`=$LZ}I`F*$eYBGa*=i$L|517|_0IKKI9K63G4j zTJ|qve`wTz+$TUT9{)9i^0D-trZ3H6IGdAhNhemNj+pan*Q0b|ZORHfj$Whp=pLgi zSY|fQI|P(DkC8k@&QspLriYSmUh9RHt_M6jdm$I$8ok$W_~Nx}$lvu#zN&A4-}iiO z$2BG7J_}suJ+7z=ppMyG;^}KLpl!UN{aANjgEqej*IRJC1J`{pZ=Zzwn!VZGxE~bs zBM0H0q!YtaR#+jV6V{XkINgJLv0|XjdwHq9!MzxyyvS2-zovzfzxt(>V}I$z@A>?i zYZ}O}{w4nv7!lk%AD=tsngVi10awH0vcX=I+|d4yZ%1ecwDrdJFNF42bU$Qza&M+N zo%pCvJ@`x=`SHm8|6WP#=u=42<0|9??_48Uc`T^#s$Cnj&w2Gts8}3^^DHlGRSxfj9AMU2`~v%vAZm$>O;XxkUip4Z?)HHcxY-tH;WdPocS z6Ik7>)#8~)4#WaL!(J;I%OsbM_c$_v&k*+JS>RdVR$3duKS5e7j!@=C@a<`IL)w;# zSUsb`#{qMKmlZr^fv2KQ&$L<%RJMJ=fCTVRt1YX&8rDcJ80eJXGOZp=H2~nE0 zELhYIZCL=`9Sw_mNX1~xKq>63c|pU1MMojF0Q@`Li?nuk18e%jB8DimZ*Pb$BJAfH zSo8KpM+w6ILc_U5n!&V;PvaaXiF009B)9KqU@hks%@oP)UpMSnq=)nl@Eh6L;N8dj zhL}k34dK8W=>P}o`uwY|Kkqdo#`1HmktO3y@?Wmp-O5VqC)NW7&*kaaZZ7d_u0L^4 zI$qnKcs|W*ibrY6%FGh$-JPBv>X;GW5#ZK&zN?eogngt=dA_ZaLw`=Y^^2VdD2=Nu za~98p*xbev&-uFZ&TOW{z1#D(E8D)u{hj9=+`o5!YTfO_UM_oBpLOx#c@SIDSnTP6 zyb`z1TD*83_`;Mlo&+Bo@Ro7MEuEe$@b&6)Z?~NC90QM))9%oqZ$j7^soSth;i15r zgtbbM(_^3&cDp-nCCmoG-q7Nyw70k^@G+s>hh0+CwMy?95AD`_nr^}EKUnvX%kTck zbsUd4n&r;+OaN~bIPHM&LszJ-%N+t=wsz1QT>1mo2SE7%D60o4e{{X?)O+$!$ZCMG z-eQ^He%IBG^iOVfY_}XkryA!jc-WG+alD-24}d*L?huc7yif;4L#?+JjWPH=B=&0RFNVXr0N%EBI3cAa|;gmYl*Fp}Wq z;mHC_yWIVWZT;zl9>#wLhxZP5B=M7K{53Pmg?q=fO)k&iE~W0{y3mcgl!u|rTCgCk z*Pev%c=}1#Vhi%i%~@8==d0ur%PN-|)|!}-PJEGU{w4qK!1-^1keG%jE~8o%&>kFY~(u9(5AE* zmBNhhrD$_*YZ1g+Qc`nX>rD`QBBeB&TJs^cB4tJ9Rtw7Q#PznPt%$JX@$oK*Tac-f zFroP7G-0tKH8OXi_|s`z^4>I;$m_Sj!2%!+Pl9tv*1Ttt6Dgo=xUI)itaYffhn9QB z)MBqG+)4w?kb(B%xiZ0hcQoV}1?On^T!ddcz?mGHjquz@rmh`m3KAiXQpWl7y3`dF zs;@_A*9&5NhKH&M#sR~F?P&!fnS4n926$nAtU};{{r#|CS3bnCKOJ`s%9aw07%s%X zRYNd&Gk^v@Li8}WpF>fEfKC&PdJY1=NQ5rHdM2+5_Qvo`!E0!|e!*)A{5&(kfAC94 zv6cy*g(lpa{=}SA)Fs`V?f=T9->lm_bn}qSIh(bc)tiTHmTeYqmT#79Huz6Xv%I;p2x~84%Cn;~&8ZK6rZ-65#_bqu25Z*44#ardedl zZ%QX*$?n<@oauxr`N0i4+BvX~$2;2o#Ch&r*A5h(oleyBBlB+1mR=5ySR(I6hXHpK z>5dv-vA|BNKXHMdd(WoNH|e?*e(MUQf5D0jzuzW_=;5@z3%o(4aF*?d_Z0BH#)?{h zv{=mji89z1Zw9V^<1zxqSGv$P7b?KgGWxf|jFk5)I!VjOmtao!w(lmeC`9>_i!e;&4x~e z&MkJ7?#ccn`vCO`b)c}LsI$1M1kS&YU;97PpX~iV(}(xnNG}NtZ~}jjUS&WE?;G^~ zjDXJn4v+NBTx~4^?8b0&Zdfs0KZWQ|$T*Qj-HBWMUJ8fzrqu9m7{8Yyti$}%r&)cd zq%vH0!+2j`ZS^Og=6$7 ztIq)AOok@`f<>uGF1%i%`1KNDmG~#{X%ty|PTSO5MHiw|zdMKGKc_;(+r*!U9Yj5$ z+_vYAF$jA*DWAd41kBIB<7rxfnBBV(`V8U`xL_Ka{stGe6?ksrHREhZ?}aN1)~G|^ zdKls>;jV=X@8yp{T6+kg9ue39puMd?XcXN28ic06{XwuFv*GR`ad;Zg&Kdnp~mhRpTK$KfQ0SSU-+N$ zJE45n4du7bcq6ubdU?~-az*3;2&IwNnySl1krJ<}ZHZUWw#Qo;D{q>~=T7Hy?R>5V zax)+|Ki2k3?O8X}&Vu|*$j^b=1H7m4xzqUCQnbXYM0>oV*sAF>gAX(<50-mhgYW_G zZg1a3%bs~U-J_^zSa{@1q$Qo0+_!?)ZG0}d{^Rv8(LFXY;(>C9dx{9QESVLiO70F5C6nMRKDSfs z*9P#L@Y5HNMHYYuVEj;TZb0ilb^%UVk+^ds13ptsPf+Hc2=Yjnb05XzU;%pI?S-sF z8hU9*E8#_=`yVZ5K?PL-^cHkc%vm4*1rj*Ay7yUvt6SIh4<7 zz98uuX!Vj_b6}|dkqa^?RoyGMehGV|>vLrc%on^SaKas*@f+Zd&%tT9KMHp(+(+Lv zaHh5#<{AO#4O|{V*XJCbuXr6XFb>b9{yh#)!!!5g*dFjM%Z?qfz7RBY&C_R&L+#jK zW3~nB!TCOMOzhIHZ^Jrv+B#i5On1T;B&uEgILUMH-tVtXnL%o6P#g z(~CCPPd9XJVlAf@Wf2;il+V#ON_m?}@;1~vm9U7M3XdOFRJ7|VV20O0uR?#Z-NW{d zHLL1mME#;{@Zk`L36m1M^JXp5*?-mGo%*XqtYs$BfM(BGv|e=e#2na(&4r!VoJH+; z@6&Jz^Mmydww<`;u-^ttuHUf1u3ydf9o9|W?#jCC4Ly>PCtBe>L64}ScK8PRPGl~V zpwFq1h7AD;@i}3g!z|GE1kXxjC&&>+(+O`;QzhdJ665A+=LJi^`~2XqcLL|M*$U|3 z{hDrr*>zMR{aoiGMy?O)Si+pWVWT~JwRfM+hl&zmtxxat*+eJ%O+%ehFJX4teu!y( zLxDz~%yOno|AJHwpUQOhnJz&}!>1I^UeiTLsrZz{dCl|{q?C~QYnXO^XF3UELNK30 zfARZVY_GBIU^|a(Jht!Hwqv`FpD7BLvJMr>B07(vmSA-7W?94U+_K%?sTz+2Xd2k< z>G*x0-uXnu%q%w1fJ)9H{ z(Dm{vbPW6yc0sDacsf{xjzVfHx0`ywScTeEIQ1M?EI$XSV?msHhBFWUZm`^XPGy$D zTRy#_QmJ4-gX|5%2TH-a75NLp2kJ;hV;}U(Q0E-fe-Qk35$yVt-AY*b=OLZznD*}k z0zb<}uEAIc@(GCF#RZ`S?W*y1OyLr@1HW^SJHUN9wBa(mbH+JSxrX65hB;JoFAT=9 z%<)_yNW}Cp;G3V~I6~chn}tRPL5tZ@YFKG;i9+r{%T7M6;nODWHp_y+d;;>dkZ&E# z$7wZqSOetX#|G~|t$Jp>i-xhL+EGELjXtR!b1B%2yk)(SaR|N=i9eYntYWmy{)l}P zocW?Sbq&6TidUp>cB1&OJ{*$0@IBJCVyCDT=ii?!aZ#Pfe;^2+7Df3H{YVqSe(ojU zn^g?D!zC7SCd=!5?2|NMrMvVt0^Z`%VLC8RLVZq@5)sx)`ERqR%~U{d$2HzgWA6?N zU*~)pa~j3RCv)r|r$2(1Y(PSO&RX#MVDJjE7=Tw}?kwBf>SM%%R*hM2KNU-JaJ~!Y zz4)v*&NVyP=d>=+cSOFq)Zvsmk?bxfdb);uAKMU$r!feqb1{_yDzez68*L9Cr(_## z^N&;VjkcQOlwzZ;@HnO1Xv;XxS!86^dpJ%W&&raKzYXJD-EkC^$qzz|IQ|J0($B1J z;o}?mxSfx?_&6?299Qu1gTNiilYDtTzLAgH`M8UZ;}$@9KK|EZ2ccC^gWzlM@r``k z&c|JR9Jd^5@bQDt7buVT@_c+FAIE(pj=T7HwH`kHbIhz(JG@i57}1TNr12z)=Q3Ek zj}^c7%k=T^+dY{ zzIzzF({LXjZr7mbdfES5<9F)V|Bm1S7{hsLwS$26!H)QZ)8?JJz%h?+@4%>vU{q02 zGCUN<6zl&sv%34Jh&H15Zt&owBH$bsACgk<+h#Tyv1N9_tj~b66N7k*!(DS3{E6;# z%y3L`eCenmqumbVb1amP%{;6^mgc#KhjkI_@n`)k|L>e;_{pwinTQs5$< zz>Nqvz_YbrmV+!ZgsCDF`7lZp6^1KNa|J3ion0)U!zxQLL&FIKJ*JqTPE??~>ez}Q zOuCRd^9r$0ejrFhISa~PNFEcpYuqGG+q%n2}mO z!k)K^;XEM*+gfVV|FsF`l!1A#jB6SS-t9Sq8nCC^!|{27bET zOes3R{5JQM>KuC`kEvw<)6tCt_4zKq5m|l{BLJhh(Ao=BDbI(q%z|}V2>f1PQISCK zEp)tlhT~3NN21+!a-Mt&YT2tYb~?&352;YuonfvF^u*MILbMk2WR;@}Ys#%F$wyJ2 zYN0$Uv%_HxbH%Rkc?6i4F3`>6jrLcyON>(;gnyRf5oSD6mDHYm+!;Wh%zoa1--JFH zl~#6vrUV=VT)2V(K0WZnLE+ZuOb0vx?d=Z2)DxTLnC%#b$ijU13I;{~2EM@HJ5xA4 zG8=S*k#nFMRd#CczqJFryG!PQK6GJyCGc@s7VH>Y4uf)w z!{r!3k5y{v21g~bC>J`A(r%w&ueaZBXLWjImi9S*hvpJLzWY|&Z z;`h(&B<8{Q$6cU{U04^Pt+&Utpl64B>m2sHK&^B1PIOR z^J4^j-D4;=pMewG&g0Csk((GjvZA|kcUEWH=knSFKJj>lR?a0fp9i3=$Wk-NFPrCc z3uxqo81d}77#@?cSktVPP@;z#ki%I@V+`mQ*0W^yRL5uVwd(;D+dY-6B^mh|$32c( z)GW`>yb8Yft&To~GLNcWcfisr@??}4v6LC1Z?oMQM&9mi<3eU*c-7|La5 zOr~iL*06@DbC}R&rY3iLH3?p>bBV$e#2Anrc_~U*B>9`2dS;#!yie^$=8u?TxGDC# z7*~2b@N)t`jeY%fe&$-odV>%65x}oDcU86A9>BPqSO(*Pdpbvg!s}z2XsrVk&W>=U z%1945Jfg^^7;6eq6hD$&{yN}Z5blw3W$`f9kspFjfL)y)<_fi8upRV6HmluGjLv=( zH6l~N=ge-spTYi>R(qX8gpTWdj;h#0#$@=ioh$qj?eX?7%KS-Na6~Qghe24JEWa_-ABSeE$D#qC~S|di$MxTW+?C<0{(Az zM!3R@P!4=COW{bb zylT*+JKu~%<9Z|GbD)AhUVPYiG<+3seIII= zVx3^IP(hEh1ZFV9&%Bo}!rZsO+|S>25i}g=ug6gFPvLC9F9nod@ZW|x_&8jB)uas_ zR5`(FBhwSb8K<@uD^Ic}*tOfAEta2o&a_$|VQTSOBq9ZmWU8)1+ZTIod>ivGcxFKT zW^Xs0J35Twze{ejWa*zPmYg{jlopnsmBP$(!>l$(JBwv!DP%^5%1*|W+gUBL8uVuv zrCn4=oW)OAE6Q*xnBPidVO2pXLzjwR{@q28C!V(`m@IvOfH@arc-yYF!~0wdG9_Y| zGkBvz``0+6#s&u$%Y)zEIGlth>F3CN#FoeZ7Kby**ocaO-{p80=k?$94)tA(7O&4} ziX;j6LxX?bZX23GPD4}3`vLQVs^wtsj;gp~6<7xioUiNvE%EN_hPUvrQwgKuBzze+ zCHJN3e}Q)$D*Gw&J-(M;ihLV`@7Q4syxn!cZwgrh>$7~GUl!(9Is~4;nehD*Xm~N~ z+sch$RF)IoXuBy)nurNnhNuE8%YTFvW4i`l9rZ@|^5EeL+{20}VI{_O+NFr7_zonY zvRL?Qn71)#)t8aYHqlwqJUdqkTzXwK2iVwFko}4+3bJ3Z$$pVd-_ZVweW>gUX!mE4)wb9#?Y;uo#k*C- zRi`qL$gV^bdQ~zuqP}Sedf%bGwM+r ziKy@wUxZVa!%WdprAF|F{%rP-^>pP$Jym|~BxR*1?vldS7^qAq)9D!zoV0#=*AL)} z>$mkr;``t@sQBkdZ%l+P$1L#0Z@jxj;t1cKi;8XG&)^$rs(_5@5ixPX@ma>9-V$3f zLY0=C;w*Az2sy-FOb@ZEN{61h38^PfmQ5nwgzts*NImwRnj!8x+|RmCxYeVAP)B7U zZkbHr(p zaBF?@03&BVwtk(Hd10g_?*c~& z*=kx{o#dnBc*1uZQZZ^;IfVALJ|D%!SFV;Eapx311Fu`vRhyW1Hyvn#SV}3fI5Fwb zhFj~m@ps2^qQ*j2C=c0Kiq% zW{pf_*GN}0tg1${*Fq(s7JDeO@Qos$4>+zqnA13IioKfWHHR>*3*ko8&)v45`CJ}0s#c_*vm>7_}x4w2A%4V|F+Un{o=!t>Rua@VG z+E7%uOKQ?E>Q!sZ`AV5tMnZSl*7_QGDW*0PjLBrCX-QJ_;!9Uw#sjA*Dj*^8^B-9G z_TBj}tJT)M96d$u%b?XOq?!x$JI80#Xw>Bk>R-Q0L1#WRhMoawv~?=ZpaJe?wRxh9 zk&c>NpKVn*Zp6@l>hJHEs6V^#hP)(?j2`9H#*$ z?>=pV@G=Nwwflkh8f>3_t3jOy$UE^%J1NW81?l_2P@~vk-r7?J<*Kf{#bN|8B*mo%JVgnXzE+&x~eQ=gl)d zpEBl-*?<4TzTd$|hjU(7+%xvt$G_Y9#k28dcgGCV`W+`f8~4mYUHR?LU39*+?D>}# zm$$#TxcHBMdUeV7xqt0`wdd&{_T79YPyLslKHY?VUq3K+cflMUoVy|sB@$(UlP*F8 zLo^bPjHJ!gyBV3AbQh3QQ~9gy>3ka_S#jAW*>J3}I^><^EHk~EN0rEke)>L}ev+D5%tW5N_)t6NFZQnjg> z&u?W{Nzit=LLHU5NrpX=v)X3Sa3&TqZ#zd)U+1i=)P6EXMO-%OJ_vsjaR|0?8G60AvDq<{W0;(*vHhL6oj zu~Mr>18k&Hb-oY25LtDBNfYdTq{*!HeO+r_Pv)$aSIacMsZA#2LoEc`j1+D%w3=Mw zTSey`VSa@efa|M|GV$WKOcR>NP4{=tq*fK;vQbLh~M$DyuCMff@#Fv}x%5wGHap zRVEW;Ef+D(iUz7)Tw$!A-Bx7PILuO9aHzPjNLf?gv3k2lirWMH=b%=zG?#C|M{;*z z_BHQy$#YQK>&n~^ZX2JITvMYV83xja56B2cN`x{|BU!CtL7V3HOY3pYRjMLOx)LH^ zQ-wtqW(SEhZn|EbBbTe|Yb^O14ZYfzlfy6!pmjuAZK@$zHMvH*iZUlqq|~HVB|*#P-!m0-sD86Ezg~@#Glog3iVm1|?WmSXzndQ?HNR?;I6;x> zt3PX$>%IXH?jg?)+242n%y;toYGrqT_>RB68rM*O>}wLfBA z(M0*`S2Fh#4TSaq6V?39A#qnJ5J!;mEQ{@6zO9;QKnbtHN!>Ya({eQn{O;^nF6G(2 z#!LF{PVH-otP7#*Tz^<4auUB^;1)YcmD#6a3U5QSn<&V8$qSX1;}+KvUn_U4ZZ#=t z$*HrJ0Dh|8HQTM%Eu3RuJI{ul5H8OkKM^BBs z?YV-Zs~74n{vqf+^LF*AN53kRXZb8gzN`EF2y@yWg97 z(E7=hm5G|qe|LZLJw1tSs`dXE_rb z?NA6jXK(pZ8j_4`T&B%zrM7F`OIx)In>o93Di?2H4@(mXxh)7XCFb6P!sxrSX(JsMx7@Pt~z%x&NZ#9AV)SV6Tf$wSld$Y z)PaiUOrcOn{LX2uwk7|5rM5}?u(pAfR?pntFqUgMSkbC%F#MpkazAJhIqKZ`C%20= z#nw2PMVyzk5>eyY%(l&qv*9GEjcSQcKDbV6@Me0Ip~IPZ(I=3k9eUi<*R!o0!#TK}^C;&SLL`dkQK7gJO@x0dQ5><#>XP%^ zH^|C`ARjiARFn$AKNO#+V&gQzqIvA9hO=%8RZ%Sb*Va}r*j;bfyI(SSA=I2C;u9%0 zQ-UO7Ri$$B8=Jg8ZHhK@gc^2MC@U+J3o5h=Dyq(Rtl0lNx9afI+9;~Xc)<~a8gy9})eWw6V*82mb3 z8_hmJaQmZ6L)uVg6n%;)q+^Xy<3yt>1!JUYr=L&erL__*)j@O+SC9csfX_6Sq4V59 z4gu>0Tq;CPPJar0k1N}$^V}7Py$x?&fpduG9LJp98(^Y!@{qfo=tT~w3%9?wo2>OMs*=WG%uR#HCAbj zR^W9WT2iHGr`|>npiM+xO4Ba73pK?hpM@S+CSJB_!IrVcXfyT0I`>dGe)Fq6?ahVSQO2joxvWIco%9%wuqGtN45Jm)!ru# zh#D?yr8dImZd@>W%emBe8*ffa{XBT})H8%`0U{65!=Iic|COCsqsqF+r3{5s!+LgdNm}=)v4K@Cf?3miSW=-y zp-Fi^{nVixn44}G@js!;gHKFc)^a!Hz4z${4>c(kQTBNA)5AmGqY6XImWs3_q-djF zA=Y*DZ&}guB~`KPnY_JMc#hbH>DZ+(5i+T&3XY0Hs}3H%@KN*e9Jivar{&WpKAX7z zpG3#F!_S;t!5XM{mU5~P{3Oqx(7jJxJO9qDq4N~z>Q4X4km$ox+aJoveOlZXf+jtP zDwbuAJXm!L6`f2~jXbEVSRkpW8c^%3#iGu0=buP7C4bCRc`K^GAj=n1o#&ru`cdVD z)b)l{<;KAP@upSL-qU&R!`yNE|3th~dH9y|6YoZYt-E!wb;%VcDe+>`@Zr*TW*`7y zYLwdolNY5VNmXb#d&bDML?u4iH_$V+d*wtB_%^jEqvf3|S0{!P9`Zc#iMT~)ZKPN= z%J$GFr5US2pBi(u_f;G^q&(!l?*Z|lkf)UKdMOG)@iWT(Ypa$~jdu3F%;+I)WeW?< zfk`N?I5M)O!l0f=9IzvIE)jyll$m2I#3*E>STAhMv~+V^`tE6Tu3xL2iVix!FjkT8 zoqGGLrjYc*(?(T>R?JjYIw+L{Wtb-%W}BaSCJt}Wky^A0&Cnd|=*-@+_ip9V9b*nf zqr-Pe*JTBto8!6`7;`xPa_$=!SJ!tH)$T5v`AWe@A?;(vdoPW7`7Md^!fz%VSgHC_ zdGMWshMoWF>d4;RGIPU%+jieNYtNV`-k<&FTkm_|)?@n~i6Qs<&JC~sSog`h2dlsN z>(o8nUw(Xc9=GxGXDh?9mklcijdw~F#5J-RkAs_?{ zA%Oq^8Nw)z3<828AcRSQ0HPvJM4=9i78NZ;>r`uRjbyy7JZ#-6|Jwemdf}0 zJ$s*s#x)7tT4)y!U?gaQ3s$*(VR3WbXfX58A{bj$=DcL{=7(0aZ}v z&fD`sL=9^H&9pCSA|-b{y|=Obw5{#bl#BAtt0~xAe@RSLK2<-rZqa3%?0Gx)XN^t$ z2rC9-iwg2;+%4UPmWFrVllx7|URJo@?bdyhUD^@-r{feAQ3GDbry*7OwXXwwYX8Xi zh5HF?85C@{DWb|pjl5!`1HyZ$uY@q*soh^aelVg29x5%~4f^lf-BO}(eW~3ebqDSJ zo$3NvoyH-Cy|W~>JQbch@L+X#_uX0c3d%gSB|mPd_G4$QFR%MU&nNP3xpJ=6b$^bk zsoPmpy)6|}$9{DF;YYtgLEb&a%EfK<*vDstOEw{~FS0(!(bs(n^6%t@?O~WQ##Gg# z-`xP`yx^(6myFvKQ^WGd6%5+81G0l3LFJB&o_6hB#UK|9m@xj*5LMeF41&d%61Rw@ z{6{7hb(NIAL_{1@L*FZny7tyX5c#$yrm7#s$JFX-w>C_5R3bSwe&Z!QN~bi`Dws@; zk8a(uiD?w&-vGkULk-1PWeJY$^m;jbJHDX?;LCT0x0LSKQxh#2c*q%5lnU=3@YMC& zmm+_IY8TEcyN&qcxs^bjm*4GmEzyU!l&CC~y7G-k)_|WqK5bA!3!jk+sJ!{X*|{Be zd#Y^Y^aH&>D0m@z|H!{i92ed{@YOh!|A0Ens(AMC6HZKN?ZLLYzv!1Ww0m_P>?R9K z_RIDTD0@geW6X^{S`fG!*!7?P>WMA_)cwTJzCMz<3|R@7JQI3 zxoCXH`tZnsx1zO{7e<^%_O}d(jk?Pj(=KQ=9G@67VE5TwwiT6K*>ii*-rLKbx$*Fm z1Aq6|-G{26u8Yn*<@lTbxots*S9aaLwpHX_F!!~~N-w@?(YK?nc)!D`r(AQ(>o1g~U|@-a}0H z5v;St%sN|L7S`G3|9MbuO^!XXMAq3Nr+>EMuCZAKy_awL{vuoX&dr-Q7jGX^xZj@t zetFhU_sSaEO?!WEjm=FhI%pTSuCdi*%Nko2__6ukas~x!(P}tpa zL&>2yppEgGzemxkgss=tYO=qxH>WP5vR+@~Ro2(+_d>4+N}hV7b$u;+)AA##>;Cit zTcj?#u`a%KtE%a6(*rr1x5Pu&_3F?te(Ut&n~Fb+J2j7d^Mk8vShlLHJFg**B`bj6 zoWG;tCj|838W!!oo3mj#m))=gH_z%CFYb2mKdh~tC#zyuO}euVi+Mk|wkD?Ld!e;R zM3&Za$9`4S?d0&Ft;02?xhO9LNY>Rhab2w@`+u{p2C?%(=cj7+6xBleywL8O5gcZ3 z3|gr=tcLvHlG=7GsbzP+{X1uLXj}Nb>=mi&w=dijsmm!p;o6J$lQ7Vk1hm^RLqP}L zIQpyHO0UMP96L`%#@>F$%KYDP_@ly)w_!Q$u{l^yDgh)*tiUEBM90 zA-OQ{iy?8GS7E3ed;2d27R-SPp{j(_ncunZ`n8O?z?Wk zEmH98FZ(`o*`FV}^Cq$8R{ku<+ETQwvqH zDyfcq_!uIAWHF&PKRi-iKg`YU*=t>|o;6LuU=~h2Mx0pnVbzIE)rEzjP+?(pQ+`oX zQU2`NYW8f`YqFZu!i#pDF^9jMHy*ihXUN&e#jlO2cqr7H8ofiIE^+*#UGT5GvbwU| z&92UNC4WlI#x)E7@|*ClxOY?UyzcEn^XCm7H#3DLz^s5$g+;YW;pU)v7dFvYbtt4Z z;j=*@{*;CJs#I=QYJkMvopnv}*jgaRa#a zoHZES!DGga>(xc!rBo~|48kddRf&B5kWhZewodTe>e^FIn6y4GH*b9tHL7cCYm1t2 zswP_7tW|XzYLLI0;i@TK zimhA7p<0hL)~+X)x|N5M#l=Y;he-?7!%DH^jHoNFs;Nn>FGT(dt7^(?s_IH%VZx3b zJJ#3DpFW{Zg$AQ~)EXSMgF}khv#WY`?^)I5h8yPQ4TJ7E$k2=vy3LreuC^PpTib00 z@|>DJV_i+O%hVNlLubsGal%lfcEZpZ)2GkEHj?$V${xL8q_Re@uQ}AKxYwaWr9Day zt)D()G|Rhw`uecfG_HdFtEjK9uc#PbUtd0~wzk_j!$#Jm)~f4v@7^#JB^o*$UK(Ci ze5AOze&e`N3;Xmx+`rEeuh-Y9{o6Kr0hn5coY!rrEw8U1Ur||8Q*@3xCmdd}A=Y8Q zhMv88^)JP#SI_eLi8ZN8X>2%E_K!bx+XMaMrGvgz>RdLQ-uXpEIED798EW6Y8TbcR zAheFhk0>-KLio0NJboyC2_wHStztOf`*WQSKr_C5wdm0#3PR+(tmlTQi zH8+2F^EHLNu?#<9g|%Wr`S^(w%ggK6)|Wpt@5C{~t5Jh$Bc3mB?9E?Y-R!!$nknP! zYHI4nPpLs-R^Z?!q#FvId1h#E-r(ZFZjP6OaU+>TR^oA0UUS5eoV18=MiUnt{TCnuA zb*ZTf7A{x;XhCY;x>Wthp`&Mx!;2NFUrJ4z+qiOAN=;vO`sqs+q$W@5zii>c6n|>k zg2vRe#s$k$$1k4WxF}7UysB~eszwnJsm5h17Ni>Hu9$n)g2n|aRzlI|wO&>2l13yl zF{~QuCN}`8*O!_4(od!8&ruWRQf9)k)8xDq=MubVR-}fh)Qst))U;Jg=g(cICN7i9 z^i>O15d*r)d~XR=Pq3}cf~q2X2HA_0!*B{;(oSL)@`96~+7nBHKyzzw^Y2^v3c~Y0S2Phi{o;}NtIAIG1R@W47CFB$CSgk@c zhpW&zIFjc2bsL;K9;A^!0rLJ~8(s3LUtq43^>OlekXC@h*X0$fv7!4$sL(uf?5I(p zQvvh10I-h}CXM*cHb)C!6e07=cp&3}j0Z9v$ao;*fs6+-9>{ng{ng{ng{ng{ng{ng{ng{ng{ng;~gBI;P?W^*ioZ~rAh}JGi*rTit+)Keb27wJGfVBNWX#o2Bb(RA6!w9DqXQ) z$%45n7xYSmNiq zal`-DE6K$o-z(wEAA&sd^NqPuhQC4_whAYGIUpg@{NDrsw)$xYpT8dZEWsvRS?(>k zLRnpF@D_8u-duN^D@5d{^YxSNzP&=E_YFAt0To(qWO&i}YC%OXHKlI*K|AwGeEwGG zFM-@4T=$5EJ`KXfR%i9`<#swMR0rB?xYBPQ;hK-D6V(0zC_mC{^+JDN&yba-Pa5*C zbf#^q8!LT!6!sd864ToRJc{cjxDw}&>AwJ+{q!wdOG(5pTVI6lxGGd*aO(TNGIV`g zeLLJwk942UYaR4LkeQIB>vIvVY=e7n_3i6+tH%lIvuyW(Uykd0=1O`QPxy7w7u6Bh z{1CxaKX^R|IhH>f z)9oZ>u7k|A9@i=d_H$L}BgieuQ=uKe4;QG=oxpEPwAL$=$w%I7HS|J1A1{N?^uNKC z=@ch*I+f-+0auRn8*%mXNx$+}pfBnAq5dAoy?`_tJHp?%KHf=%-U5Ahp$aX+HPl&! z)&|fXQ@Xz$!j=C2rke_(Z>z@cDzpi5U*Y-`t`8Nf&_lSc?V&<*aOIEbzXtqjT$lGm zzM}HqHllaFco_Fd;9@u{-P>9ULLJ~e44)me7{~PqwPCy`Sx4DFZMfZ zn&0tHK7W5T{PaEk74Q1|;#w8jhI;pZ+Wu|t`~2JLTE`j6X#V;Seg3E5Z}OGX{JkIh z{3WARXvO#V&!zbX!LRxr|En~=aEuB~`X0Z>r)m4(w|tL(>SsPbG**SK{~rI!Lq2~m z_-sG^PnYkv-}(IVdKJ3XXW}{~eW!M;_3&GCKv1dk+Blf9wv#mqmw*#oytGl-q2LY@ zLk@1X%C_8z5Vx(+alF{Ud2-1*k31*1ORHClLe@}RoS_tmmJuuk7$`f1;F(A~u!3Ol zIjA}dtR8?}CveNdxMuAKEwJ}Wf~OPw8L7IfJqN&}a6pAaftxrljLe|5o0*1+oI-ft zPXIc~`2$nDl`2jJ?cBl2j5;wV1`K7H4t_RaXT5{06tGX`91A=d?7s$=$kz}E4j`!F zv(Hq)3MoirFcQ&lDDn>Oni`Hq?xGcuiN|NJRl$K9pqZ~?PBE^b4me$kL$Z&A<^e7a z4snr2WHV9-4%J0iN$bOOO8ZDZmT)LC36&MBA{>o`nX%!74bC1eH1k73F^sC^tk6&aNUcmm-~d8bih67#IAyti=WRRo6$t`Wc&|vt zXRlDfUx{FR_8Jwuk6QX7ivbr$7O=EW-vPKZ5@B6E^IM$D;7&IqwZ7UK=oC77pi6%VyWU=VP6WK5yJi|_g z&{7kf$vI0n<%!b=16gYK1!qvAGxNP%IF*TZ6kB0egHx5bkEK{;vp?1(W)WE}Vs(i! zWH7i!IQ5DCG_cmLgU*D+Qi`1`VhxF}nS=EcbQ;7Q^^pAB$C0lOfCsx; zZ=o0+_9J7_V0Wt=HJ13A9_k^mN^pi0>}fF>C$WK?5{va3LNY96%%RN=ps4KN2vOKX8q~OJZtW7*m)0fy+AUB&5KcVSM?Hhq?OKc_QGD&B5B0U;u-F^7~c?0M4iKo|%(=CJ#9VQ27L=}AH!k8_AE12lbs@>1iD)d)&K}?2cDJZuV+{-{lP0PK;>C-lcji%w{eRb z2fFIH1SUhxv>qU#WF;_mWK~*+_Rj;0Do^6#s5mlhCRG#RUQVhuL6EP>NQCZbcvO_X|@@HXsPG)9dj2h?gA3@?QLPSLRzCwq4DqA(If9xbx$<|PsFeS>hjK_bfA{SvkBfKzt(zuR)wqhSk@)h2py?xt)@v=G17(Q$TnZlJ%6FXgveT zY{EI5G3G4PLRApL=qy2{HO=CbH+vC<&ZCeHHR4ah$`!!l9|5=yK<*&`djS+eJe zH{d)4rBm@d82be{?Ro-u7y#L;VbO6o7tQ}8op&I>%(XurZ0oo5Qvp`%o+hC3&!YG4 z3b347;1|BYJzC&CTDU5}xl@Ak5bG)dhf`0$g5}EkF=By?Grgr)xF24b;lFT@NT5CMDwuAHu zNF7;G)|5`Waf!gws*rBruMUURvK+#l7K1bx%ubB}W{VUniN9hTRtsw)ryitE({S2G ziO&B-sd!jhI?uv|hjo7Ejc^GM>(tKmxbUzRblwgH9@d%44YMb+s!dN0qOGzg-w8f{ zJptQ)qF$H5K!cFP&|m_kk!;vqC#C6*6V$ynsJnSkhfqNsLIriF59$FSXiMJ@>Tv;j z90G!R2yk@>#ROd)LTx5kj^qLrLe&g9stPZ` z>7O`co*Ph6L{nYBj_GKMhEkTL&0sa*{FsiV2q$AY zmLgmj)3Frcl*(f$!&qu1Q`WH*K^4=n6yZ(nbS%X@E34hxI0vT?K`a$!dtnokf^=1R zek}C}?TO1yC8%OLmSU<-Ovh5}bfFkC5S+(?Z-aAaD*P%=JdDk3hutwhz8Yu5QUTOy zY!9_o6I57z2fRis!vdQ{+{97?9o7|NDUr;TSV{zQC6*!>is@L2bE{}f$5Mo|b9F5B zHd2kp*dT)sQ9cco@TI3t$gq$@wk!5Fa=Ips+cOU(vnP_i>hi&%=B z%A|>V@=Y;QWUF8npldQ`lN}aRzqh((!^2}Ye;^LGh!*0c6!ppQk*f) z>R@6iw%dBEgNdcsGACFaOe}RF1mChdm{_VW%6HK2U}C8&!9y&S?XdZYgYSmR+BjHH zW&$#`NIr*zY-cCV?SBO-n@t;WlKlF3j51VZb83}=_J<(In8?N=JqJ&a*crO{IEL2` zfFqz{O?2Fk+%ce<2Yym|Y7c=`(gajY#z}5q4U||?pGby9&30(BBMu3uZlVDbP!U#1 z6HpOxlO~`#2aKo+^YRPOO%6LTpu*z~l{5hrJDN(GfQohFBuzj?sZi1cR2(~tlO~{I zM(dL%pt>ALL(&9POOev7udrlR!CWRKaQgt~2#B7I@uIzr&@<3PsINM=Q>&hPCx6(_6ydLK;TgpuU zBxzfvOhCmUCDn`*0;=P233D3wB;>lOoCk3!`UHAzJ}E_&$dN0J-mL(b_3&-TOi@pO zp=&o2d;+qeAJd;>^)@Ko-v{X3Nh$u~IINaa!6;t7c)qgcyo013 zhIaAF#is+M+@FBU=)JdyGPnoR^J&38ZPVOy8m;4Q8 ztf2(0hLZ0Dd6&qP(vM4Usrd{@FNre7FyAssOTo*upY41EQntflO3Pu+q^wHy{v&Mh zaC6ijA?v7n;8Qab+yQTK1bYDt{x~uE-^X-;jqNax8gwEQvAWK=oeA$SN0dc&Gf~`x zRP19XgCATD&?;I6(3R=y!f)UOxEM~q73Zw)fIbaCxiZlmicrO{NzM8i=pV=qod`ob z?3tm-xbU!NsB7Q=M^&J-rhwV7%>sTzCHw}XQT-nl&>1uzijHLe`$ct+Dr#0~;8N=d z#6xc&LxIb!*-SL_7?B+owVlvGBFz@~XKdxVxfU*~iiA00$_0 z0zt=JQK9UKQWx%ufy$mlFbV;XClijlOI9emfndJ7{4`}xA((WRuLOB2;X)NS83nOt zt_G4t2WN?c&8kL#agGyR1ZIG7POxksK?XNLq=-hq;Kp5GEd%U1!COWG4e!S(xR>{o zFoT=m&q!5~TAVnyj8Zs&P%3!SN}v+l1aD>khJ`0t{|~w^Aj*;3jy-*AU5e za-3#hW~n7kIO|EALh-#g=QtOWPyp4?VF9^b75XR5XK}sCfLyOKAlIuxN2H7lle_{p z#9RrJy#AwLNapk~e~|4wJkZ z!a7XyY6+*qByW5k5|S{DnT74d9#_S4wJmOT-woLk~fb9-v;N?iEQFVUqVN5p)qIdG`_2VUl-$8DJeIc@GfI zb{Qsl4{ksjI!y8&qPz~1yvJB@9VU5CaPFwXB=5lSfOVMUJ$)`<9VU6t>;hcoGEDNG zqs?-_$l3GEStVd(?FHJ`VUqXKk0GzaB=6;00grMSCV8(?SBFX783AjCY$Zngh}2Wy9k&Glf1olH`p^_lJ|4_09<0iB<~KpFL=0<?zEHvz(?*gczba0l47J#jT4kWU83Y+v*-oU>*cyM($I;9` zfTq{g;%calki72JVelnF@_GoYBP6e<#bk7Zwm%9U*yJMM_6V z-uX6%O&uY57f4m=2+6z9o(p{)A$i*{kMkoW?;@KGUq?vZc0qK6{F2& z9U*y_+Dn1x2+6xl($Nu;ce&{32+7+ah>noFW zF-dVq2aPjT!Lu~J(Z?AfdDqxC0+$HMYY|vSNZxh!-C(R$5e_E=#YSfpp;Ota4PJQ2 z+bEq*A|!8@%?gnS$-CZWS~}IQd<_#J)JHs*GQ`SU`-`#H56mwWBo?voYoZNij$~rKcmD?tu4@#M;R?Wsz{lzDQ&37 zk4YGg#R8cnS}p4D$d{vfz^Iw`-3;(N5F1c~{B1%}|I@rLa2T&6*!^ZgRBlkg34qMY zI)NQ|fCnrhMXxqXRALWmqBQI8=+NX}=IflUImc2glqC;$10PzC0P_|ik19NE^mK*W zbaCKudpI&1t>vWrN&6h|RBRbU0tW%jEx}YIYCk?yEn1tZDuM`88{}uS{9>20y-O^_7JEP#EFg?2SY;z z3B_8dI!usg>|!Fv3KEZ15~&g-KUPO%xFE^cP9oKU6vjS7RR%@~l8TOEscHl%jzuX} zD@bW<4v~?9l*J|x86`+L@>!t*b%G31+0T+SIxr5N%=t0OW1SZapcSR!Q-BOWxpH>` z$Wg&=Y%wI{O@)fJbuhqS0GUa(%O|1GvQ~hU|5rA(E*AZepCUuUsy!n^>m&a?Wvk_J zNEbAog{MBBu&!x8@d1?uT|ksUwMK6v+L%T^1FDh?Fs+~9NtnC=ZMAfm0P=}ID^VKj z(T==y;^1mGFYiQyc5@^2)T1~Yb!8Z5{calLcsBk;P~h(#82(R4{XV z3+BUU@HJ-tq6-1K&Luc!ZN@3&F+{lzN0>t8D(g~QBJWVPnPgd12t^BMCt%-}?$as@ zBaNf_;{7C3im4D`Db|`&MB&W;R0`9DS<%vkk1mzzvaA}15%bYq7LSkGtR}d+%Tg@s zw!p3S%K$>-*fxJ|p8;5Tn~=A_?SeSoLAWwlwjhpoImL4X33)q-#080Zc&}Ooas`QdPY}ry zBwy#Vogm53I1UZ@f)sk&Db`+)low(?3j`_l&L<}!NU4g>BbE#tLMFo;25&|tr2w9C zb^&%{&<*C1>{de7fFB4*1-D-sjJ*WV>PkQOui{%Rj9Idu69&OPMDfBbqo9U>izoEfuVOF&FqV!$>{YHB)O7Hb2dMJk~ z^j-td__f#sL9LbAeyjH|7m)&7auj2*ir)qX3vg>&hA9A?_X5}~z;DuQmG>@a|5AYV z_ao~(f*sqB!i7h$Q+wES%&H=XDrYWE!6l;5c74&@#Its@ty^W3{QYrA zJ`}@KzZId?$kEEsYdD`9`Wr+xhKg}+@?OLlODvGFy_*3CykR&y-U*Nlde7kOdSk%N z^6muP^8%oRy)!_GcuPQudffoWyn&!+drg4j-uZyrdB=mB@0|&_y*B}Hf%jva6W%tbXpk_y->tdCKM=sTd=jn?1k&nU+)te#n*I| z;hH_JLD?IuenbK)X9+IMM7#$8B+ty{%mqYgA$HMt7at#?m1sctcnOER@OY-O(K;Rm za!c{n+ruD6xk74RZk~%fbX1uA4?&!~nY9y?eOQoC^b3mpQ;LD-SUXtK@2o$;Qaj$L++$gaz;z%8 zJ%Y|4*lu?M%mpJO0OrdwY*sMvmZehdWimh5-``}loC}G9a8SRPqY?vR?Dx!?I?n|6to&tCv4qOR@mQIWwqp>Hy84BBZjzQ7_(xX zQ$V?j*QGB``#|4;db4u_oiPNf795?&;B*%b{JK5{i?$b#Vp1W+1PwuTyOsX9&kjr@ zhuswjdunQwhN-5CSfY=RP(Ba@4Clacjv9tVWi#721zX|6MZWp+l@^QlXf!&nPCEPwRmNxSU7X*GsxE4E8sw+Zs!R&onSiwucd6hfGL9Q1-y^~1p@AeZ|sDC zf1^NBz!{`=An37}e+CfdI_~ARa^Jw!yigPw3b{al>|mhm1WZ>cokYDyDZN^`jC~?e zBp0YBIT(28B#im_U>DY8kxex6A$2|=Js9{1TTrsckTA^BR^k(|$+kDG9A^as&w?*zUh~bI z3^RPSCHqBqIWX5EL%(U2{RUhWc+l8EkyXwywDSz?5EDBofKsL}VJ8Pjb`Dd2$08#b z*n`xwUn6C_t@CqL1M*WtJ15$~z&7y3&LZCq9u2#k&1LtXZ?H%xcGBrx4piK}MY&BB zyNkv@vq{(4%3(has6d-cJ^`j=G8I(rJ=Dr$(Fy`&Xu0frS^Vn)ZS2gXojcmviD9%5 zJK3&s57W+BO#O)f8OF|y%=Ubzjh(r)v)a*oDeMg2&M8^Stpk$%A+;`X$UqyL0;dI- z!wErcXZtKTZ3*q18bpHvU+i4x+j&2v+)HTZY}#oIlF=r;$AOB|E<^Dtb`y=C02_6*v&E31titiY(ibAlWxj>$z+)+Q`iWDw(`Rxnn4H0mY8wk*>vZZm045c5Rd{0aJ{> zP_109DQ7>+qV;Y^hL+2IjhHa*H4#?|dRZ6(s6a5ZNn8T!l{|_A|YB!eyC0DA@nJ zEF)4!FUv$`BSU<09Nh|_M1{?=%wK@XvdlqR{{PsrOxP^Tj78qExJr8~>K2()fg!SR zqdc=pdj?A3gv=@}k&tIrX^BKVvr0=O?wM6uBKe+Kr6rQ|%qlIBLeH$y5=n*3DlL&> z&#clCDfP@MEs-+MtkM!G*UMUUlF>mbY*uMMMNuLXz~`hz>H;fFzXEJlm`FA&OalJ! z3R71!3u_mw;1L#}mQvo#Wp!y6L90P8hwQ2)mrog3yD=_6SQq)9Q?Ob#rnN58T5(yC zx`JogJXxT+m<=fh9Z$7e!(42nG=CV*kdu31GcGyVNSnN2YP}}P zO%=WE)LY~0VMK)9pVE43sCPC6V_ZD3mipg?uv+-R5narsrkKZx1Wj2}@+E)Em_ID5 zK%L7l)?)wj5>^WrhP3)(Q{G>T1l6yQ1g~PwPNTjq&C0aKX<9?YxL#wO=zqh)YWY!G zK|qoW?T(?3tM)dA)x!uj{bpw(;hO86un^~a2fRNp(hDN7Tg05 zW6{chqHwne8N}0{%dT;nq%hl#Bpr9k~0R^Hvp(gJEIc2md?*Tb0 z2)cX^D7e7llaVaPx#e%ThW3Nz?0uFX-ve@fMym2yh%De?3I|jqpjl&Kkx{-|z>>t|T^+YS9ucZ2Up#RK5LDTCSI4cOK_|*B z4H^zbxurqF(I{5}G#t;yyE^W`8==W}b;jZ9RpWFw4#_GKng_Vp9ny!R%4XPghwAKd z{nH($Q`$%Rv4lfWZfS6<2uGvb(%=p!9FKkgJ8m`M{OG;R!3e_1=n~4*5H5^~ zkV5XNf8Y|`L#@>WWe8R78nFxuYy`1`U@UTf*$4T~#=AQ1y&{>7cXixfiC{L~)p745 z7>d41TlcfQN29Bmvj+%gXY*Yh_rX_SDjsd1%tMqbS2`w=Vh@%Dh4O2~looaNoQa=Z5I#m`u5EkAv3qD7Q4Y?+!!` zXGK4Pmir!i!^u%@X>i}C?tImb7mDZ0iG|9)0Qt=)9p1!a0o9%?vpw9MW0Ni0!`*qd zNXhna_jLO#dV9EghCLZi$n^Gb_blP)?cwfHdp+Rw0O*Y%D*&gohvCjo&wuifW?MqG1WA^N!0<$@ZQUn!E;u zmLuKB)_6}JM-%t}rrfR;-a$1R#@+7L>EO$TaZKC^>kZ>>Pm9Uu4dZT!#hT{ZJ1lpO zLz{ZTxI4ny3q&@IyEOvq4dZUDAbP{NJJRBkZ@Xc~Vh&!??Rur1XYy_k5cJsopT|ULcjLH;lU%+LuCKZy0yC*(;Hf-Z1W7WV0*i z4dd>1LG*@k_hLcxhH>{2`?tuA-Z1W7YQGLdZy0wklXUckarbi3(Hq9y9fIf$<8HGc zdc(MTg&=yvxO=4_dc(N8Q>;C!Jhl=hDGuqNai%JGmc~E!ac&rQud!ojZn9zAZ4p>+ z7$=uM#oLZ^9qj?*MTU2kG%oY$oa^et}Uw z{AUphC9a{)r-DR_#??(#;lGGZJi#X~;m<@TuV^wkp9?2H!N*YHL&7OYY+^cJh=F9H zj@G^uq_C)V40Qf#GwZ3MkyC+uB?d|pd{!0yZ!yqYx#!cu*LE4?Iu?hQ1wO&-wTOXW z`0N0)uXOfT1ekproC+0QDI7;=IwpeTGzq6LF^8N@ z!s(K@o}A6XNhQu8XNz!(l-r-I^8(+nQU@Z@$gwPQ_d5wzJp(Wpco&u4y%JhJ;WHAR zf?{O2miUMSx1g1PrMOi0SKCNnhefJ;`!*6^k+6|QtF?_UNqC?Q0W+~w_Y2w(5IUy1 zKiY=y2?_V1eMd&@mz*9X;bmsMMibrxL7tLDJ+{@<@30=yjZevaA|J<8%ZIs1;Ati+l`Fs{SLFi=Xm&<9EJm{Wj&(A9&1UX zx6VK+J=XcyBgEGD*b?-c9*cbJr@;DjU@1pPjlWGi)ryB20u6 z%jUJg=9FPuLt1iP+39Vt`DOFkU<>=sN93$+PC^oW=VOPmYD?+|@?q4Kskzp+BL>*`_*hd6 zNVA(Fje!ZZimKiY``^8|!{Rx()UbyktH;`M64|}KL}`1hOQXv;;;cnK)ZCYdu1lj+ z(UyCxMc>ohXNj&$qdm|<`-tQ2mHXXQ!28Zs)_s!Do5bK`jn%?OebKTswh36zER@FJ z&k=uvIe)?CJC2_b{}dUwelK_ji1z#w`7a7yNBj%&UlM#7@g(t=1;3VfKF7H~2>t}{ zzAKTnR|GvIDDw8IpeJF{P;oa-17}0zA<6x~*4-E9^EB{`m;!B_Rn^t`dszI+| zu+2m6#s2sC75#kPqpi9cR2Ad@18Gr$If$?C7f0uOP$rw87EC z#|9GjkhVHSgpEN} zd=o3^4r!|6A&D1ML6D|;hvfNsxKx^|Mt?(;O;w`@g_}k#WJ{W=<`xlUQ`P7spt`Bv zAx-rP;L@!cac8~{4M)1w$+|?kpX>gMzKn0k;0?D{@sG8*bZ|3#JI!;bijvL8)hI~u zXXX_EdF>}{ILXt9#A98%y*dd|3XYKP)^T!en!hz2wnu%puK3q zxyVjmd=KYGlARMl78j}%UcUpvTBg%bNGTi&IUNm0+(4N&eBTM=t7G=VHtn`Zpmly* zyW@~#S}(Xptx`qey&pClT&311G+C1};?6o4vrZS6MrAaNC$vjXmol&g(xn=E9GG^g z#@{C{A)V;hO%e2H0FLeB)+N}T0Om=^qfiA%MFX|&%@DoI*>UukHar*lmu)2$8AWk<9YXmkmt9g#wJm2M*XZodX!J^fx6I!{}!eEzzXi@Vl z7p)P48kJ=pHw}*k*qxE*RT6_wGF+mfe_+)qQ?6Xg$=$*407px;VDfsZks`-PIn6TV^4;#|lG2y> zHh(}`d%Ugm1OGvKkkk*Pr6JQc%G93BgE@_TLJTG~7GVd1S&fwe)0M9A ziNH(t;5+E7^jncX7KaUTiWJI^G3cIqjnu1cr9$WQq5}QfKEdu>9&HZ_#eDQ1*8*%Wbmf%WquHlUa*eEbl#cc`p2YCti(D3gXde||-sQKo@Ojkv3* zDV~-Np`*&Q{WWdv(~bY$zBFFiZ>??J!Q0qX#i!Bbufy3`mJ^qA{vs}a-Qr+;0A&@I zYxElR(!o4C06b&C_2!=6tUzb(l1 zVDe`BC&3;DCN5AZrOv_YrYKTmLsU;c5lO)hkqvQ;t}zn^1lz4TEm}t!Z@T3jCGohH zfIGFl;Og|u;wZU~+ggH9qnUmjC6ue@fH1b2>?xSXh*eBej*=UkmJ>5SoU<8eA%Chv z8*T5gZTqrLK@I*1>vgeZvC9u(Ft}JeIfT8(fSg(T)HJAvq{UKw13J^lg;KQxIoG*T zYz&-_iZP(fajp{b0RH&^>uL@Eid|>7z!ja41qp<nsNF*Vp_v1VEpI|qmAnNnH~)ds@2sv+$S z4XeSYaEKpmVHHs8jZW(s2qUnDw4R35;95Fkm}QlV-ax|a9YfZoK`pPzs`xezV!bT? zFJD+K*FjPDt6rk{33~_T&wT`oV2tZ~hL6<%E5S~$5Eme}LlJ$&Dn}!<%2oLu&}j@b z8F?{bzJU{uZq`C@kSylppQID(CgxA2!R0iFwXN5Ua-*v3p~_bqsvcpK8n%fZ`Z1mr z%AfGCT9}7pd-TQ{BS~CSPfFiS^!+w?A=Xga)2tq_GBSdYm)6fqe`}d#-yhj zT4<;$*=}eHeOj3+*?Yo~ zP4axBuX{k1R2#W_ecA=81n;tm+|$19U{x~S$i3~;>QzaDk^9o84O1mEjhtI-d@w_m zoNVMe8k%>PDw${G`f3`Rz#>DcF(jn0)M!rkHSbj=jYjNrBUY(O&M~BOeX%X7WRsy? zZfKzrRdRtbcatyor7F3^$lYtqAtP59v8R32o~q<(BlbrlhAw-(5&Ocob`Wz-Bj)tb zJ$r;I*=I;eO|nB!z0=Ujd|Dq&Kn-n#QLR!X4;j)_LqfeiYDfzV38jC^kk!=!2E8xp*WkDp2FD%B+0dq{{e1OS zCB4l+_`aq&Yj`g#DL2%=8%ah}gAFYQS>P>qwMbSOYIjXV#H30_g2r@)7+MHj0iVAR zpG-8`t3yHSa(jPmQfkAR48|c^=gR#meJ}$YQWYq(k}!u z0=5LPrjCFm4Nk**3QTO+{j|1#){r?^<88l2w#qG_HLIcaFev=tsRdTzMz+H|VlT{& z3;}qMIa0%}VVO?Bryy}JrV$pnT8x~+8095MjiQ-vAc5Bsl{Ht)eC3C5Z#*{GIqph)fI9VLZEWjwTKlVb34%mZa@O%Y?`e~HtwFrbNA;@FjZ9w@T zSPkpO6bt=7(`L2E>6IK3MFnL|R`%dmNvK=r={ibDA#TnJCF| zV_X$t`xu{=*a-3j5n|m<{0HpRL#TniKo_h3ScpTy8vt_@F0L&0ZgM>Ig=;l zSzqQ80@Uh)S)16I2%y(;Klv@+OP=c@{M}-)LjKtwYMVh?PyI^(JWt>%07aMxjl2=S zuL=Adz}o<(-w$B=6Fj}Z)0;ef$kShOnnCOJ0aPgLPN5DKmBmOH6ALjrjsO$7n*fvU zj=StJRGJy=r_^p>$A@@?PDZuP>;hmtfEkRS=RjE@#hHyj z9t0Ktm12b*fS7hY*Q@xLQ1e(fe`&+>*TVIxAleDXTzUV2_dC&3GZ>KbBOGTksVzX< zQj-)brvg-jr+Q)WUy_<7Jb$sW?fNv@#1AATcLy33fCZ5fT?Wye+ElQS>pHFETMb#3 zYP3m8BllR`Sp`XBf(8FX%Le{xH6X*dOu>Sv#-OlvWFEkNgs(TDV~3 zVF2?8xENZ`BM=9$hd@UFPXL%k{T*bGa!^3g>PvujW)h&~s{!;%@#P<6xx5U3 z-;XdQ!TT`a)80gOAoLM}z|LIH-Kf4eh5-t7+P?Fo}0 zeDwB&IYMc>Jz)hYM{Q5oDwH4Co^bTnbjbo^Tjf`5O$*-rp0{+Y?At;UPHj5n*IE0R9aI=O(@gFP|xOZe|+#Go{YHKLSi| zPoRp~o^U4>_4WjoB-?CHxPex_Mo!%U1XYe~PoP2lDN(nAu>O>&hV`dJH5|{8?Fm1H zWO>&TSHiXO4O|-obvyAojZOxQ`XxP2virF zBG{e~z8y5)bfqBazh38_!Vg?%mz_#be@fJy%~bWLMBTakI+p&Fs5_4Z-v;N^;=M5n3vRC7b?FpRW#rD7so?vja!wW5d*NA0UU?a#r2vKZLD0f&_+@2tkIkG)L z1aoA20zv&LQTP5yfc2+D-3JI~=jiPTZ^D%Rl&Jd<<@KjT-N$YRtUo2{K5<eS`A)Q=;yh4+7So5_R96gmUXoiMsDrqN4PtMBVq;8}z3{-S?@B zzh1`+#oNn?g=&8>a^0SEc=H6X9I{%sCy?!LPY@}8d%_CjGQB;4NP2q$k@WTi>ZG?P zOb?-@%3rU;_5^a$+Y=Uplir>{PI`O7IpCzXC$K;2zg~y!2^33jPar3~Jz*1c(%Ta# zmfoJg;-t4HR6s1fJ%R1Eb$bF^X6yEZW(c-!PZ)yo9ZYXexDGsQPl!9sFm1Lc2po6V zAjRd6(8sMV7nIq87WcZuottpZe-Z??p*E5v`IYlK%211Kt5pWtUw|XSAzMylH$?E~ z7uYlU_&7$^4}fEPf{O;I|DGMTCtzNl-kv}>y*+`+q_-zX0|q`@!^^KhH#wB;2@hvMXAk^@?FqZVPj63PMWweVP%6DWfdgrJ zdjd0>-kxv;ko5M1wMZ$wJ%L>zy*+_QdV2zq^!9}3kWPAg0$+|zZ%<%4>Fo*BNpDXe zlHQ&`B)vU>NP2q$k@WTiTEm}TV2fdr;t>4#1>#IqaQyiN;-C4r*`APx=H_otAe`Qw zPy_^jet`oFL9u~9zpxu3Z081-?FsCL{`Le`h`&97Y3Wqw`x<6@Lfj#x3;Uw9JhX#l zfa4CkT^Du_zm;Ak{% zOyScQ{ziq<$^^}nu@~_rcAvnP*o*iQd$?NL;7ja9e2LvB@Fn)5 z3)&DqC4n!o`x1PKy@)Tdheyy2!N5Th_!4`#MiclFd$cg({0@O;jGrfp1PQ7bKTi~K z2|F<^mqfA%hhqFZQ6wa@r5Ha?6p@`wu^2y36p>*fJEo``p-fJUpC^h$3CCmnJW(V@ zI5)=66GgHK=f(JWqDT(mb}@dQC=w@}ALHkVBDsXy$M|`oNFL#W7(Y)GX-7B_iFsaEV7z`BKa4p}%uyQmZpM)DRr?%pnP)5Sl zsA4Nu6MB>I0SS38hzo683H_alcqsj> zV99P~godiF#9QZ}V3kBZ~ zyzkcbDl`+fqkLp`5Y{NsdC|sLF?|K99ss3PR2m{U9wMl|uR+O%(knT-){Ya_rC<%j zmlD)tAor0Pn=FhsX+vsly5N5&zJ(c|A$V~GYSAgswRk_2+xWF@Etc$q3>|`}=msiz z%_m8nU4V?;$2u#sIoP(Xvpd0JD`{gpfE@{@!ul;mm9B;9W8nu8!Hdk`1@W2_0lf0e zcX3O0LyS2n83uC#yzOV;n9p#Vdpl1r!lG~82TOzVkm6PpZ*UfXs|b7tseJ&3_@b4a z!TJp-NR5mVy)X)CXz1ux z{;)xOBvvmHgV4tD83bqz!kaJSEzUj$%{v|NaRQ?)%wii|S|7tR2TZxFmMN&aDkQO# zvMG493aJS4Ig!(VaKzp*2oIS!gjh@2Pwyhyl15)7Iz&(oir*2fPNO4_K_`mCNMk!Z zz`1}KIEP{vfL=X~=($Y%7NR55XurXD$W#ff>UL1GHd5mR&`Q2W-p_+rzp88vbORq1 zf>#nb_7!2A)OBK^>Za+|uKLY0!jt};a7C+d`9=s|h9rK-sxgQn%|hn3s*Po(zSSm_!sh2?YcCmo5W`%uY%A>dFuH2`#`Y*KJuXg)c#lWCN}ep zT0!g|#A?v04-@z~bZYRz)<21S38dewxE}aQ(6&(we9%_fgr)k`=jtJDxaP>~zp8wZ zp+Z)ViRdS9GNIE4p{>D(=qHWPs9FgUvpIMuXvbca1Y>S0EwURTb?8cSnRTn74joB@ zQ`E71G2S{UnwEXm$ez?Ht3k+)NI-VRL9F*;DuSdr2-o4|%Nd;1;)CyM^aN&Z0{gke z!F9}XV4OFNWf-6tWBH1$2J2VPU4kcA6j$RmP<1fjJxHKR65#vwRj@IbHjYQxhKn7M zT1!-H33?6C8nIVN8xIhLSBBEW#9^=&m#A$t-$=*b3WrGGmnMe;T5~82HU2IZ6jL{Z z@sf}6#mpRGpYUT!;0Z~ZaD)ULKH)gdfVQIkJ_5;VNg&z5zXGWdc^Ui|fZGW?58yol zZvq%`ELL>h2Vgg=37^Z=nMgC+&@(GYs35n3vK7>C+i@o}1$gfPt8bLf{h?qm8ZDK};Cot8lkD*$DkR0XXD1&e9L#ZhohDhd1}ZTS0mi*_%Y(BFyCJ@A2SNkfX|{g2a21 zWQsEej4Serp-d&$Kx8uCG~^MUI+^ci@CY|d=F6Bo!ZRoHJxLzn>67_3J&*87>W_%v z9Cbqnob?|ka8R>+NWqT-^0%lXe5wD6U*PpZz`gz-_TB_Qs^Z!kzqfDqot~+l>7J#h zXJBBq24+}hV{3+)0Ra_e24rvpTmab>P+?eHLEM+9#3e>iQHgPnCdS=pOk#{0HH&*< zc!@D4QA3RJnN9z{->JH{ZzCF$mwf;4z3-uY=WMl|I(4e*R^6)cpyn=H%n(Wx!!s*P z*eqKtBsu3)rL{r{E?b;IO3t#y|vy@If}UP0JfuOMvJD|qM!*DL1XZvhuA9>Y(vnq9A$2<@Bo3Wn4-M7!;T z^$pSPM8f*&Gq;1Vw_ZWmTdyGOtyd8C)+-2m>lK6p>lG(4WxZZO&|9w{?5$TY&z84d zL4@lS_k(smgrp#W^@{H?K2h0`1ikeNrs}O%JPW$FUcrKMy@F8{@YrqsOq_}EFM;^$ z6$lKvu z)+<!S>)US`hIUEr|Gw7F;p#7cKY--(R#~ zI{u;s!}yC9MEpeyBL1QU5r5Hwh`(sT*sy3pE0IMCmK=)~#F?rn2#XfPKlE_kh=wzj zxFF#zS`hXZEx0m)MGJZvS)^c`ShV0D8oR_f$g1L*N^FaABO1w}hPMxk(cc^&>l!+%6>>xN;kUBu?Nh_~=TwEk&OHm5Ja%Y7@o1F)Umh9_PF*MNk( z@pzPLEibArxbh6h)bgV0f~#1G1&seXu%(Q)Rr@?y*K7l22oKuO>8Ky9!n~tiE<350 z%TDU$vXgqb?4&*o!Ody8>?AFhouuWmleAoRl9tO((sJ2JS}r?D-wFBrw1cr`L0T?5 zNy}v?X}RnqEtj37<+78sTy~O{%TCgA*-2V1J4wrBCuzCtBrTVnq~)@cv|M(Q)|Z_O zt#M*&?GKUh6fZc5_1i^A*OD`vV(aZvAmP+9ayAHOONtkq#5M}&jEcv}*`&kR6>ktb zK?kxcc)>~RL>K5PPXfrR%jS5IEkHN^X>@@^9qJSt;~cd8}-c0 z6|k}?EyTeZAMN3jbRb3`{5-3YygXiT5JOSIPJP5F?dlgP(+yl$h^`S>V zYv7^FYG;VKuu?p9S$#>6a4JLOMnR$}zTHw^79^J9q08zfK@wIT4_#I_hx!rQzzTJ5 zs1Dg^m@yO4-Y+6n!@fiw5G0)XP9?-26eOCOMdTqtVkz$2RSyf2Xqb&4-w?RW%6pPx zIA()Mq}8`Ww=fA_gQp%B5i3QLSKk#RoLWWX2|=O_IA=?JPvBSsLp&*PqG2DvPYGO> z+R6Y=3sTX*Yw*(^W&<4DRmxIjInD74OBj8SnR-XUlr-=lGxa;+=!4AEZsF*I z%+&8C0)3E~dRLID1|DRl{t#m2*EH}TGxeTCpbs)rf0PJ@TX{UlOuZkv2W1&*+3K&M zS6P@B9xv+~qt;pnsS)E43Bv+~qw!qI2tsjb4Pv+{UW zo;uz6B};#hI@fswZ%=gT&lh=9dfcprG)(C~Cmd7y3x(sR;2 z__!|)$qY_?KzDJKa7^*H3#YDO>a2q-b+uSRx?%Q#Q!RCkh&7}puw`E>V#DEuk)0jd zlp5yH%&!x%mee$gT`yv7sU_?HZqRm>T1jN5Aeq$3%)yrg=}4_1=SD#$r{1C``m)3} zE#(rykvGWoeht%@&dtJ^o+>8i7U6WKni;{Z!s$&_k%N2g5N1}x0SI!tFlMKIKv#H& zFy>&8N9}yY`2~y{p6W^GOL*C(>-lNP36VDRD1xBH&KZp!MUbfW&(BJgh|UelImp%Gqm9#a$XTmgPbF&UKI|yi_2KbpEys!h-K4E(L}c3MsAuZ>fqwK z-Zaz5O*0rAAzjMrkQwz zpx!hScM0oFGx0padecliIs+mx*)$W+C#*Nk#ATYQH_gNq>3Y*lJVsb=nu!+@)|+PH zMTGUHnRuMA-ZT?W5Z0S!;>CpZrkQvNVZCW4UP@SRnu(VY)|+PHNy6MTGaG+p(@ebl z9H=0?82PW|Jzk0E8iKsXE0HfC@9|0$2*`W95=ubc^FeO?nE<3Qj`3)*OS<0r)5xtq#d!>&FG7(cK1=dBtf@R6VsgZ1 zi8>iz0k`pR0aL~z`BvoxjX$GA2lrS-99$JpBX0+)=w4Z+ldQ&LSn^3RP$EtS`D^TDK__d%kr5CU zv7q~C!UL4ZFwQBOa3Tnj>TzD2rB>r_8O79v66aVd?_v_BX~GN=u47U6)r5g0ETF`G znh<6_Z^9J$+g_X@tMYEZjU`mT{v_i{X$HH8!Di^1Z6o39ERG@Iqotb0lS$~&Dtd-G zyOhQ0)r23AFqOrbsR_@K@C<{@(u8M8ut_*T6T~`ZlQ26=DElq5~FhAE^m1A`?<^ z&wC*pe8PY{MD69{@F%`*DOP(|=px6f7d?isQ+QT8=&J~a z3m?SG6niz{Na1hsro&#t{@AsO{s!Ha+w0C}0?SrneRVyBtU_KVXKx^E7xJqsdm{sc z3VT_nIG>x5-b;O)AQ2V5Lij{R6V>Iu3ZRrbW)uE11Yu%0vr~WW=YF9xHs5hHwVq!or^uK9e$u!t41if+Tf? zCM+RA(z{v{R)HX|eXc;lQg~%Gp1=fdI0ux7)9(q~?+Lj028+3T{ALljlLE}lE1tj* ztFeih`00}(0JT|-VG`a65H?VGA8A4jq8N2HOL%eK$gx)RuLxmppN}9-lkuLanP1r1 zm*>#~6?Xz3!pOcL_$1;(8T1Olj|7gl@mra})APy@85$)bYgtE``FT%|v7*y8xRjJN?r}r0 zOiy#&{x%401;ec99~o{mKB0wc3Ev8MJBa<5e%ss6Lg3c5tIv&C}VoWAoUXsJfY9hQ$_$v16F)Sz)?gXWIv-HvgI>JwWh%5xn`K zLBRXMtfKD_KZfO=BY0#Il9TIz4ix+e;w#rI!Kct++Ta_&o6lo%2MfP_GVnh!{2_v0 zMEnr)4;B1H;Nz}f`f~-hn%6M#dEv{ESKi>=%#nyaUzk54eh(u%OcEO~1-nKnP~SgC zfm(40&RG%W`CyPU&$L?6Hzr~=39Jd&!Le=H1nfd=v)XLk8QP05Deq16T~;aU(^g{TQ@0 zpuMbV*gKc`2}soNyM{E&D7ftdFr>OHl>G!qBx|%<^FQ+Hzy*hOFj8|O&g)B9Y2_fZ z4(6Hw{U~vt-7e)k8Wmtqq2ir_>Wq~cYGltave9F*vH(3^#39_*nK{VB7^*cEvzsx_l$_3{Q1lLFRb-DcF*X`m zDOD)?`n@N-1h!{r;W|-`-45#k=^}_#Xp%I;U7%eF z+E`7~m)^4wG`HUvX5Su6dyJKN&+u07$%9dRXn5!D$?LE(u@P4EOGxl$%|kjYKc5Fm zniYosM38T{dhE1e|4OsT2!?Jk>`1*XHQCv~k1xx#D8vqttd0QF)+j3^45q8pn<_?#anFa=9 zuhI;=MQpVW`2=Hr20g6_!K|DJ8hyb0Tw&@W`i^hdjCQL@Z`~g0wS688$k(bP7P-KLnA-ZXIO2ofc6ynh_?3toZZBV0kGc$d@P}*I5e;_I43~->S_~o zJ!0+?S5pEGHGQ_>=w6SOf=>}dC)a2WrZA$4I*^&YhfM%c1$NRJMKqXDKk(UBrp2W3 z+uStPT5WT{`O+w4|7ZZ$js&n3z*(^IwkrYPR2--g0CUKblb{b{3-?)>d%$34v5#h; zIJChQtL+&uq&s;D0P}i`kucTvsIIoLR^~Mbu--TO0vMY$o6scynDBLbCOiNPCj6jg zII7}tlk$9U7+>2^3>lW8kIXay7y;mQEgRW()2Wx*R%WglZ2Zl{EnOkCz61<5?NP&| zw5DlCwq1c>P_YgVqmFFbDG{9tc^dybEic{)ZvAetesnPh+S8?5VMBQovh-(LwQL|# z9lIZC3}Xs&cY<_}2`l3Rl-fnk+_top>4E?wf7OIRlSOX#i1=_LWWfV* zXtHg)E*2}*Pkn9my1qOACl>eSy^$r1! zPi6K~Z^>MSj#Kau_G=Hs=&U|$zX#eR>}{T1Toa>h&@0qtiX44(4$^Otj^RAKS$6?IzwrS|Zjc|`oGu{XX(n;hC zdp>5E#h;z3jI2dFmc#$t^;z%3$8+?Y9!3!&i_W>`CdnAqy6UUEyQO1Fh?-V2d zE1zLyrW+bYAS_74xsP$Q9b(AVR37eO|IB%>9>*z54bVaA8u*#iK;BfZ2L8jZfdZ(4 zHE<|uOHAShuL{b*VHK=39Mdy%P&UBm^jyutn@VOSGt{W{dJ{rVuTY$kM*be3VP!H# z_*tK3^w(vCf8jIGzZ=@0HO;Goxh9TM6jax(iQ`BkKg?&qQyN;ArbQfG2OCTrhx($X z4o)`m$M_5k2n=nj7l*Eciw(K`asx>HoJplvQ~TL2pK~yPif)l=VF#wGtk;aAI7 zjr>fXVP)%;c6P^)y@aCR`g^W z;P#CeeC#Xk;cC$WzCdV}*HhOziF}Mfp_JzIU`Xx|{AJ){Rvn919M?Mxiu)@vC3RNx zL6mnOaH>M4JrU=LC03NV!-#x1azZtZ(Gs@yFVJEe7}VkcCaBROCq5aI`(>IHac*J> z+Pkua;^104e2$>Z>#nHf+i=R(Qi zS`+`bvay&fZZZL0%5tpCsfPHLiJw`#*hJw%e@N3SC9-(Aksg@kSea`;WERJ2qL)R? zJ9ZlJUd@R(mq`}yG4U_U#$vMgkO^>7mSbfeGsKHb{LJEyO%yk01+^C2Uop}q_o!Qscg@@8+1!#8`lUt0H}#~Bmq&s+duma(GMRKqUV5T{m` zfzc4QpG!spuQQpm8nq85mF-TEC%jX!wAMfM2q*?)?ZJHNw~V z3@h`vp?y6N!4FLYFZ*)Hbsi1`v!fpkFqwJDgnQeUvD#lVG$a~v9%7wYQ^&C7JspY; z!uMGY!0oM=eC{_vQwi@v%iHg7^utff_q-nwKM7vO;3M}1&ieoiJ`*@!9X=z{ClbT? z*&4f(*pihS@R7CbY)b71M>U4^_MG6&z{gv8Sk*(qx~^Ufnek5B9Ar_(StkSFFnpID zUV6iD{UWM~!|+}ihOdXN&wwoJ@y|K3E7ePpzd znGa1w699vC-D^T`!*t?t(3r1HxiNk$U$lW|Aj^Dx-pJWUvfmEhv7{tI4nYZj4?yJZk!I9==dlTtj#c^ z^~_&%B4&@^Fz1=$O!zrk#Cx^70p#bwU#iLUfR}?b9yNNAiA)!1Ba9!1_8-o`(GSO_wk!3v{4i2p_vjhO^ z>4qGU=t)*)4LGc)dku%Cb`EGXwO<&TDZ^e9$B}(fh7Yx@qpCmf%J7hhX81U*3R8wF z_g02)n`oxx$g&JS1V_s73ILX2d5%c*Dl79kI4r|ShQl&^2pY@qWkWM%*lXf0JQwTX zF)fRCTw$*a1HfXUKQYl5OND_qm_YBFK)T?3H`QXo@Prk5;Ap+o-fpDX!RY8AX|;a{ zBceHj3_HZ+kqdxb`Sgc7LpI;kO@g!ADb8*Z9G!-yh=Vk+I8O~*`}6Qh`_K@_G~XU* zMSmha72mQo|B`Vo5Y7_#LHf{z679O!GEpwVQ-7rcKiaPKahZx4lJs9mv3?nNIr`rA=O2L67^@iJ3 zSS{OT;~R=RW;h;V$J;*uCyUCkZs-Ir>*XQBp>1=UWo0=fTVuyeM@jFX9x5c@YT#qA zOkNop2jPfw@iHsg{QC;<2S^FuoT2rkPo5am4NR8Os-!nr2fS$q6r+_gSc2F+R0{G; zrNj{{OS28@M}7DNxBY0t2olXugE^3)M%*g66}86qerEVOy|WTo`hv}w`pya*S1V=h zY)4`K%9jz>2xlBpW~E*$$80P-5Zv#vo82L&1NX00qp7AXepz-( zn5!X^sjJjwd3BGnWI7Dvy&T2_I9bCeL6e#V6Y5^4zW)>X&ioAqM_KLj`o8areV2{NMr7I{73(Oa0_Qa?TT2Bb%AF}5BI0}3X-hYuzB3}K<|6ea z+;h?{l4F2dqhWFQX58lP0ep3Df^u22c@wo-Bb);%I_j|jAQaml;FD)e-;q_Wx9aT& zr6RVBVl!k_*L*2$Z+{6g-CV+T|IFvL)(j3ecEDe)kT|AxV$pXRNS7jT$1DI}ComVl znezZF0dN<99tPWmRwlwf1*MxZ_MC1?*au3`k3eq2rV{CpOjeMJ98ha-Kb}c36Qk!F zE6Q0gp263eFAcGxS4hUVFQNNuAlb8fAI2Zoc@eK5uATW^zzYz;%pU=`6hQCK0N~E& znZL&0?}0Fj5w&5bLlGkCU=-ztVM^{%W}lCkXMcf@9emu($6a{fU*G&ZEa2c*ct{@) zHsG%;-pBK&_$wROhe~2a;kceY?_=?z!}?|nKxy$y*7jYjaQ+B>B}ILW#n@YdUujui zD=7Sxl=W?adGJ@%*T)-o_$xZFk5_c_SG1&$CpGX_R@~=(rCxMMUmuK+zjD?0qXL{K zk6$X@_ZP_VS6&ZDl9^Myy1<%qWOJ1D1yJT66+*nCu~Jvy5Yu5kcGy4j^tBF4x8`V^Ckc@=kU7c0RAd|c|-89t?>2u6WxO92~T98 z{M(#cL!jdWOnemJ+#aI5rM5r`&K-h;)hVOH#m z40l)PF~&U7c_Z`_@YEZ~r}L(XxeyiP{5o_zBuvb|39(SF`WmX)`K^dW)fXA&EkR-h z{EWtVTf!vNZ0>O5HTZ~ z$DVAJG#Gk)kiL&qk}>p&hTf{>%cdJT;}F_D$PXsnmc8=g@z_2m`C$c=iY7PRt6px+bp6mZ*#zUgz10h*ePqq2@6^8#QMv)i!ylo-I#7`YL&OLihTYUp*H zL(~*C%=(^#Nm|LBhV39PRH9+qWVc!+j~e#yTy_ZT{0&xDde)GQR;^X?j1lY26>}h_ zFPABK#Ypft-atBGNbr?F$s2}$el9=4d?1_e8TKu??9G~8_Mu@1Vm1Y|Dr0Oavz{Jj zMZZmjY(E{nm)80$YW;4gZoqM?c%%@~=Yf_>>l5^Sa;5RjqB>Ix@YY}2o}f5#N9tfU zc~iklu@3r(EfNgXFo)P?U?n&+RBB>1d^|I{5zjt*5{uAbmDCvSMM18vr|>o#Yw;yb zM&hnq3074Y=k7qF!$>@zE5X{riQ}v-tEAh={AaF=RF&N1Q-X87B%diL%Fk!0U#g1j z{5Zp(mdj^V#kW~*$B_Kp12$NbhfEp(%h+Osm*onx;mW=WUaE|vm z+3cO?)0j7tKJ#|N-Wbf-V?l<=l?lgOz2LKTA}c`q%^tLMpxN4$YQ0#Trbr%rRiQ@S zrfLULwJXr1mf)|wox0UEB8)%yH6m!)LU6}ad%?y69lQZyrAE#Gz#2J4r>qr3g`?qqIa_Pda&k^KuXF|k@^ zsR6>1A!Ki7zUnxbI0RX)C$9xO8iPBiL*yYVU4!w8{n}7$9Yt4nG=4`R z?-$|s6w9zhOJziA>M+Y%1&J-6Ak`~UH$#dNm$vUcu7x61(tybmBvy3nU8-NCwnB;$ zM}JJ}W>{C)I!C02j=;ABqlV~guYxFF0LY|F9|qxsBP-YR`%?)$T`-qxgn3Ll=Ja)IjXuAKM~WiX7Z7LV@Vc=?wZQ#)WEQEnvmPLR)=%6a-a0U`Gu=(6DO2Gop^D z;jr@RRs>Z)f=pD613h0okFW)*XgDHJA0bps&4fk@)fN=0NKJ!GT*Uz=)EvOY>Rv3s zmZ%>>!KG>!a#^M>LUxksT0G0ug@`Amo`y_?dIir)^(LMJR39VW$Hu3kW?d}t8#SYM;->M*`k?ikgGuodkdhMcTkjS z^*5wjqpm`nwdx>9)~T-|wtDpdWYQ{%P(#%Bp`W4Zbc7wI_D9SOY7KJIs1`zF!xc6Z zS|ikl2sKjOgt{K3_QSJDrBIe;bq(k(DvkJC)hU46R0$fzXf*~hW7Js0HdeJl+vC)q zpr7&T7{D2|0%0eptw^_B#gNKG^(?p@DuU8=s{cSdUFt2+C#lmA&tx?M^82VR(5I;T zAvsm;2gzw_C(5|5x){&>)L&4#{ng>f?R51%$}&Seja+rBJE4Id^;49nSKSPmnd&3J zvs5YI1Jv8d!)(Qk$$jcFJm;vBppygDeSi;A7Xdz4-GJvI>Rvn#RUzbIu6i0N&Qtf{ zIbU6b5*?;`03WWn*Zv4~JaTxXx)1aPsvPnQ)pDe@NbxY@qtsQ%&tk>fJC~^2QHrJN z7(AD$-H>0d3Xr!I>U_wrRKr0(T47g!b&TTXomGlkQdg_lh;xniJ|T8v*s`v|uh1&G z7=I$+ui{y>0}uFugF=9B1ss15(L^TMl#JhuXd?Xr$H;sIzd|d27s}v{dKO6j3MkMW zOW#m{tv{woxZ{tCz?LT=TbBAIs>fC*qDUciFrJQ@fr5qAcTfQlH3I5$RUw{vYBo$Q zs{Rw1&R1=q6sWuKRO%KyV=9ejp{jy%i&O&&AGg8}qx5daZsy|@#O8J}+5AZmarcLW zmH#@*;!Y=+xB&wB7f@=(HIRygFT}Gr|0~Fy+jFN-cH&u5N;!N~V7Ui8F4TMQEFFie zwYdA*?*S?MHH*K$P0d+l1Hf^o+kXNhY!y9?Ke2ByX%`KWJ{xZuBoJ^Yp5*v1hakud zyNvLWs7$w4roH8zNLu?8cY*x|xN11^ffp<_)ZM#yI_g3w*-^_xgSA7c#{}z3g^;I+ z8ZFN`phwi>La(9*)HdkURWW8&ErL2+^?P}KN9ZNYgKB_eo*IOh^VC{-wn343>Sxe< zp4tscRGo`FMAiGqXH@+Sh8DHr7okes&2}pb!@E}9tx}kHGZQ#d!;`77b2L1G^z${m zmdRhJ;i;r=)9`F0=3c7d!w7#t!!s#!rG}R2K=M>M>GWqeG--={*q zqv7M(K%Ulcl4(7w;UR>7sNs56%<~%l3gutYFg`G{+*dU`pSt~-hPijj{gsBp%-e4S z<|+BsDN!0)yc0Iy{?SR@a|!@FN>TDQuzpE+t}Rp$j?Dhs}P~3s!;@6 zJpv_!)QMtqW6;>bY8ajobp@@;isPFt=rr;r1dIQY`MxWUCLfP5uaD<3JK=?(=bgkM zM3I}1*z}p6;p1p+TSVemf~PTHC@SwZ!#rg^?-E1;in9O;H-}|~63)p;KUR#0j>b<4 z^bua#0*-Hnvhx0FlOE><-+7@B;ne+z-X5FR0N5LO+1o3yd@(k!9kiVbk&IR1u=(Br z(XcIpwF8kKjxo1mu!id-tY0)D7rBEq^QKo1)})-FZhH-~gd*0N~ z$Af#Ipf*GbZ-8{z+5cU@Max$8Th5FN0mfG$O6TA&0<;oefrwpCvR6iXdmhwK4Altv zrwf7LxP3wT7C}k(!)EOvtTd~1p9NT^8Oi{!f&~=oZGz$+TB1u0dX`4) zOcWV5b%Y{gz8`87L;aGW%AP|yw~#T2(KS(fe+DBJ5tMmrT>*5Rk1hpT(a@z=x>D!+ zp)Ld+@!f~`e$V*6!Fe|suTnk z9=QxOv(#YW6d$w-ryft;DvlVVTg9Wu-4f(s2Ks>idaDQzN3@|?_Btl57eAzhoCn-% zA)J+%7DDnKE#y^@{<#+NAwrrKawS01LcRphN{mOg?0S;D^4i;1LM75dNPY!+mli@~ z*2=xM5C(V$EYm`WHXSV}TL{rj8f6PP4(PCBz|}2;+}~)FEre+AD&ew)5PeLeY#|I= zwi;aBLdZQ+qii8WzpGKU5TfhWh%j3S!|pg1C|d{%gEe@o>`ho2&n+}9gi5x`dnfC4 z<`$ZuZXt|pe+0nml6(xa{Sc#ch<=1%>p02}F^VA$XNdCqCRx#00Aiq|-l45FF*B!v znaZR71^p_}iW)?o;+8T^`!z+T`RHGX&hXK(#{-?^qtl5F5tNPcFrssP^aP?cK6(Ms z1AX*ipeP$p;yRGI%(lDd!13B0i)7lJfV$lYsM{Tjg=yFZ6gbfCL`8eHyK;zztp(_I zO}l#)nPG2~-p7ib1Ln;m{}t^n*w+64?u~dKh3;v*GTPe}O6vDUyP<2pH-eq+tv6zT zGTjpq90w_&Y-dFIq68@08N2&)ftq$E;ij+$8%FTE>mfLW;RHPp?_q(mjWOIGiRv~+ z;lFGWlx>XY=o18G8zXw$iGs3?G3@S>fO@^qEa*Hr8&>rZy6o~mFO=K_Vi{VCChATm zxuO75Pd1^^W7z~!8TnJuDSxI+!9fYUm&0zl12$4wDj=-HTEv=7?m&!pFz{E!tW)>O zp9*e>w3|*uh>8~kJcHoyy~Xo9;u%nZJXHQoBpLUN&3IVJ7Ep0Ip;h@hInpDo1!rLS zGQp{b@~gApH?!bL0#Y-0UGoCcX3Hr5lpg76s48qdk70~y89m4=TgGkE^gGLq&7aUR zWW*VoE(2w=9`B9Wjzppn4#~`zEzA*VsK;iz-~0HD1Fg&P%cBU!Z)f3;>77X4qj&lh zNTzq9d|>=0Xml zWTT8}Bm`@>2+Br6G^0^Ak|%&3OcVw?41+6c9grjwLw#FUf~)OwILl|HZYAL;W@-d& z!>YKC#*!s$+d}FdBMjVshWcz8=GW(XQ=e}k83t%?kuZEa>gWNtlRMzu8$KphI2twTYf z3cn6N1Z?W?5`Z})j2%*kBzxtxw-16!im?T&eh$cYZSm_6HV=oThuxGhbx1IFnqP-R zM{1OH$Z_mtL@}rz#&n#msKe(_GaUMspU(7$kJ%RogT4!eFN8qF#X@7^<&do;9peD& z8z@u7?ZRVDjt9?5G2~zX71HwYtsOSxf-zvAwEW@B%s^@R8kCl=L23EJnLYkX%|S#= zWuUbE5xQ5zTk*?4LoIeus1Co7b#()6Wk4%ta|rVqeh(v4doBmuB~lkaY8ND`_S^Fn zJ}wS}-SPE@@gvSS9SKD_9{C%BdLvr}UP$g)44e1#Ia9v~r?^hHeFTEJz09Px#J#$X zytxoK7e84z`p9z8Us(B^`b9cOb~yD5o2g&8`xTJH?81GR{AA58JV#K^?7{~MiYhW@ z7vBGGfW_>>GdSN9vkM=*6QGs&3#+l7t<)>7y}b?^5!XTK2e+EemdKxg7(aqprf-7` zU~G_J71|C^`VpejHA)+71bQM+)7g>>ke#hWp*vcFH!zIuXc^{Fph@^1zU;#mxAHWq zhBm@JASK=92&%`bcoXLQA3kxU5G&s$;WsSkD9LrDgD7(d>|uk10YPL>M>Q70VQa{6 z-(YHu!K^~Awj&p>wfzq^m`W5@8;n<6?3RT_e1mxnbtR)S8q7Io?A2fxz!(g{TOnl( zhUnikN`q+ydit5Z!ALl5Fa)my$BfR1{#>I7H;myvBI+5U)_!Q}*R7QdXo0EFM*C-)OOmWqaNP+-Rn zb|CX5reVc!prjSP9k8v76EOT)3)U11MS6ff9hMMhtPkYz}3U;NE) z$KwwCqzp*tD8T8+_+dzcLoq8dL6>74V{g|f-9q|A!qM2Q2w)sR0P$D>GuBBs5yOGF zR-}t?S?nI>U=rbq*ec3QCR`Q!J?Z-pu0dPDpQs(_Ue1(gL`a4+F4rQB^8 znZ-O?cIj()M*4{07NvaZa3h4IAk{b)w%xKWh#Y)3qZ5rCLePrwonhoqCK`_MzVpaj z9N3A1oK2O@`vKr{pc}@N|0Ev#nJDAo=YW*O!&FXU10K=H`oH2&Y$tQFfuI$`&x&l6 z_z@3HB=IdoT@(4@Dx_Sz;5aLCrAQVpSZhVD62amH8?DH8g3;KE41e`9JY%^30q`}1 zi;5Qi-P zkyC8mvJo!7GK)mZPed5QiIwM5MVlo|q8!cFikxOQAS-3%90f;C7fwa_Ac~zSNL4vM zb&H&3UxZOjO=`hvl=2+=G9c;lQi`2t-w33kd@4(HfrJ@ZzJ|y}g0z&s&vY)9bjFmI zM1XwWz71hA<$qJ^g8=lh|Mj(mJwVp5gd*RIv%-msj0*+lx;=i>pw)&QcL$_Yw2F9FD$imA3;+~ z_p@e9Ej>Wk)Y5~2T6&1`rj{O&T8e!al*qSeuQjnb%*}UpBh7TIt{Culc>_>GY$=uY zWEbF(F>YUtJT(_^OYwsBN5Mrg{xN`|(GMiH!=# z${_SK5X1+wc+y7k?Hn82sUD6zzX3c_ZQq2PCLhHk7OA%%0l!>)!VrP2a-Jp;87h_- zEydDZ(c#>TRmsH-xDw-^?RX!V0NA?lKE#F9Fij7y)R;>K@ zjBQ^VJ*Abf@<|(n&?dXd0dNh8$Xt5?W4w>KILsE$UOtz|;U-HXp{U3a!iknQGsYt& zNDMinc(NSrcXs3`I|LgqKZNNo6%)70X&;eg*pALNzYfVqmJ1RqAIwNs2vSzg9T1U~ z627YZ3?fHM+UfEXGjfcGHIy%51givTDR;?PEl8%klAJYyOy&jbPDELzia-i&P~ z`~dCkt=Qd!ALR8YyGwsX`G?Pee1l!O3N7CK#uY$@+ofa4d4x!}4Sg{u@h~f40DY2} z6bM%d`6;Pvc8CM$RXij7o-nyw6%Q{($bl!)r95fVr4QUj_$dt^Pe1y!hOeL&n;bTh zf!hc-J2w!{qs%@IyQ6rRYq>>(@TeNZ^@+SCESd8Hz~~{YvjoeS$sf)Obz)yZN%BWh z!ixPIy2>9#I2_wVdK2Mj>}QbAZzddz9ZR@{a3XdqWm*ZB#a?6BHo_ILe$q!1u8Pe? zN%F@Ku8F-&`dGs0*dpXOe;lh3o{8{y!i}-3DU%^QJa!wyP9QuY*306Gsx+!DKv@{4c-AJ$DA-m}t-KCY%uMxjlr-M0;*8;R?~7JCksgXwRKRxJI<+9zZxP z+H+?UZV>IceT234+&P3>M0@UmgvW^X+=B>bEcZGVs1CYvm$DFvZz1C`clix05KYEi zNkMHg?$Ly`$+*W5j#}ELcgMa% z`k92^i~WhkI*afJmisl7E}t;-D(*;WoOu!4)%Z6(+_nZi#~7}pG7^76#0htMK72{+ zCMI$XBeP=Xv7pxy4#%z|eFx!atd^O&j&RI!pGFLW`bfEj5r|uC2B6cGXSMF?W`e4_ zI<~(`&R;4?gTEL9R}l|0m~@IK`;r1NrOJ^3aR!Zt`E`^eM<*x=VZh8LbCZWxTZ8%W zU_mu|b8lv5Z*Rotulih+-)^l3!=7EUFY<4<)gu>c&VdmhjvBK^GsSNLtzEJXAE{4a zrXM^P=(@Go;4qb$syYuZJuhQK(-`OJL}xSXzRf^~pD)?u{3{;Dx)KTjYS`k*NM_df zHiW;3U(0ly#|nY3BCdbWtPwL$YVDtyFuIs9K98_@k3s|Cn{FYfCyb<8Q4UUiiC;dH zXyMv5Oc>dRs=$O%=?UXK5b!6A3}PmX(5e*+7lzYJz-)CSZ03s8UEItSFJ#Oz%4sEN zC9-ox6__ikz+6!U=86fKE8;^G%oPj6j5FGT2R^vh*+)WVuE7!stX}hY;k&UWiW56_uVV-U)hC>AB)}0iOfiFsA6E zc<^VUEDS#mq_i+h<-|AOfw|(l_@j0r;>ZSqd~pZZ%oPh|t{69S#iNjNLgtDhnaIu+ z6WO_xokY37RGf!N%nnJY4a!%@-8Q7J{#RD2i8hPmPs7(q)d-IJ{)Jy(=k z(sM;!OM0%TYe~-)buB#@s3kpD)V1`8)ROuxOZqL^YmL%##W#>xcg1BE6Pugfm56%_84t`R6!VrP2WN@ySJcZ>RW=q3BGBl{dFyk!4Pv(jaTvF1^6$xXX1fs@V zk%*fN&J~kpuDBIa2`jo9e@Y=_vRmfO6%S^NX09lnJsF%UCe2)toM_U_6&WOkoRL`O z%@sdjJZ7%QIL6n#)5@|{D ziMb;GWRe(ZaIQ#XaClfp17 zp^`pHObUc;LjI;yHao;hdKJ$I9}(sq@;nS72bj4cUHSksR}|RH6$LhPMK+QFX0G@} z!e*|>?r5N%AF?!Nen|br&HV6?0_a4~52Y@Zo*xnpD?L9X994RLNI0hS{E%=$>G>hy zGNtE-ge#Pu9}=!odVWZ_M(Oz>;k458LslKU5e8}b;|Vt^JwGHoTTp`+XXA-Uw?YXlE*NFDq0|=)@d+uz)4Wd1_kFeIBJBM(KXwN;6 z@EFmadl2D_RdhZJr00h$MBK~|KgR;;`5^_d^LhfB(b0sp$+*W5j^YplNDkEVLk5bQ z`5`Y{PU!jJNdPUS=ZAz_l%5}+4|t){^FzWXD?LAC#8)UiKP0?e>G>hy9ZJs+uY&we zrRRsF-=_5Zkn!KC^!$+YT}san3BR7u^FzXKDm_0W{Fc)5L&Ce2o*xo^PwDv~;Sa2$ zt5LcrVdhm_kkUBwBDkyZTRq&yZR?ndxK~mcaWg;s17M}+hm6cpdVWYatn~bla8&8} zAz|F}bPqxe)bm3|Ag++_#dNyztk&Jzcu;lsCT*0{l?u|}ng+wc6^0p1I>KeXq(Drm zVq`#^K?}oEAtlMt@kv4$B(uqU-ovY{DxP>#P|F_Nn}gZgxjHZiCoT;o*`7U^d*Rt@ z-+Vs4#>2Txvftr(Al29-F`St#zW@lf1j(ZFCLlF$z+u=;oVk3C=mkWZ8SxH^;?$}Z z&X$s&lbp)r5XT}7DJoS?(ZHgEQ^j^7g{fc~A6IpO1m|c#IN)%(#lnqv$(ID8#2}|MX$?aMS(dbiRqC81BNA!3A1uQBrA#oChmlqUP{dN{ z=RkyU5Qt<)kb$P~f>dS0p)O0I37nT^4QA?0rFx9k4N{p@Ne=cFdpgyG+9rEar6vul zJln1;woBZ}6;v298P99qPWB!t=<0x3&N4GqRNqqIgU zXc)we{@?(cEGE3BNT&(2`0V!JRa0coLbzV7=hY%Y+-}S&z$=oyl{52ZYGgzD|LfS zGcVXQqrs+$7iFHcp&@#eq`amX3pUNdtSlP@?!ne=GOpWX!fz2`Q^k-Dw8;{`aS69H z5Eoh#&g!B;B(rU@T(`-TA53aF*a(pYxM9gXnYpvOK4>m8a;u*W(3Jku8eopeuoW6_%Ia;%riZa!79nr=XEKUZr63cBDUUi#hQWP{Bbcy>jTE$W&JWDC|ETtrv6^fKL!I?4} zG;?O9%t#<|cxqprzFJIQ7U(4D`BK?7&v=e=k9kiK;xcSBs{Z#r_2uX zIj;y*PwAd@i3XExaeHYnW(Z%N?O0R6I-?FNvK58Vj&Fi!bL@IBw3NcYNZDcs21Dzr zFm19bw~HI(jZFs!S{=$;oo({o%%CRg9I@V*!QaL}q-r8iuaCL7&Tt@&Q9=*EhC2O2B&knR0~6@ZIfy_%;y!Lk##n=%gIe?|F%d9Dc$8wGf#EMZmjH^c zCEE$?;hNaX7||-cObN`t*nO~b@n1LuyB6f-le(6FNXuE*9AVM$A|t4&yx`Ew8={Jp z?qQS&==Ia$qCB?)S=xS~KT#2`=XMM?t5kpTBVwFUnZk3nQ=;cgrP(=CnVvHxbu0S6 zX5H-Y zkH>8s<%q1iW85PVxAE}I)2ILnZj(YUS>iIG=0GMO*y3fvvRbnozD2hwJvti?-zDRX z1*v28m4GN)<}xt54igXTjHScouxz+J znqiko#fVM{ghcr!2e?4@$?aaIc-_m?K=*>=rv=l~CEGU}5sus1vwzz^Nbn1WCDUv~ zK9w58C;h(fKziL-l*R4Q)rE5rvUHr>MHQJBNeDA5m?S$voaePiCpSC$`o=iLKJOLJ z9A&1GJnai0Uqv0HUqv0Pac1)n??up|0ziRtnJQknMRoRbJEXtcGw9~-b)%To%P1Gq z$e`=`m%a7LbzO1OjE(C`c>TeD?^m#&-aG}q4Oii9AqTw|M++ol~1)8Z0lG|v{ zT<0^MX^d$wl8>>0#xBz1yyiaMYhW4Az$cjIEdkrvM7%@1D*n>ls+wuB_^b zPSU<|vdNh7Qu}04&XlJF!l02&&7$x{Mw<)?-o9pJi-EN_^4%{hfejnk+`#>0lY!3( zhRi8YchHsi9QdJ+`Hx=Df6Vlp#w^c~u-f2WE7xFpd#{Xx%gKotCzIVb|b21~E zoSCUKje2ipn)YUGh@LTO31HNQWPXrgDS6Dh3ptW?{6r_M{@7dDmQHM905x3;|5JBicd^d`5 zOcuco_-r&)APN)3*m{R(jVXp7BX=(%$^PfH?{{o%o^@9M37Hg1kUj>AAhgqO)0V5 zrx$rYK8+8)O5tm4qcqNsyhUJWf@mx_kSWY+(0d_kD#Dwanu_3Ct$^keS(FpYVxV3% zq1OCYTXeXk0edUU+S{kR!pU|IGyzUb8Mo<{DzYeTywWegp07^%J|_@vU?5i1ES3$k zU8iRvW&}FO6wahLINLPwPA3~mo4@x?2g34BXAk45^IB28*9mcalVc!a9@wZ4GsWAu zfkiMBI4hXUznbQoAREMI-G|_fLEY@kI8V=vqeGF){H(6D<1YBPPgb74j(LV$$R$8; z_koE4hNfdkcuR=IdQM)Fg6VOIu+$$dOMg%XGdCtlyH0wIqdX@EBAR^_2&e7UHVj?A z6AV~xu%Ui7Eg{=j`P1Wq;JW-LHPm2J|D?SdN)@V@lE!M9GOR00EKI>pvimgxFFf!L z$tXq4F%dM^K(W~@_wrJS%0xIeE53dWG@dfACkebk!uzA_$T;}+2yM2)^O2Ptrv9%| z|5Zxm_(D{QB^{dQ|LS%x2CEm>0@j=KtT*?CXMuJfuy&lTCZ0rbdw6Bmqp|z(7SCwN zRsRoZ-SmZ@*-h+C>oigNnq0l>*LH9bV$HeQ{xnyCcQM{39So_w-E#lq{qNostB3XF zL9@!j6N z_&@7S{#UJfhW#&AE1mS-tQG3^_Kt|h_PoKrY7J1YFBXm08=AdI%fDh5W$vV-Ja^K; zZOvx-z~OpDc9MiGtDG4O@U}r>_l-AO(bJqNPM-o(O-&uVw;{XnP1U(m*ucz_j-HEx zfk97TgC)72=3zc_odqlF|ITgbxs{d7tt{4Ept4fg%EHbNR#v4~Sp)X0EU)&^;h5U{ zlzPIB5WgnS6X0t!A4N@Yk9we3-+yLZ{9CL93O-@o;zg@gt@|fTV(HqoYmU`c5U`*Am8)qFFq3sFm#06Nc5P2>PDSp@l6bH|$hzh4t8MYIYx|dOTD_Ns zuz2;lmH$BNvKFjdv$B8XqE#zTT)JSzqP0slE?T=(t4p_K80qTKZOd9VZ8Bx;UxLF0 zN1@dMM=N4^ckA-jIfI)*wl3@kB)x&A(JYj=q+pNzA1&D0rR$dV?@=bv&H|lzv^J=5 z>4L?pTlQYGy(>W4DZY1h#@XQz?uoY1hVBnF0sihO9Zq*sC=VJqMC^Y!pP%j}Kcyl~ z6-(3jCmp4D+K)R+Z6nswO^cTv*T3@EHBi!;C99UMHSJ_yk3QWaiywto%&B?fVPW&W zhh@76c-Xxt5T4X`u#onAuxU8>8a(QB+NI+voL56NrB2BMDQBx);|!>QPbv?&&@4}# z2w7kI43_kdHH1&p(#HxR-Aj%#U`fGNf>!adKz>`PqUl^~+jV1|6KbYTo;h>Up!!KO zo!?qD&SjfxTAiO+O>IZiwRd)|=t|d5nlu#txxTgYu)~h%fuQq;Q@cYYx`mZFi0Do9 z6;gw9sQMGlgL)+^Hw}j%5K1f<0zfSyn)+jo&HY{D-f9%?I zfu=8Irsdzp8ah2}ORMH#AtCF|Pl^}k)qG~-{Ur5+Zn}7Es2a0q5!}!}um6>8bXvyN z&Y=F3T{pO^wz|2wXI?GT*4c~)wARf2(d}?MyQDSK#Zh`Nq+7If-Qe0zcDJ_M?RItc z^vvrLq{;1a@@t%pc5QWCb=}0;y2;YHjuS;a@+pe?r1JkG3iK7VWa+9!CulwW9S@i5 z+jThIy~#i>U;*L+XaSdop@{;!Y-Al=-iMKH=dR7&&W~Zfw{5QR|Gr=?YsNCiUruNW zY`a!>96UQcWF7hmn)6Cb?ZMitWyh}R z7iXjgdCPFGj?cHBA!uq_*KDu$P#ZuUfo>vFmuP*QJVY|AdS(cmGIL zYX9MxezSJi!L~qC{uecb7&Tsm)7b~N^z_VWuC1RxuQlG>>#VKm2^HzeL#ZsM$u1jQ z=ae-$t7`-697DZn*=0Q*kg3|5~2}fFH@FCg#n`KuF5^I~} z4Y$Jh-W-EgJ6R8}I%IHNXJ?OuZgTlI#6fhZM|v69xkPd)-+{4}GnW$mjW~oNWbyQv zz4}tGo{iynGoICp7Oz;jX6fE0Gyjg+&|d6i)yfH@$FypjS%BuTX#FbPRLsoC^ycWh z{N9}XnAe*J`f7^k?hmG~W%T3;efwVeJuCtRJ4c`^OE4WB$OZbGz|$=knopO09L^>5v-XJg9)I0=JgW zVm@j^gS18V<{{RBc4>8OeY_Sn#(@S*UEI#4?D?dg^{-8m>h=u z`MPKH?B_eMTi=q!qMnAy)+K6tyjj8BjOxcAb`5TJHgvw2_^EyYh6l(+avWB)(`k>g?px{Dd$G82>YW1n>|E;6Fs% z#~?GQ%S&rn0n)lIWY^So`sr^X?dFhOx3+FR>W!^&D*ifb-cGwvSid2+y~`{4qYUyu zh*et63b)-Rw|7NnD57f?_m4-N?=Tg^?QnZ~yOtk5*qaMa#!(eG7$zt%J4ZlN`|FV1 zw7#bW6P*rc`{s_8jXlnP0K8#y)BF}^Vuv%M$r(S_nbonry7ugIF}7%FubW)mnjTd< zYQ(sCEj=x3Iw#gT$HI|z_c|NqE_V{$AEPc??pcbY__AX+&BM5&XAo?)-l^$!j%w=a znRoc<)y-YoMm5jxy?sO1?HhUldYX`67_l|YtDc8pVb7peCtl<9*Ep$e=NN{)b4PEq z_740)F|8b&OCNQ1hB59gT;}xKo!gc>`CGmE`7xPygIQZ`+L$|QLs##lGsX^TpY9Kr zB++M(Xz$>z)2pMU*FN~r?YG~)-gCsl{wdg9BU=us`&G2__8iWyz!@^IcCu4Z?7O@q_b)kB=hZf9jvwD!eow{6=tZ+=Tp=cwBHmY#WDwMx9_N9?A$mb9~}CY?#A zM|SBzG!=~1R*5ZixC;&&RNvd#Bem~1Yn~u`9v=tuF^-Srd@Rn%*jFO<+|#Q&d)DWc zbnB#}yXN2FjJw#G-0#$HJ$+Pdb0>{&aNTH(^oJp`kn}Rn`mKb~(B;qiCg<>` z)(h)SsdtK@Q;bAAo1KD=PG@7sCFxi=oqzAObkf zdbTPX7c?-x`O?HVG7eEup?OaKGS451-XGEFriUNSP@k6W#`!CI=l70Ax~EU9J$**) zF~<&JkmXKc6VjYNn26+rP>98FqJu*TZJpC&Fu?zG?V7sYuQ&xY&CLz1iRNZ!O%0G1 z4Bt`jqh-|o0Q#elb=ZH?o_hH*Gt>D$-C5`K&U*}~(Mbn}y{60F$qE^V&Oto@)9jq@ zyK=D#eC<+~=S7qDGjEhh*%P}+%ez*grGydHi2)TWj*d$%>CaXZI1^{%gOu5D>qj%Qo5 z6L0!hEOlKiXX{wl0z=LL*ErMXI_))1NmI)uy$^cPTr1J=iD=d}Aq(Rho&MXL3Ei6z z4ENLFaS0=E`|)(Py65z?4DK2+t*gaZ-+|VRziO*9XRgy!^>WWxzttVOyPiYQ)AzxWqRwleSYjSI>m!y7Qg&l(b!dX0U%oG4%Qf z`bmu4ol#pSJM)_crqj*qn>$~s!~5l~mWNxqoaNVyX@0TJtIky=2=d2}ovsom;7Teo zY_qGyr@@cUoQLL)SKWB_4z3$n*F1Scb?u63=e|>F=FO;WcD@&Cs&?)%$WuUSSG3i3 z_Oz^D**V79)Q@-7&dPqLs_6?=X=lVTbc~~FTj*-n*3>$M_+fTq{uI?ro?j;x*HSmX zu4^AD@)5e^^;8usK&qT?078@TaGayacAUX;oghyOb{?U%=aK2~Fy>8@W z=U%)yujqE(I=RNV)TxobmpI+d|Hs|iK*v>G>4LYa^Q`hsw7#K z9ZBfVMzUnPR8^8CCPSw^jE8Yp46rgx zhR&pECd058n&HtrhD9@(EFQxmG)-rCVZLvld+t5ARKn&bz2;3xyY{~O?6c24`|R^` z&;6RZ>B%#^H;T(`a?Fj5|P!dEvE_~ZnO3j{U^;z>(@lS9CveBZfl zN8pO$mjge5s(*&+AKX$N_>Y0Rw^Ywu7g+LE;ELX@fpj^}W%0<&Dek*R}B*O%)yyUPVF+; z>9NTXWoc$?Th+Emze=z-@o#?P3`a%Z1_@Y_{z-mSXdSdP@D>!K2dzJ=PcTY#xsv>joWy*m z)O*_XTfc9m+FmRVV#AT8;MAm~q~xpAg0VzOyUwHOwt%m!bltv#7=<=yV;`ome-^;{ z(1*o*4OTrEUPN0c82AUPcYSe=M>s7hKlA5-YkOsLBhXbISkjA;rD8qKMn+^ANoRrq zz<)#Oy`P>sQaZ9x4Gnd{z_;ou0*C4XCFOyUx~iJ0Dm}?(SHrfuP&iIBj)jzI>jN_( z&KkaLfp6{USl?HCPk2K^Wc}ZWksaknaSo(R94l`T6KIqybu0Qx!KkOjnz1olQ?Wzu zEIxY;N_!clT^ZuO&U%a?p}@12I3v&*3hdnTloYbNZZ`b)ffd85m{d8M8MP^!*%WS$ zPynM~7&Cdv4jpgj)DHASb^RYD_#o)&*S7^ zV+jn~gfaX$$g*>9i?-olL&L2dn?||d-_aXr?46M-vRq~~bl%!=7-u&Xfz5Y6eQ!r) z;EMA4hBGiOH_`xKaM6D>bT4+A)pQ8EFr&YFVo%_QKAbt+c@ih36Sl>jC_||_Hayco z=0s=1S%U?SbX?a_R==(TGgTy_w?s~bVEem4--fjt>N`g2HwWf?^&|E8Z_s{!j}oUA z`}SP-?Fi0V&er#xttZ02LJe~90X_Po5=j2r#lFThjkRS}-!3T)mv)wxtto--j$Fst zzWSNI`ZFUA)zN`de_lmK*6apkePOY$eD8>@yIyPkfJy%zNs(_~SJ78L(g5>vEWLiF z-v2d~{pm8ud}zybcx3GPX>KDV?kvWJeM$XO;-8=_cBC5yWm+TGzeP8y^zDC*47lvQ zwr^Ai%PZ9L7sbAB9OT*FHTZEaxcXq=%D3uEF_Ev0G*lc6jF)$c!mvJXN^e4@cb753 z`qYey3kZq`1slRbbu=lf%7cwFJn`ai(OAzQ_LX#n`}z6Yund!QDBRi6*VlPN z$HBh6X!X){74;2>0qn|bye3>N~ zA?z39qDe_fM|}fUp%wKvFpds}E1;y~?>g#lz4g`^{M~x%J@q&A9d5Wm`Z`Z?p|Njd zWTc^D^kBojHQ_#g>TBCDZUz1p>!#V>z_LB-*REf`Ht=(7GE_tkuML!!V=WuW%&iS< zD?Z1&9JCqw7PzP$k< z-FF?mJQ`SA_taBQ1)e(jWZ-|YhC86PzN4n|DeMQXkC^`*O?$Ui9)x{QR&-QzRR@V{>PiBmp@V&m2m4y;{onpNRQ&Wrd4r$#{-B5AQLEy>UtQ_@ zT4zV6-m}Cr!8pyjk{5}tJBX0jyr%v--BGek`{ygsQIOD3cCfy4BZK6oP@nE$&r{;n z<-V^Stq-iM!kCJ;0hVzJA!mRJ;+prev4?UMRT&D$P ze5>$<&;dI7RDj|_sOm_#3c_oh7~ikcTW-%&@2@OhXyY|azeSgAI5>mP$lvs>ujtc@ zn7g+_=Kq3B6Hl?SzRLQMTW3Z_It-DbT8Q9HR2#3^6fWIY;zFn1c&zlr6Q1OPzu?$bAZ~=}7gXtM{ zFgBT)+={5gy@iumUfaW{00EV#3a`Y09iQW@`%f{{@>HO+ew|zb7!V(P|FV5hk(nCK zZXHfv+85T)*lcFF%D!@~aw%gnI8z+wt#v4Sd2DWE}$4&I2b#RKj5_V1J&fnXo> zh?+kI!IWh<5#aU2WjH=t&rSFxL2BE$r&l(i{A7Jia&O?gyq@dD5R1Ya()>kbb-lrk zKP~wV$Ql~j5PT5dyJ*yIs_ESGpbWK#{%~HNm>K^(UVf%QygV70s|#)ZEnN_J0w*IK z-;p!Z;GS%-f)yGJ-Ywtsr9W^i>-bUD%|WhFmjsJh-z)gF?0w3~753n#HPT7S!u5FW zM*AK_(bgcHD(aT^ss>mrtQsnBcoJWxZ-d_}+4?uKMtBaf_&okCYZCv) z5XGBI4pgk~VAus@d-Dng(v{^_py&}FzklMZ!}ovX+k@|)%J=vEA<&Qe$$!F6nZNd* zmN;E2?kJ->${Ao4)YZ(5-{#i$ zW^YACf6+9*viv&AukSMXBpuO0AKf51Q%p(oVqRMG{^vgG{Zm!Rvr^_gzFr#qkeKlk zG5D|iduZSVTv`Ye{fRW^pUU^$_(m+V-S)%M`gWwB^#@n{!I9LLQo(V% zg6rk%OjU3PYqFDHjWT|X?veg?^%|^UxD9ZXnk4pQIplZo>i~rhl?Qu({uQqR4T@jJ z$eyf|v%95#NN0?HInKb%30xU&D_L(e_dIW~Qdjqu2YL4cT@ic}#Qa)=i8bCKMoE`= z!*-H*enc`Z~810oc?!-LNxo z#d&OF1~!DgQx)h71xiDK!*zjgsQY3rNW<|b4==Cb%vSruwviJkCNaNw#>*fdLL#A@ z^chJr;BjOCx;=C1!$06!&!YGzByH8H;P)0ec?;R`OUS)} zdaMAZ{XFJ}$7a0>@$>aD|0;y`d(darU-S7KmdVf0&*NU?$2y{zbt#lShjc!fgPtqt zJU)eE#E^4*8pre#^E3TNdFc=29Y2_Ne9kyF+nqW;f<8Vr^ATvY%c-L81*GkD8lQwo zBdytJvqJS~gu#4%McZwb!@3_q0-p*QmvUC!8a%V;`$e|}exPH3>3k04VP(gHZA{;v zhb*6zXa(J3$0}_ipN~SYt@SY%cc{BA<78>$>PN(R^Z~KGwd_$1F?R%v-y|#xd{YHjj~HZ2?Fe+jU%r$QOzmvz#|X##2tCnSNq^y2s9C^Xt)O=6~)I`S;|fw|f2blll6i zrv5YY(>>*n7f9Fb%R6olN%?O3GRDn*%J@3B7<~q^bt0?ci*n@iQwI2~$Fza@-+*5B z6^#D~`7^=0utwCnc>5>I*T=l`(>&%)pFE~NsEfCH))i5gr#;1AOy@0&zm~E*=@OSr z=lzLy=jU%;enji%EpHd{^EWRKYaj83H;$R+SZn%{^?0Y)vUnqu_8E_P{}X+n(|OaA zt|!xZx09|Xk2`T(Ddo%`Bbd(nov7cmgM5D2&*^)8d^KouO{8rATgEV!t7U1U)=8g` z&)bz=K#Vn;K5tPzV>)jcisr}Q?&Z?Qn9iGgUK71Wo9tTNrprCI#ws2~x*nT!xx58u z4r4)HTTARy?me|3G3e zWXtgu7p#%!qo(C$u0+%FT8TTUBW_qZ1$mK?AxXutwv{)u{PI)Mc{9t?1=4jp@m7{2 zl5Wo*&C5gDKVVCn=C=!PTe%-;*PHFKYx!oalXs|Wk#=+YehBic4{t8XA`m>jZCQRw z&ykej-2s~+ukGNS0d+Vw=UVX%_`TrkxZ*tkZN@P#_tPeA7q9hyjN|;6%}r$;hYa&T(urZEa-M#g7=hsXQL9?K*L=la3k-QKwi zipFnJ#tqJ9Mf23~F!n)cA!~;^Y8zqlcxqA~4Nt04h9{wO7!|vT)oLCa5hF+XCnoyg z$dO4<@MWrhh~F7LO?#8rjjyAFqXRH=HVd`TF@{~Xw(wWrOqf^s2Ww6belGj6xq%+Ck>D0~Bso|~Rs&GXt zHJ*}CL31)lX>c;5n%-uqP?svR)r~gBMk!x>1Ain3p=NR>Z6#5qbZT&Hcq}!f!+C6S zcnUfD=Z+2`7BZ<6Gk9MsLk&|i>a{UjC&D<+j?PRBgtm@^w(ie_wqkF!eq?e6MQt6PNM$nEBi@Rdk7P&d zA&maY?z@%Eh9lms#23J9MW-Z2{^6niY`=L7r>A%`33r{X{sF`mQ=ux;rt7Sjmx87A2$@FgO^W8t5NSj!mRz@FE^W zFq>f}gBIW*g@K5EXCxh!NK)N>assb(nnDAP*Hrhb4uV=GSr^2&#F|o~vW{hjXqb#p zZkHMypW-+(je!ug!9OF!9JtckGQ4JGzlgzop;?7~$C&CvD#8oALkWJNC#~V>DU1^s z1SZEYd`>C_0{yE6cU5h6K|k-=y>n@r-!&?YK89Ed_BJ)NSIp%H;OGielq zF;->HjLlb~U-Xp3Ffq<9YM6(%MiZ+t4gI#oG@j46EZ`f-EN?VZ_P9oR>!pTRsW&uA zt-Vz$V1>fE>4^%n`E@&C^S-G)))KSYTjDY3-M2q##oH9!8gI5*qTTJSR%};%SFC4OYuKS8 zR=lM-nZTt3YhO=$OHx@7ET;V)P- zo$XGyaEMM#TS&`bRWX>dn%bIU@dN}?S?H5iv)bajAfKJdSi3u$;%(x$*3>X%ckPQ= z2V&8f)f8>6tj_+iNaxniGI$p(xa~faBWDi0ZX!V=e2CZ02i(_9}dtxM+9-iz`FK^0kUs2@7qpJxuG}{v6 z20Gf{O%@*OvZppu**O_$Ng{YK%pS|8)BuTBJvuLDYOi#y5>XjT67752_g#}uRa&iko1DrdsVrQXJUTswSz-u_fFUuZeyKMr36X(s;DpX0{|^owj-ok*tiJqC!s; z!!40y%V_`PWNO?_)#kOxZO7Ju1FhGqQevv>N38C6Q!JrNY3gimw(R~fPi1AYO66t9 zp%v9_iw-hxiCt2faePTGaGx9mbI!zVQ=mpfXB z5~ftE6kQonEGf;iPKpOvjn>K5wlS35(kt<2GF7*ZWpWmI~~sI{~1uyIwTM@6MJ&(;{$B}Ft* zsR@jld>vOZQmqNCyGqMchHd5IkEnW>k8m z%%dG1NsqdSHc^{pS7y7{FX#l~TB(RxY_+!u;7+p%yhT-c%&5`6Mf{i=BY7p;u91?D zjtyl;b?C@KU74+o80=3cJ#LOvnf6pxhWV85Z)Hr;W0&}|3|hPK(zb1L+nqOASaJp(ai_JQp)jHgv>HeeBSmF##WA4Yg7-!ZQ8||8&hMHt@1}EjU7+AF;Y)Xvd@$7!y zb&sdTQC38uN=GD<9)m|^KVX`>AIBgtjb*SbxAj_cn=`i7IMjBBszgCh*(tGmTg^6WXf7P#SEbWT z&g;%}g~dm7kI5KiSR-Sk5;q)izSA1BQ&NOQAMlKlSc15-rNeEF8CmBKjb+k!-y%)) zC?6b~hV`SV@ibPRss+%^T?4qdR}PMLM~yb7rD9hSOAYuPW4_t?Gy~H@tha?H1l+Zn z9D*imj?p)gvi9z8#Vj~HL%$|b`2dv-H+K>bvan!siK{dS^o@|Us{Al zj!un_V;@bb=}DLs^R+0;l)%&s2`YUcsZQ)_F4a5X2`6zAgiCCl4hy-a!~TXuSlh1l z>)R4esxEPMgna>T`G)%u{}OBMm2s}qt^J9?}=0w`%j96OYGSm|icP8fBZ!1GmXbQ$98Qs!Z$HGmOmCe6(fx&kNIS-j~QuZEse z=ooe`(y9KeHH-?6${4J6l$>Iv))-+2Q3LB(k|@bVx0^xl9a_U9YLLVJXBH3B$$&SB zy(}z)tihS-%+z%9nB51gIi(5F&iyCp7qH1Djya{nUTTw#-=ow0X=@fIUNimUbDB8D z>C2wGw6AHhn2XJD>`G#n%1q(ZBqnJl${^1g)2eOaSl-~H-r(dEmzG^d@Uj~(w}R6}|2BDWy(%3#yZiKE!c7$WfPair3Q z?XmuwvCEEKzDbL-zO8dkbaJ)o@fQ6k-r}~-95$UN$J^OTZXH`Fqe8nIg2G1ec&&OCMxaTNw_iOxGViwy=`jiQiTl}ZltzGUp$ zO>@g#Dz8?Uh-#jMTa&4&?Gs4`?dTB3G&`#HiwE|jCopzodCd|gB(T`5{iv-p0GnRU z26fY8=aog`s@Uwe^9qj;%Ap<|$0c{S4?)g~lv8g4wQ5 zU^d}simaK`IE_XJv69tn4G9_6fZIrFFJWd{O@6Gx&=~5HtaT*W2_yooslho6(^$sF z_O|E-zA1$_i(v2l`p!<*dd{&CxdMd~i-|GzhALGoRWQ(%4yU?$Z$wvaCc}{n0l-jd zmrl$pkP;K@gQ{Q053pfncIWC=B-oV90S1NPq7(-bx^x=-MH0p=Y+d&A3zrCWNw`=vhRrN} zI5(BXg+r`6p?%t#l~BWlFwRW43?{yFWXDn|3}5}2GPTEK!P?9-kM=~evwh#LBt{In zjA3D)4%x4%N>3fdAi+5TSHRQ=geZ_uRcl+h83MD$r{ z8jmZD+0l%JJw&W%WCmoHlenNm5lgxkbCAvSTk$?F(wtsQ2jaGPZr?H#`4n*klM1)| zc!>p_Z6>{!LrUft3bLkK$7Xqo702uo!xa`Rd#2TpBk2h5S(PW+$xXOPT%eiD_AAxM z7K36Z8!mgOLU_uiW(n;>_YDqA;}F3V^B+Ci`;a#u1#w;xQ246c1IFS4GMrR-!3({jNk3R{=1a@rObBBin6aJLYv`y!*#l1-TONB?LV+DPizM-B;grNESve5reWQ-1fG1>%?l;7H8)914h{}yFr#28 zl;VYYT-D|{g3*Il4hP4NC-E8qDYU1>ZF#$Pv;}uh5cR|bUB63&@OULQfU>yrU<9^H zv0T*Mgr85TN{$cV1Qgp6>G9ND2=`3j1Yw>_`Xk#+=5YV^${HA0KyJG#HzBCg)5a>8 zrmKg|d~60R0o|zDzH6_UuKPr##dj#+GCgJrSGcC*pmw6s5uh_UdXystsp0etRtgzx z{5YM7JF{?7Tf12jWGnNI=LKFQ>t(IhCB9 z!tjclPLjCJMT3o|bK4uQi1#?3c6hrTIFWF^%=T^J@bEllBs?gZxgJpqYWl|Mtl}x> zh7)~%nJ3maC&?uli|Gq_UaNBXe?zFQ`uk~h$L^$MnTp&$VS(D;WK0eNHbwjyo!YmTu z63**($h<@4bvs2hHdE|SADljh8ziJTFd1gB@WNtQmV+sy4KWs(#iY_Zs<5#{9mCiz zz}+2=KHWqP1EDfoo5cRBU7$LyloH3WrDZQ&lT!mXV*f7LpT$@Iy z&Tnup18<+l7CI-wp*CaMyUWRlEh4ty)F5_~&~`FrBTq6t=*f_9BC@*h=w=Ty+eJ?L z+)*syEWWe_w+v*k|87)pd&<)+D({46WUzS!ruPZYpkm8aJN99t8CUGRL9;zOgjKk~ zvvYaI8pZ3!3~dO)72EUjPNX53UjpVh?4{CivXYpb%1$^(+wz4Y;YtiGZoJ`T9^N8% z)YN+CRhm(aVZq3=*YW85Wedb*ZDUWbo$);VG{B?mVBR3rvpZ^LF$W>8rr6b;;&(@9 zw@F<&PcS~soH9UTqGRhzRE!U026>8YRCuBvSLe`i(>GST@sdodQ$bVEZlNkwoTyW* zWd9Dw9Br#nfSqr9rA?rTbu`L?&0H#NZ!(-5w(G^cQ!HlC$h?AsKDM{rX9 zS5?)9p6xtKOHUzia3_W=Ky>-}6OlI66NFp=PLB=FZtpj}!I;2oYQ&sp?sG$>wkbaw zyF(_AiI}KNeVKRa*>~olbq7c5VdZR1X6uC9sfU~Oc)wny3&Z-!?yYK$!JT-MQ@EQC z8-rUhIA!Io4#gas$3Xud<8rFtZ9!KpM( z$Z`q0|2Q>I;*QHC?jFVuK&EgTrda_v7i%#N|GY0-Mt0nmgDrIo|7=aRdvXvzdNi*> z6A?YpbEof^NMlEN8heRJ)I&l6_vPV)pKmO);=5(ub?uqPZhO_N{W}3UVz@u8LyGxz$O55UeQMGwGjTXiZ3~%Q)>kKKJwP9C`>mzLH7%m#_--g(x z8i_A80;sbwTe{HP2zlHa!CdJvZn)VSKZaf%`rgPi1ZY!D-U+>0>`YG0;stkJQOrGK zGC;Jr=h3xE&p=?c{FB7+LEE^9eXNMaFw;AveGl;!MN?XOsvCea0>S-<7VwV &1_)t_vPyXv$ee^xp!AnBDoJ6(NpQ78JsMOM%j67btBa zgB@Wpxqbh>WE|_Ie*PRbHidD1q7tMoZY49LW5d|eN1nWdL=u}uVDIhjR27XRaSKo? zc`!MQ=S&JG!1KwOQGShE-E9ZdaGacjytV`9)i~f4=j2=^zpC&x%Ph0w++WSen;ji< z;=A^?vkenT+?TIybeVh##jYTpLMbGH3pFzX5q{zJjF|zHHeXB1nw-LR6p|Mx-Hef@ z*4AYEzQnHBJ_L`t$N`NWF7DRlCC-@v&O{i&hKA53hKA6YhK8#6rTFeU)0|3FjvW^R z6Z=^Px;VCBal47^hVhcOyqb(}?ZN5u#279)i}dao?=gh@46c;f{+Jo7RKe>cjvv4D z*0T8qF*>R}9&f*XU(-Ih^nknL`F1T!zhf)O-#|{b?2X#ZEU%`*l|l7_DrQF-``7W* z^c1e+=5zSWfV{!U((iFfws3QXi*)s<1@0=6*&dfIGsh+drp7IKg^fJqfd?|e>V5)@ zg1DIEr-%@zEb^TsA}oZ{+hOxco7W3jua12@6Ha10B3uf%k@R zWq~qvd61Rl1j@iwK-@}$eIw*icG#KvFGh4sm>ZydDSCM$>IK+aNiQIFj3=VY6Kg8xSGj(F<>0sz{i%<%ayR( znVQDMuOzMkK=@NGJ7D8ra%$mg59XVRjMrINyn5vpk1KT8C{<48wRJiTPi75^&Dhey z4Hj^8YA(%yH`utChPymyq3uI648Fw2rxrLV(~nUVI9cOq8c)XTOZ|43n$2bI6q@t` z9;;9{3*hW-W&m4>6GOOxV+hx%j$sE10SF}SQLRRgAS9JT6VjBbA??fAXklW2mEDO`bQ}ArD?|^TJ4EcGy)a0~ZBhtm9r|_$!Hqzv5!`2k zpk%wCdm_eEZ0oLzE`ecS5-Usy;BgUNKvtd2Y+pVos69`y0 zyIPHmT7hAox26RI0#@4882La7_hQFr_Mgh5pi=lrY%&bOFD1? z4SdbiI)L8_=ZHgqMOMbDTb(0$Ex>2RYk(RR*$mXGNNpZBsc^r(>0JxQi))>8jUj8>?Yn13s zArnM2(pxXe-Xj8CL|VYDm#ZvBWzUFgH<6Z&Ie~mX?D%uQa#SJsPaBv1I`B^$ulXm- zNq-D!KLZ4;C7;Y=`mHL5$JcA&{dn{?5#NeMvt6qwuv`RUMAs@Z3{D`TT4Ir#4U~QMcM~IX+(VWk=Fq+a1H|&Aq1=3d|IJlr9t|wvyBBLz;1Qf zg~m`f)u|h&lEAw@D|DaVok}jBxs2|em)~c_+@hS;gnfKpi+qf6xiIMpI;!Y7w?hQ1 zvrnJYQl10NGy;iP<4z2GdWkSoYq0$2ZTe&K4PKE;XAJtRL3?yKd^g|O&O)@obEX^E z;Lt|8Gshv_p>?{?I`HYFPDSR%OVK*rXLWx%>83gcdn4b_U>0n!jrM~?tE;h4ecaSP zbZ9&AY(zQib3)q_i=G45#sy-!a9|o-SA%1PH?#|u2kUgk|6fG3880TSE9r@$LUHN} z78)gemcw-gohbHnCxcsvL~C4h#wcR|&+iFNKzlN{g*zc_)XZ;vR|}v~FHIX+3kKAJ zA!$_1vD0vZ$K-|h3km5O7+u{P&t}a$H87gh8Sy*<2G<~+Y`Wyj=^I9^OmTy4w5_4o z8R{{O81$v52BRV<(8=myyDe^%SnSdngFb7}p2^7J>wHE<4ARqlIC#PdYR`dTpV6QO zw_quSg39QE#whD%H(J!`8#wPfS$K*sETXl+!32*g6@a z#*F5S<|f+^HTs|_>aYz_!!@R;!!|^RH0`z3Ve4cx@&ZdObKUNdGFmM!L>!|$d|edk z-&mM-PY_HQBT#fUBW}IptSjII1O?nPA6H<3!O#_OYT+HOv;a)hvUxdHU|B< zy8ajU8yw(tDr$4r?b?f89nFh?jLAt5V*zm<0^UG;K zCmytoekI`CWA%d$Ute9fi~M@BP^@e;}N<_V8WoaNKyxMbe+ zXt?BZs-DpnUPjeF+xm*H{r(F8s!qf=eA6IzBi|M1G6mcqa0OzffIG}l-~lNjPNa)) zHzBkDd~Q+V9Dv&m#FQpK|6??j*Iq4XG}a|shyt#?u7>~5O>OQdfC0GeK7XXl81D

FS1K=VezSiFxaQA`pLjVgS zegJ?G^Fg2sihK-+`HXRtsXrE0_ai_T6{+pw?+%O$D@sHYyk+tS4MG4IMa17Pm@lwF z1iFZ{fZJ=SK?%f60k;>p0&!Eo?X}w2f05X6rYdhWT^qVINddQ-nrj%TSwXxKIP7b5 z=3V~a#5(|p60!c?!pJQWpE}lPR=zI&n8njd7ZFu^b&>m$643T&R=%zyxSnv8h&oeF z6s!c`D^}or*{^OaYuq%AD>h{I7D^zKiZK5Y-Bn12%uW=v%G4To(<#8+6rY4-8nDg^ zyyGOJ{Hu87sd3ZQE4Oa;Syz88N155nkfY40%aGHq8iy=(qyC=qodV}2u!OlnImkQ# zK&unkj`3B zP~r+iDW?V8l@g0tkL3zNiKr3awc8cwG6h__Dc~0kF(R$OwVMJT0oeA1 z3ILxGaV6;WnJds`3b;O_z#h>MBhngNpHX192*ioBfa|j!aF2^X_bs-7;WMTlk<`Qx z(6l0FfmEJ^o5%4P^Qc;h(G*l((z0Hkx#HpkEgsF8;;zqhKZVaU>Gj!XPtbZ6Tr_|7 z1Xtw(J4nX9nBi`N%SyS;_$4N|rhSPEd}DF95b4a{1$QYf?WW6ih!cp$zJOb4XQ}kr z8`Ut}(`H7^9MUb&2~#654KhD?ot+B9kDi^b%i!z6gE);$Ti)kch!Q}7QESVZ@e=) zUVhT$s7e=B#q;|0xZ4A9K*YO4ym8haHHcfahG>r2%0;#ZKao?sQ<2(2{>at^09u3S z34rvtCqevDACPzsfZ~YwgIk_%c@d1imh>po|7S(&BF6DMVD|w~1QCDs%iG{T0{6cV zfv#Txt@|2fdx)+TGC_0^5VU3yqNTaHl~(aX09-wJ zAb8|t5W6Qlcv+uH zYAy*R&H$K$m@bh7?Xt(y7~+4(P; z`7b*8Uxmb5N|GQD(T8!F~tvVQHdnw!*{W%x5`x&Z(~o;XRO8NhuO;)6PY#GIW#{HjhM@iqX>PGrZ* z6Hcs96XV2o%o9%akb$+def)&uqX(enm!j|hb!Vlf2iP2E0LFN5j>U;!7m?#k63m4P zT{y}3JtHdOM7DVsPST|Fice%)cfqkvnuYeUP|-xPFQCrxLWyt^`YB z+ZvXir{!StiiD0c^Xde%ykMsjUnSX{1&8iUbS=A+CCNQSKuXfNpX6Pnegr`C6a7Cz zI!lwE!;CUv#c2g=YfQJ#BXvSj54ow%9=mS#s}M!J1@WqzEoVo9aX`H*bs7RI=%i|8 zg>vdnMeQv6D(e=d{iv(m%|AcQ%)d-*?_o69t?qU$jCn@vxxMTol*R>9o&Mj<#_U z`BYC!u*cj1K)ljN%@P%fRv`8O%u7Vi3VDF24e<|u?g3&~FqU!mK#Owy(UUpq3QMl; zoj|)4`8G+(l{g4=T#>f`J*voyK+h_Y=vM%l4_VY3asb^V)Hrg~y+ipTR6j1I#EEDs zCV@8M=K(>kNh51=q^S&PPH;cz@>;cr-ULt0FyS0=waU{;Tnj+YA!-&fM#QNHT01%I z*d;jEB!34DOvh?PCmU=1Vx*KxYLv)UG^8b=bV!>;(RF}DR%GU6S&k&L;4ovA=)5?>2|0YnFcj1r9k z*lHwxJ^4s=G5 z+SRPijZ&R1B3+%XoLQZ&9INv@;0o)gdnYv+FXS`pU|S;qZAYXk+eOq1z*T-g|{JOF*{WuSM2Ofc6f0HUZAs9BNt-N)i#MG}nyFtU9&N8+^N6P;1~ z6FCxhC_WL*fV_K3Njv;tGAfB_Ga}J2*%{07O@2=7?EV#y%GJ$W4WgjC5$LcYhk%YN z@)Xc*io6|&)))gA4^JT+VT*Gal)MK;EdB`4MIpQ226_j;wG8q5itR_{%>d}U7AU4j zq67f_^t(9{vx-kNr}!swBu*$k5zTnGar0${OKd$#pH|C$^RUJ=F)#h^{h=1AzK zW>);HCf#}th;ktFtAHQ8BzqIk9z{lhCKZ_lIj9xzBM^^-?sq{g9q;lV~3L9xJ8YQgf`((Sfunu9KC49PL2{( z%XO+A9mv=Du0mQEfTdFa5$_?YwXKNdNKv=ZnW*|lA{!^VAmjleDx~poLv>tRXY?_$UI8q@R6A>xa+i&V z9|Eqx8Y~zB^C(WC$)Gt)l^jym2a?=PYnF;Dx{3Zs$QT{8M{$X6P~1a6hXEW#h?NVSy)tTjU9={M{%;{; z?*na-{0SmzMjs~Hskn7OM-({#q?9_RuUx6GQTtXzA%Kb`QspXvi2G&U5X0}P6z>7h zTH+x9wh@TZfJIi|CCdtF=TW*BKxyJ(fN_4?jKd!ZEAapjf0El+mbO+SGazUM{th~G z2SI0zV_iseE2bpC66@Z;+4Cpv_1#;mdC6wMTN*`5v?mzJn2uo$X-_&#eiA(5t*fj3p z6S{q1!o#MXhv(_R9Y(o(eHwIizha$z3q9-XulaQjU$5HT4+-pY(pjZvvQN^#^K$4u zIWGqzjP9A2L&xvD9G9s3YbV}@5x)U2(unP7e(i)V3x0TQUe)tD#WSMD&iag*^%*BC z`{08B=sS0UHC(4!?%W9yAvwT3!z5TVF5R6wai0%+__}VAQP=0CYtat?X1M#|nIORA zJy&KG|E~ZHAH^|@7OQyBvr#b;Wbj}PPz;H)z2xXJf)M?o%DaN1D|qlU0HQ0-9wA4I z-o61n9Dri3PTcFicNq^p06_HWv%}#$ zpc9Hb4fK6Q65S`{0iu7SxIY3q2aw0KL%wy+fUp|O7e%I<=w%_hUIBVlkwotb*+cYO zA)_AveW=La0sTis5-md&Q4ylA3K_i$Xca)pZuGlle;C4+FaR#{_rM`n@u0edix**Z zgSUdmuL7=gc=YCSvIv;jm=~gFslwsg;wJkeTl{Pcg0{GBg5tG^F#uLKM5kZ~mWIyd zSSGKM^hux14us&{2loeQQi<=}#;OqpFUl_|#o zUqx8v8BF%M1vBbE)J~x1=z!M&SShl$703*7C(!kZ+y~UH$U{JbiW~>JOOba2u}ovF znP0$1Qb2+Q)QV(+1*l9;NEgm@fSKwf(}4yjlM@`-)i}!r6j@7OSezsE5CGk(mAFXC z?Fj-=JK5R?6uk>@HO}eL?oj~Nk!RcP^?ldk>Xm6P16CJK_c1`2{u;uf`pc_=92%6TVj;)eCv}wY zEkiC0ZkvEq6`T?6!YYibfO_71fRmYrPa^Iv;0uGpc``1N@q}Vvcq_v2#=vB(`w{y^ zh<%*SdRi5m8OUM<~P3pEUUVJ*}!`GvJmLmIGs zo?n8W+Rjd8m^lmB{TUU^U_)rl&UOE^u|`F`b`Eu&2Go2;eL6q$o&kK;3gL`fwJ|f_ z1*rXu2Dp*W+;;=MGf#t`k#u?8hYHRCzF;q;iiZl@Qn)i0>dI8`=ohzzD*hY5=jwxW zuZ%0y@bnkag3!IUh#Fq_!dj@|wJ)rN8eRv?57~JGZZLnWmC7*ln}GR!@X`wA_rrUO zsOvpI_51+N51M%f-77iYNAAy49oYzD=8pmMd*G$3qxvv&{~l1F2j*8mx@5r#j0%=x z!u*0gkSbOHF2@!wzGXVipG>LX+AnSkRdC(&1*@c&7Y}2K=W2oLF5;g7uomLXUjpZW zyq1liNDgTCD3asJUn-JLwqOxtS;ucEavjh{MQ#CVR%9y>tv8li`4)U2795}jo27sQ zv_NHYmiUuk%}Qz)(d_{2$(%n);!lJhCE_rS8!*qG4A!j6@qjhJqKw`3Eg`#zJ_I29 z(z{Cz!obNR((m$nGH^W;eEcD0om^%-c$)hZ#xO3-cboe?>Y&jK2Qlnx;}0=u|EI32*ilA*|8iciW`@5T-mrO z8#iQ~fr52-3xL-c`*Sq!Lw%roj!{daUPes}+jSm|jrR36kCE^ScH2J!u%q}lVVVM9 zoM;8wr^qN!T9I0D;Y>Zu6cfpwgpxbP=5p(wR`1+9RwO(P03c7R!-(2LP)M{T`T# zNo!M>F#*6ZPo&Fr?{{NCAB(^No!_{U|IV-xN_W=DF zV43xg)|L;p6rK9vs*Y=%p;fE>itNjXVs(zHmCsAiMVy1qhg1&}9m^gBArI5DhV+bAX^Vedg4ubdI#v=w2ORh93dY#6()ajpPTx{k;hE z5K(|{kdJNn7;V1YU3WZ>+bCX?TPdPM)a$jK0{>0~x`?!ZYr88DGX-2*U4b|Sg32l) zt;{w1BMA6KAWC$HkWS2yRisjJx@V_4VMx|jB{fb&<>(E%ksORx(zLgxnrkdODd5)B z6>#SHQP?{JfKnn>)vMGM=rRRdrLI8C6mZ?Q89J*~5k##{5v1Bw0udE?%MOFn3}7eH zwi90gfWbsp3z;C|^;^6RJMfRz#vJLeO2W7EQLHG@jQ}l8`ZxeOiQY1jNPnP`h*n_< zu5*#bFCZ`%QJLROf~50NWp)uY0(@34kyE^HW6mwU%Tqj(+~T`D#UqKue@lw*BB~Rz zm&maMQYcD3y2?K52A1(00OZR+ECQrf53MZ{7djNI~}$L|DS zx}nCqMDV}`AeH@qn?26#_^k=bqHS$W&g{sxq`6%CN6MDGRkq~gjX5%U02sBkyFBUI zQ647i^r6Z`^f92wn*GF=TYTX(1e?fw6Gz_2w8|ek7X>c>nCWrgXGBuE5Hs?p3y9etDB^YqXYb$;l+koPK#5y>bJ~7= z%)(TA_Y$dc<9;Yy0nk#~czvwx(#N#zX8@mdkVu&+U6tmct7&O9D|nJ4M4vk zdPK-5(W3x%AuC7fNtM9hd0ml5PzEi;Qs^buQAZCz6PU*fjRq1Cq|C1{B6# zqJu&nAaaVw1nm~z#o`}SQbdj=ka8{QdIL%CD=8w!C`ge$D@Jt@sqi~M6iRHRP&)Cw;*eSWbfGr zq%`$FR6eWm&1Uh=!C+7Vy@OWLL{B;y%3IyqJD&76kp3nB`H5&Ao?8Fj3Gou!%p$Z!b;eWslxO>B<;#jobV`)=5wRaY z8IkHjeMG7y<3#5~ppQuPml)C8ic9o?kTD{<+Gq60d$9F*Zv`tu5~+iq_~eKnxP4gq=)D8v4;7b4d8YRbkiSt} zqEn*3msM25NSufbf#m|xeF=Fj=W*0eTHVnw7)x z_cO-ZO&XAqiwO)&M4bRLpUf$B0+~OvglT2pJ=KU&sSQ3=6GB8;%UxZj=jSu3f)V=(7o8RznoH_337Fv;trV(QW{LvWvQkPp--Fcn`qQ&jU8yQcP}I zh{wGE8cI9_@T^iEvK@qQ+6~+H0NA~NqCzHOKy(QNh)x0QwFB#_)-OY=!Yrt`8mEhvLRd*L#>M#?w)1GlVGrq2~&5rfR*{K zGe=hDP za->&_NOT?0J|V>|Y-)H&XIzPtT1oBEtW`KNS$VF^!F`f;f_+)oi}}RnZFMhsTL-53u@b14U~k-VDGZ zhR6{y))5@j?*=U5Dcb5B$@>6wBo}ROg662sp2VO$4zNW@a?;bH?}C00fWoR_stU!f zNsw6pxVHeEQRF>9_X!#M9ni;$T!kux0CoW+OQlxImNwA%jX|i2;n)7GQ2@ST-c>=bw7LofKca)T&61 z{C6voo}+W1m)=+-Ms(2ytP;4i|F|N>5PWR{90Fj7p)JoVlJWYnA{noT#H=XII-^K8 zK%=yf@dpjGkO2ph*3mSO37{cGo&kDak@P>E2!U}RdJQD4qsKs^c=@n{T?_D8hlnbL z>>=V>592kF>VaKEsy2PBjbF^_BU-8~BwC}mM5<59#uwd>B@j_e2@o9=vWsY3afz}* z#^{gR6_-f$-KgstX*}hcKG!vUWpF^XIH8Y-oex1sM5m$VM9OzvL>ymHO`@!jaU#{j zqV(uP!tEovC}bCr>LPta9|`vmk?Ji`x3~1Mx2zPGA0pxi4I7A5A38*|S-5>f%}&ic7@iM~Or#IQ!fvaQ4{r@WJKv@9cVz z)^?I^g9h3{8m%uMMueIodfx=ez~+oX{5t?98lpOB#a<4`Y*d`a5UB=@8C}qwBzoNj zjWOiesK{0gq#Cr#ZO~W@+=LP!IxM6)Z)U+!4H_e2qe2VP!9Swb-h|Pf-6ZI-CovylGuj}+)ctk#Q-ZTK`)@Ok30ML2F%BS6Lfz&=_ zXHt&r)-xOCRrVF-({B2cy+fu_PH*%qbQ8TRWR!?23=t_tos?g@H-p>>VDWU}5CAbl zMBj$z@vP7R7t9XKL#KlpSd)o7P;!9|}cM@ESl@gh%xj-xy=BMimrKoc2896c(g z0V~f&i5T-_6Eo69o&?>_1lRphw!-Z;8%~uE{eKvM;o%6-2_X|~iid@a6R{NH`?P4#`(9RFx?a9)|!3M$ zh1=H*)GB10BW^;-1p6r?47M<~P6Otz4mUT;~NX3cpd)zdYi17$37*lFUjk&$sxft*> zga&6x1T?1vd^6F^#r4{1Gl zlhzSKS~ovw-TtIG!mv$A!#L-&3>4ans1cBVHn|34F^Zh;K@;I5y=en+B54a(u4@ATo$}#umiWdAuA+npWfZhdibQYSkDc zI--(9lr)0{T385!MQZ^mpR4e_3V^|dNEMXD6`e9Eh?V6VoYQ#wo~}4VcY@ufauFR7 zGEOuAu=jg(y&w;!d?xYDY8#!Fp7@MTX6efNq?$!vqCja3999UW5z%SbA1W4)4Jp2M zi(wEeM5pCPf}x4U>fj|^2Y?15jt4pkr1QBN6rzyG5ixc-R)Eg}cvcIu zmJeftvY!5+#XU?VuR0aG0#+-VfEcJCnT581#J7AHYc!F+VD4;it0bJ4gHT#}s6}P% z(W%6h0QiB3zR-Rkty(EcwA)A`eFT79L~IqEi}Wx6NkrpD66sr1647ZRiS%76iRb|% z38eEen!^#vYmOQSV-_N!r?8pm%hiE6sQ5%j0QO)-Ykvqp4x;-3h&A`l{pDcLFP`?H zI(o#z)GqNbwKF_S?FJ81JHW$48S+_%Z&n6P&azo`qxG+LQoERXNK(6q4g=&F1KM$1 z@mY{k;GE`MGJI6oJ=CtU_JER4E52FtfVJfJ&YV#S2Ax)n9kcMaxM#+o>jkiL64M24 zDor}$;ov|%*W#O+bUxODG%8O?!-R^@kmIt@Wc^dLaTCrIZ*&)L1(5y=ZDmX6>c zV*itHBEhi{d?JRF@JY-nKGB@;5lpv$IHCBr1F-nyyOD<7J83IH>S z=qhPZivAD)KECC1$!1igbi1WE14siDGy?oqrKc6k!7Ii*qFS*HN30_~P0UtsQ&~%v z;Bs&vAGRVjv9*|wQq*xLFrAU#a?RkOUPSaE=Zvl#spBev=oCODkU9fE4kFf0C4g`~ zrJyjK60s?lV4%d0SYDr5~QxH;>kLk)A z^EMJK7L9H|#DXzy5UJv3P+Tcqs-uhJ4mCK2ujSUqQz{=3y$fylc0NXHu@L2Zx4161 zxSQt{Cmbp6Q(KVDwi&>|5x-Y~D>@sBa%3>F3}$hTjIfuvOl}iYP3&Y}VKlL3=G-Rk z?u3pQfP)l$RAe-%@{#Lqrx$56@h%nDJRG=Y;lMQq2d)`twN{kJauLXG@ycgr@ycgz z@lO9oR=a(=ZU=cEKs5%b9|4T90!OGDSur9G9k76im4Ia@b4Nf70l;?^&?nAE<%$xm z24GAhS|enPh`PW%4RnVhiS7c(cuC?O#dk|^VyhA<%!&PrkTWQ87$MV`{@CPg!ip2^ z0ibIX?6I#IHt~1HsE}= zn1DSQfd_yI587}JnD7ulmva!h4grP$?-_bo#!7?;;S4~_pGV$Djr>e|&xZSoT)Cfs zJ`Z>lZ~^cb;Aa4>hqABO@M~bg$AF?mc<=?Fy8v+aiMgf}N26_*GKL^=k@b3Wq6To@EqXwV9QFtGKKS}t2!RIdlUIaW2 zcoFat;AMa=$4uw%`xWBzw+A)Pe`D1eY1v&lOahlH` zOyjSl>EB1weC;odKQCYZ*pL2+p3kdC+oAD7df2x7ZA8MT4G#ko9s}t7`ItX5%HI|x z@b^md)AcdahHMzd?*{>vtzQ(**IEA>pye(YazR5*r}L%QIuBnSZSr5Ub(ws=+xJlbU&6~b z!)kf`qbU4+556K+^Z8>dw*&43JP6Qy{UZ!#Ap4{t&!2O76mS9X1mH=)GXR~BK6v9Y z{7IQ*s5>EK1K%x8;7g?me8n(<^&rr00$*KA;LkTX<*vf(UjdH-o&@M;<8}Hho|B&g z=ofMEO-_8Zkxu_5=;r`00$u~~Jz#v`RHy5wZJ!4382}$2<@2dJo$tBhYv%Yyxlim42F5j1{UzV%+tRtTxCh&n_0-r)A@aba$pMWMj1Xw6O zHUDAA@SOn!)}O$75?CJs?I*lv1K%=8$Zk-;S3VN>mPi6$EJ@(gtGXQ0e7KeHz&91} zCA)-L8~Daw!t*w)MEwa{Y~Zt0+7G1p%oKsoZRv7I^Vu2D+9f0+V-07i{PT=?gfE(pZ(;uzlYB0DI)E}!+11JDMnndI`YX$$x3P2D;lZLc%(dy6^atPZFlJ6PbXAKPEj>115p1{u%7rO(jdlQX+wngmK1@_3Cc# zwDtYtZcmmR8k+A4dhA1OT|B=bv=@sZLaT=LQwaFxPGtnx^y4@-ocy%!%T{J{u$q%eCJ zih$~P;F2-9xzlFnmWVG91=#e@m@b3Fq@NJ^FKLnf79r<65I;Yd{0D`6eT)33 zB6+9Q?@hs*k)HjBdveJLg7<+nhk6NM_-8q+xGF<#iTd&{ai5Z z#b+8R$JlIQ)R{K&lzz3_T*u`z)|C0rM(k*rlGyPG*d1 zndQA8m~zIhQjTxNM@%_mS1Ttoj+M+ zrkt^{W#+$4Fy)Mmt(?pl*)r1)L~(8>{x}}y7{Qe9OEA{0G;ZTaX@A1pl-3BIHy8S+ z^`AJd>r}fTImy@u=S5+A-UOR$rhdjomRbLbb7Q7{jG3goUohp2rL3IHm`XBZE6I$Z zEVI6@^O|`Uv6YpxJjPmz|1mvdRx4+DcU~GZ<&0;g z{FaZ$O!?Z&V`l!(+&iGu)mmog3OgUqA%PfDjV9FWKOZl%7d@R>2|6VjdnDyuT34SiY z&nNf?g6~DeKLVqBm0jP+MjuoDNx^>%!9Rj!da_JUf02y%rin))xtZ^_CK&NsnBK^X z2@Vo`Q1FAO_)%~h&Rl4<@{rlQeMR#lV!@e z=VY1o%0>HVrhW0gn$dskoH)JCFPQmXUEVB@_uowZdqn)A^%Kne&n5UoG~V$b)uMmm zeG^muR_u}3_ON{Jp;%`5M+H;PJryax^QxFB=U$7H<3TfG%DD$)^*b%(MUfxRPSIigbB~a3gIqG}UlBbPei(1jMA@VH?7rWQ_5FRwB{Tm9 zk^jCH`DZu8`46;^7lr)c7V>>UuKP#K=j6ZoL|p#kE%F}~a;6_B#OcW^24gh7t9&+;q0i#dOg}30{naj|9%rcJLpv30)GMNX&0tH0p5!G*&)kN|4Hy^ z$jKKW{b?``-Ctes-&DKaXHVm#>pvS8vi{4!gV=AGfSmQMPsl$7?tnflkn(K_`R{@E zg!4V?tAYPiwC`3hpRcSv{}BAwXW%y}hUGl~zEz}u3>=r2Qcr@Vz9$m$lVE(Fksd&K zwC^eKfpEXKOP!(K1i!KbpYeqCAy!sP5wD#c@`tcxJdgagf0l#sErm$m?;*X^Ck?sX zuk1p7mw;ar{hI;%h-Y$P`JVuvgnjXhrR{euSo+Hh_;$p9uZQxlcIxMuH1@D`dv-$3 z@nh_lQoF&JGo$w20sgVD=YH@vupaCU%R30h^G?*hL*T#Ngug;X`JzsB1bhPeJ`<*Y z7A)<342~%6`2yrzFN}Vj>J{)o=tuvcKmG)q#{b+`CjS>0zMF;_HN%C}t%#TKu8pq$ z*TBn#ejfp!3H|w*0rk58EbV<6_-X7nTK`!O#*yX^j>nDQW!OJh4W_?Nf@OQ~-iI1T ze7J=5Lw+;(Iphawd+!E+8v0rL+zzg#Ex$|8}gC=L&l*1%FM9pOxTI z`1_40kL_Cnmib2#ycPVq@ZSRXCxR>Ba~8+*!{@=TpuR4Y&-vy)uq+>Y+5GG+_BSy0 z=OcbRk^b+&qZp4HU<2y=QbPU~_~JqMGv+ng8}Ga{)wdLmC+lAUj{UVmT?GCn>K}l< zoFA?Le^ltxm&iW~Mhw1~UBXXaZU8T!|F&!HRC(~Nm=BkPTm_#H<7qe8gS{4^1KFNC z!HiGrc)1V!4$8+#+wWmqbig044$J!%_%!@`BIFa`Htbh0KkfZ5;1c|AALX#eYv7CF zPj){08CcrmEbKQvAoN=azCV24VEzo{m_I%g);9pQpTBYa+6IotUrNn_-@)_Y!9Cs*Nf`cQrs_+C7}+4*lj_!a20A=Ljt@NVe8DolR}df;65N|$ANG6}>**87&-HgBKybR=6qe=`b7R~5_}WbM|qs@E<$-bz&KEC-F!g&Jd>6*6?XM%?Gx5&JJm(X%_aDIge2Dey zcnW-hsPEsvvi(0z@JE&?)r0kr`?xIceDMBD;qN$;e*@?D;4f?tc{TWD=(9THtH5%- z`&}^CM~JolPr>1LIq!QGeCIy@GE6H!$AlpR~uFV2=Oe=rHpA z;2%Wo@8D-?>b>Q7-zwDa5cneDe}4mh5$)0Cp*`OQUx@kX?J)fb@FC0(wtX*x*NAxQ zE%42kVE$nJ$p1bV-^Yyf$KD;kF&nk-EU>hHA6U+R>%rWwxBiEh&AtZv*Eb zr$O1jIq>bU2ddTWuY;e){zWeI=RIIq-`(J)=r22eeFa=Xe(m3|-$RM?c>hivLw})o ztmli=^WX+PkK?`(+xuc7{TtwSR_b?!wfw&m@@1HqPp9EOVgB>Mk3{WFsY}84LLVEi zTnX;z4Ce#Xw+XD$_)qI|`u*`H#_QkUyWkI0nEsFlV{AwLQ2`%k2|9mD&4EY2?0?$x zHt@6feDNhP+lTiD`8xoj{9gl~KzgXJ$L9fX5p4V8RdmE9sL#qDhJ1UJKBfK=T*Ca& z&GMn&QScfuK2LzxVZOKX?Z1LIq5alg?|^TG{i@6l{W|dq#vAZoyIw8>uM_L%a_~yw zuOA2F-K3~JePA3qUS6i!)ByM#d>&xS-vY)n*y4j>eLh%@zXkB9(Eks>51{_%U;yfO zH+TX53ma?R2fm5p0shJP?Hgd}Uw;Rd^XK#6&*1rI0Qs5zCGfp?{;>1kRWQ8t@3$bA z_I(#D<-d-Oei8o6FqQGgGH?U--Wuxno8UiNf%oJ>?gh*I*MWa7?6)0^v6SxC`lVC> z{0po<$HM$`;MKzaZUL7tAL{->|9=U58J<@L!u0#WF8l+{(*AJ>jCb6k{yGBwm?-ZU znEO$7{d*ofj`f;M`>#a%@w)}0{QnO5?dVVVtd^@eFB?>9b*CPb`g-%-^YfXkS{0~O zIfYwpEofA6!<)}~)xfWmomsb>D|)p$ZaVdade$u#d0lo(UZ%gVr$@Q9!W^%96~uv8 zYAV<-`s@1odyt{z`emHzJN+O#>-fFdOcj-7dX!hrIz_i0sM@@f_sf2L*2}42-l=(7 z9TjBOUfJKT9Bz>oN+0RrGw`TRNM$VtB`+bmR z!b_*V!>>BH-R%TugyLnG!d!hY!CWcl1Tbtx75$k)HrtE(nKs{ti&CR#F6xaLbCLJw z>-oCR78EOPK;`Rss_fQEPPSC7=X?Ja0=&0TQ3GTc|*FuvoU3_oZ}Q>}R)xF>Gde9g(iyMB4julqAakG|x zq7w3cu~@@I3hRzzVsoYf7ltssE)B5d3NNwhvHz?7yjO&2bbn4wj5c+Gc8lS`Cbtb|(J3!by1%Dv ze>+a0+(^!>$_{I&Q0CNxv*~oLj4onwd?<98vRApP{=yoxd^IFTc<~RojzHH9y8JvbAG*w zg@%qZ-xE4euPn{Y<*-P>x8z{O>RDHC>t0#*ob4GOO3d3PG>tvkJ6WuQ+Q~SbTqO&N z{0A$C8rlS>8N5cyC#Rcw&GG2_o2R0|G>7^Z6vy?J;o;G1o0Oc?3$C4s>a&%d4qeaD zUdCz5^j)L^T^JLmS$?$%!qsD4vqkKpZdc-K8$q=ZT$|5FdFhdJdPZ^*%RWjf1oR&S z6_uO^shjIp!{dXP-Vn%?y<)$!#<|jIZ6s)jsog5 z{79!0N;%^&NU2c@CrmR~;k8Y}Q)4tzChA&(YLWIW5}lG}-3*sf|)St4tC3yP-tW%B$!8322Rl zq#k(|otdiy2eDqq=(v#+HvC@ry&g=Js%b>N=H1+YcP;2y?uOA}{N`~E*{Ed9&rJh0 zG$-dTT=rrl^f*lkOx&jdx$JCagXq|3U;r*UN z_0$j-avfV>&E(=ds$)l+Im`7-4>iWPexI5N@Sri%WD{+Va3Wj?Lza5c^Qz&BHmV0! z=y7^6h`o<7L7nS>UMDN%ykBV4%uMc>&}%_IcA&9{VMF`$V^#?5)7R{Dm{jzlq*t=B zu|(ujZPaJ8SaE9#!`hkkN`BOPY$mK>o1I4>kN8eH46WSc#@T$$*ye^ChBwQUE$1DK z1H|-!Q!8cZu1&paW|~UY#nYZ`qn-j23z<%rgLlD*oU;QbC{<&fsg0Szbe!UF6~h2T zLLGP7vx!r*SClF_8^Lg>>X;#NT3t9*F4VDbi!~F$*3Oz+RmDoVV63>qTgW%c4D`bw zsJDS3PH&1_T`%rUt+wln@kUX;89a?3%jh@srvTBbs#bR9BF}@z(|JsPnpvVp6`X3m zyu~~=C*!H>wbv_$Pn+GndckpWJ1Yz%L$$TD!wV3=#ENSR6x^uZY!Sh_YSbB^Bb+qP z6^zDOuQSFV9D?1t+%WdFjpv*aMyGgE#M2=k7S+{bgHt0-F2zS`vlcW>Y8>{6K>Rrm z4++|_dYp}upK`9BaHc0W^Fg7h6k+6rURA7dAk9EZ}U5{;asB_%PDp z`%=+Cop{`Ve>M+!@0p9#YkUbHJnYq%!S^754WEvu}M9TeA0w;wMG;V+v;hb`kU z?$~Pz+jpnbH1-(nVeRrHZZMs#YU|x8^-=NVI?DL(Sa`-sA9LSHscY`C6xa1b+>-S^ zv!z`ua^ZHFImL)+1&ZJL&nwxOw;qCy9WW8cIc@uR*r zO%WOuv>*^eTgAo(NaYXEm8`+ng9*4u?KsI?)N+QT<0d8 z#H4-7xxe#0&i9@3-E+QsoV)fMxK7hF;gBZQi3LuGiyczq9h9(6^oSMWqZhR+J)%=A z6Gl$-y)a@-UHbdSmwbI;K^*TB5xdvCe?w?>`R4M5;AduMRXcR52u9jto~W_h5s{n7~hbL$DbneP20-upO)?$!JliGH)i^qWNq0zQrT-+ybV?@de}eP8LNfjSDmBX`vrYuLON}n$13=RO zJf4Dkxd6ZLd0!&%@88=v{bN5 z3hj~XFuGTxEvpvFLJM=)7+OmQ9>0L;HHh4*jq6oB4`~U}vJ#5lLUGWo&}$fSB{c6q zQ(UBJ9BMcWr3V{EKW#TD%yZjX)%GZTbb%%N$Ib1HWBg3R9Q5Zc)b zGJ76ahtf0*GJ9*mwp@V@M_IQ2h3xf0!38|HNU=$@tb>9JIPX@d1t58R$y~q>>uS+< zD`ZO+(0MPSvw2r^c0$eO?dg065;kvd=T1o2yjOH~BN=SoE}^w*YeVe;Bh(W*vb5OLSyfLt5c8W?TIa<35tuTnQ+^9|P3JG!@ZQl5M&FZVjs%kj`5lxLXr?*B5tn3DM>#glJ!eB{EEhJItaWoiV{R6+`wU zkT?>C;A=BZVByrn1c67*BR&Ae~#Td z(VB!McJ@;gIY*w68kH<^j@&7B65zR(`W%f5hNCb4?u7h4bvrXHdq9n zb>en`h;XayP7rtqE?*b+1=mGz3>L4;c9tS+leR|)j%})*gMLV{3qcCL%eQPS4NBG7MlD}J9Iv(GDQ{U>ozM(iCk={fcUq{Wi%{R1NZ@{XA zvhIa-!nTg|_6;SZ)jr?$q5b=B+Af)xZ@b|S8z;2B)sfYat$mT5dJ`NV@MNY`!&jHR z>ipz%ZANx2vpQLvK3O&8N|CX6eUYQdk;#dZWplTwOsnZiRZNVIjoz>~B~p71?@8Ub zXLmx3UWe~qHeF4NTG7hS7R_uplS@~`#L?X;F}?@Ny*C^Qj|>ciWyZtF#K4xsrerd_ zu42xaY0F$6J~o^hi<^aMGn+ND(aq86O1hZIg)8Rmc`IKkhLf8HKAqTnOE_A{lxsto zQl)CnM+*t?)m*JG9gfb1qX(^U6fb3Hwpc@`=uE-1tn{oIoimHG)!Yz_XYAQUIXiGO zwPL0U?@`N?i19OAhMS+Mn5I=t7xAuVMLL_Uh=aqpK;V%SyT^v>`I##fXT$a7^L8`I zJSLKpCo1`>Ihj3Cs$^xt)3s{JEM}R;6dlb(xNuZ|^zFW4~V*V;TCTBo+$=+e5i6{OMAiLC096C2yBc z$Hrjoagl*y!&~D5dGNguVyZ4!JOcyQ$;I|QY5#EDUS2oroPqC=n~Wu+4Sa^&WJqrd z5(B@;++>JWH;dKqL%TqRyw#5X(giSmu!Lt_|z&Urs~0)D=Wrm6)3*Z0PHWxW4g{-2~+nQ17wxL3{3b+DC|Bl0?{FM}$3dM!Oq{ zu$v;nZiWcE2Z^xbKBC_zh^y=$FM7~EgF0S4-#(Ey2O@?F9b2T2h?m2wGUaiFn-mTy z+@)|r;W33%3M&dvD!fl2=SRQKD*Ud(pDX;m!VbJ>+Vv@nDcq`XT471yoeCdNcwXVR z75-Quf4I@_FBQH?#L@ad@&6>^;G#%LJ3o#+`7VX4h_K(Ja9m+Y;XMi;RrrF!R}{Xd z@RGuAlo8HnHPI_XOz~TYh&!bCy^24e_!|{}jEHeng`ZdWjKUu&yhucx*A>2@@GXV! zDtuqzUlsmCA@5Qg?@@@?B=Z1PBC8Mc!YV_=7L|ytDDi5AtO?X_R=8E+n8HH}Z&G-R z!kof6g}kNH&nbluDLkw2DTQBGDEArcf1voEDSS!c>qO-7*9zZK_y>jWEBv!U{vf4& zqrznh+ZD6&rI-58uzKh{+3PY}&#-71zcXg)yhvx$jt)YhATa zDzoNvZFVwWoGHPp?5C%van-aP+Y(%X+-w^6(OF)R8QQkETr!t0;%9`d#oR?KQz{fp zTy9*WW-93djBwqJrK{CSe!9k+_y0~Po$_1be1(}uH{tk7>cbPS5Z_OmmfBHAx(bc& z?vw0zJ~+l5mwVnJ?gJ9flOJs-8fhC29>;Ru(1wli_`PuZdjkBEXbw64_CetGHwS-H zkkKFK;`qA_eP>PRirruWjuV$|7JawBSKyDelKwa^$KMIp7<9!!?AcGb0yy3Km)PBb zNgZ;OF5MaQ-EmjqER4gBaap6BxL!^W(X8#-J+#NE&O2Lr(WQ5V-w434g31^oMd? z_xBR|9K$_A8pNQVIGY$eb!-6|rm#d9Gc_`ey49DmG_ P+wLOf_pxIHbnN~E+s$+0 literal 0 HcmV?d00001 diff --git a/Release/src/_write.d b/Release/src/_write.d new file mode 100644 index 0000000..a5ae42c --- /dev/null +++ b/Release/src/_write.d @@ -0,0 +1 @@ +src/_write.o: ../src/_write.c diff --git a/Release/src/_write.o b/Release/src/_write.o new file mode 100644 index 0000000000000000000000000000000000000000..ce8c29ed18f1999458d1fd31fc9487e277c1bda2 GIT binary patch literal 1176 zcmbtS&2G~`5FV4HrG*1jApRs|E|5s9e^N+Fr5vgVdTBtagoFfDw6@1TB6i%}bz4qI zJOMAm`*7sS6TocZRh&w|fsxiT-^{l&-kJIQ^5~UiSzyG1F02s1_bZD?=h;Ga;Tmki z;p?~d*!S(Bv+MYF-}CppLBDTz1SV6((#Z=}tnibhFMQ7IPZC?!vj&9F#RIwEo`v!tN> zVaf%exGF+L*_p(Jru%Wk6>s8LAWFrHC@T_h&$w`lSh^yeM_HA-={!fbndmUY{@)4FTjv+i3D+l%3? zeVQ|F!_QyMU~6py09vqI0>f#MrztI1FVKQcGfeD_OL!At)g(uL$`ud5kxDFeYAo6d z1&*E~IDwR8Vo)X1SyrI2i3(0Q&vPt@N{i=kr9>7~3gueWzk>%9);%$Qy4?5G9n*nF zHP3Y5GSBq&3GuGd`4{hLosZN){*-TzqB^&pycW&tnPOyXQ=f6I4ex}U@5pDw@Q%nq z|5h6RHwyR$kk&jcTAR0P{DT}{NpIChPyR-2o3|2#3%azejap2;n}nOZFU0#`NTdz# EH&*ttumAu6 literal 0 HcmV?d00001 diff --git a/Release/src/delay.d b/Release/src/delay.d new file mode 100644 index 0000000..5966aa4 --- /dev/null +++ b/Release/src/delay.d @@ -0,0 +1,91 @@ +src/delay.o: ../src/delay.c ../include/delay.h \ + ../system/include/cmsis/stm32f0xx.h ../system/include/cmsis/core_cm0.h \ + ../system/include/cmsis/core_cmInstr.h \ + ../system/include/cmsis/cmsis_gcc.h \ + ../system/include/cmsis/core_cmFunc.h \ + ../system/include/cmsis/system_stm32f0xx.h ../include/stm32f0xx_conf.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_adc.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_can.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_cec.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_crc.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_crs.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_comp.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_dac.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_dma.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_exti.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_flash.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_spi.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_tim.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_usart.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_misc.h + +../include/delay.h: + +../system/include/cmsis/stm32f0xx.h: + +../system/include/cmsis/core_cm0.h: + +../system/include/cmsis/core_cmInstr.h: + +../system/include/cmsis/cmsis_gcc.h: + +../system/include/cmsis/core_cmFunc.h: + +../system/include/cmsis/system_stm32f0xx.h: + +../include/stm32f0xx_conf.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_adc.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_can.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_cec.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_crc.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_crs.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_comp.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_dac.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_dma.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_exti.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_flash.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_spi.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_tim.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_usart.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_misc.h: diff --git a/Release/src/delay.o b/Release/src/delay.o new file mode 100644 index 0000000000000000000000000000000000000000..c4c4ce680d5f49c0e3debbaed7a8e2e3e89cf4f4 GIT binary patch literal 7144 zcmbtYd2C$89iDk_*WTw{J8L_K9mnAr5@IO3>$RPOgdEP=iI+IU-F1!%(aj#u-fi}9 z_N_x)j-WyXs23&WYSRrB_-4alhZZncZj8 zsz@Dq-}k%bo9j1k=K0jv#2(H$Q-!mB*3cL`yHa?(!vgwQA2ZoIeSv+!r@HcYvxV~) z7h3l5Ef4N){oUC<-?c{5I(}CEciNmo&A}; zuI=kOx;oFUeD|fS!zj@H}BbJD59Tfarx zyiFP+1V<7kQ7g2RhKqJos zB5a-0KeCJdaps|}v^+#@Jjizf+Jo9Zc`vF2zJ}(tcSJoF*p3C$E(pcbacE?MY3~Zf z7qF@4?}=dqSj!+ac9FjZrp`4WXxc`j&=W9w4H7-W5Ic8+&g-XaUp|TlZ}#GeLytD7>&VpFYeJ>6HUzqo^kt=QQ@ z@MGa6m6tgDo!sw5te0W~txhBGY(ZeFOZ8&1p!z5jUZ~4Bk9Sh7U>~{>L3}&7{EDl? z6%AkKaJ~OKyRYfSsE65J(Mb)fx+2VXc01$S(A~~Ens#+Pu)CYcSKj>z&f0kt;wpC# z`MSJyPUJ(FH7HE9xVqt`CVJepohI&gnpo2dda@kxe+2bwC_#ufinC zT0F1BPiMx$`-~bJs@v#9MAoAarBg;F(k7rnSw)4mlq!_gw1;SW&^}cSLadh$!m|mv ztg-K-j>az_EpUp%!tmqaaKx@=8Ns|=vr3UdIa{2|S&?kXF4!zGXICS|LMAek%|_DI zQm9-hTOli*DMU7hhr&@6P6Vzpso)2e> zU6>DR21cu@wId5P50CD^+qPlt;mao$TQ+gt7tuIkYK81EnAi0@{TRymhE4}ey1BA@2z#$P zXvU&ZQzWZ7I1t@3uxW76?5{cvUtwN9lGq=yN*ODcvvQ%$p-eSh&gRXkb)sMwDrIwU zQ}pVA%{Q2#Qg(K3JJPvkoeY%*px5$qrHmPxF+&GzGlbOMK2x4UQ=#dSW!vc)D^#?~ zGqwD71W!AC3emJeo1QCYYhVxAmO#{>&ZTQ{_~v9W%q6q_B&YHOofg30x_X zvE8Yu`B_WkSW0CcC8%S*?od4DNb%TYf{h)SiVvjZ3^($sK3SAtb9f95rXZ*(Bx`b< z);=B^ONgd6Ig>t~uIBcn=ZZB)rR*MdM3qmXb55!+;%nr$jiy95lU8j~Z5h=EB)Z%h z@ucj3eZ`Z9;- z!O7HAVs9#TVE^I)j$>_#R@KQ}*;kt8;gs6w69+~{<U7k&ijD)uaOrd^(-?>Aw#7ZrS<{mECK2D5 z7rOg4ijFgUF~3j5tCN258BhIhSrRXTBaafT#M`B&>Jl|esSBb2j~oU zF;~&q3YSKFxJRA3_qt7Iy=+-sbFTTl&}o(Ew$g$5?qA~HBK_3! z4$L>j(JIido&9CuAdu=)j&)#uk4l~LuLJW}Sfpcq)N!z`#@6LnDkbtSHCMTQ62(CW3|x<>h=;mSsQ`Li zA&FUuvl1VW_@u;_CB7-~9}kXk*X4Jmi9X(o|gC} ziC-tgMtVZ(&q;iN5Fb*%l}P`#(y#&Fmik`_k(Ue7?!#s!e~=LK&?hl0aht@w5|0q# z1C9!{1680Yah*i*5f1;=QWyKBL+&To(Uj=FNeDi%KjbUW&5I!lezDI`k3z^#?-W8) zqH0(0pwd-j2M!Q|U+in(7Scg-jl`c3f=A>n;=3s?5ceTM#EEvWnMHpQCwQR?Uc?I? z=(~sq^(F|RPZHu^3OT9g3Bkw0_I#<9&H!sw2lGn8`C4OPx>K@n#&mV#H`!I9n-|EZnPHtxi|dB?RGWA5Pb5)k0>j2HFo==yb!9iT5(q zq4jnbY)?`8@T54TzbH%N$VX)ZepufB8Ao}rwB1qIRPjiG@`mmMyQJQa1B23m{yRW1 z^rQC1@N@H>gidj)D83OG+w7h!Pojl1~htW|usLw55$0{uVnom#>->Ea8x_~;xYK2;urkX3_(tb7ka zcK7cH_-L_d{^%c;s(+6{R&^kxYf_=*Fn{UWKgcKx9?$jgugY^1TAx&G!WO zXw8X_Zk&qmZOEz)MD`5$wz>>Td<#A|p9vBZHsZszsLpo*GS#8Epz=2)L6sVlg?#jD z!owXmjsNu>Q9&|>{GBpRxy~Yv_L3@!n(im={_R5lCJ{vaqj!oLuZcLM2Tg@2TaYAC zr2wf-DuikekX}UGE*Nli6#oq*z94?org{fKWRJl(Pl7CpPo||ZvwP6L0p)~MiT?)C CcD|MX literal 0 HcmV?d00001 diff --git a/Release/src/font_Arial.d b/Release/src/font_Arial.d new file mode 100644 index 0000000..b7be879 --- /dev/null +++ b/Release/src/font_Arial.d @@ -0,0 +1,6 @@ +src/font_Arial.o: ../src/font_Arial.c ../include/font_Arial.h \ + ../include/font_typedef.h + +../include/font_Arial.h: + +../include/font_typedef.h: diff --git a/Release/src/font_Arial.o b/Release/src/font_Arial.o new file mode 100644 index 0000000000000000000000000000000000000000..deefb97a317dcc40e3d36d5b64ccec778f288a6c GIT binary patch literal 137696 zcma&O4`5T(*+2f=+%z|B)7+GzrZglepn~&H3JA9nn(${*lqov5;pRq48K7f&D{iJ* z$qB(0U2Ti*byYhk;5(K1Zgo1X8`BfQ8gvYp+qL7?+r0!^lWeIoKZEat6}>BR<k9Wy^rIe(0@er}leKRma#+izK)UMxMcJ@E2e7k>4;v@=}B-kf-Ntn*0S z1mBUc z(#DOm)>EfL=2hV__QtLDj*$|VOP)XGY+&j3a=mi?*kG;y4#6_lOL(83v%IV{hr33= z_knos&CjT6{)G*$Mn~9{V?FaUd4AR6rN`~!eCbtI9WW zSB72j^|g~6rM0CNOqca6o?mvkc{L`4{r+03Rmzn-^X#Y3nG07r6;(XgvVd?ds)c)jptf%a%oxgEj<3pn=tFm7B%C!1Q zbnW_waLFeYCFBTK4jCG6$YKUYM_yhNsx`^H_zovS-^hGRdx{ zv18*@MOBsKzB0#EL5}t@iP}kix%ua~^TUlc!lnG!Qmbn%OnAnl`Wp zIm117Zz2l#9VI&#@1I+_{tt`4?!NY>r@uR1`h~Ug;y0)6cs0|>w&%X-OH=5yyfxt z7rwk^^Rstc`RFruT=tWn|JQdu^#1;r|MhOyN58r1pwIQ&kv*ONN8fdokNWPa^1%(Z z^&j3+8L6Cb>ybW&QACDGleHUW;EnFTEKq>)$i+@Lc9R^5s$QeePf08-e#ObX6>e_rgV` zRdC<=_yqTj_}AG(qi+|4>q<2_a^8K9nC;iP!lxaU2P?H=lQ7mUig%{_-bCi5EvEaL zzpuT=F*iEuzRw@rYO!rX#l6mHYjH7es5=0rOGeM{-V!HN1 z)3tpOZ``sjVPCwZ(zS6C3|_$9QKuHzR{Q!fmh&G2{>n(v$0u0*j2Tk;*)vxvr4jh} z7cEli+0RxFmhtVAwoe%K@ykB%ez?rH8>|Nr9V=GbMTz_tKT{=fYEBD!$>{gdnkQ?>7X#zKFg7`HcB zHvfYPyNm7ldjFTHHpd!W>t(aiaf@-pYA&M+@$RuZ=1d6U>V8C@xs}#rW0R{9ZjW2v zFA2xWo5aPofM@ZNjZ-F8UR!H78(wIeJjF48aqqhRRd!Pz^nWY$)Y`p833io5CRd$S z&yRd7ZG6Gu<)&=KJGu4qD=pzLKBsq<3SqmzowUp{M`p05rDyGn%{!lpfidtff~vNG4=`4c8pR$A9>7&|r`4nteJ?Q{I|EzD(EZ;xC3lLS1q-#y3P zGntz`-l&%mn{Tz){Vq8ND_go^0c>dT4;M~a>@q*zaFL`;+3A0J>zq>i2TOHJA_@oV*+-*++e z_qE>d+l$@)tT@sKUvvMge9RGkzSoc9B@2ZgHAid&;{vM-*Y-E|_s<_YVGjCPQM^5eNsSgC@Arq-`(q`o#}Yg1 z);olCnR^FWN%UCnPHBCl)OA_+*eFqWl2e+SaoloY$w)64M_gwU7EWFL+?9^zMcOsp z_f(e7+qmnIx*H$A_>FbTtKa|6U#JIPne+C2?@cZnvth#S53c*sB@16}efqL%e)ZZ5 zm%n?%yMtF=zw@)Cn!jt}?@qRzn*XQoeK)q^-BX+7hyGUo+7EvE_Z_}ze>qiH`qJl7 z2&hxc8On<|R8=vGLzX*)SNg6knKI|+k@8iR{%N-5F@4YYWN&w2nrjc0#y^e=dSUt7 zQaC5a^)Eg4y?vRFE#$o2Dm$)SQTdeEAim3kT8-k^6VS_VhY_#!@2Oy_Pk6EJMW>Q6 zWVdB<_(aJ=nYg`i#bLKU%t|(7di;$ux*WB3!muVpmEBZ!G|*j0kY&P1^W+j&?KaIa zMrgLJ5+e2E7CkO7pd= zm)t8eTInha+wGKkR!?*9Hg*SadrOYB2GG`hx!_%Ch1I}r>j&T-juJe7z zM)sD&9V<`GZhCcJcA#c_zOC5V4x{C`8%s8^X0Nq7<4-=b;*@E1D}}DTcLseG8}>BU z@#2a)ZW5pBJA11Bcpbw4PwhM9&6sa6lG$U5qxYw}&G+y9{!R14`JsL#mfR#f^}z2r z#JzFzfrGLbKk(i@W?dzGd)vqsbAqo_bQ!Z*>0(Q>bor_oVdVUa#U=APTb}q*#mi%F zb}DXeUu&Tp(SZ%y7%Y znO6>}xYQTiCWW)lr@N@kKVh#pvOrUaTqUH>cg~G|yQ20_;SKQ#7q36C`GN_5TIv{i zZC1yKJaPTgeUE+I`IYNNzI)YB|3OdUrTgWbmU;FEt0r2z9((Jvdlr9i>n+b;JTUmR zJ3eb#)bjXrThE`K{NwWPUh(Q{gU?)c^v8)`wcdEs-y3GWU+{Yz3D@J*^Lo3h4)1F2 zdeqkV#<8zm{%!sLjI$Rw&*ALd!Yj`MXBVD`l&coa#MxYRqRv-v?3zZU4}F{j%-)mr zM`fm8S^A4RU(Gj!!*YxDMsZ>wRkwacB*^Iyn-N)|y7vU4juvqq580c=UYSKDzGhlQ zuaZrjkvlC@7G71d5n#Kjsd`;)!fG$+0ov{kED7`vxmZcv9IgAIvVXztlw-{g(!cOl zHSx9+cw5?HNvCo{2WxE2zLZvSw?%7y?NFDkc=>cXqM;Il0!+YNX_%K1BSTFrqBjVd zEjc)>=gL$I_d7)Pu`Su#>|P%G*k*Q^IqR?qJ7T?xFmPvmzQMedO6Jn)0ozESW!Tod zIjP}NwjdCXR0=X#FtfZHjF8{FgyjM;dE$0(GOr36#5@4Ahd^+S8zZzpO33s$)I4A<=|xPi#d zpcFSWS*uXRh-XZV-OZCdvE7mB5l7kG;?h*U=?{s(QNukwvUcF0H68^`&QI!^Krzu}a!V)d=PyGl*O zKHV;L4?oe~yg9oEX7eE(3hkX8Ie72s9rjVgjMM`$ap$OQ_U7ZbvnGE(o`c~IMY091 ztkiS17NKKv`^3LT(Cl#f#k1+>N6pu1$jshi`Kd4p+%3YyL@T%cDC5_re{@L0o$r{) zy&%=nyVpeS7GdT==S|j{eWBM|(t}M5f;yATk?Z3TVGoG$i@%m zH=dq7QAumCYF$&OEsAyQveKA%iA2ePK(o!!w63nxHjP%V zl&W8%J*urP-X4goc1Tna7n59Gwpe!(%f|L`uwY+{}v$31H3%I#h;4<@4lz7xD$GOWK zq&Phk8dQ%&yV|jF5E=X2Us;Hx0_i~;MVg=JSi5(or*5F>sYFGM=r|Al#EY{Ve+k~L1yMC0f9;brR( zBz9Orf9E8}t>L_ANMe`JNyA87V-YbRDxyc03!?5=XPrq|;}mhzVh;uEamy!8maW*k z){B9}1I|cGqTS=xRtkfX=HqMP9X6-i9cjVnymXy7Qy4_*BCoR^6oz@*M>TyzYaZ!R zGYs9jZJMGh2WB)4)eYh7J`zn?a$-S}oMNZ&B2}|Gu4-D0`%Lkng!jd-3Io-~ zzT6&?AIkrarl|om)qI0wNAJEI8t)Yb#vA+cO$nP@;qQxq@hoCGh8YKsMyk2UC0*2M zgiWKpPG8Q)9C2}*@rir78^dARC+MJ4%@iaJD|3Jj3K=%t?eKWwi81b-!hoQYMi;P> zW`W<69Jr&d^V<~(qylE+y<&$X+JsKwARU3r3gD@f!n+#q-Zh^VO0g(c(h>f}p>z2$mgqVpOF1O7(@YtBC^TaqauYU50mgQxQ z*Cf}=V^+*_aPDwrv9eC_5aX7kA?>M^NQ zE*<%hlD)%v6n7_!^2&VbeOqQKKY?ASf7?P)A6%4se<};d~jv% z&=<^)rWmK=y=w~IqoS=zc=z>|!D|V9AXp|MUQrJTe1@msqY@^pe|*6|+Pw;Ho|4=% zJ%*Q~NR<^*$lpXPnv3L!c)*`^RzF<#RN$#eHLJ@e$I~=KWf4nXeS0Dh3`e~FJ%PQR za(38!%-z%(e?rhuEbs^{C!6h%&S?rLMe(IOZ|l#bx>Jq?wt$&#Y=8Te_f*@K%)wv^ z!D;~MMtSYD8-@H$d5M|PDh^7Pax>RDR4=xyxblno&gyL2_gt1MuY2g&&6hv;r{6wN z75GlYb8pPr{mqM>UjEvTZyDG1m51N{*5wcG-?5}-+=@po7eO9(} z_jg=dZ~NL0UU>ML#`=pVf4lFsCm&n4W?xz9+-HA3=_mhv;r6e*llj*3SN!mo-~ag7 zp>O09Gd6uDF|pcGbN?*sIBV^w!O+ zW)rRO2%UkzuqbJfpuEvKM;CLF$Dd?bb}uymbw3i?r%7u>s6U=b=|;3IV5w_bWBb)R zLVM!kM|K7t_oH%S8+^y@PE7i)!yR?s;|8mlb8~;w3?q>W^f;PoK5|bqK5~;~Y9{+& zzpe7JiDop*Nd*ZCr9YBB{K@QMb#! zWjFI;{K~9y+*-per29m!I}izj)J8fn$DA)@jiYA#!2SKCi<$@!6%px>W?IP{x>#ya z0JI`0BEz@4F%YJ3fG&FVP}s*QmJ{?K5+8{qn>@`Cda+X->C~EfdDFIl15~Iv;BF2m z+1}RVW+R^Na%&V&NehbH2NInp*hR!?O+?s`kUke9Jz_CRIv=$z&4u!j>Lti*V!AQH z)=(?2U~7zFgIpV}Y^`71-IlDdxc)%Bp`bh zO`|o4d?|y_b+eJ@mQZ02=B_&)MI=3mcdr1p(K9dhteZUpEy&Je5g|ox?ua({%+B%n zD>Q>zjDlw44$GqmqXT6d#e2j76oVWwY~Vj?T_W~MZl~MhR@|yvtL8PDPxGoC#qF7h zzOs-+DSuRah3=$IcorO)I)y#Zx|1YLEKrPr zqi3-K^_psEAqGI%W}FqpFlT{Lb{Ot{>9d@=lnJyhLe z>lN7y(!5J5SV~ftyXz8Q#c#NiosFw)+$ZQvm8i1EdIM#+swg&xkfvG8#+k>YTM-24 zEK^mt!zp&q8s>EMSl#qKWmp6Whw2DOiqPwq#c+fmSC5!6bmA~xQYa#Di9EQhnV;Ph zv4o70U%j0@^T=-xHvmww)&b?Qu~X-T10{oRXFr=gzN?|^rg?%HtFK3_mM?mDn~}3t z-{)y!#R6q4Ed|`f8+;=py^c}ej9|roPSa9rgKHAs64jMmcMU~RfiyGV@%%#y)Fk=> z1&Nn$6rUG5de8Q?CJu>#HQl~}lm9GvRTrihNwfTRQkxS*dND6$~V57*t2$T zFnL1gtxtC!Xho@Wu*HyhnK|UjM^0x4XY;HGTiy0p8!vhN?f$zfyj`|493tICfi=#$ zlrmG)LZVWaas-;CfHG>oIxm>w)d4_2 z#I;oZ=(|s3Uia1~e=ZD8OV7*(zeVSyn|)5YT1Va6(&PcU>Y-;|dBp=TXEfa5NsR z2!I2KOvM2kw>75QUwwx%XWi}vl)4tcs91i5$RFkQ*WdBT706GNY1fJ}^0V4mX%>5= zTbF4x{NGTS>V2YW>%g}hEnBZ1(zNkU+dIbm;_+LrKmF9z=}8}ZUwnVv;wPsxZolH@ z=P%yH-S>M|{{8CbUX~n3zBy}Wn|#QT8cfw}`{c>qs_luJA8x*J`|L0O^y;-cmi&75 z>N{t@^_zQ#DY9eX!!I1a?su=I<{bU~f}j5K(3^k#hVg@s_qOi;tQRtT{%bT}bzon| zR^lCN-Vw;MO{h8Hsbu#0tH04M_gh>Jx96I9wgtv#?toI~GqhwpwLTE3c=a>#!!VM+ z>$)`Xh&xAkT^=y#`&NpgdBMg}y0Wk1lqX2edNVCxb1nw;sAt&oimGlf^Pv?S+b=EPVckkiaZ2W&|8TH-0u=5Peu+SHISP!z@$%d(4^H5bb1Yv@m- z58KR#O&QvxoYKOP4FbEo6@{QjyBf*jG@;!o>ppWTm4G#7rGQ|*us~yAQebT0{2T+{ z4!9${AmtT>-|3zf&_M=aa^j$e1bVP~M-w|m1(Q{15_1Sz16q5Dk*R^aRPZ_jPOXBu z&x5W4>|KYDfwPS??yV1*lq1p51UwQY%|lK}>eNzaJC)4H5CZFvkO=U=sv#si+`Yza zb2L+`Q&pPMKE)kdD|Vz=fGAC*M#&>;J_;F(@C~cOsvyLSPa+*?*(usw0k>R`j3f(a z&UTs}A@160xeHfP)WXIqh;r|PHe`$(=zzEvOkzCq82MO^#%!^$5cB1wc#?Zm#KRhf z#sbH}tYHpCOrW@%6Y^BK)zV$SOt?27Y-F~B=t6eW3M7%i7)nnhZ?&`-h6?-nI~RNg zcW$-Rfm;Z^!ktvfsA`La`?!qSa8yCGb42i{ppYdXogrZmD0i4+y%iwe~s6uU74A;mnh$U}JwnUlE7 zkc=$VGkFQE#*Eh(BSvNrK1E}nEBsq0M=Y#09iBiFM>6U_0eeVvJ0sKBo#FsHfEp4Dx=fl<)o)oz9z~3E z)q!dhmpq_9!hj3m%S-6GnVgD{wdXj^ZT=6)C1aqrmA5F7R zw1T)_G$#}=^3bgVuw*O#lSnlGF=6x{C;WqLY9((St2{fDRd=-kLM!8!kBKN7A9D0W z6i3M)aL3zyt*6a#>%~06^my-Mj&|T%e~`*7Fs@31m!z4m}%lU3(?aQpdW37~Z$1=`YQ zlpwzs)tx)do}xzNG{Z2OiRUfs4@@!g5dov^bNX~2ke@Om`Q8Pe_BOGK=RTm*-37H3 zy9I~npcwFIBS!KhRj?UCmoub?$YDz4$i+@3`=mi>iOsT={_w_YAC>&&=>B?J_k!kD z?$|2)g*l|i8p*AuZR!HOerF()=yXKZ2pp~7J<&V%KGBhDyX(ZsROX;l8gxiY95%;& z7Dw)`^S%B{+Pxy=0CCjJxLUFO14nKqA^?KPAvz$b)tR9}wZ4aFRPawfC%CE?k|(*q zr2B*`PK>0~ubL`Lnp^i^pAz%&7|s&RqJuUSgivqS@B&jJb;*>?Sq}@`DPpGu=L@5j)i%lPaU|z-&Tyxi+h+upO_ZANwhi&gCe^Z7 z2v7b@=ye3tY`jy9$gu4k_Q1^T7q>%GDxN*|yf7d;Y=J-|*?~*TY!P|Av~EsZK+sUl zr}rD!1#_A)6VVj#AaExI06O+R9P_KuHP?!wU30J6i8#xGAa*=8;O>Q}z~>76UDz5n+1U#xCFd{^3j_cPbrbJ3#jcib7hwCBEilMlS| zH|DO04^Dk>$(o0hpLM!-KQci7{&kL%*-ET7+eCNq-XtMIS3Pj@x0a~2fAO^F5tm(~ z>nOvcM-m;E8b)nugGag1D0F$mZY#jku0GHx5{j95*^s97WXC%LQZK?yjQMo@dXJhl zn^$Q%R5$!Y#?WG#obd<9p|N`!Nb_;ksd(&KhAWC*nM_lcQx(z*g}U0LbchKD??HUj zguOC(RMqM6h>0$N$4He~StPs!*cf9{fuhk#sv@MA9HbDZ9Ql}t@Sw~|ru!sC^QEax z5tEuvO5}Y7J(lHpyU@S5rj@L1uU>AmA+dC+fez88FR%_e{92uPa>ClydIbZTh%Uv^ z^LL50I&EQ1i>QGBl}x^2#ysgxBdtY!9SV+s?O1;!X*U{qpj7{vOWJ-Bv34%FGNuWg z{F10uqf6*+TmSO*NfBk?x+PAL?2&Mz%uyCD_++P;reXGdUEBxERy2?5ZScy5XrOv) zjqpaBBz2^RPyKql-2a(V`qzVAsY@8)p!hm@{_USxQBm;EhfF*Fx%RRbj6s8aN2!&t zea!J>Ll{}=aXQIbv|KFbGoyuF3pavGBAaI7VT8Z&+^I^Qu&OD*YcrKS95ZsHpyTUq zH2#az34S6MD+E!*{S!GgNtOD9Xeq)oy;x=#bc z?Grl^cp%2H#fV;GMiJp5szwn~nG**Fdz3PX`nAvL%_~jeimLc>NYo4&D*O;#NnWYL zh$G&PHiYr{@;=Flf$kWUY@d`hbYsv5=Oj!kD0QEIK-kSMS^I-3E*v~#{{Guz=9(^o z+Xl^C(8mixPT=6r1@du_!91>8rDr>Ch#C8-)F`0wmq^giz(51hY=9(E#DfMN1ZsUw zbf4UXfO0RE$b&%XL{K07CzX&ECM(lOZhLhDg)~r3on&Y`hCYyxh#VwWcB;WxAGX)^ z%y2rB?UIt|pp@uSWvO2CII#!d878%Lub^f7#CTefC1y7549>dTS136B#4JJTJ z6!NxVm18h8b4f$cyNttE8ht(7Aoyo77^9Gllcx3HM3+&Rq=`KmEEVBevTOWS_;JB! zq-lhEH(_NJ&AR~1G!Fxy&opsRfLR%NqW~gU7GV)sR!oynCGtuv8U?eHJTws^aOxmQ zp;nVL27MAY@&fi5a#X7ECPVibNu%H~?c786DfE3EYLmLiqrsG;n%s@WEa2D~#QA#6 zc$d>=<9*W|N)3Za8oxP)O{r4j^bYz0qw)w_1t{_vn5>ZVNlbDsd=xlIc%2+RFakC+w?$PdPps7-Vc|4?Quw+@G zpcLWPN9hpFWTi&FTw~wW>46-r4UzA4=G&)At;52;pxQFr;R)*ZN}D8pTx1%=To$Bg zPI!+6@1>Ew;-D7IB(sSQRT<%H(sW#tv&`2;!J;mJk>KbBL2r=JZN~UP;F~`+yGym$NW(R$S|x54tlvFem9528%e!yde|8LWUUU z=H7>{Ku3xKm3kG*GH7WHlUQklEdhxz1OtU)nU0ug34l#Tf@NAWoMcsn+8+w|)d z#~81WbMW^iC9qq~ii)SS`!w)9CyxE{6`4#j&ZOPp`QU@7sB5j<3|cuK;*jyGc8ww_ zaxmmGe5a%=e3@O3yZWqrs1Wi6f!o7aj#F$nHEg6~9bPi~k$DIu=Uh~)*SrW&;tsJ- z@?oD@GVA1$7QUXuc(&tAx3S6BC+#TqaFU(Oi~vK_pjzyKnLX%Hj4tjoavJPNb+!dV zND?HiBodzN>&TqF)M`Ab-VR}gpUZ2rwGc*>`lL-hBzb4zCmEJ~P->8U z1vwAwlOpB}TJ#em#>vd7_!-`SqMpXQZI7J!kcqL=-UU6=AMh>k0#eX)o2WHk-fKZT?lU2%d^h`UI-YqiecCv2TF=i0C5bx4VS%es zBU_kGy`DDqbsU0YpXSQHW|_-DPv>Oz`HEVClt*4&n2x`fF-CHyM{lRk>$ssp8=bKS zGd`%Fn{n#A0vjG6r*${GV&A>*4JWljHnq4UJ{Hr8ON-P`N5vzCA_U-cHXpBf^q`T8 z={|0a(4@+hRmL+Hwn&-|k*|+Rdxb;NYrfF&(7^_XjP@SQ>yaF`IZ2+};87h-u;v4P zAI?*h@1}1790q-2pHG^Xh-5m{-O7-n3vtk-z% z+lhKm4y&|70<-bT9&iyR9jP~mYw$=;8N+3FdsOELhRgeXBwOR0sV*~oqPMwA5oDN* z5Dv^GUC=~+{^N~?Zq2t|E=wu>iVC$Y?cu^*g+6Ip5hSkb?-jJ@wnN@HrLR{dfA*ey3+ zSo=`*3%~QdHEGhL_f6TFx@vAd&^&qCw67>tXXj2@+&KS*MYsI-O&3hO`Iq4(SNDA5 z!A#S&GgsQ4zw@jAXpzGAu6$*!GH%_f`t?h`-tNBRA@?sHQ9jvt>m~nDzw$?=YoEOR zXMGR7v-wH)w)?*LlXvca_MM;p*VpsEm^J_9@>PS2>EFN3=MXmJ5MS^V?_DSivWs4C z{a|CTXUQ5Fb&m-Ai zi`oYW@g9AoYhL?!ryC^@Zvi{!Bt!s?HNFEGd z>m!kcur#fjgt#V?raJM1yiN_`N5M}NKPrCAxTjHThEph&0uFZoH@bs}TjL4)!W>03 zE}1`KoZ~n#cjCt*Ai@j7OhLGb!Vt;_!_!T;L8%6^!8oM&M5YQHObSID#0LU{1Pwtg zN9wkM6??^Qk8sE%6g-6QHZQfwRFD&fWDF;b1Y0YR@WX}jYxQJpylotIzv6Me%j38> z75xHBUMboYha@m9;IKBfjpG52O=P>A;v}V_|6`}EM_cYRGaIuy-8!YIw?D(mtsslo#3~7X?cO=_2xmzbCvQ zjrB}YZ{j}^z^|0><)SXYp%Ek#?C#s>@0xIeNk2j%%_(;vY9jQmrIJB*IYnUD4LHdZ zJF!>)NbdKAXOmhw=)W9H0o!xfUdczndBDiM;G`sdE)e0pj;ki?MNlpNLWttzGx9M* zH)X&P8-p3S2DyV;G;oHaB%04)|ILN&V|+BSwGl`KxXno(45DhrLpoN-6oD{joqR5c zDr?}Ypp{)Ft%QAmN{bw)EhN%(r`ODR3JgR=310zDZWOjLi-*L`ECw!-(t=S4cMTW< z5+L-@!o6N8fytR!fH{tt2*ZL=o(2VEUVw!L8HJSYF_P~Ue0)TgHqkYMNdF*ZJ(rxM z=e!Wq2gYaW`icIVpaDGp8l2mLi^es9*d1nji~e_w`ZMoUe%aYVaPe z>qw11)PzHzZ=hibkn5s+=a?Kvh z?Ba%2d|KEZxhQlk+a$dFfcbm#mwI4RR}%TLZjy$17r?Y+9EAdZaS~ok4g&XLqh26s z=BoQkd*@#jG7JD5D2CYq9G9Rwv$1A2UR!h-2tcCQDFA`V8t$TAO~mM*b4T{z1*wjL zS);9B8V(*YV^7@NB@t~Tg_8)d9X%RV z<&JnNlgFRP6i{yt4I?9L^C8KA#WxU%EJqXtNsyV0fCN#nHxL3jBj}hMgZ``i61T&; zXtw4O(qtwIvJ?mZL!Pis;2xI`4rdhnDz#in!fwRgAiHZ*(#nPV@>xoX1=5M6`eiSoKtqzrtAZrGt?=SWc9zs+siR#xzJ% zp@fT7pb&C#5O@t+^;iY7Q}~1_xzL6GtwJTL;u3N`isH&Xs0$3oOF{EHX_%=zzwdFI6)o48mnfmBb$N#h;V7(lJY;KO^eHxtw)^us&uLp$_LCx8kW!ZgB=lEp0qsytxN^FvYPOVjI z0O=vkoEG5qHAEsV{FRHp<`Rx6WZC#Mo7F-0N_1Qn4uV@bCDrTHJma}%mYG*7$Ep4x z-9Je8Vx10>oCY)$H6DZ2nhCZhX=}}$wkUbwgegX|p?IY31e5fF8ek2AFcnmc&?JY( z6f+obihRYTo^GJ{WnlFcYSU;96aHZ$t9Z~f)6=k6162nOTUZMBsR%9&!oG0w2jhYx zwV5moaTs2oVAP6nQ4fGsnVLfh0m1~3dv#0f43A1ViJL=f7>#^c$OqYo6>YU>sD=Tp z=SB_nHUc!GvVl&Jlt2O;P0>6OpU8qD^NI{fo0MQuiix{a)1JMs=W+#H0QI6`#R12i ziWP@>Oh}UnTgXs-2tFoJz~mXKnC2w_7o8~j!6uTyEJJWR1cD;ZDI4^gFu7kMByrOP zK9>GznkNYCo@O!1sYsI$K2S)(U*mxzaT7pbh2jnpFdZk<0=sJ!naDs{QE>p2`8@)c zm`)lB4_+&2u(BvgP}e?Ua7-aD0Dx%BAT5GEXch+u4?|dK9z(qA#;{%w;O1^8Wl?>? zQQuu%VuEQNuvt4Qh6yC?fWa2cqlOg?C6`mIUhA2KX946s!QX(c9D_6!4l0ur=K@zu z`;Q9n5(Q;Q*a<8~fpeOo5CJhIppI7jaEh6Cih#)AFaSf+QD7n+HBlHr2ZK|R*X&+5 zmrqDBbNW$eR%8gXsC?jz8H0bpSc4>XkqNUtj_z%^9{?pPSNwICLYZcyLcI!_#HKM( zkVq$y6GVa86mNj9;D&PU29_8%ATk8U#wn<+xcjz?LZ{mGLp3{<8+DUdc`Ub;cuGAW zR-VP4p7GcmHk*9X(6RqBuecAa;F7Ik94bHHpS9kpINXWEqgp-ply~Go2~e4O`1&Vv zZ9$K-^fGXv99+oA2c><~%B3&{msw0liSBfo*PG;M7}z0imPU-@zSB43Xj%ZNP`Mu1eIfJO&g6#Qn z0tl7jzoMTMIV}}X1#Am#5^}0|$}C0%b-BC4EYzLlYZX(}bJWq~8wk~Is2qi)JaCmr z6E{&tZ}VY1E^8%&ez&9*e3{I|b+J#oDm-HqD!nFnxj2$El$ha@huK;Wokg+ABrDkr zibV-SMTJW^NH8!EOP(_dl3DJt7ctWrl44oobS{{aqatRaqfW_%!AMm@``I(xy6|9? z{}ZAAGr9j0ryL4xCi`Gy$_}h?D-Wt(k1R>?6o(<}QWUAj1DaQnWFd(p0=FOost6u< zM$qi=b%chB?UA`zJ>-ma=T4k8_N5L6b3W)#mv;!<7Zuqo^9-Z?vdHCG{oX>z*qqph zng(P#0pUHLQxpPei(;|Hfim8kq!ohm-vC?bW@I1~by`GE7-R!=g$;GqW*@jxz zh>@RVNWM6N7yF#zPML~p)1)2$yXv~Jgd~+*78y7E*E5B-O6@LT2V~stzeLu|lL;9O z{8%yLvkKdM z66}!nNyA2qp@cl8+vyTB!U0O|GgC9KgmgHFojj@AE_udCs);^uPPo^0n&m-cj7s2T zqUKR5*b$Et`mal{Oxh`Qc(4L>NZ*HPT4Ion1D*zJ%+oXoH9;&R3|D|6E~800ux*sd zg6apc^)j1_*bcG6sY4|HZ+Cv$aW=maWc_Fi9XM&-^C!<~%*F3A#9?e^s^HQ1P;-4X3GKAL)<5R{* zW~#}H#RIoB+%C6VcR}S{?#$CQO~3Kf?H>P@wf3#1%PjvLNGzOL^=w1)@zDCq=l$@z z*Im4D$yato{=8_#ini55nLB@E{a*Uc`(_?bL|6Ra2@&Oi-sj%h`oSa5KUMXMni(%$ zf7{E~fA?24yI=RXcindD8;+m;Zqd-b-&^1M@ti;Z_|bR&`uq0^Rfk{u%CXn>>7l?s zUJ^joB`|Zp&+4{bXVu4l;#t8d*l6 zrQ=}}wDsuM4C5@SoQ*+mNeq}64VK`p)WQ9@Tej$1bvQ@>bc*Q`sse`ie!ihDlj-hu z1fxwGq7jr55v$f=jcDXHZdZfF151<9;3W$|*V+rS1 z!{Hkct~Du#4pz9>ZUk*hDjunl<`w-u>ig5TEgi&(} zasg|uQ6526;*C-4DJ3}NzzQ3{;6XMJhropp$j~U%V3!k_jMmWBCZ3S#0TlbeJ!4QD zM^Y%WP%?*|Gvid!$YZ}$Msb5%F1&8zYo{Y6Z{5EM;)wWLUJz9<2v>B9b{G4(aHB;w z$%G=JCZZL$&P(2!wMml%NIrVa?_KQO?+Z7Cb!RyEuMR{8`v2sVZGP3RcHg@h1P_PN z^5P-?h~{VIm(RVrU#76gF97vMsf7?EEEo1YvGkHP3bWZKZC+Zi*je?rY+P4~5sl^|Z3EKL9cUtV5n}B=ogD0a<)T6H`bu z;qh2A{6J}=G2`k8DgFLmd=r~n%y1!)+(guHFEc8AHETQzZ*feN;T zM0hMi=84n*`;ri6sR4I^vlKOJk}GLFin1o~2CWn=A-zP1a8P)u&Jc4#BPi<_C|Q9Jl02&LspR=spff0=Fx!g%rK^t2~-m2IDk z|MtXQv=)X`p?Jm%wMyi0OoZLQuNmH&m8=lH;kU>bU|CQ+9xHot{x6pr2EY`H#?8K% zX)7=bG>)M$TH+fi`MY4ga9j*dFVj4=QXbU3CXjEeuHYb@d*`cp3YUVw2fk!~B z(F!3AW^IN?7;5naxPtDf-%CAYzK(tC8}9&JIF9t1d>Jn$-k3`Um1~4TLf$0rKGPh5 zeXI?qM|mvWEohOfMw;4NNEyd)Lv}3wWHA zHH=*`vs#mjQd>8Pe?i$q1NWrUngHk+G0ZX!cFD%nB|02%v?sQ!K`3l=K4cWcmP}g#Se{qU`se|=3{soYCuOo4XkHKqlz#K7pDS% zH0=bDLBVDtsUfV>sOj0fvCqhs$elSZU%waa?H4;uk6%gPI ze&G|=Nwxaua7vRuHhYh?(h zNm@|INo+0t_KA5V4Y7uzYe|L}!&p=xw7GJqpbT>{2Q-9Tvz$rqP!+;^Y%$^ZvCk}L z7L`d2aLQpu4W*pby+&di*>a|e5Gc8mv+I2TfuCbi`*zU%A0jC{ndQ+_-HGgQDw#Q{ zjcBJ5ClbThRy+YJvJZ=W2p(rn-ABR*NGq@c&T=YG_rFK8hne@JCIi=Y1jR$hVI+1c zq214Ov$ddC_sNK-JA~{ZI(>qIr}D>HrRtaf9W~NV7*0y!WkbJKK2M? zEFF}g!!1n7f{^9`NQN?cQOZ_G=JnxBw~tPvHj0R1;v55t!<@_?pJ70<*r<<@d(?S2 z1hB?T&ynCcL3qxa7#KQ&Yr;?vf#A$$6hhc60ILAHIgukUo9}&shQDybrV8@^M&Z$gHZu%;CiZ7lG>({nYeHxgUs;_+PBOdz@xRUFTn?pPoM5nak6;U_vrZ zbzri@-w&7=^D6jM2PMx3FtDxPFFRJG+wej+>EY}9t6Z)FC^eD zf|#z!ur?|%LsmgW>FP{mBA4xFn82KwdHSi}`%|Z9azWSqsxis zB*S?WW{9aj2Aa_tJ1XI~fGv&6r@e@J2h&Ur5v)QcaD@Q4UNKXeqnOV9%s=zAIPqgU zuMDtCa1tZ34a#3f$f%xs zJ-V^m9j=xGF+e;=wDTHLI?9T?d%I*iR}&cKJ^~{nA@n98_cV|ba4PQ|fJ_(HjgS)& z<|l&Ail8dwr=f8O3=9DiGYLnaW4#>BBzleMPlyv9HQH{jBOmeN4SS{l^wBSH*(n*bdAx1XJ`XL?*YFE}@i+IJS$*KL)dwzK-IGS9 zCZ4{%dal_wcHJ0}yPI#n<+_`Resj-h`!4?fy4{mTfBRX#Q^lL@ zQ1$ni-s=>7S*Q+vY)AKsw3|rYmR~+|KSJ3X-tzn%YzY!>zwW%NaQpFUm`fPYxg@U! zR-&{)&*AM@_BjTwf4nJ<9s9U;cXg_9#F*Wn#|~_N$9YqGzwH6&D2uT>&#n=e?)&+p zz3#hH{h^3zvDWPFcleZ-%d2aHu1nZi#(lPy8?84r*Xzrh!UUqG>1jDKx9}Ygv1-7I zvM-VVQvU4$W;^qIem3uR>ll7Jf2xOptxuMLx^hyFH+~)ud_DQY=!=3N1NE53EJHRN z+W%~}_sr>>k%u~tu%-Oeu}0#=rJcs6JU_6Tx-l2=1z&wZx{#&7Jbu=>)v+0y+ADJuaX7jTlDK@VH{GvU zKCBowja$%(LsNU7w&$f-(jCM9>vM0PI%95gH=ORqeUsiDKH3|Ld!O@w8N#~7$=&rK zzL{Y=Y_by23fJo;2)XaU?PGIt_as|Qlu`wco7LOVh%e6E!uAjGTZ{;F{lyP32N#>`kr8~*{!DeECy{Fmeo50* z$C7o2aOJulKs(C`*xGuRipc zW??6e+{Y&hjxPT1ywo3DGu@f49x%-EF{H8$y#m|(!KP<-RCCeH$b8~Lu}uMCr86h5 zLau)?*-1Paj_TG>J8pVl;*ue=I``nx*B7?#s8$i5*dKeYSltrlqt(ec)3>X6&7MmA z-RJ$`#B1){3)pRl`}X(t-Mo9>&h9>T=EqPS<9}#wL^7Gk*39f+y}uk@TlIS1 zoc8VR?qhrU^Qf((b8+9k-tp?_@`Blyh-vP-K6N-{X-)#)H^gSrNrjvnrCw? zXIjS&BSxD53x?qY9=(=TReu;PQL0+;^kuxKc@?aoChB;S-4f_n;c#B|-`E)`t54?i zZlGbi6ISIt^}lw-OW(dF-EruViTlS#-}5~WUvt6!-`@1SyDoqCwoCTC z{Ate^yZrlp_xTU~{M+8~JMVqXb3Xi@Pd@ybpZvt)d(H3K8&Ch6^S|rYcHZ;ev0dNy z(7*ld-+J2bfAGCW{_r2BfB(i;Jo5!F+4c|r<7?Ml{^0-q_B&3z8K(d_w5ZZ1D~b+`Af+KJO&{Dq-G{f_T_+sfRD-po5{v+W4hxRWOFyH8EwN8?UE zJT=)_^%<`Wg4Ai|ytcR*r+72jeHmBB@m=i~Lf)YwWCG1I6HV7s56|8h~peNi9i;S<93IPeLv8{rIIo1(t>#2B(4B5Plo&x+zu8h zw%?saHN<_kj|w|@oROyqPtzgp2)-J<;wqu;nI*Db8ip@6$VFoa!w(Rq8G;tTgXCYQ zaJa_B9bzjHeKQH9s36n=vxk;-96z%63e$z`L{A_(!)2TrSjSQ-8do(#vps;A1n%xZ zn)UFOW~eIqD#nR}$uC0t29IjV7#KA{7_U2@T)o=ke-2>tWk1X3Wois3qvNdhZc4`E z!a0nC<=DUDWrBQ?OT(6QpF;tCXxs2U{ySdrt1E~9Db}yJ>qXEMBJ;v2m^I~QsE%(< z-_qOK3=N>~3&IUJYZKF>_~Bq|sXqyq_^*D&PrPU!6k!uwYdg^dH}OH9j+@CB*MG+X z)9tkg?~aM?o9c*8+8BTvb{C%UJ)b$S!^|Drap$qYK>OkVfj;ttHS5E(y@vfyKFIw) zUiz*h^gY!{Lx}hw@YW14n4$mj!1&Uq|Li*+B#iXT3zu?l=vNMmFNM)t%y=-T%#Qsa z`Uqjv`V9d?v$H#NL)y99Ojgf~7woHc!C<(wpmZA44Z$)N4aUBg zL+eYXT4&Aofa!d-F_UD@$NC^O+#E+c*gj%!j_^60qNDm#k+m>Hs8cuDH(e3Mnp52_oa-*}@qk9Zu^Z<~nf}K1(8WeUT_Hs0mp0Yw+mRh)#b- zj$nN-BF@tM3`ukP_Q}{JXI@cEX1>O!SD0+velAH)es{^#Yf;PYzBj&`{2b%?%*^N1 zEX6&u^-~kpAUXztH#0;Gg$a=N$8|_ZI$)-msBrikP^|W*>|E+Foo6~}7CYyNv>_dR zGkr0bJZ7ri&2%J$g3pi4=R7fKD(ExD7@`z_tmiPP(>J*$zyw=ojH?YZ4s&Yi6@#(Y z(vX>JS=%wM6re&;Re7K@4b&=30(E92-nSU-Az31lTBG^UFWu#2PVb?&2pMeT407jK z?%jnGv_w=Z3|#CULl0xJzXT2E18yuU__Ai{JA?cnA>zIk+h{>XB0_{@ETPFk15(j3 z+}O=SD0JIrjOAadX+{}y0v3g;H$>SO4BIKX_RU3HUJMahUKi2!ct1t7d2K<0%ki`K zwXB*%`z03rlKlt(fC8Ga5Q}g{_i(Jfj@e%c9TsB^?GRC@8MEvM6hTk2$aq`Utc9(QCeGb2Ic8C;;89@7TUt)Pyl+yrr8~gUC6;gfEkkuF_o37%}+I ztP#_6;fYMu)dv(h!)OuJZBTbO%9M;RPLL6>*P*bIrB_ zzVZOyv>UszMeLqhO}@o(r~6>ydbv7l*} zgDULC7pNN6cn~E{b_ESeoVrBfCE^_%Q9cjg(IX(k*)E%xGE>K&$~gHI>qvA8xy<4S zPKqD%XMqmF@QNN67r#n8CWk<9R%q3;xP~8T!%M<|N5uG*Oclp+$7%pMt3Hy3 zhXPd&($2y)ITc6A#KA9jH9n4TApUsevOb;D7&|O(Od1igRf8IlT{{D#RK5A+f`=_

>@S8(rAp` zuVdMq>GZ^DxLnY5lZN6gw;ZtG%E1eX=*C6Mu?vnI*tJM*J`4bPg{5j<#Eo1#d^mKD ztvKf9;zH;y96pq~^DEsrZ5QYGs>|WnOx7!GP}{}OG(1i=xGOpG=n}HXx$!7^FGP@m zBFjvFzF=z3z?75Ny0r($M~^Naj-9oISg+u=KLBDJ37%{$w!)eIbe-rm-Ng!o5YoYu z1h>}+vaeu$mt*I|8dhbc?I}Zm3;{Bez^(<3nM$%Q{9y#KtWqS1NQG<~2~$YIZ*lsV zKcc^wf!`rI%_xB!MY_5VaaVm^Qs^8>_b(GA%OtI|q6^B-3XBFv^s>~i?2Xl%8FoYT zfk!i1UZxgard4rT;A$olB+~vocF0(PzsM{=mhvQ5q~J`#JqgCM@ND4LQGUQLjTb;; z1kg0`DquGkzS#fAv-kp-Mn60IP@l<3(G+|+V^+WgrbuI=7$oR4W8cCZhj-}gF5zo` zAWc@P8!Fg(mcS*MvQAR zGeeVQ>J^7=Qged-Yx*Y`1;6N4rc8vENnj@amH$V!2G9{jV?+^+v3Mm_UnfIN1vE^M zFKuSj(;?{50U;qJ?1+9rZ60WEY))XV={taGWN6VKCj>$jQiM_l|$Ap&iZ03O2=7#T*K5_j@QrLVQS6664u&3sLQ;lM1>0PK(-nYfNR zz6Ba^978cViHi{0FBc|4eS}e0XfVw-SJ3vHE(sO50O#eA$8u44W`~YuDH`MIR6i)W zARexm0UI;Ca}T(aoO0lzC{C|VyGONwG>s}v2o*0sp#bpC%F^Ian&5b=cK-;3i)GjV z7J@Wio@BiC7x}?asF1a^QNz)D#mdCg0A9j13@d4(TWzb3GtX!EPi`i; zJarOJY!U*{VxYPUQNn^B zO!Y7aaPEoh{&mCn=Jh>GK+)SYe)EMhb()?+m-f0_KRSh^A`@EOmgPJ1f0pGfEE*9-rk~8detfW{2sr67J zB1p)VBUAPWvJniP1pfj>f4Z9&>wNMMrjnPvXG})%9}YE(ew5x>c(J;NlA;+9!Ywxr zB4A)wI{8?1$62sX7i!aec^#yjM}bsxT1ZlPFA$0B53u_< z3_i*Zp{fNhOhW}UX7q>|XYOk=k~M07(|p{OPra+Rm2Uw|58X%v;-R0|BPHjL6L6lk z#f$^sao*Gh+DYM}IfPeDnA)6yl_>iYy-Ju8&jD>>KfDLIQsL#u!!*-LZb%7d>HGmg z12itDIx}md+1xVxLfJiE=_^-x^`s6moyv2k1{H5G4V>u`4-@$oq4Lm?uyrY2duDyG z-rIESAD(}o3!QU3AqroCV)4n&I8${gGuC(%o7OGEe z>his#oj0VdKv6C>4UIgMDx; zo^QxnZKn2IO8uz`{-p&DS;r&I#re#Q>9*C>qjQOnfVG_^)ku;w+OezO#o({x*tg@DW^{0tY;> zu;ZNj<;>Dhaj|ol!Xw#_dcE)?=2<%UL3pp5@J6vp4gZz_J}G|eSG(aC1&`mWQKBiFwKf}m8Oi-od>5;M>=%vUJF`M3yCKt$ndBn^j&IjZpKBzpO9s7}H; zJWsZCePq=zD%Hha9kX6$o3~74wb4~Tn4_^^CJzHq{m8^+A4FG`hf+oLZIG}~MGn%F zawD)RR}KKPr>!enJ^F>~U&M$+-*kx9AsPp!H+Rw$+zEWsE7b}#c}AwC4Pkm@ws#f0 zZKn7dct-ybJp7rDerl!td%t>{p>o|H!qg5}CYRoT#R>o}2_O)WU=ynxl!)nHTF3j! zXz3<}EqnlrZ5Q46u1-RWCw=>M#OLr@H2DMFydG`-1Ug_!7*M08K|I^+N zesJ+;|DS*Q+z(&+#lQQ{U)lGP<)8cU*If9n0Bq;}0CI*EX+5&3uD}1Pl0CGyx^HUe zbA#*_Kl=x(fAdqbi-CW3`NU<7{cQ3JrZ;w#8NLtBz^Xx~ccA!|1TZ(9%lbCBmlGnE z$nw>cTwiUcoUc9qTJgZUlAfauTzpu-!m1=t>a zhApN;nC0qcaquFv6U7(=$1@mHoUuE^AcQtI(goZw?eUpw{0wdoOKcB$%&}BQnxe*N zTImAIII#_VagD+x4!D`7yAm3Pd~s6p$2y1ZDki*0x~hJG4^|+&4Naw7v{*njDp*0G zwo1eh1Q-C&L`>CgRO?8H93+T53kgO82}Yy(j0QDz62JljfTe30%oc!w1W4&lkOGOY zq)^bz&EGj*aqVDqhBFxR*4A?pmiMK8NV`N%d5|@d>qa(o9U_U8#tvhIgG+ioiwf};QP24 z8JJh5O-ttcI7kX}s@^y!IH$*9jt(mzO)PHBzTxXHzWT5!Ynf@Y1GY>}52I5p{|phN zvN~upeP8_*sn647Ox~<9I_#5=*9T2AE}n80on2}DXEy!S`GrXjKiBoR#HhcMEmmE}DwbYchi>Q%&vP}i z%r0}mw7Ei832%MeK6XICz#8$kNV-FC@ZJz0l>6L3L3k_xY-Z0BhRySP8{EX0nls)I zR!o>Fgv7sq_6x9mo*%6BbwkU3#U_HH+oebKtPzrUE=ri;+pilw0B4xVxb(0X0nt|z zS*RU8bF#laa5LS{cTSo-Ri8HQNW}?)N3hhraaz$uO?S2cJQzoElIyV$3w7gxN$Y)P z%fJRa2!05aq?3sg5LK!I+!Krcg`zGkEj$8Yb2(gF_aud; zihKx5VT&X~fkss5uzkuw*8vSQN!V>K>dsZsxN(N0KX|S_nVvwyEs$7s2C!Dobb3iv zokV@cMI@>GVs1G1(>bYMkEj>Fqo~fKOt6CkrYo~7030mf33iBXHNa_%(N~Q^P-z?N zjda3P$u0zOy@}$^RGC}>z}lz;>$E`AS_vcoUc!;ENoZ}o_Q5ux;>d(R(WV4Maad4* zcx7t5g1{15dc*8- zh3%H*CyWoBzK6fO4+C&U+r1)Z_b7&irMi5`dKEi@(qnBM*ci#BBM<{7s3H@DOJhdA z_2S14=tjF|Ikv&S_n3#c`q77LB|)@zpx ze+bU5^Mht69!#EKfTppcxb zu_*X|))Q5Rtsag!SnPgX*3%bJs1qJ)viJ>hRA4Ri6p=;j4aX(9f*xiMBP3N)L6nLp zhCVh~XrXYPM*;|lRD?Kc*#|8zHK7nPWZ31vg5WHa(33DmnR&icD0>RPC~G6VB>f~! z)N#XJ|W1bm=&q8D-i&RyXS^NY~y%Cqu|4@13Dze6`V*i-sZf9hBLGlSdlG_IK# zz37rhP9ap9MdhzJsWsp|$|FVAY1~nMh~y>12c)aJG;-ATh!ztBsUXyZ@q*dQFnbwhFDKMi`>WTY zsaN?y9w~{c0WyAiev&Z=fIu;jNS7lvZIwi|$iG|Bm=`mbHq%KJ)JJ#8UP+UJB$-|W zrio@Oe-5Cy2sX$9$nDk1^WhoxY00RStSpdrU37Jks}F)hS0_cm>f$AMl%enbY7^IElUxPY3gL^#48Lo;_DD8a7KR5a-{mCngLyD1{+cItfSFEIue~A7^5MR%$Zph zIgH|Xl}h*kBvXbXF}#aOh@4|lO_#agrQ*@EbYB<*xyw~;HG1OexN;Ha zBsdhPbo1@aru$$8pM)Y+LFuprDyE9a(Gr9)NuEO49*%#Z9DxOTjl)9Si**x#@5vEc zML@?oS@va|6hHR{)(UDM;IxPWoOeuF5H0F<{Bcj1;lfl%dz_B199Psj3lIVN^t4&BTtJb4R z&h?|M*sNtmKH88hBog|mWbNt!jTC7$UECCOJY6fRODK>qE)6l1wDu(G8U+mURsf&( z0sD1z02XzoW5%O#nPk*SLP)j+wF0N9<^vS6LP8VRW33Se7r7Prx&jch9gMl;0^OQd ziAt4^N<}vO7lJpcTOj9f3At6j^ZIM{XG`p{p#eZ_gGRmxIWgBsLmfLL*bq zqHx|-SB?~U5`ICXE9Wy5KIhq!FiB90He%i2M3oEA4{2O+p*}^4ac>t$>r32rd0|p? z=GGogB#$yw;aWAgNt9O8f`TYf<kanLsw&0UAgJQS#!9+^hy4C zGnbUP%$R)dv3J$bFJ{k&d6rHN{K)Z(AN%+8_88@lLWv{v0EPOyc^el^utabkV}`nC zKPp?|>wo~!qAwE;`bBLoB2Js$4^Uo1_$RR%$%hbS_3fjL+#yar)~wTF2g?~@44u$B zWlCHi!9|XuNrbW_ora|9lbC^!XLR5dF`lWZSrIA+ZXIXwJx>>$w*@Tb9lk$aGOk)+ zERH#$Y87n6W5ZV`L=>1gmf;dWb!C-UCDFB)T+){uqFtt9~W6f0`>(!?QW(I2RiHL>R zCkjhC&S%ih84^ycK*x0w7AxR6fQ}W1YQf8s3@|j+I>DIE8EV%jPoPNFkXOLMZZFM4 zH94^ZHd@f3-G+mFM1xPVKma~g2`kYiz;elB9nt_3dJt9X4{?;sFQae$!dfzUaV46( zv=k6kF@b6%5ZGl8g|da`nbNw|+*D?d1j5?184VmzVvrLFARoP@f|7cvIn*&JZYRju z^1nxn@YcmH8RT{nYkQM>DNwqFF6>cKXxu}(C!$E&Eioz4ng;-d#d%lKy(MjhVPopz zcGE*tO&>@Vxd47R5i~h~RR42O5KJ&BB?WFEj!HGAlXSGkWy3;3aLsla=rCj+oKKSH z5l|7RBb!xg38$mt#+?LWnXvZJFGfbEhG%b42c{X+k|a+e67_0=g6Bt>@0aT&vXxYNg=P(90o&?*Y-qS=277kAc`P#R3;H?bPeO*qQ1LFHLm@N z?mMSNG}NQ+PZjcR=tT9vdM28LNCj3m5Eki$z+Dtl4&@DjP-oFr5|NW-2;igJb1C_r z#c6<)oFJA$=bpbAB?RI0H+~)yMAoNZSE!y7^l52Nx4JDlLHHD7X#DG4U>NE7;))RN z6ax|!IK`eQlK#la(YATKFOgEvitiqF&;ru6I*AVP8dw$r4OauuU7OIiph{M64RVg@^f#6y}q_YkP z#@`@riJxtPB!fBqkR&A_3sxnGA{&`SNGx(e2?^p(;wWen!HwEf!y>Da+Ts_wMe2y> z_<9h8^8qw)IEBFjtH3WTNxBPYPC$`$9P5p?7C%o(iQgvDZKWeq9YFBRHCPOtcYz^e z_wV|;gnYv~E&+&JWAv_OPdSO)Jw-Jv40$~g;#Gh@OWcKt7X=Eq6{aZ>x?oYJuH$C& z?Pk;aK|!VxX^__n7>@h;wC+0%;J{CYAWQ*6I{hi`Ie^N2w->mtd21yK0UzLB;NEhM ziy0OtV0~MZ*_oBi+R0C@`o`n}%L#&Pa_4JJf7V2a9EISxU(w<5I!AKk@{9vPG-jL+ z*uEfvLI8c*K=z{9L{`mBE!aD!sZq8(=TN6d5z9wFM#~9J14dUuuw-kSwN47n5w&Z^IldF?WTSSl%5Ig@YNTpL zF@3QTC7nj0g|=Dwu@}nPj`vG|2_To*6`gU+Z+`YLnTyc%WKvjin3xWk{OU|5Kb$;? z=@1XfG~;E`Sa>RV*YCVuv*{1S66wo=pH*4FKmc!`@%Uqay;~N{Oli z#luQ*n-Zf=kbRx85Zf5{Y}Ho+D$BsTo^|z|dA&a}==f?Wti)HPYkN=UI}N?jp*woo z2(e*!(eUmW@30UzwPB|2tiIWm$W#7+J7OR0 zK2~!8Y~=68UK4raW1>c|EmE%|11lj|TbXG>CQO^A`+CjCNw)kFM|#Zk4b01Xn1o1k z8hc~DrYyUf&e)}|=1p9V5fMJ2awm4{e=IvT0X3}kJ0ez$K`vf0q?ewrtiol}5I$w2CpGXZxpI?n>a0818=Ev5|z!QIV zs3;pm_xk>4J@zLJuO*1JSY9HbI=9o*$2gd^QoJ7i`SLFR-Ud<^w1%mVqO(|=D%9J- z^~9YEMJ>p&m%i}unR$ghh}~6OrbCQduhHFM23^1)l)xrl5X6|0N~kjpGiaY92tL*< zar%}R`!_<%5h;^gcRZlplxW8+o#V%eHhG-&QTVzFaI3h@k;qc?vej4|3zeU^K~Ud+ z@navMv-KcPhOZG+na$*U6p|iGIjF|cS~Ho^E3`2I#^rn+K-B=qFY#+ww8}Jy|GX{8 z)*yUz7RE0I994Q$2nK6GYeb=fXY#w{UCa1;=?+Cs0~LjIKt$xS1Vjc>LAOocI?6c+ zXalN=Whdvw1`4Q7|t&J0)_ zb!OHsZ#wI^IOnE+uTE|@cL(lxUS=npkH-$bgz>gWtPkS| zAWk|^&twE-K`W3K!hLG;AO(`^*e zOPo=Sh0?4)K&sVln$WRe?x28YQo~I`lA6#N>2{jXry1Niesogypl1-~j4NW_1@`DN zLKhe+ACU;;fgd#0gwYNZ65yj$*EI*2R(76po8yen2klaB9Nt1vSA<+Js{}Uw59%uY z%j#<7adpM6HTH)O$20pF_u^{~KqzC`M`GR0Dq#lLc=2w%;VdU2udt~J(Ua7X2;2NB#n znv;MpTChHbDO*g;-()$OjN&d4>4Z*WY}7N19lpK$)xE=}=9tE9GeaG0_~1x?WIkQP zsSZdrgrs_ct~k&xjXbhT7O4oRBn%pQARRD+PNAq5dmd%DvLIsf-D|X~*dUybjt=ii zrlw8z7{BG>&JveE(2+X*_`pEfUC<5#;*IWSI`UK6<`5#1yWG~CYsR%hL)3AoXeqbE zsmhbcYffWOqM8tDn~$1J*aI7NWE;{9_5=v;i1(rT*gB_g(g!xu0n@(h?%+rF>tvlA zbzBS7ndPh_t8}G}(;-T}L^ao&a(EmwoX$9iR^SY$(#3$MfmvWcJd={@NNT-;uQJM_ zS@tzEel;PZ5SUKI%A$!dLC-Y9Fk5RKZDlAxfG$huQ~ql=Ss{TIM6zfd;$Z}89Jdk^ebf4*Ff>jd5WFF(k%j z#>wys3~z!nM{MB#U||W!O~5Q8$XI^BEA%sL{NJvN{D2gR3whZ-BT7QbJi{ZrK!`IW&Gzde7XOwte^Y$2WiX z-t)hF^BvFp*xN6B`M;a}$u~advg!Zy(*Diw*g5=PUj5eZ|FLhm@BJ@)@GswX)vvA2 zeem!v-|%DIpZ~t|pMUc&Uvber554z?e)f6)IR3QFKl(pk@!r3A@l`MXvA2!9^6&ob z&wgcj{)TV<$ZNlE^_9PR@6X-2`sjz2_xwiq{?Xt4uFJ2P-!ZZ8mtJ=5uYB>@Z~DYf z{`A7jzGv*}M^60uwts)>&M(~hj&Hy7BNzSdAHV0;xBSdYqu@OIclI1=%{kN`-(7O6 z+pEv-tlr7K!I@Ko2R?h`%nxnbyLGVXSML6ff51XANj}SaHes9De5)CH)Ida}Md7Op zM0?4UBJyy+#{KXHqH1!@PL+yKk-zwOBeVahjfO+ph{!@1Efq&fqd_=35^u3F-<~v* z+4*=QGgT^@v7-wQ{!<(O)8r_|zF2w;1(HUm2KC=Y%c3Pbo@}!_Czp0R6wYq81j24D zXm`sgY7@;~zM+lZ70l%WeSIUBByi`G5-$bhzhePBOZ(?qA+lqiMs(vB853F z>FIeTmNsSoNnsYgW7H332MSt=SF*sz<+^Jmg#AgDNjT}#iT)60C2?Nn4r1Ak9>&9N zeN(KV*T7C{zzPm9W~$3d!W(lbUlA~7++N&2AhjY+N(ag5!aFNf^iC!27S95m4$4l6 zuCxbAIf=R|lq20VjGq`_8@iAJt~Q{pocf>w1CWdEMr3rxfIgI~0ZOi8Nx4#3DT$0+id;%cxJOLLvW=x_yBmr!_d!yQ-Qb_2Q-4Ljt7i>N92*ocEb7q* z)n&@i39I^~tU}x(LmN`pp8suwK`@3oVh?FssmvHtXSL>Fr{t7{7D0R;ZL&;Gz6rr@ z6p>r)x8ut(K1-hH8EY{Co;@jkfuiW(vjAfmd6S4#g0a}1f>D$uB#a;q;0)6cVbLVf zNe-q8aSWRsKNc2cYvv&CA2Y}$KuqASDTQxCx}A=a88X#hy!kt}=EbiaPs3lh=gvqF zr&BCWq#n*8)Z^t1ynqSCPbCe_a4owu+vs@bjCqbSNBBn?HcS=U%yk-if%=%zEg}D z)2=Whe;w9#zB&aF`%};m;q3(h+yXvTgn3%y2`PG-G&RDw zpM7TzTSLHQgiJaI(LuTp1mIi>a)0b0{5dh!2hPo-`wRxjjQy|uFM2|le?l@nLO=ZD zP!j)3nU#=R!U)anZ{C&X4jnjtbTx)ehkotNpVUI`&^xNT2Ae)_s(tWgLL_qUF%XQy zz08YFvmct8!FVZn{gevQR4EuM1yv~sJ4?avY-9GTy1BrHp_^1!r@hBYmS*tSy>C4Y zM#x)vaa?N|O(o5(j3kmEGICh(YrI@;a{CA#r#jG^jZJvE+!c?s>VJqk_aQo~wKYi` zIDkUQoKMubK>|BRQnqw735Y?%3LOhU%?)s7tdu_qxj6%vRK68Z5>@~r%5v{cneJ&3 zgOP!N4f-6^77$s$unHp*vZ~ee(o*01-XPDe4|pl8=HEm3vd$6I>tH)2nbE^3STgqc z(IJQfXdoVhIEV=futy0BC=z@DIxpT?pceKD^bU$*2Wcsv-q?TgAl~OC_DY(z@Y(nS z+(CJYOA@(rN~CSdl!mP00Ezs56c`C^DGk8dxJ2TWh@hn!oS=rPSygkYrW$1pAu`EP z-Kg=@jv@sb!8iaxMk93k$8eBvn6{A{$ z=;f^m8+QZNFEc{-VG_wmi@ioJNIC#-Ew!+6!o>p-gB1n@Gg7Mn-cr&g6WrOPB$7D9 zfR5=|#}|nnl9W9z96iV{C7DUEIIL6~65npyxq`$7W0M#go+x9`?Yy6O1L7ci#~+<( z)CqyY9hj5&-Z*0mD(un(l~h!WK@rqi=eO9ICo>CHzYH*Ll}so^!-h=Gx@%cik%{%8 zIFf1QJ#idBGYl06g~>#^(Q}bZkoOV{3-v*rVlo*Thm*F^B{DCAmC`m8jRXcvO!5m) zKMGy*!;wUtn`*DbLl(pwIClpN6VctwtU8SBJCTS6Iw9O1g6r2gx(2c1n2o?>(6S-f z<fT>bKZ_$MPC*9DTKBvajHX-loYs`uE1JWV#PAbJ1tVm=C{NGdh&57U`2@oktkv| zxj>394rUR4vYeK&q(>s{oJt@}mm}v-v?;*p4Qdej7ZwY`XPKnSX%se99dMRSW2-Yi zCcl8^atNXv+u&6okqK(BPLFUH2Jy;+OpDlwj){o8V#q{z=?V!5-J!=A~Xs2z%LfZEYlxeY}(+1DxoPHZGlzV5B7jB*9pCg*wSe!z8-S2@&wgN3^LRI0O+m znS>ZD0J)+irku?yTBMv0V~IimLQ-}|IaYz#6GN-$i9Q3#6D?K2tIjl$!rDNZp3AxR zawx!4A84MWNja}C1aQ)j2BtJe9MB0mZij>foE-_&Q9$i}k-O^jQUD|oN3#OuN+fXs+IU2U-iQRCSJ==pHq~D=rj>(k+Kn7&D!Ba+M^SW^ zy@0F9S-ffV5-YRFY?P^OkwEc_$|Q6n%v1v4Mn+TD#>yxpZlBB3o3DY`e1~S!i71r8NK)x4ff@?E+Ac zILeE{(4HPumFMZkSdF1Gf%KTp!Od{R_%K3H9ZHI6QuM7bw1urT2-~S_M#ny}|5vv{ zj*T|}u2kkoc@}calJ+ft7BLrj^oc~^6zf|2ttSk+0aGa!v_<8)7UUpkqo5^eZK3C; zn0S#&0Yab-l+m>GBxIjTvq;6W*-s#q`kdis5$p%fpIn8IuZ??#;^#K%(JvN05`gII~Hf1`rpdLa0nq3t?K46*Z)?RPA5Q zqON~6eeXcs|u0@bF{eZ59$rFIo5tQ2@m#j zlM7&giF44)1;%fPRiS?22gfPpDtOItop3=k09R*TEa6O6<4kdgnUg-@Q^un&FNz{H z+GK|*jO^+phA=XN00KPee3j^c@CXX_x*&aDud>zwZlHNHrz@cauJLjb-|D380~_I1 zY2b|vN&T=ZO=sXiSz*H;V(z3`ehrA&r!p2{WkvugHi^|Q149AP!$s}Gfg%Ij$OuXB z@;Mnn?ird&aukA({9E%F{NhMNy#UpB&@x!@EeCpadOJeO6>?$46EH~;ioMu3eNIg1 zMl?IG*I@S520+STD6m0f>A(D;G$oh(vD^R`{zOEY^9Q+oxx?JFYDdq-02J|Py%^1F zgp0ZWLcadgdwZw$?HxDmUFlNdxB&xqQH91>^+5* zsned(q3~UWAjRpTu$-$jD2i?ExyHL52ZtA|-T9Lv8j`Lk)AYpiaw6AngA0SH_ZkFG{M2$X0vd z88riL=u^Z8IQ8V@CYxH#z?w^>oIg6I3${IUmt?RAJIc!N;{okaOb%PdJm^JF`sy~8 z2iC!~*&rTy!i&Ij8QQ$B;ejeq=|~Q`Y-%sVOHofq4u98)@~jy|*w&|E$VW@}kUS`_ z3`uB<8c4cNR3JPPcnB;?rF)$g4iPM*pbKeQ=v}V$}bGEbO#Voz|aMa5+B$gh{8qG@*gh)%S!U_ z*J@Y|R)jk5{sb;=C6U_Gs%8r7jps}NeHMAa$R-}j`h`WM3KZ}MioOcafQ^P1L|6q1 zx*L+%6UPRdjp0{zY{JWo!-s<-I5h z)S^GML+<;^`q}?a=g}Ptr~iO5g%r99YCZXeuRGW42$^3>2rh>z!G@|}nMeWWJZJ$# zV>`AFeMPJbQ+I?F8`!QBuG5)QBH?qTV;_*Hgkp4& zI8LLz5f}VYBxsgo7xiD3&*B1=^!AJ@$sMMW=C~@kxki=r;X)lHbPGwAmLXNCL#RrX z6icL%WYfV=JVLB*l8mV$Gqyu)Tbd+mo_#!nT4!A;K!PqklCmHN8~P!wvW2k>p_D^p zP|mF=H86)WnJ%G#j3mLPkN>Jk&Mb4L}z_s8T``NLE~CjwBhD0yAzqUg5JUP|xG zF52hB|3+HgOJyKCVo9ViUVNegoa6#QEbxJZW`Xc6BjJAWWNh-Wn~6f zUiB%JKv7K#hq+Ywp7JPp;jeD}lJ@Nj+8~+AMH;!3xRshP@pzQlr8%cd2Ck&F#Cq`ScHo27B^jHaB5eHnv!(k@K=GQ%Txx4S|kQgpP6>@Pd986aDkBU z+CWh}*Hm!23Qhii%j;Sm`yvb7$U{epig*FGO#)u4^76NR3#w_EHgu(?jH*j)#lkG; zp+xn`bCC{<<$$mvlx@@-uU&~vpco|GPZz=*Qiv+4HHglayj8e0QE=i1efM4P{~ zfrIW*u%yDhu+?*c;LPmk40)_`hLCuv>(A@$|O_*l_2}LK6 z+Se#CxdO=+kg7bSYVDFuyfM_?aK=BTY9_x~2)64i2HL!$g9k;#fLVk9R*elpMi{|b z(w461AHYE4$|V)^0iMbxzo`XBL${=>*PjKP8=gDxa$hhji0EF;Xr4-1WDE}R;Gr6n zEe{M#Ljge+DdiMEc%W17uE5(Kl%OFwz^b(E9m43rx9LjK{ZT>EzVlP!$@J?~P*PSc zbWTd=yoIB&nfP>yLl@yWnxFV%k=#_IEf#qVh1msAnoz6`)o#m<(a!UMo4+Frf#*R! zBm8R*dY~o!AZURw#DzF50v&HDQ#KfEPb7c%&{VgO`&Y3UBj_dqw9^)&RrToKuudN<;)bI2(5FM zR4j)p5{+<6u#u@U8P8s@|77ObBKvfu-rU9|79x3G%%hGvhE(F8E>!cnpt6eFiBtj$ zKysl9F`aT@n)Zkbxljh(0KvA9Sb;ZAz^8!FzB#4Pkp##LkZ2-EI$6$NF`HB5x<~{G zze-pZ_ewElk#vGbstyMpqtTyOcG0cFo2~__V%%}9xN|(VbF;V){#^xsGFvJ$_b3+Z zRxI%Q)r|tq?QWl2tX#MJyAdHZqo#rio!x@GBNc$ z5}*|NxFUVUtoSHP5+CHQLj{UmP@s`wJ$Pdyq~f8_(T7095dueY_}>%x5+!}xg%6ad zzresmHN_CdDAe9~%QnD4FK!a_jm9R1CQd4L(yqkt+NA8^xLNwvH<###zS&&@Ngco{ zZz<|CADqk8X<_In!l|SrI^11eSS+tRZM+I6cTTP(t(T}x0<+6Tw-RYUl5B><#wLgO zEzW6GI@+?h)u=8hlVVMt;CW*9=^2MrvWgg4+M#NsZMc=Dq+BZ}E>xD6g;gkGlNm4Q zwiv^WrGGKIs;xG%0)h}jO}BKa-sKJn!d5HLDP4kJt8ba-fhQE%#zhYWL$uI_9<6iK zZb`cjK&A#VsO54gVyo45;L$cz6)?WNxWtoBWq4Mz0*3Gv7cdZ@ASkdgZgOC_6~+_@ zK~>|TMs%t!eA49Ck2}#%gITm#P@{6$h=33o5|A5b)0i1~9MX-U0Pq{T4`)G0Dt&yY@h5{2C@dWhJ)zFVP*ab$deY!+~I%H7ST`{&v$q6hY?zOWzw4%o*!9G5=QJXar63H>WkBWst&-EPx7q84q>AMB`a37aQv(3+3bAe85BB6wLBeeioMbWSp00JB&~YXzNps7!jN77)%?&+RB&=OJVx0dpDN`NegoI%q%xV|`&ib833t7YZe zuS!Uf=!HsCzrh8tUW%Z-N4yb(b`&x%lBZ~VYcUn11|QX5-!Nsxycr4P)ir`uZRCG$!d2|)D{7=vTb zHsF!6+z@*S0}?1y=orw18P6ozQU%lU5gAWTAhB{!^a@lrgvna|imqM|z+py#%Lo@ejqG?+6{Iu~ zBgu-UrcT)e7q{Y8t>pYkE=OF@)5awL(%7DbSEphRI4^LH701Mil|+)0CgZ%;dvL%v zjHiGYAHrn1$@A~_mo)phGkH&hMujVjDs_}9NT%ghM-dsTH5K!b)qL{w-C~9g(7<}% zS?AOci$@@eB+$4W5*H5*#q|=h5Ev{jp#qSx4MjJNXcHj_>P~zi2_%qS-t*|amkgEZ zU3_f%qH7(6Cj#N-bDwFL6Y<=EX53LaV!m~V^9FlL9Dt(sQMyxTlyF%Bb5JeEean8O z4kzK^e*Ti`Ir+fENM1QpzT;)%@GD<)$Mrh0iO+Z`M{f~*4&UYjD0ug1HJIYPl(M6L zW9FajnCG7^i7uM49hVIKDKP6;Igl%XB88G}6(Z{FoM*=HYB#Eh`GZ+t9iBKE0f&N5 zgpQdk$y1FR&Q!tMWx5$~Q=jCfCk>A|+o{KoL@ z^n?E6i_(AvFLct-Asd!^wveTAVXyZ&!_#FZ4>^TDOpjyIatRqMGH;K`kN}O3ng#my zou;v0fP8SSM0i8HX%3Wyb%JkA`jBcX$ZJD2)Yfb!d6H5|m?xo= zNV=y0rVXT&BiC>=@T`$KC1mLsuRU>FK5EyIuB--gnl=X+pmgGrg@yX+RcpD+Xs}V^ zA_~%}Aj30V$*mgObJ^<>O20KdPcnr)PRzn6f6f%9Z!m=-zokzZyN(Wta-x)e+f|jI z7q#nt4tOIJ*fPTa5YQQM6-e?tdXK1X^kw6Jmc6{btYgyPGR;h5%i2NTEG@J9GSF?O z4X}5C-4;xWjX8)aJ!@lNpKQ$fSsT-Rij7e`I3E^09DI{F>$QLGfU_#Xth**z}p-;CP^` zSM#x>`Q$PEe{2mo%gg!TayB;&%qUBUJq2I+D=W!>v}AY;N9_Q*0BGPO!=+*<7%~sT zTzLXzbCGEp9-pS=D~Y?A%dkBH1ziH0o=5;3^d*{BiRY0lf|Kw;Nf`#_l11HyRt&n) zN3#z=R$@E#%0Xban827G9mcpLrw0L|J9R0_$ZF9gs+fKlPVvP}w{AYgH}TDgUVf|7 z*1ETem$-ahKQJ&yJfD{c*H{1(^)T)>AJKG`4=G>SF^yZ-u2t153D`ise2Zy=cR;hI zxhtd=Swo(HPE75*vW&86Jldva&I6~!2X)6}Fk_z?9=fMtX2VBFPmdcP>CzO<6J*** zru!IVEvmGHSc)1giB0g!Mocpe(BVB}u}Em0Hqnf;iI!~=Q9~|{x8Ep5pYe4h8AI)B zO_j5;P|S?MrpQtOlEJzj3o*!HwtdEQ{upX{^v4>oNGAdvk9L{y6xRXHob)XrNE6E# zaz=@ufUOyTOT8BLUY-7dA@>G6W7(#g z{{tmTt5;0`ZCQch``GfuEr=-G@%8BPyl)yFdNQWLY(N=K*vxDN|PX8bXv&m8Z%BKBe=-K9ahrtEFngU1IbdP;R3*w zvk~Qdj4$#L9h8qS-6h}w6i`euv570-mVFj%K23{bSPov;-q@b{)vqP5eAHFn9~41b z5yY!OdcImq?zk%wSORPrmccEFA6$ZS5;pimF3gCq#v&u29LhVRe0+pg^d)B9!xFfY z41&MJoBBc%`@w7O!W!z27fFMLk~ykLjZ7JOIq#_mYu{n-o%_Q}FM05hANciqZ~f_azH<3@{^E}|cfWG|e}DDozVzCk z`>qdv`xjpF>9tc2{@&9*F?aQMf8w{U`~73DdFY`J{lHg#z({p-CVM(IP~&oSD)l?h(DD-`}L(i zSbyK2Pu|w?$MeW1&wusv@o>-JysYrXI3&6sMZ|gKM;1*Tx4wM1^Ck#^m<2c$YhKew zRwe3E4G@_5=7}o7Xn04(62DNz;qcE?)a0Sz3iRi1xxK*rwtpWr_24GmOi)czi;g`V zJ37Xsd}BqzPo?6uZC~<(`2&-u!efS}z7cS9!9P>c?0;g#Y6FnXU%K#vzXCkb@aKRG zKt&XrbCT2`Vse)y(}M(AdGUDbWk74$@c3=+VE9*cA)CWCj*oo2O2i> zl$PiS{|3`emVJzsqf+0dsod)yz6Owz4wTxwSkg?2dqr9o*Z@MR33x&QG!>u$mjdZC z0a~)!G;m)Gimip2EhfYo&&QuTsk~P)aQMS@0G*K-dgdR825AFHeZW0lMH-(G{9Z*ro8nRV-brA)l zH5Y19RiGV8g;YbjpvqJjvQc@eilfq$YSLFyrN*3pR(UCd5mk)_bV?fppD z2AU!Th~nc2Tbo+)32!JSqJROl1v7V|OPi=&0iq+k`YeilI^t^neafPYk+U<1zNs(DR>m$Mtz_ z;F^Kk*^E5*vX|kdqcz(9smcF?35o3g$J)CMNq zMH#+{|7_{;1HKbQ4g#d;FmS$KU1N2zB_`-t>Xh&6IzB1!U#}g9=i5#=Q|5IDDaZ|kV<59Gp zjclvPoZ6c0u7Lv{#VSZQVNU;%&;PlZB!bg_zE*thTmQD|^y}=0_$|e{yMAa<9)5UC zd_?Xz#?hxFw2#K1n8qvpjGH7>px&z;g}wzg+sy-SCu7ok7|d#}-je9&zRv4j)6KYX zc+RC4y^W`_HDWwu^_>%$Z3wWg^p*1yP-uoKJ}OYATlp(jeeetLvRWTsKYZVp7q2~U z*6q9hoL~G4G&u=lD{r`yMcVP5`AyyIfzAjrL{LaK-f2v$yIWTB`Xcb>6Pr=}{#L!# z%LeNhKooQ3)nK*mH$CQI`>19W?rOeN;p&ww*u+9>t@`Y!?lz*j+l=b&jYiJ5t=!te zcL(qM_|rZ5>^oQ;K^L`5pz4ZFi@W3-`dX=y{*z+>wa1Abdow`u9d!=B%}cM>Si-`Jt9vzD1vZNQ zKi~rD$PA=hhsGgk3Fx7i>i|9#(46GHM_#_#y8~$EN>%z2+ek4Rt7l6h;8B7`m65?s z_vFSCysc2id~$r4Us53Aym8=&M<15WC;Qc1+CBv))>q?~K=lw~(oqO+`B8r!gnQ&1 z=-OXFjkijX)-qgaP@)@gT~H~<))mBPlwn^&s-J0qg<%b|V7f=P;wn^eeOT%IM`e%( zwZ!!)AV5bc_pr%T_drl;&sB;A$hy%eiax}cj<^VA;VYH{gRZL(2OQ$kZqJoLnULKS zE(r)Aq4vPp-BW_IaQ&))2nPs)5|S}K4;z)r&|!FLNZ>Jjd<>PLG++5O4*Ro=3tjOL zGkRzKBp$uGR z`XJmgtz>99S*O;cH5iT=Up-3JlzGKBq(Si{25B^JPhm8p7>zhWxVToO%a?T3h6^2@ z?zwWxLp1kOH0x{+DR=*i2UEtM75C*~%X5fY-FpUviIL(3CZSJYLChx&X(kmnx>jF% zT8yZND{P=q2*^{rb3SvMx|ydY6)DYxu%^gz#)=3e9O_VS=Ls)i#ur#9B2?KcsP)m*R-l1@f zz0!#-aSuSx_2?Ptw>S;8(nDR3%7e?|m!Gs5P0jBDks2VnD9@#n;K9h(gZaM*f!Sl9emHqp<3S$6EzcPwqz zk+QT56yE_5Bl(1ilJ2XpQ^=JTUP1G~FuIFJ((p}D!h@=nQT(z=0t9Dn$vg zt_&~gHSIC40^WlU-@f`G>X7J+Yp4W%VNwRs(v6UO6`x?bRoAIxle898%aW>egY1=- zz+81fx$5U-pf@69w*eJD_A0G!xq<TCWz}?W*8q>oD6K9#?u*^K*%+ zX8lRg>>V-wpSiZlBkj-()u;rtSy!nl{4*95Y%-^4=B;z=8YM_z?XV z&&G4O(n8;y@3|g!57P9sI=)^OEf30MW2~_JAa_3Lk`tnkA2yx)fTVkK)kzK-)+fo} zFNh>R4TIB|15ckqRoIQYDAkvJU@`o`$M_Vc?XRJi!BodlX=arsx9ef4WKEhR~ zrTuO`N?e=^cmMt?waXZ{UfeyjufJw?j2oaU@BByJnVeBp-~08qo?5&w&u<+zyMrJ9 z#Ji4ypzAhu;eIe7^}1RX`2?Ixjd4(r;Aqd5J#}J$L1aKocwW}2q4}KKm$TXdMvG*Y zi(05dsY&G;9dlaq4V0Kx1CLV+5KxXCRBh}Kl>$;5zEmB|08|a6YBSmJVQWfa&1$_h zQR6!;-Q`p=S{!`vqR;#jG*3vrvWh31)jQgDQJhKdNQZa2SU(X9FTJjL(6v-u&0;*v ztPO;yOA%a$NnuEXfdXxEd$m{^b>dz4+iG9RZKA$U$*$@$(?w&zN0%F%i5kct0V_pUXmW)R*W_zq zkY$Wy44{h)47KheJUoHe?!kE>rDZ+Q$na&E9;H%CR<6^%vq#Yw>&{Tq(Z)*qp3+1L)TsM%1eIm9V(5^ ztQ1Mq5CMN)rpsPBk+dV&<4IdY%&K5Eq*uZqG{wmfT0Nr#N+nwtnzkGi#4TmYd+B1J zAU^QaNGJ;XBL%fV4VJ~WfIH1_O&5-17?D@@42Bc|LYcaJ(qT+u@YTkP;TDZZHS}1< zR=mQi!^*(O%m69B!*4CNsYFpUa&?ow(Z@8@XCPdbzZ zR4XT59&sg_-$}`wInk24(!H0i;`I=qNSj#?@NS3Lm&E$ap5|DIr5oa900jPd;y^_L z(-*%asla%s#}gr7`Vkr-l;nCa0Z56s%9A}_x3rdpmRi9)qa|2qC1U#dSXy~)s^=Jm z1!D8X4a>Bis}M#J=A*dgg(iBHMd}rcdNM%lVJn`Q3y@L52&7lvK$v0)M(#*gj^(nZ z%AVo`$e$F|AQ>Fsy4dl_C1&ekSvgwYn(iF20 za9R^XOcC$|Xbv<GG5#Zu3hEJGPdm}?OhaO}(lBN+!xOOAus?xL~1V@qXRUGBj zNfDX&6i&0b@yL7EuA$oU-Y%RJYuKGDu|fi^xp}-*v_*|~{5>`LrBnjXP6Dz)jW<76 zQsZUpmNcy@d9OTyVM^;9!$$8^jr`0u-2zYuqBU#x<7%Z27(4ZlOSyHwRWr7Sm%eT)m_Bts2WZI zg28UQH)`N8YSwqJcN<{yLZCc&96Fls9x)PnL-+wy&b@PUO?RcKFcXL=R#`YPO11(Fqr_wNqhUY)fDB-It0R?jMU6e=V^?Y(o|= zjPZ3frytr)yP$Sj7T2e#C4npNWpB zklVp3T;=u$5l@IlVW_S=s>0d$@2uI-C-2IuFc~MO5-&AX4HyKDCKQI`=o!lF&0mH7 zKfGk82g693kYxiA(O@FH2uoauht`LPn~_4)LC`cDx;YlpD+Y~hsv zvDX5`Ny0IX6d8uGQ51+{9g%jnocGuIDCa3PbGA?3=a8i-Sbg&|^PLS$#jC^Lx&x&O z4iN`kFK==FfE|Lt%k;bacpy%v!>1=kbimQmuCRk5#xG#q@;FX9uOp8eNOX;P8tW2i zy?i1yT3ayb7+ELn%~7gkQY=}d^nn=Dgh)nw-Xoi9hZ|%e2B8|LWlf; zc97b%%#;@3&RPVql~R1hL9up7fLTIC#T(H5w~&L%yVE^hxXbIY3?*3WGG zoE1K6zS~|=z`FM+SPo}UGNXF*)u~?&ZNQ+0pmmBuAK4mNw;RU_8VyN**&u#koYWt>ykiqc zHNQ=5vAXjue77$^hlmapxpX(VV)MiUVcpddKoRZoJ6@~5cV64((~|K0a%*U7-hZU= zzwGF%IRr%MHMoq^cDVjr7-jNY#)_abO$Jat9O&Zs9m*UinK!*?HISzuxYy7xLM#L< zA00}vB86OwHrg&~O@MCH`Q&fTzz1N7$m%SLtMCv+YEEoE6N#PznZz-T$enlP=GuqM z%j&poZRFF>%zDEH-E9yM;yx;;ij~$=|4Yx#mZ^XFqb}=~sYY z?mJndcIRogm-QYZS)Ssu&Yd<0P{>8+P20$kpMYs!%9o&Fm3vTS%4PAYlku`hXqV+I zijdn?sbG-f^=Jhg_O~o`%Rw~cz1kWYcg%H)p@-qiSvDc6#RHYqLAsv)+-MdOvQ`M>|wQ5S% zP06Y$SvS=$ATFHEHhOu~ZRVT_4-}X14Jk;@ccjHKaxam0vnXgkP?cRI%NnlA#A8nd zVF8L!-cv4!1jP(%hlY$M7WK0NBV+}ote{A0<*TgbX|jS+R#3|3*r~a@lLbn(f>JH> zy|b{XEKts>Gm&L`;4Ex9oAsS)LpdAE7@&OX16)T`%R0ift7AQQ(yUd(Lbl=m3=Piq>f#b0$VB+`ebSnx3Xlq4$ARB1?VtUYKN^~%aedr1-zHnOnWYAmxeuiF%*|jowv+?(r9JKso*N?9s(=J%c z-b9avyeIeZ5S{>He;!|m`Cb^Cds_Pji(1dQ-{RIfMKVa)t_JZV`9)_=g@*Y_E=hko zW9__Q)T?0{k>|S_4`bAZX=xdZHX2J{+l8A%D2*=%(iVkqh)4uAT4TKy9MWFlY=OZ$`>W_`?_1q!ZL1q3HZ z?Nb|oM%e}SgcgBDDH{B-<>H5S)K%CvNkae&1MY1M9T>@>sq=X@PZdQd6iagiXgQ(r z+f{{x3^6AjD+$FSsIflujMu4=Zm;UkMVie{6~J|3+i(%T5X3?3S{=$9f>~Mza9E zt$>NU3?Lfo#6#OZ70lmL!LBBmBogso1-*o_GA)t!M*=A@9jX~1wLmcIiQ!YkvJ@z> ziV_qoR}s>_8I+QxeROF^#Ec44rF`05!ha}3S-DHqQ5rm7e@CYjywrN~y8RJa;9V%GyQhX+pXd7lJ|$(~0O&kv3) z=(uC&Vm5JMpA_K}iUuo((ZW=hEAtrqyS9*?nL6mtzv`0Tt;C@-DOPM*X-OQwmQ_pO=oBogO6|IL&;>+kb%3O5lCChtus>FHBpx}} zs4m{%8}8<;JP@Qx4-y0rX(93F`LPHVl=9oQESB%~0%-~>iUAAXf@+u)LFZIF0b1c? zu!Tbsz0gtBFAo#Nm_s}|KyqHWD4f@=-?X`QSQNmQ6q_L>8bP0Zx;&{AK94wNIS*w$ z18ekc|A=E)Wzf6~}ejz{tk*dZWW7M2&Su z>u5EUprc*|Ji#$SEBN%2xR2`EMgo)dE=0%^{0Vv1AIJ+D5baUh5R-PbW+YY1=Twb# z%^J<>{R|6iLGf=1+a8-K*CYl7(=1$dsySnYlm&0+}tOM@q={%>Mf-#P` zwcJg}JDxpNG#ej8C}BM&f5SL1Q6MnjcaBAJRv*+L|Z5P>r(Vrm}QjLH)# zNdyFrQbp^#`{nO2+{6xVYv#^j{q@}&%^$l(^TUJ118vmGk=Dut<0UTk9B3ODOZTcR z=28|_BlU(#oQa9#4k}i*-^-@RN;csF%BU$G$b!=JDOL`GRgpI*&MHTv!Et%KR1$34 z+=#(9viG?$Co{@2K&w{vQkKVfq-i~~)~m7?8&qbs(ayNSgnZgUr#SMGERv!q8YUNZ z_Xj*tXe1#L>Yz}?J>B`v{j2SpHZ12Hv6_sO9n6l>WWh$@Ypd=g3YYV) z{LIc*-&{XyuRUeO0`h;+y2_7RNxU#FoE#&oRIWWJ8YCVOdLgQbN+Qh?bDa`s;?*+` zgm%KMMUit>9E~GqO;t4xYv-_XSoi#!-piReWTlo9VPU?M5+!qv-v?DqM`ozXP7dm} zW?3D>?ZMtlkJe9tHrj@}ftZfqE+KtKYorcX>J2-MDO#WfEP67mrWwOZMOK~~2rp;@ z7PMO~5f-;r0~yyHQyEHmKARGuGd^oPgUa+lWv9?i$PIPLG&HQJY4EanM9BzEVRib*Hj^@(SKsG55j zwV@I*bv8w1n*?`xFguBrEr68JJ*Y5wPpVMTb(h|>w(r%_lNF`C$v|5EMw`Q`h><9J z-R~tO5?W(L9x@-Vmp(mTBXOxBp$fXY2$W-kfWjsxQ8sdj#Jab;<@crKcr6+bRpf`E z%>%ir@U34dR3wTXvI9sK%i7A$#`jAp@i9h#azzOCmbyo|4(&W7mE0+QDcQXdc85{LvUV$RaE)fh$#C+Z7P+O##FoKvVz(;{cI|CCEv> zRACZU0DzoWqA88}MvJaxfEmc?y1r0jZb(<%@*7mmBV1hhaH6VxDOOSKBAF88(=3Mdf zBIG!-`h^z21g@ZpiPGI}kQjx!7bpdUX?CWG^8rcH{hoO4u4vp<3Isqd1Hf)@weI5z0UUP)d^dI% zmV>pLr)x}P51qtfqqiU6wtz03oC9?ihAyaCwFGr$ zqQVWJ?gpR<`g2aPnm34oTDSpt?`VoWwQ*;+c9rFV|A5lrM=$V6P!0|a&eixBtwZuc zhpPaRa{->Vl-!i|cn^;exOvR*BWfC{h1|`Ayzr-jgesQMLM}ooP)pUCC7Q+50U@;n zPtTx3DBgNmooXq>NiAs?6I91OcyK}Nu|a-Pz5{YOfF^=G8Wl(-elKK30Wv{u@h6sN zN5xqmt0NEAte!OFdHJMqu$yf*knX&j_OJdPK1bjz#i8#A&0kyhwQeXyEQK&HtoO== zimeP~8&9Qyh78t@rH>X>(f{wr2VtFhnp8n3p`t%O=Yz1l0P@LD0>LW1qCb;bhG`^(0TmBB4L-S%P@#f4&kcKxoL z92;yKExxkFTP^M*o^3|VmpKi;*2*cjhCKh3Ua@p7Z_JGulB4E_|A<^zR%X|eJi}`y=|ss zuM#%Pz+5Y^`;%50AIH1nqmcEyL*-pR9Y*0hD~HejwM#g}SkS4i~?NnUR_yQaAoblf1$;>hOEU)<%(}7t~_2Y$$U^3 zAIzoqe@BNp?+3dUJp>I|lwbk6EmYOz2az6YkaOopVuGJ{dBVfNA=V$-Jl_frEL+s4 zN~K9#H^!Oj`pyl|n2qmi&@?g;F?cJYs}Q_wz!+ar2e!J zXD-a^+Piua#{Ia;*o}K&CmQe#FbeoMA_XkZDOmRoIX_Nudyj-;;-0kE+wu5U{v+|i z?HzIQAS&YK2ThZX&jO>~DjF!rG(~ou_%M9;nOMrlqffEiPhKyU zhb@AZh^zImJtk}XWEA1rJxFXiL~fg zAB8#2d)~v3Q7V?&1eXf_8`1Z z-GduY(nPKaGO{%hD^i?-!9N3u!C6Xxz|J{(x081yPmu*@;~!Y6lXhlZxfvt_WT(f^ zEA6AH`6yK+pMrC{vd04V(UhAtfPj}x1s={YfPWkcM zL<=cofDGwh3s*F6uFaw*xH2>$;+rQ^u={)gc?%5i9CG@yTYAqO?df z(IZp?deEwzK`YS_wGJiV5L{(KTc0c7iOAw|rN%T1LeC$$ZT1jcq8b`zH?FcfdiWBE zP_kZquYPdxI^1JT-DMk`px=ElBk$@KqTkFgaxNW;4=kPPmS6|pz5cczwNIfT?X>22 zjLgQPoUn>(z!t6!Z%@dM@SbJNdo(0!-NxoR>(-raS>tM4XXC^0zUoK$*2h;O0k=Q~ ziBzi6Z@11|va595HOahNf=$&l?t7o#$F(Y-uDT^w%C)eBX~~U#}O+-@+#frbWdw*BW=DM5v4(z(h6gQCVl)IonGnKkOObR;=S zNm+*-+PUV6?Cj^kpC2A8$%5=m96gu-?QZb3$O8M(Uk_Gng#Br}?gODw=8R8<&=cu- z%<}`i0oOnVaOzI0k{L;R?O7JGBB(SW(Nf7Gc{$%8ne~#SrV?m*@nMH!^k2YOjE6@^ zCOH>}`6SnO!w#taX&xMEcEAPC|LsqlwS_$g81D7Zg2n|NSI`iU7(BH^z^~|*8PO1L zzEjizHF9#fPYD)*c!^#N##ebBf&@~HC|171Al#7{@LGg;l#5lV8(T>xni5HmA$Z7? z;_y|3J%)O7g*|zfx==i~Y_YZ_q3SgkVm0ayeDc%0p`#s^)-iozwBQA}Bws#`P4reV ztQV4=_bKBz0QuO`i?^@9E#m=ry%&sIsGvtT&vkFFMf`I1Y>YJ}#_He##la^uVb6Ut zGZ4b&s3Ki8jKYHSQRtEK!k#N`$Q8fTfWewl68Ro54`K>s(G*AbJ61bj@f6sUT3}g4 z`YxKT>Xz%>+%g#ur^RXJ~M>BNW(NNC>WTUm4m+ zi+^ZQM0*T9aP=(38u48{B|V1Gva1Y$Fx>%Sx9L6B^yNV`!uLc`0#%qGiKM<@tZzQ( zc;hgbd3za_I5-tS@69oy1i1r2R{h9!s3C4sVJ!gpuvdkd)0s3ds0SsGrYpcPDy(3C z{uSZE1K+eFJcghi6zPCP#;TH&9sqmpjxpY_=Y!~3Rsl=oBky85lb%`Q;K6hvPiIW~ z2#QUzmK{>!qn^&TaZtvPd!!^yXB_Fl?A+5?JQ0#?ynN;&N!^(v8K{JV@`MXKBtKme zt^nVIGM;WH&7beqf#LwArWETwTs9&6PrMW}EcLRb~h zMm#{0=F(xe?=y#=9CY+MhdPBIFa3*g)ORq|9P>AYb{}F*wZ(A+et8|1BMV2sF*A*) z5$JKGtU6SNHbdxvPu>yxz2^>nF|+?Cg!E%o3|4S6*OJR$0mk=>Mz`Y(E!bTzAB$`C zAl^MD$qa?IG(>1RrrVqokeU$dT3V)d;X9~R}Lvy3_zA^U7<+BGj~}Q zocFOFfVcE8pO&VAvqzw|0Y!KnfW!$sgDHz*iYQ079S4Wua9RU&=l^!M_8x?XVWW@~ z=u&;OfXN^HAi>5MvZDk$3V_g{&mnB}2+#}~$O>;dYe{|rk@J?s5lGLIl9q(SkAea= zfYwKKz5E~nLG+;?c=BeS6PaZKeMklTT$S(q@Y`KZ==PBkeDHo%FEMbZjTn&LYTRu&1qv?sB2Hzed!A|YfszD&TDOCDrhcuY!nqLMhN5+^FZCskLrq}@3h zxzVaE_8ZiK>z!={`xsC9H-|>!z3CSf#QE; z(*yumG+83iw^;_5;A7a3@WXsb9Tr20!FchHVV1Ob$L6C>&Dy~(yb~-6ottC~M_hYB z3iI4omO&M4vHsSa!KmS@zb;Vp={khsia7Ak6;|VaWHntIfGa{VK~N5IHDvQd32hEO za`7yWW;d>=Pi}h~{=ujh9jd1SU!Vf}C%LDuQ-Z>% z%5@{WQrCqr0;#Kfr0TlY6NSA%FHP5B1$G3_6-XWeK1B~r{$zsGuKO@jsT4~;O;RTI zh-*(;{<2ARB@H?CSup`9SDXidqyyhp0(3>(s0dJk5Y61L!&+N;RC$omh^jOft@j9X zvDh8_{{5?e0smk~ELuYMlx6tl` z6V61phyM(84gZ=&nNr%XQ7ZPeSCgW}hV&xiWfZ{{ zv`@r&*hjp&#f+!{&j@q1<)ln)c<5r}eXIaV&5uI8^2)2e`=3lda=!evbDmm0C7CV} zD##U$dbk`QXOqkLupMoC@B$EsWE3 zmu6tQIkPi!%)>HRr?ndU;$uX5@ZDkCOT(wV=-Pds6gD0a-{T2z(DoV$vrE?z(+Y9D zsQc3DaCQBc_x{WIPpp6AOS&7b`PliddfgA-_8Vva%06g(}#cX z8{hNRAG`b3A9~#bKk=LY&Hb1D?6n{MUr#-K@A`Fb{ou;4ecP2^_^xw4^|4p~$M^it z*L~BE|HkKEao!Jn_SoP1&@X-KzrOps-t#+u{WbsifBD@%{kkXq*@4An54~&i_wIeo zZ9jGPKe&A7jbHke^MCGLpTFTNAO6%;KltYNe&+lB=3~G2^Dp_g|Hr2efBS*=y?gd; zSAFzde>8jRpZ>xZ{`#9f_rLw^r!V}Lm;XP%+MD%uiSJY&SX*0JTRX@S3tg>t7r$ZO z58e6D!S1>jExzZ=TL-WD<$v=FKlY;Ux$VO4yFYlrp{fU6fBveD_=^|b^M<-IT=s_5`DJhH4;;Pws?8tWJn+tI>vtSD`YZF5za^Ll z-ha`?tb5T7f8)K^yx}*#@n2o=^B;NVEDh`3)*C*0#dmyQ^W5&+zw{G3_bw3R_y5xD z{DJ)af9=3kJ;c5||HJi&f3XAp#03XdzU}OddT#gHdv|{pV}EYr0>;KyydiiISzyJK#kX`%r-~WrBRQCUT|5dE2H$U>*2j{Q) z$M=8Fb(aM2f48~XU2xM`Z$JOVN6+qF{<^<<{4Y{)@k8egulve(z45?s?Qd?-_&2cG z{G0#n{onWfo6-7PR`v~7{PQj0{lo>}z4Y>{?tI6A;V=Ey*HU)fcfM%tg5j-KeDvO5 z+}|G*UU=5*E#G^|cfRWA|M>MExZ>p>`Np5T;urqu%Rm2fJOBFHFMQ?b zsqffWd&&BDet7NgebaYc__4Fz^jAOju@C;uANbyXc=`kH{(K z{P=hO?tA|4&wXLhzvBbneE#2g=YROSSO3&!Zhq?ZAO3@{`@tXh`#=9%zxLxtZ~p$5 zx84!avX88uwRSGQdwFJvx(&YbzJLEm-ySs|U47+eyPslXsDI27Z-4sjPrd!=H-F{L zkG=U+{v^M7@etp?+U7lxv(LZu@na0FdDLZhR4TE2(1N7=`_gl#kfptUyJ2{rJ_LKg zE&c3jh!hWmBp8D=lr!iu`jv&B^?HH2wf=?Mt!%w;9m|Oqq=y{OuA3cW)O2`yO2C@N zf0&M$U6X*>rgXOX!gXMO!FDW+U$}0G^ZA&0Am-v89+)*^ADduLYTW!Pb=;WNg!R1b z&i*QOYyAtiGd{S$eotNYg>M?rkCa4c6AV+33zB!_=n$O_QXZjdHX;DP#O57(Qmlzm zu~hE3Z}Gq!rtj|#G(W^?VPz}Njp~tw>|&JzB4U2aYd-S7@&gl!hrL)wA}q6+9NFbY z{6=_S)1@OGV*l));{I$zT8F(E2>4cst?qcU;Nm?6g{fCDVzzj2oW|N>{TiCzK^|2>b%b~?pF|Tup)STZ|j5tZf z2?WiG5j-hI9ydfRX;yLz(5683%2H6NJ<6Y|HFVl^Uw7(`)BgcgkXPf% z6}GsN8Mqb^ivdAQ*fw5X0NHCb#dGmA4ags~uY=A!XMR<02XSkc?=8N>aky);sw*{HS(*h)@h4T(WH5$Fg=z~BZak?CPIM+OPtt}#e4 zT9P^ll)+sSN*PVCuAvz2nj)0Z3CmGc0j<^)5E|adB#1x}Bm~;*W%4sJ>;jiyqwVB1KeXII$pDv$)L2R@0u-Z6uBPk*)SJG+t)l+DI&eNZV6I2L+gx zi7F#AmP+iB5wk2ag&}jGCQ5V~KV>kgtQysc3>D#RI0Up!ToR5FC%g@-E}Y>4P9tsJ zmW6C-OqyJD&8JS^L{YOMspQ5aH(5+4=CENs3qA%VE{W4XRQf&iNDgc!VjKDJj z3$EZ$ft!>zt%MAa#eo-cH0A&nATQ{yv0sKbst(2__#}L73Yxa^qB5;#gj=Wx%uPCl zBWPBSl&5x=aUYktL$x&F)`e4=QzM1GTWYUANncS5-$6sTrxaEhj74RAq(InGdo4&U zqBc*8Q`Zi~IW@RCGc`^Oo(OeOJCpzMFT`H4Wm$1VHEV2NRex)q&q5P zq|8%zp%%|f=A^7#-7Tti&croyZqG*OhqYN6*(~vn!ECYrwV(OK-2ec&{2MoE zOM`p@ouL~40ieN5BbEMi;H0t1r$OW34+-~C*}K9+3_SITqjU}3w-?T+HSWtmTQIbC z2bt>u*(WpJ0?0n;_w7okM6g#&k(t9JS#SeXZry`Q{dP@6ZUm0Ug`{v=t5NVb&`%|V z3OUyz!|fH01`Q^iNd(V@8L;)m7VrZ|Ks2X~54ZRQlGonxiC+eoJ7M6e0)zm3xV0K& z8o1CXfog>tR!^acP{P9Inf!DbXhMNNxl}}waM6#m3>TY&9Hrtf>*>F^>%hidD}+PP z^&=1nha2ci4VC{43wUy3uBT7Zu3H83kE)-{v@>1b{`6n|_N^{vwVNpv@^hgGif;A} zshZ5I#T(&taWv`+JGS79sf2pBy46tpjfSFI-MIGdkJI&bhh4t(@zm-f-MW+R;T50v z&FXm&KKrcOf9zLwwG8L-N&?fxyb+pBC-=pUe_RHg1$>I9c8 zhxVc*FE*E{4W-s3!%Wb_ns^2KJp_IJ`JW`Nk@0Y19 zr8cC8wQvDaD^B(5piXTmwGl#*+OO1#mEDIZVBK1#HkH~h6Rb3$;NPhmq?T^|?#oVJ zO+1Qe2zcm2F2+~_-XmEV5j9M@c&w70K%81!9CHs>F};P#M6B_5POKSRGoHqI&wSw4 zOfOJkPc74ohNpT4VR}>VrEOmTgOd+9j~_a}I{qu?yYl2+ja7|=;_+#*hBbE~Nl0TB zA~4+{M7Z;D1M0<^$m^Iu^@k)Q@S8;qp=<<+?k43hsu&S@$FNaAthr6G29l9jLMkra z!Xlqez_bd`LR_J?Sh`S<4hYr-F{GS_6VDYbBbjSOClD@?LYZ1W-?)}TvU=& zTR@~4!`jUxWCbvYLz#m_A%TU3-#Zm$SWQq;NF);TahK->_*Hq>X9ng;g2F?+Pq2k2 z;X?ru7?S&ZBzh8+#CxE_V}w@4nz3#f*Qds9| zXW68J+6k9<6w8iPEWmk-bBh&G?rLIJ6U(brUci;WBjH(Uc%93l%yR&75=qvhSxP6y z!isM-<)lRy`Lw&`{M?U=h=n_y$1$_&ap2iN9JW#WEpo~aj@QR49Z&fLFA7CO39zZq zR>ES#`D}G8!F01r!A2#P*C~_$i)Ua|9oUjte@=BA7|A}>twZO~4qjfM8mBOHYRF5p zM(MrEr|N9AAW*PokE1$n!i%Qtsp?+Q3(J0!;V>-HW-1<%NG@tj=-yPNumr+MkT}^>@cH8RD{;qhl18r z3XoDHWhq{?xDprgMBoa>(Os{+?8|I_*M5(UaI8iIPyb4=GE)RIz2nK?%kdS!ujHnF@(}>or0JF*LuM?1Rb``U+0^4rwX{tuE$r3mR-&pQ(S0LJ|J5z! z7%-ukpciWXU_6l#b+r@<52ivX!Lx~QpIs42|2sfQbyy5Fd&T8KK#xT*U%)Mv*~ ziGrTac3{p6(3=$tt9io6FM2X32K7Jr(BWV*joY)<$}4sH8ne-N*3l5WF<8q-CA4%Q zvmAE3j)N%APfR<;Gach_=!L-k!EwB%AixK0$JzKL6ls7X24Hbpq#Za+&B8})P4p=N zW$Ek|Ile4}J}0$#3k)d_Tp;L;nm7vsE}BGw7+i|0dzHGBgwwHECY^}G(z+9@u(uXo z`e}-Cd=N2mhudD4MrcjO^^Sc~e ze_~@GR**^wc+p%jQaOeNOi6LzyVzENB1h)j_iB(Jt^q_8}vkUD@lBsKgQ&Xf6 zN=&uAl55?J@K3$ z&lLVuCbCMr&hdoe#HL(vVW=f$xbnox!0i|#B(=lX2~p=}U+dNdM@9+~Nnu))_Er*L z5ieRS5&|QVt57V`<_rXt+|tbkGIBG+fLt~d?9^6`Oq1A#8U#%sRzw^u4N*;AKCAK( zN?AK7aN$ng&JtTvhEA%4GS<3!>qIQDK(OL8Z$N?h+2MDwJILwP@4;hs@sA$ksln- z$EzKapI1_Jx+3n$TMEdSYjsl97u;KM+lP{w`lN@iEUtR0nU{&x|78prCPT51F5VJ> z32p(47=<`LG}DVhRJ**ASA8F`?UF|`0&bfJDF_2s|n z^Wx`Lz0e6VN7vWC2BZp}LWp1MoL}ZqD&8yWykt>6du%cAuSUks#v3yifLt!ORe9vVzr`HtpqJaRU)-gmR2s#Q7pZxm}(aj*Ophb(Y^e29n{7w9-^`(;Q zcVBwusdWyKCjW&S(;*T&Dwaw$ek(2!i#g>{gkx8e&xoS(5ggf@Pnnr>CZphd9%dMD zvqT^+5`2ApAWJ_?PDLWk#>bCYA=z(Mcg#20d5-Hr142IbpcoTY#Zii1g(6}qrF@w; z6ukBniXTT)cZ(TVHmxpCO^+qOCWrBDegJZ-4y~b|u)?3OTC`=KiS<~X1*_F;bMEECy8ToiMqjoM zUub#&rpP5)M+-H!D(gH^4SLQvfXuPT^37~@Hb8i? zBApuJKo^k9$`vg&*6@YQK-etkfZx-zZ7M^}qh7G(`ei49Jr zk#->vVnEVu-=c<6p+0XjfDGlTn%l-SXvdXQ$4~7gDKmoxRFJb;g^^qIIzN{3;GXJI zvknYMS>gP8098dQw8Bd*mDE6fq%eM50G?G%p{uQRx8Xw=Qk2Xd%B=t;(emIj-+c)} z7`Z#rx;{h{!-*8oaVFWveo+cQ5?FJWg=_J58@x#Eom7NO93#d`)ki3PEit%DZa9J&4$*=H2A4qV3ajLfA^Io+$KuJ@z#}Z!roRDW&1H)8pJ&e`W z1IQ&k+(S};77q-TglZ3>@LXDTh9NXC32HN`0hVXKr0TJ}jmn>zVywtdcA$;#SbANYe4s==lm)?AI- z8N)g?ddLB-hVKZFP*A!^v>>g5Z3=Q)tF#r6o~9&~guZI4gaJxw{PH~xOSVPv^e6~P#-t)8 z>wu6>zXaF)*Pb#0PL&0spl$L1q|$nzpjSe|M$aY*5_OO1q|x94fl6xH!3{mWs2C+^ z=#iijU*n8I2DC|}&h3$sVzJuPCO@B8RFSF>!a7vCA!#5Uk%W|>+QybUOAeYN#f>eK z3sz!a51K9sR>D*?K@&kDK!gNtdtc=N6s&AvL5KKd*D0+>`KI&*&3^>H>4_N(q;G6f zgQC9q2kF^n&=3q?v}{TPX6oKdR9h1WaX*2Oo{f7#T2U1ev=z5X~ke z5Zt731L2sbk0dv>^3-z9v0ja0q`%;mpPjwivZ^eE9;3!tSjd{+`o?_oel^{9uC+H)=-K6Qhkq24sRKEA)nIPSbU*w;Nn zYk(&Xnp$-8rx&W}83pvw5afv*Xo4IH2_=&V+(k!8v_`N=O3g_Qu|6f)CKL~RO~^@I z@Rg%TXHgOQrY^1VB6v1YvT>9c1%soJUT)*D77dQjk~tEECR!RF2xz>dIY}Oyx^!|| zB|nBN;d*lpf1{|hClEl@aL)M^+wh^W-Ll-nIkw#yb8v&!0bmbmj2yPas)vjl32v1@ z3b!Ul7<>{O%SWis@spuB9C%B>Ob)l`ng$`*y@*#5L>XIDMFfxoq9CL#DHI`3QnF6f zZKfzHbT0^wtRR;eLE~4gqEOOOsE4!!YBEKjasFolMvX>#3dMz|-I&%i?Y8}6#+ys@ zKT!D)R-g;qg*F|c4pVOiEL+X!nY+9p8BnPG#7^dTHjSzBxSY`xNNAc|T!- z*c+RUOtC%uk_MA*oiC~*@hx**T9HE zpAatAPB@mbYLz9ieQT~lYP?^f(0+)!^poQnzWEO=o6E~9X{ta9tO|D3tWqU4}@ zJD}MWThS&;2h|b~NYRBSKRdfs5QyTQsbs%Qfx_)gp{1yvQgxYPwp2^P^rVoQOl8Xl zFTfpxc81YN0aKR)dAmsucet*_LzOMX`n9F@hJN3|G8~3zwJ3WU>M>~!)!>sYg-0z@ zJ8js*3WuBG*7-r?P#l2E)ahci%Uqwcrcf4Jgf>y8@h*FTto3BDP4!bHNHaG~1k3Jo z38p1!ZWcCz^YKIqg7Do^$kI}D|CYiJTPiJ6c{#`9no*02TWUVG844xoCJbUwv^Uu- zD2t%2RfM`s4a=1L#{m&r3Z=DFU8X=EWipXdp|SJvx*slMgx&9LiSY}QzGugpx_QPP zYzq4(WiJ;t-F9oYc+rGlby7L6k_>Lvo%>vzuiV2qHN0y|)D4z1H$qY zWVmJ|4P7EFfR?NzbCk+JDUxc)@MQ0x;e3?dia23V8rl`#B1vl~M$*SJCG?+(a;RIA zR-4VVEpNwI(CVj+sRrOlPNT}8XmeC(w(GtP6IX+HuK~#x`*5cgr4B3k<_Qi znx;7SF0J2Ew``}^kQxNVOK0o4&rJl+^g+G+A=F4u2z#Nbu^m;1UOzukXA*hy#FXx( zPjqzqvvTd6fEb$blAkaaXoIpYjDntO*r;A8}Y|w(LMOJAI5bZu?8GYYc{E?JJK_bxyIYq2+X+zS1q;)}tCZVEm)D!?h1VshQ zocEGZ>{28qfJ{Nj!Kok_Nz#`6g1bIDJJhr@=L}xjZYkz9rU5+~xkWN4wE{ zr$cM2ka2WU+DakC__$P~hcu{a&k2_um1%8{uJr8IKwG{YCc7WPU2rO`M~fakVfbdeIe zNC{n}gf3D-7b&5OlwDc)jLv07=akVoWpqv%ol{2V6sAGJ!eSjO1v-k9@)+z?EJalo z`wOL#cyeu^Q(0M-jpALkd?MT9hBk$gQDsjoQ<%0u5ZQbS8UxJ(_9;IwT|k0{j! zEmGK1L`X42w^W-3C}XS^5mFj;dZ+qjN*+F_4CcHfHwI5K-h+6bgly^;$mEnkT57VJ zXC0TBT%<&9N)0WQU?|E&E>a>gr6wQJfE#5Z7by{$Qj;e_u5V?KTc(DVf?P`>Q%gZ^ znVKdw$h9(5F|9;soNY8zGp&LdE~f=(8K)JmzORZF32A(^rD$><{q$ueFieZDX)!hJ z<)*dGEv?zM{h*s2vuAXx|Jmkpm~s5gh{lUg-Z}fx)3@fI7`F|w3XUV~g}ON}*g?wRc>S08 zH_%cCtlMKUcxL3xyU7fcQxG~~a6QUSRaY86Sa= zz&XoI2-*vrKLqt#2%L+WkU)^i#YHYXxL7Bk%VOQ!pjZY1vvjDKOjA{=%COC9ONbhxK3_OACN3s$d3d%igq#e;B3Y0=MhgrKoHzf zoLEvViz{3OxB48o7AxBlau=?GTZq##xQ%Dzf?Ixm01$J_m6kJ{Vxbb+2O$qmj6|4) zT0nT*A98>I*G@=1&g%UUYCTe=Q7aW}jPc};$JK&>7@#4@p5eC;M}-6lAOwOxHrnl^ zyTBod&<LJc1@GAY{lMbTre zw06SGN>53IMEX{vmoBonmQ#B9X*Xn$3*&g*W^)u3fvS427AoemresE;rdH9he~XS$ zdC<4{rCFmg9ihT30}2O~#{ICD=-5J{V^pGJRAjkXCQpiu$u{&w$EZZdsAR!FB|2ej z=maY01S*Z_feI1L6%x>M{a`F~0u`hK6{KsRf=-}<&Ixr{X@4hBA|85qx+R~JgUnYM^F^6c!-L?VV;eaQA0&(Y$w2= zZF2?-4e5=Laoy@v3C6@)z4%ny!P>m87N5~1SdK0rZpMZ{{EtBrw1nsqlCL#2@F*pj zWtA%#5XLUa6^4MQ5;h)eEr+awGtK7d0JRhNMzfI@Aa71{L+(xVbVP!ztV zw0cJl9fm(um7XL7na^OfdIZeflz*|F^jy-zF=y;Yn&tCfgE-pzhg=-@1IaN?%X<2Vkxqe z0=_5V;Cqr8DVBS1%9gC7L>f4tSFhQ~D4q}&by<&r)@KYvP{*`XDP)A42Z$r(2_y1i z$DU*sqp`N0k7`s@KxMV@xyBHgD52DCh!mtt+9;Tb>}04ilGb*B1e?j_v?COy2PcJi zQka~1;ZkFdcH}1o?A>8gl^PnpI05k-iRFo%_U#c+ZL4b?MqbrILj*&mm9$kN$dh%+ zPGo(O?Qrm|2g0jZU2kKKm~70CJ8hWYRrpqv+Y4=7V#pcPE>zk=n+%_iqoogIs<~@S1o#3laAxOuYBqcJ}urSza^QLZeW^K)y>HUCxdS%gW>Rx zFmY9Rvu&?*5tHGZ$w}*Ivc5nH7Dp&y0msmhu9N#yKykJ@eZ>VRKx2a%asix{o|wgZ zrQgKhtd=QktdVZ=-HZbjdlQga`&DoRWN-;``Rm|fRfjD_4t%|fIhkNkags9lizGwm zaxerm2O}V4;vE8HeY|%$7_N^$aclzFJMRa4XS>lM{p7KR9Cm$PVmxV@6s7FPwkMGJ zc>f(!TJO6pf+*}R2SYfSq<~Ne$D<7NE6Y67LYre2StC^mXAN=Z4J4sB#40*uk>}|q zxS)C&X#k%GLyRQN+o=k>7T6eJ%SM;M$j|Ww5M)}@d_)bn6*T1xDuF%)0MZgTz)5l) zgr$CXu?Uv++%x^m%;`JWQry*F#&33YN2*V zreq%;ia^Z%W=&_RS$dQT@Pb~cq$8WElq}jr%hO{8GHnAy?6qQrKzK+plXWre%qeWh z=`pPhj(0|zmj)d<)pO|JMy(A!yfGyI2|#uIK#t7t)I&NUgUu&_hcGIsDu;1cKJEdI z2@w8UEvXzyQkYwTR0EX0qO6k2PAVnRal&ODlO+<5-T?%US?rlddrk;5O78-M?*WX; zdZY?r3hE3%_ay@wWk{{+0917Vy4ry5tpTX&0917Vx;g+=9e}D1Kvg#*$pcat79rYD zhCSL4sOlr(HAvQwGlRAE^Oa-oQ8PH#_(r#fJl`oWt*C^t+#+|a;h!|l3^->MC(E{2q=0DMZNWrlyE8sLE0dPROfkq)YfBq9~M z65M=QW_8;HNo8*9R8s(DRV@tHPpPn(umo8#P*rJr^iHAR0F(9uOtnK)(jpS@(kd}m zZDmXC=olqr+Er2koT_g+b*CpiEAPUU7<|u!ZnM1924%NQAcQ zlnRcqK+|ViL0xe2r}u6=k34YDf?nT>Zv0|W;fB1y0s4XK&HRPmK13?X3VzQk3;F66 zmm($Tose*OeZ}r;L3hF3uRMLI1dCtuEw#OyU|;pln@>03qfAdwtdD=x{35p#34}Us zQ^9P!{-fb~*+b*aAocv#8<%!xRBAmBYmfFyT!Z-)dbk0GBB9A6%XQ=hSZq*2>n%@a zdk-c~7KW3srrLyM&`c|mAhy*oSzol0ihx#kX&q7Up-_x(*Az?c4;P=@;ij0uX`v6G zPU$>7wrAT<%~0Jm$iv1owrgPX`cY)jh@C)bEtE}1eD(GcO3~~zKTxb1!J?dLsUnpN zkBf!azC^C*pm!=Bly!i+X_%Cy8hOY-D#(jQBd;P=Dde%+nm|NjY3HGNZA6VGNcjDl z;MO#PElb`&T#~J0_~$|105R!cF%%Lk`Wnv%t8%kR5hUCu7!4MKe;qSVVp)nn<)vs- zLXmLAx-nagH?tM|7*J%^q;`Z2+}2z}VzvUeYmKA_61+_Zp~+CNPx0;bs7%|i>KDV5 zZsgsn>0L+k4GGn~pxVRTy<5VT$|n$k3#5a-kLxQjLH8t@Kkq#_Yl*Ca4TId{mI6<4 zYedQED^@P{xx7-a{%~_I32EHZqwpfX)^ni`4McjlU1>!ZMB1!uMq1!{09`PHqV&oS z%yx5VXbd0XOx14at*rz;9-t*So`xjGi5>(xk2iQ4O=$W2R-3-ZCqvO5QGg#8lf$^V zKK^LxDfmaXfo?o$Ptjx9m1g|*v3LhpfS0GuRNmca`M5KMXIMS_exk6_Hk#)ht3Hiu zEx*WOnzqexx_M$~r5a`eoTEj7Q|EF%6)Ng-QKK!4vBK8gSBm>G?hR%xamoa^ z+{WPAy$G9j04{ei=}lA9%_yizZ2`wpw=yW8UNyG^%2jGK2Ug&sq(4X*e56d^U=tR( zv#Ci$iiJ&mrrn@gHUX8u!L(^OV4Vk4&3*5Q=5hs>YtLPs6!?@D1%X3c%$cyLVMBo^ zDR5x}i-`-Si73Q^k=FDlY@#S^)ES$af=zWveg}9H(bxnI;YoVc*#>|c8*Rh{sD!9j zMreQ$7SJ;0S2q_HF>0m?GsNHlaS$_*Ff$?}W~ekXWQ>M3!lLFzlfzG-W@fmU8NiKA zw>bL%hkeNw*b=iCS-_1A*^F&HoD}SbU`jlThYms9EI#&2o^4GfT5mUL^&`M!_0zS3 z;uKwj9)m<1&I=7cj426$d)Q1(uifz5(b6|R+zb|v)5oNt__=A~^|+%PKcOqQ(P$Ww z`i_Z*yqnM4V8gIbDUIa^gO^qy%4_}U!EBj_DGhF|ofitq7juVSR5DVvxzQ9#c+p+A z&2E}@9)L_xNyA7L1nr^aWNb7C6>8IzgAp}p$qcEMlu*iwVF(5j-fBe>0!9r01jIEL zpUX!w*tBZQQ!ILoF_La2jvyd~dGT%nku-rw1|P;4y4Ief=|RaRzZyp?mzV(N(ni`A zAz7#03L4o{RSg2N$q)pTyr;E74ae=RFsXg1DordCR#El)r=M35B^69OfN z1~7RBS&}``CVwCvxO$qikEl#EgjWGrB@F-%E|dD4)C3N|SfhBpmrQ%fvM0sJ)HoOx zeNIVKHfe;S(!@lcEh&Arr1aSoogmuSQR|je6xxx2+tx=0Ysm!pW*?!9Eu8BjX@f=5 z1`D&B)3BxKI2mZ{LQ!SE5L@;F>9BW_f?!E?fg5{QY!kx^$)*Z%S3<>^!4{m2yDvJ~&wgNXCK^sykh-zaA>Y&hbkL`v7e8=5imxZHzfR%O+oP(9KN0u$TKOeDuCIVTyQFwy9`^9DCgP6G&r zYIJ3TGm?!3Ibx$L@y|#OkXYT~(zaVSlWZF`oeZFgf$QujmpCur_frYUtnE`W7KojX zE4JX-;SV&(I1GXjo{86`fJ<+m`pp?!{uhInNqt`%_U8kiw7yi?vWKeUS{m%sG>e>3 zvZvwa1#dRl17BL<&jCJ6%uE(vGV{FHzb5d>yUOI9(@=)}CsEJ9{U`#maq{!{&z2o@yDYdijy`T96Pj8QZLdo{n?F0DL4Eo1* zd8g!*eye1)?C^qH?Vh(%tMcvmZHVFQyKd`#CX4ODC4RCXsegP#8unUuOA>pLyeYu_ zS|9UE2)+7S&pNVHAVJA*sVrC+s7?GNhuZLK1r7PimOd505|<|auCf4oeY{~)+k^f3 z$p%J2{cgjAd}V7w&T3W21=tI4Qw*`LXvkShG~_gC$Y~mdbvJ5xCb!^%IqRWnZ7x&*PT9wXg5+KToB$sgttL{l44( z#h;p^Zng=2G}9BImMtRGaiyYxm492Zw}pQGvb612={aj)xkpal+3Uo(1&>WJl9wv& zdW%CvIkh5<=EY1A|9k#qwW6iyOzI?OXgyF;$qhm~AJ^IrPQE~iSWU4d$_sCC((db} zT|N&RW;-HoXmsHle*Evh4A+dXJ0-@&zO%pXx?e`t;^RE#A>`j^yL!-P6t%k{FN7pU zkeSNRrBfR({kT8bOFIRoCAkq=m!_}}u{?uFGZXqF3@z5$O+m{!hbit`zS6FeW{U~E z1fa~I!NKIXWRXp1G~_!Gb4=OYC}M-0zkwrL>X(d|m~K=Ao4w;?CdFn|emu?ky9-OuV+3O#*>u+Z^*;iDPC;#b``t%a{ueBoicuBHm%O$W*YJ73=gT zVs20=okzEy*y)VTR&%_BTFt%yud9u=na14?F4x zmB6MCW~SY{gp_8MUT;FkYJ3&h#SOVm3{_lqvS{k5I~iL?_i)C-un4JMtf3W4M#KVG zV(Acv!w$XQ!g2lSk${y>Dn=(+SrqE5zW%MOj_Rn@p@_104cQ)rg2Jaw)2!DyU4L9)@UbBtdh-3W^BZN z>1nW{xCkNLCwlhC@K&A2YY1h?s-6uVu1Q^Fee#=2E#42)y-+8_3 zWse@{v>RmfZumfcq!UsO4_RczmBg0HA#bKZTXgoN=Q=nd<4>X&i`<7Mrg2U_t{{^V zXo)&x8N?2KDy|S9wzE-Bt)#FMU31Clmu)GJ?w%Fz_A1tR4RCL%AtYsGRF3eVLYIR$ zTO^%$LJ6!ylHCl@SXmreS)3}^A32kAawxP1jaETO;Nb7#c905<{Wn{;Cy_{u^x4%mg;TCnyZyxAOBI9DSp+69&GS<1RvUQ zD-g4Y1!x`?O_tADtuykX9T>N#rE!s{CW~0AMLX(Ty7wDnHfarxeNv2W3K480nuJqJ z`l)7Y4X6XmGW=jQFnMA|S$484(=Del!qpJTZVY4mSipm1X7SnA`XDw`ZrQnfLw|dN15zGRXRn3)isiq3#RKn-~iAs{#d1O&xOUA4YLNCuKE zBrypJ_?Y3LP-F#LvA)4VtM=EbRNHOswv0m8ZXaqNyKUXwIxAT1YAx;BE>+Cz|9|ei z$v0ny?f!myVdmU(&$<75?z!*#O=hOj9@r*>EzOn$n0KTD`UFa1|HMd_DsI!g8G}&R zLL*)GebfvZ10y{JbX3ZY^f=2+VFF-V$I&UWpcH37Q+9CjdjV;jULZ@b5>jlbJHWpo zwTS0xgr@YuX=eyth@@FljTXi9f?fgJcrgQ?O0NO?BHJyhEe4B?fHX)Nb%z6Fe?ULb z83=5q9KQsV1a`5la>iHK{)m`6?i8}bPq1!qONPZtEAd>F`x7dIkUO3wksl8SjsHcD zq0|Yfz5T>{9BXh|I#5dc409J*Og32-lTHC1BNrvmm<*haU_WP^5j(+(ouVmHU5$*` zNj&66-82O()sc!o=crK40mtsma4u!K-J+eVS@tcdF4u(&`Vs)R^J1}>1ZWgINOFST z8V0X$mxQn>_clou(rMc|zCn92{gcG|QzT)02YHsM zAE#(`2^NDiXiERx$X{b$*2*W`ngi-q}G+XXq1kwRvKkQpIlMhLedBZNnpk>A-* zg8I??5|A{m9^&W?U^&1tc^6QuSh-rjV%+GL=H;Qpi;NXDWqAr4XqUGL=H4 zQixOvkt#x@QixOvkt)Kdp8AkVAyP%i3tVt^q630-Nnb}C=$8G5PLADQB|o1RCrX@~ ztc5I)4%(!!D3z!W(S=DBsLqcf{#3dJajl2j?H#B1!yg#=f+K{i#dwxS1P_ z+YiBpzm`FNfKjKe@YXlaxYpp_UZ1B~c#B(Tby46~pVWI$1zSb@4z z4VNVkvfIU>i~dbl>V78^T%37z$IGBsrhtKxwt;X-CW}4YQ4o9Z$L8-NvU<6OI7$T6 zf;li`VP*yhr@joyuquaHeJsUMu{d`kM>h?*43R%>M)J?3p7v*6qI#^NGOwCuka}XT zl+vvr-zx%Jj!HJR7RtodUkYKP(Jd)#9I`a!Me$Y&b1ZV>Y7z|rDY_BFs0XSC$FO>s z`DC&}jP1#QCi^{UT3?Ewlb#S(Uy7W7W7#+;o0lTIsz|43M4U(9G%SSUV47X1{d6=9 zWC+)eWfKl=#MzK&e_5H~aI^(&l;xWRX3R!h&*s=7>5Vx4a7cO=w#rhI-?Nf1Dt97^ zl8{lhw}6#hFW~4AsK@~q?n$wc;^-uFbJU!F!{#(?cT7?9cbkK)w9B;8UZGJlXe^D} zjl4c(bL*A?e6Byv(lA`u9B7YibOuIEltV6sO(4WDU7mENc*bOF@sv$Z=zA;F07(q# zDBln1(=~nuM#d0&55@f04aJ9%GX*vZV6bVl7u0~jhSF=e++T=nUCqOW)CVw;_GE#x8=80;muf45%QJNwRE9*r25Ls62ZP zoK2rV3GI%M5lh8jWbsN= zr@|WO(l{1N?KBA{gA&r5{>jrQCK6%w5i_nAcZ_^OmFNuze-n`fAdC1JLkY-Sl)%Dq zDM)jB^06DrjiCzt zX_zSkhxT%V3_EBUN(h~0ujl!_Psof+DSGx)tX@~$+`FQjvP1u9F3Z*zKXWq(2$U6v zCqec?7vyD>4d?RA0MB3tnvLSbokGnp++iyeWe&#XNP09@Y$k5uWX=<1mi-4^l|rtU zDG*ee%X1VpinCvY-`wt)8{d?^LWI|&(iftD2{S6bCgqZO#p)o(Pqa1}DI_~D)VFq*>92hNd?0zli^3LWtrthRhO= zW0o6;%fT4-phjF;QI5n@Sk@VT1L>%(j-x~!*I(X(IR5K66ePY2IsFP=q4{5UPfA3tNthG(3QgBeFH5$|UQP6J3jCCysl#U&|&G(2p@-X(*~v@&kv zs39wq=8s!Q98ZY(qi={uvB{8l25~qBaq$%6cxG$jxXvoUKue<)uoFa_6@gKCaUPx} z9lsOD_%=3(iSN>JJXjw1=s4VCJ_PIX>yVt>tMC!T5`Tkn$Hdtk;99s}z9|jy0yS$Mg8+xF^x1B>Nqu->H1I-@wDDg8GVwh06iH)okfoOQtii#E)vqPE^(5#^}8Q##Qr1Sw67SKoZoc3@W_YN!q z-jX6f#lz5&%`7}9&HyzY&WML8gsvE>J)A`?xKr027W5R?7U>IVp-2=@VlSh&GxV@7 zU0V^wPMSPUrD8TcES|*Hy1RT&u{47kxSD=dsuI;32@K2>^V;u7v0n)gmv4}QYxR9N zrd=rl6F*F47nF$@6BcIx)Q7VG{DuJzG~^PslH6wDp{oaVf06J}^WlG#Oc+jkgyD-Y zK%p9EI%eb8jf{I_<+OBohd-5|HT3 z#bpiU(EzSlRFhoL6&LcLnn7~3KPvqyWxn$Rp3Nee2SyMWB4GS-wc~nC(hY#gAVaxy z=NMpeq7EJ=CCJkT%CoX`$%G($S~@LUv40#CRM9CO$uX~mQ_UE4wr2nwFF3e~2;(mYm=fq^my*$guc?yZHD2^GoWL-r3{ z`KYc24_pjB)=nozI>2h{WUGx#s0xE+2W+=BOH=Bz-Ll4CgSLyZ&vqX>XnTgpgKSo_ zc~!x|mZ`ArKj?2~^3dEZ@ zN&0|RWA~5qEy~^|Xyy&d$iYvgWz^L);xvd=Fb&?>M+2^=Q4v~dG75x%r3j9y$}yai zkB(&-qjAWBHOrJnj`EnW&1=f-d<|2DpUVqskmAjBX_# zq{*m?9O?$v6fJf|Wo$-%H15tu^Q&)0iYGAAEJ~?NoUNkN1c0(J-4{XGV{U_h_Jl@z;F`FIi6ucJ(0ID~1R;UoQ2AeW10Q3r&h0E&a2j02eoTe56QSU(pD zQ0aHmh{RD)Ehtp*AxH!}VwFpiaG9d2)s2D1;$dZaPJmOX#jfy>{y;^5VDuDj*NSDJ5F@x!+BJ1W<_*>!tQbI((~ zKk6IP_u;zAb(h?-azoX|L$__bWA+{Yl)WcfGTH*N)3~s-5Y3 zdUrXyesXW}bN_w+84o=C(7cCldH9h>et{*!Z7O*_5o~+6p&}6uESPd~Wc;mI`Rez3 z4qj9;=A7>I=%#Tkla^c@OjHIQ7}-=?(KNF5zD=7pRqa?jArokOtG48cCu_g4AX2jb z$=%Ptlo*!&!C7yP3LUGP6g`#*eEOeigR%B(psF-omMC*4Pm7F5gl=tFu)d@zboL7g zFdK$%E{$ytXCxY!Gk?K)#D)boKR)F+b?=BI{xUqU^|*)=-`e>S#r=UzvClB`#+G@@ z9}~LxW~Zq;aIExK?v(GpzGC>X+M>FxLDvbTyK^d<0iVvSn7A`m-W2L0fbsx2k9wHFsicr4x-*P0WUyDwj9EPuG4cU7i^6 z`1VKOw@vdWR+JTQnOM3xksi?$ezqx`scagP{>RYN=caAn4#3TaN3C48XyJT;YAY*U zkF<}MH-A}GT=c=*iPsNn*g8+A+&gJxDPp%rmWQ15%Ch6(L@4)#SOTR!yBtPVCMqN2 z=FcCAI-H(3ZS$~E^*g3bJy05h+LqEgV~GQk<|Fr((tTgtj-)$^omf*OmMVVY$v;2E zcB+^*IRNHQUrZ0%x1;K*Na(Dm`->KpZXb3m)DwGb$EtLBQ@Hk;hwjcWVMfs>z)n1W zHqycOE&8CMu`Cg6ylAB=zv$_|?H%>w;!2(2;q7iy@bHR~Ltm0G^u_!TY)+S>%3h#+a)furRyR!DFRg?Pi%%Ck&gSN@8VYzZ*B~Soq$# z!?NWSd*-W=*~*IXSI%etol}=w9xK1-nTkE1gi7dS>5_$6^w61~eJ$;7d->aGblUsx z`l$*fcK1A{RBdc{@k_BI7e=<;o49K1;)?q^CY0Rt!S<@py!6Py={wJ=eeL{9kKXtG zg%w3NOHr|jY@|M{)I>$q|3pQr6v{m`lxU%2U!UtF2JwRwA>d~3`0ja54)eg9wP z-COmmtFC|WOTYTThJ8EOO233xI+!72J9;_gpfrJQ0$l{*g#PLS~;_gds|N*FJ7&!kQ%<}x+hy$SD5 z8RH{dPGZh5#zXEmsZ-8)*xkqU;fzPzPcc4%@d|eabwZ4fbic}YnDI*Y9+nkhe3UyD z?@k5dqupZKGm`N!?%j-6GCtP*ka^s9&kO2dqPozXIhR)Y@=ljuxF%Ox6Tbht#9Fgik_pJX&7(JCT@CECo?h(vj# z8K{uxA7ETyq(n!;kU*tG+o?NBqMxVkXo)VO!WfCJXST5teF*D8V4OtpGiE94J%F7t^&``74OJ84pO5Ag_5q?zJFO0FoxiUKactrfap(ZwWHT z8AJ)6LzGJ#56mwu%=LhI8BAy?YUZ{$6d0V_iSunQ&iTaop%*8H!lh1s1Wp)C=xfaN z9}WcuXEzPJIN-4-L7Zy?9(&p?&Oa8Z;HQXll)1VC6nOM@ffcuJR>2h2I;i%3fazK- zd&f&z2*t=)u?jxVT%TcO$G8+|y-+n%9(6r9R}tqKFU|-wm*9kgDtMAO5xfC~ z0)w-HP1;uE!D%7R%|%)+J?%=1b3=&=Hh~F!k-2sjQDAU3(w=3-9-KAAxv|)T^Qgsn zt5gMd5~qeZeZ>@b^p1cPr`?0w-+zYT;X$(iQY%`Vc~??4EKJ{4H~}(xf|s z6llHBnap*t#DlY$DMv~?I17pm&OKojtOFC;$sY202?Yk{HbA;-$~-uKN1Rld2WN-H zSzD=s8;El$oxi7y0*~H7uu|EFRPb@Cae%u!%9*a!!VfUzv2stQw;`0uHk_e?|H53T zt8$+&r$Fn4HnF(a#mFzI;9{y> zNVVKZrfaqE(*z$?>B+PcLIHp6LKVD~xw`1db1Es&dZGL2$(zS}aK1&HyT^NQer|Do zd5sDlCQgPpkB_IoqxTV5G4g9F_%78P8u|DnrfaqE5rY5yBu}O~ERtg6-bYn11}5|n zb$&dF0*~I+UNSTo%$XdjEO$evhay{bGXDg%u%MkogX3|`Lk=`|glt!vh`B^9E*J*`Tu>gw!k?%U9vY)h`1-cBt^ncvgVvStY1 zDg}zHxuLeXt);I;X|BFjt?cOQZC>BCYE^Ht&!pDPw2_A9j?T8^dL{35&8s?kdIyy1 zG?0kuo7c1qNa`E3q$k;%?72DFX2BW_m@c}`Xj!v#8TEN(G@7ilRn5&UJvE)HdTV;x zyV^R|t*vSATAQrtZs~1BeS5omIyzU^BwN>XboVB!Z|Um!bZ>V{YqF-LXKnTB?%w8A zJ;|GTlB=p~XVlhQo?Me`=}j8s8TENa!E{|=V`Htgz0OAJZDfXxG$@Zl>#WH$>eaf= z-j3Cs$+lQ)drObeuCFx(h}+wf9jn`|Lub#_ZoB9cSH>3B)x~B_pE12IR$p7!SUa=6 zJ~p*S8$K;|-Tcchtx2w3nQUuIwpGunUfI*q+1eiKN#5Mi+tJk-tDjjnyLQ$MvFf$0 z-RtJHcJ=fn*H^Et1>e`cZtcog_3BvlWxcWL-oCbZt2@`BsOnW~lfAtytCQ7hlAWvj z+UG%el{UVb#)Dh6uCuid=+(VRp~%0A_4e{`bF#OurLzsKVd^_Gue;UN<+-=M(c2ei zS=Yi5d5ut?ujS=t=V|7_)mcyLrkrj2^sM|AuQOi1IoU(!4K`XwXP+J$URxUS`!ITs zr|lv1aCI~CY@2Dj5(c0bvCe0X@t1UuTRPhM+U?l$3@~ei#%XQoZqDmSDA{92eS=!l z(V1+P5ut0eA#b$TH=0?c#xsSq4)#~UTG!dp+J*VYjMhfAblK9`GaBle`(`xjxyXp% zPjB^R=b2&+m)f-@*9^=<=qBD=b;gtGqJ<0R#HQArKWA1o2SW8t_0=<{{l7)An#!{h;p+E^c}A z@k`ZoqoDE2)jY%BAo#<)*@5ThvEX@vtA_jVhpS7BT;qq;wTAyM!OyqG_2qU|*n`gc zM0^?%`94W1ZNbY?m5Svsyo{!D^cSq@1iZULc&zB2;9^bAw`i2Q)5tacSpFG~go)S# zIBJaHG;xRUV}0^*KKya&3r0iZpRNuXK8&VxaEk)?YaTDXHdd--3cL+bjCvWiK zH>kA+?+Iu+YL>dq@ZXz8ex@(KpP%KEH~R1!)s8&;3)F*#|H*~KpX1B#=P&Td=lbyH zswWKIbI`nv>{#VzKM^tho4Y9=rHK{ZK3+9;dcj!zd#GkyE}wm z=#w}3@SD^ddH9#8-x=O@iGQ&#|6*VM#p*+&|6OQ0YN;xNT@3pkCBH;7=G`5_^X_Lb zxI@abv%A)D)v`fl#9Z|WAAgyT|D=z<+{gcokH12VHTF+{q(UuLu{?gRnwG~ms`@;> zLGgNxLFcbkO?muz>e4)Zs=6wVuTsrpQERQczPvr4U>X|$~k$3!SRaFCLF5kZDf7^{?bMDzT`uC-IJ6+%2Hh;s3gI(TU zF7KS@+aB88w>fUv{ow%XF=*iAq=jI;!u&Gr3Dl_O!{(nldkel4!4sNaK&Cen4B`!uC1$m5bq1^Sfi zfXH*@C*=x9%9VojDnnNqiXtR^qoH>h`dLFCGxW=be#6k041LAW*A4xRp&uDqjP-}* zjy5!A=(&ck|T&*?yMpBHo?WCKO+HcaICB=CAf#H8aigEZBX&Rjd=PH&vf)wL$ zq~W8a7@yUoDSSNFq+dyj@p-M`SCb}`T1R>ZK80t}A0=IcUq?6m5z@s<{gm`}rG979 zKP1I?&KZ7q5In~DX{5I)bv`NVTR@6&e!by4NHP9zA-z?p&zkhTq!|AP41bUm^THug z47%4%`rD+K7n~AM;D<;tUrZp~fPQGwn@BMq@cc%-Pm^L0Zy;T7=82o&$LYNr*7mim z1nuk5wB5#V4cMoq%ThCaWpA&VjvK}4JzY$guBZIES|sKt=%r~$s$Ss>Ak_I0%&x+R zU@rm-Ak_O2%<||%u=i#K5N7xh%!QZ_!Cuf6KxptIm`#ii!R|T=Ak6e5n0rPag1s#( zfPibc{I)QAfg!1`)IXRkknJzfa~#mUAt`@l6oox zeJnqx`_8Eok`v;$1;>^PKeG__K`-%dC z_qPk%_amR))^`fq_kEvzTRrw+2n^WAI}6%i`_(?+@p+C7);|4=c~EZy9=<(il|Zdt z2o?9@owv{_=)Ymm^Ug2#dF)F7&-#xa6Y%0K0UnOxlyyrc5i#>QfKD_O~FFB{uxu;K>NP# z!~6B`9raBM4r=Xt&!=}kJ{Hb>h7DHl9bdWc1p~5AXStW*1+nlS`S6|wUW)|-wRk1i zOEJzlksdy(c4a7_cqO)B6B^ITyCrVDsG~=n;nvVKAt6fYy(`jdV z#NP8e=bn4cxp&V!tg*1XCBCQ(pMEGy2a@bo4ivX6PwS*G{5BP25s-M&o-B{>pTG7Aa1XsD!TGMUAZWM<`@*VAXXUtL&On2s-HGLy-X zURV1RW~UZ2neiba4}z0v@3kL(bxxtxjQ&1-Kq`g;2s2CqmYlgUv7LxRPm z;c~eI=&sZZWMNR!NRpx^=LCaY87jzd_#B3TvoLsVf>*%lm62P9YjAvV3|^w5Uu&u4)8QsaPzP zN(C?kjM(bxs+Z&gm&5znXFuLGWJ%hk)V_-R)LAmzffSAt$J9WK-3HI{+SrlT@AvX^ z#5y?*FMdgyOZnrfsx*Aa&lguCYCIKyhvf$k9yC&=)#Vh)Q+Pde4^MJRCQi>0AA4mi zKJ>{a`Mw#fy^n;l*G970z2peeO^#%dv$C4qQ@e()>V4DMZ1&nTqFtNLuCBgAw9rVB zV`2Xy2@4JNaNIwBco;YvIBcwD7kIyo)kcTQ$VB=4qUm%x8eK}KBQwe5$o-j%sIAKJc8~irt#PGc%Dc{9?yV#*p0to%ntLiL#!vLSjnQB z{V_7BX^JRZIAF5@bOz}Odl_JVPk7=fTroX0(SXNx{{#qW@Umf!!R3F10XihjW)BnUC6;PTOe8!94u{j}IKZ!%%_NJMh)e2$GNiE5@$u)6KmXV_ zk(ux<>w>-R0I>mKfjN- zvV7-`Jk>YlpK|uNdeAq#UZmo7Q$%f|Uk(ex5DmUO&_{6)XGwG!jZ-p_Bn$(0orUlN zQ$ghL3DQ@i?TKg?>=C*73%!g_iwCUlV|+$D#kimG zfY{49co=&{58Iz+JV=tnZ>UX>{{-e_UHb(L!kL#@mS8Ef!C3&;1cql4IeC4X)b548 zgNx4Lawn zs1p#r`~V58K@MZYn)WltmPknuGX1>XHG;`-8}c}RJUut);LNy2v1d^0g_;lpni%v6 z9))M!rwDa~TnUd53WY1x;>J!%BPwrI>$&>gwpP;0p>>{K+bEV;+mfhKEor-xxpGCX z)u~Xa*K#Foqn@XoYOS(X)k;dGS|@m{>BaEz(jsM+Gt=kJPv+|9a;*@w2%oR-UT8Ut zS`JO`(cDHJ&UdPn;udl;gRE)9Mtyo7cnDaxJW{Z33?|`Jxui>zl!~?OLv^Ywzh=IT$$?318JVw0uo_ zzKP;`UZ+wX`?B{ycQw6M*{ZhE*|kzI^QB^bJ7*>M#+zAXesWT|5IPr{RHBi|SY#?1 zRRVe|!nkrHd37bMZ5FgrNh<{}1Pgk;T3lCj?QVtLE77UR>BxnfN^rBdy)#?f((Br8 za5DnAzP__rP=aep@KQ|)*6O9%wdxK+1XD$SJ>%sS;!Kv~8`z$CKL8a!ke4#?Z7+~9c>sVGIs7E zh+bh(_=Yg_^~!HmImQ-A^w(B%wq%iu`~->C^|4hVnHSs^AxYHww6s-U4<}NaIggHE z5$@>;63PCQYbiy-N7)Gy$#p_PuOM`Y6C}P6T_o;z&q<_i>aj#0crWrr|1s$ZIrSpH zpQhZSg_onBtowZ!0THeB16Xy#B zTyiWwp3URxuW9huGT@73V+5yAacgr^<8F$U5z5!=dZn;ahyDLfFToUBJ+8R(FDz~S zqaYfw?CeT^(T;sEy^4pc^}pGD6E?iY_Rs#f7HzVx27i8>w7U$MYt$w?uKATbzj<9T) z*>iV*PsUB*Zg3oq%X&Mm`IQ3MrZD`aZ2{c&_k9a<-($K5JD+`+klBu(k1TH6{RqL{ zfzBq|j_(!T*|x3!5_Xfe0B*-+ej*I{&;t}G-O%&H`(Vy{vTFd4;y7o8fkn1I?i(lV OmT@jWw~fGUyMF_}(ytT% literal 0 HcmV?d00001 diff --git a/Release/src/i2c.d b/Release/src/i2c.d new file mode 100644 index 0000000..48e1a60 --- /dev/null +++ b/Release/src/i2c.d @@ -0,0 +1,91 @@ +src/i2c.o: ../src/i2c.c \ + ../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h \ + ../system/include/cmsis/stm32f0xx.h ../system/include/cmsis/core_cm0.h \ + ../system/include/cmsis/core_cmInstr.h \ + ../system/include/cmsis/cmsis_gcc.h \ + ../system/include/cmsis/core_cmFunc.h \ + ../system/include/cmsis/system_stm32f0xx.h ../include/stm32f0xx_conf.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_adc.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_can.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_cec.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_crc.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_crs.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_comp.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_dac.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_dma.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_exti.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_flash.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_spi.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_tim.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_usart.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_misc.h ../include/i2c.h + +../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h: + +../system/include/cmsis/stm32f0xx.h: + +../system/include/cmsis/core_cm0.h: + +../system/include/cmsis/core_cmInstr.h: + +../system/include/cmsis/cmsis_gcc.h: + +../system/include/cmsis/core_cmFunc.h: + +../system/include/cmsis/system_stm32f0xx.h: + +../include/stm32f0xx_conf.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_adc.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_can.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_cec.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_crc.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_crs.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_comp.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_dac.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_dma.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_exti.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_flash.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_spi.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_tim.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_usart.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_misc.h: + +../include/i2c.h: diff --git a/Release/src/i2c.o b/Release/src/i2c.o new file mode 100644 index 0000000000000000000000000000000000000000..47e55aaba336e66669a94705ba9cf3b544f85ff9 GIT binary patch literal 8992 zcmb_hdu&_ReLnYIQsP6Rsh2Iuu1!7MC~Zhe@-wj&QzB(qmhH&2(n?MXi6XB=#uCMl zRBSgzqPA`uZ_Sp(O_QQ7Qg~ULZtms=%d)m8=AlEoVGEYD{iA5sC2g~%z|sO;uwg~l zYTtM6x#T4iU>LRoTz=;}=l44Ab1xqnKXFvkG+`%A42UWd;-z=V8uwla1EN>-h|a05 z<6XH&$9iAh=zZMq#k*78xsFL+tUDF#?K%gZ7JbG-e8EU<^y#@*+--3q^(b=NHRim? z5w$)&3tT8nZ1jFtS#e7%ufB2fs0ivYF(YD|o3CzeZvN$_==;PC_Z9!tWg)KkrZ#fg z7449I#XDu-aa}og^zUXnV;j%i?2eDkj^2E(;YMNN=26#%5E>pY9uJ<4zOn4*5JMb3 zgU@UIO~>1^e-Lk5*y#07J+9AXeR1F9*#%$rTHJ@Sx$NVbFMf7`TCYg0;5Tm`ofUda z;7Q;K^?oeZHuhgHeJgh*{;gDDLhI{_O*W3gx)AYf!|}FQd|@o>chRFUH76g&wYe!a zsZU$3zK`a*VIy|$&F2aeuHN{)uRQmWTnkD%1?^~kpN$2dPh`7eulrut6AOuKPka== zkLg759@oq0GxVc>A^1(>cuUrg_WTO{XWQ45{f{gbCT841xCE0+dp`!bDXI%`T^3Y- zbgkhqign!`MxpLais7y(IK-Ub@m zB8kWACkaZ@GYVs}ci!+VV6h$JCToLwH1q~H4tYepp*@P3#E#w5AT`%#j( zB!gD}B_!D^e4X?wfPb01CRX-YfYF5_Ecd_rtO{o9N$ zN9Mz$U7fC|=Tv(eHA+zZMT#}g(p;KZt2L#HM%vOqOf-6yA_+X&)z4H!&e|exQREaw ztkL;eMdXwcX?vI=QM(H)O9R+Ktgeev3@s4BMFu40LI}0v09_8Ug`=Qb=V?XKjw_Yy z3~IK0j&z6?^~bW-;y(x?C!AY!{+4#w@uJM!RjX42DmtOHXuAV#ej~6waQC(rEw~M4 z`i0+rCyFqOw_;nk!+*#>*@i7|pCGtZwFmQbZ>9Q3*WoU#+&0bchrC;Zpr=_F9+Jtn zgMRFaptPl^PnibAGSRfjHtIC>z(*9)%@OTLm*xAGt`@DeA=dfiSQkYC?ut{rQ;02F z5G`#49pz|63n;y#P6us8s1DlZG(Xu^~@K_wCNfFv`d;G%K0zOAXiCNDANSmc)LC&(HH_7NqP6erHQFP_O2`OAP;IoAAJ+X2i5G>|F{f*ek{=4KXHWCU z+^(LHxjEhAsQIbDHle$;hET&uPfN5$>t{l1pQjBy|Z^@WJ+pB8i@KX{!Hl&4&hI0jwq%1R3=jtXXNn2 z*NSF*Wi5S9j82aYCC|(xIV|%fvpk<)yjV6%qLf`LmP5RiF0G`NOGC2$d@)xx#aIIO zFN#Y#FU_v3<(EV9hboi9@e3kxa&&&?V!=$9OCmXbW<2@6@x-8rADu{w)X@03_-d8l2!h?GTqe*kcOqEO-a4w%Ki`05~&CF*+CE8>> zUI`Tb84FvNURy^~&_Ba6qWGEd6G;)D9!2E&Qf@hKWZ7%8!DRj=SsP?d}w(8(CvcGOUM7rbOs3Wm4solcSr=QaP2!GF+BTE|u2`vc>EJYwbt5;L^g`;Obac zI-)X9hUKvC8OFHQRC3sd<>2p8o>JxYl2}QV%Jb&^So)GOKsj&X*;GDnu2hC)dK_~j zek!5nsXc_&B&~78kt>?1%zQqD*-Zx9#j=>0JUM>X-O#^l6fY+D85YTt)37?jxhR`d zV+Zn+r!ZC3a)_VAxYJrLpD{1Uob+NlDVkV2vKgHGmAI)a*1DV+IgbElgN<_b+p?>29F{~GH~`Z zIyf%@Y=5RwRvUqVyGyOSTgvaP$m1^UNCqx9weq||Rg;0*+WJOm?_foww$>1yI(giy z9mx>hx_Ympmi^;M=;$QIr(;v#h!Xi}hKLtMzGTXN)OTC`!1Ac7 z->+~);h4f1h4(02P*_xWQQ;>QeoCRdI>Y|g75|RH?<@R?LKg-_#;b6r!ov#BDZHTY z;|d>F_%(&!R`@-IKURp#qO`w5;jIeyD~v0gR`@}M=M`R3_?W`$3SU(C1BE|T_zQ)< zQn*RPhn4`gOtw>g;bgxn&Mz!FmP11E(+ck)_6l*Y!ix$YQuUXK7}Tc}zozQHs_+F> z{#Qi2LcgT=4^{nZivJ4{%lqFI*RfSI&Rq(36R{oaReV(86cO?9-J0_6Ct~p|DPC6i zAtDy{WyPOV_<16>!Rv~DUEyC7u^oR;@gEW4=O>E4srWAy|Fz=SB4iwXg&jobbt`_m z!XrdH#}&skl>HAg61g*TJh(#=dlc?gc$-2V!K^=^@Q_08Gb}%)@O=vTNsHwxM2uTO z;dzA*D11cWV+ud3@be0<6EU7Q6uzMF8wy_}V!U2f_ydLisPGMi|EiD&Kl|I@dI9S?v3^!z1MP>beVP5vlY;dqlH)%>#Qc!`85DwNHsg;G zF)xo1(cWny`fZkoeq12(111r6<@f<%TH0??2$RweOi7gf;g2U0{f3AT>Q^Y^fqyy9 zz(JNnd9OklAL2Po4vY~IS3;qT7xA4S2g(WZd8~ZupaNg3CDJcR}fA zi11%fyi7zK8;V~d!r7yWf0~H6zM%LsM8tPP@joLX&c9Lo?};3@Na^BgIkgBZ7cI=% zIoxH-A|hXWB8w$_DPci`$DMpxty1-hR8xQh*U540R;hLPR=IryS4$jk`_;nATTNY& ze4VP6IgaMKLJ`4>ZzN+bt}mkrOKWJH%%>I?@y6?{#rFp%P2sh88DAb8`fo2;$>s5t z$+Czp6p{4W>Z*zNbcfbbF|`UIymd!X<#I8%xXuq6|BHknl=mmDXQsUtRDN}p>j7d) z3LGag)yuJt2~$t5)&EJ3>ySE5zh!Vcxm4y5&?)yUc)}I}+H#!lPPsS1n;dd>J3de+ z_n+YJWba&^9PceyK9ywKd!SD41mv7=3AWrLb#mNC2P)R8?YLGaw*filE#J2He4QL# zTi-Fhzpaz|0_0*SvyGJ?^Qr z$9E&!UZT$48?g5?+X&?BY^=^+3=4Wz*+bJS_NJA+L6kB50|u9OO*_#ZpL^=$W-;k$ z&rY^nR>|4rHz48Yk>SO qAU6%g5c2QALwg8C`gAl;crgFC2JK|qgF5|I(lG?ZcM&_;+5ZOjT2A8t literal 0 HcmV?d00001 diff --git a/Release/src/ili9341.d b/Release/src/ili9341.d new file mode 100644 index 0000000..317058d --- /dev/null +++ b/Release/src/ili9341.d @@ -0,0 +1,93 @@ +src/ili9341.o: ../src/ili9341.c ../include/ili9341.h \ + ../system/include/cmsis/stm32f0xx.h ../system/include/cmsis/core_cm0.h \ + ../system/include/cmsis/core_cmInstr.h \ + ../system/include/cmsis/cmsis_gcc.h \ + ../system/include/cmsis/core_cmFunc.h \ + ../system/include/cmsis/system_stm32f0xx.h ../include/stm32f0xx_conf.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_adc.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_can.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_cec.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_crc.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_crs.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_comp.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_dac.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_dma.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_exti.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_flash.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_spi.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_tim.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_usart.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_misc.h ../include/delay.h + +../include/ili9341.h: + +../system/include/cmsis/stm32f0xx.h: + +../system/include/cmsis/core_cm0.h: + +../system/include/cmsis/core_cmInstr.h: + +../system/include/cmsis/cmsis_gcc.h: + +../system/include/cmsis/core_cmFunc.h: + +../system/include/cmsis/system_stm32f0xx.h: + +../include/stm32f0xx_conf.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_adc.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_can.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_cec.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_crc.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_crs.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_comp.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_dac.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_dma.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_exti.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_flash.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_spi.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_tim.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_usart.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_misc.h: + +../include/delay.h: diff --git a/Release/src/ili9341.o b/Release/src/ili9341.o new file mode 100644 index 0000000000000000000000000000000000000000..454bfe9ff127b5d3133005ea00150d03371f2d67 GIT binary patch literal 62584 zcmeFad3;sX`Tx82IVUG410e+DWMDWMAOSKn&mjy#5;259P$UErNF*dN1A}7(hk%NN zpkfllv5q(#l~QZ1T5YYiRogm4rL7gU4ydj8vwrLSeAasQ83Ok9b$`G6&wbs^Yw!1Z zp7pF}&1`?xuGpPyDUG1=Bu>sRcgfC%9xIWi7Ed5#p>u#_1WyNy}6~iMHBqP+G9F$7Nq!<&$FsMaUWt6 z)h}kh>rE`mDvk6HZ_g^tDp9E`R%Ml{j6s#X^HMsh;iVULL)2ekmtK-yl;R)QzGj~4 z8rWfV`ASt<&#K;eR!`NOWPc~@2B?>2|K6KYI-n@ppWJSx_s)B|*!8OF=}ul;ym(gc zyfyRAC{1os>HCYLk3^OvbZjejzt&sqIucWw(s5q$xv+^V8Q664XS&M&PcG^4PdG~k zw)6b{z}-WNC5-&Hzub4J0yw-RVVX??!Z2^2zh@4o+ILp{C;Rp^PicZ>d>Q|pRj$+cr|d@C$^wsE})!}@7{ZL=83W?pK!ykueOsY?{rdnT}`kJ7xSLo|Wef8<< zGy0mYuO=^_VyR!yni=|oI-pudfCAYFay1hvW3scw4B$U+C*ZeT~#tQ+`uxV;`mUCa*t-giY)q ztugikblCVYxj(BlrluxeQ#Ml`V`Eyw=#7U_I#oPIfJ-SoPLAnO692Q4PpH(mv->Zc z(lNHfnqp10cK7)A_&thkt}>=}+*us+*2$k)`zTxE5BkS;JWzb{Eo9D^h_V^vTEY>u4>0Mk2Uu*hVme%|;kT++r?JpTC z8vJ2pGydG-F9ZIHhux95#~<@w`8)B%HIEEYu@9tlxK)33hEiR(7pJ_|?%(0RsW{>t zYy9YBQ?LHVZYp*kz0qHsVioT3tDY?N)p3V1c_`g#k&m4C+3w;2NP9O@-&5>D>I;xs z^|+3eq>NHlq3SWdK03ZSnQi6VeQ%0pk8Ah#;)o;ZDq9UzQ`JN@Ox*){j2e$nx|*hj ztEnkH{-zYGi}oAlxp4Q1*!_q8J&EVVTWJp!M;>+TaoytV_Nkr46-QImuwxa)|2!Vi zeV6~%Fz^Y%|Gr_V^o?l=}gPMcl^W?J06MXibF4{JyzF-c~)9VhjaJulh0G<6{q+k zyHt9D-__~Z)j~yhNDM~iG5e~SW|H)?uzVjjP3C!`y=-_x_fZ9b#%FV z9o-z^>3(6ZBl}((KgpV64jOPfVGEv1S>7NYarUm)9FMz^>jq; zel5AHh^^#CD@FMoovyB!J+2;0w^F}AD_OdgEVQ3#C3m2eT>Gu@51{=v%%gutx2sF_ ztWuBpBf8jPY_FK^D74rRwAg`;-fM?m7u|D_S~W!V9P%Ga^e29lvIp~_-S6x%b$dVQ z>qOP#_kWbU1GO+(M;bjmb{Y>Kr5sE4Cps~6=tDfD7!RK&-xu(3hMu+`;x zV0gz=Gy8i+s};j8Oq{BGYKKleRTU@;^MsyihxrgwpxC#Rxf?q9#2G57WQd}VfmpMK zz3nX>*0HNN`R&0S)=l%09-n93`uJSO(K9-7k`Ma(u4Bbm$?nHmX6Cudj(+Xr&nB6Y z%sAv%x!=5IO}oqgBJM)J~B+jKcF&FDzEpux&|Qc?P%W(^HO$>QqC^t zz6i8s3jDgex-i;jqxn2tp6+0BZuAB`P-A)G15}80_^ce>}LAN9&7ri$?l$UNy~@1dNTZp z7z;W6cC3U`uo5Z1y3v$y!@NPh#8u87$cS;In^lUd0OyCZ(@Gtp77t57>n>Im#XE~$ zP9E;>^2cCKICi@`qdOzITs;w-6Yp?NY?$ZhPT8rtdeEMc=m%$a&(6qw`x6hM{%IIt zEE(309>#mRoZYI&v+vf#L;eEk39H-DQ=od1d;E#eL>YUmOrsRn<9xAlVixA3{SNx= z^$z9lj@n0?G>l8;LV9#h(k4=eR9@^6%-69gW{h0>UXlahnVjKyJx9%Y=jw`Ni+S|>vh!GHPCN$S?MaHpQ=#Z$pih4-L9_4&WKL6mn)$g^H5rV%Vn21wBe4%~U2>uh{dA~M@lG)WD}dTdpAi_llR1{Pr1p-{xw&*p z@}7O-i5ngnss=saRrI4et*$dL6Ngj|=ANMIzT#C!Z^!di-7$r+HB>p(B;>1l?krAz z?J#yQMz(tP6-OSix~C4g87;?kcevl$y|0RIlnn|Lsmx z^Nx*CYQO55sv^}%toO0EIQQM!p<5!+>G#~?+UL+?C#Ktp*&5NkcFx{;PK?wEiEHP$ zx*R*N{;ColM;&(M&9^~$Q*rIl1!t-BPgh-qowT*j(NmO?l9;8i8|<1>sz#iLesCU5R_`ar zqGz`IooMxE5)VU%J%VoaE`LIjtILmm`3L$XdSukYp8F?<^}*Nd1N2N!VgYul(g*3^ zuQF}@jI^~I^E_fVd*ws)N~*H^#e^@N0mhOSk z%5jU_XO#k`V0cZG+9k*t%FDCdu_`$Yr!c&}i z#=C8#(>LHOU(qHNU*^d2zUstjWyQW~o)1r?k7*y-PH*;!XD1)SC(?7<)7!r|-r@WB z_=moKhVD63k#!RmMLZ|sa9P_OO2yveRO-11r4C!c9(P#oM<6=Cgvv2yBCnR`Eo!dv zAUtsaHI9hPC}>KM-ZA++t%>}Onu2I(&e}+gD`FN?oj{I`voF`0$k7x$5pLw^@I*cp ziITV?>Ka;M9XZTRr7IfB2$!=7md@C{Naj2N$F6MpbgpHJW(M8&pfnLRm=;P!x?Ddx z33@)k#dYs*7~DY1`>0h>tVATr5=~>Lit)Ja%z_yE9&&Wu%{)}>P+VO1zs0L^-T>dO z2bjcp9)k}*0KM~Rl*2ukHR;!l(j~g{dgL~7c6LuO zIrV3FD#M=G`KXe68pE-%-SFd{&TxEe4a+`*;X$#-X)}}I#MnGEle>uFA+ZgTw6Vp#z98dkgmjYC&aui(N{eD-&}4k4l6 zZSdf6xBUx3Y%V)v6N4)DLVDP&J;MVBLBF}^lv?)_V}Q8ICgnb)E#oSimHWrqFs^d5 zavx^U6MK;D^pgd275g2o?k5?Ji>q9-PPu>j2J(oHy@I8GiuQ@IhuO2gxDVkWu|>GL zU)YC!_r=l1)MwMSGS0 zr^U9hJb!TGS`_-2PqFIBZ8ZqO%XVI)l$4v4brO@nXL(DYq>ojX~a6T4!*K-JL(q?nKBWSi+ z$ISO$fYQ3RI4(w-GVd!aUBegI1)?f{h*@|3641u$I|`7j(v#x#DT`U4zXBfE0OXHhWooX zAa#>J1u>+_wJ1&Ar7ds8b>Opb$T1XRNtN9>FVaS*LjFM;$RlkT zCA|#gbPu;I)F|m9B#3pVTk8?;)zfx_4l8dVV%#GwX5;d<>3WYAp7P#L*Iin8-kZ;uz1rJvR1`-Ev(yce zWMt;5ag-wuqF08h9Y8%isAypp!P9TMX^yi&P7f+ z;l4~y!y%mE?i(HKkRkh7##W-#~%6ecpG z96{e3aN^vGP-ONRM*Wgj`K^rl0#T`xA$zL1Qbm0Sc?d+Er-fx2;nda0C2A^7le42g zaC`!tmvb=sLkI1Z_aR)PKXUvTaCx6caiTwVFjKd85~8F3uFX8&Y^M1{3$bYn=2WQY zPj#Aj@9&uAGo2VGEgDmd{bp2250DIw9didIr4J2noH#$GYxJ#Q|QJ|tPbh7x$6u;TY;yVyi zsG?hRjLQ_VRmZr~79)!`9pN!$+@vF-(^&Y;IwIEOy+udFc|U{4=&d>?-g|Ku*?)(N8sYB6xF;iLR^mgPQGwo#rBe1$baW%>irkILmikTi_aZg`G zNngdGzKRwUC1ys5k4uqRn1VNrFvV4UEskJN$IN^tSkn7h^rE1`IRfR6jpA7K{Wb>G zY(|RMn70s2uZDXoiZzyM&O*?N4k|K!Ma5>_2Hc)lz3s6|jo3&Xv*0oEI2>AAwVVn$ z6V+5tj8dusrdd|G!!tpR%7U%|x>1D)Tt6Ct3Dht!1%a~}C>9$vn)hyNrp~n<4R7^c z5{F#3P{-Ed6dJMBmTsW5*_NijenhP;wLuy)f-Yw29)FN>c2MT?N_I2e{I1lF9i1z) z*M~@}ve$%2tFxO6gO+Qu*M~^e*=s_ibvf0|w&f7CaZdGmTb!oFHMY2tV!-wiN&(Zm zDFrNFgOoc6zlk_D`(|7hxjKvX;!aWFXhX-a z;`@C{eQGRRopbg&)TnaNs?1(^eit5wqqX6|)mg^0i?pW-N9U?6Yq6tqwaWC1-I=ys zxv|@XRLn`+tyB52@Z69ozL1wL&wO2;=*~Ir&ZjPSrxgr=wWo8wyHz2q)aVr$K9*DW z{gp^>^{$FHeecv=^evi!eQ%@-V8^~UQXD2Q``$?9kWAk@bsJqqS@*q>?}x1W-WS&Q zwq*L=mQ3HyTuv?@D12a;i=8LHs9nWq(gnm@&eg=D^2C|3qspRy22DKfr zH6TvMO@G7|%tI4|%}{+<57pI>Ge;xS)?s+a!3@#! za;2$}ndfHyVlF!_RSs-kGkIgA`A5cFPjFejU7f3$6g8^`B|-i?NuYge1KcraU{$y} zbzY0vEMl%Q$}q~UYju0Pq}!t&-;5ZsoH}j~??RbJ;5%|gdVw{%iDpLrAW%ai55#RK z8#nb`x+xux1V(Yayo?=aNv$8g7 zc`4*f?ljnRqXx_9L!CH9%;@8Q!>KJwZHwi`!t4ZS(IFNaZ3`K}L5ps&xZYUEpbh5n zpu`{if%vB-{*@oh;YG3d!nWvJ%KYDpg`Nj}YpF6ixeT1I`{*)QTD=*G=oPf(`MR-o zps~0oG19%1uqQFnA1Pr^Vx+Gqp^=T0jhm(Ez4LWnFNd5t4H^6`32%2X40Lg%!CE0z zM0T!rcUHT(=E=M?BRI1fsYaz>l$%so?0hgy>s;=}XvCt%#CjjM*ecM|Sy0A@*^ixV`6C)j`gf=mf8@DC4 ziIFlPnKoId+hj51%=yTGtMp+syKWQdKzop|IX1&?rP%!?+|FLobTb%B4%`>vF&c$F zwbSi|Rb^f$cKOCm-yQ4;5VX1jR=wD~t`aN8h?T2TZ@KJdXDJVh^>wz-(^#7pr}gi| z`pN%bJx=!ztn+ybWJyq`(1{c%#U$HOO_r#IY>;W7s8gE{(Y#e@hC$?+vOLF z9deCq<$_K}l69z|%BbMt?bI#69hlY2w%7Xur=A68q9S^KV8mLA80tpa0cp$)Oy+d( zVfuc`u?R@~%anD4J9T@Wgq*!jSrOW`qqAt_Ufzz~TAYeoeqJ}_NQo}bK~H$J(1yrt z^hA`FoY=l+J|uPYn!$qY{iRB;6@fcczL!xfRVk`p^tn%D>6FRyX;rV0m~70dv%t@DL;`r>^j|&6Zs%0 zLGG+=Z6Iitq&nSw1(6&a*XXVt%e_vQ_A!?G90}?@&dpj~aBVcK_nB}K!?)>hVG4?% zAB1+Aj=MG(XM(D5u^o3qFwO*3VWSsA>s}qHCL8G& zMp6@waiLviS)3ePs+Z~7a;cUO)>RWStzp7y!cZ>pb1l5JHtFUD(n$y_unC!TCafm> zgNx7<%gWd3#xl&=F>z}kXzYzzWz@2Kqu9S{K2EE5KN6aGHA<&E%-Mnc^B66?P3Zz# zio*sv6RU)NRkRZcF+i+*3_>ekOP`sIIro z#wqO-@YVy<3Wca_RqBWXt)9r`D;R#Y>@%(F#hHi)|lJL$*fL4odSf=Mruq+5cjc1d}i zo$^zad9|3`COS{G*_F}TW0G{N%G@JnzZ6xmSxag4j_vIVm3gb=@R_YUsWR`9q>gk` zeUDFN-Y<58MHlsq%6vrZM%#AjDwC@*dt!!dhbDeX>?%apilOtI*sZheUQn4Yirq!F zzZqt?$1?A-by+I&kCOHdJMFJj<~x%1kgdB~WgZi|m+Z6?ROSa__a|F7UuAwGc3;}M zDJt_zv2$a3adLQ;s?2Z1E?IO@kE+ani(QVR2SQ3+prLb?gr6$GF4`pxVzJ~`%-0QiQOS_hl1pa*-LiPkt%bXm>m@} zOj&+Hz`}iDdpoA|>q{2SHNwp7nJROhq)ap_hX+Z^M3-&r#;D8+(an^k)9~CZstQq| zUss8$MpUSMwWzk*&K9c73q*Il=%T(*nS8IovfXamO;nkiMEAJ3gX$7dy(nfJb=ySu zu9#t-@J$B2eI_cDZI`I5k*4xkuJ(#*kf_kQ-B7XFvW&_R^=G_W5wod5Grmxx|AnH0 z{|7}?C8|021VL1-qC&wAi|QIt%~F|9i>g~xs3kv2rTd4BO83f3qI*tsQJ90TitY{D z4x{o7(S0QD&<96E^_{5D?|%_hf7}T$6D;)ShoVY1DxK+PqMK;zFxmbgx)MnWZ{I@2 zRy$u*v+#vuhcqOo8KS17;67trf{CTLI9t7Zk3NliolAJrJqvfUX?)+Ur3OlT-L0h? zbet_c!uuZYaLn)(yIi9&&!A(Y{mtlHn|UuZw_Irdmss*?3ag^F?2jVwuDMBDLeScD zqs0>wCY$6lQFIhncmZWaesi%pyN-W!ux>$5=qT^tlFS;E;UH(Go^q^x~;eI*& zdM8?F6WfIc@4i+qKeC#JE&e8M|6gO1;A0dmd`SVDH!TcgGfe5{LXt)%#x50!)6oJm z^blm~V=daGS1! zlTnjW7KY=aBw$enb(uC|-<|a@_u!KE~U_^H;Da?&rg9 z8ogAUh(IX==?K&#P(f?@Vq0tN^|sw@3^3)h2#f;tlSBSU1olI+_x7rsk4rqtaaz6e za**tGsQ$wA?;+sC>#E|95XfNQD+J~uu$ak?A&J(kvu&784;XW(}c)8I2A?c^YY8!+G5)>O)n$nSrDc9*w{M1vdU3lU=d!p7-=yjm0yD7;Uy~P zdwd=&kk!kQ6n_a-|1<=?Lm;04H|EeH2I3KDW*`{>{0~F5nCZC#)|#K&Hb)s?s(&#+ zKN)!Z(4P5BG^z}_>3Osq0VxsR>BCpmnij>=GY_kjH6m_cj597JZmD;G#gEDy87d}b z22_~OgOxLGO3c)l1-M_gEf`2`bgEh~ zFb@f128P(i25l!HuHQh*85i^vhggp(0%Q9#XJ!|#%_8g!2ZT7mf}3!L%0!C{Jj2RN zGI`@3%4BDZ)EFE{9l?TmB{eF-OcFyxI73ixO`x z)>({*2&8nND@O)%q?oy5n}rT9(4CRB6Av?v#Li+k9EAwQ2rLn&`o78d9s}PT3@8b%$X^H6fu38YU)r`Fpy=9h)dv#)Y9-E*QvCoSiF;s2c~j z=v=97ps^O|3Zo$^Vk8PH8iVZ5CF77BcOoORn9HbPiO$ghq+8BhrzJIb%rd|Q3EZ(nb?AsCI{}sjnIjZ9Xpd&pZ-3b}4%MRfxXgq4&_irpq}aO1 zc$~0xk=(%22Pr;W2MaJ0_voC!d!3Bn+7(6y!hPYmsK@Dx6@sj1ce7ZaE1 zUYmz=#fs zFA7OtWc#<{F*q5WjT6CqfF(unRKsO7EYz{fI75sf*OcWyfI4uP%(>gv?-fu7X3iPnz(?=Q zodbqpW`CuGkAWv7%v{_$m!-^wle*7(Ii%ih2t}Zew z%-%&+h;MOfJu{EC>t$Cmbm>7nN1cpkJNv~4?Ce=HyT+(|F#n}?{-{ha_odAJOYLxp zZfH|m=FG>EkRbpYoipbEOTgN5r6$?U)H90?oG9=yfWE0Fzs3o5unWtf2pn_>OFfaq zv5OoedNNUmTQns@7c<<36XiSxNQN%*Go!XMWV?hOlB0)|96cl+x>ynqIYftBG&$I) zhe{t)a4p7(K{^LG*8~ZUHQkrDA@IBr4qyID1diE41Dx$P%}eaj!Nml#32F2`xh#hR zG$M0ZZGuk&ztO>E?MQl)PR`X)AMEG1aH7kJcXeBi0SInn9lJbKFydC zV#@Z{M@Rw6Myom>1fj2Lgxq@PzpA(3cM`L3q0*XoCuZM#!Lyw2i~tka^3JZyN;LFdC6e%CW_A zbL7I^YVt~)n8elr25!O`iHN<9bn5^G`l2PE54M~Sr|l^hVLoUTWE@~HUyIEY8C(;L zWso_**g~wGS(Ic3m7SfqgRMSJmm`;IJ3EwaKJzjq4KCp`pewdqj5aW396j}!1X)^DPVmNeYG<0}Uqsjj;ho9*lRS9Y2H_pZv4##LY=dA2#zV`@ z+3a>9I3A$VM=-u1G=8;2>xp2}hsBrM@oeNmoVaz21Ku~mj{y&=3vD#OVj&1+;K)V@ zgPgbwCyK-yP~ez~5QaE0PY0I}v}6m0H&CKBz+bfrxLS>1;NYDW%|jIF;8KG3SEp*T z4lrQ*4K^E;`dtCar5O#`fze7zd1(?j+z7$eMT+eYJb$+8=TGtB3OGO@4JVp}IEEAM zILiXZnFygth&4L6lsJa-)Fzpv4Jrs4z*XS(2r+b*$7rSxuR2E~t4?xUaoHq~>2Ub6 zDYkllCANAA%W1Azl?a9DL>4$f0&i7{9dY7jmMj6p@H!4J+7JB#o- zo3fvJtDrU8BJ|);M|lYj^Ha-f`cgkC*aqR{jnf|VKHoM7FE5)_mSx)@yu6`(L~r(n znbv*F8`?)=d&(X-w2#C`V0dzwWMv(y-~ic-6ALi@vsXa|*87VfGD(OE8hr#)=IfN= zdA=P_j>d`BB!--}HI2cdP=oN+B0vbm$qRzxyF+j zII%4s37Cao$rJ>cF63d8vAJ5clzlYK1aS=d5V;IXOVH<>(!J`c-2-_gM41=^mIlcdvK(SrEP=Yib>BTZ?_iF};lnNjP*8RE-U{lDpp&E`mzV zPjo8rzu7R{6PUhQf{;EI;z}W`NEf27s66*{5mcHz#u8%N>1?R{@A|3%mYZ<;Li-B& zC-6VGhV>SV^uZKcaGp|PDla)*1eHHn%$8t7u#2Eh-okb+;zV7ZBMoZ$-y6k@O_ z)F7Az4H9t5&D8b~EH@2!N5IyEunmHXGOKHb^HNSI8ic%bVysWA_?2XNa#%6}L6c@l zFwGJu^}#fzR=UtMH0@&BhPP7CTsMMkUVb3d{Qq>DMWaw?Gs13?|Btts*<|QXM7hA2 zab_`1Yx@jAIoXl zfd2tP@7kDWh2D^HIYx&O92Xd(#0;Y)>=IPy609~6#5$bD4@0#$;fJt`RuNLPiqN8k zj|kqmWrJ^*JvfUHr?&#!deV>s%ifaGI&@1KY@sDAQ4>zADlE-z6Wj;frh`lG1&-+8 zGF9=T4dMMgil@nKw*DdnOy+@As{<}};dJ9cqDhT8!0zK9)eY(wGpdaB5c!umH4gf-BZ{ zA5LUxCnZa9Vo4%eadH%g-x-X-qELhI1;(vC@V_4iJcLj4Xl<~Vu(JrC=8WNVCgXJ2 zeDFo<&}p6wxf~~kC+ooIkjcf^Nm`|Ep=BnBt3DVz8YiYqE@0d&4Y~Vt)1!D*>CF z^gMwi*wU-Yk}s2l0X<-ypzjk@>L3gGJ`S`tfjxqXZ-BCuat2KenAsP7fZO zojmMv&M~5HAqJ0$e3_6FhQ~_=dh5?1KTF}k&uMtn3)yV;!6N!_rs3p$(>~aG9E|Ze z?ea5j9!@rSEzS#Y+Q&i!SP%AJV16UqfU^l_GtON&cjMfH(>_AuciKuYRL_;xKG+w7 z<@DJ~@Q3uYoq}^3PL|I;en`(Y;0Rxc)9w$Z`50#c+K=O_NZOJ5g$Q#!{!t|7aRqwC zVf_nV;>FJbB8-(nS-H7+EzN6HURz6ZUR}f5`nKwtyoQ?1^>u6VHdd{zt!t<`ZCuON z7Ne)(`n7BGs+u?EG&DBUQW92y&y|(BVtP*gfYh*pe2o-84byz5 zEMMu2>C>mrm@#8GuG7O}dn_x>`M~A5&bL*`Oc+g{&a0eSF%uI133R{~bb`P|n+GJ= z%$yOH*X<6=mpVN>|N9(PT65aD=r_ylbI%5yLwUh(^+3b^b-1U@2&?&%4tD8qb~r5D zWwp~C5h0EG0&|gA{AgU+jP)yrIif=h-Uu@&Kh@wPhn3q_n(zETO>_2MJ}rN9sq@bW z-g$ZMx%tki)0_)(ofDTk7fx#%o_fuWyy2<&Q__lt7i8q5=8T!JBEK}hVfxfmXQR(K zsHDufY596*e90-=b?d`M%G*vWcg57yw9=s%tLaW(iE~ZvjM5b=w-3*o(V3HXZrQ<2 zGY)PlLolo*w!4sQ_=+4REO7SsIa_^BZ;5jQ(>`)rnJ4ujoQ~L#y5Hrpe9nIBoUPXM z&h^fyZDIZMI3iPr%N%nr+%%(X=9S}zPMJT$5gFp*cgVDC*o^JNJp&K?^r?df54K_B z5}egX5j`V2e_7gb&-8;~F~<=zA|L=RV||u-jSG>P+9Z zJtsA9ItSmdw6V^uzDziCl=9+i+oloYGg7W|Wp2T)v`f>S1JI^z(~_k>|O?DCm+fpZTZs59(G3i^766@;`8#H4L%6@!&6hy?_>2al-o>YQ(H^z+Q$0EW>r~< zyIfU$O=T;Bo2u&DYE*08#+v5J*1EMDTC}!hojQAQ`P{j4DpX~2O;xphRKzSn%B1k3X7=v*5*%(Wt7WZhb>dwQp^0RkO0|Q89P%+=^v$ z=j1CpRG``#LM?6m*nq{jKxlj*G$9b07zm*k;i{=-ZQZ)MnreG!)HSSYWSy|rQI+fK z8`o6Tht}54u2AW6E}6Ha@|*>8mdrYRx=YtRyFYkkc%o9bHX8XJ6t6AC8h zPdwk3vvF-x+jKNxYt5FNjrovUYuh%i@#U=d<(%E(%fTLO`uc`8WR{z?z*yZ-MW?<^c&_HCs6g4fk&5vQk{K{sRVr41jln6Fv zTNCoCsjh2j!d{p|D6Fz;>zdKDwKerkHE7xB?n1f!+Ct_5wQ9bn$j+RXedrv8B{1x8K*Cgt+k6|<4A9%(3&+A_Nq>r#z6 z>+CsmD^%X5s^+|gbuD?#wT)OcH|EtgZmh{`!m?UbpWD*ZjIo(l!}e;a$=Tf4yrHG3 zYHf{vd|Kbs!a`lxT(d4Ge{6nUg_&@wdMk(BRt&qa?p|EJ0L84e`)l)By&Bt#v0kmJ ztF{KJz!fySSMZnzw-{~s*&QzSm<0U$VOZF?tc#HakZGB@)O~4&(H%TYM z&(=^stfsl4$xJiDzomxvEnKnUuWM>F_f6b>*2v9NKhe!LW!t!>6{V2++iQpR8@yYF zOyj_9Ne|dlrzLL-dKtplz0ZiWGLXD?Y%jv+4_6*DIE3KUY-KvkER zd4pkFxde~!b86NpOr-LPux@Rt+fq{>(4eZEDY`#Vo8Vo(r51M;bDNjOZE0K6*wl(W z18-{j6+yrYhYRakQ!PVFkG`#3_=^|gr$f#xUvPGyNcb5k+bX+aQn_{uI)`<})Y01qq^Vq5hGkjr1oWDQMneTw-a);8kjuePkI!Sc&K<*o~RFBzYeD5C7#Le^s5&O^n*K;Cwz*9JR%U4!0g z>AdP%sxgRkAM#Ftm0B+(%z1rHD_4B3H(}0s!wks__f0(zYisJ(*WzX0nX_k4@nsc^ zpE5Crdx@M23v(un`rqDM;Jpi9^nH)RQjSaF@c-8B7k^Oea9`QS2s!vNc~+dS-E&3c zHusegSGlfsUgOwh1zv8`j4#BC<2+aP)$`@)Y|)425eI#!%-2Gpa&#Y=FKI*L`7-oB z$=Qfc#AzRV(LO6K_DbhfEMa(BzHnvv?Sn60XT>FM|Dn3#Sq$-~)|D^2ZN1NS2F};| z|J;78kKKNu7uG6otm~gNpxDPJV#VCw_itdcF|v6CYO3lD_eC z!rO@-g!D;Y9_pVTko1WU%by>d^oz$TazRZe_J8Ezk~?YTafgDXey zaAK7Rw~y8K83B{fRfPWI`q;C!!NZAfgoXR-AB;rEiI2U)DKO<<2kW+d4*n9if<1ZS798Q(g#~yzTB;;`7qs;L9 z?T|;NxkNqrd&u@X4W0oDzbgJ2X z>}MPMfYt0khykaXtK);pxxt{0pVudTUZ40g`^XFW$h_kP52q>%3J5v%$JarXGwh>p z#`9z8;NjFC+lR`Fg91WM{D(}gXlx#?va778qZvBmQ%G`4#;C?U(VeSWc4p3iy zKdX<-8imF$?<247BRBSuxAc+Q`^Y!+k#FuJ{|GY6%ai4Mw2%B#k-1Mu!2RmCB2UwD ztopOayt5>rH@^~@bxOef#SO>w%{y5F?k8T6d5=p#j#-S9gZB;dJuLI(kOVbQzJX=S zXQ&mDJ{z_PX#I^Mb5ERr_54zixl$)!{k~r0axJH*+eGHRHv#MOL6N!NO~88mbCJ2v zO~Cs5Taoj%oUYyz+4viwz6g^ul@orU(qDo|z%S7cVnfKm`tfHP8P7dy0@l9*klV?Wz?ZK(97=y3p?3dOdPo5#~utOh6@%LmU86Mx6tnUMB z@P%(^GCaqIys+WZc0)Da_SuCCzU>Op1m0HIy5Kv@FpYWmw^f0UC_)wbeVP5n*NzDP zKqpMgXZGNG?a&vN_WNu5HFDqA+P0gJ7fZHEzdW;r;Ac{{#=JeZCBA0~e}5BvQ5R}s z-g}2?^t(L%5xh`k*vm>gg0C-58^Nr?-uu}vI>LO0eBLE*@U+=!-|N+ezKyi=XEsa{ zc$X9!5qJ|=S*f3QD)I7tQy_mP3s~66>{13_$MlT}zMZpU&`-gaYQfii!H;#!vy5Yv z5R>v%&c%)ROOGV(~SV>j3|rp^L=Li1)?ldhp07mPof;-NaQz(L_YE4 z{CQuZ%r6m=iNawd;xj}ZEi(55w3{IEG?9yi^MwnA+`H2LT;XcrIw9{{jBgh5 zJLi-y6Y@Ssd8crre~Cxy=le<}Qp@b|*EgntsgFZ@_|Lija_ z{J#^rl_{ql|5wPkze>jAHD=s#UU6J=KIw6bcs*_rujdcqvn8I4M*IvC@j4yi=l_@S z8BBMrjCc6a;~jqV_}yv#i$L`CO10Atd_?$f67l0$FQl77BHbDi{<=kfo9JPxqIa0T zzennE3_c@zJw73SEV3SNkOwn8ct7=UqV2&?M0PM9ay(_^tJ?|8m3ZAQh-Z7SoJ&ZQ zvmRtSvz}~cwj0wg7uxmjpp5jllDqH|C&HJ6Zwd9f)Tz{J%GkW?c@OIRP=4(Xypr+Y zO~QMHPYRzG{!Z8{{E_gG@Hyc~@;bBrlEos|lBmxf5)Tiz33Yj)uV%YJ-z3!Y0{VTl z+it$dOX_@Jr`Hisw>!vvFWXc1586}DZ&Yp$^=x0zf%_8u^M2AwHkk0E^y_s(#coa=`k zHy9j+)NeI^WitAr;QfaE$#Jus#JFL4N0qssIo5IS3>oAbE|PDi9MuX>Bw&rqU+8lr zeu|J!__Qw*E)pUutzRqD;}v$e#cKUFA%>KecMCaQ>F;jggTfyR*{_WMt?80nJw3Wp1q3fBsogqI3;3U3zPC45x)wD4u&Tf)ByzZ8BijEykmND}hz@UvcH zg+;=J!j-}cgj<9+2s7Q1URWeNOL(rZRd|JPm#|0pobVOl5#dL|uZ7M?lV7}$KRw3s zj}}f8&JivWt`cq#ZV_H3+#@_7d{D?=_NIS+C_zpX&K9l~@;AO2&!6}ppB4T__@?l< z@Jpd1%Gjp~CkST?%Z29)FA!cSyjA#s@UZYb;itm>(I%f!!eZfhLjF!T%iSj2CcHt| zE4)v5NcaoktHPtgzY9+a9Wlm#9EtUNpvc2Xtm7FX=aX2+$BR6R#CkqYig|C$c*hGH&iMB-%59T!HaPuEGEG7X1{FXG%Q(z7_3O3TuQ7!p*`fNcim_m*M_T z!tX=Er-UyFUm;=tj>zwc{ISSq^)u;L3O5M13a=5~DC{PY?>!{^9uoO2;b+2cguXaq zKVNt$iF8+zi?M$vQU3ddhlRfszD&aY4Uyj!`2&#`^f&333)c(VgxiIk!kb9=yMsjj zFA2XCj*d6_vBIUoN)qYTk+_LpPNLkqg!_dL3i(UKjDJb^3W@aZi2R}OYoQAp4BAJL zup1;YoUy;?g-z6CNu<-A~ z=z*r31IV*6zDbmSvT(le9N{`4es;pZp9kA=yDj9n^u7W|V)f2OcZ z;?EIzrO4|=-X^?8^fw7_7yXY!epKW`BZ*hlH;RzZ4GeB0b8N zNG`zp7ZT;0A>@x2Q9f5#E8IvT-4>BAC6WFy;TOUYiN-FQJQL3iB>eI3*O9A*4Z=%= zSCH_3oyeUe(*H#GS78h`-qaTeD}~n!e=7Wdguj$z!z^JQS&Z>RqC885YlRmIH<3tx zg~(TvNcW)dEg?Q~*80&T>uj0Y0_R|wY&>q*#c7Wop9uMzn=k#83HK9L_6`6nX3 zCi43v@=F|II7hfexSvFRcabx2Un5bj-w59kzDL6DW05}>`CE}=@liSBy(H2P5qX@* z#lka5wiSgkeTMQMgRlMk1ewgii`T6#hflIo#MiCH%GUA41D#;xmK= z!bxO4`d{P<67^XvY!J4Pu)9`xD~WR5P3Gc#fyh56k^Xtnza#v+#D76%<9%$ZVSizw zaEx%KaItW`@FL+Z;qAgFgf9w@2u}!IX(qo!;TYje;bP%B;a1`G!rO(93x6eiSNOTm znQrp&3daa%3Kt943ojPlAiPufW8urf_k>>wBQs1sDZ*UgEa6gNt?&}zZsA?R9}8a= z{z>?yFk*zsCrOwiED|mjt`lA)+$Fq2_=ND+!Xv`Zg^rOXAN=x;9v`EG(}ZUW*9hB$ z9l{>r!@^$(-xPi<{2yU_rpYHmI7wJ4TqSHI*Wo#U9F5<`BiCTREWA(nW8qUI>|Paq zApBMspJn1Rgp-5|g=>VHggb>jB+79&iSsEE<@mMm4dD?Ic7GvJ*Dpl=m&EgzFPUyM z3A=m}V``?z{QJ$6D@oYZ3L7Q9jl>+jQsi9{f3xU&$ZEXL7yZM+LnQKhio}}ty6FET z@?S`#`&9H_3;%~ix+t_MIY>BCm@6Dd;+{TJ%Ot*~09^K zyF|a2#52sDB+B&+iS~Fw^lys%vB;m1usbPo;uvE;l!Tu=k&8t>n}mJ6=r0ugc9Cxq zxtoODox-Oi{#lV<5&17Q5E{D;CXgx?CCIj}?hVoCTrLpV&BDaIuQy^rP2 zB9YH@k?~7RT92PT(!}o*X`WBQZk@=N3p<3J!fq0F_lW!;iSoQC{7e{;XY3M4l*3EH zZme*HuwK|Eyi9nb@Im3T!oLf7&v(p0zmV`hOqeOm7fu!ylPGto$V-Ih3)cx7h4`OV z+W)0Og@e!iE+K}rmir5FJJ&L98=8~IW#$iukh4WTQ@BuAAv{;ON?0ST6J9866J8>0 z7v3Q35_Su372ZQOEA_C*j|ra={qrKfD11%yZ;O0XcwF?Ki~N=FTj9Tj5tgZclyHFX z455Cnjdt;goGBb5R`=G2wCH z--X|jiYUMKUYD%--`TiVI1}xx_yMn!ePQ(VWDt}5Wk+N)9KG$;I~5L zbA_vf4Z>#OR^g?>D}^1xn}t2XJA^+H9uz(*e1=?v=UL&)!dHZE2;UL@S@<{MC&ClL zlfr)q`4a;4?-BMF4ipX*rV6u!*~00lzsP>! zA>q@)=Y+o&{#N+9@NMBS;rl}U`5pY96#09h6VC)3Co#hQLa#7Im@do|<_X6NrwC^V z=Lt)M{N)qovs73ktP@@+Y!hB8yh6A`c)jpO;VnY_xg-1^6!~%CVd2k(zYyxrBVqrl z$Zrde3O^8jEc`kkBvuiBNxj48O04{0HGXLj5^1 z;!lYD58-!0evy{t;!kanvBDujpD;_9EgUDDBrFon5ta%0vljHbT39Wt7d8pE2rm&{ zDb$}oBmHiX_X_VK&%%2W;lskmgf9qxEqqn@N8txT{rNQfd?E5bh5sY8`k8zN3h`Uz zI^SVJ{8+e_#|bA1i-dE8Wx{gd3gP*}3xo~A%Y@s6JB7Q1w+QzO?-f2M{IT$-!e0ts z622`wDm)?lhwwY0iZk`&FE6saV}*l+iNY*lws5R)qHu<=Sh!etj&PN5jqpOU6wkrJ zON8yhJ;IxW`-Qg)AN#)=yBqK*iaUcr)ID^UY!U+#CzB2urXOpT+0#C42=da3}7?efT9F#qUw$ow@aBh^JvI zJOh)l2c}^^9E3wL6SFV}Cu1(=VLr~q0$hMA%pvN>f=}RTbp0qaeBdr7ru`l z;U{<)kKl3q0UKL?8^w41d}JHaXJWFMqVEy0H}=I#&2B+31~V}Wr{WBpgSX)#T!OCO zkm5Z;dM&QU7jYxLZFbf7jkp^t@eBMKzr#AMV$W-Vt+5@Rjj3j5{ay?E<3JpX<1rg^ z@Mg1v`hVekT!@dFN&4OwOK~l}g0JHa+=ZW+`o8sZJcd=+*!n4HesgS(ov@FoYw!!v z^@mb=H0g2XRDG{X`Z~-d|8~-M;e1?(g{GeW80l5GhWs+~M)l7je>=Ww=IVEUq>teb z~o`FOWE zQ=dbTej1-6e>3SV_$K+gNmt?l^1mYe4cc88Y{+hTHK&^L%~(j-TP@Sl9ZcX?}fdjLoqlcExkC zCl1D8I2to>B3_TvaVE~g0$hYka5+ALkE82vr}Zu)U5=Y^3%dSyDz}650sIudz^~DM z@MrZ=4_ldibaM`DkDahL_Qe7CYs|zfyap%X9J~$ZVF513NAPic63eh0H{%w36aR_3 z@O?alhw&&L$CGsow(W0-ZSgGZjNQ=nGgSFB(wCV1^g73}I3BOTNjMc}U_Q>pd+|PW z{T3DfQPL$?iW~3+d>LIoM?LQ?((mBEaStBGBX}Htz=rK&+jkl!;OTf4cEE0!f@#i|_$ljw`VQpTTGGulO=< z#clWwzKeVCL;M`S!YT}Ot!4FAA5X>R*b0-dBX-Ag@qD}h2jUPMiI?GT@G6{&Gw^o2 z3m4%Md=l5-dMv|@xEbHTH*p8$=C>+Vry)R-7p2u#|!Wh z9EoFbJZ57K-hk8aW_109)t>W7FT_GD!bkCO{4=_K#d>}@=}lOHJ8>`W!$au$AM5#5 zq=U0#_0+^16a+2s3~YxzFctfv>#wZm*}cZ?`C~B)vvCIAjJM&PxCEEsAMsDP8lS<9 zxEbHTH}QS^01x6JJdQu$FZ7) z6Ys#g@%Q)#)Yr|yN!g6|q3`Z>dG7jAYWH{7v3iT?`jP4_vg>D>X6ik3y4i|x3iPDW zmew_4rm1sVwwa`Uwx*V)w+!z6xxw~H*Tg%z8+PA)NZJ+;=< zbwQb_{ce+ak@^jq>5R8BfN@q-Kb3*<^?BPtQ=iiwHit8giatjV>L@)*=Mi%Zzn8vT z+i&SBf>^(@@hYduUC(0!)YlU(|8z{mBk>@`vIG9E};6jX5|Or(iDT z;ar@D1-JlR{p$V63ev^664#n)zxC+qTj_GrTg@cBZ^i9cft9A(Yd;>uLwL+oJ654< z2c_#-y-WAIbyZG+rKM{R>H7Q0uH+|U4@|{$9E3yB#uu=7ndTtI6_DAab1>J`{*i~X zF&_(X0WQWuEH<@2t;7;6#WGW`vvS;IHc&qt+-jAEui<^!qV%{SfuKcl{9MXv^3Bl!2M1_LD5kHr1{< z==v$@xZwIJ%3RA&S9{`Yb3hQ}<6Kkw!8|N5b=+8hi%lIr3bDx4abyJ+o7!JiVu`8a zN-3^2wLh%KGE>Kya@=Il$yUirdLt5WMmhQlLNa-p|tNs(LJ#BkT zZA3@XT}`#eAkst4WR71d?~Y&AKFptOs-22RuQ1hKYe}y+)o$+iqUXEgi`vf}HHMrrrD8KUJ=-n|ag?%PRMm}>vS zq}_g}{h+DsS9*Sesr{h`=~Pp%r_rP{Ozj`Jq}_h1{bVueLR0%okaE+U8}qK7Aa(Bs z=Vbqv#>UPIQrr;yDHC*)hZNm-C&e;TVuK{sq!});Cc}>qS9{>Z+GT3SFN`~{dL+Zx zqJ89=@eJeS$3`_gaYpsnhH;kS?+Q|T)`{aB{>c2;h=)HhQ#WggtxR+T#8_^09K_m@ zLL(y9p6SL$tessmN@DGKvGEdX=huv!7=K>uW+(CI#YR(%KhKS;7=P9YgDBQ6V&fA2 zOp)pl7vn$M4aQh|mU~w9c#E~?y8#h@V!l29gpnC*hp-|Rrh1IV_(iJ6Vyr#ep8Yek zZS!gdZHynn%G3FtPYK<?OVQ20Qm)QZ z?M#@Nr?CJ3q>rQn9qt32LfvHN#PFm;uAAEHe=Da$rJJJVY@SVB^k|^R&y~~Zr`B>C zDbG*3Byf{XV?jeb(p^gD!X>fzk-}#OUH|+)7A;`>J`?+vpVqcbow|U z-Uy`|_>H8T2y_}cAzmZJv+D+1KU*&!Phanx5HCZq5|!sCD`(SmJ;K|YuXwtYaPdx& zKHmNMJG{NQO4zpf$;Vr$jBva{#YbRTFQi3We+Mkk&6# z<*YsInBv!OLnNNNhVu(kIsfOnNW4Ky_4$rwT0C7USI6^Xe*5E<{q{!Pcd92J?{ATK z`gj#L(CTQha+drk67PuOB`M$Hwb#RMZyl|GidNV22*r!H zzkC;omrzs_uR|!_nUQ$;iWhDVTdqxQR4&{esiAnCG~chEjinb}zimGfuU8~qMkt;g z<9)obk$8z}m{qm_Ce3!!m`J=l#ha`-R)6Q{;p62-;@NLK663_15{b84@zROcJrr+A zB;Fn!B*MpW&34nGNW8=cYue+Np?Di2@jh0i4lcc5ZYZAphB4e8$vQ~p zh2mMg*z}J`ysS{X^EBVr-=RpnV#TYp08EZJ*R*dR753{lBNDGd@hpF6*$i)Qs^ae2dp#55K(?k$59?GMy49-u6hm zs!+U(L-CG9;@MbXS(@)BzkWv|@$w$3+5ZNruwTFC`omU7#od&kle2FF%kY19h?Hyf zBjtKiE*4E~rgF63-EttN8+vDsr_Cv zZ9D9m*2kL_iP!T+eLm$YSLJ-Xn{Jl|B$%~F4F9ozh5@$69?DR<9ZvFnm(xiysY`IRbH;&(D-+H!4r zQh$WoW6ECDv+BjRH$x9AXYFCXA=cBim9eSd9*zIy6Vh+58LHNxT;(dYfK26IuZP8J is)sEzv^v3x#TxG;l;PvqwQndpSn+|5e-?zvm-`=bR#uGw literal 0 HcmV?d00001 diff --git a/Release/src/ili9341gfx.d b/Release/src/ili9341gfx.d new file mode 100644 index 0000000..5926eb3 --- /dev/null +++ b/Release/src/ili9341gfx.d @@ -0,0 +1,98 @@ +src/ili9341gfx.o: ../src/ili9341gfx.c ../include/ili9341.h \ + ../system/include/cmsis/stm32f0xx.h ../system/include/cmsis/core_cm0.h \ + ../system/include/cmsis/core_cmInstr.h \ + ../system/include/cmsis/cmsis_gcc.h \ + ../system/include/cmsis/core_cmFunc.h \ + ../system/include/cmsis/system_stm32f0xx.h ../include/stm32f0xx_conf.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_adc.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_can.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_cec.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_crc.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_crs.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_comp.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_dac.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_dma.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_exti.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_flash.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_spi.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_tim.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_usart.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_misc.h \ + ../include/ili9341gfx.h ../include/font_typedef.h ../include/glcdfont.h + +../include/ili9341.h: + +../system/include/cmsis/stm32f0xx.h: + +../system/include/cmsis/core_cm0.h: + +../system/include/cmsis/core_cmInstr.h: + +../system/include/cmsis/cmsis_gcc.h: + +../system/include/cmsis/core_cmFunc.h: + +../system/include/cmsis/system_stm32f0xx.h: + +../include/stm32f0xx_conf.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_adc.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_can.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_cec.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_crc.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_crs.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_comp.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_dac.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_dma.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_exti.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_flash.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_spi.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_tim.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_usart.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_misc.h: + +../include/ili9341gfx.h: + +../include/font_typedef.h: + +../include/glcdfont.h: diff --git a/Release/src/ili9341gfx.o b/Release/src/ili9341gfx.o new file mode 100644 index 0000000000000000000000000000000000000000..5746bda252868bd81bad9a554fe0b6fb5b845343 GIT binary patch literal 36428 zcmc(|34B!5`Tu|J+{t9JObB7gWDzDItRa&SBAb9A0R$3|RT0o38%atwvp`S;im1_A z1%e6$4HmTSrQ=53tJYl$T9vXWwpwiK+N#y+xBfn#bDukzjQIWjzpwx6_xjxzci!iD z&U2o#pL^%z&Sm3_(wT-~DElzf2-PDgwfIUM6IGxwLXB1VD)GUW-OqSew0qmL9M0mM z?aJvaKGLpSzT)UC^+-lxNYJgwDY!U$JzY9X|v@(;)CWk_w1<7IOW{#*y^~e-%I_T;h9vEx-#)G_hZfjUMZua z#JkB+lCmkhJg3vSM>vn584nwIMv1qn=^WPUvj?v~V0QMuJFO#TySsD1-Kp&Z?@nv) zqnw>DmN>Sibr@=A(cGiYm!x%c7tKEE8sb&+i}%co^Q!Ek6V9$<>Km^bIpu`8%f08; zB6TSCy{I8EyGn|UQR>jgC!M>Dk?PQ2PpZtQ?GMlC^13?JkTaBPw{zF)D`Ja`Lq_I+ z;(BF_{Wutv{m;WHtKPkO<}KH#oVY{#gM)MWACAg&bbX%kzSr!!I=DCZ{lEV6y|c?0 zw_F_yJ`{9zjtxe2y8Uk+?sMR?#|Py^AGU01X?8g?Pn}91l3kdd?ScNQl#||H2RA`) zX3|TJ@o~^ukQIFXlovMM?D$?bj?9l0tv(K#1s|RIyDRR^Fb})$l{iPiJE!W^$3dgu z=&88fu278z7Oz2#zOrgGbd6j2J%{cM4)&)Xt}1qPMeqI?wYejxI-Ok;wI^2>>*MN- z>N3viLXDhV@1{g`JsDKl>hQKxYRDk<`%{DbZk^g4mik@PZ!GGUczA?b3C}URpMvL2 z@H|mDyIB5l##ce-nK{A7QOmKYWgoGO?Pd9uF2z?t^US}V`lqYUo0hjs74GdJv2mRF z_Ng`MtDte_8>e;z%T?@lGqb!nX8SLcdwUc@(c6DAGwGTqgU;=4^mz0n*Y-*1^|;Qi zQxj)9_QZ6=q+A`04@T`6SE`0q1)}!cR-}#(K2=aUtm9uPj|HQ5)XhvEwm;z5kyomQ z-5zl4xgGI+PWemK@b?2z-4ncfAxEFeo~4FAA8_n^#``Gb@Bh*nET8G>Tvoh#X4*AT zJLAxT$JCZ0|8b{E!dTevy{E`HF)B4F=-73A(Zu6@R9f&i!SB5fL)(&?7MwR|#-M+C z@A7s9x9bsx@wts^eHQuD) zYp3kB;lE?_u48F0Bi+-d{2_1N6OJxpY+BIK8QVqgQHMr^;{JX-T91lo)WtaK7{2&Y*bj55xc474HewaySS4^j?>*kbugQJ5F6eS-v#z*CT zeAw0Xu{S4pThWV$`f1<$ilUGAm5}3vdnZSUfqC%psW`2@AMr5~a-4{<;>V2(zIp10 zYoWDvTy?;))!a5v4OVJo!eKQc_E3IF{I2v4PuKQfSMciK!Jyi~T%s{YRaT-Js)`3i zbs9s826YyiyHg9D+b0}Sqx+&QRQ8xdLrU^ee-UK*r&2s!n^M&d`q-rVMP(Tn%TYVk zh!cmONWmI$BBkUm*q(vB4y0Ok>IUYeMnA9pJ$tB6iRI1H^^mqW5PbNQW6#l3DktGY z4DzzlOI|nhdGV|_=FIy(2g^7UJb z)QQ>eO-ns_X^i*9RAbEE^}kp@t=Lz?vfNf`!^;vJ6}gtsJhN)32jn$MO`cF>iutUBP~v)DTzamXau}TWK8&y}OJ0o%m@< zT07UA_fK9{qH@&HZmim=n=YHvKD%E>%!cKdA6BaNIqORLcBFOeDpGH}c5-Zrqq7O} z@(r7U%e~RN61FZ+eK+mm66dy*j*D^4fYssP$;R0=B`PaEkk-++qkc|Wit;60gx2<6 z9eg__VfVE&UAu1aM(r;1J``N&b!`ixJ@=igoTD-pTy$NLI(A*~{5jD(lQuk+Qa*iq zkgdHrc+o61bVlGV#NHJ&rXC1JZ(TM^4ZAWBz4OYV%Z|HtUJff$?F|03Xw3;@()OTd z`=U82tAD_=dq+|I@v@n}LHtB@P4I@IRVTWFiJk5nuS9RUx2~Q!=-M3!^;cI1Jy@+1 zckb7t?=k3VPCBi1`NZavp54*6xVwyeW8B+mU!|@sKC|S>ptoaF(8yJP9P}Q0deX`I zqI-j9Y`XB2qs!cVLHaTG8!MtS9XpLIN8u)4;xuoO>yVjg^^jxNmUQPBHO#Rss_W)7 zUyeHA8|v6KO8U>$WvH$cV~4tFlu|zWc66;tS&o*E>bk$^gCowavs2R2oLDPV_6x^7 zB?-Gx67QyvCm6;UXb#u{|e>4jA2Rl!lss8mNbNjzr&+ItX z%orQf>F9Fovg#LGxGAIWv{+?i#BNJ1ia8Xs%dX?)>9MeL!g{KT?dsDR)8**w)3t0+ zpY2hvJG)|cccnTzpY+Z>RV3?A!HLx~(|@Lh#A(Z@uDIPdr=n&4=o>mpId)m?Hom0q zR<6$X7bP4&Q_{tpFfvyU+FcmGJs$0mgDX2*Dh{7b9L=0`unl_PNnGhJw={lUJ1F6_U($t ziX3}rKqy6gmr=0X9pAY>_~5BNCI1YqwNIUh?%G%M_#3e$MuE3uzx2)*r*tl7zxkKb zuesK`>rhu6h#e7sII|>kc4~WE$Lp%giCdpwj5!#xBVC&T8w zZYajjquLQQF$S6z6XA&~wIG7bBR@m+N zPbeJkIfgc~^oe}}_y#rhmq^)PB|7JUvBmg!7^f~OGTIAYS+4PU=mgJW2)ia)#k~RT z?3!fdl)~^?47)ui(TJ|e499z3g&)@xh7&y(vFuYB?(b=23!lxf*Rzx1LWa{lSJ2Ni zhJC8FHzh5h*Lf_nGLm*sSU|yPsM!0U+XN$Bk-@6( zWMs6}a9#KW{plvVh(YD)V6p&nb$YIX##Qz#KHVM`z*WwQcc5|TD)tZf;3+;6okt<` zOZYiFxLs}NS>>r=>DDl)Je%oZt@aEL90Unl&~G)a2lIeFfhOg8NL%&^G%MG`+OSVx zt#Tb?(Cx`(+x%u8!ttI0`g(-ngg$}tRm%0~G31@-xrC*EjP_p78|>L51M4x|1L%6t4pblx@X4>hVQr7<{?MppUB(B@~>#t;HX7RLGrcCr%A_5NFL5K&5lbDGdcMMnzcDN9}AP)@#$Kl&88)gMOw;bzgfykeKS7;bmuj>5$tg5judA~-`BN6O+rh#w^>Pfm_Bl9iXBplp z^swK-ky&bZzhqtSaBPF&afkN+9+IFPW;Y23~ zq;B%xA}XxOwJ1%#6H$rIefaGE92{~Cg;`Q%ch0M{VJeQT9vh_o95H%1hi8l`-S1o5sRMjhgl^|T$T!z#HGF|J_-vvDT>mBMg?J?%y|taqZ5 zK2t`)S%T|q<6b(rpAA^3!z$UuzL};4SF*tsrpQX%Wm20J)!mG|031y;_nn9e4dgMXT zh;X8l6LJuzhdoMf(rUI%EJq6OE_BuoHMowg=Qp{&46b7Cx#nVo%`}9gy`zzh?{_eF z^201f6{CH{P@1ujqqCMU{sTra6g|3{QBTq;ZykaeB?!7Jxm;y*!)wf03W|)`2*#fE z8IomwiKy7gM-hxd8$t0b%F{~`Kqtmd3A1=GQqd5pcs5dTEh-Z`HO$8q$gG!QN2JBi zBQ5%&jIn348Kk8B(UP%+J&O4BIOnU#*^`0l#YHiwJTJpdoQq+nXDdGAq8WC3Zh@aT zx4v8Qe2zAWi(%N~nT6`d>189qGX`xF7e{>`&s)^TGo0wr_g5Z<`+6$qKY`&S&+qXW z*N5SLo||Z&$Z&tpb1Y9^h6i|7&}S0E13g(B#r+sg_OK7*`ZMhH9HspLhEp(@rh?{g zXgcs~6x8_!${$PR7YGd5i@>)|<@_^*O!jEJi+X9I_3#uQ{Z2@caT%J~h@)M`rT8%7 z^&l98mNXI=lyt+X=o6;68!n8*FohTOGx~-p?xrH?P>+ufP*|fM>m^SA9;vtiZP&}< zmPo~PRJ)hOoJhrZ)UcODVWgsgPW$%^lg#<_F@Viz6)bBX3w8rq23L2S#-6qDN)7F# z*$sNhWz4V&W!#9b)=JHQG&~g_*TZahCIYlqBYw?{HaZNdN5XoewpLk}Bhpxd=D}Sd z3%6%~U!_LDV2wd{70_q@l4;i(oSj=JbEq2a1}$$y%Iv2Zf1QqhhVsvm(CE}MM`ku_ zW89!+6BWrmpYlz{muUSdkVi9fW0#h*CqZdoHvoCn()KerFmBaxyeZB8hVnrz4@b7y zyf7P&YI#27Ve6FfxRyR*>^e5n69(Hi7PZTn3KuoVts()Y4a#^-*I3}(b_co8 z(S{qzt+2TZjfHq4&r;?Zi=ww3+=x5m%v{H1%CS}fPDd-U9J3Yf3X$Xpo8@_98j6sA zCv^FH@uBioN{(T6Qtv*(- zmFOtmm5hA~6@LcmY~5q$>WFxh(dxCuTIPLF_QkBo5-l%*?B5BW?8V<8aag;C_u}xW zC`Y{)ISh}N(C|82rTZ)uPVPWFs_`ZKg!kEW@gL^f+%}y9gdOJR-BdeVpM`eNCM$P1 z5Er%Wv5gEYa&B9UOVIEFn6U)IU$Xf#;6j@Woo>F@1pt<}jB)%ddek=>S2F+O~23Pbp zkm|IdEKi6E0AqZ%_E4}^8FLKYeH4^eBV3}x7z=S|G@}8@ z)nxRtv1b9Ab~3VPpzQ)gPDU$(Bq1nUG>l-BFQfB@(#V7 z?T_S%i^*wn#ME4cbi6JXwqwkE#HtO!C8ltlEzN^8t-Vc*1 z;UYYJ6;!;bb!=-=Gq}zgrM#*cTwG^1LE?SWIs6)6MVwQ^SZy@~iO`wmzQ$(vwq>Bx>I$)J!1I-wM zq8ejpVm>G(9Me-m9iisz=2DQ2L@G;{V-8X(gJD}SlNN)*6i;x?N$ydU@D7N_hd7Nr z$>{ZQ4?}euuT;+<@Gb+tM_>TXamVn{gtPPmd^onL(oZ#=bLplXF7m0!XKX%g^O-WA ze)8#c?zi}$*@W*92;!U&jb(f+&Ix_-aUla~__!aZe-sQk3-3gE_3c<7A*R6DGx-6*n7&a}HBP zltjaos}C&k9bc@X80}6r;^LUZfDq#eOCM_(v-?pSmjOq-9>wxWT*kX zd&5L{NeLB28>dRCwU8#&)k1ntI;GC&hq_Nj?t_>+a~WJXqB#6&?9BHy z#-J1`uH;qJEF~&E-9)T&ddkRf)bdQJ|^f(NkBp2)EM+Oka=nl@k2Dv%B+lo;1 zJUaqkcg{fkLSsqt(zpwBd*w$dmS}7obaYbCQ)t|V(wgpV>v6PZ8OB@LVpj_hUHWWCfaE|VmgLPQCJ$(xVT5e zH6koG#Le(yRCBO$JX(#9<Zz+2A4(p0ZcZ&+#i66X8|GLgSYP42_Xe z-GV5_+&DzBV)GcV`|w;knw-**U=+5YJ&ykKu`zIBc9N~#RRv@ zTxtz&$1=O)ahEU-r>XE=nE`GE*pUoRw<8${;55_%f_F>NOoT7k-4wVrfH-0&PVJC^ z-CDnhxX0G>3$72RHew(Xr=b=ROL02Xw&^6l(`p+AHcJF~(vD!ji)LU7l1-vhpq~1e ziO<!=tp&g!2-)`6#>U?$wM+Jf?i9YxzO@5DoBO=t83@{Zc zbYLULuUETRL`d-tY-EuNEj=NnI}j?J?iQAhnQBiAaH|5tkl^ss`i7oSbs$s;mQ5}Y#7v1vJ-aEFiR^LB)--A_B<5hAWqbXrC@Clv}0E?Mypoz#BvWoA9lAVVHCxF|9xuG#cE*xoDl|Y z2D&*8=(oQe$1ioESlij@QigkH-bre`<$Z0B_n!1Wj0;b{SJ&)3jt1%Vo~eb_Vr^yY z^~|zsVax=ET1Y&F(^SnHLmhJ$6s*~h)74Bj!x|Jc+iC{8FieCEQ#I;`mC;Eskl2TX zS%t$wX=(q`|1u5j*=YZpeC#rEC(W8^i#cNk;ly}l8@;82i;n=-{98F&&kj85IwHv$X>sjq<3Af?+iP}yl|AZ5(DbWXQgGMHNI8D`NbWcEFDo&b{l{jHe=)XFt`2+_p zE$#siN|<~LC#C@5(5<@I3An5vk*R~{WdVABvS+%W&?*xru4ly4I9Y)O-Qm?)(9P;> z!5OF4qQE$II5NAb=!jH)0maui(RYMZ*#!jmk4&}3=w_{1VKnu@jl7Ans(3!Z;%PlI zv5zDKusRZqX8{+6rW}pj+F%i38!Y;P0a{KQ#=^?MwN$LB4?pMyIwvW%PBKySWPcrQ z(PWOahbnZ44|kXkH+@*?wz6-bzo1h7|{2$6U)(oGg?j9HhqU9y_>>Tt(a&jSSBV5S%g<% zF(T2dO99#;7+HnmmiirlmsMEs$~w#njt26rU;)5vU|?s^vx1z@737GXnQM)1E*u<} zVXH8wun#92j^r$6feUvS>D`>Z{JVQdLE(0-m}psW-J-{kgWR4M(_ zE$>t9)q#3D-AhRKp{~uszX5KTVx3^BNmh{HdK!(}pl!2UgSsiu6U=NUyxI7VcCrYa zruYOGh6|n4SV4lz6t3QduCZC&Jxf;TzLmZ>zp<{{)7-ia*qKBaOoseJ10S?lhzZ+Z zL9b@eKlrxs?lC>@xUmC?@p83Uj^4E?w9hqiQkE7+h-c z#6gov@21FAJ`VR_E+3R@@fDg17AMxSLri+NT|8cU5rrZ@F9ds5$tPgh%v;mg$Uw6 zC;|a}Y{4g12OLiQ$qx=>9!$*R$H;!?(ci)k$iocdWrbIQy*TZo1_9gd350DsJ3c%O*IoOdeuwx9*RyV;aB}?Gf)x3;08uC1~vx1nlnU2S=8eOX0KZ9~;*<673WSb7>( zS5)MdHP`1fG&WS_RF#$2=8pG|^^dXroz8(`zUx|AtLkm5+=}{^+7{}i7l!OoBZSTgX%TK|t%NP~=$z)Ns)klE zfgV3Lu>^!sc!be7R#5^it@UH`SLL<0L+c9V4*`FkTGiNKWo$Wyrn;`8l3FVs-x+mJ zo8yd3GwzWogEOWqo9Zyo)^-H`s*ssDrNn`saD{Y(PNT~@jV}8%x;N2#8G|zh=T`U4 zz$3~%PLC;CXXH9uVaoSTr#uB^u5vh?uF0-khZ$!637p?MI0JF`4G2CR{4iTx7ha)N zlU?)1nhlf9KE5H#7@Nlr^ODJCjDPUdsd&tmVwzv$+|A~bhTnX1gFo+z(rvkBU!Qrg zzqD;|Zbn{SH9qrm%|8Agc*&faca`O3vgPF#6MGMnd}fkAue0<~+fBE2!%w(r@uLXi zN1Cnom=ou;BbjkAKRW5a#orj2n_V3xd4r~APoJ7+woNt@CxdaD&4o)%zt3Fgqlr1x zXEr=y#<-W72}_y0i(0D@T;`BfkR0an&1MW+#Bh($@){P>F#9cKLl~~5u4QH$Ep^Zx z)~-)F41Y;(u9>sB&|KzE%gV}a%bjv0(~L(+9?zR1B*M!OGHUWO zrj+Eh)lMle+gr_8zggRAru%P7&oZ-DU67NJlaXh}`^;uvhUvlC?6Z;JD_oYTM_gX! zvdpQ|SOD`vtL8)4R2Tue%cnA2h!4{&XS8V!T54YCHwXEvQBkvX4*ZWb<0hLgs-?G% zE;JwBFxm9ZF+W=GGk2Ii%}#TU`LUKK=amf3$Q)B}`QVJUjKO2h9-LuT`^|&K}e|#72+2;vcpwkoh?l?pUhl~rOLY^o|l z%-ZJK)+&W%aBMye%UUX0YwN25rTMHrsf!2Dst!Qa(ZLBXxn$|L85NOaI5f^Bws!)NtaRp^M6YY0x zZDnhXS{IcvSH)cZKxcq$Ih~}!gsy)P*LM+u3A&uf>G?tA2()V-uMfBIrSAyZBr^5n^EGN`aH<3HE2{{PPH%R z+!kLBuGUkk8`_Xn&Z_#VmX@;WsvPuRb!*KO7_YJ#C5J_Zw5qKEgSxRH2P2O}`c;)> zt!3fzD%2b8-GCc{YNh*9k1e&fxvWVB(wK1^N&23_s_;6g__}aO znW%RAbGGP4tZJxe)cLeE)FOnTRMFVDx)xkpiE(M&=7c7f9!Z>e0oJ2ebWI&^$O4iN zrzoP zEi-4A&LAsmQI%RW%&NMw>Xv-9NZ-a4H#S!l>j`TWvGm;HlEA_l#Y+}0ntk4kz+$V3 z+wGE9H8(djs*19vfXpDh(qR1QMWcvw1`D3uqJiedwVbJ#9D(|>b~ai|1;;JdJ}bbP zRe>?rfZtB)_84O=5&^75SOM}PR!`|Zt5o&^Yb_tvvRGAL)m)8!TW2*?Xo0X6u0TU= zV|h!2PibeiQMF!s8|usI&?Jg2QqkC^XIWW&eVMLnby>ZtFKfZ#!jV{4%QZD8>$~Q@Lx(nsXagwd6L}VAQqM=higVSLHTgp)afR zw=^|lz~@$R9=BBGtZi&w-O^N6QKfI-tD9O_nv0vOR^{Z4&C6YA&0^JSnCO1M%2tnM z&0c=(vDehrQX|WCO~C5o-dC+PylP>s)|U$VN}-p;$}&BLu*Bf&2Ua{i5HR=Pg$a0R zvF&k@u`V%O4`JS}he`{+9@Mp#$+%SQ*0N`Hzv9)hU4O3Ack&!9x<~AiBi?Fb#9)P9 z%i=UPm0gUk(0yOo*jCOfN=02`OBKFfG-FMt;W`@HPH@qwYsQj;POHL&adzo!et!wH zjty`|>cyn0iap-c*g}aHt#V$9S{v6^NbPiPKb)K#ql(MDwJ6m#aQ)OJs%&Wt)Sw|) zIyOkb1ifZ8wzVp&L97mI*BurpuUoAf#x64IT~=9%D;*lX94j`{qH|VTvxlqytQoV< znYCD7FvE(8*^jF;DzT=jnF~28BMU^RjM7c4Xfq1677+-`@X)=+rjxEs^&GkvqJl@`OrgBnO-wd55Ss6 z{6gHmVPh}xHVijoGMuFIF=DZLqD=y*g>~l_T8k@dTbk<1*4bC~a510lq;H;dUbQWi zSf+G;X_-qvpt`CRnkr6reg7jJ9Oj0X&2TYa$)c~$DK4Jm8!_h0N#k>P?~rqGe$Kd& z|G#f0xZM(u^LreIa;#5?_k^~q7{@J`X$kHvj_V95A((Cv}pR}t}f;qlzY>J?v< zurfTJ+j0@{dG^*Gi!nmSTWvHg4?-C?c9by;!6;npd7CyjPr2fw=f)UG&i=*#BiZyC zDMqR>2wDH&;C_>RIMwIh+hG#>4&fr?-g{;yw|Bx06WcloVKTQf@uao(G8uG)ZEw=d z#1>C)`zYPlJ@rLrg&ijLdwSbPN7!TcC+sk>AKlwNCc++1xrZGlHmiHv$3@uVInJ=d zRGtWXkG5wYSqFY15_XuXPlSCRZQnEg@KAo(VWRbVm#1%pJzKZuFjc<@`+nL!F=Wy& z6k@ z>cNP3{<$GMzvsoCHBZ8PYFLIXLfTM9Aky$Tbo2r4jNK5iYxc!R}@{tJn6lD8gef00GL0;#QIN#xnCcLgCVLtP%RFn_s_%y|b0Vs1# zOu~FCWac=i>x=orH_3$e*Ico;;{Wme`4MtCWc<@7>;IDoxj90=?V313h1S?EM6mHo|!EX_I8)~M#`+~dohDv_h$K8AAiyv>;SwMZ`F0^;3P*Q6xaTMaY zQ;y?l)>`E#Qp!ge3o_RlN1?>eh=`vV5kD&;9t(J{^d%ATrPf?@%(L!$nGfeR^XGkt zV}Zz6__cm9o?U`I7SHm0Cgf97l=;Y1?D+aZ8CN*F;iHogVsjk#`Co5&nnm zfco-@EtYQu345+Zgg+HtC)_Q(T^JM| z7wT~izj|DQ(WaG8fl#j(&@UC4-$PiACgFNvhmhl$@y`km2|pBmA><8*uCI`fi%{mX z%j7a4=K1_(2Sd`~0wd_5mI zTX>$ZLf9m{On8m(CgFbJuZ3R=quk+ZQCFDJ`zy%M>OELVzenW6nU zqsRxy2E4mP3)?EZUh`+-v`Z#yaeWtgxG-Nh zl`O<>XhlAkEW&+*$SX-K?o}dROyWATM&!*Tu1i;mjQ?&z--qoKc|Tc0fJAwo622_)ha~#6Un0A)O~~?iNVG$a$oVA7J4NIoiC-%6g(T{^ ziiF+8qF*EOPer~`)=OW)E@*a_I7x``y=?;kg5z#+M z!v7n>KK(7ZM0mOI1`_$~6FxyA{})7lRpevBzY4#T_!xWkc^--L^xVF zgGB$;3EM=!L3ovLtMCRAe(w_gUigJD-HZ4fypV<*kNa7XON0$1+OJu-PI#Gci?Bm@ zy|7cbTX>65;ox-=x7V6z3Qa6WnlRH$7ozA|9w|gpEf)x92yrRb`uW1e!U_`WTeYx3 z*eu*4>=0fr>=f=6-XgqBc&G3|;ctXb3!f9dE__S)uJF&ozX?APek=T5=;HT3l%IRt zWItiDkbB$IX9}~0xkCO{j`5R)#lmxh`ui&47m2(=xKhZyZ>Hx@=EyeTI^j=++yiI) zjl$i+TZOj??-K@v&j_Cva({|`jtbusejxlr_zxjpPD=Y|A@{l|Ckgr1W6FbtBZQ-c ze3>cZrwL~XONEPs+~cMlUvNs+3tNTlLcZ{n@jnyZBz_-`S9*+zT){T+-mEjdXzP{YVHFX6YsSndPBEF;UbOTyQLZwZeI-xGcy{7CqjQ12(f-*+PO z6~XkMC`=Zn3Hi!k#`}e53MUGu31U0Bej(&5d?`l@`6ge=sY1Tcm$Kdu1NA-_ zSR{JBjMm}9>ji}?gnB;=`k#p0AZ!<|7j6-D2(K6F{V}B9E%GhGUkdLQ-Y?|;3&e6f zA$(f+qVQGWo5DW|-xKns@J#=a@H64Rgx?DB%Q0=o|7eN!dVdY1jvRd}259^nC@-nT=!ekbxP z!b3v7Q<(Msi|}LN=R%YFUWktt_7V0IrU?fN`PN6;j}@LJJX?5c)lUb-BH?Obqj0@&lTh!gBK0ONASSdLJ6`*ND7BxKr3I+$ZGgtm*F|;qQbm3Xclk5q={4htT9cFw*ml*yKQA zs&K4uyl|?pNH|+KSIC!X(~sW&25UsF6SfG~3O5Kh3$GUbT)0EHQ@B^SUwFUpVc`?P zr-gc79OZab*kT@qX{JToeN3qtND& z`ND;AOqTfp-Dr^!rP~!zI=+xZIZ8#IPog|4L|#dvTy-Khk#OE2^0g$&smBkT?xBo! zy+h*fAyMvwB0om@tpAXS5W#u4# z+oxG$hxkaY^6Q^;`OEPmKtC0J`}bsF4=elelWr@r_p`(LndKjil;@LwEM7mC{G*XS zNNhhbYd?+LlQJwuo=ZM$94lx2KJ7=N_4CO;jP3QL^68^PPy7COw0_L@^wB>O#b<%p zF@F6(uufW8Ro+&O2Z8b9eZLhhD=)_n>Qz`Qe|8)umf?q?)m7+ScA}N$hZ_CEZHdM3 zQ2vU>`g*<_AS~6Y=Cb-K<;Rcu{bjAK&9&uit#JFlIMQH?X{vZ_;!$8B^oc2}j|_a$ z4pUYik#>yZF&w8G=l^6k8a9#nVv2+gJKxz6cAUdmAuH>eMsWsCY|E%ZoIF0fKq(){ z>4qgl|80=vT7@$_-yM)o=dT?4aDVP)J^rv=81i>zgg>qor}MWt!rzE6f6T{;ljYlo zGrWAqA)n4)H}v7A%9$Z!~O9Zce?WN z+8gd~Ygm18yB6{{F2WzLg_G?{iXEVzi4XU;6aHR+p7q6J10jD)BK+;g;QSEr_F=nT z5K+FB%Pn8@hf7w-Uu%TFYcY}en;iSFgG~|sw!$B;OZ1n5lXmQH{CADL+K(E9QU{Ee`ki5?~WAz+6YN4wj+wpCBuOE3!WHy`r#;U0qd`f%Fy;NOnJ{q4%abLw_uz|M~Q zD8lYxRJMo%N)FrZLj=O}EnJQJ4h&T0I|Qel@3#^DzB$Xfe~I+>uLyr1ZnW;gR!s+FW<^d=wImQk88YLK3{~t&!=GDoeQoUw!icUe|tA0 zU)a#!NSwAm{tcaJsORykV*Fhi`^omfIG*^AAbZ(eJ}>t}u;YEOeK21h ztXp_}6E9clB=jr?Zs9`ZTL3$ZJr-RbdGqnSrY(TBYZ9iRqY`#}Z5?gT#>spWaWYT% a3mui`W4|OUq3w@rT)5q5C|}uW?EVjJ3;8wx literal 0 HcmV?d00001 diff --git a/Release/src/main.d b/Release/src/main.d new file mode 100644 index 0000000..aae29d2 --- /dev/null +++ b/Release/src/main.d @@ -0,0 +1,115 @@ +src/main.o: ../src/main.c ../system/include/cmsis/stm32f0xx.h \ + ../system/include/cmsis/core_cm0.h \ + ../system/include/cmsis/core_cmInstr.h \ + ../system/include/cmsis/cmsis_gcc.h \ + ../system/include/cmsis/core_cmFunc.h \ + ../system/include/cmsis/system_stm32f0xx.h ../include/stm32f0xx_conf.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_adc.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_can.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_cec.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_crc.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_crs.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_comp.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_dac.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_dma.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_exti.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_flash.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_spi.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_tim.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_usart.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_misc.h \ + ../include/ili9341.h ../include/ili9341gfx.h ../include/font_typedef.h \ + ../include/font_Arial.h ../include/glcdfont.h ../include/delay.h \ + ../include/i2c.h ../include/si5351a.h ../include/i2c.h \ + ../include/delay.h ../include/24aaxx.h + +../system/include/cmsis/stm32f0xx.h: + +../system/include/cmsis/core_cm0.h: + +../system/include/cmsis/core_cmInstr.h: + +../system/include/cmsis/cmsis_gcc.h: + +../system/include/cmsis/core_cmFunc.h: + +../system/include/cmsis/system_stm32f0xx.h: + +../include/stm32f0xx_conf.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_adc.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_can.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_cec.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_crc.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_crs.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_comp.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_dac.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_dma.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_exti.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_flash.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_spi.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_tim.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_usart.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_misc.h: + +../include/ili9341.h: + +../include/ili9341gfx.h: + +../include/font_typedef.h: + +../include/font_Arial.h: + +../include/glcdfont.h: + +../include/delay.h: + +../include/i2c.h: + +../include/si5351a.h: + +../include/i2c.h: + +../include/delay.h: + +../include/24aaxx.h: diff --git a/Release/src/main.o b/Release/src/main.o new file mode 100644 index 0000000000000000000000000000000000000000..d358ebcb09d18e5d9ff5f07b014e1a502d35456f GIT binary patch literal 75888 zcmd?Sdtg-6wLiYkIg`mGlSu*zOkTh|0wz52;x#}LLM9-|1jqxCK(9$iLK1-x@_?Wf zqNqjGmJn(sLBVHLZ0k*>wN+ZGt+nd4iLI@Owb)wITJ>`K&|d46-{-UUnaKq7_Iuku ze+Ty2Yp=ETdhNCM+2@>@%--eYD>O|L!9x=nVyq=Zd!lSb%##cmqF3w{5oOlWgcf^I zLfvt%r7YDlp~db`sB6DmB#M<6;x1ee7P0c6=jDhA2ZT2&QoLf!op|6-r1pyDsV>sX z6554F52Un%-#iSjQ5N4*G-MPdwD-mMa>jvgs0B0&5cj`)2I+}o@bm1MX5=t6CxHHORD|WviKs)EAbx9S5+ME*K&%6 zl9Hk_#IH18`{i*$^tPXLNPQN>ih9#ES5o__XNFRvqGs7&&6#U&kMkxKJu?)Q5&3$~ z+(5hV-U@H8oV#)8zeaifD|E)6w3P{0b%9VjR)$BuD@XlR4c*a$zrDdecwc?Y;BV_2(q7w@@YwlN6NK)Xx#)WTPliOM7(R5) zmL2n|Px=xuv8Z%cbZ_(*gw-AU5WUk63a_^C`$J+t%R4kA4xJi}GAV)52-&B!^qCSb{ghk>mc&8Q>1&qF{{12r@Pq(^T{N&h|Y<1cDjloQ@Ubc;cKN*cZ zk=nCyX!Vi}Q~Q^l9kTVG9*s7&<(S&COl=XSwpmhJrqpH)X-f}8eu}o3{>YHF$b*MW zZOctZZ15h8+Djj9SdrzM<&;Yez+P^hnlBF|vC!VwO0wb2Rqh=htd;&kpSv z)v|R^J{Z|Ls%QUs*vS6duqFFHhppM~4coHCaQ*0cj5reKjyuKin>BI%q?qxMCqm2> z^Te%>y)3jthIOhwe{KPbn1& zBL7zMfn5@|9v{?1(mKeK^pIS<-%M zuQ50|?}c7*C*vdTbX??f?ueL^Fg#)Q^jBTdySO-S*by};EzWSOsP7xn`pvj3yfE~W z(J{Q<|EI8)(f>!}lImkUk(zwxj^B=Ivn?ZY7hh3)#j^K?em&|Iv5WM~$XCUjh~cc6 zza0LP%%z`=-ZRynIsEE}qiX)^zW9?j6x&B`Ew+q^S+_OjYzHIzEQcn0#B}S!RY{Y2e_Uoik<#n(475KR zXkC#aj;@H$D}BE72MsF*T9R67TF$o6qSFD(Kx)tEP<7Fx#l8{ElTh3^95I+sJbn1P ztJ1u4@)o;YLVTH=nLV4l+6T)sZHRpviJKVbKwz7mCdy(acR)niu`>oRR_`Le(>wiF>2TZT^Y%%it za|X`upMwP>XU{Ehd!--3{dsBI9(mR!&NgtL_{I8b$_Ceevv~e+^z_{UD^{kcfeiCX zW<8=ZNAtwuYHWXqHmh^A+bVNdE3h7XZ%DYQ_mtH8l+=6jT)os2IY%3|%+W_0WJ{a# z(~(UInrE3Uh7(6MX$R*4Be?;Y8jMVp@U0YV@o+CZRLmYK=jxSepgOr+alrenrIJ`yLIPKK5VIi<1lLvL*_}GUhtueO` z*$zha#R%cTc=Sgfq9%{~PtuC{vS*G^>$2v#en^v+sB_ku^cb~M2y*D2TgGwZm~y5| zIT@cJN683MFP2eg%24rWbSp0}wnfQsnHnyZ@!?apr!0>pU4D8+xc^x4M68U%`I9$2 zrac;c(B2nwsG>B+;}Q;e^@%>Q@wy3j$KQp^$?(qN=o6{e5!zO~GO)7rgQS PwTf zJ3u z7Jo{qRYEyA=XN+Rq8{`PLhl4qZ(YYrZbRlpT&cR^sIwZ8h{w*GQAS9Gc)4_oc>0fa z@rV28i#fR(_d7+!*fAsT9VKIVc;jOUC#{Dp2P66-`(JWfPTc2u{Q%<;%>P80Ini#V z!?-8|Vx>1F;~QK+BV?{mH3wjPS?w;iSS=iKQlZ;?^) zN*R_D$=4d5@Z7hYsJT`jhe?r~AHh=96I2o2BjFuE)l#Esb> z%w5`TLy1P=fw>#3+7izs5^K!fwc2iI4 zbx|QN#_WH7tu$B0J>34BlO3*`9*dP@7;j!vbDz)sLHJI>UaBH=(0eu_V6e>ez>=~fE!lcxB7SM zyHj;*-e8jOoImLllYyL4dedWr*zehU^nQI%yK6A%?9kB_{X<6oiQ=@M=>yftXNN?# zHk^QaT6@p)Nr&4vr0H{C9m|c79@W#WCXOlqa_V1j(Or z#UBq(@Dv7;TcZ6bbuLeG%LHH=S{mwNyqj9EgPUm`G2EM44){0KpvXr8O-c%#O-=H*DObv=-Scj|xe~hQ0uAwEN$TsWmGOoRzhSo!{rJ=sp zTi<$Cx0_I^VfXjC8|oWce*&nXUh~$qCi&~?dtDE-7HJv&KdXIa~w7jfE`(LX&?K!d^nBL*ik+K8V+gl939b;n? zr7fuzyWd}T-mAG&HGloSmbw0Ybq1cm7k?X);8_ix-r)TG!0EDqy3=K^)g40Sko$Xq?*a2YU~Vum4+fqpO=+1XPJ2@^ z)<-={>b?^=BvNiVyyCd$WpQTHhK4TBv|AVZjmuK@rQ8P1HxBIo_ceL2eBglY?{y8_ z@X?oquKPdwf_7Qmij@7}=zS!Rbkmtli^Q?(Q}#Eyi1}*Zt7U07y|yW3zp;?*fm`4^ zsIaN`-hk?LWdHH9d)6=}Df{z)@AWQj8APTosXH3j(7K`iG0$LNqJ|mZPp+%Mxdvm$ zNcJ+ii0MFR>^c7CwMDL!ZZTEXw*^|vyPC4+%TABKt8t5)Wyaj3&Vj2vqCeU_(W~Ta z@mwE>$KI3}O5Yoz|3XSW?%5fr5@~M5-5IDr?|TN#K+Gf*EqRnZwAd|X zOV2FssRuJ9WOGkDc$tJ^+^&P^67mZ7L64YvMD_Cu%`+_odxYzVCZ%c~uZS1!BV%zU znZFWuchbsK%n)TS=gN}0tInCv!-RS8x!8Ka zxi4G;_lo5L&!UW&^YZ!Q$A69!6%|6uHYAi_+1iloG%hkU@Ao z;B*td@ZUhp){3ksq6no#E1I?%xE!s>;za$XI41<~79}Tmjh^Piz8=>g?zy?&;oc*7 z{gYmMmb5gw=nY%v0=B~m{l5;R98Nww`S7H}iHDO8#~*ecjyh~T9DO+QaBBaVa&M2A zWek&Bc)jhv2&AGdMsnX2uAc{9Dbw63bw3YGJeb-u;h??$XMs3CF$W#}BjAh0IjzSK z!>eKj9{HS@DTbThj2jfQ^x@|M_JNf42@-xb-~c>P!aoee0u~wC@Y8{`cF&_~jAPvq zuJj&SaB}7MfOuNanl7~y_IW(yw4jC|*u6Vk=V$#ZFsddxdB zCHc2K$piL&@9voXhTV?-{^H1yltKHzK(R4m8;lv~FUFM<`792;@A1f8f^Z*}QXPY7 zj}C~t17f<;c9+E3kLaFUnOo|7r^Ln#enmbbQ+ul~OWd3LE#o-rThi{Ne_K|}80bwG zhh{u-X#YU3_elD{^g)lLWJtNC-pP*)CUs(W^~PTEH=6e-*Gs9;F2eP9nAAVw8Rp%^ z;>_tcuU;|xM8XRRPa7{7PiNejd1U6mtU=28SMak2l_biE8MO7=2UGeTgUS6*n2}z& zQpniVgzd1xpIStC;*W$|9Y3he9UO}9*SyaDRps9OV%FT@vas@~|X9yJoN&vJ>La`EB23!=Nq5vVw8Snm7jI%ymC?i-H;C{)F`z6gA*}p`##mLQX zCiQ&evt)=f-EY#*)7rPSZ)o>w6ZWCE$6Z;Z+v&v!* zC-hF}a~zKAvmfsDB;0jKTwRwikZ{*TToY#2S+HZ<@iy0j;M~Qm#{3pVk31rwOHQ2I z;YSu4xnT(PencUXo)zM3gb;o-zik&{9qRrGLbRgZj`id7r~^}k_!8=SQ7%60cWHAb zkIbHFA9;4wvuoz;e{@B`{;v(SrG0Ctu(x@|Gpl!9aeB=d=Je{0D{dckpwA@P=R2#u zb4i~k(C3?BeNL`^Ycw|0MBX~OX>tr9iXO<_Jw*^ zhxMKadMxOP=&fXzOKQ37Z4+DCW5kK}h|%j;RSmWE>>SE!|2ocX?T@to{cX>QjmgQ^ zh)m~j?nAnVxwKp6HlJhO^877$ju}2T)V$asb5rx!@B}kr_?{v4j3k!N#XX%mx0SZ@%?y%C(4SxpG(sO8iq#91y4D_>G`+xSv!ZLv9jKC zPQ&ww-@j!Y)Mr%>8?&w&)@Bvr+5OZb*8ZfyBe3wbw}dBZFkaBIse?)VFTaJSvch`g z)}p8*fugfRQT_SQr(@3ja5Ne#z*)TQh?^&%`fTa_1Eazl-5)*oHT0TxB(gtIY9D+nYS22M?n$Q&CiYtgBm4W_avhl@ zskebDJdrY5uE9zDH@@XQGFejgz7;tTwAwv5xqsJNQIad#`$qUZ(#4bKe`zlPO~dnv z3)3!Q!gc@C#zA-=9z9Vkh7(4g^WHO*I!>x5a?7E}$X6oD zChSLP?{yFCKY%@IJDxjnzd%hfsC!-ZviOrfYc-0ahNDUYJuy8;kx$Ph_4eQ`z>aL|{E6F(=gc_|lViHX--!lj-Y@!3(ZJP!CY3NLs4C|^e5^{5X8Zw|#WlroeG z6kfkJpwyx?qHICwM!62+>a8cN&O=DjCC?_E|g4^9F)r|s$C_moeiz+TU*HyT_+O*rXvUt(*b){mqOJuo3b$wUoVwZ5KL#*B2+`P5P zwPtnp_RX6mPEfTCsAv5P&b#ww1 zq>a^Zdutc8t%?>EC2J}GtyI-IRly?RT6v8quP0ae_6B)w!}&7obv+2~V&S@CtzT4k zw>8%97OS?)YHfE@C!1F`HMS{eZA*8DM6Kv(B?Vq~cMvG6Z|kn_*ezBxZR(J~s``$G z7O||oqjjrTMTYLSCY-kJ7R$PuyF0t!YkODIwoOePVogKWcGj!6?^KAArUnHp7gvha zqFT7t_}8y-t=nKQhd9Y1bL$RRn871k2e}&iB ztZ~+U1t8{2m>|u_zE>quopej&_kl9J4s^_12&ArAw?nM)Q^?e3l}e25G%yyzMkgNK z>kI3M)+26>1LhkrKws1$F_ELtVRTOfX4Q?vSR$^1Jw|F2;5BzhOyoC^ow_Yz1#z~> zVrY)AM6|Ybp=J3To~l|c#u7ZJG-6JG-}ojZT4qz2@iK^(4uX+)!;FX~Z8~6^#qwYz zjE(vsPL_vW2P*0uIUgogMAK|1AUl~25o5F5hZR6LKEaw{d4M{EV+l@{M}E(u){i;F2p_n>yoV5k5bCF!C}oMDB^0j2x}e%S{z>ki-K*A%Mf4% z$2jmQ4HJ%!tL+iixkKogDB>+OsH0co^fZbz6^ecVS?Sh=OAtcGp8#7IDRVzTfUS#_ zrjKaX62dk|fgNx@;TXqX(aBmsINo8z11=<-=vc%EFD0Dh*iN{JaGK*K%3Ma+B_=q~ z*``^`uBGNvqyz{GM;AuRT28ok;#rKobv11k+QfUQqLK}ZCZfLs+^t}ej!Y91M(jcy z)U5yZ6UvhzyNaN2>}R)HYPC4Ng(S7s{}gzeg9cbP(eeEV4n;-(8YdQ0X1wKhXe7j9 zS0!xLZaXs6F^Pk*lb~>X0aWWQDH#%&1hH=;@mj1Wmq1TkZM(33OLE55b_naYC1YIe zE@6Fwpv`g0j{e`N103VvoU(qGaBN)drp?0o#(a({6hK{E>cza>} z(bq6BTn;Yl)*t^8aJu6=jQ8_@2b|$(A^gH5^qL)4+r3FxU!u$$z_9G6w9E$>rVUem zzN4P@{45pxMUHnV^XIbw`{Qc2qVF%+x5V*Z9G%z5U+ysAto7`(fGZrQ7?(F{;P+Zb zK8DEp8$ZtL9d}UXTbvD_bNn~?f5*O!B9Rr@C&?3?nsf)Oo%CK1L zbdsGLnDv`<$>sbxFxF=M23Toveub8)hRwOv9%{rm_c4a8vQNBo2G#`Y)p{f3Bsw`x z)@_oK()6Ri=5YS*mg>`66YiAvrAG| zI{!pHJ^DfPDR=%me6n6E*(#iNvVC5;s~TNk-|BF3XagP$irSturVI!(SVR^BGX6CC0(_b1lw3% zw=!X-X%mozDM?tqVys^6^PoHB+?_6A;cTX#Gc>BPI45$IyG-M7+n|Qd!zr9odNKB~ z)}`7h3b;ouIT9AmR_5X|*|0jFG%raNDvp*PDBUg`WQ$MFj~xhtGUC}6+7ADY%X z_i#bGMdy5IaZX~!9*~W8=YICNRW^E@f2W??^fzEluk%*s!RQiJnr;T^dZ@J%6XQe`(@*Y&QV76u$1NG!M0PRp10z89E@}RJ15vt2@B^DM&d3#4}=~O%~gh=lrcp_GpI~O{ zx<}5%DV*lkFY6qTDKF8+yLIYPTDyWhlEl;;Amc5>Oyh)&c-?U6|fuE!iC5rY;{EP@7Vqc z#xT-#1=>a(MldqHnIr+X4eb3zzNWUB1wDhZRhQ$XFkf_`B63TPJo9KZX!Q&pqU`G$0 z02odA_kb*Y)P#F8x$f=*X8J2|SLv~jY=wUB=OL}bI|mW#^!^B)ul43a&>n9A{N0;= zoWW0@g>=)?6AMiLsPxN`WYOtAKrefGJ>DeVvI zUEoMfvVU9mpq){=3Sz$_SwzNiHohwx7UydiGW(OVVRPP3g-^*wjPo@LIwc$N85QXA zJqag@NV%Q*zWxGLq}zX}KSCADX!)~}ML4%1t?WOR4U2Ol^XEC)uw_((>n9S9$zYG? zB^;lz4DbsQPIU5OV1H3Ik}}p5gYqA;k>)I85MGiEmxw%tIc5K;o(1)(v+Zx|JCRz> zjf}?cC5v!AhTO6LLAN8E7MWG{cXZA{tCP3H_CHECo3kD$`@6CclTlg%h40Be@y>5i z;rp`B#Ednh{HLTOI+znMOJLIP|JCWDl9AhDfFkncVzjl|&{fCi2VnG%SLEBO|e9 z*dvS^&;g;g8{Y*IN zNX#f@Y9z=;Qbs9rBT+WeoWCa9B-wB||IX-6mW_1hT6k=C%0`BWTtcgp3^yvwsHsLQ z6ldTCt=%O#gv?^Mge@6WZ)_6q*zo^bxDd<&f#uJu&HUVQxc*xI6rntLX1jpyvKyB zSm(zancb2S@8t4pzeZ9fI_J>dYb7Po`5RI`FDa9qzhR&2BqhoDE-8B?CB@lC%3euH zbACWducSHTez-}L@= zNin_uqNG@z`>60sl481lP*S3uE)HIwq?rC6l9X5(v3^M~-9Ib|6El`yj*xv>QcU;n zkd(>JyJ`JbB*k?9PDx2|-cQOANip3Ykd&#;L!8@#l481lR8l+{{?%)R{Vtga=@}K( zeqp~`vSm0eh=cu@WSfaq80H*TsgzO0G`~l(cv=td8)bp^UtaN^#lt(0`%-Kr;CnTlZ z`8+Au86crnXRJY&uSr6Mlc{U}x+GMINW@RrzhV3q$&HojdE)^rIBJ|#T7+1Y-)Y}sT3QdQhr#9jdgw>O6((&60dUpWl5RnJWcIClL8Vmsw!dE&m~)u zngOp!wiLCx{X(*(snzY5vf;|8;;ea9_DNTB&1(yp8mxkAk z7ceUBKLd_k!Wo=76|*Te|F2jbA`k{3aO*f8aWi_v7KCy90TW^z;>#Cv%tHjnaXg6x zj4ce4@fYk+$044%nB(J%Ia)EAu}iu4HZ5IF(~HIsF==s@f189I(sazKxCny6aVuPn zvl6yA{tI@-MH03-8Zo)!Y^7j{aomMOi;E)caHPWhIC)^gW&Q5%s!;R>~;ae-% zz&f@g$>JP@CphkhnQ^g%CptXD#}Q6&JWM(9gcBXBCz*g508wGeG;mM96T&3a? z2s<6Wq&AHA3=_vEWz7|bxJS-p@~nD;BN^g6O66^Lm6Hj%$yG3?-pTMghr+Z4o$EUZw@r? zMkhqFhe8TrjfwWp1B^b8*c}BR_aadu`8Lw8L!c8T67BvLgqtAN zCV=eVehXQmz*$4EUrQ%eDVvpu%+#ijAu`XxZ*4{x!bOhDIGs#`e+W>^2;(?Fj?6HG z2Km~|b0IC6$6%s1H;m&1wagns%>H*wDs8^fF#8_(qAf5RkFv4QYRiO6R#drW7_z7SXL#7Q$sVy0sVbKKt4!RsL+>2%=(#rgILS5w3 zgR~@5=2DUQ4CaTnGzJ(`W*!|a3PThy;LE}gZ(}sI;xUBO+8&gdATsBZ!CyBfb2es& zRuYEDY(ROF=C# z7NX2Ebf-KF@e!?E6^2+(8LPt(YmkWAnlQu*OqYr=#DpIpYw^|Hb^Xa$23p&Mww^>0 zx4pYdXf=ejxJ})gg|>klc+N)DeE{Xqej;WSVy)EvZ4)rcvsr)T&|Wo$kOTKhu!kXH zzYE7~TJwSwsOfBK5L$~;xsB>urAkL8)&=cq!g?HEX=z&s8xEc3ZY6AS{G2@72uC=s zWqjLsJ+_M26Nt-Xt@BnY*xcG9v~Ds9#}zbnCt=Oe&S376yGutsF+GGWj<={_w-n@f zf(ovo7@P8Y5TNusM#K(6W4d--Nh$kx!OgFvwA|KJ1sh2`&{b2~H>dr8P)OXhyLO%An6P`-v?ILq872LNU z7$s9Od?(0Y6`8Z>?XwS$G0>RTf(+9|W(1A+)$<{S%uaUqZ`tM$T|%$+shT~j!3RRJhDHgu&>B=7TX(`9(T(2D#?-a4p_B)QWz#Bgyp_Mr_o&3=OUy}_klQY_KUfKEA#1#axu4_b*qo588LIOu zG^$NvW>eSE_s}J80K~r*;52ub{w=qh0L-I{0*>B{&bb}iFiXlToJ9SgUod4>Te$oheSh1Nog`NU*`9~)*@?`M zN(+bRakh^F(5htnFKFj>ZG(r^vi)t?nA_UcC^S4zMR@qoFZ&N1sVgKs6QZ*t>F7Gy z#%+?w9^s;MrEEWo_JT!pbiHhg>^x4m8p|E9H5Po??=k2bB=KpsYuLu)Q&dsVv+zy? z;5YaRUv4X=M+9vy0os=boo_F}+a!<{X%%pLkyfSUiM-Vy2s~W%tp#8QP#5A5z6~aB zm%^!J7QU;2o($GLlhyX8MOvla1tB+>9UcmHfJz}2cVMjC=s?Yq+14eZFI-3|OoJ7= zZT%vxI?DE(!lf&v`oOKit-~fg*XJK7UzTT1QM-) z7%j(S-;Ajv*@d+z$o?SNuLfZpyN{2WXTz=r@WD3apYlZ-RwVMEU;GCXaW;U3;PvGJ zC*}Tn!2ba<-xb2kjc5IR@*^4qfoLQd=zj zycz?b6*KTgG(LpsJ7DtOX!6>&jPU{t^4jr1Y~O&%`&f|o7h}9(a_#uQw(lYE-Uu6h zG0ui^*kD8#X%MVOT@bz}Oo_VN%$W0(xJp`DK_=VRX{zLX)|8lO@=C9C+w&KR{DmoU z-FUVarOe}F9!29L;dXaU`tXcISosI8vt&;!bQjw zr4vlI)h4m>BBC}=_|}`WZ5Pv!6q`)iEf>@Bg|8j72cYm_MS~vt&vUiZi3dfJ{#-a+ z%MFtGB7@yW6`6$a-gp8d$q`=VHOXV0@kB)iAX!nVFYj*P60s=w@OVOCnG>ao$n{;t zVZ4U#f{n5MH^s)u>pPA`n_}NK^>tpPFYf~oq(yv8K%if7L>Syj z2%i<#R$gcxH#_n|Q)%gYbdQyTh6xh`2KIX{#2|d~IWBO&4$8`YHH#7lL$> zg)hg{l{8%iMP1a8#tTgT*&%|+D+KNZTqE*$7w`ob>$?iTibXv=5*<9MTs!xN%L+7nxQylc95aacXDbl5Vx7VMnYua zJ8bIs<9Hn%BJW$EJTM35zXaeIE=GB81GpJEp7#j=+blRV5xX;5m@z}m6O{{32ww^a zbZVI*z#Zmbj>ya7ehvg*J^ONZ%mZ%U$5w$0 z(hZ6?OsJ9`650+%t_ELLj9id=fqD$6Z<&3Ai?0=yS@Y6`?_N{*S+fs@3D#aD__WC+ zumW*w(sxw3#R(qL{+h{@c@a~PJH+@l73NosYlwe=RajQ{iEg0Ly6(BIS(EN|$ zsy-pW{i(eB@v2)vE}XKhi$bpr!n_vkFTgGBBuJIT=gj zO~(fYZ#sBKuWma2X8Z^@DSBU{56_3BK|fdOw7FbnY;OqPR1j##`zC>t*ofxtfu?c_ zM$A+xAvIzZ1e#NKszQgh_Pzxse_n`yX>2kFLO63ZT4^%Zh6vaxn7Ew^7hza|z(xQk zD*RH2)s)d<^4}LCU_CW)-wn#ZSV2ZFPL%Pp5G!S1=X)~r3BQz|`8m7*w5J3$Kag9M4I+%oSohjqG z5G$jUD}0|bW%PvzVlk%%WymPNIUN3@kfYrtqwsmIT1R(b^RZkm4|mBZ=zZqL|#WaxXoZM%5;2SOfPt!nipM@=L1}L=8 znr%iHZH&-joH)uZg*N&g-)jz05h(01e~co0!C6+Skoqo&;8;>b!x$q)AhUua+A~H` zlZ+-FGDVmsV&5E`Y7Z+)gaOYX{{~b3GhmNij`)(d=;T7)AJA zHj!U4<0&{DwNeEuc@d&~N65T8}Nqt@BK+gbyQLGCQ zgbx`gaa|^kTf<cV94$B#;)B(Z*NMZL?LvwvYrWa; zy%3LBe3glVrx6CCg~M;RBUCTSMh{}A9nHnf=Zblpk1y(ke~SEDQR9$pZk+ge(iM-y zhuYjatw@C^@ROd8!bgWM$yO^{R|i|i*lKLuDYT!;Pc~VxSY;pJgddjesc0|kg)BD| ztFii}Zti#TIP2s-3o(@2@N*bn4x0JEL_LVg;x@coZo|6~>(7IilOe;>zU+bDdKL1DVa z%~Jt@3wd0>WsLbepWX6IqRmVDY)eGmCQxX(uf^B30li6~xdMI>sD&8O zFPXxWOS>?5RhGWb@m{Oi(zlkkYWISZnf;K-+1JQ)#-;KhQ`u7?g2)>NPFnJYNqk)q z&D{3=-bDX7h_=8vJVHaV^Db`MeC0Q9r{UVC1~?wPRIym`8qpUb$;{XnnqoGaV$5;6 z=F`S$g(;?Y952UdEhx-FA0Nvy;P;JVv0aO&JfLu#zHL&NYQ4bGhu@kw(}z!0z8}2w z;Sctn3)SyC`=y)KFx=xOfeI!QR(ZZ7&B9m;Mi@;P9K<^l;eChm0|XY zMpDXU-zygL!6;RrZHfn{So{H!i0KS8@(?$Vd;wUIMearp-m(ep~3dm0|Equ@Oowwc-AhG4B$QmO%R4Xu-6*JClx9<+j5FWY>P zH&4DY-efM0qi?^~ZO z-z+=jM`QW1>+C|tAxU=RcWdV1HF>hW0L*HI$!>-;Ek%0xOWY!D=z* zUXF4n;@yik@>rh~>btCpN4 zXbJy!D3xF5gNFo<@+m2U?U&+P!L;IS8se8C4zVrO`K6F&DP-=0Ol4ol(nKkU&s|HJ zdNAHT$@&pka~t`Ylf{zLo64>y>GM=A_~`-Fm9I6k^BGl_q!g2N4)0yH31NA`_pR#V z2MLnx3bK{*tu7B0uUElS##gx3k9a;NO1a(O(So8K_2cz_ehEXA~0p-(W=VGp;gPS?*pCZ0u!$mVWy~z*g;h^!ZQU~gcW%F3*%Bg z*5q*~iguKrODOv$P+CR#DOBckS@mPUt07?3&j9QLQ2uKGdf(?({Q>n8K&+;q4G@A= zMdVXN#8j**K}^N1kX-QI0aPpriIr_2vP?{@Jd7?Zv6Yo`Y#3IQ*y_q> zU@S{)W92o-CYHnrl`mt+Sz^~!?f@UlWP4>Q_*k5Al{;WG%jDQfzFc8(##eCz_AnA9 zNf4_10kABw8!GXjSFj{bWGYRMO|ToWsj*i$Cus3bL@{01?S(+$!y1!?5xdyF#9o?! zH~upOs|b?}E39$g#P=agt_YHCPR(v-7Y&UlM_B)8O)E_x*6xO&Y;=rC2;+5(@%liE zP0)lXBL5rMb zH+VqlNnuS$NuDqJq=YPzeNs*1Wh2e>S~jMPb;mQ~1cV?TMogm-ROXtef&yhrlSy%# z2soq=9t(Ugw9`X4CS`i@x9?-qaBWVP0F0bIj!A}l225foWRJ^W1tUhE;6z4P6TLIT zb?R98XUahVDf-^Tbn04fuaUvaj}W;DG_8OgauZ~S!f@MMGU7`kLXO~l z%b0z5DnBoJ8FP zYi~yRRN`7#!_UxtDluru28ch75+T+?;G`g$TYzCK(ea2vza_j7n}`mHqVL?EeoNml zPe14BRh%-A`ZG}?M0LNVKjuMz51~YgehU${AENQBLfD9~yn)6!lnBuu1H{GpISO}T zydOl-#9I2x?{ETaGhGK5bQIvH^$%KX2)tr_7NL9zMHjipSf59c1cs5{FO>}fbc0;1 z7o$i5fg(xBJ63}FK#)Lyp0dZIsOb}7)_gZBdlSgVi0ESRG1hzuD+vVX1>Ft0K+CMS z%4wqNIaG8VV2~OdAolo+IV6NRG)yIkeQXa!B%!ZtP{>EY#>b{aN%=IHVL^Ln&r4=F z!2QskayU_;JbGx)4FGNqHW&kXA=&expU7ykaK^yarf^D zjt@+@e@~d4`!A6bgJAV*!4h;gPV~Knnbr4uo{r;Gh{WUc1A$XcPF6WHiDY~)=@Fch zm-JwUF+7*_2v=n1@JssZl zbf_!mpbiCKKfZ?^@^hfFLEuK&=+=%AplTc04r^ZRSkO1g8}x^tXyZpa!_$2;M*nJ* za2!`}E=gEEY*kn-lGqq95o?KH<0%vyIQrHTgN8gN;(RX(`o@zro{i^Fz#89IM+_SB z;9S~-0@lfE`}O`9HhNLOI=OE%F=)ucg)^y|SjTF!1S?xmU9CV?jG88{WVKI%6*r=~ zS%C*o-L61ZM^%5$iGqd-<4NN^pi zze}*FW@XiENahM2mhR zt^h8c?RQWdAsnL_OB4&PY$j_TMTGDsd%r%0=1WGh_f>(>#6v>pNC5;VSn;ihF8bDo zXaG2}xWcnyK3K$`waR0JOy!@F*~+y5`G*tA9icviUrU>EdYaExTMp1WDKhZQ8))4L;bu7v(AtLuB4oIPz=$f z9V2jFHg;*p2z-R1i+RUbM@uzVqHE}&aaR0g7W|ULI1iQ4Imc-501C4EAymrdbz?TK z3rPaN=vw6>+CPbK4oaf90=o#U@2R~QwIY-f4)g+0+CP&@%FfTElCu9ZsifTTnN(7S zK9fqyw@@Z9&&C@}^y{D55roh|$2nT88AasD0#sWRxD(Yr1s*`vr@%W=G5p|t2o(nx z;ESlJ6Clo^BV55eV6n%cf-VJ8f$B6ar7!JtB|G)VPFG$N>NGAnxM1Qht`0{YBb0@L zX;s4dAPQ3A5Gp<SWYV~{eiogycmEeUX=w=4XZ0s-=Kn$`jbZ+*{tzEJ z7=ET7Yaa@-gYG@5z^|jCq_BN4Fe1FuRLNP*PRvClA3Hs%!1q!8Re}7z&SEL5Iv8zKNQD^pK&>sQyKPXt$Sw%}- zSF&Qf#)}|^23;fq-9ksWk1k-%^nFZ$L#UJs>j23k2Iti%1=!;5#m&t9dy#jK;e^HE zQ6e5E;t7SoYGJ|h#>8Z<!0cRjNnEV|>o|u5u=6m=ivOd4Zd~co7Ek?f`T~{p z!QfC9C&q&Rqr6~$_C1I4e{~3V+-i*3`5hGB|IvW4%xCX+QI=dHL1!lYzfB(s_!#A1 zoP`we$*0@$>67`>rZNR^{rMMdp$G@cKb5fzuUuCsA?aU{g4FG|Py!duf7%u)g%bGp z_5L*}l)x*>r73&Kf@{5at(9i5b0Ny5bMPMvxO5)&TPUj>W!|L;d~woTVo<-0Jy)ar zGw#R-VeGsf<G*a0~uKlK7e0av5^i&;+*TmK(z;pSUjPA|Tg zQUHGF_g}SzB8LBUF<1^lM+_kDyI6CJi+vNX{MRXvcluvZAQv?5cEG^(MBRK>GsvGq z0hT`UH9Np-P+hOU{iyC%;Bi#69t;o=I>Ife02cc#T5zKRX@Tk#+T!z?_p+o`vU&>z z&tx9mOJG#uD_C(Ek0jo@VCu2pnvP8wr)!Zkqmoq>3c5eFm%tSgU%`qwi0)6x?!kma zcSsE#7n`mlZe*bSd`z^L0Ieq>cuWQ0Lb*s*yh5=emG|Zq#|X_p0WYiBD2f0ebVLKf zGXhpgD2CXf$wve()zHJFR0gF;CeYSfmP6-@#!>8GE}h&nq4K|2$DVQRSsH0@m7cPR)_J1 zmVWwBf?|kv{TR(#7i^%GN0^skeua4wW_z#?Yka&2Mpdw4@~Yt>q+(eCD0H|0ao`#1 zt5L8{Y(=$Gfjy}1R3Ofw!v$!3r*-Uf4GJ>;^QcrOdL)lDoLwlvPV@|6W3@nn@=+UQ z;E7Zt>t2bjVs$eL(WvCH0cREWkSBcZtxF`-mH5~{Bvgglv&rAbx=P;$78nHuPa8iGgKv$ zo#1-2z0$0c%=%-q4pxjyGz$HyLJ9f-P{xcA<3vqCIfN4Q4iw>vn34GU+!jEXP9ZGd z&aOuA0*{>RXliQfGFgDfkCmtfV3-XUskN=Xt3^Rwt=pOu)Y-LdZrn7kc{tcWSezc{+Ym4DRMzjm-RP<8%3jJIiR!pSxi0Ts=C> z(Jw-IoXgnlQl?Eax?LIUIN!)D3rwrA9m??*=1%*GG%}F2%SbF!Cbnkzr3o~uKw4Pi z0iu8w2NBbA7Gy8dqr$ZP0@@rdFTyv?*yVB=KNK<;M!CyaT=t|?vLb(H&aaI4%}PyE z7KRz#q<7EADbAH1m05F)s4VxQart&XKI%5jtz6CmLz0qvbrwO{&uDf@a!yWRjw-r6 z%(53Fw5;iF7&c=X&H&Sozb(~mwiXud3(RN<6l5EV)*D6Zy94tjA>Ue9zAtc94hb0t zpXv|f8TPD#!W&`SvF1X=!oZ)W-sS2yqFi~h1MDiyG2Y)(X569W7Z|tg&FT(pGb!cJ zp+xQ8+#MitTX|t$7zz;yEDfX=Obr-QvvPCwDPgw1Z`Hh0yaj>gf()ZaD`+mj|H5%` z?~T;Tmd?t}4ixki)btgw!hcm2;?Dq%CH`HJT2We&FMaMTw>SS$_dLVB*{F3Hv99c#Lc^19 zT;*D7c(PFCsVW!qEwI6e;hL9I9;m4)-x%0XvkIf`nVMZth#bIzHa#_`AiJQTupqk} z|I^bpPVtt{ak~qrdJ4dWNeXLRSU(L%ezrT?NOT!nT{&D`0tJPE9LU+oJlc?x4IzPF z1`77=+t-bM`}Q3w*jRH_;YK;vG2JP#rn$MfFuP?#;p()U8oeoDKGrScg+2Mk&h>lx_s-JDXYq-nh{3i^fGJt z&cJ0{oTg?On_LBm8M3CPutG-Cb-ZRmrsO~Q`|77vXg+{b1&}=*}@^hzn zTXM^9x~Zkc`0C#L8|N4kFk)E&jC^Jw=cd+ErdzNlMN@S!JEFCvd{@a0x0zzT>hJy0x zOp-0GnsGDiwOB1-SAmh3Z?vh)+IlNKB3`g@-1To?oR)aiQr!|}$-y|yV?>ut!P+v# zBlii}Idk0Ifu+qxN`Cq(4tBsu%yJuT`B?VUKRp=&s;ZY)ty^A_E2@?&C@)7~`{k?c z68I~t_bEw5UR%4fertD=kh`VYc{zgnvX0uW)`l&e zlH9pjtf{V8z8rs@8($@_#b0J@>IrU%@SBFBwxg-OQLJ89>aSgk-J&UIL5`^1)zRA3 zL_6l@QBr+p17+9pYdy6MJG-_vwTaf+uI;t;qG~Pv!g=*Ne{E@1Wt*t&ZtL!BYJ_QB z+aRT(v!iSKwoRSVhbB?mCIx_2%RlW}yLG|5dMQ(RurNXl07 zrq-^`+FktRMX|EJqj81Y-70O|*ow|wtz8W*wb&2J80FOFs($#f$6D-~+l7C1$yx+% z8+OHT2{Fj4-CB>|HQe1)-yup?;RiiR{rK6C&G@ZInAR?uo4RWG2P#l%8|%C3#fr6f zf?W$sv1M#+tKHVLt)YFlz%QWW@{|YCu7(zZ^8j|6qgP!~nx_m=-Yr@n&6`)7JD=#4 z^=*w?n>s}8=GLuE*nfA@y4vk+wM{*(UA6Tc&7I2DTrhON*tMmrauGvZsfw>7(95N-k5np?YY%OYx9x3za;o8I09B@XA5T1rmnWymQBLEYr?$g z>T2rgQlkak?M)4>n_HV2gR4So+ve>YR@}~s+UBj>H`Q+qA8>j9RJ*N{X`fr`Z>eu< zYuXw%Uz&EZW6+B{%>a1wY9w`*R1no?DN7`EphqkD_s8E zT$jAbb>-#c`f?WJ<+(CCnzlC8cQ$3ZHZH4LmCaue#jR-LoP~2XVUQYHTpdk2TRU5~ zx4H5b#)-sTx%xvta-_?PDjzhHYXLto?Py=lg{uTHck^HrYgVZhWA*m7RrQ@)>Njm|D#ddMbxo<=%ts!z zJMjy?$PIBNU00O$`JHkdb%o|USJv>EG_O{!?QLAja=DbPfO+$K7GlBcTv1xSoONR> zasvZY%cZI_kAnuQx8gE`)eP4wKc1oZ<%JFD%IPWEnzk?8R?EM+9(23`(+6o(zQ!M@ zty=ECqN=)d-SXPCDp7la;cV*YXxlDY8n?HLhWhqebL}=CiKrhhUbA_#G(cVtIi_t` zFE|F}e*7E}Xk zgQB9M;urc*g@q=%!OWeonP3VBJP1SLu2T8L72!M+;e_-#Gib$((rA zEz_oQPp81tOq}L3toEL6&`zl;Z>5Dh=A3Z7&4`AL>gR9WxTO;AxRLG@p-C00Dm9K& z2Ul0s#>XBFIl4mEPQT&(^#Q4lr&i7CIAc;x$5~UVCrq6^z2lVX=@UE7RKrdW+G_Oe z=NXebPIR?YGqHneg_CP$R*jz+9#u}BSySm9&YC!>L#M8tIu48L?x?bxtGa?qAruQ2 zw_&<^`&G}FGEqakT2XFxPmE5UsOJ}|=YyuRCAJU3|F>{9K|X`$ZsZER5JA|z39ajluCX2_tygZ$LCvbJkw z{LEIFsp>dB6yJ^9SmqWvX=b(iAH$Dx)g9W#<6I}lm4!}J((cIJQR03}Xq$vvnH#aS z)u)Y5PKF$Z4v{bL&~tE7a~YAp_6rIlSCbog;dU)2ZdCZ^j5;}hGhr^^JT zre8lNTSdh+Zn!mb@_auGH~gf1q$#Fyt3C6pz4Db>au;z4=}Qw~+_aNJ^DQ(Fh9}Jf z?JOK_Xhc_zQ|l;qvvx0yd$mk-DV!YlUsSAeS?FeeD$53iV^C$F#&K;L0yK2yL9C&<;rQYRG9C`2gcXb(Ibu@>ih|pLYy5*aZ%x&RjsSW*Sqig zm7x-eM#PntN@*^&wQ;qj%1pJV`T^?N9oQ?^Uw7<$ z>zt+5Xo#2^uI5l=brLH}puRt2`u~CDlK(YRh!Qq5ev@ z2Bufesh+7muW#$2K6k~zL8x}|Sy9~{m$RDLCS_nRTC3KL+pD@L!tE+ouT@q}m_RbSsw<=$W;8n- zUATGLSY@lAf(lh}IIFozB-OE`R}dQhNyR?MM>=%kj0wX>#)sgxP*Sbv3Jx_u@~}lG zsM1rb^r=X0KCWh?nV~GYMh&?aE8V_wCx3 zx$oq|MkG&}Qpr>IN#}IXQR-Jj1N!wlsH|P*?gt&%!F|mRr*!GiW556J&Zl1wdc?p_ zS~Nky+{T)#i4g>j3ge~H+ON;k+ON^G+OPMMrHfYjG;V(Wj`Mf8pw5LQ7Zq#Dx#ZQm zZTwokPvd&?9iH~%;SI?U1>1SpK%d4<=GVEPm6{J4Ol#MB-pjdTl8t% zGYq##Z02bt*p$tycW&MJ!ACkR&-^d(tG5%MK2Kvqe53g#7w9bYZCsYlAD`3hotMQ5 zACS)X{*BwEeR^n1-_*G;lYO#yxJyCa_G>)PZ@bfFshxB>9fwHw+fJDqmDz4!MmtUE zbZwPRm&rapz$y=Xh>G^r>JIAd`jO6%PMWi)?vVOLrFEJW?NYQ`N%NxJi}onmTSF7J zS#+qmrB3wCPdT9#y?{?k>F{1Z7gnN>^irb15B1Uk()yis@Z$1SEWMYQKc>PIm1vMb z;r2TO`+V6{0Zc6=8lX^UUpLq{$=PUZLTd3>Gz;xL1}(qnJK&jk5Aew^B|6K6+o#XE z^XnIx_+NzdxPFKiO>2`{^ntdFedAQD{WZzN=a0;WCHh5aVS1Wo@~dh1;E`?hnn&m1 zNU!FW5>41qxc$yy`)N6gSU-^~20Q0syi%f{%olFIOW3|5XYXIp=a-Ubw~YO6!Cp5T zmN{D2r!K#gXmDkr{V#+4rksgKUFMgPsAa~!Ww7^sAzoT0D}g0Z>x_NtV4puJW9{+{NX4NG`@JB~i!B_8r6aEpqwWF=O93W8XR0e~>F5ar||4 zlFj1yPjl5w9PbG(;w6snlq(c*yyr(r$A95UGAwbtCu~V{vSyY+VFsCOp5cP741 zCcaN5zHcVJZzjH9Cca-Lz9JJ}k%{jgl@a11Tom=s*!R!aAD)RnJQF`46F(pmKQI%Y zF9|j*i3Vlj2W7TDA`^c^CjQ7weD?k{I7(`e_;?3r><4H34avl3>w}{*@gAX`UrM5* z^FnJSg}=&>J|+`CEaNYKC$nLRen?eV9&@AXgP)T8)EwxM8T*kTJo&FggQ^StvNsSSokFlBfs*L}tO#Jwao{-TKGkQ`+ zPtNEm89gy*lW&kw0Ck zO`@?u?-zBIP8R3iA;fpmda2rj1JH|u?hqY=b|1V{?YHrn?N2A({qWMLb98nl{(_8N zn9?Y^r|$*g+iAU2 z?br9D)9L$^c(>$Ab$8i}_MNR%?a>Bx;`9y-x>w|f7*2olpbw5ZqPGTpNYq=}i=T%y z)&2bN0zEVuT%eDMhM`*o`>IHvKMsq_XH(rz$D!*5Jt~@3phrft3-svd>;gSJx)AL& zH&t!Cpg-Lb!8!-t^r`>%-h^U2c^r{{=hXY3u^H0l@aQLz0{(Z15&MV!AIe=3*u zwp$hG@^>IQ_P6n;J{dh&I$d7;Rn)W|ozW9AdRj)GnbDVK^fejnZ=$C6cTYwqKNf1E zR~WgWljSq@Jioki)Mi3{JV<&NTI!*HZF$cgn(kLm^DeR#s}@S7jIu*12-L z-kVm=K4oecNSeGEVSmZ~lW~EmaRkZh2!>OpUaNQrOloM+cHbFg#x105!sw(#=U%iY z0o#n2%D??jO#JdJS?4`fcxA^+yyVqP=brJ~sAME%NReOk#P6syVAyZ&g2=rs=%a1C2c#}BQuhT*L-1UC<6#nuRr7Ql^PKhhiPzPa>Su*B_ba4 zlqh9J?p<>d=KPEYoNY74DH->cdX6c%7;3+_$lx zd(jW0Uq!En`fXv@&J#F!yXL00D?__2Y~2^_nNV!!zJvF7Hgwy+_=UKy<@mn%A8o3m zw91tI8dLt(nzDNZ{T_NfdZQ`(E$AeDO}syC@8_uA-hCo#Kld+wSzr7ySHykJ27ilZ zGjKjl!QVXSzGE)Gw4XPnij7e!Y{O57xz6IydD3Vzrj2D zHZFFLnX>x_Ivj_z8y?=yeI0LCYHB<8*}R{TgpV<0KY@5pG1TB)O~Gxxrk|mkI$qD4 z)8I*cLd2Ax<)-put*PzT5xyR7H07s`8WcXBMyBizLia@vHI>d$rqVgil>fP=wwrHi zyA|kF=%-9=_kyYI-ZZt{MpN5uF|}Rek~rRd59>DQa`Zs4ScPG*d85){zORXdOcm;} zrV9HM^fc%;viIw@r~S4tl|QXarDK2CgYZMpeW9Pm*?t821n6>8{73!r8t&?F`QO{r z{@R%G-`-UIXZ;^eeDMExJT-y$GluX2f{=875*o5NVohvhYsnLUXT9Tly-WZj!=(@ja|+a zzN;x6>IbphTKU|=l(TT%DZfL#CJt42u^zF_F_*`ERNJ?(f7!P(Ww*bneC=i`-wq@n;UhW&2QspRZd^1hn2pu4p(~o9Y*Ktsix}H3*psp zskuq#4gDC}Uq!V2M=+_E>y*Udo=4m13iYt)XFm=8rHT4X9dB>*-@4x62sj2#GykJ< z4d=s!@M=^3t~FKJ+-km|>)q7;J`jsH>-siTNquHcSNW+Uey4PpTXdf{zt?qSZdG|O zZ_|C)yh8P&*x>JK|CsXorm6i6-9dasQwN&L*Kwxu^9)n@JKt2kE+BlVDZ6FnOS+$$ z&OhQenzG*v^|R7YF6)^JZwy<&R9Kv^Awe1Q|EE4xk1;rdA082<}IqH%-hu7 zg0<%LI&O2B&NJcj%=dJ@%+qxJ5xy8Mfw#jI@P4?;{H;ExU@lgB)Ks~9!u(PB(m=1h0SI4D(@d4m zx#mx5&k?^Gz79V!b=`a+I-OseO6MjsDvCCnx?Z-L9*EFLR6DqisheUw^Hl|#B}Gva zQ#bQwrY34^Zt7c%EzD&~r>XPM-c&wyGL=u=OyzfP(Z@g7)bY(QeSEGD)wu0Oz1Y*d zS$5`4al6Xpq{3R|Mo9|&A7yb=ye6JH$@}@hTKn-*e0SXcG5=q+PG{I&$qQ@(o5AL= z1uTPYU_00z3jf#i{M`NNa*T@akNb1QfA(`oX>k|0yZJz*w;$pv`iF||K)mlywm%Gp z{FNSw9uKELU5df}40sV-0Iz{dpiX_TUkO*kr=hCQ5U;L8;5Tq9EK?D5`rL0cd%+5L zH1y=4j-Le2f|tPG!N=i?@NKvOehW3AH~4F)`?f-T^Fum|i1eIItZ#=vRN_hE-$ z3~zvk=z?+hKzJ-12dm*F@M?H7Tmj#J>)|)>N7%4#yr1T9AJ_#R1_#6A;UriC=fTV1 zweU80KYSF{Q^n!q+XaUEr*ybqin9rS7(NGIho8cK!=n1JzoxJSY!7?E-mpJB4*nXB zhg0E9I2T?7Z-RHhhv5_OIrtKM9lirUf}g=J;U>5R`lY1vX-C)ymcr(6Z`cOz4?Dpg z@DSJ+4unU+5%2^!7W)40besnLEhy_N;2+?f(4Wb6{L}C?_%R&h`?li4N1?>upclhi z;Jt7S{0fHqzP78c8=d{MhW+6%cs{%y-U-*h=ixfI0d9htK`;2%7cK+4!@h7TJPlq3 zuZ6e4`{AST1-NVD*l&O6>0f<3m2euo5-x#v!3SZ{PVsg-!A|f9cpRJnPl0E{-@seo zz3>sZ4sM0Js$t=Dc7y}rv2Yx$hI8R1@M?H7Tmc_~&%rn07T8P;2k*BfEQbfffv^gm z2``4fgEzsu;cECS{2K078t<x z#qd^mFMJ3-Yj!J&UO=xiyB0<7qdzyh6h&X7x0;$C(EdMU&Ar=Ke*|9Q1s1zoO_0^!4x#xDq}JpNDV3 zPvAH32UuSXOCQfJuqEsOd%^zj7&rme!gJuI@ON+tyc7NjJ_^^uH{eI`pKvqON0380 z8^hgU8`u#Jg`>@OMNt)cy4kiUnuR_O-URQ0tKj4C1-Q<RdT+Ch$_Kim*;?fT-P>FfMg7son0h!l59>PO8rzmK9zOg;Cw z+EnBEX7iUt(e0+vald(H6g`W6&D^^vT8IAB+^ZP^k!52-5=2PcbC@7pT?&A?_p}7+%M4wn0pjOozVXDbFser*9Ses)Jv{m=rQJQ zMbUWlQnvRfotKL za6SAQZiV&sjMLK$mcjP0C+rW8G4-%~Bzl~=i|Q$Kjj1`L=b-1C8mM>;`W90!v;Km9 z%519hiQZu9rQH|k&E`%;(GTeQ>VOyPp?zah`M8UDlAe#652$<+-pyR8{v^5rJqSGl zeIk0CIazbvqHE0wQFIRaLbFQkHuPe1jGh;p+RtjjA2(0bdoA>9=23c13BM%#JM$QQ zhIp@d`_{0hspA>|kAvfgpNyV`J`H^ydJ(({-bVbr=m*e`p`S*-f_?+N9)3mmCiG9} zI(x_I+{x7OH#3$0`=Sppb$k_Y2&{s$%w>9Bhh7A4HgAifJJ1{8_onvaIpOVhSGd2a z@Q&y{&=btNo|=H34o`)b!5iT+cprQku7lsgt#H?}I2~4pM{^n9b3nK_JFP75pWEwHm^{B5`76= z1aE~8!?)l^@N-zFO}xLoU}tzDtc7R6%T49yRp^!QS-6h)572*yTTGRwXrFk0yTcB! z2RsapfHUC5@ETM5zXAO)dgUJW0B@4%vVvHkwA4?F?hW~$zK2EGcvhxPW0<9C5A%!(*F09L>ua0)yH zUS!Ju26{ks`t63>l?xkC43aDf%8qJ<5Kj^@B#P|To3~l? zf|cenJvT(34Hv;1Ol^Owsr}z&_Kc#xqF*StIXw5 zG#P!dsr~%c?5_KWDgS>Y{2{_$hhM{@j;{LxDmWWn z4sU{gg6rUy@O$%*v2X9UzV=zHV`^?nw>Fi}?a-PECFq{$e&~Vd;pi$@4bOq|O`k{f zRi@e(*Au?n)c#k(58?N)tZN+K3l4#&!zIX z2=9Oo!KdIGrnY+*{Uv%6x=dxz$9FKC49|s^!liH(Tn~SO2lR;j^oK{mDR3^l9X<}< zh5vyK4~+e^f;~;0pX1>~I18R->fW;e{XgbPy%&MY2w#bQ)_g$uf&R$U_TR&1y7sL* zz<%&VQ|Xvwstqt7{aaJ}y9#{+`fhWD`oV-hLiqFWUHFly^lU``$CUpjy!h_~nE@fc_i&5N;s;OS7rk2ZzM_ZD=YzyQ23*?~87aKG57L zijEnc9A!IUtHoBz!FTRPzXp?=&ydI2Ph>fq#OJn6g`oei{95Q~9(77O8Dxy#s6n zo50=Rp0E|%7j}T1VNZAn><0(Hqu?-jJp47B0H?reSOd?1XTuBNC2%3U3jQA60B?oM z;5~39Tn*R2r{G`Vi|}>04yp$do=4PyDndawfxE#yp}J+^d7PRd!A`fYKwWl$avL}V z9s@_g(ePw*OcZ_tYo2PYa&ac%=fDdIztWVm|ADtc-I7B1!|*ZqHhdp$hFhT?8HVlj zNHS25(gS5Rd5Y_0{#_-aR55b*U=v5?Bo6regZea z%}@_1gIyi?3)mFy4)=ol!u_FtOX~d`2oHn(;9%(S)3)=tJ##di2&ckR;B0snJQrRH zFNYrAXMfkio8fKn0r(*FxIf!J1z&@2!4Kgl@SpG-=<(X#{zq81B-RaKGuRyZx1+ZA zoG4~@*bDZBhr^@ca2UpSYrC=Nsc<^uOt1|AE;cn@ti4t+AL zhG)TZ;Uai7ycK#pruY9Bvya+a@UQSi_zwI4{@YaLy9L(WG1d)XOH*x+eW1r@TK9m1 z&7OJ>0*`|y!Z031@srTg;VIDLH@*E_cs{%cUJe(*YvA>8DZCxt4ex``z_sviFpPWA ze&0iTT&UCWclb}Z32ufz!IHYMy~iwiJC7qZcY(XZGS~(l06W48v%A_q@K_ke(I|W> zdO8f_XcRsly%=5x?}qom7ftoA{sz~<_u!XsBm55j0PEI^w{HmdgujIQ!u??w_p1H% zMh}2T!eim_a4MV*!?+%8e>(bHcmZ4h!}wO&-GIIsE`xuBe}aF3kHM$l^YCT34!#FB zz|Y~g@IP=zwT+#>4dC9e72F?|!|pJQH*!9qE8uXmZ4`xZM`9RnBu*y$TzCPz0p1KB zf{((t;rsAA_ygRnLA<{`VHX(218Kjb(4*l5I0aV28h8dg8(sh}feYbP@b}Q4UG{O` z3YWn!PDtSop`V1$!k6Hy@NM`${1R@2Ti}myhlcTf>%%6n8EkE~iK4c!Gwcq31^d8( za4;MV$HKXA9$W&K!YARg@E`C?xRV;%PS4J;BkT%~hQnbstbxCUSHipDeeezVHvAZd zaZlRsm*|b~JNN_C)UomN1K1q4fURL$SPr|uUhr420uF>n!{KlooCK%CQ{Wsp7hVn* z!CT-Ra0LwGv2?r-q91`T!`I-~a1-1LHH}Wlhq|yKEQMiQm;CQzU8eWBFpTGto{7E> zJ^;7CA7SsE;_WNoh450i7QO^a)j{+A!uTw4IQlpk##<@;HuT4E18mbY-o7221W$r@ z!Z2=1em0{24G%1hw?7!34bOv5z-M3sJu7i~8^fV+1iTtv3*Ufm!?w-h?GJzx;Z%4l zTn0abU%)UPNc-=+OYA3%`;nf5{xf_CdXi$Nw+=iS4u>bgN;nCg1W$pp;aoTmUIc#w z7s0FH_3%b`J6sO$gAc%m;bZV+_!@i{eh5EriTSFuqB8GWv9Q7Q7rTg3DnT2c_*EM?VceHdXg*fM3Fm zu#WP~@%7+NaA&v=+z)n!-C+eB2#3NEaH^@gb~>zub6^-(rTFvFi{RDpdUzuYc--DmRf530xzu*pg$H!M6>M=)Dd|&*#ZNKMHH5{%Z-4es~)y~xQ*vVA=(9=}C z*4tFQIMCEaLrq=VqfDKfv1VC3?}+;`Gp*IXn`7#{%riUcIiJ~u-;sBZ=M(Ysl_d^8 zSns1uJ-1q6>Uq~Hvm%~H#pm@IYn`u`%%gOlHjjy-56lzwJ8E-`-dmYf@q7s$2O0Uf z_~dv#5|6j^654aH9&7}gKs6VGU74xl(!aoVP=^+DC)f@4Hg)_;df-4f7!HLa;8;`6 zoK$lPoCasYS~$;Ce$Iy%!v%1$seHK(E`dwo?Ql6<0q=)vOy$!P@EN!khJ07~dBIJy1jC!+FzB5&}D!ZS=cd7~bpX{CHjrpQqktdz~*h&{X~ohC@x2+YxY- zsq#A-jx~Gg{J|-v%JVch(^R>xg>%e4dOiy0nH4&p@M3d-#vj0irpoU=MSx0|{imctdMu8aHODzi%Ce&HH(g3dR5#+)3_uVcPst@7|H++ymy@9g&_I`5v( z!RNcbsq=h-sqb(BJ)cFj*BW_g>#fW5pU;(QT?Ixpcpr0nbY zyzBh5F{M2pNO2!scj$qpGHWb)f~oU12km*8d>t%CUuWt(dj1dlTV?8ezKMRv)Or03 z{e`LX8@Zgx-t&R@JU2my_k0tgxI8Mpjl*@`I}zW_)cKFfYfhhDTQyG9hwTEVBx~Vg zx8>n;QRU-mYNB!nly5s_Wx2j49LJ@nq}(Pno{};)44?DLTkt9KIF6YpW5Ji@@}|s8 znKGRc$1#at zd6-NxADsOLW$8B$N#Q3ytGeu&4qirTjET2`KE5YT3vlqHh$3eNz zH0OhI--XNt<-esCf|#-}tmh{(%*pWS-Js$xqUTn-L}4{QKVnYClOzV2I(tqepGXZ+ z=}BQj0G~k&>*)y;!%oG``)ZDjuC%HK zQ6|^ab|ZCZZZ|xaC)409n3Jlb z@(E$RYTP(|y*<9b;}BIfX<4ODyicB}>fF_KY_V-f_-r__%G0QPyuNepPt&Kinl#H_ zG%wc|klTM%8INml{61xfosHqh7CSvfTaliB|X*H=L+c{mnU8nuc zmu{xNWJ&y;pn$Z$(emf*?XRx>5`U*?J?(F?blP8%fAcbS%ca%y$t{W9T!p0fJ0W!( zYA)vXdzseL`+ZNkjsB7)@pr8P(sp$uIweM8a=dqD?7GQLkLzEl=+e?E6UziKk){C%l)Z=PHqwJO*{x8v_0vPt`E^H}_R!v56c&iS*mv_JPnoaSUn z(zjIsX@AS*ucyN7Pp=1Z{`B+F0)IPg-)OA6x-Q^Jk@2@#7n%Dd$&&axDeLd4`1z3iwbWmdz6&z` zY8yq-yu=xHmgi>teIb9&7yE0izr>%%dg@=U{CQ51XQY!QN#8XYf1{sPKT1aSw~zi3 ze}BsOTdjA|s}-LtiNAX@{#t0KD`aGUuHzGbFJ%19Q6(@|@yU|-doJT|t^6hBc|RE^ z{yaC8{^gGMP5Ikief4q1U!7<3<@tb=zpWX6_0(VXb)GCq`Zj0$HIlz3GV<|u&|i|i zCdGy6TOxn$onV&4UnAM6XhyvWZ;?u$y1+Sq?KA$?YNswU$&&bU-!|>9jr@81q0`q{ ze@Xg0rq;>PWgC{>d&TphA%mUQJq9=Juf+@b{OhXt#NV$o{-(&^A&E2WERWClYa@S2 z{;5l!^LKj2-%|M-Wd|(D@p^1;I(^+z{tlFFlD^+%{B4!Lfr&HhEU(D;t4JMhFYM}x z{*FvK|NNWn=61l6r0=-megrQL3a` zux=#&{w@QjGpUkmW#{dZC0XD4GwpVgqo3oi)z7r^*yXIh3JI=EG~chvTh{)He~Fs{V#T&lP~RW&401;oPBA#&t&KNC0UZ|!*lti z?KaEK$CWIJ-OgG`UzgKT^~-P>+s@nVlkpdo<&RO(x#K-BV^>FZ+uLu~%zo#l_B&Gk zlKmc$@z?0T_&Yq~Z$ZkR>(#{Hn2f(>^4Cf6$znS%9#fyrm+RzjtioMixlfe%^O*Z| zK39}&|9DT%_}iLF-{_P-e}5_MZ?ODXCrh$^MaFJO+4k*j$k-kAU+g?*V|u?sWw*V0 zcZKZI`O@gceEX$JiBxnr-;d)j>Dx_{znc}8EZ&#@{JkeLvD>L->_2Pg-x{Rtn#<1p ziDYq{{~GO3XxBk@>GGG@?VqvhF1w_yV4sQIfQ;S2|HW>6#;%X-8ru;|;?KWL@OpB* zN6XIr=wwOkuFu$wl%29Vwb=?B2@kchi@8-=Yql_d8R6 z$$r1c_*;3t{3T9gm#lu4@%O6cCwBkH{${28{gmc z^4C;_D7ATX*M(7ZiXT|8ByqoxT{@pzG*pcK+25)9OOAIh{3UhN-dAWISa-}>?9YGg zGImp!7Pco7yYAQ}+dm<@fx4$8i}&lLb2fdAh@R} zY%Nmdn%B|r)fjD;XvzrA5%gII3k5orub+AP=~ixymOlYCBmNveny;!fqBJ(u|EgZy9e@c@H#Ko!9lDvAm|JeuXLtQsO-jR5gVw)C)%}DpL2# zkrnD`P2FeSUAIErRANz!3x5adg(DUfocDT0uO#R_utL@NmKOOsuIsAlip;aM!i9Iw zv-0FGqy2Z0=Xcun@y8Tg`{-zq@~8!>y61(emkd=;ok-n6lyB(t5qNM@$;vKrC=0`f zg$^IyJz`5D^O&+M+%0LV%!Me?;(zqmUrwAbN{{x|yVdvd)r)(>r9l;--Rb&!G+ici zZ~chK4Usp9+@eb#Q|j2!YaVppY&6t#tn6`P%$YZ-rrX!Je_ndVTSu-?GtD1A{|U8B z_ngs?r@qp)t1H~SLidzcKSSLt*?KayxZ881B|p8#yj|V=#1YQ{wW#s=nl@{+p02`b zv5etB{X>#68r*l(tTCQfOWe=74_ugUzGy5lp5NPG-rQSX8Z-~obXmFcA3XM0z2u># zu%!29EV&OH$alTCw_YvDhb2{C3tPkU2i9EB`GPUsP!_D|dif83JyD|6YlqL+d&_O= z*oiB;_uf*~gL$Vu<5QT13~u9dnB+wdm`eRjGqMktJO5IbQZBdqyI{JEyrTq{XEDL; zS%!QruV)mLc{f=tgLt}onKZmfNX^Tcy=^DiV`RJX9|FgmAbZ&t$-azicm6Hpc=NXb zJZ?`co>F<&LUIH#zX=aRxxWhV*1=8pSpcF#UP}I?B^AC+G;mBy zDt()1;2mwC%J(WI?`op1uyZ}~yys%01Pa&mgLq#XSm?WzzI~t#EXE2$>O)r@452PQ z^K&S;u&cjKnR86tN+80@EY^hEw}fSsXu|7jBT=e}BHtv5GEJ2F%1QV&QDL=txhAR# zySv~@g(m8J&#;!KXd>WaX=bG+8hz_%V6G+>s-jm&RhfT;lX(|F?M~#=ol&6NUqsq_ z0ty~K+1@v@$;)(-8N7UW{Ct`}hE`qy`_%m`Gh73$Jm1Sm&bbFk!-G;V$ni7|K8|r; z{Gr9=SY;^wjz!Z#ko418`D)TpX7w1<-;G#OkB8wksDC?R=_=|MXqr>4Y*HD8ntB-0 zvN2`&j3r3@916EmnlyX*8%1K zEVTPPN`;)-F7M)Uqu;d?IR{*6Xk87hQwo*p&Cx1&h+5u&@^f-fK9Z3u|F^}D%Q8Ip z;quli|M#WLdvYb=oH8q(6PuYjxUBLD_M)s`u@SC>hFXtk9Ap(LbuV4XPFfG~T-`AH zNRG2zDv+R$KB&T`(F%8r4&`qYeuINAm{eADdQ3fM?h8eg_SW$3dyC) zm}1h%)aXAf57AR>VfJ^w(W?9bD6s-2d|@Ms*r2#g`CCQ2I9Kd~xL~I`yK!sNE=&gh z*`l^NSIvZ)d#75_r2LyiV=`C64Gjz-@*8YsJ^M8IBTDt;+sfvA8)U7Xdzy6Z zxB8%uvKlvg1bwiL)Cx_Z8~RC|1IoW12{!dqzSY#b*b~NTR$-O$Zx`v8oKmZw-206$ z8_GW{8V}`au&dnr6*V}kS;9|qHP~BuY291O&;5=%$8&XbSEY4VT_+lI(NJtq?WZfH zyNdJtu*lcu%Gp&V`&Hhmrh;QNJ5@*1>KcrUe-`DjTxE8gH8LvxRWuw$vF|u4RNX~r za3jQiVz?I3I7siUX`=;cv~5iyIxc#*fSku;gVDxp4}+YKvehfdjQ2te5_k;aOi*2p5 zdbQjH$tNMXG$T>|e(>ntbr~LgL;2jm=-WNB1)~tqu_v4Y@e27q1u?yPDI>N9$pm<> zJ9yl$lHeI=B=mz-cU8f$LLaj%RkwpnP_5k~EZ;cDwzYah3!XunTRo!5H$YaV*pZqn z!a_8^82NOM)FHttUuKnTH4q!L5dv2EmK?z{tZ6hZ;qi23&0SaUER5o%rFnSg=ZbTMFPgP?(nv~HqukktPF?y=GT{jh%`^@6n z;vI9#jMBL{{WdC}?`*KJURUC9w$gW&uNwur&rk%9h~Z_PVRV-p;N=G)3ZWw2Wtj}C zt5;RSrE!`YAO*M@a zdosCP@U}!sL@tu0S+WkRco|43ky8KPTxp=j*ehYE{JJX*<*M4h26M8)7GT-Rl8F`R^dsVGhcVPRdsP-o>We9&WF>A zwZT|(<_h>&y+GD3j*=}<%du7OQEj>!4L%WJl(i`KTD;imbPOSeQxOf-N8q{Dt==>G z4pCqSu4#taMhNTVxweGJ!EUI20tYp-_a9>FE<~5wf6);j4Ks~oCU6=UYJgyuJCG@t z1wE)0&b9L!DpRg4El|5u5s$(14%u1`7P9Nmf#*6zRFada2eC+fpq9M9#LZu+wI>x? z0<*`PwBh4TwZ~P)_(=ko(t-Of4<9IkKxa_hQR25Wdw?LVz~xQ{Kb~yWJf)AwhiHX5 zHm#NL;9|uy6s!}hb~(qcv7t)_-|7Gwbg9-u#2Q3H?cnlgW!jO=#6zJDSL1mXA~O;1 zMf9StzHE4VgNL32^(G>v#CH+%R6=>DgPC>%OO+zRKLQ*1`3M&6-Puj5vbtf9BIIfQ^}c)IfnAIULWB} z#FKq5(F)rLwnDD&mO{T%A=g(+VSunw8#{+!8_T-QR$s0a`UpHA?A zO2*DudPZBMWrQUpQ=_(9O*jWGW7`3pklyG)19YtZR5 zivniK2)B=4l^!4OnXQ7uOH=Kst@T@j*|^zdIE;MWWwZp%;uiDLK*%fzG=)R+%z~E9 z^XuyydfMCD7d6$Ig`4VEw)RY1s2$#v7nT|^o(oK+2qd;*ESIsnFX6% zr6^}ZUw7}|_B}Jvwb3y&dptFv(9DC$XlgJ%yeAb+D*VVDOGGbK$%*MiD!}{Gk%>q= z9-Y*RyArWfG@BZXjE*K0u9ey}Z)7?R{mJS0ctAgxd+nCaOo9FD2G;eTvuOT*+ zmWgO&bZ|71iYQyKRHcz;#b8Qxug6tj@AmWi*7aj3jmM*-0r-(nW0TX7l!CwMnJwwb zRLrVFXlEo5ijO5jiHYgaSb8cnF+CLx%|wzTk;#_iOd=K^4@E~NV>8KU^RDT{CCQn{ zNK_B;@tNcx>zjyqj9jAD4B*;yOYd6v z2mU}bKH480k6}_I)O0#ElTKkcM^fpeO2?i4Z`isc(ACx!&=V>UZf#r9x;z{XEKFGC zE(%=O*}o+eof?jgjz&kD&ukt}MB*b8fkbp?EE$`Q2g1wSKGAySCj-q>BQxpt5p+^? zck@&$=+s1dYB@n zLpH2>2m02n0|&#PA0s+53}Co>>jn<&1y2D+WdA7N$N4qna+C4a&w%UQS*iyH6YC~7o z%D}?5GghA2%wgDkX}Ed$qW|}})b9-VMixKKK3iNg$9ji=eTJa}k$b5fxQ%rdS6!92 z&+~cr)#f#>8w`D3w&mO&JBv&Axj%1SO72A&|gU;v_-qjV{A8xluZTiJcKYQysyrcoe0ZR><|h#M{Y%uX2HdkJv?Y*B-;gL8SOjVX8kTUgemMqJ}2L{eys!Asbef|K;22&pZowRdA z(f<6b5Ghm5n?(n-M;rwmh<@}hEs!47v`7DBLQ)6*THy)Z4x~5O1dw#*z%KL<&<>Qx zYywD{^M&Pc-uco0*}k^qH-K*k>L0KPAnC8oqWNRg4wQe#CV-@WIE#J-G|PVy(U0-; z??TfrKYI5)p*e5;7!PhLOQ1dfEV=ufetIRhKR!Z1TPlUcEQ*7fL9Cu zF2M%{zb(kIMmxG3AgZA0m4fR9`vr#tKP71A4+z~V*dd6jtHR~h@AJYlrJYeP?LX?X zk#c0(OhmnOdqH2L26Zxp;$@LvR97JOBZ>wxwX^O|_7 z;8MX3!7YLp2&M$F-Rpb@1n(8(OK{rzm0*#}qN@c@6@Uz0_ z#||v#R>6b9|GLl*3qC6Rr-c5Q;4g{ryU=Z6t6-ntsNm&-hXub&L_0i1#A5N1(7z?Z zpFat{FLJ&dqF$rmD#2|;*g2PoK|Ch(3=wwHLSG^DKA~?A`evc;6#9O_?-OC~_kwOr z7}BQ;ZV{Xk{DR>9f=?0Q*N=$BO8rvkSBdcJ1Hq4l@6NaQ<$_g2>d3T_r05Ik4#V!>g- znBbIPN^rLzRt!D=FikXqt+7NfDA**(eT(yz`wwxoV3*(~LGH_xpC_pIdC;RmPYCW7 z{H)+rg4YP%E_kQlVZnO^9~OK>@EO5p1%EI2n&2_P_XUf&Zo@C01Bs^zo-W9bqR8JY zI3Reg;Gp1$;HL!Rg8Ybz`SIFLquxhA-y}3Ys-pZp!G{Eo3O*|MxS-x|p#Kx0e1>;hXwhu4a>m?l^Xv^@KM3X1@-=jb@nHufv*VuT96+9~fxfJR3f?EW)3GxFf%Etxcf(gOviCBlfBzTM9 z9fJI9i1G&o^?nNa5uy1V5#`Sd{#;P+tKjp)BFf(t{7=FE5_EHagxo90kBvz4GJ@D7 zxJZznACbRGuuE`*AU{Z=`~ty0QjNM9}DVp0r;g@lc_gX5U=Pp%`Y^#UbhLZ5Y*=fq}L0* zNl>3BklrCQzvW>5O9Zi9D;EyOr9|+mh$uHeM71a!OmKdZzRIrkkF$<*xe`ewM5uIEcCrZ7=Kjg z$BAs0mgJtPRAd;KN?15yr*P+ni&6d7pk+9TcTQxq=wIH}5BU~crDvEq_wqTCoFC;` zN#^2t7R&Ln!6C8Uab+)@PZH@{Tskxw9Zrwq_IGR=&g*n!co>)ZN@uY+xOH}t5#0Qb z>*Y8jcHnu_8E-jQo85t)J#UM#dkQmI62IL#M5|BHa5j>1sD zn{q2~JUIiFTOERUQV+|K4zu+rV>k^F!{&d~<2asOZU=aFa7&^S=+sMr=Ge1?t;gS| zI7;gIN7)Y=tT`D(8pB%8L;7_gqSM~bL38Zd!M4ZmRh;%XF=oJ{Jsh<&_V7Jqj=dom ze-b=9*!C_3!)b5EVUK+3(Leg)^sf;ez&hK(wzm%qr@i08UI%#e57RVb@2f~V?cD}@ z>%p@FNFBa{r_)}bNvQyMw8z_6+rP(qFQeA?=7TA?^$c{PE)VmHwJ_CDp zux-2vhO^w=r=uQHZUtm^Jx(BP=b;VHT{)mOV1H2$2mq*(k&$)IU zu+tI5HE#tY^X>Va$ww<}B*!CJ{+521Av);E`25ozRS@v#&J??EmL|h|f?6rzL zxUa(<*eiKAU%8N*qLw}6k2Q};M&PDq@8*lxWnT= J4(wnj{~O^T1ug&p literal 0 HcmV?d00001 diff --git a/Release/src/subdir.mk b/Release/src/subdir.mk new file mode 100644 index 0000000..3b80d55 --- /dev/null +++ b/Release/src/subdir.mk @@ -0,0 +1,51 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../src/24aaxx.c \ +../src/_write.c \ +../src/delay.c \ +../src/font_Arial.c \ +../src/glcdfont.c \ +../src/i2c.c \ +../src/ili9341.c \ +../src/ili9341gfx.c \ +../src/main.c \ +../src/si5351a.c + +OBJS += \ +./src/24aaxx.o \ +./src/_write.o \ +./src/delay.o \ +./src/font_Arial.o \ +./src/glcdfont.o \ +./src/i2c.o \ +./src/ili9341.o \ +./src/ili9341gfx.o \ +./src/main.o \ +./src/si5351a.o + +C_DEPS += \ +./src/24aaxx.d \ +./src/_write.d \ +./src/delay.d \ +./src/font_Arial.d \ +./src/glcdfont.d \ +./src/i2c.d \ +./src/ili9341.d \ +./src/ili9341gfx.d \ +./src/main.d \ +./src/si5351a.d + + +# Each subdirectory must supply rules for building sources it contributes +src/%.o: ../src/%.c src/subdir.mk + @echo 'Building file: $<' + @echo 'Invoking: GNU ARM Cross C Compiler' + arm-none-eabi-gcc -mcpu=cortex-m0 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -Wall -Wextra -g -DNDEBUG -DSTM32F030 -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=10000000 -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f0-stdperiph" -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/Release/system/src/cmsis/subdir.mk b/Release/system/src/cmsis/subdir.mk new file mode 100644 index 0000000..89b464c --- /dev/null +++ b/Release/system/src/cmsis/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../system/src/cmsis/system_stm32f0xx.c \ +../system/src/cmsis/vectors_stm32f0xx.c + +OBJS += \ +./system/src/cmsis/system_stm32f0xx.o \ +./system/src/cmsis/vectors_stm32f0xx.o + +C_DEPS += \ +./system/src/cmsis/system_stm32f0xx.d \ +./system/src/cmsis/vectors_stm32f0xx.d + + +# Each subdirectory must supply rules for building sources it contributes +system/src/cmsis/%.o: ../system/src/cmsis/%.c system/src/cmsis/subdir.mk + @echo 'Building file: $<' + @echo 'Invoking: GNU ARM Cross C Compiler' + arm-none-eabi-gcc -mcpu=cortex-m0 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -Wall -Wextra -g -DNDEBUG -DSTM32F030 -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=10000000 -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f0-stdperiph" -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/Release/system/src/cmsis/system_stm32f0xx.d b/Release/system/src/cmsis/system_stm32f0xx.d new file mode 100644 index 0000000..264a885 --- /dev/null +++ b/Release/system/src/cmsis/system_stm32f0xx.d @@ -0,0 +1,90 @@ +system/src/cmsis/system_stm32f0xx.o: \ + ../system/src/cmsis/system_stm32f0xx.c \ + ../system/include/cmsis/stm32f0xx.h ../system/include/cmsis/core_cm0.h \ + ../system/include/cmsis/core_cmInstr.h \ + ../system/include/cmsis/cmsis_gcc.h \ + ../system/include/cmsis/core_cmFunc.h \ + ../system/include/cmsis/system_stm32f0xx.h ../include/stm32f0xx_conf.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_adc.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_can.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_cec.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_crc.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_crs.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_comp.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_dac.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_dma.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_exti.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_flash.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_spi.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_tim.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_usart.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_misc.h + +../system/include/cmsis/stm32f0xx.h: + +../system/include/cmsis/core_cm0.h: + +../system/include/cmsis/core_cmInstr.h: + +../system/include/cmsis/cmsis_gcc.h: + +../system/include/cmsis/core_cmFunc.h: + +../system/include/cmsis/system_stm32f0xx.h: + +../include/stm32f0xx_conf.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_adc.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_can.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_cec.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_crc.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_crs.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_comp.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_dac.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_dma.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_exti.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_flash.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_spi.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_tim.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_usart.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_misc.h: diff --git a/Release/system/src/cmsis/system_stm32f0xx.o b/Release/system/src/cmsis/system_stm32f0xx.o new file mode 100644 index 0000000000000000000000000000000000000000..8148622c3a76330c16c3ff1315aa991541014f6d GIT binary patch literal 6080 zcmbtXdu$v>8K2obKkv@(BtF|o*N&UGZSG||kEU^a_SuP@#A!G?ZR0lB=kwZk^}TYt z7m})wP})+c1WKS!BBhj<5G^XA5fM^_iwXrwAu0W%jevqgNedF9DlJ8&J$~QZ?0M}} z0*OzW{e8c0zWHYMo7tJ!6T|y)Snh>e0JrbP`W0)fmTp9f#r(wK_aGEh0NaqFNHCO zsB!RnfUfUgwhqA9ER4m6!pnaGlcJRM5je_zKu}p$1yJ8b1I2d}JRJjgl4U*F5RNeQr;2!I_ab%nydVyD1l8)#1gUh5!|Uflce$v= zFN9v_8i4+S(3{-%QG;I!((Jl%5H&9f(&qj+4dYjWXsl+G*sqmm0nTmeX0;N%ilAH7 z;xO9CVVfWhS9lbGt{0@z{Wx{8T@aW16p}KkaAib>SaZ1>*I*Kl8zXCV@ znKBi?>OO`?5S8^`hEmJQ+Mzqh&~O9>e)krrMc2k2GPH4?gQ>|)WF4nGH1#j(Y}H28 z@;6{%Su&q_4t%wl$};{Jnro6Z^eECHqU|MmKhZb_S*(2#lr?`y{4A;Oq3|=FeF(Xe zIE4SWg`o8iY|5!@t1i$KRrUPpnntHu(^_+IO+Bwew@N2-I(Nc^Y^-K#&35Mv&Qa`H zj?IjqY=eMu>4iC{=q-8mdv+J^MivPa$5~I8WLVYK~B~z#UaX`lGYTgV}H6?bF(CLa(Ysa8u~TbtpkxUzn+@WXJ_?U?^f?jE}D+T zwVZx5VI(qXt$R!G`oPx1nl}~8=KErqoT(r4rUKw*JfE7;yz`p(Mnm&rYWn8Wd35ES zOX-FYo!7ldJw0#6``|ohB<9nIAB#tGU~~C&%tUmrp$kO&x!I^0wez{0t{Y}FjTxV3 zkzqQMZ#*!uclc0*<zP|aaF@r= zc)QjW+`N6Omll`zNVj*(HUIZ&qwR=xZd_~&oGEwK;3%U#(GuFC25Ra~IzFx5t$cwm ztD|jhu%_;A$35!3R5uWSAxe7>;~SusA@#I|#{#U}RWVk@8yro16y|c7 zI7^|u&JqWEt6=GbDs4~w}R9BCD%nDXK6zh?X zD^H3T>oi&Cto^f{ni8vKDxbji!Yn4pM}M=+_umyhEP^pq<1%v_P{HD+F)2uOIbm&a zy(>snJ#ipqg%C{`P9N4zh$~c=wEHEB8wUL7FO2*LB_5JU{}p6kkVrWqewW10Nqk7+ z8Hwj4(z+!7*Cnn-qKS(u0dS|}QxcC$yjS9vBt9nbNr^v{__D-5O8lEd`URwZ))KB| zY=`6{g!uazlYCO*oJ2$7aY9V>X+kW7hot?hl7Cb3rzAfo`Hv(Q|E1{v1>*R`E=l}7 zA?D+CiAam+hrU|skM=D>T6=`860ed-dl1>_l1UhpxLM+m#1V-HBu+>a>j&+oB~MAD ze;cJp z2`RYGIG!@2Ge9#}#JHv5JTRG$ZXnDzV;Iaw24C?D7Du=b_a(crbbQO>TD0{o-vElX zmD_-bG^@|#=cf|sxeR(0dUR$6S1x9&#U;>AqqvvN>lhl1q}b+4OEQthow`_ycVoU- zCY920iLkYr%SBUg!nMyAHO*XNCT}9_|1Pwik#ezbQ7g)?UGP~5X~&cNtkZ9$AJvg; zM4{>VZ+@HLv$Eg!V6%kQ5y=3G-ER{}R@4+9mLKhxbn=CYX10hmN^6JqTPz>(14ZLH zj6(6O@tpyowQLF1k}w>Wk_voxVq_4cVUp`M^q=t?skX?c;j|<6DF;jgRaU zkH$yevpwFEs7Tukmip}#ey#X0tF1~~-8Z1y`+XQMtHF=@rEk;f_q?qQRCYD49bKeI zu|hu$ZjX1qeksp%ld$5w0NrXsA;u7ozF|wOy60iA$Gd=dA=qeqG%r>>+Mld8P}wID zuh(X<)K^hwk5`Aio#IeDsHJ#sLZ>#?n7)VP|7pd%QT;zw_&wlc>=xK8As#R!DS?YfPZq#ZZ literal 0 HcmV?d00001 diff --git a/Release/system/src/cmsis/vectors_stm32f0xx.d b/Release/system/src/cmsis/vectors_stm32f0xx.d new file mode 100644 index 0000000..e1604ae --- /dev/null +++ b/Release/system/src/cmsis/vectors_stm32f0xx.d @@ -0,0 +1,5 @@ +system/src/cmsis/vectors_stm32f0xx.o: \ + ../system/src/cmsis/vectors_stm32f0xx.c \ + ../system/include/cortexm/ExceptionHandlers.h + +../system/include/cortexm/ExceptionHandlers.h: diff --git a/Release/system/src/cmsis/vectors_stm32f0xx.o b/Release/system/src/cmsis/vectors_stm32f0xx.o new file mode 100644 index 0000000000000000000000000000000000000000..03181541cd811e7e4b4e1680a78b7fa465bd5667 GIT binary patch literal 5176 zcmdT{U2Ggz6+W{+@j759KWsUf`_)UJw!zQY9oFDnP0LwR~rG?s(?L z6-YdBv^(GV&OP_sbART}y`Npad{I#p5~9!y?J%O7``wcGoC`B_l#bB*?+EYzU)0`9 zyn7ev$J{Q&loD`!KYG3$>^+PTWzRb>MI!M}GsNP5U`WKTGbo8u>=GF{%n%z{U`UKC zqbwSWw@rtQXTV~2@KC-`M|m87QeOBXo_k{3c#eDykHqK}p5MfOFFR#uagT_C_aiS5{`Juc@%B1qp#DTHs#IcEuBa_PhBPcmRV`ERigfu)gfgI*2I&pUF z+*s+rh3Utq5%REaKrZ*8PU!&Bd6*ayhv+1HMir%WKmp(T0L{@KgEc#6H5hL~nUHDydZ3zGXW` zH*H(BbggT*ZK5rs=JYIEvz_j2u93NUGgTX|-MAYy`uUg=Q4pnnNjK{q!=k3vZQy_b+D`p^(;T2Fwb3pYwr!<1Fd609*WYYw8THhKm` z{YG7P^dN6ohG9DxhPK(HT?R9~+gSR;!DHi&#=S$bV`itK(a;ASM-u}+9AhrgxcS-* zN^j{_+HBZqtJSNw2i^5a&<(xXCgowM@xpMDS2MI{d}MW0nTj1$4k<^XN0n*iBg#jI`;S}Q zfAFFg5~FuN5ISQtv^z5ozCq00eZsF2#SVAKXRL%hMtq%>DDjrG zBT?GBL!d=NBf=b;P(Y$I{GbR^l%|C0Vw5H&evppA!ehccJ&yc8Ch^M>?@F9E*Rxe_$3Z5Fl7VzG2J)QNntfMK}0 zx)yZhTthuUo}pT9=GmZ6WvvwQ01uUya)nSic&Hrx$%Z=wLueG(BQ!y5kjG?RE9OJF z!%2=Z8_XN!p}aV#hQSMT-!(0jpVT(iwDs}|k5;hQ9l?ORw{HAp@gYULu0EtFJTRe2 zT)wtmn$yDLz&0rwn=)D`4zGwndlxU~E0=8`&dkDo9i2@I0u+92=)rb7Sf{+6xm~^qh<2ZcF6uy~ z+la@0LPXhZ7=rO`2jcPjEaH6~x~Ri3wh`|dE1rn5uYd>RZ6h9!E9ZwH^5cCAI@ihI z&+;e4`>O~7&MN=E@1gMf9TJk;WxqE(KY%M4Ols288Mq%TKfynk-;06%PN7Wn_vg^D zM*9F))({U{sW03n3nNnZOq7cf*w2wVh-k_s30hU2fZi+6b0AsbysD2#|;sDQ1!jP zdiC?FUe7%D(6PgubEb&13D%bwySXf}^?#49&~(j2Yulfu?=)=n7AwNpdTur`y7oGa+rYcBsMjZHZgyh=N zO*=JQ1W?oF7$4_bi>pWU;>P0K`f)zC9@;HzWaL4pu+()-FYX%IJ#ut4)+qIejx$sG zeWg8Ea>3&JN~vmFX`HVr?BDR(!4k))p%*T3HqI+xhb>0lK{0j20=Cd1(9|IlM~f#? zm`Z&)tEZi5>}~4#U&R#+>Bb>Ymbqow(Zwhhz8!_G?RLUgT<}?6>jiGRR~NSHM_$D2 zUKHAGuVy!0*LFhR3_5`@g;VqF8EeX_*wUS`suy^%=d``2MYZLG_47_BESIKCr>jP> zKQ-AXU$|hkXm3$mM`lgLg{;$N^2v_%oqV&t$V{s>w1wODx{)x?cfzw#*KtL1hRtqNZG_@nC>myY zs%)PWZQ(?szXulw$a>hx)MQod^44yaUUyYEVf$jbdOCt5kIWgfm5PyM$(Srx9w<*w zP8t(oI@fmNi32B(+rqDjdR^4b8M78Tf!i`dG4DlQCom?bD?7_GXAIMKyS=^XJu&?< zvx6_S=Hu3H3#lp5(O5C?7q2ib{l( zL-o(n;u&>T7_d{_?UO!Gu5`A%Zv>~akpX$dfV^@*9v_fVKQpAWRT+umuVovdp);ZL z-;DjtWIV>eA4Kch3+(iO{dT2o%WX=Ce2SUkv~;CO9d5mAS*6m#zZ~15%q(AvZwOGs zvC-Yq@bRG&AcQGF`Z8)T-c5+(n~-{2;)4 zV(blx?@Imqg!ssRBJsM^eNIiYe zNl$N0!*xlV$)HL(DC7f z+HN^<9D220jIjTm)LT)nc*np{x|2k7*XYe8A8z2FAK8eup;6xMyqxI4JD&8gVY7AJm6~eQ`NK&>}AuFCtZ$g-mJ_O2k8GLr$%b1Mb0nJMl zR?Yhscr^wryAFZ;6e-)AP-Np>MLYvKiboY%#rqJv8UvR72;m!IBq`f9$k}+GAs)SV ziboY*#rqUIjiLKM^brz&SS24a*{I!+sQjotoQ6)3@}vJ4#4CCde*2XGq7=k8V)C?!ElG?IumcEpza{uq|%GTKeAet!BX{r22#@BNgy z*N%VvkJpaVCv+i4U*&&;;9TsR6JG%*=QW};v0~I|V(cCGXjG!D(W%3ISenC6}e(JC2@;CC>r3>i93Oc%ix!*nt zx1HQE#j1nTPb!gXs{dV!W!{ol{y>|426kRIH~nK&bLMMk^!GJ=_7$kKKMH;JYGwvP zCov;_P?{_1rOQia_RNUsJ<#u^V)16E5Of*or9;IVi|cd9e*-b(ua03%c@#_7BIqW#Og;tickuEF@F7 zX5r^zVMff39hpCWY=Lv^yi!!=SaWyr9%P!nl7=GA&5Wfc5(gS^m>p?YjO&T=fRf|M z9M?EYS@~laG>H5o>1^%s{-K5`U zY2#R3ukW{wxZ~S2@WXD~mra9(qwAZv3hUL{Ce`bwPH#}`w#{V}y-jUD-~_hc3hkiN zZ*~Ws-RXPM-f}|M=~>}c(DmE4bbH;cP?`_+gZsiQ$CYuB+FN1070CMo*)q%f%J!!0 zNhg$}iMc2f)ox8DwOTty159<_ay_D2yf;-8s@m(j_fd7@%=#*3zP-B1B6xWxPMtBT zm5LGXhOu0(94xOaFB?liGUTYrJ17;&|e79o+@_}yH?fb^^O67;; z13xiL&)pgvPR@hrl_5u+f!8q1wqc$Q4HLU{xa|)xl-crR7&>if_N3pAI)~xhN-A#h z!XUKg}uauupo zkJaxyw^=hpBBFEU~?mz3UC$e%#=Kdf+7;q3}H6t)%m3LjGV zq{8zGUsCvIh3_i-r^4OXP9ASj;q?la8L<^>3hz|dR2V6Ij1lp_Q24CExDMDVt~Tdk zV&vUsd|M%(0}Wd=uVk{qb6(^$fKiZOC*^RCaR>S0lhp`AvRGkV@|an8tgNPN4BGXs z-|8bG=AA|ZuM}mh4&JV|M4nN=rJ7#XmuU)2ge0GW`K9JHIHiUan6%KmLiv61M;`y@`C4Q~;)9F=nPs|Kf3>I4;B)_GebwdVl1d zT}ckaIHXMpkTl`1q$M;p2_d8nrz8!nAwQ@2AuY5e38e|p91ew$bJ`RVNJ0vU`+aZj zNNdA6?KvHL=DYX4`|iE(zWd(38C}0+WUFBqD!dG}Ld|eWJ$0^biLKGFLiMO_Wo=WJ z|Mul*^61vYX7kBcUb9XZ&%g3o;>6Ld(JMO8!hhqJhZdE3-BK#5*{Ja)5Uo{sxIQwY zK*}`Y-yxVW53Oc2wwREJoziWIA*h??tb1ZgMSjG`nyc6loweGe+N>;u(G<%o(UV)y!B?L8dmXXr!O zhe$uL6ym6gd>6K3pJ$iIVUiF25-M%c_UOkULauLvatG;I55P^L<9?9s(VHpwHwxa; z_Q-j1Gg5gKi_yoAT^LZH(CN3%fpS?j(BupfY3>%t%v zZ_wgJfv49gznFBwK8DDxOGvlcKSw8P1L+R?`=l==J=dOKWE)94b^)oghDa~4&u8CF zq?4*M0tX4hx}p;bHkXLCgQT)?D{F-GiLN_1mR*cl8C`=6X)l?mp;|r+TmmIMkVUHV zO$6{U!#aEo?dg=gm!z^!<7v6{8nwSm6B)*ouo-}r<-l)5a%ie$0uSC|vpsqpn7MPt z@l05alK}g_7~KR(W&b(HIjJqf!X}93Jcouc>#x6umbg2vtS@WLxLZ@!!&))!PAcnf zNG9y_8NuJK1l?+HVg62$Zi~Cwg0dcYKTLJl#~`sDrM_d&q5d~G@CCL({coj^(WLzZ z>Brs;y3f9bG5y1}pjX(JG2f5hf#=G&+sG>GpJ;OcG$Q+FMz$U_LVJ?-FR_0@U*G>z z=nvTo*!QW=<2f96OX&Nr?0cDg7wtbo{So^l<9U`_-yWMaW&P+?v>vb@CjG*3$Pd{s zqL=j|SK52*NzyN|Z(hwKP`z6}IH+zem~P6E%{S51!KR*JJXS=lYfKK-xdoh+HMN#= zAv##2*wiq$&Qf{}n1u6_nU+@Pzv;KA`*b+{FmL^y`Cnx$QvThl0I>=PaU!!G> z6Jeim-Ll?s*itiRV;8=}xru%nCfDPTb2wJ3Hw}UaH{SZI%~hQhp7kgS*{O^U*) zI7}V(VkOP!p!WwL&>Ji3L@ydM;2#Njl=%=tU1Z#kVa)$E)^n@1)OZW+j$Wk8G_4$$ zLqE@;o2avkxm#{e1DiAxcm9g|#%5z1 zv|CjRVJA9Bgy%eIoiKMLVBlq{-C*(;K{+>)`JkSbsPleW`+cpIa4vvn>kmwpc%Re8 z*gmAEa+_12+8>%3^xxy`pxTZ2CB;-aKc(7-O&0!`!=-86q?vK&ZYWzfYi7zxu;mu> zy@=+7bClLTVphQ1=zNvod{q1Sl=BF4_(!_Wr=5?`z{fQ67tRB0`M74jd$b$R7FNmz5Zbk=lFuvU+2}cKzQr)MchO$!Vzs?14NLY+GYz-3BQ8t(lgyH#uyywhM4KPw~2+7`O_}7@;QMvo=^#yiMq zVreW$AxxN<^gghh3t^W{+iN+)o*I#o20Gr|_om8f zMp~@oN{zfX-I8wjwREYNO^@bs=}fJhs#Ggp%FASn>2>|9`v=p~L21RXcg34zA9#8v z(`CQtE9Fh)yzzRmT5-oRm3+yo`TaSDxFwWt3&mqhmS4}~RVRfo`p57-pi0%;5l~2x zTR%4L`2h{ByjKV`f^oWjy}Wu=VPI+sQdC=`QiM{VUGuz3Js`0P;RI`RgVD9ti9Bm2 zyCR*ZdLlO%$;kXKD=%AL&B>eX@7^Su)^`P zQBZC+nUbrA zmhp4-V%ZCrAca8`Z=XZuRVIqHDgwq@MD^&%%E-B@VtjOs(yJ9&fgIW~4~2jh%qgK* z!5HZu)2&BNLqP>Y;OC2&%OWg{X3FJ^4iS`^M5c5~v93y3Wy&4dJ-ox+w`KUsefzf` z+~OX<>T9k%HyG`hi&R&tm3v?w)5TrR z>V>Gi`ayAui0iAVV6eBLM39*M2Zv{-Em(|*GY5MWyr{Vt;<%S97K&azT&l%N0i!Et zrY7^8T<$uUSkGf2<*E&G?nH*mhteY~sRKo1VtQX;J|>wDy^8bI1_HzGqO+#gu$wI% z3AP9QoK7=q_wrp=CWi+HlX|~St{NCzKd^Sys^p4Vkb-w5uimt8XWA=gJ?x$N)Vfp_ z+gENZS@R}}KKAG2sg+>L%T&<+AM-kD#z%|g!W5PVlP6gGb%TljM zSr&CH?jvp~!!j#W^iO~aHjXm}?`HDM@|7dlR#C5B9X>o}4os<<#mZ`0^$nzJ^(vM^ zqtfs(f858hPB?3NcXKP{ObJtt1+{ifCRm3Umdn9l!RS&Ay22;stmx+%pDvP_m76P7 zxvkdl3xTzU|E#p8jeL(+$?rcnGyCHgz`tIGECF@-@bE>+6@wRCv@XTTOdVa7TKlg5 z_w3@uOR3Yi3}s%|)@o~>zlgke5Metn()_6m`S5TP^5G#T%3M!<23cQbIIF(<#1AI-i^;% zIA?F8_%6lRaL!*z#N@JeO-vhW)x?7tCC(G%e3-Lk%$PpiAMI&rUn|JGvEOBaI|TO# z9u~|C)&!psd`a-4QCCKkAY_AC(7v#4%%I_3BDfk7!Q-a?XKzxnN$^g=&j~&)_<|t6M6zETOOMzo$jyiR`GRW&`Gtb= zn&3@>cM6^q{DR;q!EXz`B{&<4l6HCo@gl1ELBUG}cL*L5^aN{y*9+bv_zA)L1ivWw zb-{lWd`6HT+!)6%1S425x%>JLRbD)VWeEQ_Vd^TU$R`spDAXUo2<>r=g!XoW4*P&q@4;{WubKoQnK?^uKNiFuc91L7R#9zA|Y4UHV(eoUf)8cD5E`|Dnol80v+}Nss0`Iu4)p5%dK) eVJ(AHCDh+XNyru2V+_rDt$68qEK~x9djA8&m15xl literal 0 HcmV?d00001 diff --git a/Release/system/src/cortexm/subdir.mk b/Release/system/src/cortexm/subdir.mk new file mode 100644 index 0000000..a41ab99 --- /dev/null +++ b/Release/system/src/cortexm/subdir.mk @@ -0,0 +1,30 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../system/src/cortexm/_initialize_hardware.c \ +../system/src/cortexm/_reset_hardware.c \ +../system/src/cortexm/exception_handlers.c + +OBJS += \ +./system/src/cortexm/_initialize_hardware.o \ +./system/src/cortexm/_reset_hardware.o \ +./system/src/cortexm/exception_handlers.o + +C_DEPS += \ +./system/src/cortexm/_initialize_hardware.d \ +./system/src/cortexm/_reset_hardware.d \ +./system/src/cortexm/exception_handlers.d + + +# Each subdirectory must supply rules for building sources it contributes +system/src/cortexm/%.o: ../system/src/cortexm/%.c system/src/cortexm/subdir.mk + @echo 'Building file: $<' + @echo 'Invoking: GNU ARM Cross C Compiler' + arm-none-eabi-gcc -mcpu=cortex-m0 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -Wall -Wextra -g -DNDEBUG -DSTM32F030 -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=10000000 -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f0-stdperiph" -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/Release/system/src/diag/Trace.d b/Release/system/src/diag/Trace.d new file mode 100644 index 0000000..5f594d2 --- /dev/null +++ b/Release/system/src/diag/Trace.d @@ -0,0 +1 @@ +system/src/diag/Trace.o: ../system/src/diag/Trace.c diff --git a/Release/system/src/diag/Trace.o b/Release/system/src/diag/Trace.o new file mode 100644 index 0000000000000000000000000000000000000000..3d146cf4ab15e0bbffd1bb82936846622f11c894 GIT binary patch literal 1188 zcmbtSOKTKC5Uz1{6Qdq9D84|(i*CT4p4r6R7|0;@zU3wpkKd{y03RbQSTyl@-`tT@nvGYjD7rD>$QHH98rg)6ZC z@{KnNLvQGB`k~hk!tG$t?|VIo6BG(JymxztV~%BnNrDL*vPg<5&OM1Ig(~XG>kqE z$LobpcZSS#j2-vcVB^1A2zvnyMxclaa2}D`9nHEq4q)Zl>Uhmr@7#25Ik(+A&Ryr8 z^Pn@GO=)UuFDcDqS6lfLTgz>twyzU=>^7pikqI;m(F(o zEXj7@;hbkXaGq!T`j~i^>0HEnGOtH4m4DUSrl_fHMsLLMw(Mo38`YfA94#*==Uehw zvAhFv(Ayg8|3QJ!8ia;t#Gw6mWB(?{cfz&#F_XVO*X_TO312D6aIDyRH^{Nb`$oL? JmPBZIe*r*fwqXDO literal 0 HcmV?d00001 diff --git a/Release/system/src/diag/subdir.mk b/Release/system/src/diag/subdir.mk new file mode 100644 index 0000000..fa2638c --- /dev/null +++ b/Release/system/src/diag/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../system/src/diag/Trace.c \ +../system/src/diag/trace_impl.c + +OBJS += \ +./system/src/diag/Trace.o \ +./system/src/diag/trace_impl.o + +C_DEPS += \ +./system/src/diag/Trace.d \ +./system/src/diag/trace_impl.d + + +# Each subdirectory must supply rules for building sources it contributes +system/src/diag/%.o: ../system/src/diag/%.c system/src/diag/subdir.mk + @echo 'Building file: $<' + @echo 'Invoking: GNU ARM Cross C Compiler' + arm-none-eabi-gcc -mcpu=cortex-m0 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -Wall -Wextra -g -DNDEBUG -DSTM32F030 -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=10000000 -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f0-stdperiph" -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/Release/system/src/diag/trace_impl.d b/Release/system/src/diag/trace_impl.d new file mode 100644 index 0000000..8fa4b8b --- /dev/null +++ b/Release/system/src/diag/trace_impl.d @@ -0,0 +1 @@ +system/src/diag/trace_impl.o: ../system/src/diag/trace_impl.c diff --git a/Release/system/src/diag/trace_impl.o b/Release/system/src/diag/trace_impl.o new file mode 100644 index 0000000000000000000000000000000000000000..78c0250ea4a0eca77bc7f2cc7a03ed8af23052cf GIT binary patch literal 1196 zcmbtTO=}cE5Up`HiBS<1#V?TYq8mt0&ulcC1ojXX%_UI?2!cxJnW_1}?b%6pPc$d5 z9zFSw{6T^TZ(6-OO?Ct7!Ghjbuj+O6bXD)CXZz1R&jV*3^x%vE{J1d9EIpY*4=%$c z*n9EHA4QQr2sVPq?}yP=xY_UfJ%wWw8rS?cyN3rHWsGTxDI2g@i7F|4g(syhCzapd zjJCtUJDR4gM!i|t0&Mpo?!1bv%D7jV%PfL+=qiEAnDeG~N z0PKxMJAN;Ex-($5ZS1(uHrM{UkFXokbOegH1n&{KOQTs!4?*+AXW>NvbYS)8&ZDCpk6rn@8mwE zZC~8i&i(^udt4VDwmR2^^E%ht$E3SR>tDL{wjROM{#0*^vbMIJzBQ}cc88H~UAsmt zI-R88Yl=B@x_t`Jx79BGjS`U~gjQ$GqPx50KPm8qaJ5}_`qx_D-IXYOrcGC^)0(Sy Qo%p=&E9u@k5uwxl1}#*&@Bjb+ literal 0 HcmV?d00001 diff --git a/Release/system/src/newlib/_cxx.d b/Release/system/src/newlib/_cxx.d new file mode 100644 index 0000000..4acf981 --- /dev/null +++ b/Release/system/src/newlib/_cxx.d @@ -0,0 +1,4 @@ +system/src/newlib/_cxx.o: ../system/src/newlib/_cxx.cpp \ + ../system/include/diag/Trace.h + +../system/include/diag/Trace.h: diff --git a/Release/system/src/newlib/_cxx.o b/Release/system/src/newlib/_cxx.o new file mode 100644 index 0000000000000000000000000000000000000000..5701f84ad9514a367689721f913038edadc1c200 GIT binary patch literal 10984 zcmbta33MFQmHk!SvP!ZnWUGZG%f`ZO*|O#CmSlOwfQ>QOV2lHH@URuVR7;I}qpRDJ z2^kocU>Fv&C7BEcA0WXjb4W5_Cpk=5GDA4Q1QG}khQl&s0yqpy*aDt=f4x#Sh9NU& z>bUE^_y7Cvz5o9EuYQ$$_Nui<7>1$z%TPV4%As|(?x`Ep(4#t3yK1>}?+2gl_3r2F zr&Lh)1&xaXpzj59Rh@1byP0k|rJB?UP#icNt-()&!B6`@)R}`*#sdOpk2Vs{*`?v! zm~Q;mLJgN3t>Mxk4VRsz;qogqY`;Erpa*u|q_G-AgrHMMP>DKV=r5e7oLBl^} zG<@$o4gdHP4LhFFaO1lgZu(5a_uD5>%Ma#gxOt6+UBen~xlqGx*J`-^Uo^b^te(R= z&ui|zH#NNfBh0-n@Mp7`@ZmHKAGsPnp0DAP<2C%{YJeKoZ6Qp1pU0?r9WleOf`*aM zTK?6u@GH;4uRROTda7UXRKM!!e9hDOx~o=TS}tJ!2&M_}zI zn02RXsDB=#CIsuQ_jK$eXVpJL<=qe%*Yp-Tnm&M*`gvh=Hr)ZY>PsYB4uaY`$DsL% zR{c%i#GqTyJ}Fp#^LAis1pW29{)Xg5xYggnUKP5O8op1xDs&C$ThBmyP_;D!?!|9^ zY7D5R*Wf_?Z4O$Rmf}`_$70+k2it?s05P8@F}Q}V+J7#{DM#bhZpBu>cIXob zSp6hbr@dKO12h^8CE2WLD>Mjkk8TR3s71H8blRiJntvpfsP^C<2(`U}+X-mU-oela z_?gzC-IVEtUTcXrrQcHfQqNMF?FW&zLY>GLYZ>XL(36O#buj6cPzegGLr8~08G3Li z>Gn_=v$vL$o*Mcc+gFh8Qd27c%dn1Wfs)V^`hPS@c#6wfOZuE?%^b0gJ}YC|T^#W> zGC@PNJpt^3ke>AvpEx+R)e8Av=dLE-3n<35}f!p1c$2H z%DC|-I@^P1f;nKy-*OICWha=>X>?)>NfnwwPe-(7XyCd}c^jg`)}6Znopw=KcWKE^ zyQHkUwP2?`qO5yJTA@35zqbwJnnL%`v-?OlciM@xvhM!|Y_x>-(8dFlZx3yw{6n1h z)KG%*kCw0+U7^j4{l8rcdS++`XZzTLpnF2^GJ3y!4)nZEyOL1Wuc)&RG(3BPo-GCq z*LG9?ve1dt|I|y6Ump4?$3Fcw=#`yz7Gs~`*uz7QQ|39!uMNFH`uUacWPRvj`uXA> z%zH!VF#7ZI!)V_W`jD}EmHXl3&}z27#<3|ioj~zMedDAWpX810h~`J=>R?ybX3VH3 zXq{$qvIo9xoo%jzZ!>mVe`ihv5k8ilo@;WqsjxxjJd>J&;YqZ2zIkN>Ap9zOE-;z< zGsDND-};tGTdTtcLw2FrkGAz;6Gp6U<}nzvDcr`Mi%fby9Nt9*7i*>%o`#Xu-)m+x zd>wl(F>k<_bHd|j^iuQ3V77&0?72+a*%@x4(aZIio5Cg)Y}d@~;djYgp_!kAw=m{6~2ZRcbLBhGpc4XcGfj! z3t;9$?72?IOobm~M?$ND0-7H(kHnZ@m^DurE6lYOrYSswV={V7OSnYGPB&l1m{9mA z_T+R=UwAQ@y!ioo2E%XCx1#P@9A3_zl4;>_uq@ooI8{uRwdLVq+S#JT4i7hT2}X3! z>hL7adDLvin6=^WQtTUAY<>6@dVQ8&>J8zODR#YC4-1>RSqiKhO>Y0yM)#*2bd%Wy zZmrSH%&>Nu)1mJLvwJ&r{FB)PUtco2i{$Pwd(ro%i5%oE)_MAEcvO?8nw30#5&GJL zqY#+B4kR~TjU=1=jJ|;~9K{V;mBHvo(V!n2+-|z|m>#d-mlW!jN9f#i;|G|=EEh}J zWQC0t=nw11L${_?_#sYjmO(SY@TCmOY=i4+!3<~F9;D7$3$S|4)}h9^R8ZowEZ4LO zzfWd`X2ykQFl7!irb20xY9nwj`5y9_#hllChiW6wwAXyS$1^E4KUuZ0;4m*WKTWl9 z$1;C>p5x!~`F1t?131|pWJ?cIMu!XypQ52X$h_&{D*EB=2HhSE;oin69t1)wHr1RP zIj3lV)nv{xPAL|65A;Nm^h@~G zuw)O&_TYQC>uj-b#%vtBp{E%Qb9-OruoSa-UOeHdh9l@MkF#DpB7eY~8&*a4r#EZa z$HQ$SA8snT2$N_y<}@_$*T{6{A?pQ5MVGPfYaGDyuh$n{!N%h`S)PWa@qMrj8(Fw{ zHm0&Mp{OB4eLSXX&s1~+ zEuGE?@X)RmOV3n>p~&goz#e_mwSY}nnO$hb2{s6Q9i*c(=uVcZc;er8Kwp&Im+&n> z-jMjg2RpRxZ^4v&7!)VPeE@-?9`O@))?z`Bn&m(*p(cLO~J>ytn6z*pu%`|FC0&@q0 z(a$B#b2faR@Prs86&uI6{(`R;o(}^()MpvoA$;4=?+t2TI#;~G;CAB6N6p*B0M#@E z^#Hz*cy0}}BC#79bt~Ub_MOYXztf{;qaW__#bw|A=yw^ZotL7EziKxYIoJfB2QHxF zD~wMdcgN=?dgsI0#umoC_dJq+VNiPSMk+Rb${6(SfpH=0;ir%Z%I>AW{JSAwEN{en z?_d+iDInOS+W5#Jr_0+U)j^R3e7`al`NBtn;2V}FOil}Tst$@QoQ$sVSI|lz4Stae zPFI1&)4}SOGK{4$waywN$3a>PP`X~E5kpH$*HOA5Y8=|(smwR8X$}Gmb+6-e&D~0wy5H2w+llOy7Y%T&dcg)hhPHDwdJrfk~gc=>EHLX-LRrl8U zftyxi1mQTK4Z)t?CYHL!Wb3HuKyg(wGh`Z?35ym?kTzykS=7iXvltd;jd`a>&Thqw z8OsludJ%x8Lv@tr&Von1(u!$%t@EmD<*!tvxMQo3s#3_Ep=w zHSe!#;yCQKF$uWk$;=;X8V^NOGe{rTv<`Mm#fmS88b`Kv>C{|Um0TlDcnbPUf)}Bv z(chYHo@h)Ox4iv3hr!&Ei_SIFM6_b&Q}M&5!^P*PcX3q%_LN;;+A5Wd@@@}InowO_V&gWMdwHRV~I@J{c4e~ z?v2Guxk$c{cOp(ak%^UuE4f5$%fd*mMl-yK4JDKNhs!r3NRw@%8 zQp!$_jz*KkB4dG%bvDi}(P73m367ya{lm1DBI1P>8Na$=Pr`yu}c^*xLDaIu3KW;L-`8l zIk3pKw>YIl!G(xZ%4PELvLmWXtF|bcLjC>9c5+T>$jK+Ss{TGZmvGCJgVI#I99Q;8 zvQ#eQ61HwuBM1~Ym+h|ZaHXdj@@i(q#^RkV$LwP6F#ZPQ_wNLBm*fypX z&uY851Qd@XMQ4Y}%!N&%*lg~H|xCEcNH#X%atsWdVG^U(UqXO*4K z#xcasxR@%Ug%!`hlzqgSwX0w&yV+YT&%;!q0#BfNOIf>8NT*!~rVvj(V?UH5^qMPx zNWgOmgq_Z7_i_nF2bS}2)h(1D$H~$aq$h{L38#dq9hMo=K^}_da&avL3d!QcQ@p#C zY#AT)bRsbz$k^JYL9mAtT3Mk2rEr>2{NftAOg>o8U}_$j&lHd$3%p6wuAQ#rlgb^2 zvt6GvqNAEp3D=32lEcdO*16A{Q9NtwFvZO~0e45oeWa8rOD=4M18T@ALl*@QXm#Yeja@5yd;9yl zbRFs%=<8qHw{T#ftEc2-9c0m*u9H?AcTCL5B^;E9RAf;kf%zwgyGqWMjGHOsy9O5a zFX>x!N>?P8ELILqV*1W#B-aOCSHZ5xP*>zww=04LI~coG8;hiKj_byUoCv}_R31JU z;@BhHG7;tlI7YJ!{ShQT5gO9mthGG14Yq6^=?EifRNe@R0lm@+^M!~rnskc(aPXya zIRi;h71xO%nuI#jxJ6mi&~0(jN*g3qwKZEt~}a4Zq>?- z#~r`s>#OVyER|{AGP-D1GgZETKwLDErg5W2WE72nF;&Xm(>nZ~jg^KAsZ1po8!qIWSP^L%&qm#12@#GV%Q8iTZKP1z>=se%^`mU4=+gT$ zN=`b`H@`1-oR>Iy$NN>*cD-65h1aX)I*#y$D{b49uc-rgq`@;pTh~OdBAa2*>}A{(XQiKYV>JychG#U65%PR5;Yp6b;GeRK3-FNFj~WD2?<6lxW;xd$ZR&&z?@6RG~-sDkpMKiu^UuOJ|?JM|a z&o~c!%9sVRZlzcJj_Jc+!|IP|FeU{A?(2j%i6yt#E!B&g_cxLslp!%=9K1~dK zu9v)bK=x$~9pDDA+DIU2v9QM38^6 zA$XtQBZAKfzAE@9!A}JFw;|d;Kya?$Cc%_oQIMY-DZfqdYQdd?w+r4Q_^{xUf-egG zQSi@#0c->6Jy0+zxK!{6!Q%wa65J+uwcyQyPYb>z_@Q7BZ%?$-BFJx<ZWr7kc&p&uf)5KmDfpt` z8-gDS;_H~!KS^-9;5@;lf~y6;E|?ND@V5^7H$iZU;B3J`!F7Ts2@VTZ1m6{0hFU^> zs|8OGJWX(`;Dv(Q1#c0&Tkt`_-wD1d*n%=m{e6Oq1lI~C1&0N{DR`ye{epiIWZ|Q} ziGs5P4-(ucc)H;Eg0~6YDfqPDdxCofJ5V#Jf3DzBf*HYWf;$9%F8G4rTY~%oNj(P$ z4hn7%EDLTIyhiYcg7*tPD)^+}3xcl;z9aalU>zQN+JC_T!D9qB3l@mjyJrew+b9z` z!RH#=c@a@gH1hv0kmrBbFfpcG+UE(+{ECdE32sf$`MVt zu8QKlF3QH}|LI{_Gwh3pVBMK=5|tsG*m3rbdUQOIz)PZMQCjfoIOK>EUegy_vYEW& ztH3N&6bH;4K0ehdN|)j}2;t2%8ZVbinM9=wwg20Tf09CI^>dwLy#EhJ%DeFR($|5w zQx1<2eeEm9K3=o&L#gPqZm6Lt_fs4TyGY38>$nblt=%7XdwYj=QL4u5-U-?t15*7S`nbpZ%kTRU8fx`D zSfdXmWlY~MK>K5;<1OfWpr*kmA3|TPzTMErc+fwF(T~ehpgD&5!0Q%l@E8Tp~m-!!dWvzYjqp=ZgS+6`_x3 zTK}S5Uc{Q^R5w9xJsR;hD}A!3UB;a@{XGOyy?208$CHrD*T-{pt=xxJxuN`Wn8$1zwAv7M-JLLSJ9U$I>fJ9eCc80SZVl{ilzDBpMc zw6-O?%Bjk&o&L@__uO;NJ@?$(cV_R{y7NlIFjU+OHKZmvr9L-T_gJem45_(lj>^7p z=0D#(lYPO+5#KvSskH7*8_PiS{M1saI~5y@&`ftf1GA~LRSVk6%veuDZf4R|6JT^b zPtM4kB4=7}Xy|?e1I)Db@9ax=zf3OEy#rkO%T(xDLGoFUsTDVqoC@cu7D;Oq(zI_Z z0o|2O9eokly@;B}K0)$%hVmIoRc0F=-^6DMl~ZbJCiTqEK-vF@8Kgc@vEiO@JS;3IyArc$B2dy8D&2 zQcuKw33ekoWA8&}MEBTLs%xEW);*}Ki#~+TnW{Iv7?>Hv;{kkh_;BlmAO7A6;HdKZjo$86q zSJUqW{h(pp{0J~g*#}4}`(ftErPs85BTaZuK%TJ~fK}wg4(Yr2mW)pJ#uJ`hVdeKRNqa zXj(7d2YRvnU!3i!=RgnHe~PE|S6{<(Mb_;UmGw>99085UzQxGaf<|cHrv3Hy3EKbe zx1hh#ew<^!_hUS_WZgQ(zRIyz*mLRk2h`tbuOR)m9|FD0Uc#||w;1!@W3OdAue}Ay z4R)RJ`~!E$P4;D!|Ab@9Y9@i|v-E?Ln$^t*<;Z3MU487DeF_$a($+qclXYf5WED-V z<#5+nRdY3JGVOe6lF2yDNv6knfHBncn5;7g=B-=Ifeb3u`3!p+x@W|BluTge(X+~V zlCh5Kp0&;q_O#5)(6io|%bt$O{kYM2gnkZawJV(0n6nApv(5QD)ef3hV9ZYEt5o|< zt+vbIKD2H#IomzX-%#y{`5)a#)&OhRdd6hkZZih{n|hxzuLrl&82C7iA2avD-Ve=z zf95QH-+UXwzc&ZIL+&}#L*GA{NFK{iC-`pkClah#N$^Zq?@jZtn0Xk(SuqJsisGes zh&mj_N}ANc=ocW+2O{f4ZyGb=e-`tIi;k@M#t$)#!2^)@Sc{AiteB(EwI!NX&X1|J z)S#QRV=&*#46bViZaB-{G;I#fK!2Zgxp6BE{591!YFasOvoJPkrpp{?9@;%B zL-;TTNQ85~ZQW_!g@il5LAATgCFoa9H<{nk%aV5bxDp@HS{dg!d+s)QY%X^0V4%OP zmvWoaVFVvF_hbAn=Oon*o9p4}2Io%p++(uv$DHr6=U&Z>J9k55-KUv@4p+pw-+UO+ z-07Hf`hfW~n8VJ+?D?4X^SjPgI{mmF^C{;54Lqos&pE5u^N?o#!1;CdJgk`$&N?!m z(9EAZKceYJw6(9R4EGIP>VynNJiThZJK~SWyrbrvwjMWM0q=Z}W}eiva&BXUzhl0E zj)N-0M#fqPc9@N-XFx9d$ekNesBq{#)DcZ4RMGU+SwI)oC|BL>t3%xZ6% zk_)->bmc*C5$N7Dx8H@_3~`m-sKr;|nPH{e3PKw))%68U(dw&6M=&Ah)U3*e@E&6(?8%7$(~SfRhKb zei+eVyIl4wps{;ez8|#DiV+HEaif-8U+R&RQg_;jV zP;Um+oPKnIuvQKHa*khza38BghFwh0tNSiwjUt9llqO9j4ZH1z8~UXvF~~`5me#~@ zY0PUW+!8w#c4Iyj>I<2nPs)oufHJkfuR0^y0jvtxSu~q6G`)i?F zI*1t}hqVA|S8m_A6^85kqrgiC+S*gIQVD$>J!g*j$MIu2bw7x?N)UOi1Tf8jm0RJ; za^mpdw-Ds!T2%*7^%@OND}h4peXq=C*r~Vi?TNF(+9tD!w2u|Fon{C25E?v3GdfqX zQsa^awPrC?;aIcP&YjzjHALNwL=k#*SI^K3OYK_2kC-S71Ob=I4-V8?%|J~cY)*s| z;=GW*m8v=3hB8w#(W7 z24T6%H7rOCc9D8|t)TwvD0SuTymreDclXvUdv{;A{rau$p2;*twSk?i+%Xr)4w^E5 zop2pl*+Wsgp`Nl%P~m{rDg>3V&>Cx&Yn?`6tl97j<4A{B9}dS`wV+z?OZD1#=;tSz zt^MIR_Lx2as^cM}y0zt3@*@|G6n6V{Ul(MfsP_q@cEhNkL=eIMglLw*}OyH%d>T3nG* zv%}r!9`LvYsD|~cHO4zF-^KDFx8u!_(MBnYvZxmaTjD*}?9FW%9nI-eF1K=IbnVFM zl`C^Yt!TE(b2o0G3l9aWWAgku(<-h&NnvZxHXpRl9%yLFGXRSERztJ*wC z-SJKv+4aiI>fW6=jg(vU+wkKvRbcAPBKA)rm8E7G8SVs~5NpNb6#IfJ#B5IJ+SA97 z8#KH+78oQfJU`f4Hr$rx!o) zOg6r+H}z#cV&X@Fq@3^dSiWfljK}vZua9`EZHWr#>Jin|(|z?6V@7(WG0SjL1IC~+ z$KcOFztH%?k6T*(%bA!a;!T)j!AG}^SeW9gH_=jf=kmHc+0ONt!X4(^{`giBjYyq$ zYr!vblcqqWq92yd%2KNLEKMS%rk%%6Kaa{uM!mLd52E4-Js8GPK8TmX(~da4-->nU6_~(qbD*-BCe^* z#FQ5h@s(gm!J~r51z!|ACHRWqYl3eIz9ra=MAP0(!JOa< z!Ak_+Cs-C77ragIu;6jQ7X?oV@(VisOvSb!&K4XNTqk&?;BLVW2;L(2gy2!Z7X|sP zn|5Cjd`<98!M6lQP*BvnOmK(b4T8R4OYjcC`vo5tJSzA_!9NlFhTsnbe=5jt*7VCC zg@}EEa|M?Rt`XcSc%9&B!FL3wU_;Q(Y{5l>8w9Tse4k)h@IJxE1V1f!T=1)cUl;to z;2VNJ7gYF3gZ_I3=LjwnTqU?k@EXAz1;+$Cf+qyOCdfmB_Im`E3$_Gr7ra;SlY&PD zzaV%*@MXd82>wX$bs~KJtDuQPn0_-viOVu(hV z)QI#c`r!FU`}k(8{R1=~k3%?GuFpHf_m1@UaNmOGX>7uX9uGVG{e=98j8ntmp+?&) z0&!2#I2Kd5NVV0l{)RSO4DqVRootxG;pkMJWlqI;}<3MTHwbP5uh3_H5(0lV@(>Ww7dqCaA6$w+U-`Y*lEM;|GDvB zc1W9khj7p;J`xQ_lWq&}q#lk6-OkrzAKNl~xIVv1k85$hU#@@LV!vEFl!V$S9f$E! zqkXO|>wzEg8}Uin<1e6;$1S$E9)hI32NU+_Keo3EbUY{8*o@C!4wM%6?F65+_ZaLQ zgAv9@|FONBK*wW1sz)&>8wZu><2yB}_bfKa0uGQC_uT?M>31Xkw~>R4ez~t=zx)qP zJO-pXiOwMs(&9ecR?o4w5B6w_AKsQ?dk=z+$ADC)VUId-i~H_}AQ|7mM10)uvAw53 z$75(C(-Xb-NwdX$Pk~O_dkprnkkL2qJF&gbgXS347u!Mv-(*c;;j-A=+DeiuI5Vqe5Wd8l`w ow+}+zT2yP$tz3pmHb>`*%m?Cl`Lb+#>Vn9HWpx;M}gE_@8j-jqkV{d zSaL!VLUCgtr3TUh11+II1GG#^i^&UUO3btn@}Mn~l2TGiC@@1Br_3Zx!r*@2x&O7+ zZf4q0n$~FOR|{2-YPl$SynQ01 z)VapXb9c8N4E07QLL;|si|qbZ_pMv4S5N)o!&5EGLkEr6*w*MX9S1*n`SoE5Pq4xS`I)TeiCG8U<=9p2p+1CY;tMk85z)4IP|B_0-LX<o}>H%(h=LXKyM`7V&9EU)+W+X`;(+EB;9G>#SAu+?zUH<5Y`y!#rEG*zJ+v5 zwZ9CA7}iDm7_A){s8D> zhIQb6pkK0UNh`ju#*C*&6-^n2veF@DQ=; zZ-B9%X0JmemEA&mT6=~Eu9127!gRtq-j3=;-6>@~r7fdwMOk0bhEaD~Szjd?u@^9# zuZ@6iu|x1^eVue$)Ja>{_E*{W`2y+_vuo`8xA%hX zvqw2^Fa9;?e)~OE@7u59JrH&4DP?_^K8HXfv+pspQP4>3`}Dujev1D8;YY9^vrn+^ zKmHW&ZBe&?zCU2!?e+-c{*dimkDqSg#K?~o~(o1j_aJjz_Bv}V*f zNlnGP1e%QwSEf}rxgW=zXBp>^Hrwu4+#Azcv&-Sqv1ZK6(P!Lwmu8>TW_z98WUe$ggjz;FnrDIew(9s+~jWjSF`&i za$h#DgYG>O#pCkR1wMvO4F%S$6nGiJw^7gqYt+gnpVynj(DZPFkxqum04wQ zaw7=Cp|*zUvu8f^ZPsSvvvhC{7sQyRm9rLVYl~(q=PEK=jSaAFQ4zxJ=pY#`{JwRA zc}FuG9HH5bW(IoYY$fwMdTzqbcBXTawu(6aLd_AAXJ?=DD2MaAdOmkKPchNYnOCC! zUgv$99W}=h=_=<7>Ys4_i<(KF*-OulqdY9HN6`n)!3*YHDuR%#+S})ZC$&ryY*kx>GYJoK7bC1?}x6 z73oGNhSUY=@p(qoe6!C#7x0c+c+$GZ{CDuq?ac5#O)KY1%(hGYE#{`S{=npfEPjzL{@7$JKk8`EqgySRgs?SC$x?1Vz49Q~2D&xO zJ-C!RB3Px9T6_)O5w4Wag3zH&wQMIN#zQ<(mT|#biO~6=BYz0`A=t%K+dY8Zjqusr zNlEX6s8_RgeNGn=H3piYV;jR`+_wsMn&n3zG6wXXg0S~_6u^kHw7pT136gyuk{srS zZ-PsuRw(vbO~DqhEBo-GH?@jOg-`Q5WwaYB+B)n|+oHBBoOUDX;I`1GZ2LlpaH9|s zd4?CLP}>Ik0(*A{0tnMY#&QhXrp5r%+}dCkF^t_El+Ni@yE_v2=+5nEu(fAxN1fqvUoq7%M$9Y&~aHb4}eB7Pq1)ULHnLHPL%E>ZH1F14x$M@pBms>jcyt4TXu zaJpL)^K+yd#zUvw4J^F$oX$WSFO)H8W|0hDGmB^YDYc{nmDq^rOBtO}maXw?gD9JO zsEPGr5_(07G5gYU;>PA4zt+sU-I#BUb>FpByI9_Iy1XW)s&BTh*^L=*V4+=kGnQ_< zF^tfw;)>2oZN6WGW$VOasJ(;*n!JnvN6J!FHRpqc_mdvOGe^B|>|GwB2%K*0wHyx| z!~tVIiMMXN-D5qXVfjlN3y9yqzXh48zQVWh>$X;fpAJ~JdIiVhiR$5M%_}CVm2{%y zO&9Vhm8e%MiF_$tsAoKp(aM*@AdyR_6Uj<(uv9L2gI+R~PppfN#D{}EO1afkWip;- zh(b9%8J}RjZtd`tSM}*?EtB!Gps|}8#1+pg)qD%DQYn>v5_>`qH#A`Mgbv46@fixu ziHANBTbT&8T(sx>CFhtC49m?_%kD(7lqq;fA^!=yE8y0QD%UG|m7G^fA69NASxYK+ zI$f!iiz&BSOV(gFovv!WDuP0}l#A(Cy;RNTN?s<$UnsapWqrpk29_*%E@Z_Nx=yEO zT{Sv(Yel!}rBR2#A^nKU^hC0vaIvdrm77Xdkq6Bu%DB?GZWY3E$@OOPH8)wwRh64A zmnZWys^$uHqArr}nqJfON(BXUQ!Kih%w#HF72UFhBzxzpZh8hINA2?^bl$mpd%eaP^Rr)pRXi^nAuo2?-&*nnvmz3nNE02@cvTp`h5$%AJr^;uk^ zl4(z$1G%Xx^S`d*We0~wh7$X|f~Qw=F{QT`$LCi4^~PmZ(rZDK{vL&Frlx+=ag+!S z6BjEBsd8Zc-hb1k`ht?g44HnZ= z^-XCkP;X|iI0U{nQ7@)qgSpt?rPbIVcF(3Zzzgea3+u7?e>0@?%nU-fw{Wbp%~JD(p``(RV+$$%8klXNv!dZ|aI;EK zp|iY)6z<3kEu^9i9PRlda<+xes66$!nl-c#u3;;{vr1!l=3{*40fR>GBLM>>zxga4 z+rz)t^wm^f=Je+_IB?@5>(}6epx0aQZT3Gwa+)`Mj#Lc3=i*ApdgJnIBRaU<1#MTC5S7oGBE+YL?qiU@`T`8!A*kO1@{Q<7ra_9Cs-1!3VvGfX2CBA zJ|g&6f8X-YXv6-X9SN3z9jgn zU=(Ko<17|jFL9|4{}^N5JsLxlZO zBK-7=d_WM}S<5l48u61}BfkZ-=dWBM|4K_-Dfkh=ErL4)#|8HaqTI@aQ=Y%<&qfU5 zoe-WskxhI8_$yl5#jA&lwPZ@gd4xl0_KdCK*rGYL$GdUW42Jds_rk9DS$1&a>Zl-v^E--Foq+9gYp%&bFhDZ519Y zm;cpn2sUTO9fK@roKLm^JXl(43=i80eBfe0dEn$iol>G<9FZ8g>Jt23;L= zW8CYpQ4T`JxV#Ys<2?$x(cdZfi$NB&Kz9=ajs9MPKkgm+_;kQ6h-s3gRJT4f2$Q7}VH5);L)R`FhPS-~3xuYNNuF4*o$ zuY5b4d{Im*YAaqHt2RvHtiZrzL?jR zr|O8A;!N_SYEW{fU~B%(^pJTa z5CSiOmrG;#4U8wdT(QrSU8&erWZM*b4}!?6$>zO^AC`QCI|VEV9HjAah6`-Pk36i{ zi_nIAQn4Q*J^7SkUnl#tVyDpeS+ZjSjPMmWae~T&^B@;Ssaz&EK;zrjTgdsA%Oy>| zeSJlO)^=ruK@`6Lxquua(xi;Ni84vRc$v7fHPG2?LDb=b&S`>m(pFk!ah70cA+ezN0}LOw(WZF1(v zT}Q9o)-Y={D1Nl^?$OG7Oy#|*ay4g$RE#1IHlQyxoQ?}2)^Kue15?YXl56We06YR& zR5NjsTWck2?Skq}sA@S;a!uW%fKTaD&tV{4fg%qk;anGostSFn%YgYF7*WqjB60ZT zLC!?ka;WOA!A}o88eYZ^i`>EfDUx?Lbi>XfZ*2GuZYie1qAs`s@baHTO|1$gtZix{?Qv?EwC z5DMI0VTlArx`^ovA+nqPemDIZ=Ho*uwTeMQbbRd z&O}q0!DOh5PT2N7{#tva9N#p_XCZ)5?U!=GB7z613`Ctb3(B+xpA4m8zvx z)?OL1{<*DVm9-Ph$!#rG(Mqc>w7@DvDGmAR&{iZ8PsB6vXkYwRC(;{D#cqkF9CSDq z%|u0aYM@_4BHeI_L{q8gmWY#xiIme5A4o(x0SVDHFo^d_G}SW%$If)x9jZtKk|(f= zmZgC!T#_k=UY_8QNNOr&vznSOX__}{mOUfo^f}SAbD@3x;o+)$pD>#_s%$ zPAZp1SN39nChg9Ss?M2lmkyG`!g0IjYO~jen`L+?nhGbn)8SO_KrBAkAMPFKcf!eN zx+~fjN+(koqOjA|7f+_0;4K5Gjp<~x%LzwQ{lT7OI)ahhlybU*O|zTAYu$Nwb76yO ziK(Pw1B0D?j>uYiYC-FvbW;(_mMpo-8&7Gkt=<@bJW&^yR^O4gJup&t zaTAnLC)$Yz=`^r`CGMJUYZ7_I`E6rlg@2r^k`t_IStD!ZL_d6TNu8Kl=@(y|_1bZC zdPUqs>SP_!S!C3t8e`d~;koyido}VJ^c?}O%mb~qAf%Vak3DLh*R*n zLBt}miBnO4h0|TRaE8ENz#!vmbtUm4A#NmIEClzaZ>A7?i9sQ_9(^JFjf@x;;vlg} zh)0QN|1i>0M zQlWaELSCrlD>U-YIrLkr@j8t?8u@Cb{rej4(70RUgBl;xsPczD_Yv!z*7%{uPc?p} zk(-ZxMH%Y}#VF9qc2947+E+jH9jW=q%S>x>*cWZo5<57(#HNK(o9gUw6145i7qQ3>W zx`@>prx5dnn5*S0HC{~|gRdklZ`3$Q#NxSE%l8wJ_kN9!Xnb7b5slAjJg)JC#$RcC zO(UjLjgMbrkwy%e(qoDg^2?Irh^?dghb^LTj>bzguF%+~@g|Kijr{u%$7j37of`LO zd_?2p8jomvPUA}&f3EROBF6K#8c%C{PorA5u>V!dYW+g~M$0~~6UccQ`Bx^+LybnY zo*_4C`C^S~eM7I-H?URf)jEgVrsZ`SJ2di7Q=HF@8dDmFG~T9B?Fabn(lVZKs-8Me z@X5|Qi{pr;pz^ngXjh#dsE4CU%@;tSnco5}!$s*;eax#mH-Wa+H)=F-)I7tk<{7BY zUEm_^cZJ4wjq5aaXuLsVFA;h7X-pC^{uzy%iRi~xjdu`{>|GkwdO^E;CkaYP)ps=x48{e!H=3-wh0AglhNzUl{L)epq!)Ad!ph$lknE&Z8j zCoq$8vDa|;9>iyqy3#|u#zRzuvMxv0c&=W#<4e?3$+`bSIi}HXa-mGo?u?U)4B-=U zAcc169dkMdd+>(n9zaTpk9KzATh?ps8|d7f- z-~496C%0WJfe|w8a?N}F7C}CrUnIwGHDuN`HuOeQpD}H@WZW$NXw*uQCy!mzLB_#MHZJ#35~+pocU z+ik=p_X7ObF1NO6_gzmNuwp3&Z4ntwCiL5oz41=t9oGaMH)zj9RMzkwK&?UtjkO;7j49!%D969hKHat^(IHz276 I#^~|;HzT(!8vp`EbNk{^zunTMmgcKWC*dIkwp_3>7p(4XSBQsk@eHjkQw4pz2i#Wh{&AG0tw= zGqL5F%@lV&e&p~+M|M-1SiiCJ>Dj#Qil3%drJ|aN8U+yTkC;lG8wu1tnpFsmB`1Tk zv?>y{ij}%D2b&;YdhStqG-^ege}!DF7V9xeTcWq1t7SC(oSe}z2i+~x8q(0bkh-YV z!4A>pKk0tW7s0aWFf?X612!E389DK4lEJfLavb-rOg+@AnF?1LAOLB-+dQ2 z=R9`$-p@%Mg4@XVDOIf{{QNhbHX27%drRcN5~yQ?^!6P(RVC!c5Jc&mqk3cVi?zdL0z))ikA%eBWAHb#b zzLs<}_FKwNA>9%?35#W&O1eGvAUav6k?xFLLHcyk^J3p(2J1-Mu~l58^`wuD{Rib6 zNGH_Xe+RS})>$4SUx_TNvq`EL9%YS@zN&i*dz{OhmC@Z#qa9?ThH7QKd=W-^AWPNU zmtcCkVO{cf^rxrnQj#k6CNpptH5$8~F48YR-V$R1R)zz=0h2>ltq1YLM|{Sk{{m)S z=LUFau^JIT>{a&KM^eSwNl$9e@W8U@d+uzsy)I`$S%0f7yPTS`eyk0umJikYnjjnrPI|5IZuSL+o6 zz1GKmgI?CFU7$C0IVJQx$i8R9bkY8n_G7W#%;BHE1$uid#lElYK=kusY3B3B@zCy$ zJ&h>VTihQP#|o7HEBofud;-lE=pPPh!Ae*ypd7P#F;pE?EnI}3!Kk&z-$NIS8}eJ*;8tfXTYuYV@2y4-c5E%rT?qIqJS=UJt`VX3r6h z;)muCBED|+yhZLu=9i)SgNeyw`RNJ%8*~ayux4d~Hz0fm1@Y)z_?`b__+Z(D%qa@i z<5}9UE6Zux2EG3c0(~a3SoF>@eZDu~alEeJn3oznxsQ1W9onsBMh1FY@6_d*R(2;x ze4N2BQF|+AX29U$wjd0L8jsTFF>|4hTkDJibkN6wSg&biC*j)KpqVCnJDH8f<*;s7 zt%OI>K{8zQvUQdDSTh{lMzd>79_GqkOXiDuZKC!%rgN>fYO(*5nlG8$cm4K59L{xm zJ-6D=GtukK+t7cz-G&g>4Q2(f+x|5*H=3;eal4b6ztYTveJ_lyn=~_JKS|d&o6jMe zt85-f)-C3%U~aH4q2^W{=YIP#2E9%9dBDDo4sO@X!}cC(?$FF*_9@idshOYJXOa1` zW}dVAna*9>+b>lscQQlj3F+~9M%8??&%YJ$3)Q0ct*@Cas4)9}W_XXLmHpSu@Ltn~ zVoJ60Od+X#ELN?YRF<~z$G&ghv?#)CS&F=8t67oc080R24d zdR50$fWA%e*))%mzDF^dCSCMRZ^5ehXAdKpzIQSFmakt;ayfolzQJ;B-UNUu(a#NvmE)Wk6@;jorIs( z#WNk;P6xWj`BZGgGu`93FCblG4P+AT5UdBTL*m97lE(IduW9BDGCKy_$gF=4%<;<* z*4WIv{Yx5Vnf~L^w;_s0IZRzS%uG+MQYSP+$fv188C}Nmcz0VQz9_zHVVBXl5I3-u zDiUAYc1qi}?sYw;jr&i(YHK^aErM}JJ3u0oNaFCZ;HWj63S({S#%wM$+S=&H05c~R zGHW%AZQYc%^{Q>%DL8EJ4%x=0ZC67VXG}WmI1bjBp>87*pZ44Z>lQyiGg-5$tOw5*U7zmyAgjjev=4b}mc#$NpnPX+tnpr&E zPpKu{n1WLgeJP_eNr9)C%gb(b->X}x{-M(v{CIy!n2 zYq$KyYYf$8jKKME;a)TP44{uJFqe05Iv(n2nxXE5q+({3xZi;ViiRmrhT?Ip%QdS0 zWNg2WilF%hJHiG#KEdEqJe&wOC~!3FcWK;(Y_rjqeq0{dQO|dosXhQ@8Xv}E3SU`} zU!OO2c>GFtg^7^Di>Y${zV4^^racgRg= zim6q}70HpH&nG!h%7Ke)x>WL#S%xlEvwM@{9H&#?KjC^l?bUNRHxC*oSp)h{pzCBda84u`^^s2WZR!ojU_HWmwd;tJ_8z_ynZks}JTI%c`Jv$z!>OHa z$<m8cm>XI(l))*K z9Z%HUeMPTWtt3WI9$7QI>XO7zIXlrfEsN@Or-sVI;Opa!awaiUNDO_(OAKMpoK~nb z5Nar2c0Dg$aECA-h5GnuFvh{db7+Xkfy*~4sNQO22&W1W{qsEF!aR!yD^Nj66)-i} zYko~~TVZ4GbxLV&`+P;8*~&@hI9a>Ka7HPo;MU>K<&=OaRWsN&;VHw?6zj!w3Foey zON~my!+P)x#sSM!;1o{kO7l;uN*V8$Dwef$^2)To?=UKdV?lJiN0FhfN#B{0DyE~N zmt(fN7^e4awp8VTS>vf+&V&!*iIY5qt%-d&<3*vDl{u*`n>MXY433<%cGVD9b?CCu zp_7mQe=jpW4V5~AW+?NDczaCqe4DZHtv^pw{tx*L@s?}NTa8bZZy1JAns0Gs90$_c zXyh`J6e%+~_=GzOgW38$HG`#**nfi64W%yiNoysy^Vy{?Qhhp~bsc?lyrz zgzx%Li{OQ>|E6|S7S-e8xcxRWgNSOHWzP?h=@!A)_)LHD{URn2)q3<+<%{sg;ZTdH zHihe?ZvM5YZI(SQ$f1Tmu+GxAtHq*cWMjsPaX#=B5o(cHy(6kCq@{h3jW3R<`Lp!6 z2Zvfj;R+pU5w$49(I5Z9G~FV|b^t8L%KGWUdaRkjH>q{tgGQSzc&6=J)R-u_QoWep z4M5U-y3`+!;DngI4EEPme@?$*lPgz@jOa~8Y7{$b_8}nGD>+F0n@D*3!9VN7#FX)h z*P56{u*&2I8xd2c?J#uCt_kEU5;B93b6=t7OpB4T>!L;DG zU{!FR;1>k16}(CCPQkkczb*Jf!6yWt6+9^ThF}vGfO*apTq<~i;Aw(e1a}HvD%cRb zTJRRZrvzURd`0kgg8Wk<;~o}_VB*Pl2rd#F5L_v^LGT>G3k36m*9zVtc(3611s@mu zo!~oy`kyF>--=^}dGHVV#7%-12^IuB!7BxC61-dR1;JMY-w`}47(r3%@e1-UMdSwr zFA>};I3@Tc!8---6MR_kCxXulz9RU#;Jbo<7Hr1XCgaW%>=opn7%4wRaI4_?f;qvO z;8lWs*eL9m6g)+6tKcrds^ArZHwu1L@M*yp1rG|oCHR5hM}lqmvl`>tg3AR*1=k6V z30@$W7xVw*soz9;yh;3y7f#ywr|BEbg)9})be;6cGR1m6|>FTrm7!HNEs z2o4hQYS}Tfdg1R7{oO>Y(RYP^RPY(WUkDx~;&3}6d<3!S zpN)B-Y&7!iMZQC@S8%!DiGsW)&~76U`E3?FM{tKAmQk6wgz&wJRv2#`9DXm+vHn$&bH+rgi?yXqwlrBlbtH(BBTUgkO;U>rLA;RFbzx z|3&A^+)Sf@Hy*w-k~vMMGa20S{cL;*Z?_@iG%mvhSMv2OJ}xO0@l_`tF<_OD1Nvs6!~WPWXo0^Q zAPA3lPbfd`+aSODK?lA;suG@7?mcON?jG=Af8+4Szp8RQcpDDw?=mS!<;sb)U7PLV3j}V0Y{R8|Z zAfrFt(gT05gAV$DRBPccK|)%fI|M%L?``;FT>9hvH1PLF&_N%N>O%Ni6%qvGd(egb z*>J?Erayiq1pYn(%|5{x@4zCgVMDp7M2FSQ< zysL)u8%AQmczLD-`7MJTYIH((!p{`^jRXvkG1-Wr@=y=MZaoA`A?KLsuM-br1~m^- a{Q;A40SRe=Kh{LpZV#OBujxSx$o~OcHc06J literal 0 HcmV?d00001 diff --git a/Release/system/src/newlib/assert.d b/Release/system/src/newlib/assert.d new file mode 100644 index 0000000..ae4c8be --- /dev/null +++ b/Release/system/src/newlib/assert.d @@ -0,0 +1,4 @@ +system/src/newlib/assert.o: ../system/src/newlib/assert.c \ + ../system/include/diag/Trace.h + +../system/include/diag/Trace.h: diff --git a/Release/system/src/newlib/assert.o b/Release/system/src/newlib/assert.o new file mode 100644 index 0000000000000000000000000000000000000000..708c2b931be1aba55335443a9b8373959b8580af GIT binary patch literal 8156 zcmbtZ4Uingb?%wnxm#)OPAi?HxswE1!JY1uXm{@3ELP#JN;L+^v?A}`Y zbK2R}of3=*0bBgo!3JzlDIpcGg2@j72M0SU;Y4D%%XBk%}&G~{W&Om8LfSWK9s$J^b?POjH~z= zL>K!54v8P5ohKV0d*Z$EUPfqi9fWcp>G)9#p)4$*d(JK32dwNAz}`&pI7yXsk11=F zo`~IpaUq?seRPI&kA0fzS|^!wrx zT@g;Z{K1vhbX~+{c1F&+O_$efZrV>x!gOAwkjsFRl z{yCdqAz`&%1Y@7$s1qcW-9vgxTZRP|#+=`W>V)-77qXXhCzbVit(kNi%K9^{m~^L< z^(@JR9b+_KxCV5O{W9q{&hdK7;A$UJzZ(=;JavvVC zpJeub#2s>zy`AzOb8JD)Cs2KX{@|n*bn}C9WHXDdK6WjfkB`x~b=2f!oqgb}oT;^( zc?_Uru0>78opWs_;WXP!kMja!DC;pvXA#U>A2bINs8r`Q_EdGxnDdWhYGxWeYn(r3 ztdqKDz4OoPX_!}{XQPv1Ps`+f+~Pb;KPR->4rc-P#+2^a?YvC2X>$k0?03FOwO`k2 z2b>jTZZSFAL(XEFe#HFGZX|1fHEcatOUV5azaTY&ayX7n}hSv-)C($j?=(m*1{G|E9VMyTU#~L<=jYSn{hp~dsKq( z8yFxFE_%Vb&Ac56cTQ35c5@j0%GpWgH}$f_oqn#w9a<~l{Fps=nmjg#oI4okNAyze zcAjORA2p9*`~inyTBpp7@N~ra3VZG{S@;u9H$>LmnwfO&gvh!_Gt$Y99RtLD2y{^^K!)S?U4!{&?NoqHMK8BHsPC1d@z`4e zlsivX9t5jF_r|&XF6Cy3s`N%J-iyx!E9E!{ZOBwh*U@7p#?xeJiypJFUjdzZ3?X+F zxDQhqklo2gv<)q2Q1F%}?`u(Z*IGs7&#=g2V3heiiFSXddH zi9jnak~wH*u}oewOWNa;5^ z)EJy=%2+w$D$9Q5=JtLZfbp@ z2T0g3L1m}|1eQ-+y=ENXWpt*63fFcjT>CBxynW4BIQT9K*L5mfH>0ow!%(bfC~avB zq_cJMe2tsxEp(g4n|-|s-zy-&6qJ$4WP_7I)30WOMm}5frz+)~%C>?=wp`0sS_NNZ z)C%QL$d>Z?tkiJ`t z3C_)Jo}Bc9kPe!Kf?ouU4cYMhT60E>SU@8Qty&pcp4fGXNeX@y>%+pk(%xd8(o%FGG=s{+}U<>tD z4go?`u3^eGe;PxzY877GFgg{qaxw_ZSSVw4%CL)dKnU#()!w?N<9)hn>*Dbbc`F4`SBEvzT+zA&;RjW((^m6H`6g=z;H_!>w z>CK+-8rfPg$TlYGg>tK!ov2s+>?D%uRWbq7Qp)=IN_jHy(^K`vv0xJE(g#RsGGL&` z8-6i8wt6gk(69Kqva310)tG5F2+L7K;V#t)<7VopJDe*hWn{BhZ&W>u3^yGtR4#<0*YUrdExOuOC~xYE^2q5l(bP>c*`Hugdz> zoR2fEkY1P0;S9=8q#FK-a!{_#>U!Is+;FbI|a#LzfY=Sb5A)ZQUMhK2EHeo%DvxbQAMILmWJnIK* zP(#g?l$V2J7OUR8RqW2NWVsP>6dZFa9xBZ(*7UKB@+~lZhxg+cQ*Oy`!nn^QfvMDU z*lnFjY}Hx;)`N$ys+4O;v|b9<+LW#}eSW#Ms#n2^Vp-R&@xmR7S%u~6)^s(7mf#sf z%Rzx5=^AM7>3pTmgR_BC9<#w8YpC-)o_r6gfa9xlt=_kN`-ar$_)OP)-f<1-?7SA4$|5lmcUhGs;j5_ zs#(Uo_WLa~&>tzepv8c!G{IU3Vu%TOM-tb_>$mH1z#65a3!YwKEcI; zD+JdG?iA!#5$azMd`oZ^HU#Ah1^I=V{3gM@f;R{j1n&`iNboa)PYeEq;CaD+5d4YY zYk~?tZO~t@;3B~h!8L+g1+NyoQE)=AC3sHo>w-MKXun5rg8Xk9~3+*_>|x| z!LJE^Tk!jWKO`cj{~`QaL>!d{9{RV5c#^^|5`L-hD}>JwVQ0O_cMBdCe7_*Jzt%%J zXvC4Fk*6)kFB2RVZH@?4+o|!jo_&>n*a2#>EaSf@5BS*J)>amY)1P{vXf7RpKztb<* zF=~-t)(Xl@ZIO=q@N%U6g?PBWe8}&{6U6{h@fX#j94Ia7+X24Q-b1kWS1>|*^dH$f z1Uec6Qk}*i{>UG-h%7=7(d>H&#eYYn)X|p%-Rbuz{Xw>{9K(_=Ak@1KDM!twq&9ZwV^u{2>PlftkN58aB fpV1xysVb39RA^^!S literal 0 HcmV?d00001 diff --git a/Release/system/src/newlib/subdir.mk b/Release/system/src/newlib/subdir.mk new file mode 100644 index 0000000..0e39ff0 --- /dev/null +++ b/Release/system/src/newlib/subdir.mk @@ -0,0 +1,50 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../system/src/newlib/_exit.c \ +../system/src/newlib/_sbrk.c \ +../system/src/newlib/_startup.c \ +../system/src/newlib/_syscalls.c \ +../system/src/newlib/assert.c + +CPP_SRCS += \ +../system/src/newlib/_cxx.cpp + +OBJS += \ +./system/src/newlib/_cxx.o \ +./system/src/newlib/_exit.o \ +./system/src/newlib/_sbrk.o \ +./system/src/newlib/_startup.o \ +./system/src/newlib/_syscalls.o \ +./system/src/newlib/assert.o + +C_DEPS += \ +./system/src/newlib/_exit.d \ +./system/src/newlib/_sbrk.d \ +./system/src/newlib/_startup.d \ +./system/src/newlib/_syscalls.d \ +./system/src/newlib/assert.d + +CPP_DEPS += \ +./system/src/newlib/_cxx.d + + +# Each subdirectory must supply rules for building sources it contributes +system/src/newlib/%.o: ../system/src/newlib/%.cpp system/src/newlib/subdir.mk + @echo 'Building file: $<' + @echo 'Invoking: GNU ARM Cross C++ Compiler' + arm-none-eabi-g++ -mcpu=cortex-m0 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -Wall -Wextra -g -DNDEBUG -DSTM32F030 -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=10000000 -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f0-stdperiph" -std=gnu++11 -fabi-version=0 -fno-exceptions -fno-rtti -fno-use-cxa-atexit -fno-threadsafe-statics -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + +system/src/newlib/%.o: ../system/src/newlib/%.c system/src/newlib/subdir.mk + @echo 'Building file: $<' + @echo 'Invoking: GNU ARM Cross C Compiler' + arm-none-eabi-gcc -mcpu=cortex-m0 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -Wall -Wextra -g -DNDEBUG -DSTM32F030 -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=10000000 -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f0-stdperiph" -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/Release/system/src/stm32f0-stdperiph/stm32f0xx_gpio.d b/Release/system/src/stm32f0-stdperiph/stm32f0xx_gpio.d new file mode 100644 index 0000000..a39dbc3 --- /dev/null +++ b/Release/system/src/stm32f0-stdperiph/stm32f0xx_gpio.d @@ -0,0 +1,90 @@ +system/src/stm32f0-stdperiph/stm32f0xx_gpio.o: \ + ../system/src/stm32f0-stdperiph/stm32f0xx_gpio.c \ + ../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h \ + ../system/include/cmsis/stm32f0xx.h ../system/include/cmsis/core_cm0.h \ + ../system/include/cmsis/core_cmInstr.h \ + ../system/include/cmsis/cmsis_gcc.h \ + ../system/include/cmsis/core_cmFunc.h \ + ../system/include/cmsis/system_stm32f0xx.h ../include/stm32f0xx_conf.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_adc.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_can.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_cec.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_crc.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_crs.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_comp.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_dac.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_dma.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_exti.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_flash.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_spi.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_tim.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_usart.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h \ + ../system/include/stm32f0-stdperiph/stm32f0xx_misc.h + +../system/include/stm32f0-stdperiph/stm32f0xx_gpio.h: + +../system/include/cmsis/stm32f0xx.h: + +../system/include/cmsis/core_cm0.h: + +../system/include/cmsis/core_cmInstr.h: + +../system/include/cmsis/cmsis_gcc.h: + +../system/include/cmsis/core_cmFunc.h: + +../system/include/cmsis/system_stm32f0xx.h: + +../include/stm32f0xx_conf.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_adc.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_can.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_cec.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_crc.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_crs.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_comp.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_dac.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_dma.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_exti.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_flash.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_i2c.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_pwr.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_rcc.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_rtc.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_spi.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_tim.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_usart.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h: + +../system/include/stm32f0-stdperiph/stm32f0xx_misc.h: diff --git a/Release/system/src/stm32f0-stdperiph/stm32f0xx_gpio.o b/Release/system/src/stm32f0-stdperiph/stm32f0xx_gpio.o new file mode 100644 index 0000000000000000000000000000000000000000..0a06b22488f6a0d5e6b0cf4c99054e6fd14155fc GIT binary patch literal 11796 zcmc&)3vgW3c|LdV%92;ItcNYj59F0B8xbt+N_LDf*j_#Sie+mp**pqFUhS@=1!=Y3 zU12-WSO~{B3=J44c8wDkl0qRaaY>+^1c(VVfx={5a@6|ECQ9I^2bNaJ0V}2#IvZpUtf1s^M%Z@p+W1ja|mh z`R0jIhd<`<$IO>cOa}iY%fG`vW*$4CylSl~!c~H+4A(TZ_Vg2GUGd<(tBrfqJmbQ{ zA>-h((EhfCuf|qir;dbtJKt`ap&`p)S+f9D!cf_ zS5H5!ly|*RXKq#V+P0b7Zr%3Ww$z$qtIwQKYHZ&4(Q7=$J;wdT?Yuu1c{alPa|z=f zUY?_=HR|@FP;1TJ)?<&eK8E|4i!-J2ju8I<`qF!wZdYPF&cxG)nYIL%RTygg)l3V#NU*+%x_FOhvc+1|o0kyBK7 zF`&R(kVt09ycX1?Q7AlwtME?T4CTEKP-G%f!DY0aTxc+$dD3_l;QJv=l&=m+8LD`p z`LCXRsFsv5mv=mLrAkuZm?u47MBQ6b2}kC?d6?X!l4cVBuGNZ4enYi)HBmBUT}QVv z-_tf_B^OZbciN_6N*5*np(WEwE~MmrEvYIgX3!6`gX)qPy?v;OIa69!!{#FoTjih9 z)(zrg?VzD#1=UVz2cJ`=kSp`|9yV;M)lBco=b+*H5I5y}9e2Z5guBPL7I#ybmxAx@ z_&NyNAp8yp-$LY~e7kTn&_XKp{M4n?TM4-@i|m!}Hrx&0LAFGh8vx$uM=sTo6;ypp zck_?6YA@~{Wj;aGObw)V=v`5&9*0xqy8t(YZl}`tI`GSiymx#TSUwFB@7Fk#s{B%l z_pyoI@{4%Cmx&dW|A9LD*^)`+wFvD!$Sew#xt_$KB#4URur)q|ic)pBj6?Gwt4vy4 z)>$g=Km}SH?^@C`ExHx;HeA!T;$|oh(}|K!z@cGi`Wv9tbT21V#V0g-5jBLzWgPk< z7*#shiw1)k;i|Ny!%)U1RdFxzs5U9lCWjr9qqYhA0y>sS)t^}ud(r4t6aj;(;sEX+{8F!f!AX_WV@f?$J+hoRk22E-bHH9?+tqa1;>dK@x!#bwajJMgh zn~hcyC|0X(a#S~K)n7tVsoS+#JH=9`rY&QWuF#f#W;f%0_Ejh^>O+pJkaop6u4Yux zc0pd$4;X+aJ>i6T zM8asRN3_+Z*;AVr3z|VWre8JtQASnmaMcTTSf8(TN1J* zJ46z*C9NW-HR(!^GRlqlrIp2I>Fm-iGs=y!8R+kNRb0FREG$Y@ z$}C-0d|C0jN<4d?SA+r)7r}vHtgAG@E3AbmP>j7|v171u=H)Z7V|a}f#l^6PmjbH# z8lW);s>PK?ak0%UnPS-$tgBoK*%XjPlv!k{qyZ8Op37q~J(h_hO_YlxM5LpNCS&DH z-GqV*XOm&yhSOqQF)1?ABrC zLSYlZR>*A~Jum|zmKfzzDYZ?_3e^XjavJH1^#7d-8^V-{df`(&s5!+Jb3{9E8R|+x z7FU64=BThrLz27dbDHTk=A0>1`(l%}t67Ih_;F!`2=wU4Z1HnQSZ-PbX4?DlnQ!2Zj=Tfq`f= z5J?X=CP$L-#(1PJ5xAsjQB!juk&F(F#^P$ik#GXh;Y=cP4*uCel(2T}=p9HUMw+4+ zI`Cq6lW9cUra_LDqXQCqvqM@YgB(h$CB2R)Uo)+J=@BW=<8Pi;M%A496<3?HFK;$u z{uNhu+J75YTVZ3Ik$H4ieOzZ81P`jb|O6FF=m>R{pNO~qc+FaF^^GI zTb|2%?R?6=JBRYPY0Stq-+vb8sA*IO7u3|{M1IjkD=bsyxyMEr( zK)}*i6JFQVyLo3S-VyItsYH@TFU<=llBz9{?d@5$*yTI+RFd;*Hx!(l=yM zk!V~$)dQ(aZ+|+zEgkP~3@!==y5mFfNG9$|rfbV)72XoY3wusC^y-$blT16}x-o4% zcrD-1)q(VM$8f;cC1t!h5)<9k8xE^JbWS#s9nGlGq`Nt5Hg55^H#htBLgQ} zX=(8{q^;yG@?X>1y&(`E?u*A_@mS*}jeY4zGCJr_$8Stz5+g}}%aZ0xgO^cf3hl8NAgQLTJ{>A}+V^_w{vaulH&`-kJ1Ok^P5I22C~WCxc+x!=mE zkzEX`e>54*!h2&Tt`YYAG0bB(jjoKNNlC0=16E`0xey)=$6T|?X)veNC~k{ddZl~V zllJsFORaec)WT>GXSp7b92MQaceM$=Il#hgK~l43Hw8@s|=Iy+Uzx}J&I3DeGz z=nd^7$^OKEJajn$qNC|_JekE~Zh6wrnCj6xN&84T-aZ6#Wl!p$Q)_l=n7}>ZRjV+c zbh4aAd}>>DpK4wY9}#C!u$sh#JG!p4rrQq7)Y9vW-xwe2Z9bdTayDy`?&_t|)4CVz zo}LJ^C2Sd@FIrbiPiSfG^5sltj+eC_DYd4(eVMtR+}6^#+HPNK5JZHh5M?YtwE%OD&-R8O zK13F7m~2#dry0|Y8D_OH)0kz{&{uxJ5yL57^}!j3K*i(%#8pf=F4`=7+_S41O`JX| zayVW!9rOW*mz#l!V`Q$reXO($Oq{!O<%QbcM1K@Io>?*Rkv>}gim7U? z?_yvb!Bv6zRX-ut&+0PJoTYreD=?orgyyqcf%&spXxdd^ehdiBk*UD@`=1KUnOA{V z;=6L>#p>Z4d5QXg(45H?7|$1S=u-8D(3bzH>bE)aGWEXDe2yzH9{DHusH)GZdN~ux zLE_veLA?s=gNCl<9|ChXFK5X<`v7u|9q~MCdoEix6gkyN0Gv{>708j-IdW>DwK?jl zdow{laF+TO;tP@>s+#6ll7FpWR`3o%j+qA?Swg%J-~I(TOG$G!dgd$4A|MvX2H^(; zmk2HwY!mDfFt7cMI|hH1+>h@b3hl7JOdt7lOYQJSk{+Ec-&iDT31k`HK(zw+Jp3Tq%eTty+Ga zU`%kk;H`pp3f?dHu;BLue<=84B9?^Lg?@`TPpRJu{l3trgvNrQsq|na`9v9^All~D3;scH1{MnHHw&&8j0@gOL_5X=@p$Ta zh-PZ!F3)+%-IiD@IA0J;l;#Ho+XPn&ZV=og7!@2491+Y2jtlM){D$Czf{zM5CipZF z^XXYZ?n$Iy7W^d<^Xb=uCk5XVJR@jwU4WiXuvE}5STDFxFeu0$)i~ce1$zXq6yz^y zoNvQ|S-~BG{AG=D9LF{Ox!_+2>U9qC?+C5eInX~4n!j;zUcDjsFM_`j~nobvs4G^T)zC`uPMRl#Zv*0U*jqBQD<)h&ms{pFJ?HBH9rX~Kh{)$tBJ$Dm7kSL(I3n(1BI2zkBA)IKG*O!{J##ziPe+EKgb$ick!&`d=o`(#?f5{KU84HdCdTse*dVGHJ;~t>{DPBQ7Z~WpAvS}DRcJ7M@=Fcd&iN9_^Y>*iKd_xZZdWsT zdLvll7u%EDr8fdScigA^*dw6FxLC%WxZ`>LzKK0z405~Jalf4B@7;OUUQU151{{Ap z_t`e|F%O@=Qmja^W&85{U0bizE6|}oY$J}phx7d11AlRkI0M-JzM1E5;e6}NL4RCR z?0){P_~Y}=@<|!~-v|4sUFeV3GkJRWe97C`|)t$^fw-&|uo_R8+z+~4*7aeu$N ze%<-z81tKBjydO;bIm>1UcGkZx>bf@DEl&0wQ?n;W?ZgwQWj{aR$cCNYF}(VYaB0_@r!1Qmzq6nG_8ymiX}`ta2HhRuOM7g7N?WkP%A}y1jn``x1-dXg4+{`xP+_Yn6d19%+x#qF5{vdkv^;2d2 z=Gr%$etioSy*4p^7JJzhXCB$IKB)R*g-z+_WgNY$W!=%>dFIiMw#qIQ$~n2Q?Tu5p zl}9RKvEJBtc1cr5VBd`Vmifoltr-r7y2@kyu}syvVS4KH+}AEY(Nw6qyZT}sDIK{F zU;a$fC%ew=|4GW+NKygd` zvES%)fmz(ra;&m@^~o3d8rGCH84VMEdwb%4otoeFrBkpUG>&geKYr@o^q-s>uP6u{ zKNX2QcM7(ej9TN^eUYE(bfDHe#@tUtehj&>$vpS_$7Z(v?bP_Z+Wu<;#ZBL6F^>Hz z^0bzp)Uw6@b>s8bh0^V@p5&pa_+eqMiu zS=e+-OW@de<@CSp;KMmf0Qv$1y`%_d-f}pu~e@(;|HHr1>;B# zJRbkP}1(*Y6(3kZk%zs99jj^>58Muu1K4R4FQ zd5UXHuKd1F49R0n0mYx0ZWpDUi%y`SriI}B-4)Krm5G$3XFB3Z@ z+D@5cr|e3L&oyvwxNP{%QyK85B_pFP_1N^-?25dmZ#5Yq&N|~<u<4?*u{0SK8FQ+1J2YC%K zY65Bh3KQl?0O|D7Cx4o=t6hy`YP-T4$&P&=Z@`CX?i(JG;X6!{l6!{F&<_pHp0XFR=V>()& zQ3sXEXapIwUqWNPWFV=s7n=*s-y<<4+@Z`x=GEloRKuLPSPQ`^;kC%QPz&ifHzM1- zNDJ9H=dhbD)Sv z$aFC8Vq^v{(A}Q5fciyDXXhO*R20rbX=B@6NT#4H>bV0+;}`G& zzTjgV_z@ISzlWfLwwaoCRa^zG@mT5)$->26G!A4yIZYEE(?sT!e1-+Tu9@Xjlzt4R zjZbO&R3_vvV?Rx>?imAeVfa^1HO$09h54&^o&s zX>Gk4UQO#_@&Zk}%qg~5%h#~j%pv?W%FSk^d07Krv=B)n=rJ}%V}Ijt2X)~G9Al|k zewxOL47z?h8f1^gL>Sao zNVf&_Tt-N@vft`8$!c#&I$Zn=>#EnbqK@rGE$_2zvsjtO_EHqHY?nEKI>~SGG1GH15eOS{9QA`zmiPpwERW^WTwRy~` z^2>C*%R}1Ykh&aFA6wI`Nmi$SkQJ7)9nD5FU;!$$1~jZ4*sL8`LkD=1#=Ir>z{8I1 zd5-Phuwzm@wqKxamVuVGuXSvvY1@Zrd)DRj`#0R>@T$efIIt1Bzrq(;>F>Cs3EUB% zeTbg_p0w|w*z8}jk4`;>%$FgC81~aqe=`b}8||pBVy>txQC0qs2EGfW%#k>#RXgbO zcj+8PZB7=f8+Ve@Ma=<$(xLdskXsltM9X$u_I^3o;f>hz$oEGr9zP&CCrnT%>MW@KUOh(tOQSzT45-dXK5v39cok^fpknBjsF}S=uO(MpM-YjUHs02GZ5Ax}=O6+gt`6vsAWC zyAb%!MFaGfh>3uvb&_5tYNB2zR41WA)Wj-$z$VNUHPLdu6DjBN);H4Du3#Wa#By<+9I>-30wJW6n+WIX zWIN&WI=PAPu%#tj#5GoJA}qnjvdh%Cl>v%#aV$8NM20{LMtg}BtPC;4Q3$}W@`MzU zEzqpNCzX@vm9m4aNUyV4n*jXEo`$KAsnW_0ZiTQ-=XKE2hjcO_5ZM-bL9E3m4Pm&U zxvK2o0tn0SG1Qhr0IR)Q?DqPDkReVT@gjWE)D>#Y5|}vz;S*lP*(|UWE!YK^X2A!f z@ba=s&TOu6K0*9SQUR?IYCVGr0p8(I5~=noQvIW2=c4xzi@29F)%GF~vUlZ<~@a zaO@!QPc#*TIXFs4-au<8Hxg{Z#)Q!G_5kk%8JNu3I8#?;2kpQz6whg#>!0X;0gS?Z zLI|J9otmc!8woZc(fxOfkz#G3onTv-yd{7S?1$t7>%T){O4~ET7bCRsPcX#_=ilPkx zbCmHhYHRC8uNsX<2kS;hdg?~wgYz4A*4K>2cML~IdWU1GZfta($iDhL(kv> zo>$bM+S(W=n?r$!FT9SZOT;)4t#)j8ax5b5j(Vz^cN#{~Li4JSIV)s#8w;D(uU|g1 za{2n@b%7joh|T)0VN9DprLrOr^eAr#7-ohsbFO)H$jl6xR~eO+X3R$nYrdO{RP(Xq3&G2RAAzD#{c5_#4@H73P&j{rdV@^-BY3o+f@U&6w7Z zyDYJ$`;sZ2OfyOw8qCZkRpt40=4hy4ejwXp=yb9&A5S-mXH?Cos_!*RL+197SrIaO zLknilE-$YsuV|QCVdjQrRLz=QSFyajuA*VNnH`$Dd`{JJGoyCBSs1zuAG2VqdFFk! z6|?G_&6%~!=bJgTX7&;i>etUdZ#@#d^}UiXb3)4(nth?(W$VrC+KNDd$G;mgjcNWK zy(crtpnooz@|jFyo)z8Rn13Uw_Hb4*?$b%NFDBLAlby`M_p*)ZnGFju!@NGcn$0+> zuQ2mM^=3w>JipxB8LF?ZZ%l}%-xxSt&IpA>*c8KZEUH>o z;PECh8Wv2-TG`QYNr&nPhqrfL+8JKg7T!Iyvv-$jZf|K=xuHX?Z45U+yM5J2^op_Q zP|sB!s_N9McX;=wi8|)6%>9HEGhh=orRm0I0(VeIyTsD)z`)?xz<_F>JksqQ zD_5-D(jaA6$-5%G@m0G=)^x5!>5=&6VKs))oZq-TZdV`D~Gg>ep zG=+#Wfd)-Ymq6?P|U>$Z#N0G*2&LZZ6|NxGS_w>Qo<1CN$RqPw&Odwd*s zHg~opjs#utdDpz7Z)`N4Y_ikk_2Elo$TmdZ!$w9GsvGUm^&tktjkX%=i3Z1wBufjzs%M~IAr82bFiI99NJic0)uub6J!2!i z@vCGpaRPu{pxs4BONDM2aQ$FA8L?h(+FKeu^T8TcPd@umL^P0-hn=!1(mfDW;Z>{g z(+d8b&#q~t&#b}@MJ-tIrQ6bQ0UDz-lPr+y9G@){Y>dYb#GYsR$$)8JA_LJ8%j$d- z@r?Os3`>q)H+3(t19at$i8PGzj@~^DJ0m^u-6N`FC4Wpq`_4kq5go-eK`*nVItvpG zHe}LT3$>?S7Pc53{}EoERR*oGW|-(!ZqQ+re7=Uc60q^QZdqQoujt)lx#TV;r*`WipH7?&iOyS0phzGzb@k-X#$UXuF1)s zqGhP`)rG&_uhaYr>y`P{)+_TXvR8hmd_O9FG?Aa_AS7^T5{}n!drH^0f z<5&9lRX%=|kMBkX3z}+hw+(>3AQ`PwRH9mfgYh3edef(O@ zckfc%VYrv6>a5@5K}8=7$llA;52{^_sTy4YDO1h&$^40_dzosHDGMmhjf09IxRA1Mgi`Bd}u^}Eg4=z zpltb@uL?xA@(War$X0!Y>f!``kywKYih)GVago+&b%72z`=ZVKWzHZX}*dO*$}3IBsBpNe6)T@tEgy$U43h#rEy`Th{imUYtuQ zThfB~Xq~A!XSS0Ln?xbKC{zz6Wl zWy(PAh>6@;25wNQoVZWv`vmp8qY*C<g31=9jn zd9Js#Gh6UH!9{{$!Ak@$6Wk>j7yPIo*HezyXGQ)Z@fxL$i2P&06U3{OdO_sZiPtIh zcaiyC3gt{9{L3fq!OwR@o=3a_<0x`7@j9h83T_d7MC6?!Um-GI6{X$x5r>rGn?02G zOa8}2eo*jBLno=O9)ZawL<4Vm-Bf@^MAm6PDMDe3$krxrK z!|z>1ZWHVvcHQ+u{u8(0m+T@h5ahd5flj4bMczz=-OEJoCbq+Gk*|^bTLteB{Q;5h z6Zt`rzbNwKB0nYa4@5pD^7A5}7MZVG1=cIYSI_8w1{Mzbl}qG!5L?k6k?SSDNpO|u z*ArJOb-Bp9B!5ukIB|ti*NJ?aM*H7ZK(8LKW=|i@Zl*~bCkMYu zzMjqd-{%D%5qwPWTY`M)kvzVc&HLa9!CwjfPVi;H*97@eHt&b2f>Q+Z1*Z$@eF}Jd zADj2ZM!^dOmkO>HehcMZ7Wp+nzHd%@dfx@)`~H**1w(>Wf(?QT z1^IqD`D+C?3T_ts7eT!*18+#=5y8EJ`vh+jyi@R_f*%*WU+}OX-+yQQdcOwzw#eTR z{ITFOf_nc3-hYVvCnEMee-`|^;6DWQeh!OhA=YBVc0v{Dw?*}3C?R)OOej@mD z!CwmMePFXvuTciRA*lC-kn^~o!v3pBaJt}ZLB4;_{Dp!`1)Bxe2(A<4i}>81Z5P}r z*eA#r^O-*`c%$I0g8bhFnEw&M2Z-3O>HQ<{iz4fNBxJsu&;0KTJ|p-u!G9P0wIE;8 z=YH-lf^P}pNL1_j(mwNx1!oGD3(gl@B&he5;D<%-5ZofD_m$Y^^->1v{UtCi@;4g4Ul-&H@Z6XENbskECj|LMJo8@@d{b~j5aFN#@5j6#Vy^JKl>5055%pCQvEQsG zvLA>=N;MI&&s{@AzhOzz{kfGGQmTuHafuPD0L+f@i0!r_k9A=Km4mYNftI#QJiSh;{HeV!Ki&iMUUnCgOYSD@1G>&k%7x zR|XLKfOKLv+E0w4{lpmBPsIMFnuz^VJrVn`#YFUH6A_!uHAL)J+lkk}E-v;XmS2tO zMEuDX%p;;-(S;gIi0I!Lf*~UMxk|8_2r{}%V?7c5zCds>5&geJu!)GcMi*&ZLkubX z$}16FqsL{F;8r5Whh0MKB4V6&2*!x0d_ZuRh;fSxUP;9GvFXHdBF6E0!5fKi@>apy zi5SV9;^eo2r-_#<^^)K#M8wVOf@g?`pSJ`R;{b6K6x8t*!}wDM>NrDO z>3u&?#~b2Hp9ca%#g5E)I>^LmBIYl!IQO(Jh4qQ7^D93#Sb zT;wZ>=>O|QzLAJ=xLf4?M2yG%A|ED(WIllWDCJ6tcgQ;4F;345|0EIPrQ;d-I-W6Z zZ%Mw67mS~dSLEw>#W?EtgdAcVU_5m^Le}xPSmFxhusi5O=cZ;-nvH)B1K z{9z(G>l%^Ai5UM|MZTSgI5;5kAtK`8L6ILKA})R)@=+q<<9U%!5)mgaiTnx?@$#0) zigAdz$tJ?TJR;&}hR7jeH`*(*j`t|qD{>PthW3iwPDFfNE^-$UaW)|GFcI-~jmYCf z4E}zR4-gT5hedvnh&X&yCI?yAE?&i-6A&&&U+qoy8492os-lF-R^tz>5`p?m(BxF zPoDD#GkK=}VW_91{o0H3?9-FySWTYke?01zbRLqrDs+wKQE6hgO@3(VmUADSx;pOz zR9CB+36D|rRIi=%(*j-jj%fGTuI;@;J9lG6(CJ8bH(mr&o?N`|<`pA&TWnVp%Ld2X zDl=I#&^v^8m91Q?JF2#4_uya@FLHQF?Hq{=f`pgRY9sOZNN@L89A^Lf*K|;^OsiBW zvcOjqOQF8X@s~Vo4fN&bF^|_geA4lGCmwExlj`k)&c1?@SPJy|$9r_1O#<4yjXoal z-9<@wV?G}59hbH_i& z9`_i@>g6+hFRuszoUC6C`gq)XB&+u;J|6cX$>NWDB5%Fiqa?G(GkY&@$65S)!^h)Z zrannO^Gx4sk9(P9?dAWD?B#v?EWG7D-t&+bC#iRoti_hMJFpz9KKH=l>>^E7w@EL>GzmsR-@wXOUUJ&0; zlC}3mA8*E4c2VSjB0;1dW^#FL@I9Tk7gLA>4J;uSm`Rt|R29|8To$&EyoQ3y_ zkH_CGWNVMCKXyB^kzhZAuCFEFdE<|HyygkdlJMOHynUIrWZ9rp37)sTYtY^!X;$2G zzO!DocfQZwPf#h(1MJJLm(N=4H1nnv;<*+pkju_%_SKud3g>~~HGwxDAG_X7K6`U; z^XRgTfM+LpCg5$y;Y+OVrL>2yvW~r7K6^J{a<|(?Job8g_Rh59{1WY@y+s~-SNZHc zJInfA3@G}tO^^BP-H7k6JXdT2>q2~xt^4@~vB$pWwWs?BHjYj0MdH)Hxe4LE{ literal 0 HcmV?d00001 diff --git a/Release/system/src/stm32f0-stdperiph/subdir.mk b/Release/system/src/stm32f0-stdperiph/subdir.mk new file mode 100644 index 0000000..52db9cd --- /dev/null +++ b/Release/system/src/stm32f0-stdperiph/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../system/src/stm32f0-stdperiph/stm32f0xx_gpio.c \ +../system/src/stm32f0-stdperiph/stm32f0xx_rcc.c + +OBJS += \ +./system/src/stm32f0-stdperiph/stm32f0xx_gpio.o \ +./system/src/stm32f0-stdperiph/stm32f0xx_rcc.o + +C_DEPS += \ +./system/src/stm32f0-stdperiph/stm32f0xx_gpio.d \ +./system/src/stm32f0-stdperiph/stm32f0xx_rcc.d + + +# Each subdirectory must supply rules for building sources it contributes +system/src/stm32f0-stdperiph/%.o: ../system/src/stm32f0-stdperiph/%.c system/src/stm32f0-stdperiph/subdir.mk + @echo 'Building file: $<' + @echo 'Invoking: GNU ARM Cross C Compiler' + arm-none-eabi-gcc -mcpu=cortex-m0 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -Wall -Wextra -g -DNDEBUG -DSTM32F030 -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=10000000 -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f0-stdperiph" -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/bak/ili9341.c b/bak/ili9341.c new file mode 100644 index 0000000..9fa9ea9 --- /dev/null +++ b/bak/ili9341.c @@ -0,0 +1,363 @@ +#include "ili9341.h" +#include "delay.h" + +volatile uint16_t LCD_W=ILI9341_TFTWIDTH; +volatile uint16_t LCD_H=ILI9341_TFTHEIGHT; + + +void ili9341_hard_init(void)//init hardware +{ + // GPIOA->CRL=0x03433330; + //GPIOA->CRL |= 0x6; + GPIOA->BSRR = RST; + GPIOA->BSRR = DC; + GPIOA->BRR = CS; + +} + +void ili9341_hard_reset(void)//hard reset display +{ + GPIOA->BSRR = RST; + delay_ms(200); + GPIOA->BRR = RST; + delay_ms(200); + GPIOA->BSRR = RST; + delay_ms(200); +} + +void ili9341_spi_init(void)//set spi speed and settings +{ + //GPIOA->CRL=0x03433330; // set port for sw spi + //GPIOA->CRL |= 0x6; // set port for hw spi + GPIOA->BSRR=CS; +} + +void ili9341_spi_send(unsigned char spi_data)//send spi data to display +{ + GPIOA->BRR = CS; + *(uint8_t *)&(SPI1->DR) = spi_data; + while(!(SPI1->SR & 0x2)); + while(!(SPI1->SR & 0x1)); + spi_data=(uint8_t)SPI1->DR; + GPIOA->BSRR = CS; + + + /* + * sample for bitbanging SPI + * + + unsigned int i=8,mask=0x80; + + while(i--) { + GPIOA->BRR = SCK; + //PORTB &= ~(1<BSRR = MOSI; + //PORTB |= (1<BRR = MOSI; + //PORTB &= ~(1<BSRR = SCK; + GPIOA->BRR = SCK; + //PORTB |= (1<>1; + + } + */ +} + + +void ili9341_writecommand8(uint8_t com)//command write +{ + GPIOA->BRR = DC; + ili9341_spi_send(com); +} + + +void ili9341_writedata8(uint8_t data)//data write +{ + GPIOA->BSRR = DC; + ili9341_spi_send(data); + //GPIOA->BSRR = CS; +} + + +void ili9341_setaddress(uint16_t x1,uint16_t y1,uint16_t x2,uint16_t y2)//set coordinate for print or other function +{ + ili9341_writecommand8(0x2A); + ili9341_writedata8(x1>>8); + ili9341_writedata8(x1); + ili9341_writedata8(x2>>8); + ili9341_writedata8(x2); + + ili9341_writecommand8(0x2B); + ili9341_writedata8(y1>>8); + ili9341_writedata8(y1); + ili9341_writedata8(y2); + ili9341_writedata8(y2); + + ili9341_writecommand8(0x2C);//meory write +} + + +/*void ili9341_hard_reset(void)//hard reset display +{ + rstport |=(1<>8)); + ili9341_writedata8((uint8_t)colour); +} + + +//clear lcd and fill with colour +void ili9341_clear(uint16_t colour) +{ + uint16_t i,j; + ili9341_setaddress(0,0,LCD_W-1,LCD_H-1); + + for(i=0;i=LCD_W) || (y3 < 0) || (y3 >=LCD_H)) return; + //if((x3 >= LCD_W) || (y3 >=LCD_H)) return; + ili9341_setaddress(x3,y3,x3+1,y3+1); + + ili9341_pushcolour(colour1); +} + + +//draw vertical line +void ili9341_drawvline(uint16_t x,uint16_t y,uint16_t h,uint16_t colour)//basically we will see this line horizental if we see the display 320*240 +{ + if((x >=LCD_W) || (y >=LCD_H)) return; + if((y+h-1)>=LCD_H) + h=LCD_H-y; + ili9341_setaddress(x,y,x,y+h-1); + while(h--) + { + ili9341_pushcolour(colour); + } +} + + +//draw horizental line + +void ili9341_drawhline(uint16_t x,uint16_t y,uint16_t w,uint16_t colour) +{ + if((x >=LCD_W) || (y >=LCD_H)) return; + if((x+w-1)>=LCD_W) + w=((uint16_t)(LCD_W-x)); + ili9341_setaddress(x,y,((uint16_t)(x+w-1)),y); + while(w--) + { + ili9341_pushcolour(colour); + } +} + + +//draw colour filled rectangle +void ili9341_fillrect(uint16_t x,uint16_t y,uint16_t w,uint16_t h,uint16_t colour) +{ + if((x >=LCD_W) || (y >=LCD_H)) return; + if((x+w-1)>=LCD_W) + w=LCD_W-x; + if((y+h-1)>=LCD_H) + h=LCD_H-y; + + ili9341_setaddress(x, y, x+w-1, y+h-1); + + for(y=h; y>0; y--) + { + for(x=w; x>0; x--) + { + ili9341_pushcolour(colour); + } + } +} + +//rotate screen at desired orientation +void ili9341_setRotation(uint8_t m) +{ + uint8_t rotation; + ili9341_writecommand8(0x36); + rotation=m%4; + switch (rotation) + { + case 0: + ili9341_writedata8(0x40|0x08); + LCD_W = 240; + LCD_H = 320; + break; + case 1: + ili9341_writedata8(0x20|0x08); + LCD_W = 320; + LCD_H = 240; + break; + case 2: + ili9341_writedata8(0x80|0x08); + LCD_W = 240; + LCD_H = 320; + break; + case 3: + ili9341_writedata8(0x40|0x80|0x20|0x08); + LCD_W = 320; + LCD_H = 240; + break; + } +} + diff --git a/bak/ili9341.h b/bak/ili9341.h new file mode 100644 index 0000000..f89b68e --- /dev/null +++ b/bak/ili9341.h @@ -0,0 +1,63 @@ + #ifndef ILI9341_H +#define ILI9341_H + +#include +#include +#include +//#include +#include +#include +#include +#include +#include +#include +#include + +#define ILI9341_TFTHEIGHT 240 +#define ILI9341_TFTWIDTH 320 + +#define CS ((uint32_t)0x8) +#define RST ((uint32_t)0x10) +#define DC ((uint32_t)0x40) + +#define BLACK 0x0000 +#define NAVY 0x000F +#define DARKGREEN 0x03E0 +#define DARKCYAN 0x03EF +#define MAROON 0x7800 +#define PURPLE 0x780F +#define OLIVE 0x7BE0 +#define LIGHTGREY 0xC618 +#define DARKGREY 0x7BEF +#define BLUE 0x001F +#define GREEN 0x07E0 +#define CYAN 0x07FF +#define RED 0xF800 +#define MAGENTA 0xF81F +#define YELLOW 0xFFE0 +#define WHITE 0xFFFF +#define ORANGE 0xFD20 +#define DARKORANGE 0xFAE0 +#define GREENYELLOW 0xAFE5 +#define PINK 0xF81F +#define LIGHTBLUE 0x031F +#define GOLD 0xFE80 + + +void ili9341_hard_init(void); +void ili9341_hard_reset(void); +void ili9341_spi_init(void); +void ili9341_spi_send(unsigned char spi_data); +void ili9341_writecommand8(uint8_t com); +void ili9341_writedata8(uint8_t data); +void ili9341_setaddress(uint16_t x1,uint16_t y1,uint16_t x2,uint16_t y2); +void ili9341_init(void); +void ili9341_pushcolour(uint16_t colour); +void ili9341_clear(uint16_t colour); +void ili9341_drawpixel(uint16_t x3,uint16_t y3,uint16_t colour1); +void ili9341_drawvline(uint16_t x,uint16_t y,uint16_t h,uint16_t colour); +void ili9341_drawhline(uint16_t x,uint16_t y,uint16_t w,uint16_t colour); +void ili9341_fillrect(uint16_t x,uint16_t y,uint16_t w,uint16_t h,uint16_t colour); +void ili9341_setRotation(uint8_t x); + +#endif diff --git a/bak/ili9341gfx.c b/bak/ili9341gfx.c new file mode 100644 index 0000000..f1ed716 --- /dev/null +++ b/bak/ili9341gfx.c @@ -0,0 +1,410 @@ +#include "ili9341.h" +#include "ili9341gfx.h" + + +volatile uint16_t cursor_x; +volatile uint16_t cursor_y; +volatile uint16_t textcolour; +volatile uint16_t textbgcolour; +volatile uint8_t textsize; +uint16_t vsetx,vsety,vactualx,vactualy,isetx,isety,iactualx,iactualy; + + + +void backuplocationvset(void)//backing up vset data start location to print next vset data in exact location +{ +vsetx=cursor_x; +vsety=cursor_y; +} + + +void backuplocationvactual(void)//backing up vactual data start location to print next vactual data in exact location +{ +vactualx=cursor_x; +vactualy=cursor_y; +} + +void backuplocationiset(void)//backing up iset data start location to print next iset data in exact location +{ +isetx=cursor_x; +isety=cursor_y; +} + + +void backuplocationiactual(void)//backing up iactual data start location to print next iactual data in exact location +{ +iactualx=cursor_x; +iactualy=cursor_y; +} + + +//array for font +static const unsigned char font[] = { + /* 0x00, 0x00, 0x00, 0x00, 0x00, + 0x3E, 0x5B, 0x4F, 0x5B, 0x3E, + 0x3E, 0x6B, 0x4F, 0x6B, 0x3E, + 0x1C, 0x3E, 0x7C, 0x3E, 0x1C, + 0x18, 0x3C, 0x7E, 0x3C, 0x18, + 0x1C, 0x57, 0x7D, 0x57, 0x1C, + 0x1C, 0x5E, 0x7F, 0x5E, 0x1C, + 0x00, 0x18, 0x3C, 0x18, 0x00, + 0xFF, 0xE7, 0xC3, 0xE7, 0xFF, + 0x00, 0x18, 0x24, 0x18, 0x00, + 0xFF, 0xE7, 0xDB, 0xE7, 0xFF, + 0x30, 0x48, 0x3A, 0x06, 0x0E, + 0x26, 0x29, 0x79, 0x29, 0x26, + 0x40, 0x7F, 0x05, 0x05, 0x07, + 0x40, 0x7F, 0x05, 0x25, 0x3F, + 0x5A, 0x3C, 0xE7, 0x3C, 0x5A, + 0x7F, 0x3E, 0x1C, 0x1C, 0x08, + 0x08, 0x1C, 0x1C, 0x3E, 0x7F, + 0x14, 0x22, 0x7F, 0x22, 0x14, + 0x5F, 0x5F, 0x00, 0x5F, 0x5F, + 0x06, 0x09, 0x7F, 0x01, 0x7F, + 0x00, 0x66, 0x89, 0x95, 0x6A, + 0x60, 0x60, 0x60, 0x60, 0x60, + 0x94, 0xA2, 0xFF, 0xA2, 0x94, + 0x08, 0x04, 0x7E, 0x04, 0x08, + 0x10, 0x20, 0x7E, 0x20, 0x10, + 0x08, 0x08, 0x2A, 0x1C, 0x08, + 0x08, 0x1C, 0x2A, 0x08, 0x08, + 0x1E, 0x10, 0x10, 0x10, 0x10, + 0x0C, 0x1E, 0x0C, 0x1E, 0x0C, + 0x30, 0x38, 0x3E, 0x38, 0x30, + 0x06, 0x0E, 0x3E, 0x0E, 0x06, + */ + 0x00, 0x00, 0x00, 0x00, 0x00, // SPACE + 0x00, 0x00, 0x5F, 0x00, 0x00, // ! + 0x00, 0x07, 0x00, 0x07, 0x00, // " + 0x14, 0x7F, 0x14, 0x7F, 0x14, // # + 0x24, 0x2A, 0x7F, 0x2A, 0x12, // $ + 0x23, 0x13, 0x08, 0x64, 0x62, // % + 0x36, 0x49, 0x56, 0x20, 0x50, // & + 0x00, 0x08, 0x07, 0x03, 0x00, // ' + 0x00, 0x1C, 0x22, 0x41, 0x00, // ( + 0x00, 0x41, 0x22, 0x1C, 0x00, // ) + 0x2A, 0x1C, 0x7F, 0x1C, 0x2A, // * + 0x08, 0x08, 0x3E, 0x08, 0x08, // + + 0x00, 0x80, 0x70, 0x30, 0x00, // , + 0x08, 0x08, 0x08, 0x08, 0x08, // - + 0x00, 0x00, 0x60, 0x60, 0x00, // . + 0x20, 0x10, 0x08, 0x04, 0x02, // / + 0x3E, 0x51, 0x49, 0x45, 0x3E, // 0 + 0x00, 0x42, 0x7F, 0x40, 0x00, // 1 + 0x72, 0x49, 0x49, 0x49, 0x46, // 2 + 0x21, 0x41, 0x49, 0x4D, 0x33, // 3 + 0x18, 0x14, 0x12, 0x7F, 0x10, // 4 + 0x27, 0x45, 0x45, 0x45, 0x39, // 5 + 0x3C, 0x4A, 0x49, 0x49, 0x31, // 6 + 0x41, 0x21, 0x11, 0x09, 0x07, // 7 + 0x36, 0x49, 0x49, 0x49, 0x36, // 8 + 0x46, 0x49, 0x49, 0x29, 0x1E, // 9 + 0x00, 0x00, 0x14, 0x00, 0x00, // : + 0x00, 0x40, 0x34, 0x00, 0x00, // ; + 0x00, 0x08, 0x14, 0x22, 0x41, // < + 0x14, 0x14, 0x14, 0x14, 0x14, // = + 0x00, 0x41, 0x22, 0x14, 0x08, // > + 0x02, 0x01, 0x59, 0x09, 0x06, // ? + 0x3E, 0x41, 0x5D, 0x59, 0x4E, // @ + 0x7C, 0x12, 0x11, 0x12, 0x7C, // A + 0x7F, 0x49, 0x49, 0x49, 0x36, // B + 0x3E, 0x41, 0x41, 0x41, 0x22, // C + 0x7F, 0x41, 0x41, 0x41, 0x3E, // D + 0x7F, 0x49, 0x49, 0x49, 0x41, // E + 0x7F, 0x09, 0x09, 0x09, 0x01, // F + 0x3E, 0x41, 0x41, 0x51, 0x73, // G + 0x7F, 0x08, 0x08, 0x08, 0x7F, // H + 0x00, 0x41, 0x7F, 0x41, 0x00, // I + 0x20, 0x40, 0x41, 0x3F, 0x01, // J + 0x7F, 0x08, 0x14, 0x22, 0x41, // K + 0x7F, 0x40, 0x40, 0x40, 0x40, // L + 0x7F, 0x02, 0x1C, 0x02, 0x7F, // M + 0x7F, 0x04, 0x08, 0x10, 0x7F, // N + 0x3E, 0x41, 0x41, 0x41, 0x3E, // O + 0x7F, 0x09, 0x09, 0x09, 0x06, // P + 0x3E, 0x41, 0x51, 0x21, 0x5E, // Q + 0x7F, 0x09, 0x19, 0x29, 0x46, // R + 0x26, 0x49, 0x49, 0x49, 0x32, // S + 0x03, 0x01, 0x7F, 0x01, 0x03, // T + 0x3F, 0x40, 0x40, 0x40, 0x3F, // U + 0x1F, 0x20, 0x40, 0x20, 0x1F, // V + 0x3F, 0x40, 0x38, 0x40, 0x3F, // W + 0x63, 0x14, 0x08, 0x14, 0x63, // X + 0x03, 0x04, 0x78, 0x04, 0x03, // Y + 0x61, 0x59, 0x49, 0x4D, 0x43, // Z + 0x00, 0x7F, 0x41, 0x41, 0x41, // [ + 0x02, 0x04, 0x08, 0x10, 0x20, // '\' + 0x00, 0x41, 0x41, 0x41, 0x7F, // ] + 0x04, 0x02, 0x01, 0x02, 0x04, // ^ + 0x40, 0x40, 0x40, 0x40, 0x40, // _ + 0x00, 0x03, 0x07, 0x08, 0x00, // ` + 0x20, 0x54, 0x54, 0x78, 0x40, // a + 0x7F, 0x28, 0x44, 0x44, 0x38, // b + 0x38, 0x44, 0x44, 0x44, 0x28, // c + 0x38, 0x44, 0x44, 0x28, 0x7F, // d + 0x38, 0x54, 0x54, 0x54, 0x18, // e + 0x00, 0x08, 0x7E, 0x09, 0x02, // f + 0x18, 0xA4, 0xA4, 0x9C, 0x78, // g + 0x7F, 0x08, 0x04, 0x04, 0x78, // h + 0x00, 0x44, 0x7D, 0x40, 0x00, // i + 0x20, 0x40, 0x40, 0x3D, 0x00, // j + 0x7F, 0x10, 0x28, 0x44, 0x00, // k + 0x00, 0x41, 0x7F, 0x40, 0x00, // l + 0x7C, 0x04, 0x78, 0x04, 0x78, // m + 0x7C, 0x08, 0x04, 0x04, 0x78, // n + 0x38, 0x44, 0x44, 0x44, 0x38, // o + 0xFC, 0x18, 0x24, 0x24, 0x18, // p + 0x18, 0x24, 0x24, 0x18, 0xFC, // q + 0x7C, 0x08, 0x04, 0x04, 0x08, // r + 0x48, 0x54, 0x54, 0x54, 0x24, // s + 0x04, 0x04, 0x3F, 0x44, 0x24, // t + 0x3C, 0x40, 0x40, 0x20, 0x7C, // u + 0x1C, 0x20, 0x40, 0x20, 0x1C, // v + 0x3C, 0x40, 0x30, 0x40, 0x3C, // w + 0x44, 0x28, 0x10, 0x28, 0x44, // x + 0x4C, 0x90, 0x90, 0x90, 0x7C, // y + 0x44, 0x64, 0x54, 0x4C, 0x44, // z + 0x00, 0x08, 0x36, 0x41, 0x00, // { + 0x00, 0x00, 0x77, 0x00, 0x00, // | + 0x00, 0x41, 0x36, 0x08, 0x00, // } + 0x02, 0x01, 0x02, 0x04, 0x02, // ~ + 0x3C, 0x26, 0x23, 0x26, 0x3C, // DEL + 0x1E, 0xA1, 0xA1, 0x61, 0x12, + 0x5c, 0x62, 0x02, 0x62, 0x5c, // omega + 0x18, 0x14, 0x08, 0x14, 0x0c, // infinity + 0x06, 0x09, 0x09, 0x09, 0x06 // degree + + /* 0x3A, 0x40, 0x40, 0x20, 0x7A, + 0x38, 0x54, 0x54, 0x55, 0x59, + 0x21, 0x55, 0x55, 0x79, 0x41, + 0x22, 0x54, 0x54, 0x78, 0x42, // a-umlaut + 0x21, 0x55, 0x54, 0x78, 0x40, + 0x20, 0x54, 0x55, 0x79, 0x40, + 0x0C, 0x1E, 0x52, 0x72, 0x12, + 0x39, 0x55, 0x55, 0x55, 0x59, + 0x39, 0x54, 0x54, 0x54, 0x59, + 0x39, 0x55, 0x54, 0x54, 0x58, + 0x00, 0x00, 0x45, 0x7C, 0x41, + 0x00, 0x02, 0x45, 0x7D, 0x42, + 0x00, 0x01, 0x45, 0x7C, 0x40, + 0x7D, 0x12, 0x11, 0x12, 0x7D, // A-umlaut + 0xF0, 0x28, 0x25, 0x28, 0xF0, + 0x7C, 0x54, 0x55, 0x45, 0x00, + 0x20, 0x54, 0x54, 0x7C, 0x54, + 0x7C, 0x0A, 0x09, 0x7F, 0x49, + 0x32, 0x49, 0x49, 0x49, 0x32, + 0x3A, 0x44, 0x44, 0x44, 0x3A, // o-umlaut + 0x32, 0x4A, 0x48, 0x48, 0x30, + 0x3A, 0x41, 0x41, 0x21, 0x7A, + 0x3A, 0x42, 0x40, 0x20, 0x78, + 0x00, 0x9D, 0xA0, 0xA0, 0x7D, + 0x3D, 0x42, 0x42, 0x42, 0x3D, // O-umlaut + 0x3D, 0x40, 0x40, 0x40, 0x3D, + 0x3C, 0x24, 0xFF, 0x24, 0x24, + 0x48, 0x7E, 0x49, 0x43, 0x66, + 0x2B, 0x2F, 0xFC, 0x2F, 0x2B, + 0xFF, 0x09, 0x29, 0xF6, 0x20, + 0xC0, 0x88, 0x7E, 0x09, 0x03, + 0x20, 0x54, 0x54, 0x79, 0x41, + 0x00, 0x00, 0x44, 0x7D, 0x41, + 0x30, 0x48, 0x48, 0x4A, 0x32, + 0x38, 0x40, 0x40, 0x22, 0x7A, + 0x00, 0x7A, 0x0A, 0x0A, 0x72, + 0x7D, 0x0D, 0x19, 0x31, 0x7D, + 0x26, 0x29, 0x29, 0x2F, 0x28, + 0x26, 0x29, 0x29, 0x29, 0x26, + 0x30, 0x48, 0x4D, 0x40, 0x20, + 0x38, 0x08, 0x08, 0x08, 0x08, + 0x08, 0x08, 0x08, 0x08, 0x38, + 0x2F, 0x10, 0xC8, 0xAC, 0xBA, + 0x2F, 0x10, 0x28, 0x34, 0xFA, + 0x00, 0x00, 0x7B, 0x00, 0x00, + 0x08, 0x14, 0x2A, 0x14, 0x22, + 0x22, 0x14, 0x2A, 0x14, 0x08, + 0xAA, 0x00, 0x55, 0x00, 0xAA, + 0xAA, 0x55, 0xAA, 0x55, 0xAA, + 0x00, 0x00, 0x00, 0xFF, 0x00, + 0x10, 0x10, 0x10, 0xFF, 0x00, + 0x14, 0x14, 0x14, 0xFF, 0x00, + 0x10, 0x10, 0xFF, 0x00, 0xFF, + 0x10, 0x10, 0xF0, 0x10, 0xF0, + 0x14, 0x14, 0x14, 0xFC, 0x00, + 0x14, 0x14, 0xF7, 0x00, 0xFF, + 0x00, 0x00, 0xFF, 0x00, 0xFF, + 0x14, 0x14, 0xF4, 0x04, 0xFC, + 0x14, 0x14, 0x17, 0x10, 0x1F, + 0x10, 0x10, 0x1F, 0x10, 0x1F, + 0x14, 0x14, 0x14, 0x1F, 0x00, + 0x10, 0x10, 0x10, 0xF0, 0x00, + 0x00, 0x00, 0x00, 0x1F, 0x10, + 0x10, 0x10, 0x10, 0x1F, 0x10, + 0x10, 0x10, 0x10, 0xF0, 0x10, + 0x00, 0x00, 0x00, 0xFF, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0xFF, 0x10, + 0x00, 0x00, 0x00, 0xFF, 0x14, + 0x00, 0x00, 0xFF, 0x00, 0xFF, + 0x00, 0x00, 0x1F, 0x10, 0x17, + 0x00, 0x00, 0xFC, 0x04, 0xF4, + 0x14, 0x14, 0x17, 0x10, 0x17, + 0x14, 0x14, 0xF4, 0x04, 0xF4, + 0x00, 0x00, 0xFF, 0x00, 0xF7, + 0x14, 0x14, 0x14, 0x14, 0x14, + 0x14, 0x14, 0xF7, 0x00, 0xF7, + 0x14, 0x14, 0x14, 0x17, 0x14, + 0x10, 0x10, 0x1F, 0x10, 0x1F, + 0x14, 0x14, 0x14, 0xF4, 0x14, + 0x10, 0x10, 0xF0, 0x10, 0xF0, + 0x00, 0x00, 0x1F, 0x10, 0x1F, + 0x00, 0x00, 0x00, 0x1F, 0x14, + 0x00, 0x00, 0x00, 0xFC, 0x14, + 0x00, 0x00, 0xF0, 0x10, 0xF0, + 0x10, 0x10, 0xFF, 0x10, 0xFF, + 0x14, 0x14, 0x14, 0xFF, 0x14, + 0x10, 0x10, 0x10, 0x1F, 0x00, + 0x00, 0x00, 0x00, 0xF0, 0x10, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, + 0xFF, 0xFF, 0xFF, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xFF, 0xFF, + 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, + 0x38, 0x44, 0x44, 0x38, 0x44, + 0xFC, 0x4A, 0x4A, 0x4A, 0x34, // sharp-s or beta + 0x7E, 0x02, 0x02, 0x06, 0x06, + 0x02, 0x7E, 0x02, 0x7E, 0x02, + 0x63, 0x55, 0x49, 0x41, 0x63, + 0x38, 0x44, 0x44, 0x3C, 0x04, + 0x40, 0x7E, 0x20, 0x1E, 0x20, + 0x06, 0x02, 0x7E, 0x02, 0x02, + 0x99, 0xA5, 0xE7, 0xA5, 0x99, + 0x1C, 0x2A, 0x49, 0x2A, 0x1C, + 0x4C, 0x72, 0x01, 0x72, 0x4C, + 0x30, 0x4A, 0x4D, 0x4D, 0x30, + 0x30, 0x48, 0x78, 0x48, 0x30, + 0xBC, 0x62, 0x5A, 0x46, 0x3D, + 0x3E, 0x49, 0x49, 0x49, 0x00, + 0x7E, 0x01, 0x01, 0x01, 0x7E, + 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, + 0x44, 0x44, 0x5F, 0x44, 0x44, + 0x40, 0x51, 0x4A, 0x44, 0x40, + 0x40, 0x44, 0x4A, 0x51, 0x40, + 0x00, 0x00, 0xFF, 0x01, 0x03, + 0xE0, 0x80, 0xFF, 0x00, 0x00, + 0x08, 0x08, 0x6B, 0x6B, 0x08, + 0x36, 0x12, 0x36, 0x24, 0x36, + 0x06, 0x0F, 0x09, 0x0F, 0x06, + 0x00, 0x00, 0x18, 0x18, 0x00, + 0x00, 0x00, 0x10, 0x10, 0x00, + 0x30, 0x40, 0xFF, 0x01, 0x01, + 0x00, 0x1F, 0x01, 0x01, 0x1E, + 0x00, 0x19, 0x1D, 0x17, 0x12, + 0x00, 0x3C, 0x3C, 0x3C, 0x3C, + 0x00, 0x00, 0x00, 0x00, 0x00 + */ +}; + +extern uint16_t LCD_W,LCD_H; + +void ili9341_drawchar(int16_t x, int16_t y, unsigned char c,uint16_t color, uint16_t bg, uint8_t size) //draw a char like a,b or 1,2 +{ + + c-=32; + + if((x >=LCD_W) || // Clip right + (y >=LCD_H) || // Clip bottom + ((x + 6 * size - 1) < 0) || // Clip left + ((y + 8 * size - 1) < 0)) // Clip top + return; + + for (int8_t i=0; i<6; i++ ) { + uint8_t line; + if (i == 5) + line = 0x0; + else + line = (font[(c*5)+i]); + + for (int8_t j = 0; j<8; j++) { + if (line & 0x1) { + if (size == 1) // default size + ili9341_drawpixel(x+i,y+j, color); + else { // big size + ili9341_fillrect(x+(i*size), y+(j*size), size, size, color); + } + } else if (bg != color) { + if (size == 1) // default size + ili9341_drawpixel(x+i, y+j, bg); + else + { // big size + ili9341_fillrect(x+i*size,y+j*size, size, size, bg); + } + } + line >>= 1; + + + } + } +} + + +void ili9341_setcursor(uint16_t x,uint16_t y)//set cursor at desired location to print data +{ +cursor_x=x; +cursor_y=y; +} + +void ili9341_settextcolour(uint16_t x,uint16_t y)//set text colour and text background colour +{ +textcolour=x; +textbgcolour=y; +} + +void ili9341_settextsize(uint8_t s) +{ +if(s>8) return; +textsize=(s>0) ? s: 1;//this operation means if s0 greater than 0,then s=s,else s=1 +} + +void ili9341_write(uint8_t c)//write a character at setted coordinates after setting location and colour +{ +if (c == '\n') { +cursor_y = cursor_y+textsize*8; +cursor_x = 0; +} else if (c == '\r') { + // skip em +} +else +{ +ili9341_drawchar(cursor_x, cursor_y, c, textcolour, textbgcolour, textsize); +cursor_x = cursor_x+textsize*6; +} +} + +void ili9341_out(char *strn) { + //uint8_t line; + register char c; + while((c= *strn++)) { + ili9341_write(((uint8_t)(c))); + /* switch(c) { + case 0xa: line=(lcd_read(0) & 0x7f); // LF + if(line<=0x13) { + lcd_write(0xc0,0); + } + else if(line<=0x28) { + lcd_write(0xd4,0); + } + else if(line<=0x53) { + lcd_write(0x94,0); + } + else if(line<=0x68) { + lcd_write(0x80,0); + } + break; + case 0xd: lcd_write(0x80,0x0); break; // CR is leading back to position 0 + case '$': lcd_write(0xf7,0x1); break; + case '|': lcd_write(0xdf,0x1); break; + break; + }*/ + } +} + + diff --git a/bak/ili9341gfx.h b/bak/ili9341gfx.h new file mode 100644 index 0000000..a9e7f7d --- /dev/null +++ b/bak/ili9341gfx.h @@ -0,0 +1,27 @@ +#ifndef ILI9341GFX_H +#define ILI9341GFX_H +#endif + +#include +#include +//#include +#include +#include +#include +#include +#include +#include +#include + +void ili9341_drawchar(int16_t x, int16_t y, unsigned char c,uint16_t color, uint16_t bg, uint8_t size); +void ili9341_setcursor(uint16_t x,uint16_t y); +void ili9341_settextcolour(uint16_t x,uint16_t y); +void ili9341_settextsize(uint8_t s); +void ili9341_write(uint8_t c); +void backuplocationvset(void); +void backuplocationvactual(void); +void backuplocationiset(void); +void backuplocationiactual(void); +void ili9341_out(char *strn); +//void display_init(void); + diff --git a/include/24aaxx.h b/include/24aaxx.h new file mode 100644 index 0000000..3d6f92f --- /dev/null +++ b/include/24aaxx.h @@ -0,0 +1,18 @@ +/* + * mcp24aaxx.h + * + * Created on: Oct 8, 2017 + * Author: pascal.spring + */ + +#ifndef _24AAXX_H_ +#define _24AAXX_H_ +#include +#define DEVICE_ADDR 0x50 + +//extern volatile uint8_t i2c_rx_buf[10],i2c_tx_buf[10],i2c_index,i2c_count; + +uint32_t _24aa02_read_dword(I2C_TypeDef * I2Cx, uint8_t addr); +void _24aa02_write_dword(I2C_TypeDef * I2Cx, uint8_t addr, uint32_t data); + +#endif /* 24AAXX_H_ */ diff --git a/include/delay.h b/include/delay.h new file mode 100644 index 0000000..dcfad95 --- /dev/null +++ b/include/delay.h @@ -0,0 +1,26 @@ +#ifndef DELAY_H +#define DELAY_H + +#include +#include + +#define TIMER_FREQUENCY_HZ (1000UL) + +typedef uint32_t timer_ticks_t; + +extern volatile timer_ticks_t timer_delayCount; + +extern void +delay_init (void); + +extern void +timer_sleep (timer_ticks_t ticks); + +extern void +delay_ms(timer_ticks_t ticks); + +/* +extern void +delay_us(timer_ticks_t ticks); +*/ +#endif diff --git a/include/font_Arial.h b/include/font_Arial.h new file mode 100644 index 0000000..2faa601 --- /dev/null +++ b/include/font_Arial.h @@ -0,0 +1,28 @@ +#ifndef _font_Arial_ +#define _font_Arial_ + +//#include "ILI9341_t3.h" +#include "font_typedef.h" + + +extern const ILI9341_t3_font_t Arial_8; +extern const ILI9341_t3_font_t Arial_9; +extern const ILI9341_t3_font_t Arial_10; +extern const ILI9341_t3_font_t Arial_11; +extern const ILI9341_t3_font_t Arial_12; +extern const ILI9341_t3_font_t Arial_13; +extern const ILI9341_t3_font_t Arial_14; +extern const ILI9341_t3_font_t Arial_16; +extern const ILI9341_t3_font_t Arial_18; +extern const ILI9341_t3_font_t Arial_20; +extern const ILI9341_t3_font_t Arial_24; +extern const ILI9341_t3_font_t Arial_28; +extern const ILI9341_t3_font_t Arial_32; +extern const ILI9341_t3_font_t Arial_40; +extern const ILI9341_t3_font_t Arial_48; +extern const ILI9341_t3_font_t Arial_60; +extern const ILI9341_t3_font_t Arial_72; +extern const ILI9341_t3_font_t Arial_96; + + +#endif diff --git a/include/font_courier.h b/include/font_courier.h new file mode 100644 index 0000000..04cb8dc --- /dev/null +++ b/include/font_courier.h @@ -0,0 +1,7 @@ +#define nr_chrs_fc 96 +#define chr_hgt_fc 13 +#define data_size_fc 8 +#define firstchr_fc 32 + +const unsigned char widtbl_fc[96]; +const unsigned char* const chrtbl_fc[96]; diff --git a/include/font_typedef.h b/include/font_typedef.h new file mode 100644 index 0000000..289e716 --- /dev/null +++ b/include/font_typedef.h @@ -0,0 +1,24 @@ +#ifndef INC_FONT_TYPEDEF_H_ +#define INC_FONT_TYPEDEF_H_ + +typedef struct { + const unsigned char *index; + const unsigned char *unicode; + const unsigned char *data; + unsigned char version; + unsigned char reserved; + unsigned char index1_first; + unsigned char index1_last; + unsigned char index2_first; + unsigned char index2_last; + unsigned char bits_index; + unsigned char bits_width; + unsigned char bits_height; + unsigned char bits_xoffset; + unsigned char bits_yoffset; + unsigned char bits_delta; + unsigned char line_space; + unsigned char cap_height; +} ILI9341_t3_font_t; + +#endif /* INC_FONT_TYPEDEF_H_ */ diff --git a/include/glcdfont.h b/include/glcdfont.h new file mode 100644 index 0000000..767728e --- /dev/null +++ b/include/glcdfont.h @@ -0,0 +1,9 @@ +#ifndef _ILI9341_t3_font_5x7_ +#define _ILI9341_t3_font_5x7_ + +#include "font_typedef.h" + +const unsigned char glcdfont[1276]; +const ILI9341_t3_font_t Font5x7; + +#endif /* INC_GLCDFONT_H_ */ diff --git a/include/i2c.h b/include/i2c.h new file mode 100644 index 0000000..a11ab39 --- /dev/null +++ b/include/i2c.h @@ -0,0 +1,35 @@ +/* + * i2c.h + * + * Created on: Sep 30, 2017 + * Author: pascal.spring + */ + +#ifndef I2C_H_ +#define I2C_H_ + +#ifndef __STM32F10X_I2C_H +#include +#endif +#include +#define I2C_READ 1 +#define I2C_WRITE 0 + +extern volatile uint8_t i2c_rx_buf[10], i2c_tx_buf[10],i2c_index,i2c_count; + +void i2c_init(I2C_TypeDef * I2Cx); +uint8_t i2c_status(I2C_TypeDef * I2Cx, uint8_t stat); +void i2c_start(I2C_TypeDef * I2Cx); +void i2c_restart(I2C_TypeDef * I2Cx); +void i2c_stop(I2C_TypeDef * I2Cx); +void i2c_reset(I2C_TypeDef * I2Cx); +void i2c_autoend(I2C_TypeDef * I2Cx, uint8_t autoend); +void i2c_set_nbytes(I2C_TypeDef * I2Cx, uint8_t nbytes); +uint8_t i2c_read_nack(I2C_TypeDef * I2Cx); +uint8_t i2c_read_ack(I2C_TypeDef * I2Cx); +void i2c_write_addr(I2C_TypeDef * I2Cx, uint8_t addr, uint8_t dir); +void i2c_write(I2C_TypeDef * I2Cx, uint8_t data); + + + +#endif /* I2C_H_ */ diff --git a/include/ili9341.h b/include/ili9341.h new file mode 100644 index 0000000..09fa442 --- /dev/null +++ b/include/ili9341.h @@ -0,0 +1,102 @@ +#ifndef __ILI9341_H +#define __ILI9341_H + +#include +#include +#include +#include +#include +#include +#include +#include + +#define ILI9341_TFTWIDTH 320UL +#define ILI9341_TFTHEIGHT 240UL + +#define CS ((uint32_t)0x10) +#define RST ((uint32_t)0x8) +#define DC ((uint32_t)0x40) + + +#define VIRIDIAN 0x440D +#define EMERALD 0x54CA +#define GREEN 0x6586 +#define DARKGREEN 0x0320 +#define GREENYELLOW 0xDFE1 +#define FAINTGREEN 0x32C6 +#define LIME 0x27E1 + +#define ULTRAPURPLE 0x381F +#define DARKPURPLE 0x981F +#define PURPLE 0xD01F +#define LILAS 0xF81B +#define RED 0xF804 + +#define BLACK 0x0000 +#define NAVY 0x000F +//#define DARKGREEN 0x03E0 +#define DARKCYAN 0x03EF +#define MAROON 0x7800 +//#define PURPLE 0x780F +#define OLIVE 0x7BE0 +#define LIGHTGREY 0xC618 +#define DARKGREY 0x7BEF +#define BLUE 0x001F +//#define GREEN 0x07E0 +#define CYAN 0x07FF +//#define RED 0xF800 +#define MAGENTA 0xF81F +#define YELLOW 0xFFE0 +#define MARINE 0x041F +#define WHITE 0xFFFF +#define ORANGE 0xFD20 +#define DARKORANGE 0xFAE0 +//#define GREENYELLOW 0xAFE5 +#define PINK 0xF81F +#define LIGHTBLUE 0x031F +#define GOLD 0xFE80 + +extern volatile uint16_t spi_buf; +int16_t _originx, _originy; +int16_t _displayclipx1, _displayclipy1, _displayclipx2, _displayclipy2; +int16_t _clipx1, _clipy1, _clipx2, _clipy2; +uint8_t _invisible; +uint8_t _standard; + +int16_t width(void); +int16_t height(void); + +void ili9341_updatedisplayclip(); +void ili9341_setorigin(void); +//void getOrigin(int16_t *x, int16_t *y); +void ili9341_setcliprect(); +void ili9341_hard_init(void); +void ili9341_hard_reset(void); +void ili9341_spi_init(void); +void ili9341_spi_send(SPI_TypeDef * SPIx, uint16_t spi_data); +void ili9341_writecommand8(uint8_t com); +void ili9341_writedata8(uint8_t data); +void ili9341_writedata16(uint16_t data); +void ili9341_setaddress(uint16_t x1,uint16_t y1,uint16_t x2,uint16_t y2); +void ili9341_init(void); +void ili9341_pushcolor(uint16_t color); +void ili9341_clear(uint16_t color); +void ili9341_drawpixel(uint16_t x3,uint16_t y3,uint16_t color1); +void ili9341_drawvline(uint16_t x,uint16_t y,uint16_t h,uint16_t color); +void ili9341_drawhline(uint16_t x,uint16_t y,uint16_t w,uint16_t color); +void ili9341_drawline(int16_t x0, int16_t y0, int16_t x1, int16_t y1, uint16_t color); +void ili9341_drawcirclehelper(int16_t x0, int16_t y0, int16_t r,uint8_t cornername, uint16_t color); +void ili9341_fillcirclehelper(int16_t x0, int16_t y0, int16_t r,uint8_t cornername, int16_t delta,uint16_t color); +void ili9341_drawrect(uint16_t x, uint16_t y, uint16_t w, uint16_t h,uint16_t color); +void ili9341_fillrect(uint16_t x,uint16_t y,uint16_t w,uint16_t h,uint16_t color); +void ili9341_drawroundrect(int16_t x, int16_t y, int16_t w, int16_t h,int16_t r, uint16_t color); +void ili9341_fillroundrect(int16_t x, int16_t y, int16_t w, int16_t h,int16_t r, uint16_t color); +void ili9341_drawhollowcircle(uint16_t X, uint16_t Y, uint16_t radius, uint16_t color); +void ili9341_drawfilledcircle(uint16_t X, uint16_t Y, uint16_t radius, uint16_t color); +void ili9341_drawtriangle(int16_t x0, int16_t y0, int16_t x1, int16_t y1, int16_t x2, int16_t y2, uint16_t color); +void ili9341_filltriangle(int16_t x0, int16_t y0,int16_t x1, int16_t y1,int16_t x2, int16_t y2, uint16_t color); +void ili9341_fillrecthgradient(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color1, uint16_t color2); +void ili9341_fillrectvgradient(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color1, uint16_t color2); +void ili9341_setrotation(uint8_t x); + +#endif diff --git a/include/ili9341gfx.h b/include/ili9341gfx.h new file mode 100644 index 0000000..d855295 --- /dev/null +++ b/include/ili9341gfx.h @@ -0,0 +1,29 @@ +#ifndef ILI9341GFX_H +#define ILI9341GFX_H +#endif + +#include +#include +#include +#include +#include +#include +#include +#include "font_typedef.h" + + +void ili9341_setfont(const ILI9341_t3_font_t f); +void ili9341_setcursor(uint16_t x,uint16_t y); +void ili9341_settextcolor(uint16_t x,uint16_t y); +void ili9341_settextsize(uint8_t s); +void ili9341_drawcharbits(int16_t x, int16_t y, char c,uint16_t fgcolor, uint16_t bgcolor, uint8_t size_x,uint8_t size_y); +void ili9341_drawfontbits(uint8_t opaque, uint32_t bits, uint32_t numbits, int32_t x, int32_t y, uint32_t repeat); +void ili9341_drawfontchar(char c); +void ili9341_drawchar(char c); +void backuplocationvset(void); +void backuplocationvactual(void); +void backuplocationiset(void); +void backuplocationiactual(void); +void ili9341_out(char *strn); +//void display_init(void); + diff --git a/include/si5351a.h b/include/si5351a.h new file mode 100644 index 0000000..d4f8cbd --- /dev/null +++ b/include/si5351a.h @@ -0,0 +1,70 @@ +#ifndef SI5351A_H +#define SI5351A_H + +#include "i2c.h" +#include "delay.h" + +uint8_t i2cSendRegister(uint8_t i2c_chan, uint8_t reg, uint8_t reg_data); +uint8_t i2cReadRegister(uint8_t i2c_chan, uint8_t reg); +void setupPLL(uint8_t i2c_chan, uint8_t pll, uint8_t mult, uint32_t num, uint32_t denom); +void setupMultisynth(uint8_t i2c_chan, uint8_t synth, uint32_t divider, uint8_t rDiv); +void si5351aOutputOff(uint8_t output_status); +//extern void si5351aSetFrequency(uint32_t frequency, uint8_t quad); +//extern void si5351aSetQuad(uint8_t offset); +void si5351aSet(uint8_t i2c_chan, uint32_t frequency,uint8_t output,uint8_t output_status); + + + + +#define SI_DEV_STATUS 1 +#define SI_INT_STATUS 2 +#define SI_PLL_SRC 15 +#define SI_CLK0_CONTROL 16 +#define SI_CLK1_CONTROL 17 +#define SI_CLK2_CONTROL 18 +#define SI_CLK3_CONTROL 19 +#define SI_CLK4_CONTROL 20 +#define SI_CLK5_CONTROL 21 +#define SI_CLK6_CONTROL 22 +#define SI_CLK7_CONTROL 23 +#define SI_SYNTH_PLL_A 26 +#define SI_SYNTH_PLL_B 34 +#define SI_SYNTH_MS_0 42 +#define SI_SYNTH_MS_1 50 +#define SI_SYNTH_MS_2 58 +#define SI_SYNTH_MS_3 66 +#define SI_SYNTH_MS_4 74 +#define SI_SYNTH_MS_5 82 +#define SI_SYNTH_MS_6 90 +#define SI_SYNTH_MS_7 91 +#define SI_CLK0_PHOFF 165 +#define SI_CLK1_PHOFF 166 +#define SI_CLK2_PHOFF 167 +#define SI_CLK3_PHOFF 168 +#define SI_CLK4_PHOFF 169 +#define SI_CLK5_PHOFF 170 +#define SI_PLL_RESET 177 +#define SI_FAN_OUT 187 + + +#define SI_R_DIV_1 0x0 // R-division ratio definitions +#define SI_R_DIV_2 0x10 +#define SI_R_DIV_4 0x20 +#define SI_R_DIV_8 0x30 +#define SI_R_DIV_16 0x40 +#define SI_R_DIV_32 0x50 +#define SI_R_DIV_64 0x60 +#define SI_R_DIV_128 0x70 + +#define SI_CLK_SRC_PLL_A 0b00000000 +#define SI_CLK_SRC_PLL_B 0b00100000 +#define SI_CLK_MS_INT 0x40 + +#define SI_PLLA_CLKIN 0x4 +#define SI_PLLB_CLKIN 0x8 +#define SI_PLL_CLKIN 0xc + +#define XTAL_FREQ 10000000UL // Crystal frequency + + +#endif //SI5351A_H diff --git a/include/stm32f0xx_conf.h b/include/stm32f0xx_conf.h new file mode 100644 index 0000000..35dcdd7 --- /dev/null +++ b/include/stm32f0xx_conf.h @@ -0,0 +1,83 @@ +/** + ****************************************************************************** + * @file Project/STM32F0xx_StdPeriph_Templates/stm32f0xx_conf.h + * @author MCD Application Team + * @version V1.3.1 + * @date 17-January-2014 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_CONF_H +#define __STM32F0XX_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Comment the line below to disable peripheral header file inclusion */ +#include "stm32f0xx_adc.h" +#include "stm32f0xx_can.h" +#include "stm32f0xx_cec.h" +#include "stm32f0xx_crc.h" +#include "stm32f0xx_crs.h" +#include "stm32f0xx_comp.h" +#include "stm32f0xx_dac.h" +#include "stm32f0xx_dbgmcu.h" +#include "stm32f0xx_dma.h" +#include "stm32f0xx_exti.h" +#include "stm32f0xx_flash.h" +#include "stm32f0xx_gpio.h" +#include "stm32f0xx_syscfg.h" +#include "stm32f0xx_i2c.h" +#include "stm32f0xx_iwdg.h" +#include "stm32f0xx_pwr.h" +#include "stm32f0xx_rcc.h" +#include "stm32f0xx_rtc.h" +#include "stm32f0xx_spi.h" +#include "stm32f0xx_tim.h" +#include "stm32f0xx_usart.h" +#include "stm32f0xx_wwdg.h" +#include "stm32f0xx_misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F0XX_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/ldscripts/libs.ld b/ldscripts/libs.ld new file mode 100644 index 0000000..70fea89 --- /dev/null +++ b/ldscripts/libs.ld @@ -0,0 +1,8 @@ + +/* + * Placeholder to list other libraries required by the application. + +GROUP( +) + + */ diff --git a/ldscripts/mem.ld b/ldscripts/mem.ld new file mode 100644 index 0000000..74a3e9a --- /dev/null +++ b/ldscripts/mem.ld @@ -0,0 +1,59 @@ +/* + * This file is part of the ??OS++ distribution. + * (https://github.com/micro-os-plus) + * Copyright (c) 2014 Liviu Ionescu. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Memory Spaces Definitions. + * + * Need modifying for a specific board. + * FLASH.ORIGIN: starting address of flash + * FLASH.LENGTH: length of flash + * RAM.ORIGIN: starting address of RAM bank 0 + * RAM.LENGTH: length of RAM bank 0 + * + * The values below can be addressed in further linker scripts + * using functions like 'ORIGIN(RAM)' or 'LENGTH(RAM)'. + */ + +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 8K + CCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 0 + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 64K + FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + MEMORY_ARRAY (xrw) : ORIGIN = 0x00000000, LENGTH = 0 +} + +/* + * For external ram use something like: + + RAM (xrw) : ORIGIN = 0x68000000, LENGTH = 8K + + */ diff --git a/ldscripts/sections.ld b/ldscripts/sections.ld new file mode 100644 index 0000000..a6432cb --- /dev/null +++ b/ldscripts/sections.ld @@ -0,0 +1,473 @@ +/* + * This file is part of the ??OS++ distribution. + * (https://github.com/micro-os-plus) + * Copyright (c) 2014 Liviu Ionescu. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Default linker script for Cortex-M (it includes specifics for + * STM32F[34]xx). + * + * To make use of the multi-region initialisations, define + * OS_INCLUDE_STARTUP_INIT_MULTIPLE_RAM_SECTIONS for the _startup.c file. + */ + +/* + * The '__stack' definition is required by crt0, do not remove it. + */ +__stack = ORIGIN(RAM) + LENGTH(RAM); + +_estack = __stack; /* STM specific definition */ + +/* + * Default stack sizes. + * These are used by the startup in order to allocate stacks + * for the different modes. + */ + +__Main_Stack_Size = 1024 ; + +PROVIDE ( _Main_Stack_Size = __Main_Stack_Size ) ; + +__Main_Stack_Limit = __stack - __Main_Stack_Size ; + +/* "PROVIDE" allows to easily override these values from an + * object file or the command line. */ +PROVIDE ( _Main_Stack_Limit = __Main_Stack_Limit ) ; + +/* + * There will be a link error if there is not this amount of + * RAM free at the end. + */ +_Minimum_Stack_Size = 256 ; + +/* + * Default heap definitions. + * The heap start immediately after the last statically allocated + * .sbss/.noinit section, and extends up to the main stack limit. + */ +PROVIDE ( _Heap_Begin = _end_noinit ) ; +PROVIDE ( _Heap_Limit = __stack - __Main_Stack_Size ) ; + +/* + * The entry point is informative, for debuggers and simulators, + * since the Cortex-M vector points to it anyway. + */ +ENTRY(_start) + + +/* Sections Definitions */ + +SECTIONS +{ + /* + * For Cortex-M devices, the beginning of the startup code is stored in + * the .isr_vector section, which goes to FLASH. + */ + .isr_vector : ALIGN(4) + { + FILL(0xFF) + + __vectors_start = ABSOLUTE(.) ; + __vectors_start__ = ABSOLUTE(.) ; /* STM specific definition */ + KEEP(*(.isr_vector)) /* Interrupt vectors */ + + KEEP(*(.cfmconfig)) /* Freescale configuration words */ + + /* + * This section is here for convenience, to store the + * startup code at the beginning of the flash area, hoping that + * this will increase the readability of the listing. + */ + *(.after_vectors .after_vectors.*) /* Startup code and ISR */ + + } >FLASH + + .inits : ALIGN(4) + { + /* + * Memory regions initialisation arrays. + * + * Thee are two kinds of arrays for each RAM region, one for + * data and one for bss. Each is iterrated at startup and the + * region initialisation is performed. + * + * The data array includes: + * - from (LOADADDR()) + * - region_begin (ADDR()) + * - region_end (ADDR()+SIZEOF()) + * + * The bss array includes: + * - region_begin (ADDR()) + * - region_end (ADDR()+SIZEOF()) + * + * WARNING: It is mandatory that the regions are word aligned, + * since the initialisation code works only on words. + */ + + __data_regions_array_start = .; + + LONG(LOADADDR(.data)); + LONG(ADDR(.data)); + LONG(ADDR(.data)+SIZEOF(.data)); + + LONG(LOADADDR(.data_CCMRAM)); + LONG(ADDR(.data_CCMRAM)); + LONG(ADDR(.data_CCMRAM)+SIZEOF(.data_CCMRAM)); + + __data_regions_array_end = .; + + __bss_regions_array_start = .; + + LONG(ADDR(.bss)); + LONG(ADDR(.bss)+SIZEOF(.bss)); + + LONG(ADDR(.bss_CCMRAM)); + LONG(ADDR(.bss_CCMRAM)+SIZEOF(.bss_CCMRAM)); + + __bss_regions_array_end = .; + + /* End of memory regions initialisation arrays. */ + + /* + * These are the old initialisation sections, intended to contain + * naked code, with the prologue/epilogue added by crti.o/crtn.o + * when linking with startup files. The standalone startup code + * currently does not run these, better use the init arrays below. + */ + KEEP(*(.init)) + KEEP(*(.fini)) + + . = ALIGN(4); + + /* + * The preinit code, i.e. an array of pointers to initialisation + * functions to be performed before constructors. + */ + PROVIDE_HIDDEN (__preinit_array_start = .); + + /* + * Used to run the SystemInit() before anything else. + */ + KEEP(*(.preinit_array_sysinit .preinit_array_sysinit.*)) + + /* + * Used for other platform inits. + */ + KEEP(*(.preinit_array_platform .preinit_array_platform.*)) + + /* + * The application inits. If you need to enforce some order in + * execution, create new sections, as before. + */ + KEEP(*(.preinit_array .preinit_array.*)) + + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + + /* + * The init code, i.e. an array of pointers to static constructors. + */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + + /* + * The fini code, i.e. an array of pointers to static destructors. + */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + } >FLASH + + /* + * For some STRx devices, the beginning of the startup code + * is stored in the .flashtext section, which goes to FLASH. + */ + .flashtext : ALIGN(4) + { + *(.flashtext .flashtext.*) /* Startup code */ + } >FLASH + + + /* + * The program code is stored in the .text section, + * which goes to FLASH. + */ + .text : ALIGN(4) + { + *(.text .text.*) /* all remaining code */ + + /* read-only data (constants) */ + *(.rodata .rodata.* .constdata .constdata.*) + + *(vtable) /* C++ virtual tables */ + + KEEP(*(.eh_frame*)) + + /* + * Stub sections generated by the linker, to glue together + * ARM and Thumb code. .glue_7 is used for ARM code calling + * Thumb code, and .glue_7t is used for Thumb code calling + * ARM code. Apparently always generated by the linker, for some + * architectures, so better leave them here. + */ + *(.glue_7) + *(.glue_7t) + + } >FLASH + + /* ARM magic sections */ + .ARM.extab : ALIGN(4) + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + . = ALIGN(4); + __exidx_start = .; + .ARM.exidx : ALIGN(4) + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + . = ALIGN(4); + _etext = .; + __etext = .; + + /* MEMORY_ARRAY */ + /* + .ROarraySection : + { + *(.ROarraySection .ROarraySection.*) + } >MEMORY_ARRAY + */ + + /* + * The secondary initialised data section. + */ + .data_CCMRAM : ALIGN(4) + { + FILL(0xFF) + *(.data.CCMRAM .data.CCMRAM.*) + . = ALIGN(4) ; + } > CCMRAM AT>FLASH + + /* + * This address is used by the startup code to + * initialise the .data section. + */ + _sidata = LOADADDR(.data); + + /* + * The initialised data section. + * + * The program executes knowing that the data is in the RAM + * but the loader puts the initial values in the FLASH (inidata). + * It is one task of the startup to copy the initial values from + * FLASH to RAM. + */ + .data : ALIGN(4) + { + FILL(0xFF) + /* This is used by the startup code to initialise the .data section */ + _sdata = . ; /* STM specific definition */ + __data_start__ = . ; + *(.data_begin .data_begin.*) + + *(.data .data.*) + + *(.data_end .data_end.*) + . = ALIGN(4); + + /* This is used by the startup code to initialise the .data section */ + _edata = . ; /* STM specific definition */ + __data_end__ = . ; + + } >RAM AT>FLASH + + /* + * The uninitialised data sections. NOLOAD is used to avoid + * the "section `.bss' type changed to PROGBITS" warning + */ + + /* The secondary uninitialised data section. */ + .bss_CCMRAM (NOLOAD) : ALIGN(4) + { + *(.bss.CCMRAM .bss.CCMRAM.*) + } > CCMRAM + + /* The primary uninitialised data section. */ + .bss (NOLOAD) : ALIGN(4) + { + __bss_start__ = .; /* standard newlib definition */ + _sbss = .; /* STM specific definition */ + *(.bss_begin .bss_begin.*) + + *(.bss .bss.*) + *(COMMON) + + *(.bss_end .bss_end.*) + . = ALIGN(4); + __bss_end__ = .; /* standard newlib definition */ + _ebss = . ; /* STM specific definition */ + } >RAM + + .noinit_CCMRAM (NOLOAD) : ALIGN(4) + { + *(.noinit.CCMRAM .noinit.CCMRAM.*) + } > CCMRAM + + .noinit (NOLOAD) : ALIGN(4) + { + _noinit = .; + + *(.noinit .noinit.*) + + . = ALIGN(4) ; + _end_noinit = .; + } > RAM + + /* Mandatory to be word aligned, _sbrk assumes this */ + PROVIDE ( end = _end_noinit ); /* was _ebss */ + PROVIDE ( _end = _end_noinit ); + PROVIDE ( __end = _end_noinit ); + PROVIDE ( __end__ = _end_noinit ); + + /* + * Used for validation only, do not allocate anything here! + * + * This is just to check that there is enough RAM left for the Main + * stack. It should generate an error if it's full. + */ + ._check_stack : ALIGN(4) + { + . = . + _Minimum_Stack_Size ; + } >RAM + + /* + * The FLASH Bank1. + * The C or assembly source must explicitly place the code + * or data there using the "section" attribute. + */ + .b1text : ALIGN(4) + { + *(.b1text) /* remaining code */ + *(.b1rodata) /* read-only data (constants) */ + *(.b1rodata.*) + } >FLASHB1 + + /* + * The EXTMEM. + * The C or assembly source must explicitly place the code or data there + * using the "section" attribute. + */ + + /* EXTMEM Bank0 */ + .eb0text : ALIGN(4) + { + *(.eb0text) /* remaining code */ + *(.eb0rodata) /* read-only data (constants) */ + *(.eb0rodata.*) + } >EXTMEMB0 + + /* EXTMEM Bank1 */ + .eb1text : ALIGN(4) + { + *(.eb1text) /* remaining code */ + *(.eb1rodata) /* read-only data (constants) */ + *(.eb1rodata.*) + } >EXTMEMB1 + + /* EXTMEM Bank2 */ + .eb2text : ALIGN(4) + { + *(.eb2text) /* remaining code */ + *(.eb2rodata) /* read-only data (constants) */ + *(.eb2rodata.*) + } >EXTMEMB2 + + /* EXTMEM Bank0 */ + .eb3text : ALIGN(4) + { + *(.eb3text) /* remaining code */ + *(.eb3rodata) /* read-only data (constants) */ + *(.eb3rodata.*) + } >EXTMEMB3 + + + /* After that there are only debugging sections. */ + + /* This can remove the debugging information from the standard libraries */ + /* + DISCARD : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + */ + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* + * DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. + */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/maidenhead-calc.bas b/maidenhead-calc.bas new file mode 100644 index 0000000..29fd34d --- /dev/null +++ b/maidenhead-calc.bas @@ -0,0 +1,64 @@ +'---- snipped ---- GPS Source OE3HBW +Sub Maidenhead() 'QTH-Locator (extended version with 10 characters) + Call DecimalGrad() + dgLon = dgLon + 180 + dgLat = dgLat + 90 + 'Longitude -------------------------------- + tmps1 = dgLon * 0.05 '/ 20 + tmpb1 = Int(tmps1) + tmpb1 = tmpb1 + 1 + LocStr(1) = Mid(ChrStr , tmpb1 , 1) + tmps2 = Frac(tmps1) + tmps2 = tmps2 * 20.0 + tmps1 = tmps2 * 0.5 '/ 2 + tmpb1 = Int(tmps1) + tmpb1 = tmpb1 + 1 + LocStr(3) = Mid(NumStr , tmpb1 , 1) + tmps2 = Frac(tmps1) + tmps2 = tmps2 * 2.0 + tmps1 = tmps2 * 12 '/ 0.083333333 = 2/24 = 1/12 + tmpb1 = Int(tmps1) + tmpb1 = tmpb1 + 1 + LocStr(5) = Mid(ChrStr , tmpb1 , 1) + tmps2 = Frac(tmps1) + tmps2 = tmps2 * 0.083333333 + tmps1 = tmps2 * 120 '/ 0.008333333 + tmpb1 = Int(tmps1) + tmpb1 = tmpb1 + 1 + LocStr(7) = Mid(NumStr , tmpb1 , 1) + tmps2 = Frac(tmps1) + tmps2 = tmps2 * 0.0083333333 + tmps1 = tmps2 * 2880 '/ 0.000347222 + tmpb1 = Int(tmps1) + tmpb1 = tmpb1 + 1 + LocStr(9) = Mid(ChrStr , tmpb1 , 1) + 'Latitude --------------------------------- + tmps1 = dgLat * 0.1 '/ 10 + tmpb1 = Int(tmps1) + tmpb1 = tmpb1 + 1 + LocStr(2) = Mid(ChrStr , tmpb1 , 1) + tmps2 = Frac(tmps1) + tmps2 = tmps2 * 10.0 + tmps1 = tmps2 / 1.0 + tmpb1 = Int(tmps1) + tmpb1 = tmpb1 + 1 + LocStr(4) = Mid(NumStr , tmpb1 , 1) + tmps2 = Frac(tmps1) + tmps2 = tmps2 * 1.0 + tmps1 = tmps2 * 24 '/ 0.0416666666 + tmpb1 = Int(tmps1) + tmpb1 = tmpb1 + 1 + LocStr(6) = Mid(ChrStr , tmpb1 , 1) + tmps2 = Frac(tmps1) + tmps2 = tmps2 * 0.0416666666 + tmps1 = tmps2 * 240 '/ 0.0041666666 + tmpb1 = Int(tmps1) + tmpb1 = tmpb1 + 1 + LocStr(8) = Mid(NumStr , tmpb1 , 1) + tmps2 = Frac(tmps1) + tmps2 = tmps2 * 0.0041666666 + tmps1 = tmps2 * 5760 + tmpb1 = Int(tmps1) '/ 0.000173611 + tmpb1 = tmpb1 + 1 + LocStr(10) = Mid(ChrStr , tmpb1 , 1) +End Sub \ No newline at end of file diff --git a/src/.si5351a.c.swp b/src/.si5351a.c.swp new file mode 100644 index 0000000000000000000000000000000000000000..87852a2a059fab023a2b24152e30fea207e153f2 GIT binary patch literal 16384 zcmeI2ONU;>j2fa?l_i!05pv27-x+5&zY%=^1xtXU*clR42db znRH?xR*T6UrO2$-G;Eg*Em+P;*VbxG)|}SRob6WX4tvpI z^&w?gkzJ=IyGCKSplZ2VVqbg_3J3*yDX@tQ=T(KL*s*;ZeQ4`5y%LK!p@2|8C?FIN z3J3*+0zv_yfKcFnrhsR!C9k1P15vx`(fyvT`<>`I6otp<0dcy&qWC>g{DrRkYog!x zM)zO4;-jD9CKM0~2nB=!LII(GP(Uak6c7ps1%v`Z0inQMP(afOc@%ap^Nl>-|Hu3P zKQ|L{4O|4DfV1Eb_~QXWeh0U~PvAPZ20j4i!8z~}cpenNHZTCLZ6f3nxBxx^?}K;2 zJD?79Py;hy6g&dff$JLy`39T^Z-O)61#lRQfvsRISOacvAmkRf32uNdz=z-s&;Se! z00Q1yPso1o%OD{?gSWv9SPw4WPsr!s5;y~TtU<)AN4h}`W1ZTmMU;uoLgP11Bf!pYlTi_G)Kn(3ciD_1-5IB*6eUCV?W3c82tN9Flg-WS9rQ$~V zsoJivYHDm7miuedaCgQPwJ9I9DJgfj-KG)VCg*@L--kA8Sc^oOzN@cvXY8nc(xVW4 zoT}{}M(2-HWp6Z4R(!)S3@v17Xqnb6r-m`9nba^nHpd(~uQh$f!>QL`R5#`gojL6a zsk}n@QMxmZqC>Qx=J%2$iEp~boXK?Bw9Gkf7G?EaV?I%W;a;=Mx-mzcXcE9iuLAO` zP(Z#{0qQCgppuu#yk+RrWu9*z@td9zOl>JqjEfZnWoZ(Ys2FucDvBo$1}b+TP_C5p ziQxvlS2et-KNlKCtw9kyQ+ga-W0{^6q|j{JvG7ka&0~qyS&D2(s?i-fs~aXmC(`(T zT@7APnR(Q=Y0!kQyWrelJ{m$%O);wUcAb`Sa(1&By10}xS#~ysnc&{inL1_?jjnE= z8s>y+gY!yeZ_0W7YsVHEhFg7NsQW$tozdYaxvXSt~P)pM1L zn(uU!NYd^Y?(#6jx||^Iq*PEmtSCmqV!`3Kh@56P+TiY#Tu#j@yGFBx-32Nsr>6Lo z;qHzPs-6jW`8n? zio@`*kfK4i(_xxk(KSySmwYHOTJbVrA_Qx-lW{s8=6afwWaI%0j^VM2rt1#cHlk!p z2PY0hc7ycHtC-c(9&;r%6|DK5g|%o$nCn?~Toj%wO(t!Viup-(XkW2h!a@$;EBID9 zHW|;oqM7oX-`@>AcG}=6I=i>|mfh&+x_iV0TZ&stopQ*dmf7UCG4>dNu$%*bVbujK>34utUI( z9ZRfPhk!}zuu z6b;8>MrUr#F{*s^inRk@tfGWq$Ara?MSYj?iRiodmwXT#@3~r*?l&1diA7Gs^XxHM zURYSjH8j(8{Z@-PZmwpvfX|}%Pk9<~ z2?c}#LII(GP(Uak6c7ps1%v`Z0il3U;J;I#{SH%>`H4`a93B|mnJJXcB@Q82SdE{#ZBaw tGqFF@_xqov+K4vs13#Qh1*Z{5`0JnG-HC$tCU^ +#include "i2c.h" + + +void _24aa02_write_dword(I2C_TypeDef * I2Cx, uint8_t addr, uint32_t data) { + + I2Cx->CR1 &= ~I2C_CR1_PE; + i2c_autoend(I2Cx,0); + i2c_set_nbytes(I2Cx,6); + i2c_write_addr(I2Cx,0x50,0); + i2c_tx_buf[0]=(addr); + i2c_tx_buf[1]=(data & 0xff000000)>>24; + i2c_tx_buf[2]=(data & 0xff0000)>>16; + i2c_tx_buf[3]=(data & 0xff00)>>8; + i2c_tx_buf[4]=data & 0xff; + I2Cx->CR1 |= I2C_CR1_PE; + + i2c_start(I2Cx); + while( ! (DMA1->ISR & DMA_ISR_TCIF4) ); + i2c_stop(I2C2); + +} + +uint32_t _24aa02_read_dword(I2C_TypeDef * I2Cx, uint8_t addr) { + uint32_t tmp=0; + I2Cx->CR1 &= ~I2C_CR1_PE; + i2c_autoend(I2Cx,0); + i2c_set_nbytes(I2Cx,1); + i2c_write_addr(I2Cx,0x50,0); + i2c_tx_buf[0]=(addr & 0xff); + I2Cx->CR1 |= I2C_CR1_PE; + i2c_start(I2Cx); + + while( ! (DMA1->ISR & DMA_ISR_TCIF4) ); + + i2c_stop(I2C2); + i2c_autoend(I2Cx,0); + i2c_set_nbytes(I2Cx,4); + i2c_write_addr(I2Cx,0x50,1); + i2c_start(I2Cx); + + while( ! (DMA1->ISR & DMA_ISR_TCIF5) ); + + tmp=i2c_rx_buf[0]<<24; + tmp+=i2c_rx_buf[1]<<16; + tmp+=i2c_rx_buf[2]<<8; + tmp+=i2c_rx_buf[3]; + + i2c_stop(I2C2); + + return tmp; + +} diff --git a/src/_write.c b/src/_write.c new file mode 100644 index 0000000..ba31407 --- /dev/null +++ b/src/_write.c @@ -0,0 +1,72 @@ +/* + * This file is part of the ??OS++ distribution. + * (https://github.com/micro-os-plus) + * Copyright (c) 2014 Liviu Ionescu. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +// Do not include on semihosting and when freestanding +#if !defined(OS_USE_SEMIHOSTING) && !(__STDC_HOSTED__ == 0) + +// ---------------------------------------------------------------------------- + +#include +#include "diag/Trace.h" + +// ---------------------------------------------------------------------------- + +// When using retargetted configurations, the standard write() system call, +// after a long way inside newlib, finally calls this implementation function. + +// Based on the file descriptor, it can send arrays of characters to +// different physical devices. + +// Currently only the output and error file descriptors are tested, +// and the characters are forwarded to the trace device, mainly +// for demonstration purposes. Adjust it for your specific needs. + +// For freestanding applications this file is not used and can be safely +// ignored. + +ssize_t +_write (int fd, const char* buf, size_t nbyte); + +ssize_t +_write (int fd __attribute__((unused)), const char* buf __attribute__((unused)), + size_t nbyte __attribute__((unused))) +{ +#if defined(TRACE) + // STDOUT and STDERR are routed to the trace device + if (fd == 1 || fd == 2) + { + return trace_write (buf, nbyte); + } +#endif // TRACE + + errno = ENOSYS; + return -1; +} + +// ---------------------------------------------------------------------------- + +#endif // !defined(OS_USE_SEMIHOSTING) && !(__STDC_HOSTED__ == 0) diff --git a/src/delay.c b/src/delay.c new file mode 100644 index 0000000..ecd187b --- /dev/null +++ b/src/delay.c @@ -0,0 +1,57 @@ + +#include "delay.h" + +void +timer_tick (void); + +volatile timer_ticks_t timer_delayCount; + +void +delay_init (void) +{ + // Use SysTick as reference for the delay loops. + SysTick_Config (SystemCoreClock / TIMER_FREQUENCY_HZ); +} + +void +timer_sleep (timer_ticks_t ticks) +{ + timer_delayCount = ticks; + + // Busy wait until the SysTick decrements the counter to zero. + while (timer_delayCount != 0u) + ; +} + +void +timer_tick (void) +{ + // Decrement to zero the counter used by the delay routine. + if (timer_delayCount != 0u) + { + --timer_delayCount; + } +} + +void delay_ms(timer_ticks_t ticks) +{ + timer_delayCount = ticks; + + while (timer_delayCount != 0); +} + +/* +void delay_us(timer_ticks_t ticks) +{ + timer_delayCount = ticks; + + while (timer_delayCount != 0); +} +*/ +// ----- SysTick_Handler() ---------------------------------------------------- + +void +SysTick_Handler (void) +{ + timer_tick (); +} diff --git a/src/font_Arial.c b/src/font_Arial.c new file mode 100644 index 0000000..f1b8722 --- /dev/null +++ b/src/font_Arial.c @@ -0,0 +1,12993 @@ +#include "font_Arial.h" + +static const unsigned char Arial_8_data[] = { +0x00,0x00,0x18,0x03,0x00,0x16,0x44,0x06,0x62,0xA4, +0xD0,0x0B,0x00,0x34,0x15,0xF8,0x53,0xF1,0x40,0x0B, +0x27,0xB1,0xCA,0xA8,0x74,0x15,0x53,0x84,0x13,0x00, +0x51,0x89,0x12,0x83,0x40,0x16,0x81,0x48,0x8C,0x0D, +0x00,0x38,0xC8,0x48,0x61,0x44,0x68,0x8E,0x80,0x02, +0x62,0x94,0xC0,0x07,0x47,0x20,0x96,0x42,0x10,0x07, +0x47,0x22,0x16,0x12,0x40,0x06,0x82,0x21,0x39,0x28, +0x0A,0xA0,0xB4,0x11,0xF8,0x20,0x02,0x6F,0x1C,0xC0, +0x06,0x21,0x23,0x80,0x02,0x28,0x1A,0x07,0x00,0x1C, +0x1A,0x51,0x00,0x0B,0x00,0x31,0xD9,0x13,0x80,0x07, +0x00,0x30,0x9A,0xD9,0x0B,0x00,0x31,0xC8,0xC0,0x42, +0x10,0x87,0xC0,0x0B,0x00,0x31,0xC8,0x82,0x34,0x05, +0x13,0x80,0x0B,0x00,0x30,0x43,0x42,0x92,0x7E,0x04, +0x0B,0x00,0x31,0xE4,0x20,0xF4,0x05,0x13,0x80,0x0B, +0x00,0x31,0xC8,0xA0,0xF4,0xC4,0xE0,0x0B,0x00,0x33, +0xF0,0x28,0x24,0xA0,0x0B,0x00,0x31,0xD1,0x13,0xA6, +0x27,0x00,0x0B,0x00,0x31,0xD3,0x13,0xC1,0x44,0xE0, +0x02,0xC0,0x1B,0x44,0x03,0x07,0x1B,0x49,0x80,0x0A, +0xA0,0xB0,0x27,0x20,0x70,0x20,0x0A,0x61,0x33,0xE0, +0x3E,0x0A,0xA0,0xB2,0x07,0x02,0x72,0x00,0x0B,0x00, +0x31,0xC8,0x82,0x14,0x10,0x01,0x00,0x15,0x47,0x58, +0x7C,0x30,0x44,0xD5,0x26,0xC5,0x12,0xA6,0x93,0x61, +0x01,0x1F,0xC0,0x0F,0x00,0x40,0x44,0x94,0x22,0x3E, +0x88,0x20,0x0D,0x00,0x3B,0xE8,0x85,0xFC,0xC2,0xF8, +0x0D,0x00,0x38,0xE2,0x35,0x01,0x11,0xC0,0x0D,0x00, +0x3B,0xC4,0x55,0x0A,0x27,0x80,0x0B,0x00,0x33,0xF1, +0x07,0xE6,0x0F,0x80,0x0B,0x00,0x33,0xF1,0x07,0xAA, +0x00,0x0F,0x00,0x40,0xE1,0x12,0x0A,0x02,0x3A,0x09, +0x10,0xE0,0x0D,0x00,0x3C,0xC2,0xFE,0xA1,0x03,0x00, +0x16,0xD0,0x09,0x00,0x2D,0x8C,0x49,0x80,0x0D,0x00, +0x3A,0x14,0x49,0x16,0x34,0x88,0x90,0x80,0x0B,0x00, +0x36,0xC1,0xF0,0x0F,0x00,0x42,0x0C,0x63,0x9A,0xB1, +0x24,0x0D,0x00,0x3A,0x16,0x31,0x4C,0x4A,0x8D,0x08, +0x0F,0x00,0x40,0xE1,0x15,0x41,0x22,0x1C,0x0B,0x00, +0x33,0xD3,0x17,0xA6,0x00,0x0F,0x00,0x40,0xE1,0x14, +0xC1,0x4D,0x22,0x1F,0x0D,0x00,0x3B,0xE8,0x85,0xF2, +0x48,0x89,0x08,0x0D,0x00,0x39,0xE4,0x28,0x0C,0x06, +0x02,0x84,0xF0,0x0B,0x00,0x33,0xFA,0x40,0x0D,0x00, +0x3E,0xC2,0x78,0x0F,0x00,0x44,0x41,0x84,0x50,0x52, +0x04,0x00,0x17,0x18,0x52,0x10,0xA2,0x8C,0x25,0x28, +0x51,0x50,0x41,0x00,0x0D,0x00,0x3A,0x18,0x4A,0x0C, +0x84,0x90,0x80,0x0F,0x00,0x42,0x0C,0x22,0x14,0xA1, +0x00,0x0D,0x00,0x39,0xF0,0x50,0x24,0x10,0x41,0xF8, +0x05,0x47,0x1B,0xD9,0x30,0x07,0x00,0x1C,0x4A,0x50, +0x40,0x05,0x47,0x1B,0xD4,0xB0,0x0A,0x82,0x28,0x90, +0xA4,0x40,0x0C,0x27,0x33,0xF0,0x04,0x43,0x22,0x20, +0x0A,0xC0,0x31,0xC8,0x9E,0x8A,0x6E,0x80,0x0B,0x00, +0x34,0x41,0x66,0x62,0x2C,0xAC,0x0A,0xC0,0x31,0xC8, +0xC4,0x11,0x38,0x0B,0x00,0x34,0x04,0xD4,0xE2,0x29, +0x9A,0x0A,0xC0,0x31,0xC8,0xBE,0x82,0x27,0x00,0x07, +0x00,0x20,0x93,0xDA,0x0B,0x07,0x31,0xA9,0xC4,0x53, +0x34,0x17,0x80,0x0B,0x00,0x34,0x41,0x66,0x6A,0x20, +0x03,0x00,0x12,0x64,0x05,0x5F,0x11,0x1A,0xA0,0x09, +0x00,0x2C,0x42,0x54,0xC7,0x29,0x20,0x03,0x00,0x16, +0xD0,0x0E,0xC0,0x42,0xF3,0x4D,0x49,0x0A,0xC0,0x33, +0xD7,0x10,0x0A,0xC0,0x31,0xD5,0x13,0x80,0x0B,0x07, +0x32,0xCC,0xC4,0x59,0x5A,0x20,0x0B,0x07,0x31,0xA9, +0xC4,0x53,0x36,0x02,0x06,0xC0,0x22,0xB5,0x40,0x0A, +0xC0,0x31,0xC8,0x98,0x12,0x27,0x00,0x07,0x18,0x1C, +0x27,0xA4,0x60,0x0A,0xC0,0x35,0x45,0x33,0x40,0x0A, +0xC0,0x34,0x46,0x15,0x04,0x12,0xC0,0x52,0x22,0x94, +0xC2,0xAA,0x08,0x80,0x0A,0xC0,0x32,0x25,0x41,0x0A, +0x44,0x0B,0x07,0x34,0x46,0x15,0x24,0x20,0x0A,0xC0, +0x33,0xE1,0x41,0x08,0x7C,0x07,0x47,0x20,0xCA,0x4A, +0x42,0x03,0x47,0x16,0xE6,0x07,0x4F,0x22,0x4A,0x1A, +0x48,0x0A,0x42,0x33,0xAB,0x00,}; +/* font data size: 656 bytes */ + +static const unsigned char Arial_8_index[] = { +0x00,0x00,0x30,0x1C, +0x0B,0x04,0xC1,0xC0,0x9C,0x31,0x0D,0x43,0xB1,0x04, +0x46,0x13,0x05,0x01,0x50,0x57,0x17,0x46,0x31,0xA0, +0x71,0x1E,0x88,0x22,0x2C,0x93,0x26,0x8A,0x22,0xA8, +0xAE,0x2C,0xCB,0xA2,0xFC,0xC6,0x33,0xCD,0xF3,0xA0, +0xF0,0x3E,0x10,0x04,0x21,0x0F,0x46,0x92,0x04,0x91, +0x2A,0x4D,0x13,0x95,0x05,0x4A,0x54,0x95,0x95,0x89, +0x6B,0x5D,0x57,0xA5,0xFD,0x88,0x65,0x19,0xD6,0x95, +0xAE,0x6C,0xDB,0x96,0xF9,0xC4,0x72,0x1C,0xC7,0x51, +0xDC,0x78,0xDE,0xB7,0xCD,0xF8,0x80,0x60,0x88,0x32, +0x11,0x86,0x61,0xD8,0x8E,0x28,0x8B,0xA3,0x68,0xFA, +0x43,0x92,0xE5,0x19,0x5E,0x5D,0x99,0xA6,0xD9,0xD2, +0x7B,0xA0,0x68,0x5A,0x2C, +}; +/* font index size: 119 bytes */ + +const ILI9341_t3_font_t Arial_8 = { + Arial_8_index, + 0, + Arial_8_data, + 1, + 0, + 32, + 126, + 0, + 0, + 10, + 4, + 4, + 2, + 4, + 4, + 11, + 8 +}; + + + +static const unsigned char Arial_9_data[] = { +0x00,0x00,0x08,0x03,0x44,0x07,0xB4,0x40,0x06,0x64, +0xEB,0x34,0x11,0x40,0x0F,0x02,0x42,0x27,0xFC,0x12, +0x3F,0xE5,0x20,0x0B,0x67,0xEE,0x72,0xB1,0x47,0x07, +0x16,0x2A,0x70,0x80,0x15,0x44,0x18,0x61,0x22,0x48, +0x4A,0x06,0x40,0x13,0x02,0x98,0x12,0x44,0x30,0x11, +0x44,0x12,0x30,0x94,0x81,0x81,0x81,0x24,0x8A,0x46, +0x1C,0xC0,0x02,0x64,0xE5,0x30,0x07,0xA7,0xA8,0x30, +0xB6,0x42,0x10,0x07,0xA3,0xA8,0x90,0xB4,0xC2,0x40, +0x0A,0x80,0xCA,0x23,0xE2,0x14,0x0E,0xE4,0x31,0x22, +0x1F,0xE4,0x40,0x02,0x6B,0xC9,0x30,0x06,0x20,0x68, +0xE0,0x02,0x24,0x08,0x80,0x09,0x40,0x09,0x03,0x25, +0x29,0x10,0x0D,0x40,0x0E,0x7B,0x61,0x42,0x78,0x07, +0x44,0x0E,0x26,0xBA,0x40,0x0D,0x40,0x0E,0x79,0x0C, +0x82,0x08,0x20,0x82,0x0F,0xC0,0x0D,0x40,0x0E,0x79, +0x0C,0x02,0x3A,0x41,0x42,0x78,0x0D,0x40,0x0E,0x0A, +0x06,0x82,0xA1,0x27,0xF0,0x10,0x0D,0x40,0x0E,0x7E, +0x10,0x40,0xF9,0x0C,0x02,0x84,0xF0,0x0D,0x40,0x0E, +0x79,0x0C,0x40,0xB9,0x8C,0xC2,0x78,0x0D,0x40,0x0E, +0xFE,0x02,0x81,0x20,0x89,0x40,0x0D,0x40,0x0E,0x7A, +0x61,0x3D,0x50,0x9E,0x0D,0x40,0x0E,0x7A,0x61,0x46, +0x76,0x01,0x44,0x70,0x02,0xE4,0x08,0xD9,0x03,0x27, +0xC8,0xDA,0x60,0x0C,0xE4,0x30,0x04,0x31,0x84,0x06, +0x03,0x01,0x0E,0x80,0x70,0xFF,0x00,0x1F,0xC0,0x0C, +0xE4,0x30,0x80,0xC0,0x60,0x21,0x8C,0x20,0x0B,0x44, +0x0E,0x74,0x44,0x10,0x84,0x84,0x00,0x40,0x19,0xA3, +0xBA,0x0F,0x81,0x82,0x10,0x08,0x9D,0x29,0x19,0x50, +0x4A,0x84,0x54,0x24,0xA3,0x24,0xEE,0x10,0x04,0x40, +0xC1,0xF8,0x13,0x40,0x12,0x08,0x48,0xA2,0x08,0x87, +0xF1,0x05,0x10,0x10,0x0F,0x44,0x12,0xFD,0x30,0x5F, +0xAA,0x0B,0xF0,0x0F,0x44,0x12,0x38,0x44,0x83,0x50, +0x10,0x48,0x87,0x00,0x0F,0x44,0x12,0xF8,0x85,0x90, +0x50,0x9F,0x00,0x0F,0x44,0x12,0xFF,0x30,0x1F,0xEA, +0x03,0xF8,0x0D,0x44,0x10,0xFE,0x60,0x7D,0x70,0x00, +0x11,0x44,0x14,0x3C,0x21,0x20,0x62,0x01,0x1F,0x10, +0x24,0x21,0xE0,0x0F,0x44,0x13,0x50,0x5F,0xEE,0x08, +0x03,0x44,0x07,0xB9,0x80,0x0B,0x40,0x0D,0xA1,0x88, +0x9C,0x11,0x44,0x12,0x81,0x41,0x21,0x11,0x09,0x05, +0x83,0x21,0x08,0x82,0x40,0x80,0x0D,0x44,0x0F,0xB0, +0x44,0x0F,0xC0,0x13,0x44,0x16,0x80,0xC6,0x0E,0x28, +0xB3,0x29,0x88,0x88,0x0F,0x44,0x12,0x82,0xC3,0x14, +0x62,0x4C,0x45,0x43,0x41,0x11,0x44,0x14,0x3C,0x21, +0x64,0x09,0x08,0x78,0x0F,0x44,0x12,0xFD,0x50,0x5F, +0xAA,0x00,0x11,0x47,0xF4,0x3C,0x21,0x5C,0x0A,0x34, +0x84,0x3D,0x0F,0x44,0x12,0xFD,0x50,0x5F,0x91,0x22, +0x12,0x08,0x0F,0x44,0x12,0x7D,0x10,0x50,0x0E,0x01, +0x80,0x62,0x09,0xF0,0x0F,0x40,0x0E,0xFF,0xA2,0x20, +0x40,0x0F,0x44,0x13,0xB0,0x50,0x48,0x87,0x00,0x13, +0x40,0x13,0x10,0x18,0x41,0x41,0x12,0x05,0x10,0x10, +0x1B,0x40,0x1A,0x82,0x0A,0x14,0x32,0x8A,0x29,0x28, +0xA4,0x08,0x20,0x0F,0x40,0x0E,0x83,0x08,0x85,0x20, +0x40,0xA4,0x22,0x41,0x0F,0x44,0x12,0x83,0x08,0xA0, +0xA5,0x88,0x0F,0x40,0x0E,0x7E,0x05,0x01,0x20,0x44, +0x10,0x20,0x7F,0x05,0xA7,0xA8,0xF6,0xA9,0x80,0x09, +0x40,0x09,0x11,0x29,0x25,0x02,0x05,0xA7,0xA8,0xF5, +0xA5,0x80,0x0A,0xA0,0x8A,0x24,0xA9,0x10,0x0E,0x23, +0xAE,0xFE,0x04,0x45,0x08,0x88,0x0A,0xE4,0x0E,0x72, +0x20,0x9E,0x8A,0x66,0x80,0x0B,0x44,0x0F,0x30,0x59, +0x9A,0x8B,0xC0,0x0A,0xE4,0x0E,0x72,0x33,0x04,0x4E, +0x0B,0x44,0x0F,0x21,0x35,0x39,0x8A,0x66,0x80,0x0A, +0xE4,0x0E,0x74,0x45,0xF4,0x11,0x38,0x09,0x40,0x06, +0x38,0x47,0x62,0x00,0x0B,0x47,0xAE,0x6A,0x73,0x14, +0xCD,0x05,0x13,0x80,0x0B,0x44,0x0F,0x30,0x59,0x9B, +0x88,0x03,0x44,0x06,0xC3,0x60,0x07,0xBF,0xA6,0x30, +0x34,0xC1,0x60,0x0B,0x44,0x0F,0x30,0x45,0x25,0x1C, +0x89,0x22,0x03,0x44,0x07,0xB9,0x80,0x12,0xE4,0x16, +0xB3,0x33,0x37,0x11,0x0A,0xE4,0x0E,0xB3,0x37,0x10, +0x0A,0xE4,0x0E,0x75,0xC4,0xE0,0x0B,0x47,0xAE,0xB3, +0x33,0x16,0x56,0x98,0x00,0x0B,0x47,0xAE,0x6A,0x73, +0x14,0xCD,0x90,0x80,0x06,0xE4,0x08,0xAD,0x70,0x0A, +0xE4,0x0E,0x72,0x28,0x1C,0x0A,0x27,0x00,0x07,0x20, +0x09,0x09,0xED,0x18,0x0A,0xE4,0x0F,0x91,0x3C,0x0A, +0xE0,0x0B,0x11,0x95,0x41,0x00,0x12,0xE0,0x13,0x11, +0x19,0x55,0x41,0x10,0x0A,0xE4,0x0E,0x8C,0x28,0x48, +0x52,0x20,0x0B,0x47,0xAF,0x11,0x95,0x51,0x18,0x0A, +0xE4,0x0E,0xFC,0x08,0x48,0x43,0xE0,0x07,0xA3,0xA8, +0x36,0x92,0xD0,0x80,0x03,0x87,0xC7,0xBB,0x80,0x07, +0xA7,0xA8,0x96,0x86,0xD2,0x00,0x0E,0x40,0x90,0x72, +0x9E,}; +/* font data size: 771 bytes */ + +static const unsigned char Arial_9_index[] = { +0x00,0x00,0x30,0x20,0x0C,0x05,0xC2,0x20,0xC4, +0x3E,0x10,0x84,0x91,0x40,0x56,0x17,0x46,0x11,0x94, +0x69,0x1C,0x07,0x71,0xF4,0x88,0x24,0x89,0xC2,0x9C, +0xB1,0x2E,0x8C,0x23,0x30,0xD0,0x35,0x4D,0xE3,0x94, +0xEE,0x3E,0x11,0x04,0x71,0x25,0x4C,0x13,0x95,0x09, +0x4A,0x55,0xD5,0xE5,0x8D,0x69,0x5E,0x17,0xF6,0x29, +0x95,0x67,0x9A,0x66,0xC1,0xBA,0x71,0x9C,0xD7,0x55, +0xE0,0x7B,0x5F,0x88,0x02,0x0B,0x84,0x61,0x88,0x7A, +0x24,0x8A,0x22,0xC8,0xD6,0x3D,0x91,0x24,0xD9,0x56, +0x5C,0x99,0xA6,0xD9,0xCA,0x79,0xA0,0xA8,0x7A,0x3A, +0x94,0xA6,0xAA,0x3A,0xB2,0xB1,0xAE,0xAC,0x0B,0x16, +0xCC,0xB5,0x2D,0xCB,0x8E,0xEB,0xBC,0xAF,0x7B,0xF8, +}; +/* font index size: 119 bytes */ + +const ILI9341_t3_font_t Arial_9 = { + Arial_9_index, + 0, + Arial_9_data, + 1, + 0, + 32, + 126, + 0, + 0, + 10, + 4, + 4, + 3, + 5, + 4, + 13, + 10 +}; + + + +static const unsigned char Arial_10_data[] = { +0x00,0x00,0x08,0x03,0x48,0x0B,0xB4,0x40,0x06,0x84, +0xCB,0x54,0x11,0x40,0x11,0x02,0x42,0x47,0xFC,0x12, +0x3F,0xE5,0x20,0x0F,0x83,0xF0,0x10,0x3C,0x53,0x12, +0x0E,0x03,0xA0,0x4A,0x51,0xE0,0x40,0x15,0x44,0x18, +0x61,0x22,0x48,0x4A,0x06,0x40,0x13,0x02,0x98,0x12, +0x44,0x30,0x11,0x44,0x12,0x38,0x84,0x42,0x40,0xC0, +0xA0,0x8A,0x42,0x21,0x8F,0x20,0x02,0x84,0xC7,0x50, +0x07,0xA7,0xAA,0x30,0xB6,0x42,0x10,0x07,0xA7,0xAA, +0x90,0xB4,0xC2,0x40,0x0A,0x80,0xCA,0x23,0xE2,0x14, +0x0E,0xE4,0x31,0x22,0x1F,0xE4,0x40,0x02,0x6B,0xC9, +0x30,0x08,0x20,0x6A,0xF0,0x02,0x28,0x08,0x80,0x09, +0x40,0x09,0x03,0x25,0x29,0x10,0x0D,0x44,0x10,0x7B, +0x61,0x42,0x78,0x07,0x48,0x10,0x26,0xBA,0x40,0x0D, +0x44,0x10,0x7A,0x21,0x80,0x41,0x04,0x10,0x41,0xF8, +0x0D,0x44,0x10,0x7A,0x21,0x02,0x3A,0x01,0x88,0x4F, +0x00,0x0F,0x40,0x10,0x04,0x0C,0x15,0x04,0x88,0x90, +0x9F,0xE0,0x10,0x0D,0x44,0x10,0x7C,0x82,0x07,0xC8, +0x60,0x14,0x28,0x8F,0x00,0x0D,0x44,0x10,0x38,0x8C, +0x40,0xB9,0x8C,0xC2,0x78,0x0D,0x44,0x10,0xFC,0x0C, +0x05,0x22,0x49,0x00,0x0D,0x44,0x10,0x7A,0x61,0x3D, +0x50,0x9E,0x0D,0x44,0x10,0x7A,0x61,0x46,0x76,0x01, +0x44,0x70,0x03,0x04,0x08,0xE1,0x03,0x47,0xC8,0xE2, +0x60,0x0C,0xE4,0x30,0x04,0x31,0x84,0x06,0x03,0x01, +0x0C,0x84,0x70,0xFE,0x00,0x7E,0x0C,0xE4,0x30,0x80, +0xC0,0x60,0x21,0x8C,0x20,0x0D,0x44,0x10,0x7A,0x21, +0x02,0x08,0x24,0x10,0x00,0x40,0x1B,0xA3,0xBC,0x0F, +0xC0,0xC0,0x84,0x01,0x11,0xD2,0x88,0xCA,0x41,0x29, +0x08,0xA4,0x24,0x91,0x91,0x3B,0x84,0x00,0x8C,0x0C, +0x0F,0xC0,0x13,0x40,0x12,0x08,0x48,0xA2,0x08,0x87, +0xF1,0x05,0x10,0x10,0x0F,0x44,0x12,0xFD,0x30,0x5F, +0xAA,0x0B,0xF0,0x11,0x44,0x14,0x3C,0x21,0x20,0x6A, +0x01,0x02,0x42,0x1E,0x00,0x11,0x44,0x14,0xFC,0x41, +0x64,0x0A,0x09,0xF8,0x0F,0x44,0x12,0xFF,0x30,0x1F, +0xEA,0x03,0xF8,0x0F,0x44,0x12,0xFF,0x30,0x1F,0xAE, +0x00,0x13,0x44,0x16,0x3E,0x10,0x48,0x0C,0x40,0x10, +0xF8,0x80,0x90,0x43,0xE0,0x0F,0x44,0x13,0x50,0x5F, +0xEE,0x08,0x03,0x44,0x07,0xB9,0x80,0x0B,0x40,0x0D, +0xA1,0x88,0x9C,0x11,0x44,0x12,0x81,0x41,0x21,0x11, +0x09,0x05,0x43,0x11,0x08,0x82,0x40,0x80,0x0F,0x44, +0x11,0xB0,0x22,0x03,0xF8,0x13,0x44,0x16,0x80,0xC6, +0x0E,0x28,0xB3,0x29,0x88,0x88,0x0F,0x44,0x12,0x82, +0xC3,0x14,0x62,0x4C,0x45,0x43,0x41,0x13,0x44,0x16, +0x3E,0x10,0x59,0x01,0x20,0x87,0xC0,0x0F,0x44,0x12, +0xFD,0x50,0x5F,0xAA,0x00,0x13,0x47,0xF6,0x3E,0x10, +0x57,0x01,0x42,0x88,0x61,0xEC,0x11,0x44,0x14,0xFE, +0xA8,0x17,0xF2,0x21,0x08,0x82,0x40,0x80,0x0F,0x44, +0x12,0x7D,0x10,0x50,0x0E,0x01,0xC0,0x62,0x09,0xF0, +0x0F,0x44,0x12,0xFF,0xA2,0x20,0x40,0x0F,0x44,0x13, +0xB0,0x50,0x48,0x87,0x00,0x13,0x40,0x13,0x10,0x18, +0x41,0x41,0x12,0x05,0x10,0x10,0x1B,0x40,0x1A,0x82, +0x0A,0x14,0x32,0x8A,0x29,0x28,0xA4,0x08,0x20,0x11, +0x40,0x10,0x81,0x84,0x21,0x24,0x0C,0x09,0x21,0x09, +0x02,0x13,0x40,0x12,0x80,0x90,0x50,0x44,0x0A,0x2C, +0x20,0x11,0x40,0x10,0x7F,0x01,0x40,0x20,0x20,0x21, +0x04,0x04,0x07,0xF8,0x05,0xA7,0xA8,0xF6,0xA9,0x80, +0x09,0x40,0x09,0x11,0x29,0x25,0x02,0x05,0xA7,0xA8, +0xF5,0xA5,0x80,0x0A,0xA0,0xAA,0x24,0xA9,0x10,0x10, +0x23,0xB0,0xFF,0x04,0x45,0x0A,0x88,0x0D,0x04,0x10, +0x79,0x08,0x11,0xE4,0x50,0xA3,0x3A,0x0D,0x44,0x11, +0x10,0x2E,0x63,0x50,0xB1,0x5C,0x0B,0x04,0x0E,0x72, +0x35,0x04,0x4E,0x0D,0x44,0x11,0x00,0x9D,0x47,0x50, +0xA3,0x3A,0x0D,0x04,0x10,0x7A,0x21,0x7F,0x10,0x21, +0x3C,0x09,0x40,0x08,0x32,0x3F,0x50,0x0D,0x67,0xB0, +0x75,0x1D,0x42,0x8C,0xE8,0x14,0x27,0x80,0x0D,0x44, +0x11,0x10,0x2E,0x63,0x90,0x80,0x03,0x44,0x06,0x9B, +0x40,0x07,0xBF,0xA6,0x21,0xA6,0x4B,0x00,0x0D,0x44, +0x0F,0x10,0x21,0x44,0x91,0x43,0x48,0x89,0x08,0x03, +0x44,0x07,0xB9,0x80,0x13,0x04,0x16,0xB7,0x33,0x39, +0x11,0x0D,0x04,0x10,0xB9,0x8E,0x42,0x0D,0x04,0x10, +0x7B,0x21,0x3C,0x0D,0x67,0xB0,0xB9,0x8D,0x42,0xC5, +0x74,0xC0,0x0D,0x67,0xB0,0x75,0x1D,0x42,0x8C,0xEC, +0x82,0x09,0x04,0x0A,0xB6,0x64,0x00,0x0B,0x04,0x0E, +0x72,0x28,0x1D,0x01,0x44,0xE0,0x09,0x40,0x29,0x08, +0xFC,0x43,0x80,0x0D,0x04,0x11,0x90,0xA3,0x3A,0x0F, +0x00,0x0F,0x10,0x61,0x14,0x14,0x81,0x00,0x13,0x00, +0x13,0x11,0x1A,0x55,0x41,0x10,0x0D,0x00,0x0C,0x86, +0x12,0x83,0x21,0x24,0x20,0x0F,0x63,0xAF,0x10,0x61, +0x14,0x94,0x91,0x06,0x00,0x0D,0x00,0x0C,0xFC,0x14, +0x09,0x04,0x10,0x7E,0x07,0xA7,0xAA,0x36,0x92,0xD0, +0x80,0x03,0xA7,0xA7,0xBC,0x80,0x07,0xA7,0xAA,0x96, +0x86,0xD2,0x00,0x0E,0x40,0x90,0x72,0x9E,}; +/* font data size: 808 bytes */ + +static const unsigned char Arial_10_index[] = { +0x00,0x00, +0x30,0x20,0x0C,0x05,0xC2,0x50,0xD0,0x42,0x11,0x84, +0xD1,0x50,0x5A,0x18,0x46,0x51,0xA4,0x6D,0x1D,0x07, +0xB2,0x04,0x8C,0x25,0xCA,0x32,0xBC,0xB9,0x30,0x8C, +0xA3,0x50,0xD8,0x37,0x4E,0x63,0xB0,0xF5,0x40,0x11, +0xA4,0x99,0x2F,0x4E,0xD4,0x45,0x35,0x55,0x58,0xD6, +0xA5,0xBD,0x75,0x61,0x18,0xB6,0x59,0xA1,0x6A,0xDB, +0x36,0xF9,0xCA,0x75,0x9D,0xD7,0x95,0xF0,0x7F,0x60, +0x98,0x4E,0x20,0x89,0xA2,0xD8,0xCE,0x39,0x8F,0x64, +0x19,0x2E,0x54,0x96,0xE6,0x49,0xB6,0x73,0x9F,0xA8, +0x6A,0x2E,0x92,0xA7,0x6A,0x2A,0xA6,0xAF,0xAD,0x6B, +0xEB,0x1E,0xCD,0xB5,0xAD,0xDB,0x8E,0xEC,0xBD,0x2F, +0xDC,0x1F,0x10,0xC5,0xF1,0xCC,0x8C, +}; +/* font index size: 119 bytes */ + +const ILI9341_t3_font_t Arial_10 = { + Arial_10_index, + 0, + Arial_10_data, + 1, + 0, + 32, + 126, + 0, + 0, + 10, + 4, + 4, + 3, + 5, + 4, + 14, + 10 +}; + + + +static const unsigned char Arial_11_data[] = { +0x00,0x00,0x08,0x03,0x68,0x0B,0xB8,0x88,0x06,0x84, +0xEB,0x54,0x11,0x60,0x11,0x22,0x4F,0xF9,0x24,0x7F, +0xCA,0x40,0x0F,0xA3,0xF0,0x10,0x3C,0x56,0x92,0x90, +0x50,0x38,0x14,0x12,0x92,0x54,0x38,0x10,0x17,0x64, +0x1A,0x60,0x91,0x22,0x22,0x48,0x19,0x34,0x04,0x98, +0x11,0x22,0x0C,0x13,0x64,0x14,0x38,0x4A,0x20,0x50, +0x38,0x22,0x24,0x86,0x21,0x47,0x98,0x02,0x84,0xE7, +0x50,0x07,0xC7,0xAA,0x30,0xB6,0x34,0x21,0x07,0xC7, +0xAA,0x90,0xB4,0xCA,0x40,0x0A,0xA0,0xCC,0x23,0xE2, +0x42,0x80,0x0E,0xE4,0x53,0x22,0x1F,0xE4,0x40,0x02, +0x6B,0xA9,0x30,0x08,0x20,0x6A,0xF0,0x02,0x28,0x08, +0x80,0x09,0x60,0x09,0x03,0x25,0x49,0x10,0x0D,0x64, +0x10,0x7B,0x61,0x88,0x4F,0x00,0x07,0x68,0x10,0x26, +0xBA,0x44,0x0D,0x64,0x10,0x7A,0x21,0x80,0x60,0x20, +0x82,0x08,0x3F,0x0D,0x64,0x10,0x7A,0x21,0x80,0x47, +0x40,0x31,0x09,0xE0,0x0F,0x60,0x10,0x04,0x0C,0x15, +0x04,0x88,0x90,0x9F,0xE4,0x10,0x0D,0x64,0x10,0x7E, +0x10,0x40,0xF9,0x0C,0x02,0x85,0x11,0xE0,0x0D,0x64, +0x10,0x7A,0x21,0x40,0xB9,0x8D,0x42,0x78,0x0D,0x64, +0x10,0xFC,0x0C,0x05,0x22,0x51,0x00,0x0D,0x64,0x10, +0x7A,0xA1,0x3D,0x50,0x9E,0x0D,0x64,0x10,0x7A,0xA1, +0x46,0x74,0x0C,0x42,0x78,0x03,0x04,0x08,0xE1,0x03, +0x47,0xA8,0xE2,0x60,0x0E,0xE4,0x52,0x02,0x1C,0x60, +0x80,0x60,0x1C,0x02,0x0E,0xA4,0x72,0xFF,0x20,0x1F, +0xC0,0x0E,0xE4,0x52,0x80,0x70,0x0C,0x02,0x0C,0x70, +0x80,0x0D,0x64,0x10,0x7A,0x21,0x02,0x08,0x24,0x90, +0x00,0x40,0x1D,0xC3,0xBE,0x07,0xC0,0x30,0x60,0x80, +0x22,0x1D,0x64,0xC6,0x51,0x04,0xC4,0x82,0x29,0x04, +0x91,0x19,0x13,0xDC,0x20,0x02,0x30,0x18,0x1F,0xC0, +0x13,0x60,0x12,0x08,0x48,0xA2,0x08,0x84,0x11,0xFC, +0x41,0x44,0x04,0x11,0x64,0x14,0xFE,0x98,0x14,0x13, +0xFA,0xA0,0x5F,0xC0,0x13,0x64,0x16,0x1E,0x18,0x44, +0x0D,0xC0,0x08,0x13,0x08,0x3C,0x13,0x64,0x16,0xFE, +0x20,0x5B,0x01,0x40,0x9F,0xC0,0x11,0x64,0x14,0xFF, +0xA8,0x07,0xFD,0x40,0x3F,0xC0,0x0F,0x64,0x12,0xFF, +0x50,0x1F,0xAE,0x00,0x13,0x64,0x16,0x3E,0x10,0x48, +0x0C,0x40,0x10,0xF9,0x80,0x90,0x43,0xE0,0x11,0x64, +0x15,0x70,0x2F,0xFB,0x81,0x03,0x64,0x07,0xBA,0x80, +0x0D,0x60,0x0F,0xA0,0x81,0x88,0x4F,0x00,0x13,0x64, +0x14,0x81,0x20,0x88,0x42,0x20,0x90,0x2A,0x0C,0x42, +0x10,0x82,0x20,0x48,0x08,0x0F,0x64,0x11,0xB0,0x26, +0x03,0xF8,0x13,0x64,0x16,0x80,0xC6,0x0E,0x68,0xB3, +0x29,0x88,0x88,0x11,0x64,0x14,0x81,0x60,0xC5,0x0C, +0x48,0xA2,0x62,0x15,0x06,0x81,0x15,0x64,0x18,0x1E, +0x0C,0x31,0x02,0xB8,0x04,0x81,0x18,0x60,0xF0,0x11, +0x64,0x14,0xFE,0xA8,0x17,0xF5,0xC0,0x00,0x15,0x67, +0xF8,0x1E,0x0C,0x31,0x02,0xB8,0x04,0x8D,0x18,0x60, +0xF2,0x13,0x64,0x16,0xFF,0x54,0x05,0xFE,0x42,0x22, +0x08,0x81,0x20,0x20,0x11,0x64,0x14,0x3C,0x21,0x20, +0x50,0x0F,0x00,0x74,0x00,0xA0,0x58,0x43,0xC0,0x13, +0x60,0x12,0xFF,0xE8,0x42,0x42,0x00,0x11,0x64,0x15, +0xB0,0x31,0x02,0x42,0x1E,0x00,0x13,0x60,0x13,0x10, +0x18,0x41,0x49,0x12,0x05,0x10,0x10,0x1F,0x60,0x1E, +0x81,0x02,0x82,0x83,0x08,0x50,0xA1,0x11,0x10,0x91, +0x24,0x14,0x14,0x81,0x01,0x00,0x13,0x60,0x12,0x80, +0x90,0x50,0x44,0x0A,0x01,0x80,0xA2,0x08,0x84,0x12, +0x02,0x13,0x60,0x12,0x80,0x90,0x50,0x44,0x0A,0x30, +0x20,0x11,0x60,0x10,0x7F,0x01,0x40,0x20,0x22,0x04, +0x20,0x80,0x80,0xFF,0x07,0xC7,0xA8,0xFB,0x2E,0x38, +0x09,0x60,0x09,0x11,0x29,0x45,0x02,0x07,0xC3,0xA8, +0xFA,0x6C,0xB8,0x0A,0xC0,0xAA,0x24,0xAA,0x22,0x10, +0x23,0xB0,0xFF,0x04,0x45,0x2A,0x88,0x0D,0x04,0x10, +0x79,0x08,0x11,0xE4,0x50,0xA3,0x3A,0x0D,0x64,0x11, +0x30,0x2E,0x63,0x50,0xB1,0x5C,0x0D,0x04,0x10,0x79, +0x0D,0x40,0x84,0xF0,0x0D,0x64,0x11,0x20,0x9D,0x47, +0x50,0xA3,0x3A,0x0D,0x04,0x10,0x7A,0x21,0x7F,0x10, +0x21,0x3C,0x09,0x60,0x08,0x38,0x47,0xEA,0x00,0x0D, +0x67,0xB0,0x75,0x1D,0x42,0x8C,0xE8,0x14,0x27,0x80, +0x0D,0x64,0x11,0x30,0x2E,0x63,0x90,0x80,0x03,0x64, +0x06,0xC3,0x68,0x07,0xDF,0xA6,0x30,0x34,0xC9,0x60, +0x0D,0x64,0x0F,0x30,0x21,0x44,0x91,0x43,0x48,0x89, +0x08,0x03,0x64,0x07,0xBA,0x80,0x17,0x04,0x1A,0xB9, +0xCC,0x63,0x90,0x84,0x0D,0x04,0x10,0xB9,0x8E,0x42, +0x0D,0x04,0x10,0x7B,0x21,0x3C,0x0D,0x67,0xB0,0xB9, +0x8D,0x42,0xC5,0x74,0xC0,0x0D,0x67,0xB0,0x75,0x1D, +0x42,0x8C,0xEC,0x82,0x09,0x04,0x0A,0xB6,0x64,0x00, +0x0D,0x04,0x10,0x79,0x0A,0x03,0x01,0x80,0xA1,0x3C, +0x09,0x40,0x29,0x08,0xFC,0x43,0x80,0x0D,0x04,0x11, +0x90,0xA3,0x3A,0x0F,0x00,0x0F,0x10,0x61,0x14,0x14, +0x81,0x00,0x17,0x00,0x16,0x84,0x28,0xA3,0x09,0x4A, +0x14,0x54,0x10,0x40,0x0F,0x00,0x0E,0x82,0x44,0x29, +0x02,0x05,0x08,0x90,0x40,0x0F,0x63,0xAF,0x10,0x61, +0x14,0x94,0x91,0x06,0x00,0x0D,0x04,0x10,0xFC,0x14, +0x09,0x04,0x10,0x7E,0x0B,0xC3,0xAA,0x1E,0x11,0x8B, +0x20,0x60,0x03,0xC7,0xA7,0xBD,0x80,0x0B,0xC3,0xAA, +0xC6,0x10,0x3B,0x23,0x00,0x10,0x40,0x92,0x71,0x47, +0x00,}; +/* font data size: 861 bytes */ + +static const unsigned char Arial_11_index[] = { +0x00,0x00,0x30,0x20,0x0C,0x05,0x82,0x60,0xD4, +0x43,0x11,0xC4,0xE1,0x54,0x5C,0x18,0xC6,0x71,0xAC, +0x6F,0x1D,0x87,0xE2,0x10,0x8F,0x26,0x8A,0x62,0xC8, +0xBC,0x31,0x4C,0xD3,0x5C,0xDB,0x38,0x0E,0xA3,0xC4, +0xFB,0x41,0x92,0x24,0xBD,0x3A,0x51,0x95,0x05,0x69, +0x62,0x5C,0x17,0x75,0xF1,0x84,0x65,0x59,0xC6,0x9D, +0xB4,0x70,0x5C,0xA7,0x5D,0xE4,0x7C,0xDF,0xB8,0x12, +0x0F,0x88,0xA3,0x18,0xEE,0x48,0x93,0xA5,0x59,0x6E, +0x61,0x99,0x66,0x99,0xCE,0x7C,0xA1,0x28,0xDA,0x5A, +0x9D,0xAA,0x2B,0x0A,0xD6,0xBC,0xB1,0xEC,0xCB,0x52, +0xDA,0xB8,0x2E,0x9B,0xCA,0xF8,0xC0,0xB0,0x9C,0x3F, +0x18,0xC9,0x32,0xFC,0xE7,0x42,0xD2,0xB4,0xFD,0x5C, +}; +/* font index size: 119 bytes */ + +const ILI9341_t3_font_t Arial_11 = { + Arial_11_index, + 0, + Arial_11_data, + 1, + 0, + 32, + 126, + 0, + 0, + 10, + 4, + 4, + 3, + 5, + 4, + 16, + 11 +}; + + + +static const unsigned char Arial_12_data[] = { +0x00,0x00,0x01,0x40,0x01,0x62,0x01,0x77,0x31,0x04, +0x21,0x41,0xAA,0x40,0x09,0x60,0x02,0x60,0x25,0x02, +0x47,0xFC,0x24,0x82,0x43,0xFE,0x24,0x42,0x40,0x07, +0x79,0xF2,0x42,0x07,0x8A,0xD2,0x62,0x41,0xC0,0x70, +0x4C,0x49,0x2A,0x1C,0x81,0x00,0x0D,0x61,0x03,0xCE, +0x08,0x88,0x88,0x44,0x48,0x11,0x4E,0x39,0x44,0x09, +0x18,0x08,0x88,0x42,0x21,0x07,0x00,0x09,0x61,0x02, +0xC3,0x89,0x22,0x05,0x03,0x81,0x20,0x84,0xA1,0x48, +0x21,0x0C,0x3C,0x80,0x01,0x21,0x40,0xEA,0x03,0x79, +0xE9,0x86,0x56,0xC9,0x42,0x03,0x7A,0xE9,0x92,0x56, +0x99,0x48,0x05,0x29,0x39,0xC4,0x7C,0x48,0x50,0x07, +0x39,0x1A,0xA4,0x43,0xFC,0x88,0x01,0x1A,0xE9,0x66, +0x05,0x08,0x21,0x9F,0x01,0x0A,0x01,0x50,0x05,0x60, +0x01,0x41,0x91,0x49,0x25,0x11,0x00,0x07,0x61,0x02, +0x47,0x08,0xB6,0x0A,0x09,0x10,0xE0,0x04,0x62,0x02, +0x42,0x32,0xA7,0x44,0x20,0x07,0x61,0x02,0x47,0x88, +0x90,0x60,0x0C,0x02,0x04,0x08,0x10,0x20,0x7F,0x07, +0x61,0x02,0x47,0x08,0x90,0x80,0x81,0x07,0x00,0xA0, +0x0A,0x0B,0x10,0xE0,0x08,0x60,0x02,0x40,0x80,0xC8, +0x14,0x82,0x42,0x22,0x11,0xFF,0x20,0x80,0x07,0x61, +0x02,0x4F,0xE1,0x02,0x03,0xE2,0x14,0x81,0x41,0x22, +0x1C,0x07,0x61,0x02,0x47,0x08,0xD0,0x50,0x17,0x18, +0xAA,0x09,0x10,0xE0,0x07,0x61,0x02,0x5F,0xE0,0x14, +0x04,0x91,0x14,0x40,0x07,0x61,0x02,0x47,0x08,0xA2, +0x09,0x10,0xE1,0x14,0xC1,0x22,0x1C,0x07,0x61,0x02, +0x47,0x08,0xAA,0x09,0x18,0xE8,0x0A,0x09,0x11,0xE0, +0x01,0x4A,0x01,0x5D,0x20,0x01,0x5A,0xE9,0x5D,0x4C, +0x08,0x49,0x12,0x80,0x20,0x60,0xC1,0x81,0x00,0x60, +0x0C,0x01,0x80,0x20,0x08,0x29,0x1A,0x9F,0xF2,0x00, +0xFF,0x08,0x49,0x12,0x90,0x06,0x00,0xC0,0x18,0x02, +0x06,0x0C,0x18,0x10,0x00,0x07,0x61,0x02,0x47,0x08, +0xA2,0x08,0x08,0x10,0x24,0x88,0x00,0x08,0x10,0x81, +0xE4,0x40,0xFE,0x01,0x80,0xC1,0x00,0x11,0x0E,0x48, +0x88,0xE2,0x48,0x21,0x89,0x02,0x14,0x82,0x0A,0x41, +0x09,0x11,0x88,0x47,0x78,0x20,0x00,0x88,0x00,0x83, +0x01,0x80,0x7F,0x00,0x0B,0x60,0x02,0xC0,0x82,0x02, +0x84,0x88,0x81,0x04,0x1F,0xC8,0x40,0x51,0x00,0x40, +0x09,0x61,0x02,0xDF,0xC4,0x0A,0x20,0x28,0x13,0xFC, +0x81,0x4C,0x05,0x02,0x7F,0x00,0x0A,0x61,0x03,0x03, +0xE0,0x82,0x20,0x39,0x00,0x10,0x11,0x04,0x1F,0x00, +0x0A,0x61,0x03,0x1F,0xC2,0x04,0x40,0x59,0x00,0xA0, +0x24,0x08,0xFE,0x00,0x09,0x61,0x02,0xDF,0xFA,0x80, +0x3F,0xD7,0x00,0x7F,0xC0,0x08,0x61,0x02,0x9F,0xF5, +0x00,0xFE,0xC8,0x00,0x0A,0x61,0x03,0x03,0xC0,0x84, +0x20,0x53,0x00,0x21,0xF8,0x80,0x48,0x10,0x84,0x0F, +0x00,0x09,0x61,0x02,0xEE,0x02,0xFF,0xE4,0x04,0x01, +0x62,0x01,0x77,0x70,0x07,0x61,0x02,0x74,0x08,0x0C, +0x41,0x22,0x3C,0x09,0x61,0x02,0xD0,0x14,0x09,0x04, +0x42,0x11,0x04,0xC1,0x48,0x61,0x10,0x48,0x81,0x20, +0x20,0x07,0x61,0x02,0x76,0x05,0x40,0x7F,0x0B,0x61, +0x03,0x50,0x06,0x30,0x1C,0x50,0x58,0x91,0x29,0x23, +0x11,0x46,0x21,0x08,0x09,0x61,0x02,0xD0,0x16,0x06, +0x28,0x29,0x0C,0x44,0x50,0x98,0x82,0xA0,0x68,0x08, +0x0A,0x61,0x03,0x03,0xC0,0x84,0x20,0x59,0x00,0x90, +0x21,0x08,0x1E,0x00,0x09,0x61,0x02,0xDF,0xC4,0x0A, +0x60,0x28,0x13,0xF9,0x70,0x00,0x0A,0x61,0x03,0x03, +0xC0,0x84,0x20,0x59,0x00,0x91,0xB1,0x0C,0x1E,0xC0, +0x09,0x61,0x02,0xDF,0xC4,0x0A,0x60,0x28,0x13,0xF8, +0x84,0x44,0x11,0x02,0x40,0x40,0x09,0x61,0x02,0xC7, +0xC2,0x09,0x01,0x40,0x08,0x01,0xC0,0x0E,0x00,0x62, +0x02,0x41,0x0F,0x80,0x09,0x60,0x02,0x5F,0xFD,0x08, +0x50,0x40,0x09,0x61,0x02,0xF6,0x03,0x30,0x12,0x08, +0x7C,0x09,0x61,0x02,0xE2,0x03,0x28,0x29,0x22,0x40, +0xA2,0x02,0x00,0x11,0x60,0x04,0x50,0x10,0x14,0x0A, +0x0A,0x10,0x50,0x44,0x22,0x24,0x11,0x11,0x04,0x82, +0x88,0x14,0x14,0x40,0x40,0x40,0x0B,0x60,0x02,0xC8, +0x08,0x41,0x20,0x44,0x02,0x80,0x10,0x02,0x84,0x08, +0x81,0x04,0x20,0x24,0x01,0x09,0x61,0x02,0xD0,0x18, +0x41,0x08,0x90,0x28,0xC0,0x80,0x09,0x60,0x02,0x4F, +0xF0,0x0A,0x00,0x80,0x44,0x04,0x02,0x08,0x20,0x10, +0x0F,0xF8,0x03,0x79,0xE9,0x5F,0x66,0x47,0x05,0x60, +0x01,0x50,0x94,0x49,0x24,0x50,0x10,0x03,0x79,0xE9, +0x5F,0x4E,0x17,0x07,0x38,0x29,0xC2,0x20,0xA4,0xA2, +0x41,0x09,0x08,0xEA,0x5F,0xF0,0x02,0x11,0x51,0x91, +0x07,0x49,0x02,0x47,0x88,0x50,0x41,0xCE,0x62,0x0A, +0x19,0xE8,0x07,0x61,0x02,0x66,0x02,0xE3,0x15,0xC1, +0x62,0x5C,0x07,0x49,0x02,0x47,0x08,0x90,0x66,0x02, +0x09,0x10,0xE0,0x07,0x61,0x02,0x64,0x08,0xE9,0x1D, +0xC1,0x23,0x1D,0x07,0x49,0x02,0x47,0x08,0xA2,0x0B, +0xFA,0x02,0x09,0x10,0xE0,0x04,0x61,0x01,0x47,0x08, +0xFD,0x42,0x00,0x07,0x61,0xEA,0x47,0x48,0xEE,0x09, +0x18,0xE8,0x0A,0x11,0xE0,0x07,0x61,0x02,0x66,0x02, +0xF3,0x0E,0xC1,0x01,0x61,0x01,0x18,0x6E,0x20,0x03, +0x7F,0xE8,0xC6,0x06,0x9A,0x2C,0x07,0x61,0x02,0x26, +0x02,0x0A,0x12,0x22,0x42,0xC3,0x24,0x42,0x41,0x01, +0x61,0x00,0xF7,0x70,0x0B,0x49,0x03,0x57,0x39,0x8C, +0x76,0x10,0x80,0x07,0x49,0x02,0x57,0x98,0x76,0x08, +0x07,0x49,0x02,0x47,0x08,0xAE,0x09,0x10,0xE0,0x07, +0x61,0xEA,0x57,0x18,0xAE,0x0B,0x12,0xE4,0xC0,0x07, +0x61,0xEA,0x47,0x48,0xEE,0x09,0x18,0xEC,0x81,0x05, +0x49,0x01,0x97,0x63,0x60,0x06,0x49,0x02,0x0F,0x21, +0x88,0x0F,0x40,0x28,0x4F,0x00,0x04,0x60,0x01,0x25, +0x1F,0xA8,0x70,0x07,0x49,0x02,0x76,0x0A,0x19,0xE8, +0x07,0x48,0x01,0xE2,0x0C,0xA2,0x82,0x90,0x20,0x0B, +0x48,0x02,0xE2,0x10,0xC2,0x52,0x95,0x15,0x04,0x10, +0x07,0x48,0x01,0xD0,0x48,0xA0,0xA0,0x44,0x14,0x22, +0x41,0x07,0x61,0xEA,0x66,0x0C,0xA2,0x82,0x90,0x20, +0x41,0x80,0x07,0x48,0x02,0x1F,0xC0,0xA0,0x20,0x40, +0x84,0x20,0x7F,0x05,0x79,0xE9,0x83,0xC2,0x31,0x84, +0x0C,0x01,0x82,0xE1,0x77,0xB8,0x80,0x05,0x78,0xE9, +0x98,0xC2,0x07,0x84,0x60,0x09,0x10,0x2A,0x8F,0x14, +0x78,}; +/* font data size: 1011 bytes */ + +static const unsigned char Arial_12_index[] = { +0x00,0x00,0x40,0x24,0x0E,0x07,0x42,0xE1,0x0C, +0x54,0x16,0x05,0xF1,0x98,0x6D,0x1D,0x07,0x81,0xF0, +0x80,0x22,0x49,0x32,0x6C,0xA9,0x2E,0x0C,0x63,0x4C, +0xE0,0x3A,0x8F,0x74,0x11,0x09,0x43,0x91,0xC4,0x8D, +0x31,0x4F,0x96,0x25,0xC9,0x82,0x64,0x19,0xE6,0xA5, +0xB2,0x70,0xDC,0xB7,0x41,0xD9,0x7A,0xDF,0x28,0x0A, +0x12,0x88,0x22,0xC8,0xEA,0x4A,0x97,0x26,0x49,0xB6, +0x79,0xA4,0x2A,0x3A,0xBA,0xBE,0xB1,0x2C,0xDB,0x4E, +0xDB,0xB8,0x2E,0x4B,0xC2,0xFA,0xC1,0x70,0xFC,0x6F, +0x23,0xCB,0xF3,0x7C,0xF7,0x44,0xD4,0x75,0x6D,0x7F, +0x66,0xDB,0xF7,0x9E,0x0F,0x89,0xE5,0x39,0xBE,0x8B, +0xAB,0xED,0xBC,0x1F,0x33,0xD7,0xF7,0xFE,0x5F,0xB4, +}; +/* font index size: 119 bytes */ + +const ILI9341_t3_font_t Arial_12 = { + Arial_12_index, + 0, + Arial_12_data, + 1, + 0, + 32, + 126, + 0, + 0, + 10, + 5, + 5, + 3, + 5, + 5, + 18, + 12 +}; + + + +static const unsigned char Arial_13_data[] = { +0x00,0x00,0x01,0x40,0x02,0x6A,0x01,0xB7,0x9C,0x46, +0x05,0x29,0x41,0xAF,0x60,0x0B,0x68,0x02,0xA0,0x33, +0x06,0x64,0x7F,0xF0,0xCC,0x1D,0xC1,0x98,0x8F,0xFE, +0x33,0x10,0xCC,0x00,0x09,0x81,0xF2,0x81,0x01,0xF0, +0xFE,0x64,0xD9,0x07,0x40,0xF8,0x0F,0x81,0xF0,0x4D, +0x93,0x75,0xCF,0xE1,0xF2,0x02,0x00,0x0E,0x69,0x04, +0x0F,0x0C,0x46,0x66,0x11,0x9B,0x03,0x3E,0x03,0xDB, +0xC0,0x3C,0xE0,0x1B,0x38,0x0C,0xCC,0x30,0xF0,0x0B, +0x69,0x03,0x03,0xC0,0x7E,0x20,0xCC,0x0D,0x80,0x70, +0x1F,0x01,0xB3,0x31,0xB3,0x0E,0x38,0xE1,0xFF,0x0F, +0x18,0x02,0x28,0x40,0xEF,0x05,0x89,0xE1,0x81,0x08, +0x48,0x66,0xE2,0x18,0x20,0x40,0x80,0x05,0x88,0xE1, +0x90,0x20,0x48,0x36,0x8E,0x0C,0x21,0x08,0x00,0x05, +0x29,0x41,0xC4,0x7C,0x48,0x50,0x0A,0x51,0x0A,0xE8, +0x30,0x8F,0xFE,0x83,0x00,0x02,0x22,0xF1,0x63,0x28, +0x05,0x10,0x21,0xA3,0xE0,0x02,0x12,0x01,0x63,0x06, +0x68,0x01,0x60,0x39,0x1A,0x4C,0x96,0x23,0x00,0x08, +0x69,0x02,0x87,0x87,0xE7,0x3E,0xE1,0xB9,0xCF,0xC3, +0xC0,0x05,0x6A,0x02,0x83,0x1C,0xF6,0xD3,0xD1,0x86, +0x08,0x69,0x02,0x87,0x87,0xE7,0x3B,0x0E,0x00,0xC0, +0xC0,0xC0,0xC1,0xC0,0xC1,0x1F,0xE0,0x08,0x69,0x02, +0x87,0x07,0xC6,0x34,0x03,0x07,0x03,0xD0,0x07,0x18, +0x67,0xE1,0xE0,0x09,0x68,0x02,0x80,0xC8,0x0E,0x07, +0x90,0x6C,0x33,0x18,0xC8,0xFF,0xC8,0x30,0x08,0x69, +0x02,0xA1,0xF8,0xC0,0xC0,0x6E,0x3F,0x98,0x70,0x07, +0x18,0x67,0xE1,0xE0,0x08,0x69,0x02,0x87,0x87,0xE3, +0x1C,0x60,0x37,0x1F,0xCE,0x38,0xC3,0x31,0x9F,0x87, +0x80,0x08,0x69,0x02,0xA3,0xFC,0x04,0x06,0x80,0xC9, +0x18,0x1C,0x49,0x80,0x08,0x69,0x02,0x87,0x87,0xE9, +0xC3,0x87,0xEA,0xC3,0x3F,0x0F,0x00,0x08,0x69,0x02, +0x87,0x87,0xE9,0xC3,0x63,0x9F,0xC7,0x70,0x06,0xC6, +0x3F,0x0F,0x00,0x02,0x52,0x01,0x63,0xC2,0x30,0x02, +0x62,0xF1,0x63,0xC2,0x32,0x80,0x09,0x49,0x12,0xC0, +0x10,0x1C,0x3E,0x3C,0x18,0x03,0xC0,0x3E,0x01,0xC0, +0x10,0x09,0x31,0x22,0xE3,0xFF,0x00,0x08,0xFF,0x80, +0x09,0x49,0x12,0xD0,0x07,0x00,0xF8,0x07,0x80,0x30, +0x78,0xF8,0x70,0x10,0x00,0x08,0x69,0x02,0x87,0x87, +0xE7,0x3B,0x0C,0x06,0x06,0x06,0x06,0x20,0xC0,0x01, +0x06,0x00,0x11,0x89,0xE4,0x80,0x7E,0x00,0x7F,0xE0, +0x38,0x1C,0x18,0xEF,0x8C,0x7F,0x73,0x33,0x8D,0x9C, +0x63,0x66,0x18,0xD9,0x84,0x36,0x63,0x19,0x9C,0xCE, +0x63,0xFF,0x0C,0xEF,0x03,0x80,0x1C,0x78,0x0E,0x0F, +0xFF,0x00,0xFF,0x00,0x0B,0x68,0x02,0xE0,0x38,0x48, +0xD8,0x83,0x18,0x3F,0x87,0xFD,0x0C,0x1A,0x30,0x18, +0x0A,0x69,0x03,0x1F,0xE3,0xFE,0x9C,0x0E,0x3F,0xE9, +0xC0,0xD8,0x3B,0xFE,0x7F,0x80,0x0B,0x69,0x03,0x43, +0xE0,0x7F,0x8E,0x1C,0xC0,0xEF,0x00,0x18,0x19,0xC3, +0x0F,0xF0,0x3C,0x00,0x0B,0x69,0x03,0x5F,0xE1,0xFF, +0x18,0x39,0x81,0xEF,0x01,0xB0,0x33,0x07,0x3F,0xE3, +0xFC,0x00,0x0A,0x69,0x03,0x23,0xFF,0x9C,0x02,0x3F, +0xEA,0xC0,0x23,0xFF,0x09,0x69,0x02,0xE3,0xFF,0x38, +0x08,0xFF,0x66,0x00,0x0C,0x69,0x03,0x81,0xF0,0x3F, +0xE3,0x83,0x18,0x0E,0x30,0x02,0x30,0xFD,0x80,0x66, +0x03,0x38,0x38,0xFF,0x81,0xF0,0x0B,0x69,0x03,0x6F, +0x01,0xC7,0xFF,0xCC,0x06,0x02,0x69,0x01,0x37,0xCC, +0x07,0x69,0x02,0x74,0x1C,0x03,0x8C,0x6F,0xC7,0x80, +0x0B,0x69,0x03,0x18,0x39,0x87,0x18,0xE1,0x9C,0x1B, +0x81,0xF0,0x1F,0x81,0xDC,0x18,0xE1,0x86,0x18,0x71, +0x83,0x98,0x1C,0x08,0x69,0x02,0xB7,0x02,0xB0,0x23, +0xFC,0x0D,0x69,0x03,0xDC,0x07,0x9F,0x07,0xCE,0xC6, +0xD9,0x13,0x9C,0xD9,0xC6,0x38,0xC0,0x0B,0x69,0x03, +0x58,0x0D,0xC0,0xE3,0xC1,0xB6,0x1B,0x31,0xB3,0x9B, +0x19,0xB0,0xDC,0x60,0xF6,0x07,0x60,0x30,0x0C,0x69, +0x03,0x81,0xF0,0x3F,0xC3,0x87,0x18,0x1A,0xF0,0x0C, +0xC0,0xC7,0x0E,0x1F,0xE0,0x3C,0x00,0x0A,0x69,0x03, +0x1F,0xE3,0xFE,0x60,0xF1,0x81,0xB0,0x77,0xFC,0xFF, +0x2F,0x00,0x0C,0x69,0x03,0x83,0xF0,0x3F,0xC3,0x87, +0x18,0x1E,0xF0,0x0C,0xC6,0xC7,0x1C,0x1F,0xE0,0x7D, +0xC0,0x0C,0x69,0x03,0x5F,0xF0,0xFF,0xC6,0x07,0x30, +0x19,0x81,0xCF,0xFC,0x7F,0xC3,0x0C,0x18,0x70,0xC1, +0xC6,0x06,0x30,0x39,0x80,0xE0,0x0A,0x69,0x03,0x03, +0xE1,0xFE,0x70,0xEC,0x0D,0x80,0x1E,0x01,0xF8,0x07, +0x80,0x1B,0x03,0x70,0xE7,0xF8,0x7E,0x00,0x0A,0x69, +0x03,0x23,0xFF,0xD0,0xC2,0x83,0x00,0x0B,0x69,0x03, +0x77,0x01,0xCE,0x03,0x70,0x63,0xFE,0x0F,0x80,0x0B, +0x68,0x02,0xE3,0x01,0xCB,0x06,0x93,0x19,0x23,0x62, +0x03,0x80,0x11,0x68,0x04,0x63,0x07,0x07,0x4C,0x6C, +0x63,0x11,0x1A,0x8D,0x8D,0x90,0x38,0x38,0x0B,0x68, +0x02,0xCE,0x38,0x63,0x20,0x6C,0x48,0x70,0x81,0xB0, +0x3B,0x83,0x18,0x60,0xCE,0x0E,0x0C,0x68,0x03,0x1C, +0x0E,0x60,0x61,0x86,0x0E,0x70,0x33,0x10,0x1E,0x18, +0x0C,0x00,0x0A,0x68,0x02,0xE1,0xFF,0x00,0xC0,0x30, +0x0E,0x01,0x80,0x60,0x18,0x07,0x00,0xC0,0x30,0x11, +0xFF,0x80,0x04,0x89,0xE1,0x63,0xF7,0x33,0x23,0xC0, +0x06,0x68,0x01,0x63,0x09,0x62,0x4C,0x91,0xA0,0x30, +0x04,0x88,0xE1,0x63,0xF4,0xF0,0xE3,0xC0,0x07,0x38, +0x31,0xC2,0x07,0x05,0x21,0xB1,0x13,0x18,0x0A,0x10, +0xE2,0xA3,0xFF,0x03,0x11,0x59,0x98,0xC0,0x08,0x51, +0x02,0x87,0xC7,0xF6,0x18,0x3C,0xFE,0xF3,0x61,0xB1, +0xDF,0xE7,0xB0,0x08,0x69,0x02,0xA7,0x01,0xB8,0xFE, +0x73,0xD6,0x1B,0x9D,0xFC,0xDC,0x07,0x51,0x02,0x47, +0x8F,0xDC,0xEB,0x03,0x99,0xF8,0xF0,0x08,0x69,0x02, +0xA4,0x0C,0x76,0x7F,0x73,0xD6,0x1B,0x9C,0xFE,0x3B, +0x08,0x51,0x02,0x87,0x87,0xE7,0x33,0x0E,0x3F,0xD8, +0x0E,0x33,0xF0,0xF0,0x06,0x68,0x01,0x47,0x9F,0x31, +0x1F,0x6B,0x06,0x00,0x08,0x71,0xE2,0x87,0x67,0xF7, +0x3D,0x61,0xB9,0xCF,0xE3,0xB0,0x1B,0x1D,0xFC,0x7C, +0x08,0x69,0x02,0xA7,0x01,0xBC,0xFF,0x71,0xEE,0x18, +0x02,0x69,0x01,0x23,0x1B,0xCE,0x04,0x8F,0xE1,0x20, +0xC1,0xA7,0x66,0xF7,0x00,0x08,0x69,0x02,0x67,0x01, +0x8E,0xCE,0x6E,0x3C,0x1F,0x0D,0x88,0xCC,0x63,0x31, +0xC0,0x02,0x69,0x01,0x37,0xCC,0x0C,0x51,0x03,0x9B, +0x9C,0xFD,0xF7,0x39,0xEE,0x31,0x80,0x08,0x51,0x02, +0x9B,0xCF,0xF7,0x1E,0xE1,0x80,0x08,0x51,0x02,0x87, +0x87,0xE7,0x3D,0x61,0xB9,0xCF,0xC3,0xC0,0x08,0x71, +0xE2,0x9B,0x8F,0xE7,0x3D,0x61,0xB9,0xDF,0xCD,0xCA, +0xC0,0x08,0x71,0xE2,0x87,0x67,0xF7,0x3D,0x61,0xB9, +0xCF,0xE3,0xBA,0x03,0x05,0x51,0x01,0x9B,0x7D,0xCD, +0xC0,0x07,0x51,0x02,0x4F,0x9F,0xD8,0xDC,0x0F,0x03, +0x81,0xD8,0xDF,0xCF,0x80,0x04,0x68,0x01,0x65,0xA3, +0xF1,0xA1,0xC0,0x08,0x51,0x02,0xB7,0x0D,0x8E,0xFF, +0x3D,0x80,0x09,0x50,0x02,0x63,0x07,0x2C,0x68,0x36, +0x40,0xE0,0x10,0x0D,0x50,0x03,0x58,0x43,0x8C,0x71, +0x99,0x4D,0x0D,0xB6,0x14,0x52,0x0E,0x38,0x18,0xC0, +0x08,0x50,0x02,0x18,0x70,0xCC,0x3C,0x81,0x81,0xE4, +0x33,0x30,0xC0,0x09,0x70,0xE2,0x63,0x07,0x0C,0x61, +0x98,0x6C,0x81,0xE4,0x86,0x03,0x03,0xC0,0xE0,0x08, +0x50,0x02,0x23,0xFC,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E, +0x08,0xFF,0x06,0x88,0xE1,0x83,0x8F,0xA3,0x0E,0x47, +0x07,0x2C,0xC1,0xE1,0xC0,0x02,0x8A,0xE1,0xB7,0xDE, +0x70,0x06,0x88,0xE1,0x9C,0x3C,0xA3,0x07,0x40,0xE3, +0xAC,0xC7,0x8E,0x00,0x0A,0x20,0x22,0xCE,0x03,0xF1, +0x47,0xE0,0x38,}; +/* font data size: 1223 bytes */ + +static const unsigned char Arial_13_index[] = { +0x00,0x00,0x10,0x05,0x00,0xF0,0x44, +0x0E,0x42,0x78,0x65,0x0D,0x21,0xD4,0x40,0x88,0x81, +0x22,0x25,0x84,0xD8,0x9F,0x15,0x22,0xD4,0x5F,0x0C, +0xF1,0xBE,0x3B,0x87,0xF1,0x0F,0x23,0x84,0xA4,0x9C, +0x93,0xF2,0x8C,0x55,0x4A,0xF1,0x6D,0x2F,0xC6,0xA0, +0xDC,0x1C,0x83,0xB4,0x7B,0x0F,0xC2,0x02,0x43,0x08, +0x85,0x13,0x23,0x04,0x8E,0x93,0xD2,0xFA,0x74,0x50, +0xEA,0x59,0x54,0xAC,0x25,0xB0,0xB8,0x57,0x6A,0xFA, +0x61,0x4C,0x71,0x96,0x34,0x06,0x90,0xD4,0x9A,0xD3, +0x64,0x6D,0x2D,0xB9,0xBE,0xB8,0xA7,0x2A,0xE8,0x9D, +0x83,0xBA,0x79,0x4F,0x51,0xED,0x3E,0x37,0xE6,0xFE, +0x20,0x1C,0x0C,0x83,0x10,0x96,0x19,0x43,0x98,0x8F, +0x13,0xE2,0xC4,0x63,0x8E,0x92,0x06,0x48,0xC9,0xE9, +0x57,0x2C,0x65,0xF0, +}; +/* font index size: 131 bytes */ + +const ILI9341_t3_font_t Arial_13 = { + Arial_13_index, + 0, + Arial_13_data, + 1, + 0, + 32, + 126, + 0, + 0, + 11, + 5, + 5, + 3, + 5, + 5, + 19, + 13 +}; + + + +static const unsigned char Arial_14_data[] = { +0x00,0x00,0x01,0x40,0x02,0x72,0x01,0xB7,0xAC,0x46, +0x05,0x29,0x49,0xEF,0x60,0x0B,0x70,0x02,0xE0,0x33, +0x06,0x64,0x7F,0xF8,0x19,0x83,0x31,0x1F,0xFE,0x0C, +0xC4,0x33,0x00,0x09,0x89,0xF2,0xC1,0x01,0xF0,0xFE, +0x74,0xE3,0x20,0x78,0x0F,0x80,0xF0,0x2E,0x09,0xB2, +0x6E,0xB9,0xFC,0x3E,0x40,0x40,0x0F,0x71,0x04,0x4F, +0x03,0x23,0x30,0xC3,0x31,0x84,0x66,0x60,0x3C,0xC0, +0x00,0xDE,0x80,0x36,0x60,0x66,0x70,0x18,0xCC,0x30, +0x78,0x0C,0x71,0x03,0x43,0xC0,0x3F,0x08,0x63,0x03, +0x98,0x0F,0x80,0x78,0x07,0xC0,0x73,0x33,0x0D,0x98, +0x38,0xE3,0xC3,0xFB,0x0F,0x8C,0x02,0x29,0x49,0x2F, +0x05,0x91,0xE1,0x81,0x08,0x68,0x61,0x19,0x82,0x21, +0x83,0x04,0x08,0x05,0x90,0xE1,0x90,0x20,0xC8,0x30, +0x58,0x30,0xA0,0xC6,0x10,0x80,0x05,0x31,0x41,0xE0, +0x8F,0x89,0x0A,0x0A,0x51,0x0A,0xE8,0x30,0x8F,0xFE, +0x83,0x00,0x02,0x29,0xE9,0x63,0x85,0x00,0x05,0x10, +0x21,0xA3,0xE0,0x02,0x12,0x01,0x63,0x06,0x70,0x01, +0x60,0x39,0x1A,0x8C,0x96,0x23,0x00,0x09,0x71,0x02, +0xC7,0xC3,0xF8,0xC6,0xDC,0x1B,0x06,0x63,0x1F,0xC3, +0xE0,0x05,0x72,0x02,0xE0,0x63,0xBE,0xDE,0x8E,0x06, +0x09,0x71,0x02,0xC7,0xC3,0xF9,0xC7,0x60,0xE0,0x06, +0x03,0x01,0x80,0xC0,0x60,0x30,0x18,0x11,0xFF,0x09, +0x71,0x02,0xC7,0x83,0xF1,0xC6,0x61,0x80,0x60,0xF0, +0x3E,0x01,0xE0,0x06,0xC1,0xB8,0xE7,0xF0,0xF8,0x0A, +0x70,0x02,0xC0,0x20,0x0C,0x03,0x80,0xF2,0x06,0xC1, +0x98,0x63,0x18,0x64,0x7F,0xF2,0x06,0x00,0x09,0x71, +0x02,0xE1,0xFD,0x0C,0x06,0x01,0xBC,0x7F,0x98,0x38, +0x01,0xB0,0x6E,0x39,0xFC,0x3E,0x00,0x09,0x71,0x02, +0xC3,0xC1,0xF8,0xC7,0x70,0xD8,0x06,0xF1,0xFE,0x71, +0xE7,0x06,0x63,0x9F,0xC1,0xE0,0x09,0x71,0x02,0xE3, +0xFE,0x01,0x00,0xC0,0x60,0x11,0x01,0x89,0x18,0x49, +0x80,0x09,0x71,0x02,0xC7,0xC3,0xF9,0xC7,0x8C,0x1B, +0x8F,0x0F,0xE7,0x1E,0x30,0x6C,0x39,0xFC,0x3E,0x00, +0x09,0x71,0x02,0xC7,0x83,0xF9,0xC6,0x9C,0x1B,0x8E, +0x7F,0x8F,0x60,0x1B,0x06,0xE3,0x1F,0xC3,0xC0,0x02, +0x52,0x01,0x63,0xC2,0x30,0x02,0x6A,0xE9,0x63,0xC2, +0x38,0x50,0x09,0x49,0x12,0xC0,0x10,0x1C,0x3E,0x3C, +0x18,0x03,0xC0,0x3E,0x01,0xC0,0x10,0x09,0x31,0x22, +0xE3,0xFF,0x00,0x08,0xFF,0x80,0x09,0x49,0x12,0xD0, +0x07,0x00,0xF8,0x07,0x80,0x30,0x78,0xF8,0x70,0x10, +0x00,0x09,0x71,0x02,0xC7,0xC3,0xF9,0xC7,0x60,0xC0, +0x30,0x18,0x0E,0x07,0x03,0x88,0x18,0x00,0x10,0x30, +0x12,0x91,0xE4,0xC0,0x7F,0x00,0x3F,0xF8,0x0F,0x07, +0x83,0x80,0x38,0xE3,0xDB,0x18,0xFF,0x37,0x39,0xC6, +0xCE,0x18,0xD9,0x83,0x1B,0x30,0x47,0x66,0x18,0xCC, +0xE7,0x31,0xCF,0xFE,0x18,0xEF,0x03,0x80,0x0E,0x3C, +0x07,0x81,0xFF,0xE0,0x0F,0xE0,0x0D,0x70,0x03,0x60, +0x1C,0x12,0x1B,0x08,0x18,0xC0,0xC1,0x90,0x7F,0xC8, +0x60,0x34,0x60,0x0C,0x0A,0x72,0x03,0x5F,0xC3,0xFC, +0x61,0xD1,0x83,0x30,0xE8,0xFF,0x18,0x34,0x60,0x6C, +0x1D,0xFF,0x3F,0xC0,0x0C,0x71,0x03,0x81,0xE0,0x3F, +0xC3,0x83,0x18,0x0E,0xF0,0x01,0x80,0x66,0x06,0x38, +0x70,0xFF,0x01,0xE0,0x0B,0x72,0x03,0x9F,0xE1,0xFF, +0x18,0x39,0x81,0xB3,0x01,0xB0,0x33,0x07,0x3F,0xE3, +0xFC,0x00,0x0A,0x72,0x03,0x63,0xFF,0xAC,0x02,0x3F, +0xEA,0xC0,0x23,0xFF,0x09,0x72,0x03,0x23,0xFF,0x58, +0x08,0xFF,0x66,0x00,0x0D,0x71,0x03,0xC1,0xF8,0x1F, +0xF0,0xE0,0xE3,0x01,0xDC,0x02,0x8C,0x00,0x46,0x0F, +0xD8,0x03,0x30,0x0C,0xF0,0x71,0xFF,0x81,0xF8,0x0B, +0x71,0x03,0x73,0x01,0xC7,0xFF,0xCC,0x06,0x02,0x72, +0x01,0xB7,0xDC,0x07,0x71,0x02,0xB4,0x1C,0x83,0x8C, +0x6F,0xC7,0x80,0x0B,0x72,0x03,0x58,0x39,0x87,0x18, +0xE1,0x9C,0x1B,0x81,0xB0,0x1F,0x01,0xF8,0x19,0xC1, +0x8C,0x18,0x61,0x87,0x18,0x39,0x81,0xC0,0x08,0x72, +0x02,0xF7,0x02,0xF0,0x23,0xFC,0x0D,0x71,0x03,0xDC, +0x07,0x9F,0x07,0xD6,0xC6,0xE7,0x36,0x6C,0x51,0xC6, +0x38,0xC0,0x0B,0x71,0x03,0x58,0x0D,0xC0,0xE3,0xC1, +0xB6,0x1C,0x66,0x38,0xC6,0x6C,0x37,0x18,0x3D,0x81, +0xD8,0x0C,0x0D,0x71,0x03,0xC1,0xF0,0x1F,0xF0,0xE0, +0xE3,0x01,0xB3,0x00,0x66,0x03,0x1C,0x1C,0x3F,0xE0, +0x3E,0x00,0x0A,0x72,0x03,0x5F,0xE3,0xFE,0x60,0xF3, +0x81,0xB0,0x77,0xFC,0xFF,0x2F,0x00,0x0D,0x71,0x03, +0xC1,0xF0,0x1F,0xF0,0xE0,0xE3,0x01,0xB3,0x00,0x66, +0x1B,0x1C,0x38,0x3F,0xE0,0x3E,0xE0,0x0B,0x72,0x03, +0x9F,0xE1,0xFF,0x18,0x3A,0x30,0x33,0x07,0x3F,0xE3, +0xFC,0x31,0x83,0x0C,0x30,0xE3,0x07,0x30,0x33,0x03, +0x80,0x0B,0x71,0x03,0x43,0xF0,0x7F,0x8E,0x1C,0xC0, +0xCC,0x00,0x70,0x03,0xE0,0x07,0x80,0x0E,0x30,0x19, +0xC3,0x9F,0xF0,0x7E,0x00,0x0A,0x71,0x03,0x23,0xFF, +0xD0,0xC2,0xC3,0x00,0x0B,0x71,0x03,0x77,0x01,0xD6, +0x03,0x30,0x63,0xFE,0x0F,0x80,0x0D,0x70,0x03,0x63, +0x00,0x72,0xC0,0x68,0x30,0x64,0x8C,0x62,0x03,0x61, +0x00,0xE0,0x13,0x70,0x04,0xE3,0x03,0x81,0xCB,0x0D, +0x86,0x86,0x31,0x8D,0x06,0x63,0x32,0x4D,0x83,0x64, +0x0E,0x03,0x80,0x0D,0x70,0x03,0x4E,0x0E,0x1C,0x70, +0x31,0x80,0xEE,0x01,0xB0,0x90,0x70,0x03,0x60,0x1D, +0xC0,0xE3,0x83,0x06,0x1C,0x1C,0xE0,0x38,0x0C,0x70, +0x03,0x1C,0x0E,0x60,0x61,0x86,0x0E,0x70,0x33,0x01, +0xD8,0x07,0x86,0x83,0x00,0x0B,0x70,0x03,0x21,0xFF, +0x80,0x30,0x06,0x40,0x18,0x03,0x00,0x60,0x81,0x80, +0x30,0x06,0x01,0x1F,0xFC,0x04,0x91,0xE1,0x63,0xF7, +0x37,0x23,0xC0,0x06,0x70,0x01,0x63,0x09,0x62,0x8C, +0x91,0xA0,0x30,0x04,0x90,0xE1,0x63,0xF4,0xF4,0xE3, +0xC0,0x07,0x38,0x39,0xC2,0x07,0x05,0x21,0xB1,0x13, +0x18,0x0B,0x10,0xE2,0xE3,0xFF,0x80,0x03,0x19,0x59, +0x98,0xC4,0x09,0x51,0x02,0x87,0xC7,0xF9,0x86,0x07, +0x8F,0xE7,0x99,0x86,0x63,0x9F,0xE3,0xCC,0x09,0x71, +0x02,0xEB,0x00,0xDE,0x3F,0xCE,0x3D,0x60,0xDC,0x77, +0xF9,0xBC,0x08,0x51,0x02,0x87,0x87,0xE7,0x3D,0x60, +0x39,0xCF,0xC3,0xC0,0x09,0x71,0x02,0xE8,0x06,0x3D, +0x9F,0xEE,0x3D,0x60,0xDC,0x73,0xFC,0x7B,0x09,0x51, +0x02,0xC7,0xC3,0xF9,0xC6,0x60,0xE3,0xFE,0xC0,0x38, +0x67,0xF0,0xF8,0x06,0x71,0x01,0x87,0x9F,0x86,0x23, +0xED,0x60,0xC0,0x09,0x71,0xE2,0xC7,0xB3,0xFD,0xC7, +0xAC,0x1B,0x8E,0x7F,0x8F,0x60,0x1B,0x0E,0xFF,0x0F, +0x80,0x08,0x71,0x02,0xAB,0x01,0xBC,0xFF,0x71,0xEE, +0x18,0x02,0x71,0x01,0x23,0x83,0x79,0xC0,0x04,0x97, +0xE1,0x20,0xE0,0x34,0xEC,0xDE,0xE0,0x08,0x71,0x02, +0x6B,0x01,0x8E,0xCE,0x6E,0x47,0xC3,0x71,0x98,0xCE, +0x63,0x31,0xC0,0x02,0x71,0x01,0x37,0xDC,0x0E,0x51, +0x04,0x1B,0xCF,0x3F,0xBF,0x71,0xC7,0xB8,0x61,0x80, +0x08,0x51,0x02,0x9B,0xCF,0xF7,0x1E,0xE1,0x80,0x09, +0x51,0x02,0xC7,0xC3,0xF9,0xC7,0xAC,0x1B,0x8E,0x7F, +0x0F,0x80,0x09,0x71,0xE2,0xDB,0xC7,0xF9,0xC7,0xAC, +0x1B,0x8C,0xFF,0x37,0x95,0x80,0x09,0x71,0xE2,0xC7, +0xB3,0xFD,0xC7,0xAC,0x19,0x8E,0x7F,0x8F,0x74,0x03, +0x05,0x51,0x01,0x9B,0x7D,0xCD,0xC0,0x08,0x51,0x02, +0x8F,0x8F,0xE6,0x1B,0x80,0xF0,0x1E,0x03,0xB0,0xCF, +0xE3,0xE0,0x05,0x68,0x01,0x65,0x91,0xFC,0x61,0xE3, +0x80,0x08,0x51,0x02,0xB7,0x0D,0x8E,0xFF,0x3D,0x80, +0x09,0x50,0x02,0x63,0x07,0x2C,0x68,0x36,0x40,0xE0, +0x10,0x0D,0x50,0x03,0x58,0x43,0x8C,0x71,0x99,0x4D, +0x0D,0xB6,0x14,0x52,0x0E,0x38,0x18,0xC0,0x09,0x50, +0x02,0x58,0x33,0x1A,0x0D,0x90,0x38,0x83,0x61,0x8C, +0xC1,0x80,0x09,0x70,0xE2,0x63,0x07,0x0C,0x61,0x98, +0x6C,0x81,0xE4,0x86,0x03,0x03,0xC0,0xE0,0x09,0x50, +0x02,0x61,0xFE,0x03,0x81,0xC1,0xE0,0xE0,0x70,0x38, +0x11,0xFF,0x06,0x90,0xE1,0x83,0x8F,0xB3,0x0E,0x47, +0x07,0x2C,0xC1,0xE1,0xC0,0x02,0x92,0xE1,0xB7,0xDE, +0xB0,0x06,0x90,0xE1,0x9C,0x3C,0xB3,0x07,0x40,0xE3, +0xAC,0xC7,0x8E,0x00,0x09,0x21,0x22,0xCE,0x07,0xC5, +0x1F,0x03,0x80,}; +/* font data size: 1313 bytes */ + +static const unsigned char Arial_14_index[] = { +0x00,0x00,0x10,0x05,0x00,0xF0,0x42, +0x0E,0x02,0x88,0x6A,0x0D,0xC1,0xEC,0x44,0x08,0xF1, +0x30,0x27,0x85,0x18,0xA7,0x16,0x22,0xFC,0x64,0x0D, +0xB1,0xDE,0x40,0x88,0xA9,0x28,0x26,0xE5,0x28,0xAE, +0x96,0x32,0xD4,0x5E,0x4C,0x11,0x91,0x34,0x87,0x48, +0xF2,0x1F,0x84,0x18,0x87,0x91,0x52,0x34,0x49,0xA9, +0x59,0x2D,0xA6,0x54,0xFC,0xA1,0x94,0xB2,0xAA,0x57, +0xCB,0x35,0x70,0xAF,0x96,0x22,0xC6,0x99,0x33,0x36, +0x69,0x6D,0x91,0xBA,0xB8,0x97,0x22,0xE6,0xDD,0x1B, +0xAD,0x76,0x6E,0xE1,0xE4,0x3D,0x67,0xC4,0xFC,0x1F, +0xFC,0x09,0x83,0x70,0x96,0x16,0x43,0x58,0x8B,0x12, +0xA2,0xB4,0x5F,0x8D,0x91,0xEA,0x44,0x48,0xF9,0x3D, +0x29,0xE5,0x84,0xBB,0x99,0x93,0x6A,0x75,0x4F,0x8A, +0x0B,0x42,0xE8,0xC0, +}; +/* font index size: 131 bytes */ + +const ILI9341_t3_font_t Arial_14 = { + Arial_14_index, + 0, + Arial_14_data, + 1, + 0, + 32, + 126, + 0, + 0, + 11, + 5, + 5, + 3, + 5, + 5, + 21, + 14 +}; + + + +static const unsigned char Arial_16_data[] = { +0x00,0x00,0x01,0x80,0x02,0x82,0x01,0xB7,0xBE,0x08, +0xC0,0x06,0x31,0x52,0x33,0x30,0x0C,0x80,0x03,0x24, +0x31,0x83,0x19,0x1F,0xFF,0x03,0x19,0x06,0x31,0x1F, +0xFE,0x31,0x89,0x63,0x00,0x0A,0x99,0xF3,0x01,0x00, +0xF8,0x3F,0xCE,0x9D,0x91,0xB2,0x07,0x40,0x78,0x07, +0xE0,0x3E,0x04,0xE0,0x8E,0x32,0x33,0x4C,0x7F,0x87, +0xC4,0x04,0x00,0x12,0x81,0x05,0x07,0x00,0xC1,0xB0, +0x30,0x63,0x06,0x0C,0x61,0x82,0x31,0x8C,0x06,0x33, +0x00,0x6C,0x67,0x07,0x19,0xB4,0x00,0xCC,0x70,0x06, +0x31,0x81,0x86,0x30,0x60,0x6C,0x0C,0x07,0x00,0x0D, +0x81,0x03,0xC1,0xC0,0x0F,0x82,0x4C,0x60,0x1B,0x00, +0x7C,0x01,0xC0,0x1D,0x80,0x63,0x33,0x06,0xCC,0x1E, +0x30,0x38,0x61,0xA1,0xFE,0x61,0xE1,0x00,0x02,0x31, +0x51,0x33,0x05,0xA1,0xE1,0xC1,0x08,0x61,0x21,0x9B, +0x86,0x21,0x82,0x0C,0x10,0x20,0x05,0xA1,0xE1,0xD0, +0x20,0xC1,0x20,0xDA,0x30,0xE0,0xC2,0x18,0x42,0x00, +0x08,0x39,0x4A,0x60,0x61,0xFF,0x07,0x86,0x61,0x20, +0x0A,0x51,0x1B,0x68,0x30,0x8F,0xFE,0x83,0x00,0x02, +0x2A,0xE9,0xA3,0x85,0x00,0x06,0x10,0x29,0xE3,0xF0, +0x02,0x12,0x01,0xA3,0x07,0x80,0x01,0xA0,0x1C,0x86, +0x91,0x92,0x62,0x58,0x38,0x30,0x00,0x0A,0x81,0x03, +0x03,0xC0,0xFE,0x86,0x1B,0x70,0x36,0x07,0x0C,0x30, +0xFC,0x0F,0x00,0x06,0x82,0x03,0x20,0x30,0xE7,0xDD, +0xA3,0xD0,0xE4,0x30,0x0A,0x81,0x03,0x07,0xE1,0xFE, +0x70,0xEC,0x0E,0x40,0x30,0x0C,0x03,0x00,0xC0,0x30, +0x0C,0x03,0x00,0xC0,0x47,0xFE,0x0A,0x81,0x03,0x07, +0xC1,0xFC,0x71,0xCC,0x18,0x03,0x00,0xC0,0x70,0x0F, +0x00,0x34,0x80,0x6C,0x0D,0xC3,0x1F,0xE1,0xF0,0x0A, +0x81,0x03,0x00,0x60,0x1C,0x80,0xF2,0x06,0xC1,0x98, +0x73,0x0C,0x63,0x0C,0x8F,0xFE,0x80,0xC0,0x0A,0x81, +0x03,0x20,0xFE,0x96,0x00,0xFC,0x3F,0xE6,0x0D,0x40, +0x1B,0x03,0x70,0xC7,0xF8,0x7C,0x00,0x0A,0x81,0x03, +0x03,0xE0,0xFE,0x30,0xE6,0x0E,0x30,0x06,0x78,0xFF, +0x9C,0x3D,0x60,0x66,0x18,0xFF,0x07,0x80,0x0A,0x81, +0x03,0x23,0xFF,0x00,0x40,0x18,0x06,0x40,0x31,0x01, +0x84,0x8C,0x01,0x02,0x4C,0x00,0x0A,0x81,0x03,0x03, +0xC0,0xFC,0xA6,0x1A,0x0F,0xC3,0x0D,0x58,0x19,0x86, +0x3F,0xC1,0xE0,0x0A,0x81,0x03,0x03,0xC1,0xFC,0x30, +0xCC,0x0A,0x70,0x37,0x0E,0x7F,0xC7,0x9C,0x00,0x6C, +0x19,0xC7,0x1F,0xC1,0xF0,0x02,0x62,0x01,0xA3,0xD0, +0x46,0x02,0x7A,0xE9,0xA3,0xD0,0x47,0x0A,0x0B,0x59, +0x13,0x40,0x04,0x01,0xC0,0xF8,0x3C,0x0F,0x01,0x80, +0x0F,0x00,0x3C,0x00,0xF8,0x01,0xC0,0x04,0x0B,0x39, +0x23,0x63,0xFF,0xC8,0x00,0x8F,0xFE,0x0B,0x59,0x13, +0x50,0x01,0xC0,0x0F,0x80,0x1E,0x00,0x78,0x00,0xC0, +0x78,0x1E,0x0F,0x81,0xC0,0x10,0x00,0x0A,0x81,0x03, +0x07,0xE1,0xFE,0x70,0xEC,0x0C,0x01,0x80,0x70,0x1C, +0x07,0x00,0xC4,0x86,0x10,0x00,0x40,0x60,0x14,0xA9, +0xDD,0x80,0x3F,0x00,0x07,0xFE,0x00,0xF0,0x3C,0x06, +0x00,0x60,0x63,0x99,0x87,0x7E,0xCE,0x37,0x1C,0x31, +0xB0,0x61,0x9B,0x83,0x0D,0x1B,0x03,0x0C,0xD8,0x30, +0xC6,0xC1,0x8E,0x37,0x1C,0xE1,0xDF,0xFE,0x06,0x71, +0xC0,0x38,0x00,0x18,0xE0,0x03,0x83,0xC0,0x78,0x0F, +0xFF,0x80,0x0F,0xE0,0x00,0x0F,0x80,0x03,0xE0,0x0E, +0x04,0x03,0x60,0x07,0x70,0x80,0xC6,0x10,0x30,0x62, +0x0F,0xFE,0x0C,0x06,0x43,0x00,0x68,0xC0,0x06,0x0C, +0x82,0x03,0xDF,0xF0,0xFF,0xC6,0x07,0x4E,0x03,0x30, +0x32,0x3F,0xF1,0x80,0xD3,0x80,0x6C,0x07,0x7F,0xF3, +0xFE,0x00,0x0E,0x81,0x04,0x00,0xF8,0x07,0xFC,0x1C, +0x1C,0x60,0x18,0xC0,0x1E,0x60,0x00,0x60,0x0C,0xC0, +0x30,0xE0,0xE0,0xFF,0x80,0xFC,0x00,0x0D,0x82,0x04, +0x1F,0xF0,0x7F,0xF1,0x80,0xE6,0x01,0x98,0x07,0xCC, +0x01,0xC6,0x01,0x98,0x1C,0x7F,0xF1,0xFF,0x00,0x0C, +0x82,0x03,0xE3,0xFF,0xEF,0x00,0x23,0xFF,0xAF,0x00, +0x23,0xFF,0xC0,0x0A,0x82,0x03,0x63,0xFF,0xBC,0x02, +0x3F,0xED,0xC0,0x00,0x0F,0x81,0x04,0x40,0xFC,0x03, +0xFF,0x07,0x03,0x8E,0x01,0x8C,0x00,0xE7,0x00,0x04, +0x60,0x7F,0x60,0x03,0x30,0x03,0x38,0x03,0x1C,0x0F, +0x0F,0xFE,0x03,0xF0,0x0C,0x82,0x04,0x37,0x00,0xE3, +0xFF,0xF7,0x00,0xC0,0x02,0x82,0x01,0xB7,0xDE,0x30, +0x08,0x81,0x02,0xF4,0x0E,0x80,0xE3,0x0D,0xCE,0x7E, +0x1E,0x00,0x0D,0x82,0x03,0xD8,0x0E,0x60,0x71,0x83, +0x86,0x1C,0x18,0xE0,0x67,0x01,0xB8,0x07,0xE0,0x1F, +0xC0,0x73,0x81,0x87,0x06,0x0E,0x18,0x18,0x60,0x71, +0x80,0xE6,0x01,0xC0,0x09,0x82,0x03,0x37,0x01,0xB8, +0x08,0xFF,0x80,0x0F,0x82,0x04,0xDC,0x01,0xE7,0xC0, +0x7C,0xEC,0x1B,0x9C,0xC6,0x73,0x8D,0x8E,0x70,0xE1, +0x80,0x0C,0x82,0x04,0x18,0x06,0xE0,0x38,0xF0,0x38, +0xD8,0x36,0x61,0xC6,0x31,0xB0,0xCE,0x30,0x6E,0x30, +0x3D,0x80,0xEC,0x03,0x0F,0x81,0x04,0x40,0xF8,0x03, +0xFE,0x07,0x07,0x0E,0x03,0x8C,0x01,0xB3,0x00,0x19, +0x80,0x31,0xC0,0x70,0xE0,0xE0,0x7F,0xC0,0x1F,0x00, +0x0C,0x82,0x03,0xDF,0xF0,0xFF,0xE6,0x03,0x56,0x01, +0xB0,0x19,0xFF,0xCF,0xF8,0xCC,0x00,0x0F,0x89,0xFC, +0x40,0xF8,0x03,0xFE,0x07,0x07,0x0E,0x03,0x8C,0x01, +0xB3,0x00,0x19,0x80,0x31,0xC3,0xB0,0xE0,0xE0,0x7F, +0xE0,0x1F,0xB8,0x00,0x08,0x0C,0x82,0x04,0x1F,0xF8, +0xFF,0xE6,0x03,0xCE,0x01,0xB0,0x1D,0xFF,0xCF,0xFC, +0x61,0x83,0x06,0x18,0x38,0xC0,0xE6,0x03,0x30,0x1D, +0x80,0x60,0x0D,0x81,0x03,0xC1,0xF8,0x1F,0xF0,0xE0, +0xE8,0x60,0x19,0xC0,0x03,0xC0,0x07,0xF0,0x03,0xF0, +0x00,0xF1,0x80,0x33,0x00,0xCE,0x0E,0x1F,0xF8,0x1F, +0x80,0x0C,0x81,0x03,0xA3,0xFF,0xF4,0x18,0x34,0x18, +0x00,0x0C,0x82,0x04,0x37,0x00,0xEF,0x00,0xDC,0x0E, +0x70,0xE1,0xFE,0x07,0xE0,0x0F,0x80,0x03,0xD8,0x00, +0xDC,0x01,0xE1,0x80,0x34,0x18,0x0C,0x1C,0x1C,0x81, +0x83,0x12,0x18,0xC2,0x01,0xB0,0x01,0xF0,0x00,0xE0, +0x00,0x15,0x80,0x05,0x63,0x01,0xC0,0x74,0xC1,0xB0, +0x6A,0x31,0x8C,0x65,0x0D,0x83,0x62,0x03,0x80,0xE0, +0x0F,0x80,0x03,0xCE,0x03,0x87,0x07,0x03,0x06,0x01, +0x8C,0x01,0xDC,0x00,0xD8,0x24,0x0E,0x00,0x1B,0x00, +0x31,0x80,0x71,0xC0,0x60,0xC0,0xC0,0x61,0xC0,0x73, +0x80,0x38,0x0E,0x80,0x03,0x9C,0x03,0x98,0x06,0x18, +0x18,0x38,0x70,0x30,0xC0,0x33,0x00,0x7E,0x00,0x78, +0x34,0x0C,0x00,0x18,0x00,0x0C,0x80,0x03,0x61,0xFF, +0xC0,0x0D,0x00,0x18,0x01,0x80,0x18,0x40,0x30,0x03, +0x00,0x30,0x10,0x60,0x06,0x00,0x8F,0xFF,0x04,0xA1, +0xE1,0xA3,0xF7,0x37,0x23,0x23,0xC0,0x07,0x80,0x01, +0xA3,0x04,0xB0,0x93,0x12,0x32,0x43,0x03,0x81,0x80, +0x04,0xA1,0xE1,0xA3,0xF4,0xF4,0xE0,0xE3,0xC0,0x0A, +0x48,0x3A,0xC1,0x84,0x0F,0x12,0x66,0x43,0x0C,0xC0, +0xC0,0x0C,0x10,0xE3,0x23,0xFF,0xC0,0x03,0x19,0x69, +0xD8,0xC4,0x0A,0x61,0x03,0x07,0xC1,0xFC,0x8C,0x18, +0x0F,0x1F,0xE3,0xCD,0x18,0x33,0x0E,0x3F,0xC7,0xCC, +0x0A,0x81,0x03,0x2B,0x00,0x6F,0x0F,0xF9,0xC3,0x66, +0x06,0xE1,0x9F,0xF3,0x78,0x09,0x61,0x02,0xC3,0xC3, +0xF8,0xC7,0x60,0xEB,0x00,0xC1,0x98,0xE7,0xF0,0x78, +0x0A,0x81,0x03,0x28,0x03,0x0F,0x67,0xFC,0xC3,0xE6, +0x06,0xE1,0xCF,0xF8,0x7B,0x0A,0x61,0x03,0x03,0xC1, +0xFE,0x30,0xCC,0x0E,0x3F,0xF8,0xC0,0x1C,0x19,0xC6, +0x1F,0xC1,0xE0,0x07,0x80,0x01,0xC3,0xC7,0xE0,0xC4, +0x7E,0xD3,0x12,0x60,0x0A,0x81,0xE3,0x03,0xD9,0xFF, +0x30,0xEE,0x0E,0xB0,0x36,0x0E,0x61,0xCF,0xF8,0x7B, +0x00,0x6C,0x19,0xFF,0x0F,0x80,0x09,0x81,0x02,0xEB, +0x00,0xDE,0x3F,0xCE,0x3E,0xE0,0xE3,0x06,0x02,0x81, +0x01,0x63,0x83,0x7B,0xC0,0x04,0xA7,0xE1,0x20,0xE0, +0x34,0xF4,0xDE,0xE0,0x09,0x81,0x02,0xAB,0x00,0xC3, +0xB1,0xCC,0xE3,0x70,0xF8,0x3F,0x0E,0xC3,0x38,0xC6, +0x31,0xCC,0x33,0x0E,0x02,0x81,0x01,0x37,0xDE,0x30, +0x10,0x61,0x04,0x9B,0xC7,0x8F,0xF7,0xE7,0x1E,0x3E, +0xE0,0xC1,0xC6,0x0C,0x18,0x09,0x61,0x02,0xDB,0xC7, +0xF9,0xC7,0xDC,0x1C,0x60,0xC0,0x0B,0x61,0x03,0x43, +0xE0,0x7F,0x0E,0x39,0xC1,0xEB,0x01,0xB8,0x39,0xC7, +0x0F,0xE0,0x7C,0x00,0x0A,0x81,0xE3,0x1B,0xC3,0xFE, +0x70,0xD9,0x81,0xB8,0x67,0xF8,0xDE,0x2B,0x00,0x0A, +0x81,0xE3,0x03,0xD9,0xFF,0x30,0xF9,0x81,0x98,0x73, +0xFE,0x1E,0xE8,0x03,0x06,0x61,0x01,0xDB,0xBF,0x71, +0xB8,0x46,0x00,0x09,0x61,0x02,0xC7,0xC3,0xF9,0x83, +0x60,0x1E,0x03,0xF0,0x3F,0x01,0xC0,0x36,0x1C,0xFE, +0x1F,0x00,0x05,0x80,0x01,0x84,0x96,0x47,0xF5,0x86, +0x1E,0x38,0x09,0x61,0x02,0xF7,0x07,0x18,0x37,0x1C, +0xFF,0x1E,0xC0,0x0B,0x60,0x02,0xE3,0x01,0xC3,0x06, +0x93,0x19,0x03,0x62,0x03,0x80,0x10,0x00,0x0F,0x60, +0x03,0xD8,0x20,0xE3,0x0E,0x19,0x8A,0x31,0x9B,0x30, +0x9B,0x24,0x1B,0x6C,0x0A,0x28,0x81,0xC7,0x00,0xC6, +0x00,0x0A,0x60,0x02,0x9C,0x39,0x86,0x83,0x30,0x3C, +0x40,0x60,0x1E,0x20,0xCC,0x30,0xCE,0x1C,0x0B,0x80, +0xE2,0xE3,0x01,0xC3,0x06,0x18,0x61,0x8C,0x81,0x99, +0x01,0xE0,0x0E,0x00,0xC0,0x1C,0x01,0x80,0xF8,0x0F, +0x00,0x0A,0x60,0x02,0xE1,0xFF,0x00,0xE0,0x38,0x0E, +0x03,0x80,0xE0,0x38,0x0E,0x03,0x80,0x8F,0xFC,0x06, +0xA0,0xE1,0xC3,0x8F,0xC3,0x0C,0x47,0x06,0x30,0xC1, +0xE1,0xC0,0x02,0xAA,0xD9,0xB7,0xDF,0x70,0x06,0xA1, +0xE1,0xDC,0x3C,0xC3,0x07,0x40,0xE3,0xB0,0xC7,0x8E, +0x00,0x0B,0x21,0x33,0x4F,0x01,0xFC,0x51,0xFC,0x07, +0x80,}; +/* font data size: 1551 bytes */ + +static const unsigned char Arial_16_index[] = { +0x00,0x00,0x10,0x05,0x81,0x00,0x46,0x0F,0xC3, +0x18,0x80,0x10,0x82,0x48,0x50,0x0A,0xA1,0x66,0x2E, +0x45,0xF0,0xC2,0x19,0xE3,0x7C,0x75,0x10,0x02,0x2E, +0x4A,0x89,0xE9,0x52,0x2C,0x85,0xD4,0xC5,0x99,0x13, +0x30,0x6B,0x0D,0xA9,0xC9,0x3B,0xC8,0x5D,0x17,0xA4, +0x64,0xBE,0x9D,0x54,0x1A,0x8E,0x55,0x8A,0xD9,0x5E, +0x2C,0x85,0xD0,0xBC,0x58,0x1B,0x1A,0x66,0x8D,0x15, +0xB0,0xB7,0xC7,0x32,0xE8,0xDD,0x8B,0xCB,0x7B,0xCF, +0xFA,0x0A,0xC2,0xC8,0x6B,0x10,0xA2,0x5C,0x57,0x8B, +0xB1,0x8A,0x3A,0x48,0x39,0x25,0x28,0x65,0x9C,0xBE, +0x9A,0x93,0x82,0x73,0xCF,0x0A,0x09,0x42,0xA8,0xCD, +0x24,0xA6,0xD5,0x16,0xAA,0x55,0xDA,0xE1,0x5E,0xAC, +0x2D,0x94,0xB5,0x76,0xF2,0xE9,0xDE,0x5B,0xE5,0x7E, +0x30,0x28, +}; +/* font index size: 131 bytes */ + +const ILI9341_t3_font_t Arial_16 = { + Arial_16_index, + 0, + Arial_16_data, + 1, + 0, + 32, + 126, + 0, + 0, + 11, + 5, + 5, + 3, + 5, + 5, + 23, + 16 +}; + + + +static const unsigned char Arial_18_data[] = { +0x00,0x00,0x01,0xC0,0x02,0x93,0x02,0x37,0xDE,0x08, +0xC0,0x07,0x31,0x62,0x73,0x18,0x0E,0x90,0x03,0xA0, +0x18,0x60,0x71,0x90,0x18,0x64,0x7F,0xFF,0x43,0x0C, +0x47,0xFF,0xF0,0x61,0x80,0xC7,0x08,0x61,0x80,0x0B, +0xA9,0xF3,0x80,0x80,0x3E,0x0F,0xF8,0xC9,0x98,0x8E, +0x31,0x03,0x90,0x1F,0x00,0xFC,0x01,0xF0,0x13,0x40, +0x23,0x62,0x37,0x27,0x32,0xE3,0xFE,0x0F,0x88,0x04, +0x00,0x13,0x91,0x05,0x87,0x80,0xC0,0xFC,0x1C,0x1C, +0xE1,0x81,0x86,0x38,0x18,0x63,0x01,0x86,0x70,0x18, +0x66,0x01,0xCE,0xE0,0x0F,0xCC,0xF0,0x79,0x9F,0x80, +0x1B,0x9E,0x00,0x66,0x1C,0x01,0x8C,0x30,0x30,0xE7, +0x03,0x07,0xE0,0x60,0x3C,0x0F,0x91,0x04,0x41,0xF0, +0x03,0xF8,0x07,0x1C,0x20,0xC1,0x80,0xE3,0x80,0x77, +0x00,0x3E,0x00,0x78,0x00,0xEC,0x01,0x86,0x33,0x07, +0x73,0x03,0xE3,0x01,0xC3,0x81,0xE1,0xC3,0xF0,0xFF, +0x78,0x7C,0x30,0x02,0x31,0x61,0x73,0x06,0xBA,0xDA, +0x01,0x86,0x83,0x25,0x8D,0xC2,0x30,0x96,0x20,0xC0, +0xC0,0xC0,0x06,0xB8,0xDA,0x18,0x18,0x83,0x24,0x6D, +0x0C,0x18,0x78,0x18,0x74,0x18,0x61,0x80,0x08,0x41, +0x52,0xA0,0x61,0x36,0xFF,0x83,0xC3,0x30,0x90,0x0C, +0x61,0x1B,0xEC,0x18,0x23,0xFF,0xEC,0x18,0x00,0x02, +0x32,0xE1,0xE3,0x85,0xA0,0x06,0x11,0x2A,0x23,0xF0, +0x02,0x12,0x01,0xE3,0x07,0x90,0x01,0xE0,0x1C,0x86, +0x0E,0x91,0x94,0x62,0x58,0x46,0x00,0x0C,0x91,0x03, +0x83,0xF0,0x3F,0xC3,0x87,0x18,0x1B,0x70,0x0E,0x70, +0x0C,0xC0,0xC7,0x0E,0x1F,0xE0,0x7E,0x00,0x07,0x92, +0x03,0xA0,0x18,0x78,0xFB,0xDB,0x9E,0x83,0xB0,0x60, +0x0C,0x91,0x03,0x83,0xF0,0x3F,0xC3,0x87,0x30,0x1D, +0x80,0x70,0x00,0x70,0x00,0xC0,0x0C,0x00,0xC0,0x0C, +0x01,0xC0,0x1C,0x01,0x80,0x18,0x02,0x3F,0xFC,0x0C, +0x91,0x03,0x83,0xE0,0x3F,0xC3,0x86,0x38,0x19,0x80, +0xC0,0x06,0x00,0xE0,0x3E,0x01,0xF8,0x00,0x60,0x03, +0xC0,0x01,0xB0,0x0D,0xC0,0xE6,0x0E,0x1F,0xE0,0x7C, +0x00,0x0C,0x91,0x03,0x80,0x18,0x01,0xC8,0x03,0xC0, +0x36,0x03,0xB0,0x19,0x81,0x8C,0x1C,0x60,0xC3,0x0C, +0x18,0xE0,0xC8,0xFF,0xFA,0x00,0xC0,0x0C,0x91,0x03, +0xA0,0xFF,0x8E,0x01,0x2C,0x00,0x6F,0x87,0xFE,0x38, +0x38,0x00,0xF2,0x00,0x6C,0x03,0x60,0x31,0x83,0x87, +0xF8,0x1F,0x00,0x0C,0x91,0x03,0x81,0xF0,0x3F,0xC1, +0x87,0x18,0x1C,0xC0,0x6C,0x00,0x67,0xC3,0x7F,0x1E, +0x1C,0xE0,0x7A,0xC0,0x33,0x03,0x1C,0x38,0x7F,0x80, +0xF8,0x0C,0x91,0x03,0xA3,0xFF,0xC0,0x0D,0x00,0x19, +0x00,0x31,0x00,0x61,0x00,0xC1,0x21,0x81,0x43,0x00, +0x0C,0x91,0x03,0x81,0xE0,0x3F,0xC3,0x86,0x4B,0x03, +0x0C,0x30,0x3F,0x03,0xFC,0x38,0x73,0x81,0xE7,0x00, +0xD8,0x0E,0x70,0x61,0xFE,0x07,0xE0,0x0C,0x91,0x03, +0x83,0xE0,0x3F,0xC3,0x87,0x38,0x1A,0xB0,0x0D,0xC0, +0xE7,0x0F,0x1F,0xD8,0x7C,0xC0,0x07,0x18,0x0C,0x60, +0xC3,0xFC,0x07,0xC0,0x02,0x6A,0x01,0xE3,0xD2,0x08, +0xC0,0x02,0x8A,0xE1,0xE3,0xD2,0x08,0xE1,0x68,0x0C, +0x59,0x1B,0xC0,0x02,0x00,0xF0,0x1F,0x03,0xC0,0xF0, +0x0C,0x00,0x3C,0x00,0x3C,0x00,0x7C,0x00,0xF0,0x00, +0x80,0x0C,0x41,0x2B,0xE3,0xFF,0xE8,0x00,0x23,0xFF, +0xC0,0x0C,0x59,0x1B,0xD0,0x00,0xF0,0x03,0xE0,0x03, +0xC0,0x03,0xC0,0x03,0x00,0xF0,0x3C,0x0F,0x80,0xF0, +0x04,0x00,0x00,0x0C,0x91,0x03,0x83,0xF0,0x3F,0xC3, +0x87,0x38,0x1D,0x80,0x60,0x03,0x00,0x38,0x03,0x80, +0x38,0x03,0x80,0x18,0x48,0x30,0x40,0x00,0x40,0x30, +0x00,0x17,0xB9,0xDE,0x40,0x1F,0xC0,0x00,0x7F,0xF8, +0x01,0xF0,0x3C,0x03,0x80,0x0E,0x07,0x00,0x07,0x06, +0x0F,0x33,0x0C,0x3F,0xB3,0x8C,0x70,0xF1,0x8C,0xE0, +0x61,0x98,0xC0,0x61,0xA3,0x30,0x0C,0x33,0x30,0x0C, +0x63,0x30,0x18,0x63,0x30,0x38,0xE3,0x98,0x79,0xC1, +0x9F,0xFF,0x81,0xC7,0x8E,0x18,0xE0,0x00,0x30,0x70, +0x00,0xE0,0x3C,0x03,0xC0,0x1F,0xFF,0x80,0x03,0xFC, +0x00,0x0F,0x91,0x04,0x60,0x0E,0x04,0x83,0x60,0x80, +0xC6,0x01,0xC7,0x10,0x30,0x62,0x0F,0xFE,0x0C,0x06, +0x1C,0x03,0x43,0x00,0x68,0xC0,0x06,0x0E,0x92,0x04, +0x5F,0xF8,0x3F,0xFC,0x60,0x19,0x58,0x03,0x30,0x0C, +0x7F,0xF0,0xFF,0xF1,0x80,0x73,0x00,0x79,0xC0,0x0D, +0x80,0x73,0xFF,0xE7,0xFF,0x00,0x10,0x91,0x04,0x80, +0x7E,0x01,0xFF,0xC1,0xE0,0x71,0xC0,0x18,0xC0,0x0E, +0xE0,0x00,0xCC,0x00,0x03,0x00,0x19,0x80,0x1C,0xE0, +0x1C,0x3C,0x1C,0x0F,0xFC,0x01,0xF8,0x00,0x0F,0x92, +0x04,0x9F,0xF8,0x1F,0xFE,0x18,0x07,0x18,0x03,0x98, +0x01,0x98,0x01,0xF3,0x00,0x1B,0x00,0x3B,0x00,0x33, +0x00,0x73,0x00,0xE3,0xFF,0xC3,0xFF,0x00,0x0E,0x92, +0x04,0x63,0xFF,0xFC,0xC0,0x02,0x3F,0xFE,0xCC,0x00, +0x23,0xFF,0xF0,0x0C,0x92,0x03,0xE3,0xFF,0xF3,0x00, +0x23,0xFF,0xB7,0x00,0x18,0x00,0x10,0x91,0x04,0xC0, +0x7E,0x01,0xFF,0xC1,0xE0,0xF0,0xC0,0x18,0xC0,0x0E, +0x60,0x02,0x9C,0x00,0x08,0xC0,0x7F,0x60,0x01,0xC3, +0x00,0x18,0xC0,0x0C,0x78,0x3E,0x1F,0xFC,0x01,0xF8, +0x00,0x0E,0x92,0x04,0xB7,0x00,0x36,0x00,0x71,0xFF, +0xFE,0xE0,0x06,0xC0,0x0C,0x02,0x92,0x01,0xB7,0xDE, +0xB0,0x0A,0x91,0x03,0x74,0x03,0xB0,0x0E,0x70,0x33, +0x0C,0x7F,0x87,0xC0,0x0F,0x92,0x04,0x58,0x03,0x98, +0x07,0x18,0x0E,0x18,0x1C,0x18,0x38,0x18,0x70,0x18, +0xE0,0x19,0xC0,0x1B,0xE0,0x1F,0xE0,0x1E,0x70,0x1C, +0x38,0x18,0x1C,0x23,0x01,0xC3,0x00,0xE3,0x00,0x73, +0x00,0x38,0x0B,0x92,0x03,0xB7,0x00,0x6E,0x00,0x8C, +0x01,0x1F,0xFC,0x11,0x92,0x05,0x5C,0x00,0x78,0xF0, +0x07,0xCE,0xC0,0x6E,0x73,0x06,0x73,0x8C,0x63,0x9C, +0x36,0x1C,0xE0,0xE0,0xC0,0x0E,0x92,0x04,0xA3,0x80, +0x38,0xF0,0x0D,0xB0,0x1C,0x66,0x06,0xC6,0x0E,0x30, +0xC3,0x60,0xC7,0x18,0x19,0xB0,0x1B,0x8C,0x03,0xE3, +0x00,0x70,0x11,0x91,0x04,0xC0,0x7C,0x00,0xFF,0xC0, +0x78,0x3C,0x18,0x03,0x21,0x80,0x0D,0x98,0x00,0x38, +0x60,0x03,0x0C,0x01,0x83,0xC1,0xE0,0x7F,0xF0,0x03, +0xE0,0x00,0x0E,0x92,0x04,0x5F,0xFC,0x3F,0xFC,0x60, +0x1C,0xC0,0x1E,0x70,0x03,0x60,0x0E,0xC0,0x39,0xFF, +0xE3,0xFF,0x8D,0xC0,0x00,0x11,0x99,0xFC,0xC0,0x7C, +0x00,0xFF,0xC0,0x78,0x3C,0x18,0x03,0x21,0x80,0x0D, +0x98,0x00,0x33,0x00,0x1C,0xC0,0xC6,0x18,0x3F,0x87, +0x83,0xC0,0x7F,0xF8,0x07,0xEF,0x00,0x00,0xC0,0x0F, +0x92,0x04,0x9F,0xFC,0x1F,0xFF,0x18,0x07,0x27,0x00, +0x33,0x00,0x73,0x00,0xE3,0xFF,0xE3,0xFF,0x83,0x07, +0x03,0x03,0x03,0x03,0x83,0x01,0xC4,0x60,0x1C,0x60, +0x0E,0x60,0x07,0x0F,0x91,0x04,0x40,0xFC,0x03,0xFF, +0x07,0x03,0x8C,0x01,0xCC,0x00,0xCC,0x00,0x0E,0x00, +0x07,0xE0,0x03,0xFE,0x00,0x7F,0x80,0x03,0x80,0x00, +0xE3,0x00,0x19,0x80,0x39,0xE0,0x70,0xFF,0xE0,0x3F, +0x80,0x0E,0x90,0x03,0xA3,0xFF,0xFD,0x03,0x03,0x40, +0xC0,0x80,0x30,0x00,0x0E,0x92,0x04,0xB7,0x00,0x3D, +0xC0,0x0C,0xC0,0x31,0xC0,0xE1,0xFF,0x80,0xFC,0x00, +0x0F,0x91,0x04,0x58,0x00,0xDC,0x01,0xE1,0x80,0x31, +0xC0,0x74,0x18,0x0C,0x91,0x83,0x10,0x18,0xC0,0x1D, +0xC2,0x01,0xB0,0x01,0xF0,0x40,0x1C,0x00,0x19,0x90, +0x06,0x98,0x03,0x80,0x36,0x00,0xE0,0x1E,0x58,0x0D, +0x80,0xC3,0x07,0x70,0x64,0x18,0x31,0x83,0x06,0x0C, +0x61,0xC9,0x18,0xC1,0x8C,0x48,0x6C,0x06,0xC0,0x1F, +0x01,0xF0,0x80,0x70,0x07,0x00,0x11,0x90,0x04,0x4E, +0x00,0xE1,0xC0,0x70,0x38,0x38,0x06,0x0C,0x01,0xC7, +0x00,0x3B,0x80,0x06,0xC0,0x80,0x1C,0x00,0x0F,0x80, +0x03,0x60,0x01,0xDC,0x00,0xE3,0x80,0x70,0x70,0x18, +0x0C,0x0E,0x03,0x87,0x00,0x73,0x80,0x0E,0x10,0x90, +0x04,0x18,0x00,0xE6,0x00,0xE1,0x80,0x60,0xE0,0x70, +0x38,0x70,0x0C,0x30,0x07,0x38,0x01,0x98,0x20,0x0F, +0x03,0x40,0x60,0x00,0x30,0x00,0x0E,0x90,0x03,0xE1, +0xFF,0xF0,0x00,0xC0,0x03,0x80,0x0E,0x00,0x38,0x00, +0x60,0x01,0xC0,0x07,0x00,0x1C,0x00,0x30,0x00,0xE0, +0x03,0x80,0x0E,0x00,0x18,0x00,0x60,0x02,0x3F,0xFF, +0x05,0xBA,0xD9,0xE3,0xFB,0x8D,0xC5,0xE2,0x3E,0x07, +0x90,0x01,0xE3,0x04,0xB0,0x38,0x93,0x14,0x32,0x43, +0x40,0x30,0x05,0xB8,0xD9,0xE3,0xFA,0x3D,0x1D,0x8E, +0x3E,0x0A,0x51,0x43,0x01,0x84,0x0F,0x12,0x66,0x4B, +0x0C,0xC0,0xC0,0x0F,0x17,0xDB,0xA3,0xFF,0xF8,0x04, +0x19,0x7A,0x1C,0x61,0x80,0x0C,0x69,0x03,0x83,0xF0, +0x7F,0xC7,0x07,0x30,0x18,0x00,0xC0,0x3E,0x1F,0xF1, +0xF1,0x98,0x0C,0xC0,0xE7,0x0F,0x1F,0xD8,0x7C,0x60, +0x0B,0x92,0x03,0xAF,0x00,0x33,0xC3,0x7E,0x3C,0x73, +0x83,0x5E,0x03,0x70,0x67,0x8E,0x6F,0xC6,0x78,0x0B, +0x69,0x03,0x43,0xF0,0x7F,0x8E,0x1D,0xC0,0xEB,0x00, +0x30,0x1B,0x83,0x9C,0x30,0xFE,0x07,0xC0,0x0B,0x91, +0x03,0xAC,0x01,0x87,0x98,0xFD,0x9C,0x79,0x83,0xDE, +0x03,0x30,0x73,0x8F,0x1F,0xB0,0xF3,0x0C,0x69,0x03, +0x83,0xF0,0x3F,0xC3,0x87,0x18,0x19,0x80,0x71,0xFF, +0xF1,0x80,0x0E,0x03,0x38,0x30,0xFF,0x03,0xF0,0x07, +0x90,0x01,0xC3,0xC7,0xE4,0xC4,0x7F,0xD3,0x14,0x60, +0x0B,0x91,0xDB,0x83,0xCC,0x7E,0xCE,0x3C,0xC1,0xEF, +0x01,0x98,0x39,0xC7,0x8F,0xD8,0x79,0x80,0x1B,0x03, +0xB8,0x71,0xFF,0x0F,0xC0,0x0A,0x92,0x03,0xAF,0x00, +0x67,0x8D,0xF9,0xE3,0xB8,0x3D,0xC0,0xE3,0x03,0x02, +0x92,0x01,0xA3,0x93,0x7C,0xC0,0x05,0xBF,0xD9,0xA0, +0x72,0x0D,0x1E,0x8E,0x06,0xFB,0xC0,0x0B,0x92,0x03, +0x6F,0x00,0x30,0x73,0x0E,0x31,0xC3,0x38,0x37,0x03, +0xE0,0x3F,0x03,0x38,0x31,0xC3,0x0C,0x30,0x63,0x07, +0x30,0x38,0x02,0x92,0x01,0xB7,0xDE,0xB0,0x12,0x6A, +0x05,0x99,0xE1,0xE3,0x7E,0xFE,0x78,0xF8,0xEE,0x0E, +0x0F,0x70,0x30,0x38,0xC0,0xC0,0xC0,0x0A,0x6A,0x03, +0x99,0xE3,0x7E,0x78,0xEE,0x0F,0x70,0x38,0xC0,0xC0, +0x0C,0x69,0x03,0x83,0xF0,0x3F,0xC3,0x87,0x38,0x1E, +0xF0,0x0D,0xC0,0xE7,0x0E,0x1F,0xE0,0x7E,0x00,0x0B, +0x92,0xDB,0x99,0xE1,0xBF,0x1E,0x39,0xC1,0xAF,0x01, +0xB8,0x33,0xC7,0x37,0xE3,0x3C,0x5E,0x00,0x0B,0x91, +0xDB,0x83,0xCC,0x7E,0xCE,0x3D,0xC1,0xEF,0x01,0x98, +0x39,0xC7,0x8F,0xF8,0x79,0xD8,0x03,0x06,0x6A,0x02, +0x1B,0xBF,0x71,0xB8,0x4E,0x00,0x0B,0x69,0x03,0x47, +0xE0,0xFF,0x9C,0x19,0x80,0x1C,0x00,0xFC,0x07,0xF8, +0x0F,0xC0,0x1D,0x80,0xDC,0x1C,0xFF,0x83,0xE0,0x07, +0x88,0x09,0xE8,0xC4,0x7F,0xD3,0x10,0x60,0x7C,0x3C, +0x0A,0x6A,0x03,0xB7,0x03,0x8C,0x0D,0x83,0xB8,0xF3, +0xF6,0x3C,0xC0,0x0B,0x68,0x02,0xE3,0x01,0xCB,0x06, +0x83,0x19,0x23,0x62,0x03,0x80,0x10,0x00,0x13,0x68, +0x04,0xD8,0x08,0x0D,0x81,0xC0,0xCC,0x1C,0x1E,0x18, +0x6C,0x30,0xC6,0xC6,0x0C,0xC6,0x60,0x6C,0x6E,0x06, +0xC6,0xC0,0x68,0x2C,0x40,0x70,0x70,0x03,0x03,0x00, +0x0B,0x68,0x02,0xDC,0x0C,0xC1,0x86,0x38,0x73,0x03, +0x62,0x43,0x80,0x6C,0x0E,0xE0,0xC6,0x18,0x33,0x83, +0x80,0x0B,0x91,0xDB,0x23,0x01,0xC3,0x06,0x30,0xC8, +0x31,0x83,0x30,0x1B,0x10,0x3C,0x01,0xC2,0x43,0x00, +0x60,0x1E,0x01,0xC0,0x00,0x0B,0x68,0x03,0x21,0xFF, +0x80,0x30,0x06,0x00,0xC0,0x1C,0x03,0x80,0x70,0x0E, +0x01,0xC0,0x18,0x04,0x7F,0xF0,0x08,0xB9,0xDA,0x00, +0xE1,0xFD,0x18,0x18,0x47,0x00,0xC3,0x46,0x03,0x00, +0xF0,0x38,0x02,0xBA,0xD9,0xB7,0xDF,0x78,0xC0,0x08, +0xBF,0xDA,0x1C,0x0F,0x0D,0x18,0x06,0x40,0x38,0x33, +0x46,0x03,0x0F,0x07,0x00,0x0D,0x21,0x3B,0xC7,0x80, +0x7F,0x8D,0x8F,0xF0,0x0F,0x00,}; +/* font data size: 1886 bytes */ + +static const unsigned char Arial_18_index[] = { +0x00,0x00,0x10,0x05, +0x81,0x00,0x4E,0x11,0xC3,0x98,0x99,0x13,0xA2,0xB0, +0x5E,0x0C,0x71,0xA2,0x35,0xC6,0xE0,0xE0,0x1D,0xA4, +0x08,0x87,0x12,0xB2,0x96,0x59,0x4B,0xF9,0x9B,0x35, +0xC7,0x24,0xF2,0x1E,0xB3,0xE6,0x82,0x50,0x9A,0x29, +0x48,0xAA,0x2D,0x52,0xAC,0x25,0xC4,0xC0,0x18,0x7B, +0x1C,0x67,0xED,0x35,0xA9,0xB6,0x07,0x0C,0xE4,0x5D, +0x3B,0xC2,0x7C,0x0F,0xDE,0x0C,0xC3,0xB8,0xC3,0x1B, +0xA3,0xF4,0x9A,0x98,0x13,0xAA,0x83,0x52,0x8A,0x63, +0x4F,0xAA,0x3D,0x53,0xAB,0x35,0x7E,0xBC,0x58,0xBB, +0x3D,0x6C,0x6E,0x3D,0xD2,0xBD,0x77,0xE7,0x00,0x60, +0xBC,0x49,0x8A,0xB1,0xEE,0x4A,0xCB,0xB9,0xC3,0x41, +0xE8,0xCD,0x47,0xAB,0xB5,0xDE,0xCA,0xDD,0x5B,0xFF, +0x8B,0xF2,0xCE,0x79,0xD0,0xFA,0x98, +}; +/* font index size: 131 bytes */ + +const ILI9341_t3_font_t Arial_18 = { + Arial_18_index, + 0, + Arial_18_data, + 1, + 0, + 32, + 126, + 0, + 0, + 11, + 5, + 5, + 3, + 5, + 5, + 27, + 18 +}; + + + +static const unsigned char Arial_20_data[] = { +0x00,0x00,0x01,0x00,0x02,0xA3,0x01,0x1B,0xEF,0x1C, +0x11,0x80,0x08,0x39,0x35,0x5B,0x86,0x0F,0xA0,0x02, +0x10,0x0C,0x18,0x1C,0x3A,0x43,0x06,0x47,0xFF,0xFA, +0x18,0x30,0x38,0x31,0x1F,0xFF,0xE0,0xC1,0x81,0xC3, +0x84,0x30,0x60,0x0D,0xB9,0xFA,0x00,0x20,0x03,0xE0, +0x3F,0xC1,0xCB,0x8E,0x27,0x30,0x8D,0x18,0x40,0x31, +0x00,0xFC,0x00,0xFE,0x00,0x7C,0x01,0x3A,0x00,0x87, +0x18,0x43,0x31,0x1C,0xE4,0xE1,0xFF,0x01,0xF0,0x80, +0x20,0x00,0x15,0xA2,0x03,0x23,0xC0,0x18,0x1F,0x80, +0xC0,0x66,0x03,0x04,0x61,0x83,0x02,0x30,0xC3,0x00, +0xC3,0x18,0x03,0x98,0xE0,0x07,0xE3,0x1E,0x0F,0x18, +0xFC,0x00,0x63,0x34,0x00,0x63,0x0C,0x03,0x0C,0x30, +0x1C,0x30,0xC0,0x60,0xC3,0x03,0x83,0x98,0x0C,0x07, +0xE0,0x60,0x0F,0x00,0x11,0xA1,0x02,0x60,0x78,0x00, +0x7F,0x80,0x38,0x70,0x49,0x81,0x80,0x30,0xC0,0x06, +0xF0,0x00,0xF0,0x00,0xF8,0x00,0x73,0x00,0x38,0xE1, +0x9C,0x1C,0xE6,0x03,0x71,0x80,0x7C,0x60,0x0E,0x1C, +0x07,0xC3,0x87,0xF8,0x7F,0xCF,0x07,0xC1,0x80,0x02, +0x39,0x34,0xBB,0x80,0x06,0xD2,0xE9,0x20,0xE0,0x68, +0x32,0x58,0xDC,0x27,0x09,0x62,0x0C,0x81,0x81,0x80, +0x06,0xD1,0xE9,0x2C,0x21,0x88,0x32,0x46,0xD0,0xE0, +0x30,0xF2,0x34,0x19,0x0C,0x30,0x0A,0x49,0x2D,0x70, +0x18,0x13,0x27,0xFE,0x3F,0x03,0xC0,0xFC,0x39,0xC2, +0x10,0x0E,0x71,0x0A,0x18,0x06,0x04,0x7F,0xFF,0x80, +0x60,0x00,0x02,0x3A,0xED,0x11,0xCA,0xD0,0x07,0x11, +0x19,0x31,0xFC,0x02,0x12,0x01,0x11,0x80,0x08,0xA0, +0x01,0x10,0x07,0x20,0xD2,0x18,0x1C,0x91,0x89,0x30, +0x96,0x07,0x03,0x00,0x0D,0xA1,0x02,0x00,0xF8,0x0F, +0xF8,0x70,0x74,0x30,0x1B,0x70,0x07,0x38,0x03,0x86, +0x03,0x1C,0x1C,0x3F,0xE0,0x3E,0x00,0x08,0xA2,0x02, +0x10,0x06,0x0F,0x0F,0x9F,0xDE,0x6C,0x3D,0x03,0xC0, +0x30,0x0D,0xA1,0x02,0x00,0xF8,0x0F,0xF8,0x70,0x71, +0x80,0xF1,0x80,0x38,0x00,0x18,0x00,0xC0,0x07,0x00, +0x18,0x00,0xC0,0x06,0x00,0x30,0x03,0x80,0x1C,0x00, +0xE0,0x06,0x00,0x47,0xFF,0xC0,0x0D,0xA1,0x02,0x01, +0xF8,0x0F,0xF0,0x70,0xE3,0x80,0xCC,0x03,0x00,0x0C, +0x00,0x70,0x03,0x80,0x7C,0x01,0xF8,0x00,0x70,0x00, +0xF0,0x00,0x38,0xC0,0x19,0x80,0xC7,0x07,0x0F,0xF8, +0x0F,0x80,0x0E,0xA1,0x02,0x00,0x03,0x00,0x0E,0x00, +0x3C,0x00,0xF8,0x01,0xB0,0x06,0x60,0x18,0xC0,0x71, +0x81,0xC3,0x03,0x06,0x0C,0x0C,0x30,0x18,0xE0,0x32, +0x3F,0xFF,0xB0,0x03,0x00,0x0D,0xA1,0x02,0x10,0x7F, +0xE3,0x80,0x25,0x80,0x04,0xF8,0x3F,0xF8,0xF0,0x73, +0x00,0xD4,0x00,0x38,0xC0,0x19,0x80,0xC7,0x06,0x0F, +0xF8,0x0F,0x80,0x0D,0xA1,0x02,0x00,0x7C,0x07,0xF8, +0x38,0x71,0xC0,0xE6,0x01,0x98,0x00,0xC0,0x03,0x1E, +0x0D,0xFE,0x3C,0x1C,0xE0,0x35,0x60,0x0C,0xC0,0x33, +0x01,0x86,0x0E,0x0F,0xF0,0x1F,0x00,0x0D,0xA1,0x02, +0x11,0xFF,0xF0,0x00,0x80,0x04,0x00,0x30,0x01,0x80, +0x04,0x00,0x30,0x80,0x30,0x48,0x30,0x24,0x30,0x14, +0x30,0x00,0x0D,0xA1,0x02,0x00,0xF8,0x0F,0xF8,0x30, +0x65,0x30,0x18,0x60,0xC0,0xFE,0x07,0xFC,0x38,0x38, +0xC0,0x6A,0xC0,0x19,0x80,0xC7,0x07,0x0F,0xF8,0x0F, +0x80,0x0D,0xA1,0x02,0x00,0xF8,0x0F,0xF8,0x70,0x71, +0x80,0xCC,0x01,0x56,0x00,0xCC,0x07,0x38,0x3C,0x7F, +0xB0,0x78,0xC0,0x03,0x00,0x19,0x80,0x67,0x01,0x8E, +0x1C,0x1F,0xE0,0x3E,0x00,0x02,0x7B,0x01,0x11,0xE9, +0x44,0x60,0x02,0xA3,0xED,0x11,0xE9,0x44,0x72,0xB4, +0x0C,0x6A,0x0E,0x00,0x01,0x00,0x78,0x0F,0x81,0xF0, +0x7C,0x07,0x80,0x30,0x01,0xE0,0x07,0xC0,0x07,0xC0, +0x0F,0x80,0x1E,0x00,0x10,0x0D,0x41,0x1A,0x11,0xFF, +0xFA,0x00,0x04,0x7F,0xFC,0x0C,0x6A,0x0E,0x08,0x00, +0x78,0x01,0xF0,0x03,0xE0,0x03,0xE0,0x07,0x80,0x0C, +0x01,0xE0,0x3E,0x0F,0x81,0xF0,0x1E,0x00,0x80,0x00, +0x0E,0xA1,0x02,0x00,0xFC,0x07,0xFE,0x1E,0x0E,0x30, +0x0E,0xE0,0x0D,0x80,0x18,0x00,0x30,0x00,0xE0,0x03, +0x80,0x0E,0x00,0x38,0x00,0xE0,0x03,0x82,0x40,0xC0, +0x80,0x00,0x20,0x0C,0x00,0x1A,0xD2,0xEB,0x80,0x07, +0xF8,0x00,0x03,0xFF,0xE0,0x01,0xF0,0x1E,0x00,0x78, +0x00,0xE0,0x1C,0x00,0x0E,0x07,0x07,0x8C,0xE0,0xC3, +0xFD,0x8C,0x38,0xE1,0xF1,0xC6,0x18,0x1C,0x18,0xC6, +0x01,0x83,0x30,0xC0,0x30,0x68,0xC6,0x00,0xC1,0x98, +0xC0,0x18,0x73,0x18,0x06,0x0C,0x63,0x00,0xC3,0x8C, +0x70,0x38,0x61,0xC7,0x1F,0x38,0x18,0x7F,0x7E,0x03, +0x87,0xC7,0x80,0x30,0x00,0x00,0xC7,0x00,0x00,0x70, +0x78,0x00,0x1C,0x03,0xE0,0x1F,0x00,0x3F,0xFF,0x80, +0x00,0xFF,0x80,0x00,0x11,0xA1,0x02,0x70,0x03,0x80, +0x80,0x36,0x00,0x1D,0xC1,0x00,0xC6,0x00,0x71,0xC2, +0x03,0x06,0x10,0x30,0x18,0x0F,0xFE,0x07,0xFF,0xC1, +0x80,0x30,0xE0,0x0E,0x86,0x00,0x34,0x60,0x00,0xC0, +0x10,0xA2,0x02,0x6F,0xFE,0x07,0xFF,0xC3,0x00,0x71, +0x80,0x1D,0x38,0x00,0xCC,0x00,0xE6,0x00,0xE3,0xFF, +0xE1,0xFF,0xF8,0xC0,0x0E,0x60,0x03,0xCE,0x00,0x1B, +0x00,0x1D,0x80,0x1C,0xFF,0xFC,0x7F,0xF8,0x00,0x12, +0xA1,0x02,0x80,0x3F,0x80,0x1F,0xFC,0x07,0x81,0xC1, +0xC0,0x1C,0x70,0x01,0xCC,0x00,0x1B,0x80,0x00,0xCC, +0x00,0x01,0xC0,0x01,0x98,0x00,0x73,0x80,0x0C,0x38, +0x03,0x83,0x81,0xE0,0x3F,0xF8,0x01,0xFC,0x00,0x11, +0xA2,0x02,0x8F,0xFE,0x03,0xFF,0xE0,0xC0,0x1E,0x30, +0x01,0x91,0x80,0x06,0xDC,0x00,0x1B,0x00,0x0F,0x18, +0x00,0x66,0x00,0x31,0x80,0x3C,0x7F,0xFC,0x1F,0xFC, +0x00,0x0F,0xA2,0x02,0x71,0xFF,0xFF,0x70,0x00,0x47, +0xFF,0xED,0xC0,0x01,0x1F,0xFF,0xC0,0x0E,0xA2,0x02, +0x31,0xFF,0xFE,0xE0,0x01,0x1F,0xFE,0x6E,0x00,0x11, +0x80,0x00,0x13,0xA1,0x02,0xC0,0x1F,0xC0,0x0F,0xFF, +0x01,0xE0,0x78,0x38,0x01,0xC7,0x00,0x0C,0x60,0x00, +0x66,0x00,0x01,0x38,0x00,0x02,0x30,0x07,0xFB,0x00, +0x01,0xB8,0x00,0x19,0x80,0x01,0x9C,0x00,0x18,0xE0, +0x03,0x87,0x80,0xF0,0x3F,0xFE,0x00,0x7F,0x00,0x10, +0xA2,0x02,0x9B,0x80,0x07,0x18,0x00,0x71,0xFF,0xFF, +0xB8,0x00,0x71,0x80,0x06,0x02,0xA3,0x01,0x1B,0xEF, +0x98,0x0B,0xA1,0x01,0xDA,0x00,0xF4,0x01,0xC6,0x03, +0x70,0x33,0x06,0x3F,0xE0,0xF8,0x10,0xA2,0x02,0x6C, +0x00,0xE6,0x00,0xE3,0x00,0xE1,0x80,0xE0,0xC0,0xE0, +0x60,0xE0,0x30,0xE0,0x18,0xE0,0x0C,0xF0,0x06,0xFC, +0x03,0xEE,0x01,0xE3,0x80,0xE0,0xE0,0x8C,0x07,0x06, +0x01,0xC4,0x60,0x0E,0x30,0x03,0x98,0x00,0xE0,0x0D, +0xA2,0x02,0x1B,0x80,0x0D,0xC0,0x05,0x60,0x02,0x3F, +0xFE,0x11,0xA3,0x02,0xEE,0x00,0x3C,0xF8,0x03,0xE7, +0x60,0x37,0x39,0x83,0x36,0x61,0xCE,0x71,0x8C,0x73, +0x86,0xC3,0x60,0xF0,0xE3,0x07,0x06,0x10,0xA2,0x02, +0x91,0xC0,0x06,0xF0,0x03,0x7C,0x01,0xB6,0x00,0xD9, +0x80,0x71,0x8C,0x06,0xC3,0x03,0x8C,0x18,0x36,0x06, +0x1C,0x60,0x31,0xB0,0x0C,0xD8,0x03,0x6C,0x01,0xF6, +0x00,0x7C,0x60,0x03,0x80,0x14,0xA1,0x02,0xC0,0x1F, +0x80,0x07,0xFF,0x80,0x78,0x1E,0x07,0x00,0x38,0x70, +0x00,0xE3,0x00,0x03,0x38,0x00,0x1B,0x30,0x00,0x0E, +0x18,0x00,0x18,0xE0,0x01,0xC3,0x80,0x1C,0x0F,0x03, +0xC0,0x3F,0xFC,0x00,0x3F,0x00,0x10,0xA2,0x02,0x6F, +0xFF,0x07,0xFF,0xE3,0x00,0x39,0x80,0x0F,0x58,0x00, +0x6C,0x00,0x66,0x00,0x73,0xFF,0xF1,0xFF,0xE1,0xB8, +0x00,0x0C,0x00,0x00,0x14,0xA9,0xFE,0xC0,0x1F,0x80, +0x07,0xFF,0x80,0x78,0x1E,0x07,0x00,0x38,0x70,0x00, +0xE8,0x60,0x00,0x6C,0xC0,0x00,0x33,0x00,0x03,0x98, +0x00,0x18,0xE0,0x79,0xC3,0x81,0xFC,0x0F,0x03,0xE0, +0x1F,0xFF,0x80,0x3F,0x8E,0x00,0x00,0x30,0x10,0xA2, +0x02,0x8F,0xFF,0x87,0xFF,0xE3,0x00,0x39,0x80,0x0F, +0x38,0x00,0x6C,0x00,0x76,0x00,0x73,0xFF,0xF1,0xFF, +0xE0,0xC0,0xE0,0x60,0x30,0x30,0x0C,0x18,0x07,0x0C, +0x01,0xC6,0x00,0x63,0x00,0x19,0x80,0x0E,0xC0,0x03, +0x10,0xA1,0x02,0x60,0x7F,0x00,0xFF,0xE0,0xE0,0x78, +0xE0,0x0D,0x0C,0x00,0x67,0x00,0x03,0xE0,0x00,0xFF, +0x00,0x3F,0xF0,0x03,0xFE,0x00,0x0F,0x00,0x01,0xE3, +0x00,0x0D,0xC0,0x06,0x70,0x06,0x1E,0x0F,0x07,0xFF, +0x00,0xFE,0x00,0x10,0xA0,0x02,0x11,0xFF,0xFF,0xA0, +0x30,0x1A,0x03,0x01,0x40,0x30,0x00,0x10,0xA2,0x02, +0x9B,0x80,0x07,0xB8,0x00,0x6C,0x00,0x37,0x00,0x39, +0x80,0x18,0xF0,0x38,0x3F,0xF8,0x03,0xF0,0x00,0x11, +0xA1,0x02,0x6C,0x00,0x1B,0x80,0x0F,0x0C,0x00,0x69, +0x30,0x06,0x40,0xC0,0x60,0x38,0x38,0x80,0xC1,0x84, +0x03,0x18,0x00,0xCE,0x08,0x03,0x60,0x00,0xF8,0x10, +0x03,0x80,0x1B,0xA0,0x03,0x91,0x80,0x1C,0x00,0xE5, +0x80,0x6C,0x03,0x18,0x0C,0x60,0x34,0x18,0x18,0xC0, +0xC1,0x83,0x86,0x0C,0x1C,0x30,0x61,0xC0,0xC3,0x06, +0x18,0x0C,0x70,0x31,0x80,0xC6,0x03,0x18,0x0E,0x60, +0x33,0x80,0x6E,0x03,0xB0,0x80,0xD8,0x03,0x60,0x07, +0x80,0x3C,0x10,0x0E,0x00,0x38,0x00,0x13,0xA0,0x02, +0x67,0x00,0x1C,0x38,0x03,0x81,0xC0,0x70,0x0C,0x06, +0x00,0x60,0xC0,0x07,0x1C,0x00,0x3B,0x80,0x01,0xB0, +0x10,0x01,0xC0,0x00,0x1E,0x00,0x03,0x60,0x00,0x63, +0x00,0x0E,0x38,0x01,0xC1,0xC0,0x18,0x0C,0x03,0x00, +0x60,0x70,0x07,0x0E,0x00,0x39,0xC0,0x01,0xC0,0x12, +0xA0,0x02,0x4C,0x00,0x1C,0xC0,0x07,0x0C,0x00,0xC1, +0xC0,0x38,0x1C,0x0E,0x01,0x83,0x80,0x18,0x70,0x03, +0x9C,0x00,0x33,0x02,0x00,0x78,0x0D,0x00,0xC0,0x20, +0x03,0x00,0x10,0xA0,0x02,0x30,0xFF,0xFC,0x00,0x0C, +0x00,0x0C,0x00,0x0E,0x00,0x06,0x00,0x06,0x00,0x06, +0x00,0x07,0x00,0x03,0x00,0x03,0x00,0x03,0x80,0x01, +0x80,0x01,0x80,0x01,0x80,0x01,0xC0,0x00,0xC0,0x00, +0xC0,0x01,0x1F,0xFF,0xE0,0x05,0xD2,0xE9,0x11,0xFD, +0xC6,0xE3,0x70,0xC4,0x7C,0x08,0xA0,0x01,0x11,0x81, +0x2C,0x12,0x60,0x38,0x91,0x89,0x0C,0x90,0x60,0x38, +0x0C,0x05,0xD1,0xE9,0x11,0xFD,0x1E,0x8F,0x46,0x1C, +0x7C,0x0C,0x59,0x25,0xC0,0x60,0x80,0xF0,0x81,0x98, +0x93,0x0C,0x86,0x06,0x60,0x18,0x11,0x17,0xEA,0x11, +0xFF,0xFF,0x05,0x21,0x41,0x2E,0x1C,0x30,0x60,0x0D, +0x79,0x01,0xE1,0xFC,0x1F,0xF8,0x70,0x73,0x00,0xC0, +0x03,0x00,0x3C,0x1F,0xF1,0xFC,0xC6,0x03,0x46,0x01, +0x98,0x0E,0x70,0xF8,0xFF,0x61,0xF8,0xC0,0x0D,0xA2, +0x02,0x17,0x80,0x06,0x7C,0x1B,0xFC,0x78,0x39,0xC0, +0x66,0x01,0xEF,0x00,0x6C,0x03,0xB8,0x0C,0xF0,0xE3, +0x7F,0x0C,0xF8,0x00,0x0C,0x79,0x01,0xC0,0xF8,0x1F, +0xE1,0xC3,0x8C,0x0E,0xE0,0x3A,0xC0,0x08,0xC0,0x33, +0x03,0x1C,0x38,0x7F,0x80,0xF8,0x0D,0xA1,0x02,0x16, +0x00,0x30,0x7C,0xC7,0xFB,0x38,0x3C,0xC0,0x77,0x00, +0xEF,0x00,0x6E,0x01,0x98,0x0E,0x70,0x78,0xFF,0x60, +0xF9,0x80,0x0D,0x79,0x01,0xE0,0xF8,0x0F,0xF8,0x70, +0x71,0x80,0xD1,0x80,0x38,0xFF,0xFC,0x60,0x01,0xC0, +0x03,0x00,0xCF,0x0E,0x1F,0xF0,0x1F,0x80,0x08,0xA0, +0x00,0xE1,0xF1,0xFC,0x98,0x47,0xF6,0x98,0x61,0x80, +0x0D,0xA9,0xEA,0x00,0xF9,0x8F,0xFE,0x70,0x79,0x80, +0xEE,0x01,0xDE,0x00,0xDC,0x03,0x30,0x1C,0xE0,0xF1, +0xFF,0xC1,0xF3,0x00,0x0D,0x80,0x36,0x01,0x8E,0x0E, +0x3F,0xF0,0x3F,0x00,0x0C,0xA2,0x02,0x17,0x80,0x0C, +0xF8,0x7F,0xF3,0xC1,0x9C,0x07,0xB8,0x07,0x58,0x06, +0x02,0xA2,0x00,0xD1,0xC9,0xBE,0xEC,0x05,0xD7,0xE8, +0xD0,0x39,0x06,0x8F,0x47,0x63,0x79,0xC0,0x0C,0xA2, +0x01,0xD7,0x80,0x0C,0x07,0x60,0x73,0x07,0x18,0x70, +0xC7,0x06,0x70,0x47,0xF0,0x39,0xC2,0x30,0xE1,0x83, +0x8C,0x0C,0x60,0x73,0x01,0xC0,0x02,0xA2,0x00,0xDB, +0xEF,0x98,0x14,0x7A,0x03,0x0C,0xF8,0x7C,0x6F,0xEF, +0xF3,0xC3,0xE1,0xDC,0x0E,0x07,0xB8,0x0C,0x07,0x58, +0x0C,0x06,0x0C,0x7A,0x02,0x0C,0xF8,0x6F,0xF3,0xC1, +0x9C,0x07,0xB8,0x07,0x58,0x06,0x0D,0x79,0x01,0xE0, +0xF8,0x0F,0xF8,0x70,0x71,0x80,0xCE,0x03,0xDE,0x00, +0xDC,0x07,0x30,0x18,0xE0,0xE1,0xFF,0x01,0xF0,0x0D, +0xAA,0xEA,0x0C,0xF8,0x37,0xF8,0xF0,0x73,0x80,0xCC, +0x03,0xDE,0x00,0xD8,0x07,0x70,0x19,0xE1,0xC6,0xFE, +0x19,0xF0,0xCC,0x00,0x00,0x0D,0xA9,0xEA,0x00,0xF9, +0x8F,0xF6,0x70,0x79,0x80,0xEE,0x01,0xDE,0x00,0xDC, +0x03,0x30,0x1C,0x70,0xF0,0xFE,0xC1,0xF3,0xC0,0x01, +0x80,0x07,0x7A,0x01,0x2D,0xEF,0xF1,0xC3,0x70,0x56, +0x00,0x0C,0x79,0x01,0xC1,0xF0,0x3F,0xE3,0x83,0x98, +0x0C,0xC0,0x07,0x80,0x1F,0xC0,0x7F,0x80,0x7E,0x00, +0x3B,0x00,0xDC,0x06,0x70,0x61,0xFF,0x07,0xE0,0x07, +0xA0,0x01,0x01,0x14,0x62,0x3F,0xE9,0x8A,0x30,0x3E, +0x1E,0x0C,0x7A,0x02,0x1B,0x80,0x75,0x80,0x6C,0x07, +0x30,0x79,0xFE,0xC3,0xE6,0x0D,0x78,0x01,0xB1,0x80, +0x38,0x60,0x31,0xC1,0xC3,0x06,0x0E,0x39,0x03,0x18, +0x0E,0xC2,0x03,0x61,0x00,0xE0,0x01,0x00,0x13,0x78, +0x02,0x6C,0x06,0x07,0x18,0x1C,0x0C,0xC1,0x41,0x8C, +0x36,0x18,0xC3,0x63,0x86,0x36,0x30,0x62,0x23,0x07, +0x63,0x72,0x06,0xC6,0xC0,0x28,0x2C,0x40,0x70,0x70, +0x02,0x02,0x00,0x0D,0x78,0x01,0xAE,0x01,0x98,0x0C, +0x30,0x70,0xE3,0x81,0x8C,0x03,0x60,0x0F,0x80,0x1C, +0x00,0xF8,0x03,0x60,0x1C,0xC0,0xE3,0x83,0x06,0x18, +0x0C,0xE0,0x38,0x0D,0xA8,0xE9,0xAC,0x01,0xB0,0x0F, +0x0C,0x06,0x30,0x30,0x60,0xC1,0x87,0x06,0x18,0x0C, +0x62,0x06,0x60,0x0F,0x84,0x07,0x82,0x41,0x81,0x01, +0x80,0x1E,0x00,0x70,0x00,0x0D,0x78,0x01,0xD0,0xFF, +0xF0,0x01,0x80,0x0E,0x00,0x70,0x03,0x80,0x1C,0x00, +0xE0,0x07,0x00,0x38,0x01,0xC0,0x0E,0x00,0x30,0x02, +0x3F,0xFE,0x08,0xD1,0xE9,0x20,0x70,0x78,0x73,0x46, +0x03,0x03,0x08,0xE0,0x18,0x68,0xC4,0x0C,0x03,0xC0, +0xE0,0x02,0xD2,0xE8,0xDB,0xEF,0xBD,0xE0,0x08,0xD0, +0xE9,0x2E,0x07,0x86,0x8C,0x40,0xC0,0x32,0x01,0xC1, +0x9A,0x30,0x18,0x1C,0x3C,0x1C,0x00,0x0E,0x21,0x22, +0x03,0xC0,0x1F,0xF1,0xB0,0xFF,0x40,0x78,}; +/* font data size: 2278 bytes */ + +static const unsigned char Arial_20_index[] = { +0x00,0x00, +0x04,0x00,0xC0,0x11,0x02,0xB0,0x52,0x08,0x60,0xB3, +0x0B,0x80,0xC8,0x0D,0x80,0xE7,0x0F,0x20,0xF8,0x0F, +0xD1,0x02,0x11,0x21,0x29,0x13,0x71,0x5A,0x17,0xE1, +0x9F,0x1B,0xB1,0xDD,0x1F,0x62,0x13,0x23,0x52,0x3C, +0x24,0x42,0x5D,0x26,0x72,0x80,0x2A,0x32,0xFC,0x32, +0x03,0x47,0x36,0xF3,0x8F,0x39,0xF3,0xAE,0x3D,0xD3, +0xED,0x3F,0x34,0x02,0x42,0xD4,0x39,0x45,0x34,0x79, +0x4A,0x24,0xBE,0x4E,0xA5,0x14,0x53,0xF5,0x4D,0x56, +0x35,0x84,0x5B,0xB5,0xEF,0x61,0x06,0x3B,0x64,0x56, +0x55,0x65,0xF6,0x6E,0x67,0x46,0x7B,0x69,0x86,0xB2, +0x6C,0x86,0xE2,0x6F,0xC7,0x08,0x72,0xA7,0x3A,0x74, +0x17,0x4C,0x76,0x87,0x6E,0x78,0x27,0x90,0x7A,0x77, +0xC1,0x7D,0xB7,0xE5,0x80,0x18,0x0D,0x81,0xB8,0x32, +0x85,0x58,0x73,0x89,0x38,0xAE,0x8C,0x18,0xC8,0x8D, +0xB0, +}; +/* font index size: 143 bytes */ + +const ILI9341_t3_font_t Arial_20 = { + Arial_20_index, + 0, + Arial_20_data, + 1, + 0, + 32, + 126, + 0, + 0, + 12, + 5, + 5, + 3, + 6, + 5, + 30, + 20 +}; + + + +static const unsigned char Arial_24_data[] = { +0x00,0x00,0x00,0x24,0x01,0xE1,0x00,0x2F,0x7D,0xF3, +0xC5,0x02,0x78,0x04,0xA0,0x50,0x33,0x78,0xE4,0x10, +0x08,0xE0,0x00,0x4A,0x00,0xE1,0xC0,0x78,0xE4,0x83, +0x87,0x27,0xFF,0xFF,0x21,0xC3,0x88,0x1C,0x38,0x4F, +0xFF,0xFE,0x8E,0x1C,0x03,0x8F,0x04,0x38,0x70,0x00, +0x08,0x70,0x7D,0x48,0x03,0x00,0x07,0xE0,0x0F,0xFC, +0x0F,0xFF,0x07,0x33,0x90,0xE3,0x1D,0x0E,0x30,0x07, +0x98,0x01,0xFC,0x00,0x7F,0x80,0x1F,0xF0,0x01,0xFC, +0x00,0xDF,0x00,0x63,0xE0,0x06,0x1E,0x38,0x61,0xDE, +0x31,0xE7,0x99,0xE1,0xFF,0xE0,0x7F,0xE0,0x0F,0xE1, +0x20,0x30,0x00,0x0C,0xE0,0x80,0x74,0x3E,0x00,0xE0, +0x1F,0xC0,0x70,0x0E,0x38,0x1C,0x08,0xE0,0xE1,0xC0, +0x38,0x38,0xF0,0x11,0xC1,0xC7,0x00,0x8E,0x0E,0x70, +0x01,0xC7,0x38,0x00,0x3F,0x8E,0x7C,0x07,0xC7,0x3F, +0x80,0x01,0xDC,0x74,0x00,0x1D,0xC1,0xE0,0x01,0xCE, +0x0F,0x00,0x1C,0x70,0x70,0x0E,0x1C,0x1C,0x03,0x83, +0x8E,0x01,0xC0,0x7F,0x00,0x70,0x0F,0x80,0x0A,0x60, +0x40,0x58,0x03,0xE0,0x00,0x7F,0x80,0x07,0xFE,0x00, +0x78,0x78,0x24,0x70,0x38,0x01,0xC3,0x80,0x0F,0x3C, +0x00,0x3F,0xC0,0x00,0xF8,0x00,0x1F,0x80,0x03,0xEE, +0x00,0x3C,0x38,0x41,0xC1,0xC7,0x9C,0x07,0x38,0xE0, +0x1F,0xC7,0x00,0x7C,0x38,0x03,0xC1,0xE0,0x1F,0x07, +0x83,0xFC,0x1F,0xFE,0xF0,0x7F,0xE3,0xC0,0xFC,0x08, +0x01,0xA0,0x50,0x1B,0x79,0x00,0x04,0x7C,0xB9,0x2C, +0x06,0x06,0x07,0x03,0x03,0x10,0x70,0x30,0x87,0x03, +0x06,0xF0,0x47,0x04,0xB8,0x0C,0x20,0xE0,0x31,0x01, +0x80,0x60,0x18,0x04,0x7C,0x79,0x2D,0x80,0x60,0x38, +0x0C,0x03,0x10,0x38,0x0C,0x90,0xED,0x07,0x80,0x79, +0x0E,0x06,0x40,0xE0,0xE0,0x60,0x70,0x30,0x30,0x00, +0x05,0x28,0x4E,0x36,0x43,0x07,0x6E,0xFF,0xC7,0xE0, +0x78,0x1F,0x87,0x38,0x42,0x00,0x07,0xBC,0x84,0x4F, +0x00,0xE0,0x4F,0xFF,0xFC,0x03,0x80,0x01,0xA0,0xFB, +0x26,0x7C,0xB2,0x60,0x04,0x8C,0x47,0x2E,0x7F,0xE0, +0x01,0x8C,0xC0,0x26,0x78,0x04,0xE0,0x00,0x26,0x00, +0x72,0x06,0xA0,0x64,0x86,0x24,0x60,0x38,0x49,0x82, +0x58,0x0E,0x03,0x00,0x08,0x60,0x40,0x48,0x0F,0xC0, +0x1F,0xF8,0x1F,0xFE,0x1F,0x0F,0x0E,0x03,0xC7,0x00, +0xE7,0x80,0x76,0xF0,0x03,0xCF,0x00,0x39,0x80,0x38, +0xE0,0x1C,0x70,0x1E,0x3E,0x1E,0x0F,0xFF,0x03,0xFF, +0x00,0x7E,0x00,0x04,0x60,0xC0,0x48,0x06,0x07,0x07, +0x87,0xC7,0xE7,0xF7,0xBB,0x1D,0x0F,0xA0,0xFA,0x0E, +0x07,0x08,0x60,0x40,0x48,0x0F,0xC0,0x1F,0xF8,0x1F, +0xFE,0x1E,0x07,0x8E,0x01,0xF1,0xC0,0x0F,0x00,0x00, +0xF0,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00, +0x1C,0x00,0x1C,0x00,0x1C,0x00,0x3C,0x00,0x3C,0x00, +0x38,0x00,0x38,0x00,0x1F,0xFF,0xE3,0xFF,0xFC,0x08, +0x60,0x40,0x48,0x0F,0xC0,0x1F,0xF8,0x1F,0xFE,0x1E, +0x0F,0x1E,0x03,0xCE,0x00,0xE0,0x00,0x70,0x00,0x78, +0x00,0x79,0x00,0x7F,0x00,0x3F,0xC0,0x00,0xF0,0x00, +0x3E,0x40,0x01,0xDC,0x00,0xEE,0x00,0xF3,0x80,0x71, +0xE0,0xF8,0x7F,0xF8,0x1F,0xF8,0x03,0xF0,0x00,0x08, +0xE0,0x40,0x48,0x00,0x18,0x00,0x0E,0x00,0x07,0x80, +0x03,0xE2,0x00,0x3F,0x00,0x1D,0xC0,0x0E,0x70,0x07, +0x1C,0x40,0x70,0xE0,0x38,0x38,0x1C,0x0E,0x0E,0x03, +0x87,0x00,0xE2,0x7F,0xFF,0xF8,0x00,0x38,0x08,0x60, +0x40,0x4A,0x4F,0xFF,0xAD,0xC0,0x00,0xEF,0xC0,0xEF, +0xF8,0x7F,0xFE,0x3C,0x07,0x80,0x01,0xD4,0x00,0x0E, +0xE0,0x07,0x70,0x07,0x9C,0x03,0x8F,0x03,0xC3,0xFF, +0xC0,0xFF,0xC0,0x1F,0x80,0x08,0x60,0x40,0x48,0x07, +0xE0,0x0F,0xFC,0x0F,0xFF,0x0F,0x07,0x8F,0x01,0xE7, +0x00,0x73,0x80,0x03,0x80,0x01,0xC7,0xC0,0xE7,0xF8, +0x7F,0xFE,0x3F,0x07,0x9E,0x01,0xCF,0x00,0x7A,0xE0, +0x07,0x38,0x03,0x9C,0x03,0x87,0x83,0xC3,0xFF,0xC0, +0x7F,0xC0,0x0F,0x80,0x08,0x60,0x40,0x4A,0x7F,0xFF, +0xC0,0x00,0xC0,0x00,0xC0,0x00,0xE0,0x00,0xE0,0x00, +0x60,0x00,0x70,0x80,0x0E,0x08,0x01,0xC0,0x90,0x38, +0x0A,0x07,0x00,0xA0,0xE0,0x00,0x08,0x60,0x40,0x48, +0x0F,0xC0,0x1F,0xF8,0x1F,0xFE,0x1E,0x07,0x29,0xC0, +0x38,0x70,0x38,0x1F,0xF8,0x07,0xF8,0x0F,0xFF,0x0F, +0x03,0xC7,0x00,0xEB,0xE0,0x07,0x38,0x07,0x1E,0x07, +0x87,0xFF,0x81,0xFF,0x80,0x3F,0x00,0x08,0x60,0x40, +0x48,0x0F,0x80,0x1F,0xF0,0x1F,0xFC,0x1F,0x07,0x0E, +0x01,0xCF,0x00,0x6A,0xE0,0x07,0x70,0x07,0x9C,0x03, +0xCF,0x07,0xE3,0xFF,0xF0,0xFF,0xB8,0x1F,0x1C,0x00, +0x0E,0x00,0x0E,0x70,0x07,0x3C,0x07,0x8F,0x07,0x87, +0xFF,0x81,0xFF,0x80,0x3F,0x00,0x01,0xC8,0xC0,0x26, +0x7E,0x8B,0x13,0xC0,0x01,0xDC,0xFB,0x26,0x7E,0x8B, +0x13,0xE5,0x93,0x00,0x07,0xBC,0x84,0x4C,0x00,0x04, +0x00,0x3C,0x00,0xFC,0x07,0xF8,0x1F,0xC0,0xFE,0x01, +0xF8,0x01,0xC0,0x01,0xF8,0x00,0xFE,0x00,0x1F,0xC0, +0x07,0xF8,0x00,0xFC,0x00,0x3C,0x00,0x04,0x07,0xA8, +0x87,0x4E,0x7F,0xFF,0xD0,0x00,0x09,0xFF,0xFE,0x07, +0xBC,0x84,0x4D,0x00,0x01,0xE0,0x01,0xF8,0x00,0xFF, +0x00,0x1F,0xC0,0x03,0xF8,0x00,0xFC,0x00,0x1C,0x00, +0xFC,0x03,0xF8,0x1F,0xC0,0xFF,0x01,0xF8,0x01,0xE0, +0x01,0x00,0x00,0x08,0x60,0x40,0x48,0x0F,0xC0,0x1F, +0xF8,0x1F,0xFE,0x1F,0x0F,0x8E,0x01,0xEF,0x00,0x77, +0x00,0x38,0x00,0x1C,0x00,0x1E,0x00,0x0E,0x00,0x0F, +0x00,0x0F,0x00,0x0F,0x00,0x0F,0x00,0x07,0x05,0x00, +0xE0,0x40,0x00,0x04,0x80,0xE0,0x00,0x0F,0x7C,0xB9, +0x88,0x00,0x3F,0xE0,0x00,0x03,0xFF,0xF0,0x00,0x0F, +0xFF,0xF8,0x00,0x7F,0x01,0xF8,0x01,0xF0,0x00,0xF8, +0x03,0xC0,0x00,0x78,0x0F,0x0F,0x0E,0x70,0x3C,0x7F, +0x9C,0xF0,0x71,0xFF,0xF0,0xE1,0xE7,0xC7,0xE1,0xE3, +0x8E,0x07,0xC1,0xC7,0x3C,0x07,0x83,0x9C,0x70,0x0F, +0x07,0x39,0xE0,0x1C,0x0E,0x73,0x80,0x38,0x1C,0xE7, +0x00,0x70,0x79,0xCE,0x01,0xE0,0xE3,0x9C,0x03,0x81, +0xC7,0x38,0x0F,0x07,0x0E,0x78,0x3E,0x1E,0x1E,0x78, +0xFC,0x78,0x1C,0xFF,0xFF,0xE0,0x38,0xFF,0x7F,0x80, +0x38,0x78,0x7C,0x00,0x78,0x00,0x00,0x38,0x78,0x00, +0x01,0xE0,0x7C,0x00,0x07,0x80,0x7F,0x00,0x7E,0x00, +0x7F,0xFF,0xF8,0x00,0x3F,0xFF,0xC0,0x00,0x0F,0xFC, +0x00,0x0A,0xE0,0x00,0x5A,0x40,0x3E,0x01,0x20,0x3B, +0x80,0x80,0x38,0xE0,0x01,0xE3,0x81,0x00,0xE0,0xE0, +0x90,0xE0,0x38,0x48,0xFF,0xFE,0x24,0xE0,0x03,0x90, +0xE0,0x00,0xE7,0x80,0x03,0x9C,0x00,0x07,0x08,0xE0, +0xC0,0x59,0xFF,0xE0,0x7F,0xFE,0x1F,0xFF,0xC7,0x00, +0xF1,0xC0,0x1E,0x9E,0x00,0x73,0x80,0x38,0xE0,0x1E, +0x47,0xFF,0xE1,0xFF,0xFC,0x70,0x07,0x9C,0x00,0xFA, +0xE0,0x03,0xB8,0x01,0xEE,0x00,0xF3,0xFF,0xFC,0xFF, +0xFE,0x3F,0xFE,0x00,0x0A,0x60,0x80,0x60,0x03,0xF0, +0x00,0x7F,0xE0,0x07,0xFF,0xC0,0x78,0x1E,0x07,0x80, +0x78,0x78,0x01,0xE3,0x80,0x07,0x1C,0x00,0x23,0x78, +0x00,0x01,0xC0,0x00,0x87,0x00,0x07,0x38,0x00,0x79, +0xE0,0x03,0x87,0x80,0x3C,0x1F,0x07,0xC0,0xFF,0xFC, +0x01,0xFF,0xC0,0x03,0xF8,0x00,0x09,0xE0,0xC0,0x61, +0xFF,0xF0,0x1F,0xFF,0xC1,0xFF,0xFE,0x1C,0x01,0xF1, +0xC0,0x0F,0x1C,0x00,0x7A,0x38,0x00,0x76,0xF0,0x00, +0x77,0x00,0x07,0x8E,0x00,0x1C,0xE0,0x03,0xCE,0x00, +0x78,0xE0,0x0F,0x8F,0xFF,0xF0,0xFF,0xFE,0x0F,0xFF, +0x00,0x08,0xE0,0xC0,0x5A,0x7F,0xFF,0xDB,0xC0,0x00, +0x9F,0xFF,0xE6,0xF0,0x00,0x1C,0x00,0x09,0xFF,0xFF, +0x80,0x07,0xE0,0xC0,0x52,0x7F,0xFF,0xEF,0x00,0x09, +0xFF,0xF9,0xBC,0x00,0x2B,0x80,0x00,0x0B,0x60,0x80, +0x68,0x01,0xFC,0x00,0x1F,0xFF,0x00,0x7F,0xFF,0x01, +0xF8,0x1F,0x07,0x80,0x0F,0x0E,0x00,0x0E,0x38,0x00, +0x1C,0x70,0x00,0x19,0xE0,0x00,0x04,0xF0,0x00,0x01, +0x3C,0x01,0xFF,0xB8,0x00,0x07,0x87,0x00,0x01,0xC7, +0x00,0x03,0x8F,0x00,0x0F,0x0F,0xC0,0xFE,0x0F,0xFF, +0xF8,0x07,0xFF,0xC0,0x03,0xFC,0x00,0x09,0x60,0xC0, +0x63,0x78,0x00,0x79,0xE0,0x01,0xE7,0xFF,0xFF,0xDE, +0x00,0x1E,0xB8,0x00,0x70,0x01,0xE0,0xC0,0x27,0x7E, +0xFD,0xF3,0xC0,0x06,0xE0,0x40,0x47,0x40,0x0F,0xA0, +0x07,0x90,0x03,0xC7,0x01,0xDE,0x0F,0x78,0x78,0xFF, +0xE1,0xFF,0x03,0xF0,0x0A,0x60,0xC0,0x59,0xC0,0x03, +0xCE,0x00,0x3C,0x70,0x03,0xC3,0x80,0x3C,0x1C,0x03, +0xC0,0xE0,0x3C,0x07,0x03,0xC0,0x38,0x3C,0x01,0xC3, +0xC0,0x0E,0x3C,0x00,0x73,0xC0,0x03,0xBF,0x00,0x1F, +0xFC,0x00,0xFC,0xE0,0x07,0xC7,0x80,0x3C,0x1E,0x01, +0xC0,0x78,0x0E,0x01,0xE0,0x70,0x07,0x83,0x80,0x1C, +0x1C,0x00,0x70,0xE0,0x03,0xC7,0x00,0x0F,0x38,0x00, +0x3C,0x07,0x60,0xC0,0x4B,0x78,0x00,0xDE,0x00,0x37, +0x80,0x09,0xFF,0xFC,0x0B,0xE0,0x80,0x6D,0xF0,0x00, +0x7D,0xF8,0x00,0x7E,0x3F,0x00,0x1F,0xBF,0x80,0x1F, +0xCF,0x70,0x07,0x79,0xE7,0x01,0xCF,0x3C,0x70,0x71, +0xE7,0x87,0x1C,0x3C,0xF0,0x77,0x07,0x9E,0x07,0xC0, +0xEE,0x03,0x80,0xE0,0x09,0x60,0xC0,0x62,0x3C,0x00, +0x78,0xF8,0x01,0xDF,0x80,0x3C,0x77,0x00,0xF1,0xCE, +0x03,0xB8,0xE0,0x78,0xE1,0xC1,0xE3,0x83,0x87,0x70, +0x38,0xF1,0xC0,0x73,0xC7,0x00,0xEE,0xE0,0x0F,0xE3, +0x80,0x1F,0x8E,0x00,0x3C,0x0B,0x60,0x80,0x68,0x01, +0xF8,0x00,0x1F,0xFE,0x00,0x7F,0xFE,0x01,0xF0,0x3E, +0x07,0x80,0x1E,0x1E,0x00,0x1C,0x87,0x00,0x03,0x9C, +0x00,0x07,0xEF,0x00,0x00,0xF0,0xE0,0x00,0x70,0xE0, +0x01,0xE1,0xE0,0x07,0x81,0xF0,0x3E,0x01,0xFF,0xF8, +0x01,0xFF,0xE0,0x00,0x7E,0x00,0x08,0xE0,0xC0,0x59, +0xFF,0xF0,0x7F,0xFF,0x1F,0xFF,0xE7,0x00,0x79,0xC0, +0x0F,0xAE,0x00,0x3B,0x80,0x1E,0xE0,0x0F,0x3F,0xFF, +0xCF,0xFF,0xE3,0xFF,0xE1,0xBC,0x00,0x09,0xE0,0x00, +0x00,0x0B,0x64,0xBF,0x68,0x03,0xF8,0x00,0x1F,0xFC, +0x00,0x7F,0xFC,0x01,0xF0,0x7C,0x07,0x80,0x3C,0x1E, +0x00,0x3C,0x87,0x00,0x07,0x37,0x80,0x00,0xE7,0x00, +0x01,0xC7,0x00,0x07,0x0E,0x03,0x0E,0x1E,0x07,0xB8, +0x1E,0x07,0xF0,0x1F,0x07,0xC0,0x1F,0xFF,0xC0,0x1F, +0xFF,0xC0,0x0F,0xE3,0xE0,0x00,0x03,0x80,0x09,0xE0, +0xC0,0x61,0xFF,0xF8,0x1F,0xFF,0xE1,0xFF,0xFF,0x1C, +0x00,0xF1,0xC0,0x07,0xA7,0x80,0x07,0x38,0x00,0xF3, +0x80,0x1E,0x3F,0xFF,0xE3,0xFF,0xFC,0x3F,0xFF,0x03, +0x81,0xC0,0x38,0x0E,0x03,0x80,0xF0,0x38,0x07,0x83, +0x80,0x38,0x38,0x03,0xC3,0x80,0x1E,0x38,0x00,0xE3, +0x80,0x0F,0x38,0x00,0x73,0x80,0x07,0x80,0x09,0x60, +0x80,0x58,0x07,0xE0,0x07,0xFF,0x01,0xFF,0xF0,0x3C, +0x0F,0x0F,0x00,0xE4,0x38,0x01,0xC7,0x00,0x00,0xF0, +0x00,0x0F,0x80,0x00,0xFF,0x00,0x0F,0xFC,0x00,0x3F, +0xE0,0x00,0x7E,0x00,0x03,0xC0,0x00,0x3E,0x38,0x00, +0x77,0x80,0x0E,0x78,0x03,0xCF,0xC1,0xF0,0xFF,0xFC, +0x0F,0xFF,0x00,0x3F,0x80,0x09,0xE0,0x40,0x56,0x7F, +0xFF,0xFE,0x80,0x70,0x0D,0x00,0xE0,0x1A,0x01,0xC0, +0x00,0x09,0x60,0xC0,0x63,0x78,0x00,0x7D,0xE0,0x01, +0xEB,0x80,0x07,0x38,0x01,0xC7,0x00,0x78,0xF8,0x1F, +0x0F,0xFF,0xC0,0xFF,0xF0,0x07,0xF8,0x00,0x0A,0xE0, +0x40,0x59,0xC0,0x00,0x77,0x80,0x03,0xE1,0xC0,0x01, +0xC7,0x80,0x0F,0x41,0xC0,0x07,0x03,0x80,0x3C,0x81, +0xC0,0x1C,0x48,0x70,0x1C,0x20,0x1C,0x1C,0x00,0x78, +0xF0,0x40,0x1C,0x70,0x00,0x7B,0xC0,0x80,0x1D,0xC0, +0x00,0x7F,0x01,0x00,0x1F,0x00,0x10,0xE0,0x00,0x8A, +0x38,0x00,0xF8,0x00,0xE7,0x00,0x3E,0x00,0x74,0xB8, +0x03,0xB8,0x03,0x87,0x01,0xC6,0x01,0xC8,0x38,0x0E, +0x38,0x0E,0x07,0x03,0x8E,0x07,0x12,0x38,0x38,0x38, +0x38,0x07,0x1E,0x06,0x1C,0x24,0x38,0xE0,0x38,0xE1, +0x40,0xEE,0x00,0xEE,0x09,0x03,0xE0,0x03,0xE0,0x00, +0x0A,0xE0,0x00,0x54,0xF0,0x01,0xE1,0xE0,0x0F,0x03, +0x80,0x38,0x0F,0x01,0xE0,0x1E,0x0F,0x00,0x38,0x38, +0x00,0x71,0xC0,0x01,0xEF,0x00,0x03,0xB8,0x08,0x00, +0xF8,0x00,0x01,0xC0,0x00,0x0F,0x80,0x40,0x0E,0xE0, +0x00,0x7B,0xC0,0x03,0xC7,0x80,0x0E,0x0E,0x00,0x70, +0x1C,0x03,0xC0,0x78,0x1E,0x00,0xF0,0x70,0x01,0xC3, +0xC0,0x07,0x9E,0x00,0x0F,0x0A,0xE0,0x00,0x55,0xC0, +0x00,0xF3,0x80,0x07,0x87,0x00,0x1C,0x1E,0x00,0xF0, +0x38,0x07,0x80,0x70,0x1C,0x01,0xE0,0xF0,0x03,0x83, +0x82,0x00,0xE3,0x80,0x01,0xDC,0x00,0x07,0xF0,0x00, +0x0F,0x80,0x68,0x03,0x80,0x28,0x01,0xC0,0x00,0x09, +0xE0,0x00,0x52,0x5F,0xFF,0xF0,0x00,0x0F,0x00,0x01, +0xE0,0x00,0x3C,0x00,0x03,0x80,0x00,0x70,0x00,0x0F, +0x00,0x01,0xE0,0x00,0x3C,0x00,0x03,0x80,0x00,0x70, +0x00,0x0F,0x00,0x01,0xE0,0x00,0x3C,0x00,0x03,0x80, +0x00,0x70,0x00,0x0F,0x00,0x01,0xE0,0x00,0x3C,0x00, +0x04,0xFF,0xFF,0xF0,0x03,0x7C,0xB9,0x26,0x7F,0xDE, +0x37,0x8D,0xE2,0xB8,0x9F,0xC0,0x04,0xE0,0x40,0x26, +0x30,0x12,0xC0,0xA3,0x04,0x8C,0x24,0x30,0x0E,0x48, +0x32,0x40,0xC0,0x38,0x06,0x03,0x7C,0x79,0x26,0x7F, +0xD1,0xF4,0x7D,0x1E,0x87,0x9F,0xC0,0x06,0x34,0x4B, +0x38,0x0C,0x12,0x1E,0x01,0xF8,0x0C,0xC0,0xE6,0x07, +0x38,0x30,0xC8,0x70,0xE3,0x03,0x38,0x1C,0x09,0x8F, +0xF9,0x4A,0x7F,0xFF,0xF8,0x03,0x14,0x53,0x2D,0xE1, +0xE1,0xC1,0x81,0x80,0x07,0xC8,0x40,0x44,0x1F,0xC0, +0x7F,0xF0,0xFF,0xF1,0xE0,0x79,0xC0,0x38,0x00,0x38, +0x00,0xF8,0x1F,0xF8,0x7F,0xF8,0xFF,0xB9,0xE0,0x3A, +0x38,0x07,0x38,0x0F,0x3C,0x3F,0x1F,0xFF,0x1F,0xF7, +0x07,0xE3,0x80,0x07,0xE0,0x80,0x4B,0x38,0x00,0x38, +0xF0,0x3B,0xFC,0x3F,0xFE,0x3F,0x1F,0x3C,0x07,0x3C, +0x07,0xE7,0x00,0x77,0x80,0xF7,0x80,0xE7,0xC3,0xE7, +0xFF,0xC7,0x7F,0x87,0x1E,0x00,0x07,0xC8,0x40,0x44, +0x0F,0xC0,0x3F,0xE0,0x7F,0xF0,0xF8,0x78,0xE0,0x39, +0xE0,0x1E,0xF8,0x00,0x38,0x03,0xBC,0x03,0x9C,0x07, +0x1F,0x0F,0x0F,0xFE,0x07,0xFC,0x01,0xF8,0x00,0x07, +0xE0,0x40,0x4B,0x00,0x03,0x81,0xE3,0x87,0xFB,0x8F, +0xFF,0x9E,0x1F,0x9C,0x07,0xBC,0x07,0xE7,0x00,0x77, +0x80,0xF3,0x80,0xF3,0xE1,0xF1,0xFF,0xF0,0xFF,0x70, +0x3C,0x70,0x07,0xC8,0x40,0x44,0x0F,0x80,0x3F,0xE0, +0x7F,0xF0,0xF0,0x78,0xE0,0x3A,0x38,0x03,0xCF,0xFF, +0xF8,0xE0,0x00,0xF0,0x00,0x70,0x0E,0x7C,0x3C,0x3F, +0xFC,0x1F,0xF8,0x07,0xE0,0x05,0x60,0x40,0x28,0x1F, +0x87,0xE1,0xFD,0x27,0x04,0xFF,0x9A,0x70,0x69,0xC0, +0x38,0x00,0x07,0xE4,0x79,0x48,0x0F,0x9C,0x3F,0xDC, +0x7F,0xFC,0xF8,0xFC,0xE0,0x3D,0xE0,0x3F,0x38,0x03, +0xBC,0x07,0x9C,0x07,0x9E,0x1F,0x8F,0xFF,0x87,0xFB, +0x81,0xF3,0x80,0x03,0xB8,0x03,0xB8,0x07,0x3E,0x0F, +0x1F,0xFE,0x0F,0xFC,0x03,0xF0,0x00,0x07,0x60,0x80, +0x4B,0x38,0x00,0x71,0xF0,0xEF,0xF1,0xFF,0xF3,0xE1, +0xF7,0x81,0xFB,0xC0,0x3E,0x70,0x0E,0x01,0xE0,0x80, +0x1E,0x7C,0x8D,0xFB,0xEB,0x80,0x03,0x7F,0xF9,0x1E, +0x47,0x90,0x34,0x7D,0x1F,0x47,0x1E,0xFD,0xF3,0xC0, +0x07,0x60,0x80,0x43,0x38,0x00,0x70,0x1E,0xE0,0x79, +0xC1,0xE3,0x87,0x87,0x1E,0x0E,0x78,0x1D,0xE0,0x3F, +0xC0,0x7F,0xC0,0xF7,0x81,0xC7,0x83,0x87,0x07,0x0F, +0x0E,0x0E,0x1C,0x0E,0x38,0x1E,0x70,0x1C,0xE0,0x3C, +0x01,0xE0,0x80,0x1F,0x7E,0xFD,0xF3,0xC0,0x0B,0xC8, +0x80,0x6D,0xC7,0x81,0xE1,0xDF,0xC7,0xF9,0xFF,0xEF, +0xF9,0xF0,0xFC,0x3D,0xE0,0x78,0x1F,0x78,0x0E,0x03, +0xE7,0x01,0xC0,0x70,0x07,0x48,0x80,0x49,0xC7,0xC3, +0xBF,0xC7,0xFF,0xCF,0x87,0xDE,0x07,0xEF,0x00,0xF9, +0xC0,0x38,0x07,0xC8,0x40,0x44,0x0F,0x80,0x3F,0xE0, +0x7F,0xF0,0xF8,0xF8,0xE0,0x39,0xE0,0x3F,0x38,0x03, +0xBC,0x07,0x9C,0x07,0x1F,0x1F,0x0F,0xFE,0x07,0xFC, +0x01,0xF0,0x00,0x07,0xE4,0xB9,0x49,0xC7,0x81,0xDF, +0xE1,0xFF,0xF1,0xF8,0xF9,0xE0,0x39,0xE0,0x3F,0x38, +0x03,0xC7,0x80,0xE7,0xC3,0xE7,0xFF,0xC7,0x7F,0x87, +0x3E,0x0D,0xE0,0x00,0x07,0xE4,0x79,0x48,0x0F,0x1C, +0x3F,0xDC,0x7F,0xDC,0xF0,0xFC,0xE0,0x3D,0xE0,0x3F, +0x38,0x03,0xC3,0x80,0xF3,0xE1,0xF1,0xFF,0xF0,0xFF, +0x70,0x3E,0x7D,0x00,0x0E,0x04,0xC8,0x80,0x2D,0xCF, +0x77,0xDF,0xE7,0xC1,0xE0,0xDE,0x06,0x70,0x00,0x07, +0xC8,0x40,0x44,0x1F,0x80,0x7F,0xE0,0xFF,0xF1,0xE0, +0x79,0xC0,0x39,0xC0,0x01,0xF0,0x00,0xFF,0x80,0x7F, +0xE0,0x3F,0xF8,0x03,0xFC,0x00,0x3D,0xC0,0x1D,0xE0, +0x1C,0xF0,0x3C,0xFF,0xF8,0x7F,0xF0,0x1F,0xC0,0x04, +0x60,0x00,0x24,0x11,0x67,0x13,0xFF,0xA7,0x16,0x71, +0x07,0xE0,0xF0,0x07,0x48,0x80,0x4B,0x78,0x07,0xCE, +0x01,0xDE,0x07,0xBE,0x1F,0x3F,0xEE,0x3F,0xDC,0x3E, +0x38,0x07,0xC8,0x00,0x3D,0xC0,0x1C,0xE0,0x1E,0x1C, +0x07,0x0C,0x06,0x41,0xC1,0xC0,0xC1,0x88,0x1C,0x70, +0x0C,0x61,0x01,0xDC,0x00,0xD8,0x20,0x1F,0x04,0x01, +0xC0,0x0B,0xC8,0x00,0x5E,0x38,0x0E,0x03,0xB8,0x1F, +0x03,0x9C,0x1F,0x07,0x43,0x83,0x60,0xE1,0x87,0x70, +0xC8,0x38,0xC6,0x38,0x38,0xC6,0x30,0x1D,0xC7,0x71, +0x03,0xB0,0x6E,0x01,0xB0,0x6C,0x20,0x3E,0x0F,0x84, +0x03,0x80,0xE0,0x07,0xC8,0x00,0x3D,0xC0,0x1C,0xE0, +0x38,0xF0,0x78,0x70,0x70,0x38,0xE0,0x3D,0xE0,0x1D, +0xC0,0x1F,0xC2,0x01,0xF0,0x03,0xF8,0x03,0xB8,0x07, +0xBC,0x07,0x1C,0x0E,0x0E,0x1E,0x0F,0x1C,0x07,0x38, +0x03,0x80,0x07,0xE4,0x39,0x3D,0xC0,0x1C,0xE0,0x3E, +0x1C,0x07,0x0E,0x0F,0x41,0xC1,0xC0,0xE3,0xC8,0x1C, +0x70,0x0E,0xF1,0x01,0xDC,0x00,0xFC,0x20,0x1F,0x00, +0x0F,0x04,0x81,0xC0,0x80,0x70,0x10,0x7C,0x00,0x78, +0x00,0x07,0xC8,0x00,0x42,0x5F,0xFF,0x80,0x07,0x80, +0x0F,0x00,0x1E,0x00,0x3C,0x00,0x78,0x00,0xF0,0x01, +0xE0,0x03,0xC0,0x07,0x80,0x0F,0x00,0x1E,0x00,0x3C, +0x00,0x4F,0xFF,0xF0,0x04,0xFC,0x79,0x2C,0x0F,0x07, +0xC3,0xF0,0xF3,0x47,0x01,0xC0,0xF0,0x38,0x3C,0x0C, +0x03,0xC1,0x07,0x0D,0x1C,0x07,0x01,0xE0,0x7E,0x0F, +0x81,0xE0,0x01,0x7C,0xF9,0x23,0x7D,0xF7,0xDE,0x70, +0x04,0xFC,0x79,0x2D,0xE0,0x7C,0x1F,0x81,0xE3,0x47, +0x01,0xC0,0x78,0x0E,0x01,0xE0,0x18,0x1E,0x0E,0x07, +0x9A,0x38,0x0E,0x07,0x87,0xE1,0xF0,0x78,0x00,0x08, +0x18,0x48,0x4C,0x7C,0x00,0x7F,0x01,0x7F,0xE1,0xB0, +0xFF,0xD0,0x1F,0xC0,0x07,0xC0,}; +/* font data size: 2966 bytes */ + +static const unsigned char Arial_24_index[] = { +0x00,0x00,0x04,0x00, +0xD0,0x14,0x03,0x20,0x67,0x0A,0x80,0xE6,0x0E,0xC1, +0x07,0x12,0x21,0x32,0x13,0xD1,0x44,0x14,0xA1,0x4F, +0x16,0x21,0x89,0x19,0xB1,0xCB,0x1F,0xD2,0x24,0x24, +0x92,0x7A,0x29,0xA2,0xC3,0x2F,0x42,0xFC,0x30,0x63, +0x28,0x33,0x33,0x55,0x38,0x13,0xFD,0x42,0x24,0x50, +0x48,0x44,0xB1,0x4C,0x54,0xD5,0x51,0x15,0x23,0x52, +0xB5,0x40,0x58,0x35,0x90,0x5B,0x85,0xE1,0x61,0x46, +0x37,0x67,0x06,0xAC,0x6E,0x56,0xF5,0x71,0x07,0x40, +0x77,0x67,0xB7,0x7E,0x38,0x1A,0x82,0x68,0x39,0x84, +0x58,0x5A,0x86,0x18,0x6A,0x89,0x18,0xB2,0x8D,0x38, +0xF4,0x91,0x59,0x26,0x95,0x39,0x67,0x97,0x09,0x7E, +0x9A,0x69,0xAE,0x9C,0x89,0xDA,0x9F,0x9A,0x18,0xA3, +0x7A,0x45,0xA6,0xDA,0x7B,0xA8,0xDA,0xAB,0xAD,0x5A, +0xFC,0xB2,0x3B,0x44,0xB6,0x0B,0x68,0xB8,0x50, +}; +/* font index size: 143 bytes */ + +const ILI9341_t3_font_t Arial_24 = { + Arial_24_index, + 0, + Arial_24_data, + 1, + 0, + 32, + 126, + 0, + 0, + 12, + 6, + 5, + 4, + 6, + 6, + 35, + 24 +}; + + + +static const unsigned char Arial_28_data[] = { +0x00,0x00,0x00,0x16,0x01,0xB8,0x80,0x17,0xBF,0x79, +0xEA,0x91,0x3C,0x05,0x94,0x29,0x1D,0xBC,0x1D,0xC1, +0xC8,0x0C,0x80,0x80,0x0B,0x38,0x00,0x2D,0x00,0x1C, +0x0E,0x00,0x78,0x38,0xA0,0x1C,0x0E,0x00,0x70,0x38, +0x4F,0xFF,0xFF,0xE0,0x38,0x3C,0x28,0x1C,0x0E,0x00, +0x78,0x38,0x13,0xFF,0xFF,0xF8,0x38,0x1C,0x0A,0x1C, +0x0E,0x00,0x38,0x3C,0x04,0x1C,0x0E,0x00,0x09,0x40, +0x3E,0xAC,0x00,0xC0,0x00,0x7E,0x00,0x3F,0xF0,0x0F, +0xFF,0x03,0xCC,0xF0,0xF1,0x8E,0x43,0x86,0x1D,0x0E, +0x18,0x01,0xE3,0x00,0x1E,0x60,0x03,0xFC,0x00,0x3F, +0xE0,0x01,0xFF,0x00,0x0F,0xF8,0x00,0xCF,0x80,0x18, +0x74,0x80,0x60,0xF1,0xC1,0x83,0xBC,0x30,0xF3,0xC6, +0x3C,0x7C,0xCF,0x87,0xFF,0xE0,0x7F,0xF8,0x01,0xFC, +0x12,0x01,0x80,0x00,0x0F,0xB8,0x40,0x46,0x1F,0x00, +0x03,0x80,0x3F,0xC0,0x07,0x80,0x79,0xE0,0x07,0x00, +0x70,0xE0,0x0F,0x00,0xE0,0x70,0x0E,0x00,0xE0,0x70, +0x1C,0x00,0xE0,0x70,0x3C,0x00,0xE0,0x70,0x38,0x00, +0xE0,0x70,0x78,0x00,0xE0,0x70,0x70,0x00,0xE0,0x70, +0xE0,0x00,0x70,0xE0,0xE0,0x00,0x79,0xE1,0xC0,0x00, +0x3F,0xC3,0xC3,0xE0,0x0F,0x03,0x87,0xF8,0x00,0x07, +0x8F,0x3C,0x00,0x07,0x0E,0x1D,0x00,0x01,0xC3,0x81, +0xC0,0x03,0x83,0x81,0xC0,0x07,0x83,0x81,0xC0,0x07, +0x03,0x81,0xC0,0x0F,0x03,0x81,0xC0,0x0E,0x03,0x81, +0xC0,0x1C,0x01,0xC3,0x80,0x3C,0x01,0xE7,0x80,0x38, +0x00,0xFF,0x00,0x78,0x00,0x3C,0x00,0x0B,0xB8,0x40, +0x34,0x01,0xF8,0x00,0x07,0xFE,0x00,0x0F,0xFF,0x00, +0x0F,0x0F,0x00,0x1E,0x07,0x81,0x23,0x80,0x70,0x01, +0xC0,0xE0,0x01,0xE3,0xE0,0x00,0xFF,0xC0,0x00,0x7F, +0x00,0x00,0xFE,0x00,0x01,0xFC,0x00,0x03,0xFE,0x00, +0x07,0x8F,0x04,0x0F,0x07,0x8F,0x1E,0x03,0x8F,0x1C, +0x01,0xDE,0x1C,0x01,0xFE,0x1C,0x00,0xFE,0x1C,0x00, +0x7C,0x1E,0x00,0x7C,0x0F,0x00,0xFE,0x0F,0x83,0xFF, +0x07,0xFF,0xE7,0xC1,0xFF,0x83,0x80,0x7E,0x01,0x00, +0x01,0x94,0x49,0x0F,0xBE,0x39,0x00,0x04,0x48,0x5C, +0x1A,0x03,0x03,0x03,0x81,0x81,0xC0,0xC4,0x1C,0x0C, +0x25,0xC3,0x78,0x2B,0x80,0xC1,0x2E,0x03,0x08,0x38, +0x0C,0x07,0x01,0x80,0xE0,0x30,0x0C,0x04,0x48,0x7C, +0x1A,0xC0,0x30,0x1C,0x06,0x03,0x80,0xC4,0x0E,0x03, +0x24,0x38,0x0D,0xA0,0xF2,0x0E,0x06,0x90,0xE0,0x64, +0x0E,0x06,0x07,0x03,0x03,0x81,0x81,0x80,0x06,0x98, +0x28,0x1F,0x20,0xE0,0x23,0x89,0xEE,0xF7,0xFF,0xC7, +0xFC,0x07,0xC0,0x3B,0x81,0xEF,0x07,0x1C,0x08,0x20, +0x09,0xA6,0x42,0x2F,0xA0,0x1C,0x00,0x01,0xC0,0x27, +0xFF,0xFF,0xE8,0x07,0x00,0x00,0x70,0x00,0x01,0x92, +0x7D,0x17,0x3E,0x9B,0x20,0x05,0x86,0x24,0x1B,0x3F, +0xFC,0x01,0x86,0x60,0x17,0x3C,0x05,0xB8,0x00,0x17, +0x00,0x1E,0x40,0x75,0x01,0xC9,0x07,0x14,0x1C,0x24, +0x70,0x51,0xC0,0x97,0x01,0x1C,0x00,0x09,0x38,0x40, +0x2C,0x03,0xF0,0x01,0xFF,0x80,0x7F,0xF8,0x1F,0x0F, +0x83,0x80,0x72,0x5C,0x00,0xED,0xE0,0x01,0xEF,0x80, +0x07,0x97,0x00,0x38,0x70,0x0E,0x0F,0x87,0xC0,0xFF, +0xF0,0x0F,0xFC,0x00,0x7E,0x00,0x05,0xB8,0x80,0x2C, +0x00,0x60,0x0E,0x01,0xE0,0x3E,0x07,0xE1,0xFE,0x7F, +0xEF,0xCE,0xF0,0xEC,0x0F,0xA0,0x1F,0x40,0x3D,0x00, +0x70,0x09,0xB8,0x20,0x2C,0x03,0xF8,0x00,0xFF,0xE0, +0x3F,0xFF,0x83,0xE0,0xFC,0x78,0x03,0xC7,0x00,0x1F, +0x1C,0x00,0x1E,0x00,0x00,0x38,0x00,0x07,0x80,0x00, +0x70,0x00,0x0F,0x00,0x01,0xE0,0x00,0x3C,0x00,0x07, +0x80,0x00,0xF0,0x00,0x1E,0x00,0x03,0xC0,0x00,0x78, +0x00,0x1F,0x00,0x03,0xC0,0x00,0x78,0x00,0x0F,0x00, +0x01,0xC0,0x00,0x1F,0xFF,0xFC,0x7F,0xFF,0xF0,0x09, +0x38,0x40,0x2C,0x07,0xF0,0x03,0xFF,0x80,0xFF,0xF8, +0x3E,0x0F,0x87,0x00,0x71,0xE0,0x07,0x38,0x00,0xE8, +0x00,0x03,0x80,0x00,0xF0,0x00,0x1C,0x00,0x0F,0x10, +0x03,0xF8,0x00,0x7F,0xC0,0x00,0x3C,0x00,0x03,0x80, +0x00,0x7C,0x00,0x00,0xF1,0xC0,0x03,0x9C,0x00,0xF3, +0xC0,0x3C,0x3C,0x0F,0x07,0xFF,0xC0,0x3F,0xF0,0x01, +0xF8,0x00,0x09,0xB8,0x20,0x2C,0x00,0x07,0x00,0x00, +0xF0,0x00,0x1F,0x10,0x00,0x7E,0x00,0x0F,0xE0,0x01, +0xEE,0x00,0x1C,0xE0,0x03,0x8E,0x00,0x78,0xE0,0x0F, +0x0E,0x00,0xE0,0xE0,0x1C,0x0E,0x03,0xC0,0xE0,0x38, +0x0E,0x07,0x00,0xE0,0xF0,0x0E,0x1E,0x00,0xE2,0x7F, +0xFF,0xFE,0x80,0x03,0x80,0x09,0x38,0x40,0x2D,0x03, +0xFF,0xF0,0xFF,0xFE,0xA3,0x80,0x02,0x1C,0x00,0x03, +0x9F,0x80,0x7F,0xFC,0x0F,0xFF,0xC3,0xE0,0x3C,0x78, +0x03,0xC0,0x00,0x3A,0xC0,0x00,0x77,0x00,0x0E,0xE0, +0x03,0x8E,0x00,0x71,0xC0,0x1E,0x1E,0x07,0x83,0xFF, +0xE0,0x3F,0xF8,0x00,0xFC,0x00,0x09,0xB8,0x20,0x2C, +0x01,0xFC,0x00,0x7F,0xF0,0x0F,0xFF,0x81,0xF0,0x7C, +0x3C,0x01,0xC3,0x80,0x1E,0x78,0x00,0xF0,0xE0,0x00, +0x1C,0x00,0x01,0xC3,0xF0,0x1C,0xFF,0xC1,0xDF,0xFE, +0x1F,0xC0,0xF1,0xF0,0x07,0x9E,0x00,0x3A,0xB8,0x00, +0x39,0x80,0x03,0x9C,0x00,0x39,0xC0,0x07,0x0E,0x00, +0xF0,0xF8,0x1E,0x07,0xFF,0xC0,0x1F,0xF8,0x00,0x7E, +0x00,0x09,0x38,0x40,0x2D,0x3F,0xFF,0xF8,0x00,0x06, +0x00,0x01,0x80,0x00,0x60,0x00,0x1C,0x00,0x07,0x00, +0x00,0xC0,0x00,0x38,0x20,0x01,0xC0,0x80,0x0E,0x02, +0x40,0x70,0x09,0x03,0x80,0x28,0x1C,0x00,0xA0,0xE0, +0x00,0x09,0x38,0x40,0x2C,0x03,0xF0,0x01,0xFF,0x80, +0x7F,0xF8,0x1E,0x07,0x87,0x80,0x7A,0x9C,0x00,0xE3, +0xC0,0x3C,0x3C,0x0F,0x03,0xFF,0xC0,0x3F,0xE0,0x0F, +0xFF,0x03,0xC0,0xF0,0xF0,0x0F,0x3C,0x00,0xEB,0xE0, +0x01,0xDE,0x00,0x79,0xC0,0x0E,0x1E,0x07,0x83,0xFF, +0xF0,0x1F,0xF8,0x00,0xFC,0x00,0x09,0x38,0x40,0x2C, +0x03,0xF0,0x01,0xFF,0x80,0xFF,0xF8,0x1E,0x07,0x87, +0x80,0x70,0xE0,0x07,0x3C,0x00,0x67,0x00,0x0D,0x5C, +0x00,0x39,0xC0,0x0F,0x3C,0x03,0xE7,0xC0,0xFC,0x7F, +0xFB,0x87,0xFE,0x70,0x3F,0x0E,0x00,0x01,0xE0,0x00, +0x0E,0x70,0x01,0xCE,0x00,0x70,0xE0,0x1E,0x1E,0x07, +0x81,0xFF,0xE0,0x1F,0xF8,0x00,0xFC,0x00,0x01,0xAA, +0x60,0x17,0x3F,0x46,0x80,0x9E,0x01,0xB6,0x7D,0x17, +0x3F,0x46,0x80,0x9F,0x4D,0x90,0x09,0xA6,0x42,0x2E, +0x00,0x00,0x20,0x00,0x1E,0x00,0x07,0xE0,0x01,0xFC, +0x00,0xFE,0x00,0x3F,0x80,0x0F,0xC0,0x07,0xF0,0x00, +0xF8,0x00,0x0E,0x00,0x00,0xF8,0x00,0x07,0xF0,0x00, +0x0F,0xC0,0x00,0x3F,0x80,0x00,0xFE,0x00,0x01,0xFC, +0x00,0x07,0xE0,0x00,0x1E,0x00,0x00,0x20,0x09,0x98, +0x44,0x2F,0x3F,0xFF,0xFF,0x00,0x00,0x04,0xFF,0xFF, +0xF0,0x09,0xA6,0x42,0x2E,0x80,0x00,0x0F,0x00,0x00, +0xFC,0x00,0x07,0xF0,0x00,0x0F,0xE0,0x00,0x3F,0x80, +0x00,0x7E,0x00,0x01,0xFC,0x00,0x03,0xE0,0x00,0x0E, +0x00,0x03,0xE0,0x01,0xFC,0x00,0x7E,0x00,0x3F,0x80, +0x0F,0xE0,0x07,0xF0,0x00,0xFC,0x00,0x0F,0x00,0x00, +0x80,0x00,0x00,0x09,0x38,0x40,0x2C,0x03,0xF0,0x01, +0xFF,0xC0,0xFF,0xFC,0x1E,0x07,0xC7,0x80,0x78,0xE0, +0x07,0xC7,0x00,0x0E,0x00,0x01,0xC0,0x00,0x78,0x00, +0x0E,0x00,0x03,0xC0,0x01,0xF0,0x00,0x7C,0x00,0x1F, +0x00,0x03,0xC0,0x00,0xF0,0x00,0x3C,0x05,0x00,0xE0, +0x12,0x00,0x00,0x48,0x0E,0x00,0x12,0x48,0x5C,0x50, +0x00,0x03,0xFE,0x00,0x00,0x00,0xFF,0xFE,0x00,0x00, +0x1F,0xFF,0xFC,0x00,0x03,0xFC,0x03,0xF8,0x00,0x3F, +0x00,0x07,0xE0,0x03,0xE0,0x00,0x0F,0x80,0x3C,0x00, +0x00,0x3C,0x01,0xC0,0x3E,0x1C,0xF0,0x1E,0x07,0xFC, +0xE3,0xC1,0xE0,0x7F,0xF7,0x0E,0x0E,0x07,0x83,0xF0, +0x70,0xF0,0x78,0x07,0x81,0xC7,0x07,0x80,0x3C,0x0E, +0x38,0x78,0x00,0xE0,0x73,0xC3,0x80,0x07,0x03,0x9C, +0x1C,0x00,0x30,0x1C,0xE1,0xE0,0x01,0x80,0xE7,0x0E, +0x00,0x0C,0x07,0x47,0x0E,0x00,0x1C,0x0E,0x38,0x70, +0x00,0xE0,0xF1,0xC3,0x80,0x0E,0x07,0x0E,0x1E,0x00, +0xF0,0x78,0x78,0x70,0x0F,0x87,0x81,0xC3,0xE1,0xFC, +0x78,0x0E,0x0F,0xFE,0xFF,0x80,0x78,0x3F,0xE7,0xF8, +0x01,0xE0,0x7C,0x1F,0x03,0x8F,0x00,0x00,0x00,0x38, +0x3E,0x00,0x00,0x03,0x80,0xF8,0x00,0x00,0x78,0x03, +0xF0,0x00,0x0F,0x80,0x0F,0xF0,0x03,0xF8,0x00,0x1F, +0xFF,0xFF,0x80,0x00,0x3F,0xFF,0xF0,0x00,0x00,0x1F, +0xF8,0x00,0x00,0x0C,0xB8,0x20,0x35,0x20,0x07,0xC0, +0x08,0x00,0x77,0x00,0x00,0x3D,0xE0,0x10,0x01,0xC7, +0x00,0x80,0x1C,0x1C,0x00,0x0F,0x07,0x81,0x00,0x70, +0x1C,0x00,0x3C,0x07,0x82,0x01,0xC0,0x1C,0x10,0x1F, +0xFF,0xF0,0x0F,0xFF,0xFE,0x20,0x70,0x00,0x71,0x27, +0x00,0x01,0xC8,0x70,0x00,0x07,0x3C,0x00,0x01,0xEE, +0x00,0x00,0x38,0x0A,0xB8,0x60,0x34,0xFF,0xFE,0x03, +0xFF,0xFE,0x0F,0xFF,0xFC,0x38,0x00,0xF8,0xE0,0x00, +0xE5,0xF0,0x00,0x39,0xC0,0x01,0xC7,0x00,0x1F,0x1F, +0xFF,0xF0,0x7F,0xFF,0xE1,0xFF,0xFF,0xC7,0x00,0x0F, +0x9C,0x00,0x0E,0x70,0x00,0x3E,0xB8,0x00,0x0E,0xE0, +0x00,0x7B,0x80,0x01,0xCE,0x00,0x1F,0x3F,0xFF,0xF8, +0xFF,0xFF,0xC3,0xFF,0xF8,0x00,0x0C,0x38,0x40,0x38, +0x00,0x7F,0x00,0x01,0xFF,0xE0,0x01,0xFF,0xFC,0x01, +0xF0,0x3F,0x01,0xE0,0x07,0x81,0xE0,0x01,0xE0,0xE0, +0x00,0x78,0xE0,0x00,0x1C,0x70,0x00,0x08,0x78,0x00, +0x00,0x6F,0x00,0x00,0x03,0x80,0x00,0x00,0xE0,0x00, +0x08,0x70,0x00,0x07,0x38,0x00,0x07,0x8E,0x00,0x03, +0x87,0x80,0x03,0xC1,0xE0,0x03,0xC0,0x7C,0x07,0xC0, +0x1F,0xFF,0xC0,0x07,0xFF,0xC0,0x00,0x7F,0x00,0x0B, +0xB8,0x60,0x38,0xFF,0xFE,0x00,0xFF,0xFF,0x80,0xFF, +0xFF,0xE0,0xE0,0x03,0xF0,0xE0,0x00,0xF0,0xE0,0x00, +0x78,0xE0,0x00,0x3D,0x1C,0x00,0x03,0xB7,0x80,0x00, +0x3C,0x70,0x00,0x07,0x70,0x00,0x0F,0x8E,0x00,0x01, +0xCE,0x00,0x03,0xCE,0x00,0x07,0x8E,0x00,0x0F,0x0E, +0x00,0x3F,0x0F,0xFF,0xFE,0x0F,0xFF,0xF8,0x0F,0xFF, +0xE0,0x00,0x0A,0xB8,0x60,0x35,0x3F,0xFF,0xFE,0xDE, +0x00,0x00,0x47,0x00,0x00,0x27,0xFF,0xFF,0x9B,0xC0, +0x00,0x09,0xE0,0x00,0x04,0xFF,0xFF,0xFC,0x09,0xB8, +0x60,0x31,0x3F,0xFF,0xFF,0x78,0x00,0x04,0x70,0x00, +0x09,0xFF,0xFF,0x9B,0xC0,0x00,0x33,0x80,0x00,0x00, +0x0D,0x38,0x40,0x3C,0x00,0x3F,0xC0,0x00,0x3F,0xFF, +0x00,0x1F,0xFF,0xF0,0x07,0xE0,0x1F,0x01,0xF0,0x00, +0xF0,0x78,0x00,0x0F,0x0E,0x00,0x00,0xE3,0xC0,0x00, +0x1C,0x70,0x00,0x01,0x8E,0x00,0x00,0x05,0x70,0x00, +0x00,0x13,0xC0,0x07,0xFF,0xB8,0x00,0x00,0x78,0x70, +0x00,0x01,0xCF,0x00,0x00,0x38,0xE0,0x00,0x07,0x1E, +0x00,0x01,0xE1,0xF0,0x00,0x7C,0x1F,0x80,0x7F,0x01, +0xFF,0xFF,0xC0,0x0F,0xFF,0xE0,0x00,0x3F,0xE0,0x00, +0x0B,0x38,0x60,0x39,0xBC,0x00,0x03,0xDF,0x00,0x00, +0xF3,0xFF,0xFF,0xFE,0xF0,0x00,0x0F,0x9C,0x00,0x03, +0x80,0x01,0xB8,0x80,0x17,0xBF,0x7E,0xFD,0xE0,0x08, +0x38,0x20,0x29,0xA0,0x00,0xFA,0x00,0x0F,0x60,0x00, +0xF3,0xC0,0x0E,0xF0,0x07,0x38,0x07,0x1F,0x0F,0x87, +0xFF,0x81,0xFF,0x80,0x3F,0x00,0x0B,0xB8,0x60,0x34, +0xE0,0x00,0x78,0xE0,0x00,0xF0,0xE0,0x01,0xE0,0xE0, +0x03,0xC0,0xE0,0x07,0x80,0xE0,0x0F,0x00,0xE0,0x1E, +0x00,0xE0,0x3C,0x00,0xE0,0x78,0x00,0xE0,0xF0,0x00, +0xE1,0xE0,0x00,0xE3,0xE0,0x00,0xE7,0xF0,0x00,0xEF, +0x70,0x00,0xFE,0x78,0x00,0xFC,0x3C,0x00,0xF8,0x1C, +0x00,0xF0,0x0E,0x00,0xE0,0x0F,0x00,0xE0,0x07,0x80, +0xE0,0x03,0x80,0xE0,0x01,0xC0,0xE0,0x01,0xE0,0xE0, +0x00,0xF0,0xE0,0x00,0x70,0xE0,0x00,0x38,0xE0,0x00, +0x3C,0xE0,0x00,0x1E,0x09,0x38,0x60,0x2D,0xBC,0x00, +0x06,0xF0,0x00,0x1B,0xC0,0x00,0x57,0x00,0x01,0x3F, +0xFF,0xF8,0x0C,0xB8,0x80,0x42,0xF8,0x00,0x0F,0xCF, +0xE0,0x00,0xFD,0xFC,0x00,0x7F,0x8E,0xE0,0x03,0xBB, +0xB8,0x01,0xEF,0x3C,0xE0,0x0E,0x79,0xE3,0x80,0xE3, +0xCF,0x0E,0x0E,0x1D,0xC1,0xC7,0x87,0x8E,0x0E,0x38, +0x3B,0x83,0x9E,0x0F,0x3C,0x0E,0xE0,0x79,0xE0,0x3E, +0x03,0xB8,0x07,0x00,0xE0,0x0B,0x38,0x60,0x39,0x1E, +0x00,0x03,0xBE,0x00,0x07,0x8F,0xC0,0x01,0xDD,0xC0, +0x03,0xBB,0xC0,0x07,0x73,0x80,0x0E,0xE3,0x80,0x1D, +0xC7,0x80,0x3B,0x87,0x00,0x77,0x07,0x00,0xEE,0x0F, +0x01,0xDC,0x0E,0x03,0xB8,0x0E,0x07,0x70,0x1E,0x0E, +0xE0,0x1C,0x1D,0xC0,0x1C,0x3B,0x80,0x3C,0x77,0x00, +0x38,0xEE,0x00,0x39,0xDC,0x00,0x7B,0xB8,0x00,0x77, +0x8E,0x00,0x0F,0xDC,0x00,0x0F,0xC7,0x00,0x01,0xE0, +0x0D,0x38,0x40,0x3C,0x00,0x7F,0x80,0x00,0x3F,0xFC, +0x00,0x1F,0xFF,0xE0,0x07,0xE0,0x7E,0x01,0xF0,0x03, +0xE0,0x78,0x00,0x1E,0x0E,0x00,0x01,0xC3,0x80,0x00, +0x3D,0x0E,0x00,0x00,0x76,0xF0,0x00,0x00,0xEE,0x00, +0x00,0x1E,0x1C,0x00,0x00,0xE3,0xC0,0x00,0x3C,0x38, +0x00,0x07,0x07,0x80,0x01,0xE0,0x78,0x00,0xF8,0x07, +0xE0,0x7E,0x00,0x7F,0xFF,0x80,0x03,0xFF,0xC0,0x00, +0x1F,0xE0,0x00,0x0A,0xB8,0x60,0x34,0xFF,0xFF,0x03, +0xFF,0xFF,0x0F,0xFF,0xFE,0x38,0x00,0x7C,0xE0,0x00, +0x73,0x80,0x01,0xF5,0xC0,0x00,0x77,0x00,0x03,0xDC, +0x00,0x0E,0x70,0x00,0xF9,0xFF,0xFF,0xC7,0xFF,0xFE, +0x1F,0xFF,0xC0,0xDE,0x00,0x00,0x5F,0x00,0x00,0x00, +0x0D,0x3C,0x5F,0x3C,0x00,0x7F,0x00,0x00,0x7F,0xF8, +0x00,0x1F,0xFF,0xC0,0x07,0xC0,0x7C,0x01,0xE0,0x03, +0xC0,0x78,0x00,0x3C,0x0E,0x00,0x03,0x83,0x80,0x00, +0x79,0x0E,0x00,0x00,0xE6,0xF0,0x00,0x01,0xCE,0x00, +0x00,0x38,0xE0,0x00,0x0F,0x1C,0x00,0x01,0xC3,0x80, +0x30,0x38,0x38,0x07,0x8F,0x07,0x80,0xFB,0xC0,0x78, +0x07,0xF8,0x07,0xC0,0x7E,0x00,0x7F,0xFF,0xE0,0x03, +0xFF,0xFF,0x00,0x1F,0xE3,0xF0,0x00,0x00,0x1C,0x00, +0x00,0x00,0x80,0x0B,0xB8,0x60,0x38,0xFF,0xFF,0x80, +0xFF,0xFF,0xE0,0xFF,0xFF,0xF0,0xE0,0x00,0xF8,0xE0, +0x00,0x78,0xE0,0x00,0x3D,0x5C,0x00,0x03,0x9C,0x00, +0x07,0x9C,0x00,0x0F,0x1C,0x00,0x3F,0x1F,0xFF,0xFE, +0x1F,0xFF,0xFC,0x1F,0xFF,0xE0,0x1C,0x07,0xC0,0x23, +0x80,0x3C,0x03,0x80,0x1E,0x03,0x80,0x0F,0x03,0x80, +0x07,0x83,0x80,0x07,0xC3,0x80,0x03,0xC4,0x70,0x00, +0x3C,0x70,0x00,0x1E,0x70,0x00,0x0F,0x0B,0x38,0x40, +0x34,0x01,0xFE,0x00,0x1F,0xFF,0x00,0x7F,0xFF,0x01, +0xF0,0x1F,0x03,0x80,0x0F,0x0E,0x00,0x0E,0x43,0x80, +0x01,0xC7,0x00,0x00,0x0F,0x00,0x00,0x0F,0x80,0x00, +0x1F,0xF0,0x00,0x1F,0xFE,0x00,0x0F,0xFF,0x80,0x03, +0xFF,0x80,0x00,0x7F,0x80,0x00,0x0F,0x80,0x00,0x07, +0xC7,0x00,0x00,0xEF,0x00,0x01,0xCE,0x00,0x03,0x9E, +0x00,0x0F,0x1E,0x00,0x3C,0x3F,0x01,0xF0,0x3F,0xFF, +0xC0,0x1F,0xFF,0x00,0x0F,0xF8,0x00,0x0A,0xB8,0x20, +0x2F,0x3F,0xFF,0xFF,0xD0,0x07,0x00,0x68,0x03,0x80, +0x34,0x01,0xC0,0x14,0x00,0xE0,0x00,0x0B,0x38,0x60, +0x39,0xBC,0x00,0x03,0xEF,0x00,0x00,0xF9,0xC0,0x00, +0x3B,0x80,0x00,0xF8,0x70,0x00,0x38,0xF0,0x00,0xF0, +0xF8,0x07,0xC0,0xFF,0xFF,0x00,0xFF,0xFC,0x00,0x3F, +0xC0,0x00,0x0C,0xB8,0x20,0x34,0xE0,0x00,0x03,0xBC, +0x00,0x01,0xF0,0xE0,0x00,0x0E,0x83,0x80,0x00,0xE0, +0xF0,0x00,0x79,0x03,0x80,0x03,0x80,0xF0,0x01,0xE0, +0x1C,0x00,0x70,0x07,0x80,0x3C,0x20,0x1C,0x01,0xC0, +0x07,0x80,0xF0,0x00,0xE0,0x38,0x00,0x3C,0x1E,0x04, +0x00,0xE0,0xE0,0x00,0x3C,0x78,0x00,0x07,0x1C,0x00, +0x01,0xCF,0x00,0x80,0x07,0x70,0x00,0x01,0xFC,0x01, +0x20,0x07,0xC0,0x00,0x12,0xB8,0x00,0x4C,0xE0,0x00, +0xF8,0x00,0x3B,0xC0,0x03,0xE0,0x01,0xE7,0x00,0x0F, +0x80,0x07,0x43,0x80,0x0E,0xE0,0x03,0x8F,0x00,0x3B, +0x80,0x1E,0x1C,0x01,0xEE,0x00,0x72,0x0E,0x00,0xE3, +0x80,0x38,0x1C,0x03,0x8E,0x01,0xC4,0x8E,0x03,0x83, +0x80,0xE0,0x1C,0x1E,0x0E,0x07,0x08,0x0E,0x0E,0x03, +0x83,0x80,0x38,0x38,0x0E,0x1E,0x00,0x71,0xE0,0x1C, +0x70,0x40,0x38,0xE0,0x0E,0x38,0x00,0xF7,0x80,0x39, +0xE0,0x90,0x3B,0x80,0x0E,0xE0,0x00,0x7E,0x00,0x1F, +0x01,0x20,0x3E,0x00,0x0F,0x80,0x0C,0xB8,0x00,0x32, +0x78,0x00,0x0F,0x0F,0x00,0x07,0x81,0xC0,0x01,0xC0, +0x38,0x00,0xE0,0x0F,0x00,0x78,0x01,0xE0,0x3C,0x00, +0x38,0x0E,0x00,0x07,0x07,0x80,0x01,0xE3,0xC0,0x00, +0x38,0xE0,0x00,0x07,0x70,0x00,0x01,0xFC,0x00,0x00, +0x3E,0x00,0x00,0x07,0x00,0x00,0x03,0xE0,0x00,0x01, +0xFC,0x00,0x00,0xF7,0x80,0x00,0x38,0xE0,0x00,0x1C, +0x1C,0x00,0x0F,0x07,0x80,0x07,0x80,0xE0,0x01,0xC0, +0x1C,0x00,0xF0,0x07,0x80,0x78,0x00,0xF0,0x1C,0x00, +0x1C,0x0E,0x00,0x03,0x87,0x80,0x00,0xF3,0xC0,0x00, +0x1E,0x0C,0xB8,0x00,0x32,0xF0,0x00,0x07,0x9C,0x00, +0x01,0xC3,0x80,0x00,0xE0,0xF0,0x00,0x78,0x1E,0x00, +0x3C,0x03,0x80,0x0E,0x00,0xF0,0x07,0x80,0x1E,0x03, +0xC0,0x03,0x80,0xE0,0x00,0xF0,0x78,0x00,0x1E,0x3C, +0x00,0x03,0x8E,0x00,0x00,0x77,0x00,0x00,0x1F,0xC0, +0x00,0x03,0xE0,0x06,0x80,0x0E,0x00,0x30,0x00,0x70, +0x00,0x0B,0x38,0x20,0x31,0x27,0xFF,0xFF,0x00,0x00, +0x1E,0x00,0x00,0x78,0x00,0x01,0xE0,0x00,0x03,0x80, +0x00,0x0E,0x00,0x00,0x3C,0x00,0x00,0xF0,0x00,0x03, +0xC0,0x00,0x07,0x00,0x00,0x1C,0x00,0x00,0x78,0x00, +0x01,0xE0,0x00,0x07,0x80,0x00,0x0E,0x00,0x00,0x38, +0x00,0x00,0xF0,0x00,0x03,0xC0,0x00,0x0F,0x00,0x00, +0x1C,0x00,0x00,0x70,0x00,0x01,0xE0,0x00,0x07,0x80, +0x00,0x13,0xFF,0xFF,0xF8,0x03,0xC8,0x5C,0x17,0x3F, +0xF7,0x86,0xF0,0xDE,0x1B,0xC2,0x38,0x4F,0xF0,0x05, +0xB8,0x00,0x17,0x1C,0x02,0x5C,0x05,0x1C,0x09,0x1C, +0x14,0x1C,0x24,0x1C,0x50,0x1C,0x90,0x1D,0x00,0x1C, +0x03,0xC8,0x5C,0x17,0x3F,0xF4,0x3E,0x87,0xD0,0xFA, +0x1E,0x03,0xCF,0xF0,0x07,0x9E,0x26,0xA2,0x03,0x81, +0x00,0xF8,0x00,0xD8,0x20,0x3B,0x84,0x0E,0x38,0x0C, +0x18,0x83,0x83,0x92,0xE0,0x39,0xC0,0x1C,0x0B,0x87, +0xFC,0x2D,0x3F,0xFF,0xFF,0xC0,0x03,0x8A,0x4B,0x9A, +0xF8,0x7C,0x3C,0x1C,0x0E,0x09,0x2A,0x40,0x2C,0x07, +0xF8,0x03,0xFF,0xC0,0xFF,0xFC,0x3C,0x07,0xCF,0x00, +0x79,0xC0,0x07,0x40,0x00,0x1C,0x00,0x0F,0x80,0x7F, +0xF0,0x7F,0xFE,0x1F,0xF9,0xC7,0xC0,0x39,0xE0,0x07, +0x38,0x00,0xE7,0x00,0x3C,0xE0,0x0F,0x9F,0x07,0xF1, +0xFF,0xEE,0x1F,0xF9,0xC0,0xFC,0x1C,0x09,0x38,0x60, +0x2D,0xBC,0x00,0x03,0x8F,0xC0,0x77,0xFE,0x0F,0xFF, +0xE1,0xFC,0x3E,0x3E,0x01,0xE8,0xF0,0x03,0xB7,0x80, +0x07,0x8F,0x00,0x39,0xF0,0x0F,0x3F,0x87,0xC7,0xFF, +0xF0,0xEF,0xFC,0x1C,0x7E,0x00,0x08,0xAA,0x40,0x28, +0x03,0xF0,0x03,0xFF,0x01,0xFF,0xE0,0xF8,0x7C,0x78, +0x07,0x1C,0x01,0xEF,0x00,0x3E,0x70,0x00,0x1C,0x00, +0x77,0x80,0x1C,0xE0,0x0E,0x3C,0x03,0x87,0x83,0xC0, +0xFF,0xF0,0x1F,0xF8,0x01,0xF8,0x00,0x09,0x38,0x20, +0x2D,0xA0,0x00,0x38,0x0F,0xC7,0x07,0xFE,0xE1,0xFF, +0xFC,0x7C,0x3F,0x9E,0x01,0xF8,0x70,0x03,0xF7,0x80, +0x07,0x87,0x00,0x3C,0xF0,0x0F,0x8F,0x87,0xF0,0xFF, +0xFE,0x0F,0xFD,0xC0,0x7E,0x38,0x09,0x2A,0x40,0x2C, +0x03,0xF0,0x01,0xFF,0x80,0x7F,0xF8,0x1E,0x07,0x87, +0x80,0x78,0xE0,0x07,0x18,0x00,0x77,0x00,0x0F,0x3F, +0xFF,0xFC,0xF0,0x00,0x0F,0x00,0x00,0xE0,0x03,0x9E, +0x00,0xE1,0xF0,0x7C,0x1F,0xFF,0x01,0xFF,0xC0,0x0F, +0xE0,0x05,0xB8,0x20,0x18,0x07,0xE0,0xFE,0x1F,0xE1, +0xE1,0x23,0x82,0x7F,0xF6,0x8E,0x0D,0x1C,0x14,0x38, +0x00,0x09,0x3A,0x3C,0x2C,0x03,0xF1,0xC1,0xFF,0x38, +0x7F,0xFF,0x1F,0x0F,0xE7,0x80,0x7E,0x1C,0x00,0xFD, +0xE0,0x01,0xE1,0xC0,0x0F,0x3C,0x03,0xE3,0xE1,0xFC, +0x3F,0xFF,0x83,0xFF,0x70,0x1F,0x8E,0x00,0x01,0xDC, +0x00,0x3B,0x80,0x0E,0x78,0x03,0xC7,0xC0,0xF8,0xFF, +0xFE,0x07,0xFF,0x00,0x3F,0x80,0x08,0x38,0x60,0x2D, +0xBC,0x00,0x0E,0x3F,0x07,0x7F,0xE3,0xFF,0xF9,0xF8, +0x3C,0xF8,0x0F,0x78,0x03,0xEF,0x00,0x3E,0xF0,0x03, +0xB8,0x01,0xC0,0x01,0xB8,0x60,0x13,0x3E,0x86,0xFD, +0xFB,0xC0,0x04,0x49,0xDC,0x13,0x20,0xF4,0x01,0xA0, +0xFA,0x0F,0xA0,0xF4,0x0E,0x0F,0x3F,0x3F,0x9F,0x00, +0x08,0xB8,0x60,0x29,0xBC,0x00,0x07,0x00,0x79,0xC0, +0x3C,0x70,0x1E,0x1C,0x0F,0x07,0x07,0x81,0xC3,0xC0, +0x71,0xE0,0x1C,0xF0,0x07,0x78,0x01,0xFF,0x00,0x7D, +0xE0,0x1E,0x38,0x07,0x0F,0x01,0xC1,0xE0,0x70,0x38, +0x1C,0x0F,0x07,0x01,0xE1,0xC0,0x3C,0x70,0x07,0x1C, +0x01,0xE7,0x00,0x3C,0x01,0xB8,0x60,0x13,0xBF,0x7E, +0xFD,0xE0,0x0D,0xAA,0x60,0x42,0xE3,0xF0,0x3F,0x0E, +0x7F,0x8F,0xF8,0xEF,0xFD,0xFF,0xCF,0xC3,0xDC,0x3C, +0xF8,0x1F,0x01,0xEF,0x00,0xF0,0x0F,0xBC,0x01,0xC0, +0x1F,0x78,0x03,0x80,0x3B,0x80,0x38,0x03,0x80,0x08, +0x2A,0x60,0x2C,0xE3,0xF0,0x77,0xFE,0x3F,0xFF,0x9F, +0x83,0xCF,0x80,0xF7,0x80,0x3E,0xF0,0x03,0xEF,0x00, +0x3B,0x80,0x1C,0x09,0x2A,0x40,0x2C,0x03,0xF0,0x01, +0xFF,0x80,0x7F,0xF8,0x1F,0x0F,0x87,0x80,0x78,0xE0, +0x07,0x3C,0x00,0xFD,0xE0,0x01,0xDE,0x00,0x79,0xC0, +0x0E,0x3C,0x03,0xC3,0xE1,0xF0,0x3F,0xFC,0x03,0xFF, +0x00,0x1F,0x80,0x09,0x3A,0x7C,0x2C,0xE3,0xF0,0x1C, +0xFF,0x83,0xBF,0xF8,0x7F,0x0F,0x8F,0x80,0x7A,0x3C, +0x00,0xED,0xE0,0x01,0xE3,0xC0,0x0E,0x7C,0x03,0xCF, +0xC1,0xF1,0xFF,0xFC,0x3B,0xFF,0x07,0x1F,0x81,0xBC, +0x00,0x03,0x80,0x00,0x09,0x3A,0x3C,0x2C,0x03,0xF1, +0xC1,0xFF,0x38,0x7F,0xF7,0x1F,0x0F,0xE7,0x80,0x7C, +0xE0,0x07,0xBC,0x00,0xFD,0xE0,0x01,0xE1,0xC0,0x0F, +0x3C,0x03,0xE3,0xE1,0xFC,0x3F,0xFF,0x83,0xFF,0x70, +0x1F,0x8F,0xA0,0x00,0x38,0x00,0x07,0x05,0x2A,0x60, +0x1A,0xE7,0xDD,0xFB,0xFE,0x7C,0x11,0xE0,0x6F,0x01, +0xBC,0x03,0x80,0x08,0xAA,0x20,0x26,0x0F,0xE0,0x0F, +0xFE,0x07,0xFF,0xE1,0xE0,0x78,0xE0,0x0F,0x38,0x01, +0xCE,0x00,0x03,0xE0,0x00,0x7F,0x80,0x1F,0xFE,0x01, +0xFF,0xE0,0x0F,0xFC,0x00,0x3F,0x80,0x01,0xF1,0xC0, +0x07,0x38,0x03,0xCF,0x81,0xE1,0xFF,0xF0,0x3F,0xF8, +0x03,0xF8,0x00,0x05,0x38,0x00,0x16,0x04,0x01,0x85, +0x8E,0x13,0xFF,0xE8,0xE1,0xA3,0x80,0x78,0x0F,0xE0, +0xFC,0x0F,0x80,0x08,0x2A,0x60,0x2D,0xBC,0x00,0xFB, +0xC0,0x0E,0xE0,0x07,0x70,0x07,0xBC,0x07,0xCF,0x07, +0xE7,0xFF,0x71,0xFF,0x38,0x3F,0x1C,0x09,0xAA,0x00, +0x26,0xE0,0x00,0xF0,0xE0,0x03,0x8F,0x00,0x7A,0x0E, +0x00,0xE0,0x70,0x1E,0x07,0x01,0xC0,0x78,0x3C,0x40, +0x70,0x70,0x07,0x8F,0x08,0x07,0x1C,0x12,0x07,0x70, +0x20,0x07,0xC0,0x00,0x3C,0x00,0x03,0x80,0x00,0x0E, +0xAA,0x00,0x3B,0x1C,0x00,0xE0,0x07,0x78,0x07,0xC0, +0x3E,0x1C,0x03,0xE0,0x1C,0x38,0x0D,0x80,0xE4,0x1C, +0x0E,0xE0,0x70,0x38,0x31,0x83,0x80,0xE1,0xC7,0x0E, +0x01,0x87,0x1C,0x70,0x07,0x1C,0x31,0xC0,0x1C,0xE0, +0xE7,0x00,0x33,0x83,0xB8,0x00,0xEE,0x0E,0xE0,0x03, +0xB8,0x1B,0x02,0x00,0xF8,0x0F,0x80,0x01,0xE0,0x3C, +0x00,0x07,0x00,0x70,0x00,0x1C,0x01,0x80,0x00,0x09, +0x2A,0x00,0x24,0xF0,0x01,0xCF,0x00,0x70,0xE0,0x1E, +0x1E,0x07,0x81,0xE0,0xE0,0x1C,0x3C,0x03,0xCF,0x00, +0x3D,0xC0,0x03,0xF0,0x00,0x3E,0x04,0x00,0xF0,0x00, +0x3F,0x00,0x0F,0xF0,0x01,0xCF,0x00,0x70,0xE0,0x1E, +0x1E,0x07,0x81,0xE0,0xE0,0x1C,0x3C,0x03,0xCF,0x00, +0x3C,0x08,0xBA,0x3C,0x26,0xE0,0x03,0x9C,0x01,0xF0, +0xE0,0x0E,0x1C,0x07,0xA0,0xE0,0x38,0x1C,0x1E,0x40, +0xE0,0xE0,0x1C,0x78,0x80,0xE3,0x80,0x1D,0xE1,0x00, +0xEE,0x00,0x1F,0x82,0x00,0xF8,0x00,0x1E,0x04,0x80, +0xE0,0x20,0x0E,0x00,0x07,0x00,0x0F,0xC0,0x03,0xE0, +0x00,0xF0,0x00,0x09,0x2A,0x00,0x27,0x2F,0xFF,0xF8, +0x00,0x1E,0x00,0x07,0x80,0x01,0xE0,0x00,0x38,0x00, +0x0F,0x00,0x03,0xC0,0x00,0xF0,0x00,0x3C,0x00,0x0F, +0x00,0x03,0xC0,0x00,0xF0,0x00,0x3C,0x00,0x0F,0x00, +0x03,0xC0,0x00,0x70,0x00,0x27,0xFF,0xFF,0x05,0xC8, +0x3C,0x1A,0x01,0xF0,0x0F,0xC1,0xE3,0x43,0x85,0x07, +0x00,0xE0,0x1E,0x07,0xC0,0x70,0x07,0xC0,0x1E,0x00, +0xE0,0xD0,0xE1,0x21,0xC0,0x1E,0x20,0x1F,0x80,0x78, +0x01,0xCA,0x7B,0x93,0xBF,0x7E,0xFD,0xFB,0xE3,0x80, +0x05,0xC8,0x3C,0x1A,0xF0,0x0F,0x80,0xFC,0x01,0xE1, +0xA1,0xC2,0x83,0x80,0x1C,0x01,0xE0,0x0F,0x80,0x38, +0x0F,0x81,0xE0,0x1C,0x68,0x70,0x90,0xE0,0x1E,0x11, +0xF8,0x1E,0x00,0x0A,0x0C,0x25,0xAE,0x1F,0x00,0x03, +0xFF,0x01,0xBF,0xFE,0x1D,0xC3,0xFF,0xEC,0x03,0xFE, +0x00,0x07,0xC0,}; +/* font data size: 3983 bytes */ + +static const unsigned char Arial_28_index[] = { +0x00,0x00,0x04,0x00,0xD0,0x18,0x04, +0x40,0x86,0x0F,0x71,0x4A,0x15,0x11,0x6F,0x18,0xE1, +0xA4,0x1B,0x61,0xBD,0x1C,0x31,0xC8,0x1D,0xD2,0x04, +0x21,0xD2,0x61,0x2A,0x02,0xD5,0x30,0x83,0x49,0x37, +0x13,0xA8,0x3E,0x63,0xEE,0x3F,0x84,0x2C,0x43,0x94, +0x6D,0x4A,0x25,0x49,0x58,0x55,0xC4,0x60,0xD6,0x4C, +0x66,0x66,0x7C,0x6C,0xC6,0xE1,0x6E,0x97,0x04,0x75, +0xC7,0x6E,0x7A,0x37,0xEE,0x83,0x78,0x66,0x8B,0x99, +0x03,0x95,0x39,0x67,0x98,0xA9,0xD2,0xA2,0xEA,0x8D, +0xAC,0x9B,0x13,0xB2,0x1B,0x36,0xB4,0x4B,0x5C,0xB6, +0x4B,0x6D,0xBA,0x1B,0xC8,0xBF,0x1C,0x18,0xC4,0x5C, +0x59,0xC9,0x0C,0xAB,0xCB,0x4C,0xC6,0xCF,0xCD,0x04, +0xD2,0x9D,0x41,0xD6,0x9D,0x92,0xDB,0xDD,0xCD,0xDF, +0xFE,0x13,0xE2,0xBE,0x55,0xE9,0xBE,0xCF,0xF0,0x3F, +0x30,0xF5,0x0F,0x5A,0xF7,0xB0, +}; +/* font index size: 143 bytes */ + +const ILI9341_t3_font_t Arial_28 = { + Arial_28_index, + 0, + Arial_28_data, + 1, + 0, + 32, + 126, + 0, + 0, + 12, + 6, + 6, + 4, + 6, + 6, + 43, + 28 +}; + + + +static const unsigned char Arial_32_data[] = { +0x00,0x00,0x00,0x18,0x02,0x40,0xA0,0x1D,0xBF,0xBF, +0x1E,0x7D,0x63,0x48,0x57,0x80,0x06,0x16,0x4A,0xA1, +0xBE,0x1E,0xF0,0xF3,0x83,0x43,0x03,0x00,0x0C,0x40, +0x00,0x31,0x00,0x0F,0x07,0x80,0x0F,0x87,0x8A,0x00, +0xF0,0x78,0x00,0xF0,0x78,0x57,0xFF,0xFF,0xFD,0x01, +0xE0,0xF0,0x48,0x3C,0x1E,0x05,0x7F,0xFF,0xFF,0xC0, +0x78,0x3C,0x05,0x0F,0x07,0x80,0x07,0x87,0xC0,0x20, +0xF0,0x78,0x00,0x0A,0x4C,0x5E,0x31,0x00,0x0C,0x00, +0x01,0xF8,0x00,0x7F,0xF0,0x07,0xFF,0xE0,0x7F,0xFF, +0x03,0xE6,0xFC,0x3E,0x31,0xE1,0xE1,0x8F,0x8F,0x0C, +0x3C,0x78,0x61,0x88,0x78,0x60,0x01,0xE3,0x00,0x0F, +0xD8,0x00,0x3F,0xE0,0x00,0xFF,0xE0,0x01,0xFF,0x80, +0x03,0xFF,0x00,0x0D,0xF8,0x00,0x63,0xE0,0x03,0x0F, +0x40,0x03,0x07,0x8C,0x18,0x3D,0xE0,0xC1,0xEF,0x86, +0x0F,0x7C,0x30,0xF9,0xF1,0x8F,0x8F,0xCC,0xFC,0x3F, +0xFF,0xC0,0xFF,0xFC,0x03,0xFF,0xC0,0x07,0xF8,0x14, +0x00,0xC0,0x00,0x11,0x40,0x40,0x4E,0x0F,0x80,0x00, +0xE0,0x07,0xF8,0x00,0x3C,0x00,0xFF,0x80,0x07,0x00, +0x3C,0x78,0x01,0xE0,0x07,0x07,0x00,0x38,0x01,0xC0, +0x70,0x0F,0x00,0x38,0x0E,0x01,0xC0,0x08,0xE0,0x38, +0x0E,0x00,0x1C,0x07,0x03,0x80,0x03,0x80,0xE0,0xF0, +0x00,0x70,0x1C,0x1C,0x00,0x07,0x07,0x07,0x80,0x00, +0xF1,0xE0,0xE0,0x00,0x0F,0xF8,0x3C,0x00,0x01,0xFE, +0x07,0x03,0xE0,0x0F,0x81,0xC1,0xFE,0x00,0x00,0x38, +0x3F,0xE0,0x00,0x0E,0x0F,0x1E,0x00,0x03,0xC1,0xC1, +0xC0,0x00,0x70,0x70,0x1C,0x00,0x1E,0x0E,0x03,0x80, +0x03,0x81,0xC0,0x70,0x00,0xF0,0x38,0x0E,0x00,0x1C, +0x07,0x01,0xE0,0x00,0xE0,0x1C,0x07,0x00,0x38,0x01, +0xC1,0xC0,0x0F,0x00,0x3C,0x78,0x01,0xC0,0x03,0xFE, +0x00,0x78,0x00,0x7F,0x80,0x0E,0x00,0x03,0xE0,0x0D, +0x40,0x40,0x3A,0x00,0x7E,0x00,0x00,0x3F,0xE0,0x00, +0x0F,0xFE,0x00,0x03,0xFF,0xE0,0x00,0xFC,0x7E,0x00, +0x1F,0x07,0xC0,0x48,0x78,0x0F,0x00,0x0F,0x83,0xC0, +0x00,0xF8,0xF8,0x00,0x0F,0x3E,0x00,0x01,0xFF,0x80, +0x00,0x1F,0xE0,0x00,0x07,0xF0,0x00,0x01,0xFF,0x00, +0x00,0xFF,0xE0,0x00,0x3F,0x3E,0x08,0x0F,0x83,0xE1, +0xE1,0xE0,0x3E,0x7C,0x7C,0x03,0xEF,0x0F,0x00,0x7D, +0xE1,0xE0,0x07,0xFC,0x3C,0x00,0x7F,0x07,0x80,0x07, +0xC0,0xF8,0x00,0xFC,0x0F,0x80,0x3F,0xC1,0xF8,0x1F, +0xFC,0x1F,0xFF,0xF7,0xC1,0xFF,0xFC,0xFC,0x1F,0xFE, +0x0F,0x00,0xFF,0x00,0xC0,0x02,0x16,0x4A,0x91,0xBE, +0xF9,0x60,0x05,0xD2,0x7B,0x9E,0x00,0xE0,0x1C,0x03, +0x80,0x78,0x07,0x00,0xF0,0x0E,0x01,0xE0,0x1C,0x10, +0x78,0x29,0xE0,0x6F,0x80,0xAF,0x01,0x4F,0x02,0x0F, +0x00,0x70,0x07,0x80,0x38,0x03,0xC0,0x1C,0x01,0xE0, +0x0E,0x00,0x70,0x03,0x80,0x05,0xD2,0x3B,0x9E,0xE0, +0x07,0x01,0x07,0x00,0x38,0x03,0xC0,0x1C,0x01,0xE0, +0x0E,0x20,0x1E,0x50,0x1E,0xD0,0x1F,0x40,0x3E,0x40, +0xF0,0x0E,0x40,0x3C,0x03,0x80,0x78,0x07,0x00,0xF0, +0x0E,0x01,0xE0,0x1C,0x03,0x80,0x70,0x00,0x07,0x9A, +0x29,0xA3,0x20,0x70,0x08,0x70,0x8F,0x77,0x9F,0xFF, +0xC7,0xFF,0x00,0xF8,0x01,0xFC,0x03,0xDE,0x20,0xF1, +0xE0,0x20,0x80,0x0B,0x2C,0x42,0x35,0xA0,0x0F,0x00, +0x40,0x03,0xC0,0x15,0xFF,0xFF,0xFE,0x80,0x3C,0x01, +0x00,0x0F,0x00,0x00,0x02,0x16,0x9C,0x99,0x5F,0x26, +0x73,0x38,0x80,0x06,0x08,0x24,0x9F,0x5F,0xFE,0x02, +0x08,0x80,0x19,0x5E,0x06,0x40,0x00,0x19,0x00,0x0F, +0x20,0x1C,0x01,0xE9,0x01,0xC9,0x03,0x80,0x3C,0x48, +0x38,0x50,0x70,0x48,0xE0,0x0F,0x02,0x4E,0x02,0x5C, +0x01,0xE0,0x0E,0x00,0x0A,0x40,0x40,0x30,0x01,0xF8, +0x00,0x3F,0xF0,0x40,0xFF,0xFC,0x0F,0xC3,0xF0,0x78, +0x07,0x87,0x80,0x3E,0x87,0x80,0x1E,0x78,0x00,0xF6, +0xF8,0x00,0x7D,0xF8,0x00,0x79,0xC0,0x03,0xA1,0xE0, +0x07,0x8F,0x00,0x7C,0x3C,0x03,0xC1,0xF8,0x7E,0x40, +0xFF,0xFC,0x03,0xFF,0x80,0x03,0xF0,0x00,0x05,0xC0, +0xA0,0x31,0x00,0x1C,0x03,0xC0,0x7C,0x0F,0xC1,0xFC, +0x7F,0xCF,0xFD,0xF3,0xDE,0x3D,0xC3,0xD0,0x3F,0x40, +0x7E,0x80,0xFC,0x01,0xE0,0x0A,0x40,0x20,0x30,0x01, +0xFC,0x00,0x3F,0xF8,0x03,0xFF,0xE0,0x3F,0xFF,0x83, +0xF0,0x7E,0x1F,0x01,0xF1,0xF0,0x07,0xE1,0xE0,0x03, +0xC3,0x00,0x1F,0x00,0x00,0x1E,0x00,0x01,0xE0,0x00, +0x1F,0x00,0x00,0xF0,0x00,0x0F,0x80,0x00,0xF8,0x00, +0x0F,0x80,0x00,0xF8,0x00,0x0F,0x80,0x00,0xF8,0x00, +0x0F,0x80,0x00,0xF8,0x00,0x0F,0x80,0x00,0xF8,0x00, +0x0F,0x80,0x00,0xF8,0x00,0x0F,0x80,0x00,0x7F,0xFF, +0xF9,0xFF,0xFF,0xF0,0x0A,0x40,0x40,0x30,0x03,0xF0, +0x00,0x7F,0xE0,0x07,0xFF,0xC0,0x7F,0xFE,0x07,0xE0, +0xF8,0x3E,0x03,0xE3,0xE0,0x0F,0x1E,0x00,0x78,0x30, +0x03,0xC8,0x00,0x03,0xC0,0x00,0x3C,0x00,0x07,0xC0, +0x01,0xFC,0x00,0x0F,0xC0,0x00,0x7F,0x80,0x03,0xFF, +0x00,0x00,0xF8,0x00,0x01,0xE0,0x00,0x0F,0xC0,0x00, +0x07,0x8C,0x00,0x3D,0xE0,0x01,0xEF,0x80,0x0F,0x7C, +0x00,0xF1,0xF0,0x0F,0x8F,0xC0,0xF8,0x3F,0xFF,0xC0, +0xFF,0xFC,0x03,0xFF,0x80,0x07,0xF0,0x00,0x0A,0xC0, +0x20,0x30,0x00,0x03,0x80,0x00,0x1E,0x10,0x00,0x1F, +0x00,0x00,0xFC,0x00,0x07,0xF0,0x80,0x07,0xF8,0x00, +0x3F,0xE0,0x01,0xF7,0x80,0x07,0x9E,0x00,0x3E,0x78, +0x01,0xF1,0xE0,0x07,0x87,0x80,0x3E,0x1E,0x01,0xF0, +0x78,0x0F,0x81,0xE0,0x3C,0x07,0x81,0xF0,0x1E,0x0F, +0x80,0x78,0x57,0xFF,0xFF,0xF4,0x00,0x1E,0x00,0x00, +0x78,0x00,0x0A,0x40,0x40,0x31,0x21,0xFF,0xF8,0x1F, +0xFF,0xCA,0x1E,0x00,0x08,0x3C,0x00,0x01,0xE3,0xE0, +0x0F,0x7F,0xC0,0x7F,0xFF,0x07,0xFF,0xFC,0x3F,0x03, +0xF1,0xF0,0x0F,0x83,0x00,0x3D,0x80,0x00,0x1E,0xF0, +0x00,0xF7,0x80,0x0F,0x3E,0x00,0x78,0xF0,0x07,0xC7, +0xE0,0x7C,0x1F,0xFF,0xC0,0x7F,0xFC,0x01,0xFF,0xC0, +0x03,0xF8,0x00,0x0A,0xC0,0x20,0x30,0x00,0xFC,0x00, +0x0F,0xFC,0x00,0xFF,0xFC,0x07,0xFF,0xF0,0x1F,0x07, +0xE0,0xF8,0x07,0x83,0xC0,0x1F,0x1E,0x00,0x3D,0x0F, +0x00,0x00,0x78,0x00,0x01,0xE0,0xFC,0x07,0x8F,0xFC, +0x1E,0xFF,0xF8,0x7F,0xFF,0xF1,0xFE,0x07,0xE7,0xE0, +0x0F,0x9F,0x00,0x1E,0x7C,0x00,0x7E,0xBC,0x00,0x1E, +0x70,0x00,0x79,0xE0,0x03,0xE7,0x80,0x0F,0x0F,0x00, +0x7C,0x3F,0x03,0xE0,0x7F,0xFF,0x80,0xFF,0xFC,0x01, +0xFF,0xC0,0x00,0xFC,0x00,0x0A,0x40,0x40,0x31,0x5F, +0xFF,0xFE,0x00,0x00,0xE0,0x00,0x0E,0x00,0x00,0xF0, +0x00,0x0F,0x00,0x00,0x70,0x00,0x07,0x84,0x00,0x0F, +0x04,0x00,0x1E,0x04,0x80,0x3C,0x04,0x00,0x78,0x05, +0x00,0xF0,0x05,0x01,0xE0,0x05,0x83,0xC0,0x00,0x0A, +0x40,0x40,0x30,0x01,0xF8,0x00,0x7F,0xF0,0x07,0xFF, +0xE0,0x7F,0xFF,0x83,0xE0,0x7C,0x3E,0x01,0xF5,0x3C, +0x00,0xF0,0xF0,0x0F,0x07,0xC0,0xF8,0x1F,0xFF,0x80, +0x3F,0xF0,0x03,0xFF,0xC0,0x3F,0xFF,0x03,0xE0,0x7C, +0x3E,0x01,0xF1,0xE0,0x07,0xB3,0xC0,0x03,0xCF,0x00, +0x3E,0x7C,0x03,0xE3,0xF0,0x3F,0x0F,0xFF,0xF0,0x3F, +0xFF,0x00,0xFF,0xF0,0x00,0xFC,0x00,0x0A,0x40,0x40, +0x30,0x03,0xF8,0x00,0x7F,0xF0,0x07,0xFF,0xC0,0x7F, +0xFF,0x03,0xF0,0x7C,0x3E,0x01,0xE1,0xE0,0x07,0x9F, +0x00,0x3C,0xF0,0x00,0xEA,0xF0,0x00,0xF7,0x80,0x0F, +0x9E,0x00,0x7C,0xF8,0x07,0xE7,0xE0,0x7F,0x1F,0xFF, +0xF8,0x7F,0xFB,0xC1,0xFF,0x9E,0x03,0xF0,0xF0,0x00, +0x07,0xC0,0x00,0x0F,0x1E,0x00,0x78,0xF0,0x07,0x83, +0xC0,0x3C,0x1F,0x07,0xC0,0xFF,0xFE,0x03,0xFF,0xE0, +0x0F,0xFE,0x00,0x1F,0xC0,0x00,0x02,0x2E,0x80,0x19, +0x5F,0xA1,0xA0,0x0A,0xF0,0x02,0x3C,0x9C,0x99,0x5F, +0xA1,0xA0,0x0A,0xF9,0x33,0x99,0xC4,0x0A,0xAA,0x42, +0xB4,0x00,0x00,0x08,0x00,0x01,0xE0,0x00,0x1F,0x80, +0x01,0xFE,0x00,0x3F,0xF0,0x03,0xFE,0x00,0x3F,0xC0, +0x07,0xFC,0x00,0x7F,0x80,0x03,0xF8,0x00,0x0F,0x00, +0x00,0x3F,0x80,0x00,0x7F,0x80,0x00,0x7F,0xC0,0x00, +0x3F,0xC0,0x00,0x3F,0xE0,0x00,0x3F,0xF0,0x00,0x1F, +0xE0,0x00,0x1F,0x80,0x00,0x1E,0x00,0x00,0x08,0x0A, +0x9A,0x44,0xB5,0x5F,0xFF,0xFF,0xB0,0x00,0x00,0x57, +0xFF,0xFF,0xC0,0x0A,0xAA,0x42,0xB4,0x80,0x00,0x03, +0xC0,0x00,0x0F,0xC0,0x00,0x3F,0xC0,0x00,0x7F,0xE0, +0x00,0x3F,0xE0,0x00,0x1F,0xE0,0x00,0x1F,0xF0,0x00, +0x0F,0xF0,0x00,0x0F,0xE0,0x00,0x07,0x80,0x00,0xFE, +0x00,0x0F,0xF0,0x01,0xFF,0x00,0x1F,0xE0,0x03,0xFE, +0x00,0x7F,0xE0,0x03,0xFC,0x00,0x0F,0xC0,0x00,0x3C, +0x00,0x00,0x80,0x00,0x00,0x0A,0x40,0x40,0x30,0x01, +0xFC,0x00,0x7F,0xF8,0x07,0xFF,0xE0,0x7F,0xFF,0x87, +0xF0,0x7E,0x3E,0x01,0xF1,0xE0,0x07,0xDF,0x00,0x1E, +0xF0,0x00,0xF1,0x80,0x07,0x80,0x00,0x3C,0x00,0x03, +0xE0,0x00,0x1E,0x00,0x01,0xF0,0x00,0x3F,0x00,0x03, +0xF0,0x00,0x3F,0x00,0x03,0xF0,0x00,0x3E,0x00,0x01, +0xE0,0x00,0x1F,0x00,0xA0,0x1E,0x00,0x90,0x00,0x00, +0xA0,0x1E,0x00,0x14,0xD2,0x5B,0xDA,0x00,0x00,0xFF, +0xC0,0x00,0x00,0x01,0xFF,0xFF,0x00,0x00,0x01,0xFF, +0xFF,0xF0,0x00,0x01,0xFF,0xFF,0xFE,0x00,0x00,0xFF, +0x80,0x3F,0xE0,0x00,0x7F,0x00,0x01,0xFC,0x00,0x3E, +0x00,0x00,0x1F,0x00,0x1F,0x00,0x00,0x03,0xE0,0x0F, +0x80,0x7C,0x00,0x7C,0x07,0xC0,0x7F,0xC7,0x8F,0x01, +0xE0,0x3F,0xF9,0xE1,0xE0,0xF0,0x1F,0xFF,0xF0,0x38, +0x38,0x0F,0xC3,0xFC,0x0E,0x1E,0x03,0xE0,0x3F,0x01, +0xC7,0x01,0xF0,0x0F,0xC0,0x71,0xC0,0xF8,0x01,0xF0, +0x1C,0x70,0x3C,0x00,0x78,0x07,0x38,0x0F,0x00,0x1E, +0x01,0xCE,0x07,0xC0,0x07,0x80,0x73,0x81,0xE0,0x01, +0xE0,0x1C,0xE0,0x78,0x00,0x70,0x0F,0x38,0x1E,0x00, +0x3C,0x03,0x8E,0x07,0x80,0x0F,0x01,0xE3,0x81,0xE0, +0x03,0xC0,0x70,0xE0,0x78,0x01,0xE0,0x3C,0x38,0x1F, +0x00,0xF8,0x1E,0x0F,0x03,0xC0,0x7E,0x0F,0x81,0xC0, +0xFC,0x3F,0x8F,0xC0,0x70,0x1F,0xFF,0xFF,0xE0,0x1E, +0x07,0xFF,0x7F,0xF0,0x03,0xC0,0xFF,0x8F,0xF0,0x00, +0xF0,0x0F,0x81,0xF0,0x1E,0x1E,0x00,0x00,0x00,0x0F, +0x03,0xE0,0x00,0x00,0x0F,0x80,0xFC,0x00,0x00,0x07, +0xE0,0x1F,0xE0,0x00,0x07,0xE0,0x01,0xFF,0x00,0x1F, +0xF0,0x00,0x3F,0xFF,0xFF,0xF8,0x00,0x03,0xFF,0xFF, +0xF8,0x00,0x00,0x3F,0xFF,0xF8,0x00,0x00,0x00,0xFF, +0xE0,0x00,0x00,0x0E,0xC0,0x00,0x3A,0x00,0x07,0x00, +0x04,0x00,0x07,0xC0,0x00,0x00,0x3F,0x80,0x08,0x00, +0x1D,0xC0,0x00,0x00,0xF7,0x80,0x00,0x03,0x8E,0x00, +0x00,0x1E,0x3C,0x01,0x00,0x0E,0x0E,0x00,0x00,0x78, +0x3C,0x00,0x01,0xC0,0x70,0x08,0x01,0xE0,0x3C,0x00, +0x07,0x00,0x70,0x00,0x3C,0x01,0xE0,0x00,0xE0,0x03, +0x81,0x00,0xFF,0xFF,0xE0,0x07,0xFF,0xFF,0x80,0x1F, +0xFF,0xFF,0x00,0x78,0x00,0x3C,0x20,0x78,0x00,0x0F, +0x12,0x78,0x00,0x03,0xC8,0x78,0x00,0x00,0xF3,0xE0, +0x00,0x03,0xEF,0x00,0x00,0x07,0x80,0x0B,0xC0,0x80, +0x3A,0xFF,0xFF,0x00,0xFF,0xFF,0xC1,0x1F,0xFF,0xFE, +0x1E,0x00,0x3F,0x1E,0x00,0x0F,0x2F,0xC0,0x00,0xF3, +0xC0,0x01,0xE3,0xC0,0x07,0xE3,0xFF,0xFF,0xC4,0x7F, +0xFF,0xF0,0x7F,0xFF,0xF8,0x78,0x00,0x7C,0x8F,0x00, +0x03,0xD7,0xE0,0x00,0x3D,0xE0,0x00,0x7D,0xE0,0x00, +0xF9,0xE0,0x01,0xF9,0xFF,0xFF,0xF1,0xFF,0xFF,0xE1, +0xFF,0xFF,0xC1,0xFF,0xFE,0x00,0x0E,0x40,0x40,0x40, +0x00,0x1F,0xE0,0x00,0x07,0xFF,0xC0,0x00,0xFF,0xFF, +0x80,0x0F,0xFF,0xFE,0x00,0xFE,0x03,0xF8,0x0F,0xC0, +0x07,0xC0,0xF8,0x00,0x1F,0x07,0x80,0x00,0x78,0x7C, +0x00,0x03,0xE3,0xC0,0x00,0x0E,0x1E,0x00,0x00,0x01, +0xF0,0x00,0x00,0x1B,0xE0,0x00,0x00,0x0F,0x00,0x00, +0x00,0x3C,0x00,0x00,0x01,0xE0,0x00,0x03,0xCF,0x00, +0x00,0x3E,0x7C,0x00,0x01,0xE1,0xE0,0x00,0x1F,0x0F, +0x80,0x01,0xF0,0x3F,0x00,0x1F,0x80,0xFE,0x03,0xF8, +0x03,0xFF,0xFF,0x80,0x0F,0xFF,0xF8,0x00,0x3F,0xFF, +0x00,0x00,0x3F,0xE0,0x00,0x0D,0x40,0x80,0x40,0xFF, +0xFF,0x80,0x1F,0xFF,0xFC,0x03,0xFF,0xFF,0xE0,0x7F, +0xFF,0xFE,0x0F,0x00,0x0F,0xE1,0xE0,0x00,0x7C,0x3C, +0x00,0x07,0xC7,0x80,0x00,0x78,0xF0,0x00,0x0F,0xA3, +0xC0,0x00,0x1E,0xDF,0x00,0x00,0x3E,0x7C,0x00,0x00, +0xF8,0xF0,0x00,0x07,0x9E,0x00,0x01,0xF3,0xC0,0x00, +0x3C,0x78,0x00,0x0F,0x8F,0x00,0x03,0xE1,0xE0,0x03, +0xFC,0x3F,0xFF,0xFF,0x07,0xFF,0xFF,0xC0,0xFF,0xFF, +0xE0,0x1F,0xFF,0xE0,0x00,0x0B,0xC0,0x80,0x3B,0x5F, +0xFF,0xFF,0xB7,0xC0,0x00,0x04,0x78,0x00,0x00,0xAF, +0xFF,0xFF,0x9B,0xE0,0x00,0x02,0xBC,0x00,0x00,0x57, +0xFF,0xFF,0xF0,0x0A,0xC0,0x80,0x37,0x5F,0xFF,0xFF, +0xDF,0x00,0x00,0x47,0x80,0x00,0x2B,0xFF,0xFF,0x1B, +0xE0,0x00,0x0D,0xF0,0x00,0x03,0xC0,0x00,0x00,0x0E, +0xC0,0x40,0x44,0x00,0x1F,0xF0,0x00,0x03,0xFF,0xF8, +0x00,0x3F,0xFF,0xF0,0x01,0xFF,0xFF,0xE0,0x0F,0xF0, +0x1F,0xC0,0x7E,0x00,0x1F,0x81,0xF0,0x00,0x1E,0x0F, +0x80,0x00,0x7C,0x3C,0x00,0x00,0xF1,0xE0,0x00,0x03, +0xF0,0xF0,0x00,0x00,0x0A,0xF0,0x00,0x00,0x05,0x78, +0x00,0x7F,0xFD,0xF0,0x00,0x00,0xF8,0x78,0x00,0x00, +0x79,0xF0,0x00,0x01,0xE3,0xE0,0x00,0x07,0x87,0xC0, +0x00,0x3E,0x1F,0x80,0x01,0xF8,0x3F,0xC0,0x3F,0xE0, +0x7F,0xFF,0xFE,0x00,0x7F,0xFF,0xF0,0x00,0x7F,0xFF, +0x00,0x00,0x3F,0xC0,0x00,0x0C,0x40,0x80,0x41,0xBE, +0x00,0x01,0xF9,0xE0,0x00,0x1F,0x5F,0xFF,0xFF,0xFB, +0xE0,0x00,0x1F,0xBE,0x00,0x01,0xEF,0x00,0x00,0xF0, +0x02,0x40,0x80,0x19,0xBF,0xBF,0xBF,0xBF,0x5E,0x08, +0xC0,0x20,0x2D,0xA0,0x00,0xFD,0x00,0x07,0xE8,0x00, +0x3C,0x00,0x0F,0x9F,0x00,0x7B,0xE0,0x1E,0xF8,0x0F, +0x1F,0x07,0xC7,0xFF,0xF0,0xFF,0xF8,0x1F,0xFC,0x01, +0xFC,0x00,0x0D,0x40,0x80,0x3A,0xF0,0x00,0x1F,0x9E, +0x00,0x07,0xE3,0xC0,0x01,0xF8,0x78,0x00,0x7E,0x0F, +0x00,0x1F,0x81,0xE0,0x07,0xE0,0x3C,0x01,0xF8,0x07, +0x80,0x7E,0x00,0xF0,0x1F,0x80,0x1E,0x07,0xE0,0x03, +0xC1,0xF8,0x00,0x78,0x7E,0x00,0x0F,0x1F,0x80,0x01, +0xE7,0xE0,0x00,0x3D,0xFC,0x00,0x07,0xFF,0xC0,0x00, +0xFF,0xFC,0x00,0x1F,0xE7,0xC0,0x03,0xF8,0x7C,0x00, +0x7E,0x07,0x80,0x0F,0x80,0xF8,0x01,0xE0,0x0F,0x80, +0x3C,0x00,0xF8,0x07,0x80,0x0F,0x00,0xF0,0x01,0xF0, +0x1E,0x00,0x1F,0x03,0xC0,0x01,0xF0,0x8F,0x00,0x03, +0xE1,0xE0,0x00,0x3E,0x3C,0x00,0x03,0xE7,0x80,0x00, +0x3E,0x09,0xC0,0x80,0x31,0xBE,0x00,0x03,0x7C,0x00, +0x06,0xF8,0x00,0x0D,0xF0,0x00,0x15,0xFF,0xFF,0xC0, +0x0E,0xC0,0x80,0x4B,0x1F,0xC0,0x00,0x7F,0xAF,0xF0, +0x00,0x7F,0xCF,0xBC,0x00,0x7B,0xEB,0xCF,0x00,0x79, +0xF3,0xE3,0xC0,0x78,0xF7,0x8F,0x83,0xE3,0xE7,0xC3, +0xC1,0xE1,0xF3,0xE0,0xF1,0xE0,0xF7,0x83,0xEF,0x83, +0xE7,0xC0,0xF7,0x81,0xEF,0x01,0xFE,0x07,0xCF,0x80, +0xFE,0x03,0xDE,0x01,0xF0,0x0F,0x0C,0x40,0x80,0x41, +0x1F,0x00,0x01,0xF1,0xF8,0x00,0x1E,0xFE,0x00,0x0F, +0x8F,0xF0,0x00,0xF7,0xFC,0x00,0x7B,0xDF,0x00,0x3D, +0xE7,0x80,0x1E,0xF3,0xE0,0x0F,0x78,0xF0,0x07,0xBC, +0x3C,0x03,0xDE,0x1F,0x01,0xEF,0x07,0x80,0xF7,0x83, +0xE0,0x7B,0xC0,0xF8,0x3D,0xE0,0x3C,0x1E,0xF0,0x1F, +0x0F,0x78,0x07,0x87,0xBC,0x01,0xE3,0xDE,0x00,0xF9, +0xEF,0x00,0x3C,0xF7,0x80,0x1F,0x7B,0xC0,0x07,0xFE, +0x3C,0x00,0x3F,0xDE,0x00,0x0F,0xF1,0xE0,0x00,0x7F, +0x1E,0x00,0x03,0xE0,0x0F,0x40,0x40,0x44,0x00,0x1F, +0xE0,0x00,0x01,0xFF,0xF8,0x00,0x0F,0xFF,0xFC,0x00, +0x3F,0xFF,0xFC,0x00,0xFF,0x03,0xFC,0x03,0xF0,0x00, +0xFC,0x0F,0xC0,0x00,0xF8,0x1F,0x00,0x00,0xF8,0x7C, +0x00,0x00,0xF2,0x1E,0x00,0x00,0x1E,0x7C,0x00,0x00, +0x3D,0xBE,0x00,0x00,0x07,0xBC,0x00,0x00,0x0F,0x7C, +0x00,0x00,0x3F,0x0F,0x00,0x00,0x0F,0x1F,0x00,0x00, +0x3E,0x1F,0x00,0x00,0xF8,0x1F,0x00,0x03,0xE0,0x3F, +0x00,0x0F,0xC0,0x3F,0x80,0x7F,0x00,0x3F,0xFF,0xFC, +0x00,0x3F,0xFF,0xF0,0x00,0x1F,0xFF,0x80,0x00,0x07, +0xF8,0x00,0x0B,0xC0,0x80,0x3A,0xFF,0xFF,0x80,0xFF, +0xFF,0xE0,0xFF,0xFF,0xF0,0xFF,0xFF,0xF8,0xF0,0x00, +0xFC,0xF0,0x00,0x3C,0xF0,0x00,0x3F,0x7E,0x00,0x03, +0xDE,0x00,0x07,0xDE,0x00,0x0F,0x9E,0x00,0x1F,0x9F, +0xFF,0xFF,0x1F,0xFF,0xFE,0x1F,0xFF,0xFC,0x1F,0xFF, +0xE0,0x37,0xC0,0x00,0x06,0x78,0x00,0x00,0x0F,0x44, +0x5F,0x44,0x00,0x1F,0xE0,0x00,0x01,0xFF,0xF0,0x00, +0x0F,0xFF,0xF8,0x00,0x3F,0xFF,0xF8,0x00,0xFE,0x03, +0xF8,0x03,0xF0,0x01,0xF8,0x0F,0xC0,0x01,0xF8,0x1F, +0x00,0x01,0xF0,0x7C,0x00,0x01,0xF2,0x1E,0x00,0x00, +0x3C,0x7C,0x00,0x00,0x7D,0xBE,0x00,0x00,0x0F,0x3C, +0x00,0x00,0x1E,0x7C,0x00,0x00,0x79,0x0F,0x00,0x00, +0x1E,0x1F,0x00,0x70,0x78,0x1F,0x00,0xF9,0xF0,0x3F, +0x01,0xFF,0xC0,0x3F,0x00,0xFF,0x80,0x3F,0x80,0xFE, +0x00,0x3F,0xFF,0xFE,0x00,0x3F,0xFF,0xFE,0x00,0x1F, +0xFF,0xFF,0x00,0x07,0xF8,0x7F,0x00,0x00,0x00,0x3C, +0x00,0x00,0x00,0x18,0x0D,0x40,0x80,0x40,0xFF,0xFF, +0xC0,0x1F,0xFF,0xFE,0x04,0x7F,0xFF,0xFE,0x0F,0x00, +0x07,0xE1,0xE0,0x00,0x3C,0x3C,0x00,0x07,0xCA,0xF0, +0x00,0x0F,0x1E,0x00,0x03,0xE3,0xC0,0x00,0xF8,0x78, +0x00,0x3F,0x0F,0xFF,0xFF,0xC1,0xFF,0xFF,0xF0,0x3F, +0xFF,0xFC,0x07,0xFF,0xFE,0x00,0xF0,0x0F,0x00,0x1E, +0x00,0xF8,0x03,0xC0,0x0F,0x80,0x78,0x00,0xF0,0x0F, +0x00,0x1F,0x01,0xE0,0x01,0xF0,0x3C,0x00,0x1E,0x07, +0x80,0x03,0xE0,0xF0,0x00,0x3E,0x1E,0x00,0x03,0xC3, +0xC0,0x00,0x7C,0x78,0x00,0x07,0x8F,0x00,0x00,0x79, +0xE0,0x00,0x0F,0x80,0x0C,0xC0,0x40,0x3A,0x00,0xFF, +0x00,0x01,0xFF,0xF8,0x00,0xFF,0xFF,0x80,0x7F,0xFF, +0xF0,0x3F,0x80,0xFE,0x0F,0x80,0x0F,0x87,0xC0,0x01, +0xF4,0x3C,0x00,0x07,0x8F,0x00,0x00,0x03,0xE0,0x00, +0x00,0x7C,0x00,0x00,0x1F,0xC0,0x00,0x03,0xFF,0x00, +0x00,0x7F,0xFC,0x00,0x07,0xFF,0xE0,0x00,0x3F,0xFE, +0x00,0x00,0xFF,0xC0,0x00,0x03,0xF8,0x00,0x00,0x3E, +0x00,0x00,0x07,0xE3,0xC0,0x00,0x1E,0xF8,0x00,0x07, +0x9E,0x00,0x01,0xE7,0xC0,0x00,0xF9,0xF8,0x00,0x7C, +0x3F,0x80,0x7F,0x07,0xFF,0xFF,0x80,0xFF,0xFF,0xC0, +0x0F,0xFF,0xC0,0x00,0x7F,0x80,0x00,0x0C,0x40,0x20, +0x35,0x5F,0xFF,0xFF,0xFA,0x00,0x78,0x01,0xA0,0x07, +0x80,0x1A,0x00,0x78,0x01,0xA0,0x07,0x80,0x00,0x0C, +0x40,0x80,0x41,0xBE,0x00,0x01,0xFB,0xE0,0x00,0x1F, +0xBE,0x00,0x01,0xF1,0xE0,0x00,0x1E,0xF8,0x00,0x1F, +0x3C,0x00,0x0F,0x1F,0x00,0x0F,0x8F,0xC0,0x0F,0xC3, +0xF0,0x1F,0xC0,0xFF,0xFF,0xC0,0x3F,0xFF,0xC0,0x0F, +0xFF,0xC0,0x00,0xFF,0x00,0x0E,0xC0,0x00,0x3A,0xF0, +0x00,0x00,0x7B,0xE0,0x00,0x03,0xF0,0xF0,0x00,0x01, +0xE3,0xE0,0x00,0x0F,0xA0,0xF0,0x00,0x07,0x83,0xE0, +0x00,0x3E,0x07,0x80,0x00,0xF0,0x1F,0x00,0x07,0xC4, +0x07,0x80,0x03,0xC0,0x1F,0x00,0x1F,0x08,0x07,0x80, +0x0F,0x00,0x1F,0x00,0x7C,0x00,0x3C,0x01,0xE0,0x00, +0xF8,0x0F,0x81,0x00,0x3C,0x07,0x80,0x00,0xF8,0x3E, +0x02,0x00,0x3C,0x1E,0x00,0x00,0xF8,0xF8,0x00,0x01, +0xE3,0xC0,0x00,0x07,0xDF,0x00,0x40,0x01,0xEF,0x00, +0x00,0x07,0xFC,0x00,0x90,0x01,0xFC,0x00,0x00,0x15, +0xC0,0x20,0x59,0x1E,0x00,0x07,0xF0,0x00,0x3C,0xF0, +0x00,0x7F,0x00,0x07,0x8F,0x00,0x0F,0xF0,0x00,0x7A, +0x1E,0x00,0x1E,0xF0,0x00,0xF0,0xF0,0x01,0xEF,0x00, +0x1E,0x41,0xE0,0x07,0x8F,0x00,0x3C,0x0E,0x00,0x78, +0xF0,0x03,0xC0,0xF0,0x0F,0x8F,0x80,0x78,0x81,0xE0, +0x1E,0x0F,0x00,0xF0,0x0E,0x01,0xE0,0xF0,0x0E,0x00, +0xE0,0x3C,0x07,0x80,0xE1,0x01,0xE0,0x78,0x0F,0x03, +0xC0,0x0E,0x0F,0x80,0x78,0x38,0x00,0xE0,0xF0,0x07, +0x83,0x82,0x01,0xE1,0xE0,0x0F,0x0F,0x04,0x01,0xC7, +0x80,0x0F,0x1C,0x00,0x1E,0x78,0x00,0xF3,0xC0,0x01, +0xEF,0x00,0x07,0xBC,0x08,0x01,0xDE,0x00,0x0F,0x70, +0x00,0x1F,0xE0,0x00,0xFF,0x01,0x20,0x1F,0x80,0x00, +0xFC,0x00,0x01,0xF0,0x00,0x07,0xC0,0x00,0x0E,0xC0, +0x00,0x3A,0x3E,0x00,0x03,0xE0,0x7C,0x00,0x1F,0x00, +0xF0,0x00,0x78,0x03,0xE0,0x03,0xE0,0x07,0xC0,0x1F, +0x00,0x0F,0x00,0xF8,0x00,0x1E,0x03,0xC0,0x00,0x7C, +0x1F,0x00,0x00,0xF8,0xF8,0x00,0x01,0xE3,0xC0,0x00, +0x07,0xDF,0x00,0x00,0x0F,0xF8,0x01,0x00,0x03,0xF8, +0x00,0x00,0x07,0xC0,0x00,0x00,0x3F,0x00,0x00,0x00, +0xFE,0x00,0x00,0x07,0xFC,0x00,0x00,0x3E,0xF8,0x00, +0x00,0xF1,0xE0,0x00,0x07,0xC7,0xC0,0x00,0x3E,0x0F, +0x80,0x00,0xF0,0x1E,0x00,0x07,0xC0,0x7C,0x00,0x3E, +0x00,0xF8,0x00,0xF0,0x01,0xE0,0x07,0xC0,0x03,0xC0, +0x3E,0x00,0x0F,0x81,0xF0,0x00,0x1F,0x07,0x80,0x00, +0x3C,0x3E,0x00,0x00,0xF9,0xF0,0x00,0x01,0xF0,0x0E, +0x40,0x00,0x38,0xF8,0x00,0x01,0xF3,0xE0,0x00,0x1F, +0x0F,0x00,0x00,0xF0,0x7C,0x00,0x0F,0x81,0xE0,0x00, +0xF8,0x07,0x80,0x07,0x80,0x3E,0x00,0x7C,0x00,0xF0, +0x03,0xC0,0x03,0xC0,0x3C,0x00,0x1F,0x03,0xE0,0x00, +0x78,0x1E,0x00,0x03,0xE1,0xF0,0x00,0x0F,0x9F,0x00, +0x00,0x3C,0xF0,0x00,0x01,0xFF,0x80,0x00,0x07,0xF8, +0x01,0x00,0x03,0xF0,0x01,0xA0,0x01,0xE0,0x01,0xA0, +0x01,0xE0,0x00,0x0C,0xC0,0x20,0x37,0x47,0xFF,0xFF, +0xE0,0x00,0x00,0xF8,0x00,0x00,0x7C,0x00,0x00,0x3E, +0x00,0x00,0x1F,0x00,0x00,0x07,0x80,0x00,0x03,0xE0, +0x00,0x01,0xF0,0x00,0x00,0xF8,0x00,0x00,0x7C,0x00, +0x00,0x1E,0x00,0x00,0x0F,0x80,0x00,0x07,0xC0,0x00, +0x03,0xE0,0x00,0x01,0xF0,0x00,0x80,0x1F,0x00,0x00, +0x0F,0x80,0x00,0x07,0xC0,0x00,0x03,0xE0,0x00,0x10, +0x3E,0x00,0x00,0x1F,0x00,0x00,0x0F,0x80,0x00,0x07, +0xC0,0x00,0x02,0xBF,0xFF,0xFF,0xE0,0x04,0x52,0x7B, +0x99,0x5F,0xFB,0xE1,0xBE,0x1B,0xE1,0xBE,0x17,0xE1, +0x5F,0xE0,0x06,0x40,0x20,0x19,0x1C,0x01,0x2E,0x00, +0x78,0x09,0x38,0x09,0x1C,0x00,0xF0,0x48,0x70,0x50, +0x38,0x48,0x1C,0x00,0xF2,0x40,0x72,0x40,0x38,0x01, +0xE0,0x07,0x04,0x52,0x3B,0x99,0x5F,0xFA,0x1F,0xA1, +0xFA,0x1F,0xA1,0xF6,0x1F,0x5F,0xE0,0x08,0xA2,0x27, +0xA6,0x01,0xC0,0x48,0x1F,0x02,0x01,0xDC,0x00,0xF7, +0x80,0x38,0xE0,0x1E,0x38,0x07,0x8F,0x01,0xC1,0xC4, +0x1E,0x0F,0x25,0xE0,0x3C,0xF0,0x07,0x80,0x0C,0x89, +0xFB,0xB1,0x5F,0xFF,0xFF,0xF0,0x04,0x0C,0x4D,0x1E, +0xF8,0x3E,0x0F,0x03,0xC0,0xE0,0x38,0x0A,0x30,0x40, +0x30,0x01,0xFC,0x00,0x7F,0xFC,0x07,0xFF,0xF0,0x7F, +0xFF,0x83,0xE0,0x7E,0x3E,0x01,0xF1,0xF0,0x07,0x83, +0x00,0x3C,0x00,0x01,0xE0,0x00,0x3F,0x00,0x7F,0xF8, +0x1F,0xFF,0xC3,0xFF,0xFE,0x3F,0xFC,0xF1,0xF8,0x07, +0x9F,0x00,0x3C,0xF0,0x01,0xE7,0x80,0x1F,0x3C,0x01, +0xF9,0xF8,0x3F,0xC7,0xFF,0xFE,0x3F,0xFE,0xF0,0xFF, +0xE7,0xC1,0xFC,0x1E,0x0A,0x40,0x60,0x33,0xBE,0x00, +0x00,0xF0,0x00,0x07,0x87,0xC0,0x3C,0xFF,0x81,0xEF, +0xFF,0x0F,0xFF,0xFC,0x7F,0x87,0xE3,0xF0,0x0F,0xA3, +0xE0,0x07,0xB7,0xC0,0x03,0xDE,0x00,0x1F,0x1F,0x00, +0x3C,0xFC,0x03,0xE7,0xF8,0x7E,0x3F,0xFF,0xE1,0xEF, +0xFE,0x0F,0x3F,0xE0,0x78,0x7C,0x00,0x0A,0x30,0x40, +0x2C,0x01,0xF8,0x00,0x3F,0xF8,0x07,0xFF,0xE0,0x7F, +0xFF,0x83,0xF0,0xFC,0x3E,0x01,0xF1,0xE0,0x0F,0x8F, +0x00,0x31,0xBE,0x00,0x00,0xF0,0x00,0xC7,0xC0,0x07, +0x9E,0x00,0x7C,0xF8,0x07,0xC3,0xF0,0x7E,0x1F,0xFF, +0xE0,0x7F,0xFE,0x00,0xFF,0xE0,0x01,0xFC,0x00,0x0A, +0x40,0x40,0x31,0xA0,0x00,0x1E,0x00,0x00,0xF0,0x0F, +0x87,0x81,0xFF,0x3C,0x3F,0xFD,0xE3,0xFF,0xFF,0x1F, +0x87,0xF9,0xF0,0x0F,0xE1,0xE0,0x07,0xF7,0xC0,0x03, +0xDE,0x00,0x1F,0x0F,0x00,0x3E,0x7C,0x03,0xF1,0xF8, +0x7F,0x87,0xFF,0xFC,0x3F,0xFD,0xE0,0x7F,0xCF,0x00, +0xF8,0x78,0x0A,0x30,0x40,0x30,0x01,0xF8,0x00,0x3F, +0xF0,0x07,0xFF,0xE0,0x3F,0xFF,0x83,0xE0,0x7C,0x3E, +0x01,0xF1,0xE0,0x07,0x8E,0x00,0x1C,0xF0,0x00,0xFA, +0xFF,0xFF,0xF9,0xF0,0x00,0x07,0xC0,0x06,0x1E,0x00, +0x7C,0xF8,0x07,0xC3,0xF0,0x7E,0x1F,0xFF,0xE0,0x7F, +0xFE,0x00,0xFF,0xE0,0x01,0xFC,0x00,0x06,0xC0,0x20, +0x1A,0x03,0xF8,0x1F,0xE0,0xFF,0x87,0xFE,0x1F,0x05, +0x0F,0x02,0xBF,0xF9,0xA3,0xC0,0xD1,0xE0,0x58,0xF0, +0x00,0x0A,0x42,0x5B,0xB2,0x03,0xF0,0x00,0x3F,0xE7, +0x87,0xFF,0xFC,0x7F,0xFF,0xE3,0xF0,0xFF,0x3E,0x01, +0xFC,0x3C,0x00,0xFE,0xF8,0x00,0x7B,0xC0,0x03,0xE1, +0xE0,0x07,0xCF,0x80,0x7E,0x3F,0x0F,0xF8,0x1F,0xFF, +0xF0,0x7F,0xE7,0x80,0xFE,0x3C,0x00,0x01,0xE6,0x00, +0x0F,0x3C,0x00,0xF1,0xF0,0x0F,0x87,0xC0,0xFC,0x3F, +0xFF,0xC0,0xFF,0xFC,0x03,0xFF,0xC0,0x07,0xF8,0x00, +0x09,0x40,0x60,0x31,0xBE,0x00,0x03,0xC0,0x00,0x78, +0x7C,0x0F,0x3F,0xE1,0xEF,0xFE,0x3F,0xFF,0xE7,0xF0, +0x7C,0xFC,0x07,0xE3,0xE0,0x0F,0xDF,0x00,0x3F,0x7C, +0x00,0xF8,0xF0,0x03,0xC0,0x02,0x40,0x60,0x15,0x5F, +0x61,0xBF,0xBF,0xBF,0x1E,0x04,0xD3,0xDB,0x95,0x40, +0xFB,0x00,0x68,0x3F,0x41,0xFA,0x0F,0xC0,0x78,0x3E, +0x7F,0x3F,0xCF,0xE3,0xF0,0x09,0xC0,0x60,0x2D,0xBE, +0x00,0x02,0x3C,0x00,0x03,0xC0,0x3E,0x3C,0x07,0xC3, +0xC0,0xF8,0x3C,0x1F,0x03,0xC3,0xE0,0x3C,0x7C,0x03, +0xCF,0x80,0x3D,0xF0,0x03,0xFE,0x00,0x3F,0xF0,0x03, +0xFF,0x80,0x3F,0x78,0x03,0xE7,0xC0,0x3C,0x3E,0x03, +0xC1,0xE0,0x3C,0x1F,0x03,0xC0,0xF8,0x3C,0x07,0x83, +0xC0,0x7C,0x3C,0x03,0xE3,0xC0,0x1E,0x3C,0x01,0xF3, +0xC0,0x0F,0x80,0x02,0x40,0x60,0x15,0xBF,0xBF,0xBF, +0xBF,0x5E,0x10,0x30,0x60,0x4C,0x00,0xFC,0x03,0xF0, +0x79,0xFF,0x07,0xFE,0x3D,0xFF,0xC7,0xFF,0x9E,0xFF, +0xF7,0xFF,0xCF,0xE0,0xFF,0x83,0xF7,0xE0,0x3F,0x80, +0xFB,0xE0,0x0F,0x80,0x3D,0xF0,0x07,0x80,0x1F,0xBE, +0x00,0x78,0x01,0xFB,0xE0,0x07,0x80,0x1F,0x1E,0x00, +0x78,0x01,0xE0,0x09,0x30,0x60,0x30,0x00,0xFC,0x1E, +0x7F,0xC3,0xDF,0xFC,0x7F,0xFF,0xCF,0xE0,0xF9,0xF8, +0x0F,0xC7,0xC0,0x1F,0xBE,0x00,0x7E,0xF8,0x01,0xF1, +0xE0,0x07,0x80,0x0A,0x30,0x40,0x30,0x01,0xF8,0x00, +0x3F,0xF0,0x07,0xFF,0xE0,0x7F,0xFF,0x83,0xF0,0xFC, +0x3E,0x01,0xF1,0xE0,0x07,0x9F,0x00,0x3D,0xBE,0x00, +0x1E,0xF0,0x00,0xF7,0xC0,0x0F,0x9E,0x00,0x78,0xF8, +0x07,0xC3,0xF0,0xFC,0x1F,0xFF,0xE0,0x7F,0xFE,0x00, +0xFF,0xC0,0x01,0xF8,0x00,0x0A,0x42,0x7B,0xB2,0x00, +0xF8,0x07,0x9F,0xF8,0x3D,0xFF,0xE1,0xEF,0xFF,0x8F, +0xF0,0xFC,0x7E,0x01,0xF3,0xF0,0x07,0x9F,0x00,0x3C, +0xF8,0x00,0xFD,0xF0,0x00,0xF8,0xF8,0x01,0xE7,0xE0, +0x1F,0x3F,0xC3,0xF1,0xFF,0xFF,0x0F,0x7F,0xF0,0x79, +0xFF,0x03,0xC7,0xE0,0x37,0xC0,0x00,0x23,0xC0,0x00, +0x00,0x0A,0x42,0x5B,0xB2,0x01,0xF0,0x00,0x7F,0xE7, +0x87,0xFF,0xBC,0x7F,0xFD,0xE3,0xF0,0xFF,0x3E,0x01, +0xF9,0xE0,0x0F,0xCF,0x00,0x3E,0xF0,0x01,0xFD,0xF0, +0x00,0xF8,0x78,0x01,0xF3,0xE0,0x1F,0x8F,0xC3,0xFC, +0x3F,0xFF,0xE0,0xFF,0xEF,0x03,0xFE,0x78,0x07,0xC3, +0xF4,0x00,0x03,0xE0,0x00,0x03,0xC0,0x06,0xB0,0x60, +0x1E,0x03,0xE3,0x9F,0xEE,0xFF,0xBF,0xFC,0xFE,0x34, +0x7C,0x03,0x7C,0x01,0xBE,0x00,0x9F,0x00,0x00,0x09, +0x30,0x40,0x2C,0x03,0xF0,0x01,0xFF,0x80,0x7F,0xFC, +0x1F,0xFF,0x87,0xC1,0xF8,0xF0,0x1F,0x1E,0x01,0x83, +0xC0,0x00,0x7E,0x00,0x07,0xF8,0x00,0xFF,0xE0,0x0F, +0xFF,0x00,0x7F,0xF0,0x03,0xFF,0x00,0x07,0xF0,0x00, +0x3E,0x30,0x03,0xDE,0x00,0x7B,0xE0,0x1F,0x3E,0x07, +0xC7,0xFF,0xF8,0x7F,0xFE,0x07,0xFF,0x80,0x3F,0xC0, +0x05,0xBE,0x20,0x18,0x02,0x00,0xE1,0x83,0xC2,0xBF, +0xF6,0x8F,0x0D,0x1E,0x01,0xE1,0x03,0xF8,0x1F,0xC0, +0xFC,0x09,0x2E,0x60,0x31,0xBE,0x00,0x7E,0xF8,0x01, +0xF1,0xE0,0x07,0xBC,0x01,0xF7,0xC0,0x7E,0xFC,0x1F, +0xE1,0xFF,0xEF,0x1F,0xF9,0xE0,0xFC,0x3C,0x0A,0xAE, +0x20,0x2E,0xF0,0x00,0x7C,0xBC,0x00,0x7A,0x4F,0x00, +0x79,0x03,0xC0,0x78,0x90,0xF0,0x78,0x48,0x3C,0x78, +0x24,0x0F,0x78,0x10,0x03,0xF8,0x09,0x00,0xF8,0x00, +0x10,0xAE,0x00,0x43,0x1E,0x00,0x7C,0x00,0xF7,0x80, +0x1F,0x00,0x7E,0x1E,0x01,0xFC,0x03,0xC7,0x80,0x77, +0x01,0xF0,0xF0,0x1D,0xE0,0x78,0x3C,0x0F,0x78,0x1E, +0x07,0x83,0xDE,0x0F,0x81,0xE0,0xE3,0x83,0xC0,0x78, +0x78,0xF0,0xF1,0x01,0xE3,0xC7,0x8F,0x00,0x78,0xE0, +0xE3,0xC0,0x0E,0x78,0x3D,0xE0,0x03,0xDE,0x0F,0x78, +0x00,0xF7,0x03,0xDE,0x00,0x1D,0xC0,0x77,0x02,0x00, +0xFE,0x03,0xF8,0x12,0x03,0xE0,0x0F,0x80,0x0B,0x2E, +0x00,0x2C,0x7C,0x00,0x78,0x7C,0x01,0xF0,0x7C,0x07, +0xC0,0xF8,0x1F,0x00,0xF8,0x3C,0x00,0xF8,0xF8,0x00, +0xF3,0xE0,0x01,0xFF,0x80,0x01,0xFE,0x00,0x01,0xFC, +0x04,0x00,0x7E,0x00,0x00,0xFE,0x00,0x03,0xFC,0x00, +0x0F,0xFC,0x00,0x1E,0x7C,0x00,0x7C,0x78,0x01,0xF0, +0xF8,0x07,0xC0,0xF8,0x0F,0x00,0xF8,0x3E,0x00,0xF0, +0xF8,0x01,0xF3,0xE0,0x01,0xF0,0x0A,0xC0,0x1B,0xAA, +0xF0,0x00,0x79,0xE0,0x03,0xE7,0x80,0x0F,0x1F,0x00, +0x3C,0x3C,0x01,0xF0,0xF0,0x07,0x81,0xE0,0x1E,0x07, +0x80,0xF8,0x1F,0x03,0xC0,0x3C,0x0F,0x00,0xF0,0x7C, +0x40,0x3C,0x3C,0x00,0xF9,0xF0,0x01,0xE7,0x80,0x07, +0xDE,0x00,0x0F,0x70,0x20,0x07,0xF8,0x10,0x01,0xF8, +0x00,0x03,0xE0,0x20,0x01,0xE0,0x00,0x0F,0x80,0x00, +0x3C,0x00,0x01,0xF0,0x00,0x0F,0x80,0x03,0xFE,0x00, +0x0F,0xF0,0x00,0x1F,0x80,0x00,0x7C,0x00,0x00,0x0A, +0x2E,0x20,0x2D,0x4F,0xFF,0xFC,0x00,0x07,0xC0,0x00, +0x7C,0x00,0x07,0xC0,0x00,0x7C,0x00,0x07,0xE0,0x00, +0x3E,0x00,0x03,0xE0,0x00,0x3E,0x00,0x03,0xE0,0x00, +0x3E,0x00,0x03,0xE0,0x00,0x3E,0x00,0x03,0xF0,0x00, +0x1F,0x00,0x01,0xF0,0x00,0x2B,0xFF,0xFF,0xC0,0x06, +0x52,0x3B,0x9E,0x01,0xF0,0x1F,0x81,0xFC,0x1F,0xE0, +0xF8,0xD0,0xF0,0xA0,0xF0,0x0F,0x00,0xF8,0x1F,0x81, +0x1E,0x00,0xFC,0x01,0xF0,0x40,0xF0,0x68,0x78,0x50, +0x78,0x03,0xE2,0x01,0xFC,0x07,0xE0,0x1F,0x01,0xD2, +0x9B,0x97,0xBF,0x7E,0xFD,0xFB,0xF3,0x80,0x06,0x52, +0x5B,0x9E,0xF8,0x07,0xE0,0x47,0xF0,0x07,0xC3,0x43, +0xC2,0x83,0xC0,0x0F,0x00,0x7C,0x01,0xFC,0x00,0x78, +0x0F,0xC0,0xF8,0x07,0x80,0x7C,0x68,0x78,0x50,0x78, +0x07,0xC2,0x3F,0x81,0xF8,0x0F,0x80,0x0B,0x10,0x45, +0xB4,0x0F,0x80,0x00,0x7F,0xC0,0x09,0xFF,0xE0,0x37, +0xFF,0xE1,0xEF,0x0F,0xFF,0xD8,0x07,0xFF,0x20,0x07, +0xFC,0x00,0x03,0xE0,}; +/* font data size: 4974 bytes */ + +static const unsigned char Arial_32_index[] = { +0x00,0x00,0x01,0x00,0x20,0x01, +0xC0,0x24,0x82,0x8C,0x25,0x61,0x95,0x0C,0xE0,0x71, +0xC3,0xE4,0x20,0xB1,0x10,0x08,0xA4,0x45,0xE2,0x34, +0x12,0x90,0xA2,0x05,0x46,0x2F,0x21,0xA3,0x0E,0x18, +0x78,0x64,0x15,0x22,0x09,0x21,0x49,0xA8,0x4D,0xD2, +0x74,0x94,0x9C,0xA6,0xA5,0x73,0x2D,0xB9,0xA4,0xCD, +0xE2,0x73,0x63,0xCC,0x9F,0xA5,0x00,0xA8,0x1F,0x43, +0xFA,0x26,0x11,0x42,0x8C,0x24,0x97,0xA5,0x09,0x2F, +0x49,0xD2,0x51,0xA2,0x9B,0x15,0xAC,0xB3,0xA5,0xD0, +0xAE,0xDD,0x7C,0xAC,0x43,0x66,0x23,0x4F,0x5B,0x0E, +0xDD,0xB6,0xF5,0x38,0x21,0xC2,0xEE,0x36,0x71,0xF3, +0x92,0x5D,0x18,0xEC,0x17,0x7A,0xBC,0xA9,0xEC,0x2F, +0x79,0x7D,0xF3,0xF8,0x5F,0xD6,0xFF,0xF8,0x21,0xC1, +0x32,0x0F,0xF0,0x9D,0x86,0x8C,0x42,0x62,0x83,0x15, +0x78,0xCA,0x46,0xA6,0x38,0x91,0xE4,0x91,0x94,0x9D, +0xA5,0x93,0x2F,0xB9,0x91,0x4C,0xB2,0x6A,0x60, +}; +/* font index size: 155 bytes */ + +const ILI9341_t3_font_t Arial_32 = { + Arial_32_index, + 0, + Arial_32_data, + 1, + 0, + 32, + 126, + 0, + 0, + 13, + 6, + 6, + 4, + 6, + 6, + 48, + 32 +}; + + + +static const unsigned char Arial_40_data[] = { +0x00,0x00,0x00,0x10,0x02,0xD0,0xC0,0x11,0xDF,0xEF, +0xF3,0xFA,0xEA,0x75,0x02,0xFE,0x07,0x9C,0x46,0x94, +0xDF,0x83,0xF3,0xF0,0x7E,0x9C,0x07,0x00,0x0E,0xD0, +0x20,0x1F,0x80,0x03,0xE0,0x3E,0x00,0x1F,0x81,0xF9, +0x40,0x0F,0x80,0xF8,0x00,0x7E,0x07,0xE2,0x40,0x3E, +0x03,0xE1,0x7F,0xFF,0xFF,0xFF,0x00,0xF8,0x0F,0x80, +0x07,0xE0,0x7E,0x0A,0x03,0xE0,0x3E,0x00,0x1F,0x81, +0xF8,0x10,0x0F,0x80,0xF8,0x0B,0xFF,0xFF,0xFF,0xFC, +0x07,0xC0,0x7C,0x00,0x3F,0x03,0xF0,0x0A,0x1F,0x01, +0xF0,0x00,0xFC,0x0F,0xC0,0x10,0x7C,0x07,0xC0,0x00, +0x0D,0xDC,0x5E,0xDF,0x80,0x00,0xE0,0x00,0x00,0x7F, +0xC0,0x00,0x3F,0xFF,0x00,0x07,0xFF,0xFC,0x01,0xFF, +0xFF,0xE0,0x1F,0xFF,0xFF,0x03,0xFC,0xE7,0xF0,0x3F, +0x0E,0x1F,0x87,0xE0,0xE0,0xF8,0x7C,0x0E,0x0F,0xC7, +0xC0,0xE0,0x7C,0x7C,0x0E,0x07,0x07,0xC0,0xE0,0x00, +0x7E,0x0E,0x00,0x03,0xF0,0xE0,0x00,0x3F,0xCE,0x00, +0x01,0xFF,0xE0,0x00,0x0F,0xFF,0x00,0x00,0x7F,0xFF, +0x00,0x01,0xFF,0xFC,0x00,0x07,0xFF,0xE0,0x00,0x0F, +0xFF,0x00,0x00,0xEF,0xF8,0x00,0x0E,0x3F,0xC0,0x00, +0xE0,0xFC,0x00,0x0E,0x07,0xE0,0x00,0xE0,0x3E,0x38, +0x0E,0x03,0xEF,0x80,0xE0,0x3F,0x1F,0x81,0xC0,0x7C, +0xF8,0x1C,0x0F,0xCF,0xC1,0xC1,0xF8,0xFE,0x1C,0x3F, +0x87,0xF9,0xCF,0xF0,0x3F,0xFF,0xFF,0x01,0xFF,0xFF, +0xE0,0x0F,0xFF,0xFC,0x00,0x7F,0xFF,0x00,0x00,0xFF, +0x80,0x2C,0x00,0x38,0x00,0x00,0x16,0x50,0x60,0x32, +0x03,0xF0,0x00,0x00,0xF0,0x00,0x3F,0xE0,0x00,0x0F, +0x80,0x03,0xFF,0x80,0x00,0x78,0x00,0x3E,0x3E,0x00, +0x07,0xC0,0x03,0xE0,0xF8,0x00,0x3C,0x00,0x1E,0x03, +0xC0,0x03,0xE0,0x00,0xE0,0x1E,0x00,0x1E,0x00,0x0F, +0x00,0x78,0x01,0xE0,0x00,0x78,0x03,0xC0,0x1F,0x00, +0x03,0xC0,0x1E,0x00,0xF0,0x00,0x1E,0x00,0xF0,0x0F, +0x80,0x00,0xF0,0x07,0x80,0x78,0x00,0x07,0x80,0x3C, +0x07,0xC0,0x00,0x3C,0x01,0xE0,0x3C,0x00,0x01,0xE0, +0x0F,0x03,0xE0,0x00,0x07,0x00,0xF0,0x3E,0x00,0x00, +0x3C,0x07,0x81,0xE0,0x00,0x01,0xE0,0x7C,0x1F,0x00, +0x00,0x07,0xC7,0xC0,0xF0,0x1F,0x80,0x1F,0xFC,0x0F, +0x81,0xFF,0x00,0x7F,0xC0,0x78,0x1F,0xFC,0x00,0xF8, +0x07,0xC1,0xF1,0xF0,0x00,0x00,0x7C,0x1E,0x07,0xC0, +0x00,0x03,0xC0,0xF0,0x1E,0x00,0x00,0x3E,0x07,0x00, +0xF0,0x00,0x01,0xE0,0x78,0x03,0xC0,0x00,0x1F,0x03, +0xC0,0x1E,0x00,0x00,0xF0,0x1E,0x00,0xF0,0x00,0x0F, +0x80,0xF0,0x07,0x80,0x00,0xF8,0x07,0x80,0x3C,0x00, +0x07,0x80,0x3C,0x01,0xE0,0x00,0x7C,0x01,0xE0,0x0F, +0x00,0x03,0xC0,0x0F,0x00,0x78,0x00,0x3E,0x00,0x38, +0x07,0x80,0x01,0xE0,0x01,0xE0,0x3C,0x00,0x1F,0x00, +0x0F,0x03,0xE0,0x01,0xF0,0x00,0x3E,0x3E,0x00,0x0F, +0x00,0x00,0xFF,0xE0,0x00,0xF8,0x00,0x03,0xFE,0x00, +0x07,0x80,0x00,0x07,0xC0,0x10,0xD0,0x60,0x25,0x00, +0x0F,0xE0,0x00,0x00,0x0F,0xFE,0x00,0x00,0x07,0xFF, +0xC0,0x00,0x03,0xFF,0xF8,0x00,0x01,0xFF,0xFF,0x00, +0x00,0x7E,0x0F,0xC0,0x00,0x3F,0x01,0xF8,0x02,0x81, +0xF0,0x07,0xC0,0x00,0x3E,0x03,0xE0,0x00,0x0F,0xC1, +0xF8,0x00,0x03,0xF0,0xFC,0x00,0x00,0x7E,0xFE,0x00, +0x00,0x0F,0xFF,0x00,0x00,0x01,0xFF,0x00,0x00,0x00, +0xFF,0x00,0x00,0x00,0xFF,0xC0,0x00,0x00,0x7F,0xF8, +0x00,0x00,0x3F,0xBF,0x00,0x00,0x1F,0x87,0xE0,0x20, +0x0F,0xC1,0xFC,0x0F,0x87,0xE0,0x3F,0x07,0xE1,0xF0, +0x07,0xE1,0xF0,0xFC,0x00,0xFC,0xFC,0x3E,0x00,0x1F, +0xFF,0x0F,0x80,0x07,0xFF,0x83,0xE0,0x00,0xFF,0xE0, +0xF8,0x00,0x1F,0xF0,0x47,0xE0,0x00,0x7F,0x00,0xFC, +0x00,0x3F,0xE0,0x3F,0x80,0x1F,0xFC,0x07,0xF8,0x3F, +0xFF,0x81,0xFF,0xFF,0xF7,0xF8,0x3F,0xFF,0xF8,0xFF, +0x03,0xFF,0xFC,0x1F,0x80,0x7F,0xFC,0x03,0xC0,0x03, +0xF8,0x00,0x60,0x02,0x9C,0x66,0x8B,0xDF,0xCF,0xE9, +0xC0,0x07,0x66,0x7D,0x53,0x00,0x1E,0x00,0x78,0x01, +0xE0,0x07,0xC0,0x0F,0x00,0x3E,0x00,0xF8,0x01,0xE0, +0x07,0xC0,0x0F,0x02,0x07,0xC0,0x93,0xE0,0x29,0xF0, +0x0D,0xF8,0x02,0xFE,0x00,0x3C,0x01,0x4F,0x80,0x41, +0xF0,0x01,0xE0,0x20,0x7C,0x08,0x0F,0x80,0x0F,0x00, +0x1F,0x00,0x1F,0x00,0x1E,0x00,0x3E,0x00,0x3C,0x00, +0x3C,0x00,0x3C,0x07,0x66,0x5D,0x53,0x78,0x00,0x78, +0x00,0x78,0x00,0xF8,0x00,0xF0,0x01,0xF0,0x01,0xE0, +0x01,0xE0,0x03,0xE0,0x03,0xC2,0x00,0xF8,0x00,0xF1, +0x00,0x3E,0x58,0x07,0xDA,0x00,0xFD,0x00,0x3F,0x60, +0x1F,0x40,0x0F,0x80,0x1E,0x20,0x0F,0x88,0x07,0xC0, +0x1F,0x00,0x3C,0x00,0xF8,0x01,0xE0,0x07,0xC0,0x0F, +0x00,0x3C,0x00,0xF0,0x00,0x09,0x22,0x45,0xD6,0xA0, +0x1E,0x00,0x83,0xC1,0x1E,0x79,0xE7,0xFE,0xFE,0xFF, +0xFF,0xC7,0xFF,0xE0,0x07,0xC0,0x01,0xF8,0x00,0x7F, +0x80,0x1E,0x78,0x07,0xCF,0x81,0xF0,0xF8,0x1C,0x0E, +0x00,0x81,0x00,0x0D,0xB6,0x61,0xA1,0xD0,0x01,0xF0, +0x01,0x40,0x03,0xE0,0x02,0xFF,0xFF,0xFF,0xFE,0x80, +0x0F,0x80,0x0A,0x00,0x1F,0x00,0x00,0x02,0x9A,0xBE, +0x10,0xBF,0xD1,0xC6,0x39,0xC2,0x00,0x08,0x0A,0x23, +0x13,0xBF,0xFF,0xF0,0x02,0x8A,0xA0,0x10,0xBF,0x80, +0x08,0x50,0x00,0x10,0x80,0x00,0xF9,0x00,0x1E,0x90, +0x03,0xC0,0x03,0xE4,0x80,0x3C,0x48,0x07,0x84,0x80, +0xF0,0x00,0xF8,0x24,0x0F,0x02,0x41,0xE0,0x24,0x3C, +0x00,0x3E,0x01,0x23,0xC0,0x12,0x78,0x01,0x2F,0x00, +0x0F,0x80,0x07,0x80,0x00,0x0C,0xCE,0x60,0x1F,0x00, +0x3F,0x80,0x00,0x7F,0xFC,0x00,0x3F,0xFF,0x80,0x1F, +0xFF,0xF0,0x0F,0xFF,0xFE,0x03,0xF8,0x3F,0x81,0xF8, +0x03,0xF0,0x7C,0x00,0x7C,0x3F,0x00,0x1F,0xA5,0xF0, +0x00,0x7D,0xBF,0x00,0x01,0xFD,0xF8,0x00,0x0F,0xBE, +0x00,0x03,0xF2,0xF8,0x00,0x3E,0x3F,0x00,0x1F,0x87, +0xC0,0x07,0xC1,0xF8,0x03,0xF0,0x3F,0x83,0xF8,0x0F, +0xFF,0xFE,0x01,0xFF,0xFF,0x00,0x3F,0xFF,0x80,0x07, +0xFF,0xC0,0x00,0x3F,0x80,0x00,0x07,0xCE,0xC0,0x1F, +0x80,0x01,0xE0,0x03,0xE0,0x07,0xE0,0x0F,0xE0,0x1F, +0xE0,0x3F,0xE0,0xFF,0xE3,0xFF,0xE7,0xFB,0xEF,0xF3, +0xEF,0xC3,0xEF,0x03,0xEC,0x03,0xFA,0x00,0x7F,0x40, +0x0F,0xE8,0x01,0xFA,0x00,0x3E,0x0D,0x4E,0x40,0x1F, +0x00,0x3F,0xE0,0x00,0x1F,0xFF,0x00,0x0F,0xFF,0xF8, +0x03,0xFF,0xFF,0x80,0xFF,0xFF,0xF8,0x1F,0xC0,0x7F, +0x87,0xF0,0x03,0xF0,0xFC,0x00,0x3E,0x3F,0x00,0x07, +0xF0,0xF8,0x00,0x0F,0x87,0x00,0x01,0xF8,0x00,0x00, +0x07,0xE0,0x00,0x00,0x3E,0x00,0x00,0x0F,0xC0,0x00, +0x03,0xF0,0x00,0x00,0xFC,0x00,0x00,0x3F,0x00,0x00, +0x0F,0xE0,0x00,0x03,0xF8,0x00,0x00,0xFE,0x00,0x00, +0x7F,0x80,0x00,0x1F,0xC0,0x00,0x07,0xF0,0x00,0x01, +0xFC,0x00,0x00,0xFF,0x00,0x00,0x3F,0xC0,0x00,0x0F, +0xE0,0x00,0x03,0xF8,0x00,0x00,0x7E,0x00,0x00,0x1F, +0x80,0x00,0x07,0xE0,0x00,0x02,0x1F,0xFF,0xFF,0xF9, +0xFF,0xFF,0xFF,0xC0,0x0C,0xCE,0x60,0x1F,0x00,0x7F, +0x00,0x00,0x7F,0xF8,0x00,0x7F,0xFF,0x00,0x3F,0xFF, +0xF0,0x1F,0xFF,0xFC,0x07,0xF0,0x3F,0x83,0xF0,0x07, +0xE0,0xF8,0x00,0xFC,0x7E,0x00,0x1F,0x1F,0x00,0x07, +0xC1,0xC0,0x01,0xF0,0x00,0x00,0x7C,0x00,0x00,0x3E, +0x00,0x00,0x1F,0x80,0x00,0x1F,0xC0,0x00,0x7F,0xE0, +0x00,0x1F,0xE0,0x00,0x07,0xFC,0x00,0x01,0xFF,0xC0, +0x00,0xEF,0xF8,0x00,0x00,0x3F,0x00,0x00,0x07,0xE0, +0x00,0x00,0xF8,0x00,0x00,0x3F,0x90,0x00,0x00,0xF8, +0xE0,0x00,0x3E,0xF8,0x00,0x0F,0xBF,0x00,0x07,0xEF, +0xC0,0x01,0xF1,0xF8,0x00,0xFC,0x7F,0x00,0x7F,0x0F, +0xE0,0x7F,0x83,0xFF,0xFF,0xC0,0x7F,0xFF,0xE0,0x0F, +0xFF,0xF0,0x00,0xFF,0xF8,0x00,0x0F,0xF0,0x00,0x0D, +0xCE,0x20,0x1F,0x00,0x00,0x1E,0x00,0x00,0x03,0xE0, +0x00,0x00,0x7E,0x08,0x00,0x01,0xFC,0x00,0x00,0x3F, +0xC0,0x00,0x07,0xFC,0x10,0x00,0x1F,0xF8,0x00,0x03, +0xFF,0x80,0x00,0x7E,0xF8,0x20,0x01,0xF9,0xF0,0x00, +0x3F,0x1F,0x00,0x07,0xE1,0xF0,0x40,0x1F,0x83,0xE0, +0x03,0xF0,0x3E,0x00,0x7E,0x03,0xE0,0x81,0xF8,0x07, +0xC0,0x3F,0x00,0x7C,0x07,0xE0,0x07,0xC0,0xFC,0x00, +0x7C,0x17,0xFF,0xFF,0xFF,0xF4,0x00,0x01,0xF0,0x48, +0x00,0x03,0xE0,0x0C,0xCE,0x60,0x1F,0x80,0x7F,0xFF, +0xE4,0x87,0xFF,0xFF,0x20,0x3E,0x00,0x01,0x03,0xF0, +0x00,0x09,0x1F,0x00,0x00,0x0F,0xC0,0x00,0x03,0xF1, +0xF8,0x00,0xFD,0xFF,0x80,0x3E,0xFF,0xF8,0x0F,0xFF, +0xFF,0x07,0xFF,0xFF,0xE1,0xFE,0x03,0xF8,0x7E,0x00, +0x3F,0x07,0x00,0x07,0xC0,0x00,0x01,0xFE,0x00,0x00, +0x07,0xDF,0x00,0x01,0xF7,0xC0,0x00,0xF9,0xF8,0x00, +0x3E,0x3E,0x00,0x1F,0x8F,0xC0,0x0F,0xC1,0xFC,0x0F, +0xF0,0x7F,0xFF,0xF8,0x0F,0xFF,0xFC,0x01,0xFF,0xFE, +0x00,0x1F,0xFE,0x00,0x01,0xFE,0x00,0x0D,0x4E,0x40, +0x1F,0x00,0x1F,0xE0,0x00,0x0F,0xFF,0x00,0x07,0xFF, +0xF0,0x01,0xFF,0xFF,0x00,0x7F,0xFF,0xF0,0x1F,0xE0, +0xFF,0x03,0xF0,0x07,0xE0,0xFC,0x00,0x7C,0x1F,0x00, +0x0F,0xC7,0xE0,0x00,0xFA,0x5F,0x00,0x00,0x07,0xC0, +0x00,0x00,0xF8,0x1F,0xC0,0x1F,0x0F,0xFE,0x03,0xE7, +0xFF,0xF0,0x7D,0xFF,0xFF,0x0F,0xBF,0xFF,0xF1,0xFF, +0x80,0xFE,0x3F,0xC0,0x0F,0xE7,0xF0,0x00,0xFC,0xFC, +0x00,0x0F,0xEB,0xE0,0x00,0x1F,0x87,0x80,0x00,0x7C, +0xF8,0x00,0x1F,0x9F,0x00,0x03,0xE1,0xF0,0x00,0xFC, +0x3F,0x00,0x3F,0x83,0xF8,0x1F,0xE0,0x3F,0xFF,0xF8, +0x03,0xFF,0xFE,0x00,0x3F,0xFF,0x80,0x03,0xFF,0xE0, +0x00,0x0F,0xE0,0x00,0x0D,0x4E,0x40,0x1F,0xBF,0xFF, +0xFF,0xFC,0x00,0x00,0x0F,0x00,0x00,0x03,0xC0,0x00, +0x00,0xF0,0x00,0x00,0x3C,0x00,0x00,0x0F,0x80,0x00, +0x03,0xE0,0x00,0x00,0x78,0x00,0x00,0x1F,0x02,0x00, +0x00,0xF8,0x08,0x00,0x07,0xC0,0x20,0x00,0x3E,0x00, +0x80,0x01,0xF0,0x02,0x00,0x0F,0x80,0x09,0x00,0x7C, +0x00,0x24,0x03,0xE0,0x00,0x00,0xFC,0x00,0x14,0x03, +0xE0,0x00,0x58,0x1F,0x00,0x00,0x0C,0xCE,0x60,0x1F, +0x00,0x7F,0x80,0x00,0x7F,0xFC,0x00,0x7F,0xFF,0x80, +0x3F,0xFF,0xF0,0x0F,0xFF,0xFE,0x07,0xF0,0x1F,0xC1, +0xF8,0x03,0xF0,0xFC,0x00,0x7E,0xA7,0xC0,0x01,0xF1, +0xF8,0x00,0xFC,0x3E,0x00,0x3E,0x07,0xE0,0x3F,0x00, +0xFF,0xFF,0x80,0x1F,0xFF,0xC0,0x03,0xFF,0xE0,0x03, +0xFF,0xFE,0x01,0xFF,0xFF,0xC0,0xFE,0x03,0xF8,0x7E, +0x00,0x3E,0x1F,0x00,0x0F,0xCF,0xC0,0x01,0xF6,0x7C, +0x00,0x07,0xDF,0x80,0x03,0xF3,0xE0,0x00,0xF8,0xFC, +0x00,0x7E,0x1F,0xC0,0x7F,0x07,0xFF,0xFF,0xC0,0xFF, +0xFF,0xE0,0x1F,0xFF,0xF0,0x01,0xFF,0xF0,0x00,0x0F, +0xE0,0x00,0x0C,0xCE,0x60,0x1F,0x00,0x7F,0x00,0x00, +0x7F,0xF8,0x00,0x7F,0xFF,0x02,0x07,0xFF,0xFE,0x03, +0xFC,0x0F,0xC1,0xFC,0x01,0xF8,0x7E,0x00,0x3E,0x1F, +0x00,0x07,0xCF,0xC0,0x00,0xF4,0x7C,0x00,0x07,0xAB, +0xE0,0x00,0x3E,0xFC,0x00,0x1F,0x9F,0x00,0x0F,0xE7, +0xE0,0x07,0xF8,0xFE,0x03,0xFE,0x3F,0xFF,0xFF,0x87, +0xFF,0xFB,0xE0,0xFF,0xFC,0xF8,0x1F,0xFC,0x3E,0x00, +0xFC,0x0F,0x80,0x00,0x03,0xF2,0x00,0x00,0x3E,0x3E, +0x00,0x1F,0x8F,0x80,0x07,0xC3,0xF0,0x03,0xF0,0x7E, +0x01,0xF8,0x1F,0xC0,0xFE,0x03,0xFF,0xFF,0x00,0x7F, +0xFF,0x80,0x1F,0xFF,0xC0,0x01,0xFF,0xE0,0x00,0x1F, +0xC0,0x00,0x02,0xBA,0xA0,0x10,0xBF,0xE8,0x34,0x16, +0x0B,0xF8,0x02,0xCA,0xBE,0x10,0xBF,0xE8,0x34,0x16, +0x0B,0xFD,0x1E,0x1C,0xE1,0x00,0x0D,0xB6,0x61,0xA1, +0x00,0x00,0x00,0x10,0x00,0x00,0x0F,0x00,0x00,0x03, +0xF0,0x00,0x01,0xFF,0x00,0x00,0x7F,0xF0,0x00,0x3F, +0xFE,0x00,0x0F,0xFF,0x00,0x03,0xFF,0xC0,0x01,0xFF, +0xE0,0x00,0x7F,0xF0,0x00,0x3F,0xFC,0x00,0x07,0xFE, +0x00,0x00,0x7F,0x80,0x00,0x07,0xC0,0x00,0x00,0x7F, +0x80,0x00,0x07,0xFE,0x00,0x00,0x3F,0xFC,0x00,0x00, +0x7F,0xF0,0x00,0x01,0xFF,0xE0,0x00,0x03,0xFF,0xC0, +0x00,0x0F,0xFF,0x00,0x00,0x3F,0xFE,0x00,0x00,0x7F, +0xF0,0x00,0x01,0xFF,0x00,0x00,0x03,0xF0,0x00,0x00, +0x0F,0x00,0x00,0x00,0x10,0x0D,0xA2,0x62,0xE1,0xBF, +0xFF,0xFF,0xFF,0xA0,0x00,0x00,0x02,0xFF,0xFF,0xFF, +0xF8,0x0D,0xB6,0x61,0xA1,0x40,0x00,0x00,0x07,0x80, +0x00,0x00,0x7E,0x00,0x00,0x07,0xFC,0x00,0x00,0x7F, +0xF0,0x00,0x03,0xFF,0xE0,0x00,0x07,0xFF,0x80,0x00, +0x1F,0xFE,0x00,0x00,0x3F,0xFC,0x00,0x00,0x7F,0xF0, +0x00,0x01,0xFF,0xE0,0x00,0x03,0xFF,0x00,0x00,0x0F, +0xF0,0x00,0x00,0x1F,0x00,0x00,0x0F,0xF0,0x00,0x03, +0xFF,0x00,0x01,0xFF,0xE0,0x00,0x7F,0xF0,0x00,0x3F, +0xFC,0x00,0x1F,0xFE,0x00,0x07,0xFF,0x80,0x03,0xFF, +0xE0,0x00,0x7F,0xF0,0x00,0x07,0xFC,0x00,0x00,0x7E, +0x00,0x00,0x07,0x80,0x00,0x00,0x40,0x00,0x00,0x00, +0x0C,0xD0,0x60,0x1F,0x00,0x3F,0xC0,0x00,0x7F,0xFC, +0x00,0x3F,0xFF,0xC0,0x3F,0xFF,0xF8,0x0F,0xFF,0xFF, +0x07,0xF8,0x3F,0xC3,0xF8,0x03,0xF8,0xFC,0x00,0x7E, +0x3E,0x00,0x0F,0xDF,0x80,0x03,0xF7,0xE0,0x00,0x7D, +0xF0,0x00,0x1F,0x1C,0x00,0x07,0xC0,0x00,0x01,0xF0, +0x00,0x00,0xFC,0x00,0x00,0x3E,0x00,0x00,0x1F,0x80, +0x00,0x0F,0xC0,0x00,0x07,0xE0,0x00,0x07,0xF0,0x00, +0x03,0xF8,0x00,0x01,0xFC,0x00,0x00,0xFE,0x00,0x00, +0x7F,0x00,0x00,0x1F,0x80,0x00,0x07,0xC0,0x00,0x03, +0xF0,0x02,0x80,0x1F,0x00,0x14,0x00,0x00,0x00,0xB0, +0x07,0xC0,0x00,0x1A,0x68,0x7D,0x39,0x00,0x00,0x03, +0xFF,0xC0,0x00,0x00,0x00,0x01,0xFF,0xFF,0xE0,0x00, +0x00,0x00,0x3F,0xFF,0xFF,0xC0,0x00,0x00,0x07,0xFF, +0xFF,0xFF,0x80,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0x00, +0x00,0x0F,0xFF,0x00,0x3F,0xFC,0x00,0x00,0xFF,0x80, +0x00,0x1F,0xF0,0x00,0x0F,0xF0,0x00,0x00,0x3F,0xC0, +0x00,0xFE,0x00,0x00,0x00,0x7F,0x00,0x0F,0xE0,0x00, +0x00,0x01,0xF8,0x00,0xFC,0x00,0x7C,0x00,0x07,0xE0, +0x07,0xC0,0x0F,0xF8,0x3E,0x1F,0x80,0x7C,0x01,0xFF, +0xF1,0xF0,0x7C,0x03,0xE0,0x1F,0xFF,0xDF,0x01,0xF0, +0x3E,0x01,0xFF,0xFE,0xF8,0x0F,0x81,0xE0,0x1F,0xE1, +0xFF,0xC0,0x3C,0x1F,0x01,0xFC,0x03,0xFE,0x01,0xF0, +0xF0,0x0F,0xC0,0x0F,0xF0,0x07,0x8F,0x80,0xFC,0x00, +0x7F,0x00,0x3C,0x78,0x07,0xC0,0x01,0xF8,0x01,0xE3, +0xC0,0x7E,0x00,0x0F,0xC0,0x0F,0x1E,0x03,0xE0,0x00, +0x7E,0x00,0x79,0xE0,0x1F,0x00,0x03,0xE0,0x03,0xCF, +0x01,0xF8,0x00,0x1F,0x00,0x1E,0x78,0x0F,0x80,0x00, +0xF8,0x00,0xF3,0xC0,0x7C,0x00,0x07,0xC0,0x0F,0x1E, +0x03,0xE0,0x00,0x7C,0x00,0x78,0xF0,0x1F,0x00,0x03, +0xE0,0x07,0xC7,0x80,0xF8,0x00,0x1F,0x00,0x3C,0x3C, +0x07,0xC0,0x01,0xF8,0x03,0xE1,0xE0,0x3E,0x00,0x0F, +0xC0,0x3E,0x0F,0x01,0xF8,0x00,0xFC,0x03,0xF0,0x7C, +0x07,0xC0,0x0F,0xE0,0x3F,0x01,0xE0,0x3F,0x00,0xFF, +0x03,0xF0,0x0F,0x00,0xFC,0x1F,0xFC,0x7F,0x00,0x7C, +0x07,0xFF,0xFF,0xFF,0xF0,0x03,0xE0,0x1F,0xFF,0xBF, +0xFF,0x00,0x0F,0x80,0x7F,0xF9,0xFF,0xF0,0x00,0x7C, +0x01,0xFF,0x87,0xFE,0x00,0x01,0xF0,0x03,0xE0,0x1F, +0xC0,0x1F,0x0F,0xC0,0x00,0x00,0x00,0x01,0xF0,0x3F, +0x00,0x00,0x00,0x00,0x1F,0x80,0xFC,0x00,0x00,0x00, +0x03,0xF8,0x07,0xF8,0x00,0x00,0x00,0x3F,0x80,0x1F, +0xF0,0x00,0x00,0x07,0xF8,0x00,0x7F,0xE0,0x00,0x00, +0xFF,0x80,0x00,0xFF,0xF0,0x00,0x7F,0xF8,0x00,0x03, +0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x07,0xFF,0xFF,0xFF, +0xF0,0x00,0x00,0x0F,0xFF,0xFF,0xFE,0x00,0x00,0x00, +0x0F,0xFF,0xFF,0x80,0x00,0x00,0x00,0x07,0xFF,0xC0, +0x00,0x00,0x12,0xD0,0x00,0x25,0x80,0x00,0x0F,0x80, +0x00,0x40,0x00,0x0F,0xE0,0x00,0x00,0x00,0x7F,0xC0, +0x00,0x80,0x00,0x3D,0xE0,0x00,0x00,0x01,0xF7,0xC0, +0x00,0x00,0x07,0x8F,0x00,0x00,0x00,0x3E,0x3E,0x00, +0x00,0x00,0xF0,0x78,0x00,0x40,0x00,0xF8,0x3E,0x00, +0x00,0x03,0xC0,0x78,0x00,0x00,0x1F,0x01,0xF0,0x00, +0x00,0x78,0x03,0xC0,0x08,0x00,0x7C,0x01,0xF0,0x00, +0x01,0xE0,0x03,0xC0,0x10,0x01,0xF0,0x01,0xF0,0x00, +0x0F,0x80,0x03,0xE0,0x20,0x07,0xFF,0xFF,0xF0,0x10, +0x07,0xFF,0xFF,0xFC,0x00,0x3F,0xFF,0xFF,0xF8,0x00, +0xF8,0x00,0x03,0xE0,0x90,0xF8,0x00,0x00,0xF8,0x40, +0xF8,0x00,0x00,0x3E,0x07,0xE0,0x00,0x00,0xFC,0x83, +0xE0,0x00,0x00,0x3E,0x43,0xE0,0x00,0x00,0x0F,0x9F, +0x80,0x00,0x00,0x3F,0x7C,0x00,0x00,0x00,0x7C,0x0E, +0xD0,0xA0,0x25,0x7F,0xFF,0xF0,0x01,0xFF,0xFF,0xF8, +0x07,0xFF,0xFF,0xF0,0x1F,0xFF,0xFF,0xE0,0x7F,0xFF, +0xFF,0xC1,0xF0,0x00,0x7F,0x87,0xC0,0x00,0x7E,0x1F, +0x00,0x00,0xFC,0xBF,0x80,0x00,0x3E,0x3E,0x00,0x00, +0xF0,0xF8,0x00,0x07,0xC3,0xE0,0x00,0x3F,0x0F,0x80, +0x03,0xF8,0x3F,0xFF,0xFF,0xC1,0x1F,0xFF,0xFF,0xC0, +0x7F,0xFF,0xFF,0xC1,0xFF,0xFF,0xFF,0x87,0xC0,0x00, +0xFF,0x1F,0x00,0x00,0xFE,0x7C,0x00,0x01,0xF9,0xF0, +0x00,0x03,0xFB,0xF8,0x00,0x00,0xFB,0xE0,0x00,0x07, +0xEF,0x80,0x00,0x1F,0x3E,0x00,0x00,0xFC,0xF8,0x00, +0x0F,0xE3,0xFF,0xFF,0xFF,0x8F,0xFF,0xFF,0xFC,0x3F, +0xFF,0xFF,0xE0,0xFF,0xFF,0xFE,0x03,0xFF,0xFF,0xC0, +0x00,0x11,0x54,0x7F,0xE8,0x00,0x01,0xFE,0x00,0x00, +0x01,0xFF,0xF8,0x00,0x00,0xFF,0xFF,0xC0,0x00,0x7F, +0xFF,0xFC,0x00,0x1F,0xFF,0xFF,0xC0,0x07,0xFC,0x07, +0xFC,0x01,0xFC,0x00,0x3F,0xC0,0x7F,0x00,0x01,0xF8, +0x0F,0xC0,0x00,0x1F,0x83,0xF0,0x00,0x03,0xF0,0x7C, +0x00,0x00,0x3E,0x1F,0x80,0x00,0x07,0xE3,0xE0,0x00, +0x00,0x71,0x0F,0x80,0x00,0x00,0x03,0xF0,0x00,0x00, +0x00,0xDF,0x80,0x00,0x00,0x02,0x7E,0x00,0x00,0x00, +0x03,0xE0,0x00,0x00,0x00,0x7C,0x00,0x00,0x06,0x0F, +0x80,0x00,0x00,0xF9,0xF0,0x00,0x00,0x3F,0x1F,0x00, +0x00,0x07,0xC3,0xE0,0x00,0x01,0xF8,0x7E,0x00,0x00, +0x3F,0x07,0xE0,0x00,0x0F,0xC0,0xFE,0x00,0x03,0xF8, +0x0F,0xF0,0x01,0xFE,0x00,0xFF,0x80,0xFF,0x80,0x0F, +0xFF,0xFF,0xE0,0x00,0xFF,0xFF,0xF8,0x00,0x0F,0xFF, +0xFE,0x00,0x00,0x7F,0xFF,0x00,0x00,0x01,0xFF,0x00, +0x00,0x10,0x50,0xA0,0x28,0x7F,0xFF,0xF8,0x00,0x3F, +0xFF,0xFF,0x80,0x1F,0xFF,0xFF,0xF0,0x0F,0xFF,0xFF, +0xFC,0x07,0xFF,0xFF,0xFF,0x03,0xE0,0x00,0x7F,0xC1, +0xF0,0x00,0x0F,0xF0,0xF8,0x00,0x01,0xF8,0x8F,0x80, +0x00,0x0F,0xC7,0xC0,0x00,0x03,0xF4,0xFC,0x00,0x00, +0x1F,0x6F,0xC0,0x00,0x00,0xFD,0x7C,0x00,0x00,0x0F, +0xBE,0x00,0x00,0x0F,0xE3,0xE0,0x00,0x00,0xF9,0xF0, +0x00,0x00,0xFC,0xF8,0x00,0x00,0x7C,0x8F,0x80,0x00, +0x0F,0xC7,0xC0,0x00,0x0F,0xC3,0xE0,0x00,0x1F,0xC1, +0xF0,0x00,0x3F,0xE0,0xFF,0xFF,0xFF,0xE0,0x7F,0xFF, +0xFF,0xE0,0x3F,0xFF,0xFF,0xE0,0x1F,0xFF,0xFF,0xC0, +0x0F,0xFF,0xFE,0x00,0x00,0x0E,0xD0,0xA0,0x25,0xBF, +0xFF,0xFF,0xFF,0x6F,0xC0,0x00,0x00,0x2F,0xE0,0x00, +0x00,0x17,0xFF,0xFF,0xFF,0x8D,0xF8,0x00,0x00,0x06, +0x7C,0x00,0x00,0x02,0xFF,0xFF,0xFF,0xFE,0x0D,0x50, +0xA0,0x22,0xBF,0xFF,0xFF,0xFF,0x7E,0x00,0x00,0x0B, +0xF8,0x00,0x00,0x2F,0xFF,0xFF,0xF8,0xDF,0x80,0x00, +0x03,0x7E,0x00,0x00,0x0A,0xF8,0x00,0x00,0x00,0x12, +0xD4,0x7F,0xEC,0x00,0x00,0xFF,0xC0,0x00,0x00,0x1F, +0xFF,0xE0,0x00,0x03,0xFF,0xFF,0xE0,0x00,0x1F,0xFF, +0xFF,0xC0,0x00,0xFF,0xFF,0xFF,0x80,0x07,0xFE,0x01, +0xFF,0x00,0x3F,0xC0,0x01,0xFE,0x01,0xFC,0x00,0x01, +0xFC,0x0F,0xE0,0x00,0x03,0xF0,0x3F,0x00,0x00,0x07, +0xC1,0xF8,0x00,0x00,0x1F,0x87,0xC0,0x00,0x00,0x3E, +0x3F,0x00,0x00,0x00,0xF8,0xF8,0x00,0x00,0x01,0x08, +0x7C,0x00,0x00,0x00,0x05,0xFC,0x00,0x00,0x00,0x02, +0xFE,0x00,0x03,0xFF,0xFF,0x2F,0x80,0x00,0x00,0x1F, +0x3F,0x00,0x00,0x00,0x7C,0x7C,0x00,0x00,0x01,0xF1, +0xF8,0x00,0x00,0x07,0xC3,0xF0,0x00,0x00,0x1F,0x0F, +0xE0,0x00,0x00,0xFC,0x1F,0xC0,0x00,0x07,0xF0,0x3F, +0xC0,0x00,0x7F,0xC0,0x7F,0xE0,0x1F,0xFE,0x00,0xFF, +0xFF,0xFF,0xF0,0x01,0xFF,0xFF,0xFF,0x00,0x01,0xFF, +0xFF,0xF0,0x00,0x01,0xFF,0xFF,0x00,0x00,0x00,0x7F, +0xC0,0x00,0x0F,0x50,0xA0,0x28,0xDF,0x80,0x00,0x07, +0xF7,0xE0,0x00,0x01,0xF8,0xF8,0x00,0x00,0x7E,0xFF, +0xFF,0xFF,0xFF,0xDF,0x80,0x00,0x07,0xF7,0xE0,0x00, +0x01,0xFB,0xF8,0x00,0x00,0x7C,0x02,0xD0,0xA0,0x0F, +0xDF,0xEF,0xF7,0xFB,0xFD,0xFD,0xFC,0x0A,0xD2,0x5F, +0xDC,0xD0,0x00,0x0F,0xE8,0x00,0x07,0xF4,0x00,0x03, +0xFA,0x00,0x01,0xF3,0xC0,0x07,0xE7,0xE0,0x03,0xEF, +0xC0,0x0F,0xBF,0x00,0x7C,0x7E,0x03,0xF1,0xFC,0x1F, +0xD0,0x7F,0xFF,0xC0,0xFF,0xFE,0x01,0xFF,0xE0,0x00, +0xFE,0x00,0x10,0xD0,0xA0,0x25,0x7C,0x00,0x00,0x3F, +0x1F,0x00,0x00,0x1F,0x87,0xC0,0x00,0x0F,0xC1,0xF0, +0x00,0x07,0xE0,0x7C,0x00,0x03,0xF0,0x1F,0x00,0x03, +0xF8,0x07,0xC0,0x01,0xFC,0x01,0xF0,0x00,0xFE,0x00, +0x7C,0x00,0x7F,0x00,0x1F,0x00,0x3F,0x80,0x07,0xC0, +0x1F,0xC0,0x01,0xF0,0x0F,0xE0,0x00,0x7C,0x07,0xF0, +0x00,0x1F,0x03,0xF8,0x00,0x07,0xC1,0xFC,0x00,0x01, +0xF0,0xFE,0x00,0x00,0x7C,0x7F,0x00,0x00,0x1F,0x3F, +0xE0,0x00,0x07,0xDF,0xF8,0x00,0x01,0xFF,0xFF,0x00, +0x00,0x7F,0xF7,0xE0,0x00,0x1F,0xF8,0xFC,0x00,0x07, +0xFC,0x1F,0x80,0x01,0xFE,0x07,0xE0,0x00,0x7F,0x00, +0xFC,0x00,0x1F,0x80,0x1F,0x80,0x08,0xF8,0x00,0x7E, +0x00,0x3E,0x00,0x0F,0xC0,0x0F,0x80,0x01,0xF8,0x04, +0x7C,0x00,0x07,0xE0,0x1F,0x00,0x00,0xFC,0x07,0xC0, +0x00,0x1F,0x81,0xF0,0x00,0x03,0xF0,0x8F,0x80,0x00, +0x0F,0xC3,0xE0,0x00,0x01,0xF8,0xF8,0x00,0x00,0x3F, +0x3E,0x00,0x00,0x07,0xE0,0x0C,0x50,0xA0,0x1F,0xDF, +0x80,0x00,0x0D,0xF8,0x00,0x00,0xDF,0x80,0x00,0x0D, +0xF8,0x00,0x00,0xDF,0x80,0x00,0x0B,0xFF,0xFF,0xFF, +0x12,0xD0,0xA0,0x2F,0x9F,0xF8,0x00,0x00,0xFF,0xCF, +0xFE,0x00,0x00,0xFF,0xDF,0xFC,0x00,0x03,0xFF,0x9F, +0xBE,0x00,0x03,0xEF,0xCF,0xCF,0x80,0x03,0xE7,0xDF, +0x3F,0x00,0x0F,0x9F,0x9F,0x8F,0x80,0x0F,0x8F,0xCF, +0xC3,0xE0,0x0F,0x87,0xDF,0x0F,0xC0,0x7C,0x1F,0x9F, +0x83,0xE0,0x3E,0x0F,0xCF,0xC0,0xF8,0x3E,0x07,0xDF, +0x03,0xF1,0xF0,0x1F,0x9F,0x80,0xF8,0xF8,0x0F,0xCF, +0xC0,0x3E,0xF8,0x07,0xDF,0x00,0xFF,0xC0,0x1F,0x9F, +0x80,0x3F,0xE0,0x0F,0xC7,0xC0,0x0F,0xE0,0x07,0xC0, +0x0F,0x50,0xA0,0x28,0x8F,0xC0,0x00,0x07,0xDF,0xC0, +0x00,0x0F,0xC7,0xF8,0x00,0x03,0xF1,0xFF,0x00,0x00, +0xFB,0xFF,0x00,0x01,0xF7,0xFF,0x00,0x03,0xEF,0xBE, +0x00,0x07,0xDF,0x7E,0x00,0x0F,0xC7,0xCF,0xC0,0x03, +0xEF,0x8F,0xC0,0x07,0xDF,0x0F,0x80,0x0F,0xBE,0x1F, +0x80,0x1F,0x7C,0x1F,0x80,0x3E,0xF8,0x1F,0x00,0x7D, +0xF0,0x3F,0x00,0xFC,0x7C,0x07,0xE0,0x3E,0xF8,0x07, +0xE0,0x7D,0xF0,0x07,0xC0,0xFB,0xE0,0x0F,0xC1,0xF7, +0xC0,0x0F,0xC3,0xEF,0x80,0x0F,0x87,0xDF,0x00,0x1F, +0x8F,0xC7,0xC0,0x03,0xF3,0xEF,0x80,0x03,0xF7,0xDF, +0x00,0x03,0xEF,0xBE,0x00,0x07,0xFF,0x7C,0x00,0x07, +0xFF,0x1F,0x00,0x00,0xFF,0xC7,0xC0,0x00,0x1F,0xEF, +0x80,0x00,0x1F,0xE3,0xE0,0x00,0x03,0xF0,0x13,0x54, +0x7F,0xEC,0x00,0x01,0xFF,0x00,0x00,0x00,0x1F,0xFF, +0xE0,0x00,0x00,0xFF,0xFF,0xF0,0x00,0x03,0xFF,0xFF, +0xF0,0x00,0x0F,0xFF,0xFF,0xF0,0x00,0x3F,0xE0,0x1F, +0xF0,0x00,0xFF,0x00,0x0F,0xF0,0x03,0xF8,0x00,0x07, +0xF0,0x0F,0xE0,0x00,0x07,0xF0,0x1F,0x00,0x00,0x07, +0xE0,0x7E,0x00,0x00,0x07,0xE0,0xF8,0x00,0x00,0x07, +0xC3,0xF0,0x00,0x00,0x0F,0xD2,0xF8,0x00,0x00,0x01, +0xF6,0xFC,0x00,0x00,0x00,0x3F,0x3F,0x00,0x00,0x00, +0x0F,0xCB,0xE0,0x00,0x00,0x07,0xC7,0xE0,0x00,0x00, +0x1F,0x87,0xC0,0x00,0x00,0x3E,0x0F,0xC0,0x00,0x00, +0xFC,0x0F,0xC0,0x00,0x03,0xF0,0x1F,0xC0,0x00,0x0F, +0xE0,0x1F,0xC0,0x00,0x3F,0x80,0x1F,0xC0,0x00,0xFE, +0x00,0x1F,0xF0,0x0F,0xFC,0x00,0x1F,0xFF,0xFF,0xE0, +0x00,0x1F,0xFF,0xFF,0x80,0x00,0x1F,0xFF,0xFE,0x00, +0x00,0x0F,0xFF,0xF0,0x00,0x00,0x03,0xFE,0x00,0x00, +0x0E,0xD0,0xA0,0x25,0x7F,0xFF,0xFC,0x01,0xFF,0xFF, +0xFC,0x07,0xFF,0xFF,0xFC,0x1F,0xFF,0xFF,0xF8,0x7F, +0xFF,0xFF,0xF1,0xF0,0x00,0x1F,0xC7,0xC0,0x00,0x1F, +0x9F,0x00,0x00,0x3E,0x7C,0x00,0x00,0xFF,0x3E,0x00, +0x00,0x3E,0xF8,0x00,0x01,0xFB,0xE0,0x00,0x07,0xCF, +0x80,0x00,0x7F,0x3E,0x00,0x07,0xF8,0xFF,0xFF,0xFF, +0xE3,0xFF,0xFF,0xFF,0x0F,0xFF,0xFF,0xF8,0x3F,0xFF, +0xFF,0x80,0xFF,0xFF,0xF0,0x06,0xFC,0x00,0x00,0x03, +0x7E,0x00,0x00,0x01,0x1F,0x00,0x00,0x00,0x13,0x58, +0x7F,0x6C,0x00,0x01,0xFF,0x00,0x00,0x00,0x1F,0xFF, +0xC0,0x00,0x00,0xFF,0xFF,0xE0,0x00,0x03,0xFF,0xFF, +0xE0,0x00,0x1F,0xFF,0xFF,0xF0,0x00,0x7F,0xE0,0x3F, +0xF0,0x01,0xFE,0x00,0x0F,0xF0,0x03,0xF8,0x00,0x0F, +0xE0,0x0F,0xC0,0x00,0x0F,0xE0,0x1F,0x00,0x00,0x0F, +0xC0,0x7E,0x00,0x00,0x0F,0xC0,0xF8,0x00,0x00,0x0F, +0x83,0xF0,0x00,0x00,0x1F,0x92,0xF8,0x00,0x00,0x03, +0xE6,0xFC,0x00,0x00,0x00,0x7D,0x3F,0x00,0x00,0x00, +0x1F,0x4B,0xE0,0x00,0x00,0x0F,0x87,0xE0,0x00,0x00, +0x3F,0x07,0xC0,0x01,0x80,0x7C,0x0F,0xC0,0x07,0xC1, +0xF8,0x0F,0x80,0x0F,0xE7,0xE0,0x1F,0x80,0x1F,0xEF, +0xC0,0x1F,0xC0,0x0F,0xFF,0x00,0x1F,0xC0,0x07,0xFC, +0x00,0x3F,0xF0,0x1F,0xF8,0x00,0x3F,0xFF,0xFF,0xF8, +0x00,0x1F,0xFF,0xFF,0xF8,0x00,0x1F,0xFF,0xFF,0xFC, +0x00,0x0F,0xFF,0xE3,0xFC,0x00,0x03,0xFE,0x01,0xFC, +0x00,0x00,0x00,0x01,0xF0,0x00,0x00,0x00,0x00,0xE0, +0x10,0x50,0xA0,0x28,0x7F,0xFF,0xFE,0x00,0x3F,0xFF, +0xFF,0xE0,0x1F,0xFF,0xFF,0xF8,0x0F,0xFF,0xFF,0xFE, +0x07,0xFF,0xFF,0xFF,0x83,0xE0,0x00,0x1F,0xE1,0xF0, +0x00,0x03,0xF0,0xF8,0x00,0x00,0xF8,0x7C,0x00,0x00, +0x7E,0x57,0xC0,0x00,0x03,0xE4,0x7C,0x00,0x00,0x7E, +0x3E,0x00,0x00,0x7E,0x1F,0x00,0x01,0xFF,0x0F,0xFF, +0xFF,0xFF,0x07,0xFF,0xFF,0xFF,0x03,0xFF,0xFF,0xFF, +0x01,0xFF,0xFF,0xFE,0x00,0xFF,0xFF,0xFC,0x00,0x7C, +0x01,0xF8,0x00,0x3E,0x00,0x3F,0x00,0x1F,0x00,0x0F, +0xC0,0x0F,0x80,0x03,0xE0,0x07,0xC0,0x01,0xF8,0x03, +0xE0,0x00,0x7E,0x02,0x3E,0x00,0x03,0xF0,0x1F,0x00, +0x00,0xFC,0x0F,0x80,0x00,0x3E,0x07,0xC0,0x00,0x1F, +0x83,0xE0,0x00,0x07,0xE1,0xF0,0x00,0x01,0xF0,0xF8, +0x00,0x00,0xFC,0x7C,0x00,0x00,0x3E,0x3E,0x00,0x00, +0x1F,0x9F,0x00,0x00,0x07,0xEF,0x80,0x00,0x01,0xF0, +0x0F,0xD4,0x7F,0xE5,0x00,0x0F,0xF8,0x00,0x00,0x7F, +0xFF,0x00,0x01,0xFF,0xFF,0xC0,0x03,0xFF,0xFF,0xE0, +0x07,0xFF,0xFF,0xF0,0x07,0xF8,0x07,0xF8,0x0F,0xC0, +0x01,0xFC,0x0F,0x80,0x00,0xFC,0x1F,0x80,0x00,0x7C, +0x1F,0x00,0x00,0x7E,0x83,0xE0,0x00,0x07,0xC3,0xE0, +0x00,0x00,0x03,0xF0,0x00,0x00,0x01,0xF0,0x00,0x00, +0x01,0xFC,0x00,0x00,0x01,0xFF,0x80,0x00,0x00,0xFF, +0xF0,0x00,0x00,0x7F,0xFF,0x00,0x00,0x1F,0xFF,0xE0, +0x00,0x0F,0xFF,0xF8,0x00,0x01,0xFF,0xFE,0x00,0x00, +0x3F,0xFF,0x00,0x00,0x03,0xFF,0x80,0x00,0x00,0x3F, +0xC0,0x00,0x00,0x1F,0xC0,0x00,0x00,0x07,0xC0,0x00, +0x00,0x07,0xF3,0xF0,0x00,0x00,0x7D,0xF8,0x00,0x00, +0x7C,0xF8,0x00,0x00,0x7C,0xFC,0x00,0x00,0xF8,0x7E, +0x00,0x01,0xF8,0x7F,0x80,0x03,0xF8,0x3F,0xE0,0x1F, +0xF0,0x1F,0xFF,0xFF,0xE0,0x0F,0xFF,0xFF,0xC0,0x07, +0xFF,0xFF,0x80,0x01,0xFF,0xFE,0x00,0x00,0x3F,0xF0, +0x00,0x0F,0xD0,0x40,0x23,0xBF,0xFF,0xFF,0xFF,0xFA, +0x00,0x0F,0x80,0x03,0x40,0x01,0xF0,0x00,0x68,0x00, +0x3E,0x00,0x0D,0x00,0x07,0xC0,0x01,0xA0,0x00,0xF8, +0x00,0x00,0x0F,0x52,0xBF,0xE8,0xDF,0x80,0x00,0x07, +0xF7,0xE0,0x00,0x01,0xFD,0xF8,0x00,0x00,0x7F,0x7E, +0x00,0x00,0x1F,0x7C,0x00,0x00,0x3E,0xFC,0x00,0x00, +0xFE,0x1F,0x00,0x00,0x3E,0x3F,0x00,0x00,0xFC,0x7F, +0x00,0x03,0xF0,0x7F,0x00,0x0F,0xE0,0x7F,0x80,0x7F, +0x80,0xFF,0xFF,0xFF,0x00,0xFF,0xFF,0xFC,0x00,0xFF, +0xFF,0xE0,0x00,0x7F,0xFF,0x80,0x00,0x1F,0xF8,0x00, +0x12,0xD0,0x00,0x25,0x7C,0x00,0x00,0x00,0x7D,0xF8, +0x00,0x00,0x03,0xF8,0x7C,0x00,0x00,0x01,0xF4,0x1F, +0x00,0x00,0x01,0xF0,0x7E,0x00,0x00,0x0F,0xC8,0x1F, +0x00,0x00,0x07,0xC4,0x87,0xC0,0x00,0x07,0xC2,0x01, +0xF0,0x00,0x07,0xC1,0x20,0x7C,0x00,0x07,0xC0,0x80, +0x1F,0x00,0x07,0xC0,0x48,0x07,0xC0,0x07,0xC0,0x20, +0x01,0xF0,0x07,0xC0,0x00,0x03,0xC0,0x3E,0x00,0x00, +0x0F,0x80,0xF8,0x00,0x00,0x1E,0x03,0xC0,0x04,0x00, +0x0F,0x83,0xE0,0x00,0x00,0x1E,0x0F,0x00,0x00,0x00, +0x7C,0x7C,0x00,0x00,0x00,0xF1,0xE0,0x00,0x80,0x00, +0x7D,0xF0,0x00,0x00,0x00,0xF7,0x80,0x00,0x00,0x03, +0xFE,0x00,0x04,0x80,0x00,0xFE,0x00,0x00,0x00,0x01, +0xF0,0x00,0x00,0x1B,0xD0,0x20,0x38,0x7C,0x00,0x00, +0x7F,0x00,0x00,0x1F,0x7C,0x00,0x00,0xFF,0x80,0x00, +0x3F,0x87,0xC0,0x00,0x1F,0xF0,0x00,0x07,0xC7,0xC0, +0x00,0x3F,0xF8,0x00,0x07,0xC7,0xC0,0x00,0x3E,0xF8, +0x00,0x07,0xD0,0x7C,0x00,0x07,0xDF,0x00,0x01,0xF0, +0x7C,0x00,0x0F,0x8F,0x80,0x01,0xF0,0x3C,0x00,0x0F, +0x8F,0x80,0x01,0xE0,0x3E,0x00,0x0F,0x8F,0x80,0x03, +0xE0,0x3E,0x00,0x1F,0x8F,0xC0,0x03,0xE0,0x3E,0x00, +0x1F,0x07,0xC0,0x03,0xE0,0x1E,0x00,0x1F,0x07,0xC0, +0x03,0xC0,0x1F,0x00,0x3F,0x07,0xE0,0x07,0xC2,0x03, +0xE0,0x07,0xC0,0x7C,0x00,0xF8,0x01,0xE0,0x07,0xC0, +0x7C,0x00,0xF0,0x40,0x3E,0x01,0xF0,0x07,0xC0,0x3E, +0x00,0x1E,0x01,0xF0,0x07,0xC0,0x3C,0x00,0x1E,0x03, +0xF0,0x07,0xE0,0x3C,0x08,0x03,0xE0,0x7C,0x00,0x7C, +0x0F,0x80,0x01,0xE0,0xFC,0x00,0x7C,0x0F,0x00,0x01, +0xE0,0xF8,0x00,0x3E,0x0F,0x01,0x00,0x3E,0x1F,0x00, +0x07,0xC3,0xE0,0x20,0x03,0xC7,0xC0,0x00,0x7C,0x78, +0x00,0x03,0xE7,0xC0,0x00,0x7C,0xF8,0x00,0x03,0xEF, +0xC0,0x00,0x7E,0xF8,0x04,0x00,0x3D,0xF0,0x00,0x07, +0xDE,0x00,0x00,0x3F,0xF0,0x00,0x07,0xFE,0x00,0x90, +0x03,0xFC,0x00,0x00,0x7F,0x80,0x00,0x03,0xF8,0x00, +0x00,0x3F,0x80,0x00,0x01,0xF8,0x00,0x00,0x3F,0x00, +0x00,0x12,0xD0,0x00,0x25,0x1F,0x80,0x00,0x03,0xF0, +0x3F,0x00,0x00,0x1F,0x80,0x7E,0x00,0x00,0xFC,0x00, +0xF8,0x00,0x07,0xE0,0x03,0xF0,0x00,0x1F,0x80,0x07, +0xE0,0x00,0xFC,0x08,0x01,0xF8,0x00,0xFC,0x00,0x03, +0xF0,0x07,0xE0,0x00,0x07,0xE0,0x3F,0x00,0x40,0x01, +0xF8,0x3F,0x00,0x00,0x03,0xF1,0xF8,0x00,0x00,0x07, +0xEF,0xC0,0x00,0x00,0x0F,0xFF,0x00,0x00,0x00,0x3F, +0xF8,0x00,0x00,0x00,0x7F,0xC0,0x00,0x90,0x00,0x1F, +0xC0,0x00,0x00,0x00,0xFF,0x80,0x01,0x00,0x00,0xFF, +0xE0,0x00,0x00,0x07,0xEF,0xC0,0x00,0x00,0x3F,0x1F, +0x80,0x00,0x01,0xFC,0x3E,0x00,0x00,0x07,0xE0,0xFC, +0x00,0x00,0x3F,0x01,0xF8,0x02,0x00,0x3F,0x00,0x7E, +0x00,0x01,0xF8,0x00,0xFC,0x00,0x0F,0xC0,0x01,0xF8, +0x10,0x0F,0xC0,0x00,0x7E,0x00,0x7E,0x00,0x00,0xFC, +0x03,0xF0,0x00,0x01,0xF8,0x0F,0xC0,0x00,0x03,0xE0, +0x7E,0x00,0x00,0x0F,0xC3,0xF0,0x00,0x00,0x1F,0x9F, +0x80,0x00,0x00,0x3F,0x11,0xD0,0x20,0x25,0x7E,0x00, +0x00,0x03,0xF3,0xF0,0x00,0x00,0x7E,0x1F,0x00,0x00, +0x07,0xC1,0xF8,0x00,0x00,0xFC,0x0F,0xC0,0x00,0x1F, +0x80,0x7C,0x00,0x01,0xF0,0x07,0xE0,0x00,0x3F,0x00, +0x3F,0x00,0x07,0xE0,0x01,0xF0,0x00,0x7C,0x00,0x1F, +0x80,0x0F,0xC0,0x80,0x1F,0x80,0x3F,0x00,0x00,0xFC, +0x07,0xE0,0x10,0x00,0xFC,0x1F,0x80,0x00,0x07,0xE3, +0xF0,0x00,0x00,0x3E,0x7E,0x00,0x00,0x03,0xF7,0xE0, +0x00,0x00,0x1F,0xFC,0x00,0x20,0x00,0x1F,0xF0,0x00, +0x00,0x00,0xFE,0x00,0x06,0x80,0x00,0xF8,0x00,0x0D, +0x00,0x01,0xF0,0x00,0x14,0x00,0x03,0xE0,0x00,0x00, +0x0F,0xD0,0x20,0x22,0xB1,0xFF,0xFF,0xFF,0xC0,0x00, +0x00,0x1F,0xC0,0x00,0x00,0x1F,0x80,0x00,0x00,0x3F, +0x00,0x00,0x00,0x7E,0x00,0x00,0x00,0xFC,0x00,0x00, +0x01,0xFC,0x00,0x00,0x01,0xF8,0x00,0x00,0x03,0xF0, +0x00,0x00,0x07,0xE0,0x00,0x00,0x0F,0xC0,0x00,0x00, +0x1F,0xC0,0x00,0x00,0x1F,0x80,0x00,0x00,0x3F,0x00, +0x00,0x00,0x7E,0x00,0x00,0x00,0xFC,0x00,0x00,0x01, +0xFC,0x00,0x00,0x01,0xF8,0x00,0x00,0x03,0xF0,0x00, +0x00,0x07,0xE0,0x00,0x00,0x0F,0xC0,0x00,0x00,0x1F, +0xC0,0x00,0x00,0x1F,0x80,0x00,0x00,0x3F,0x00,0x00, +0x00,0x7E,0x00,0x00,0x00,0xFC,0x00,0x00,0x01,0xFC, +0x00,0x00,0x01,0xF8,0x00,0x00,0x03,0xF0,0x00,0x00, +0x07,0xE0,0x00,0x00,0x0F,0xC0,0x00,0x00,0x17,0xFF, +0xFF,0xFF,0xFC,0x05,0xE6,0x7D,0x50,0xBF,0xFF,0xBF, +0x03,0x7E,0x06,0xFC,0x0D,0xF8,0x1B,0xF0,0x33,0xE0, +0x5F,0xFF,0x08,0x50,0x20,0x10,0x8F,0x00,0x09,0x78, +0x00,0x93,0xC0,0x01,0xF0,0x04,0x8F,0x00,0x48,0x78, +0x04,0x83,0xC0,0x01,0xF0,0x24,0x0F,0x02,0x40,0x78, +0x24,0x03,0xC0,0x01,0xF1,0x20,0x0F,0x12,0x00,0x79, +0x20,0x03,0xC0,0x01,0xF0,0x00,0x78,0x05,0xE6,0x5D, +0x50,0xBF,0xFF,0xA0,0x7F,0x40,0xFE,0x81,0xFD,0x03, +0xFA,0x07,0xF0,0x0F,0xDF,0xFF,0x0B,0x2C,0x24,0xD8, +0x00,0x3C,0x01,0x20,0x1F,0x80,0x40,0x0F,0xF0,0x12, +0x07,0x9E,0x04,0x03,0xC3,0xC0,0x0F,0x87,0xC0,0x1E, +0x07,0x84,0x0F,0x81,0xF0,0x1E,0x01,0xE2,0x0F,0x80, +0x7C,0x97,0xC0,0x0F,0x9F,0x00,0x0F,0x80,0x10,0x0B, +0xFD,0x5F,0xBF,0xFF,0xFF,0xFF,0xF0,0x05,0x10,0x48, +0x13,0x7E,0x07,0xE0,0x7C,0x40,0xF8,0x0F,0x80,0xF0, +0x0F,0x0D,0xBC,0x40,0x1F,0x00,0x3F,0xF0,0x00,0x1F, +0xFF,0xC0,0x03,0xFF,0xFF,0x00,0x7F,0xFF,0xF0,0x0F, +0xFF,0xFF,0x81,0xFE,0x03,0xF8,0x1F,0x80,0x0F,0xC8, +0x7E,0x00,0x0F,0x81,0xC0,0x00,0xF8,0x00,0x00,0x0F, +0x80,0x00,0x03,0xF8,0x00,0x07,0xFF,0x80,0x1F,0xFF, +0xF8,0x0F,0xFF,0xFF,0x81,0xFF,0xFF,0xF8,0x3F,0xFF, +0xCF,0x87,0xFF,0x00,0xF8,0x7E,0x00,0x0F,0x8F,0xC0, +0x00,0xF9,0x1F,0x00,0x03,0xF1,0xF0,0x00,0x7F,0x1F, +0x80,0x0F,0xF1,0xFE,0x07,0xFF,0x0F,0xFF,0xFF,0xF0, +0xFF,0xFF,0xDF,0x87,0xFF,0xF9,0xF8,0x1F,0xFF,0x0F, +0x80,0x7F,0x80,0x7C,0x0C,0xD0,0x80,0x1F,0xDF,0x80, +0x00,0x04,0xFC,0x00,0x00,0x1F,0x07,0xE0,0x07,0xC7, +0xFF,0x01,0xF3,0xFF,0xE0,0x7D,0xFF,0xFC,0x1F,0xFF, +0xFF,0x87,0xFE,0x0F,0xF1,0xFE,0x00,0xFC,0x7F,0x00, +0x1F,0x9F,0xC0,0x03,0xE7,0xE0,0x00,0xF9,0xF8,0x00, +0x3F,0xDF,0x80,0x00,0xFB,0xE0,0x00,0x3E,0xF8,0x00, +0x1F,0xBF,0x00,0x07,0xCF,0xC0,0x03,0xF3,0xF8,0x00, +0xFC,0xFF,0x00,0x7E,0x3F,0xF0,0x7F,0x8F,0xFF,0xFF, +0xC3,0xEF,0xFF,0xE0,0xF9,0xFF,0xF0,0x3E,0x3F,0xF0, +0x0F,0x83,0xF0,0x00,0x0D,0x3C,0x40,0x1C,0x00,0x3F, +0xC0,0x00,0x1F,0xFF,0x00,0x0F,0xFF,0xF0,0x03,0xFF, +0xFF,0x00,0xFF,0xFF,0xF0,0x3F,0xC0,0xFF,0x07,0xE0, +0x07,0xE1,0xF8,0x00,0x7E,0x3E,0x00,0x0F,0xC7,0xC0, +0x00,0xE1,0xF8,0x00,0x00,0x6F,0xC0,0x00,0x00,0xF8, +0x00,0x00,0x1F,0x80,0x00,0xE1,0xF0,0x00,0x1F,0x3E, +0x00,0x07,0xE7,0xE0,0x01,0xF8,0x7E,0x00,0x7F,0x0F, +0xF0,0x1F,0xC0,0xFF,0xFF,0xF8,0x0F,0xFF,0xFE,0x00, +0xFF,0xFF,0x80,0x07,0xFF,0xC0,0x00,0x1F,0xC0,0x00, +0x0C,0xD0,0x40,0x1F,0xD0,0x00,0x00,0xFC,0x80,0x00, +0x07,0xC0,0x0F,0xC1,0xF0,0x1F,0xFC,0x7C,0x0F,0xFF, +0x9F,0x07,0xFF,0xF7,0xC3,0xFF,0xFF,0xF1,0xFE,0x0F, +0xFC,0x7E,0x00,0xFF,0x3F,0x00,0x1F,0xCF,0x80,0x07, +0xF3,0xE0,0x00,0xFD,0xF8,0x00,0x3F,0xDF,0x80,0x00, +0xFB,0xE0,0x00,0x3E,0xFC,0x00,0x1F,0xC3,0xE0,0x00, +0xFC,0xFC,0x00,0x7F,0x1F,0x80,0x3F,0xC7,0xF8,0x3F, +0xF0,0xFF,0xFF,0xFC,0x1F,0xFF,0xDF,0x03,0xFF,0xE7, +0xC0,0x3F,0xF1,0xF0,0x03,0xF0,0x7C,0x0D,0xBC,0x40, +0x1F,0x00,0x1F,0xC0,0x00,0x0F,0xFF,0x80,0x03,0xFF, +0xFE,0x00,0x7F,0xFF,0xF0,0x0F,0xFF,0xFF,0x80,0xFE, +0x03,0xFC,0x1F,0x80,0x0F,0xC3,0xF0,0x00,0x7E,0x3E, +0x00,0x03,0xE3,0xC0,0x00,0x1E,0x7C,0x00,0x01,0xFB, +0xFF,0xFF,0xFF,0xF3,0xF0,0x00,0x00,0x1F,0x80,0x00, +0x00,0xF8,0x00,0x06,0x0F,0xC0,0x00,0xFC,0xFE,0x00, +0x1F,0x87,0xF0,0x03,0xF8,0x7F,0xC0,0xFF,0x03,0xFF, +0xFF,0xF0,0x1F,0xFF,0xFE,0x00,0xFF,0xFF,0xC0,0x03, +0xFF,0xF0,0x00,0x07,0xF8,0x00,0x08,0xD0,0x00,0x10, +0x00,0x3F,0x80,0x3F,0xF8,0x07,0xFF,0x03,0xFF,0xC0, +0xFC,0x05,0x87,0xC0,0x2F,0xFF,0xF9,0xA1,0xF0,0x0D, +0x0F,0x80,0x68,0x7C,0x02,0x43,0xE0,0x00,0x0C,0xD2, +0x5D,0x5F,0x00,0x7F,0x00,0x00,0x7F,0xF1,0xF0,0x3F, +0xFF,0x7C,0x1F,0xFF,0xFF,0x0F,0xFF,0xFF,0xC7,0xF8, +0x3F,0xF1,0xF8,0x03,0xFC,0xFC,0x00,0x7F,0x3E,0x00, +0x1F,0xCF,0x80,0x03,0xF7,0xE0,0x00,0xFF,0x7E,0x00, +0x03,0xEF,0x80,0x00,0xFB,0xF0,0x00,0x7F,0x0F,0x80, +0x03,0xF3,0xF0,0x01,0xFC,0x7E,0x00,0xFF,0x1F,0xE0, +0xFF,0xC3,0xFF,0xFF,0xF0,0x7F,0xFF,0xFC,0x0F,0xFF, +0xDF,0x01,0xFF,0xC7,0xC0,0x0F,0xC1,0xF0,0x00,0x00, +0x7C,0xE0,0x00,0x1F,0x87,0xC0,0x01,0xF1,0xF8,0x00, +0xFC,0x3F,0x80,0xFE,0x0F,0xFF,0xFF,0x81,0xFF,0xFF, +0xC0,0x3F,0xFF,0xE0,0x07,0xFF,0xE0,0x00,0x3F,0xC0, +0x00,0x0B,0xD0,0x80,0x1F,0xDF,0x80,0x00,0x13,0xF0, +0x00,0x01,0xF0,0x7F,0x01,0xF1,0xFF,0xC1,0xF3,0xFF, +0xE1,0xF7,0xFF,0xF1,0xFF,0xFF,0xF9,0xFF,0x83,0xF9, +0xFE,0x01,0xFD,0xFC,0x00,0xFE,0x3F,0x00,0x0F,0xEF, +0xC0,0x01,0xFD,0xF8,0x00,0x3F,0x9F,0x00,0x07,0xC0, +0x02,0xD0,0x80,0x0D,0xBF,0xE0,0x37,0xFB,0xFD,0xFE, +0xFD,0xF0,0x05,0xE7,0xDD,0x4D,0xB0,0x3F,0x80,0x03, +0x40,0xFE,0x81,0xFD,0x03,0xFA,0x07,0xF0,0x0F,0x81, +0xFC,0x7F,0xE8,0xFF,0x8F,0xE0,0x0C,0x50,0x80,0x1D, +0xDF,0x80,0x00,0x0A,0xF8,0x00,0x00,0x7C,0x00,0x7E, +0x3E,0x00,0x7E,0x1F,0x00,0x7E,0x0F,0x80,0xFE,0x07, +0xC0,0xFE,0x03,0xE0,0xFE,0x01,0xF0,0xFE,0x00,0xF8, +0xFE,0x00,0x7C,0xFE,0x00,0x3E,0xFE,0x00,0x23,0xFF, +0xC0,0x02,0x3F,0xFE,0x00,0x1F,0xFF,0x80,0x0F,0xE7, +0xE0,0x07,0xE1,0xF0,0x03,0xE0,0xFC,0x01,0xF0,0x3F, +0x01,0x1F,0x01,0xF8,0x0F,0x80,0x7E,0x08,0xF8,0x03, +0xF0,0x7C,0x00,0xFC,0x47,0xC0,0x07,0xE3,0xE0,0x01, +0xF9,0xF0,0x00,0x7E,0x02,0xD0,0x60,0x0B,0xDF,0xEF, +0xF7,0xFB,0xFD,0xFD,0xFC,0x13,0xBC,0x80,0x2F,0x00, +0x1F,0x80,0x0F,0xC0,0x7C,0x7F,0xE0,0x3F,0xF8,0x7C, +0xFF,0xF0,0x7F,0xFC,0x7D,0xFF,0xF8,0xFF,0xFC,0x7D, +0xFF,0xFD,0xFF,0xFE,0x7F,0xC1,0xFF,0xE0,0xFE,0x7F, +0x80,0x7F,0xC0,0x3F,0x7F,0x00,0x7F,0x80,0x3F,0x8F, +0xC0,0x07,0xE0,0x03,0xFB,0xF0,0x00,0xF8,0x00,0x7F, +0x7E,0x00,0x1F,0x00,0x0F,0xE7,0xC0,0x03,0xE0,0x01, +0xF0,0x0B,0xBC,0x80,0x1F,0x00,0x1F,0xC0,0x7C,0x7F, +0xF0,0x7C,0xFF,0xF8,0x7D,0xFF,0xFC,0x7F,0xFF,0xFE, +0x7F,0xE0,0xFE,0x7F,0x80,0x7F,0x7F,0x00,0x3F,0x8F, +0xC0,0x03,0xFB,0xF0,0x00,0x7F,0x7E,0x00,0x0F,0xE7, +0xC0,0x01,0xF0,0x0D,0xBC,0x40,0x1F,0x00,0x1F,0xC0, +0x00,0x0F,0xFF,0x80,0x03,0xFF,0xFE,0x00,0x7F,0xFF, +0xF0,0x0F,0xFF,0xFF,0x81,0xFF,0x07,0xFC,0x1F,0xC0, +0x1F,0xC8,0x7E,0x00,0x0F,0xC7,0xC0,0x00,0x7C,0xFC, +0x00,0x07,0xFB,0xF0,0x00,0x07,0xDF,0x00,0x00,0x7D, +0xF8,0x00,0x0F,0xCF,0x80,0x00,0xFA,0x1F,0x80,0x03, +0xF0,0xFE,0x00,0xFE,0x0F,0xF8,0x3F,0xE0,0x7F,0xFF, +0xFC,0x03,0xFF,0xFF,0x80,0x1F,0xFF,0xF0,0x00,0x7F, +0xFC,0x00,0x01,0xFE,0x00,0x00,0x0C,0xD2,0x9D,0x5F, +0x00,0x1F,0xC0,0x1F,0x1F,0xFC,0x07,0xCF,0xFF,0x81, +0xF7,0xFF,0xF0,0x7D,0xFF,0xFE,0x1F,0xF8,0x3F,0xC7, +0xF8,0x03,0xF1,0xFC,0x00,0x7E,0x7F,0x00,0x0F,0x9F, +0x80,0x03,0xE7,0xE0,0x00,0xFF,0x7E,0x00,0x03,0xEF, +0x80,0x00,0xFC,0xFE,0x00,0x0F,0x9F,0xC0,0x07,0xE7, +0xF8,0x03,0xF1,0xFF,0x83,0xF8,0x7F,0xFF,0xFE,0x1F, +0x7F,0xFF,0x07,0xCF,0xFF,0x81,0xF1,0xFF,0x80,0x7C, +0x1F,0x80,0x37,0xE0,0x00,0x01,0x5F,0x00,0x00,0x00, +0x0C,0xD2,0x5D,0x5F,0x00,0x7F,0x00,0x00,0x7F,0xF1, +0xF0,0x3F,0xFE,0x7C,0x1F,0xFF,0xDF,0x0F,0xFF,0xF7, +0xC7,0xF8,0x3F,0xF1,0xF8,0x03,0xFC,0xFC,0x00,0x7F, +0x3E,0x00,0x1F,0xCF,0x80,0x03,0xF7,0xE0,0x00,0xFF, +0x7E,0x00,0x03,0xEF,0x80,0x00,0xFB,0xF0,0x00,0x7F, +0x0F,0x80,0x03,0xF3,0xF0,0x01,0xFC,0x7E,0x00,0xFF, +0x0F,0xE0,0xFF,0xC3,0xFF,0xFF,0xF0,0x7F,0xFF,0x7C, +0x0F,0xFF,0x9F,0x00,0xFF,0xC7,0xC0,0x0F,0xC1,0xFD, +0x00,0x00,0x0F,0xD0,0x00,0x00,0x7C,0x08,0x3C,0x80, +0x13,0x00,0x7C,0x3C,0x7F,0x9E,0x7F,0xEF,0x7F,0xE7, +0xFF,0xF3,0xFC,0x19,0xFC,0x01,0x3F,0x80,0x1B,0xF0, +0x01,0xBF,0x00,0x19,0xF0,0x00,0x0C,0x3C,0x40,0x1C, +0x00,0x7F,0x00,0x01,0xFF,0xF0,0x01,0xFF,0xFC,0x01, +0xFF,0xFF,0x01,0xFF,0xFF,0xC0,0xFC,0x0F,0xE0,0xFC, +0x01,0xF8,0x7C,0x00,0x7C,0x3E,0x00,0x38,0x1F,0x80, +0x00,0x0F,0xE0,0x00,0x03,0xFF,0x00,0x01,0xFF,0xF0, +0x00,0x7F,0xFF,0x00,0x1F,0xFF,0xE0,0x03,0xFF,0xFC, +0x00,0x7F,0xFF,0x00,0x07,0xFF,0x80,0x00,0x3F,0xE0, +0x00,0x03,0xF1,0xC0,0x00,0xFB,0xE0,0x00,0x7D,0xF8, +0x00,0x3E,0x7E,0x00,0x3F,0x3F,0xC0,0x7F,0x41,0xFF, +0xFF,0xE0,0x7F,0xFF,0xE0,0x0F,0xFF,0xC0,0x00,0xFF, +0x00,0x07,0xCE,0x20,0x10,0x00,0x40,0x01,0xC0,0x03, +0xC0,0xD0,0xF8,0x17,0xFF,0xFB,0x43,0xE0,0x68,0x7C, +0x0A,0x0F,0x80,0x0F,0xC1,0x01,0xFF,0x80,0xFF,0xC0, +0x7F,0xC0,0x3F,0xC0,0x0B,0xBA,0x80,0x1F,0xDF,0x80, +0x03,0xFB,0xF0,0x00,0x7E,0xFE,0x00,0x0F,0xC7,0xC0, +0x03,0xF7,0xE0,0x07,0xF7,0xF0,0x0F,0xF3,0xF8,0x3F, +0xF3,0xFF,0xFD,0xF1,0xFF,0xFD,0xF1,0xFF,0xF9,0xF0, +0x7F,0xE1,0xF0,0x1F,0x81,0xF0,0x0D,0xBA,0x20,0x1D, +0x7C,0x00,0x01,0xF8,0x7C,0x00,0x07,0xC7,0xE0,0x00, +0xFD,0x07,0xC0,0x01,0xF0,0x7E,0x00,0x3F,0x20,0x7C, +0x00,0x7C,0x07,0xE0,0x0F,0xC4,0x07,0xC0,0x1F,0x00, +0x3E,0x03,0xF0,0x03,0xE0,0x3E,0x00,0x3F,0x07,0xE0, +0x80,0x3E,0x0F,0x80,0x03,0xF1,0xF8,0x10,0x03,0xE3, +0xE0,0x00,0x3F,0x7E,0x02,0x00,0x3E,0xF8,0x00,0x01, +0xFF,0x80,0x40,0x03,0xFE,0x00,0x90,0x03,0xF8,0x00, +0x13,0xBA,0x00,0x27,0x7C,0x00,0x3E,0x00,0x1F,0x8F, +0x80,0x0F,0xE0,0x03,0xF0,0xF8,0x01,0xFC,0x00,0xF8, +0xF8,0x03,0xFE,0x00,0xF8,0x7C,0x03,0xFE,0x01,0xF2, +0x0F,0x80,0x7B,0xC0,0x3E,0x40,0xF8,0x1F,0x7C,0x0F, +0x80,0xF8,0x1E,0x7C,0x0F,0x80,0x7C,0x1E,0x3C,0x1F, +0x08,0x0F,0x87,0xC7,0xC3,0xE0,0x07,0x87,0xC7,0xC7, +0xC0,0x07,0xC7,0x83,0xC7,0xC1,0x00,0xF9,0xF0,0x7C, +0xF8,0x00,0x7D,0xF0,0x7D,0xF0,0x20,0x0F,0xBC,0x07, +0xBE,0x04,0x00,0xFF,0x80,0xFF,0x80,0x00,0xFF,0x00, +0xFF,0x80,0x90,0x0F,0xE0,0x0F,0xE0,0x00,0x07,0xE0, +0x0F,0xC0,0x00,0x0E,0x3A,0x00,0x1C,0x3F,0x00,0x01, +0xF8,0xFC,0x00,0x1F,0x83,0xF0,0x01,0xF9,0x01,0xF8, +0x03,0xF0,0x07,0xE0,0x3F,0x00,0x1F,0x83,0xF0,0x00, +0xFC,0x3F,0x00,0x03,0xF1,0xF8,0x00,0x0F,0xDF,0x80, +0x00,0x3F,0xF8,0x00,0x01,0xFF,0x80,0x00,0x07,0xFC, +0x01,0x00,0x03,0xF8,0x00,0x00,0x3F,0xC0,0x00,0x03, +0xFF,0x00,0x00,0x1F,0xFC,0x00,0x01,0xFF,0xE0,0x00, +0x1F,0x9F,0x80,0x01,0xF8,0x7E,0x00,0x0F,0xC1,0xF8, +0x00,0xFC,0x0F,0xC0,0x0F,0xC0,0x3F,0x08,0x1F,0x80, +0x1F,0x81,0xF8,0x00,0x7E,0x1F,0x80,0x01,0xF9,0xF8, +0x00,0x07,0xE0,0x0C,0xD0,0x3D,0x5B,0x7C,0x00,0x07, +0xCF,0x80,0x03,0xF8,0x7C,0x00,0x1F,0x0F,0x80,0x0F, +0xC3,0xE0,0x03,0xE0,0xFC,0x00,0xF8,0x1F,0x00,0x7E, +0x07,0xC0,0x1F,0x01,0xF8,0x07,0xC0,0x3E,0x03,0xF0, +0x0F,0x80,0xF8,0x03,0xF0,0x3E,0x00,0x7C,0x1F,0x80, +0x1F,0x07,0xC0,0x07,0xE1,0xF0,0x00,0xF8,0xFC,0x00, +0x3E,0x3E,0x00,0x07,0xCF,0x80,0x01,0xF7,0xE0,0x00, +0x7D,0xF0,0x00,0x0F,0xFC,0x04,0x00,0x7F,0xC0,0x00, +0x0F,0xF0,0x08,0x00,0x7F,0x00,0x00,0x0F,0xC0,0x10, +0x00,0x7C,0x00,0x00,0x3F,0x00,0x00,0x0F,0x80,0x08, +0x00,0xFC,0x00,0x00,0x7E,0x00,0x03,0xFF,0x80,0x00, +0xFF,0xC0,0x00,0x1F,0xE0,0x00,0x07,0xF0,0x00,0x01, +0xF8,0x00,0x00,0x0C,0xBA,0x20,0x1B,0xB3,0xFF,0xFF, +0xF0,0x00,0x01,0xF8,0x00,0x00,0xFC,0x00,0x00,0x7E, +0x00,0x00,0x3F,0x00,0x00,0x1F,0x80,0x00,0x0F,0xE0, +0x00,0x07,0xF0,0x00,0x03,0xF8,0x00,0x00,0xFC,0x00, +0x00,0x7E,0x00,0x00,0x3F,0x00,0x00,0x1F,0x80,0x00, +0x0F,0xC0,0x00,0x07,0xE0,0x00,0x03,0xF8,0x00,0x01, +0xFC,0x00,0x00,0xFE,0x00,0x00,0x3F,0x00,0x00,0x1F, +0x80,0x00,0x17,0xFF,0xFF,0xFF,0x08,0xE6,0x3D,0x53, +0x00,0x0F,0xC0,0x0F,0xF0,0x07,0xFE,0x00,0x7F,0xE0, +0x3F,0x80,0x0F,0xC1,0xA0,0x7C,0x0B,0x03,0xE0,0x40, +0x3E,0x00,0x1F,0x80,0x0F,0xC0,0x1F,0xE0,0x07,0xF0, +0x01,0xF0,0x00,0x7F,0x00,0x1F,0xE0,0x01,0xFC,0x00, +0x1F,0x80,0x80,0x7C,0x06,0x81,0xF0,0x30,0x0F,0x80, +0x03,0xF8,0x40,0x0F,0xFC,0x01,0xFF,0x00,0x3F,0xC0, +0x03,0xF0,0x02,0x6A,0xBC,0xCE,0xDF,0xDF,0xDF,0xDF, +0xDF,0xDF,0xDF,0xAF,0x08,0xE6,0x3D,0x53,0x7E,0x00, +0x1F,0xE0,0x07,0xFC,0x02,0x3F,0xF0,0x00,0xFE,0x00, +0x1F,0x81,0xA0,0x7C,0x0B,0x03,0xE0,0x00,0xFC,0x00, +0x1F,0x00,0x07,0xE0,0x00,0xFC,0x00,0x1F,0xE0,0x03, +0xF8,0x00,0x3E,0x00,0x3F,0x80,0x1F,0xE0,0x0F,0xC0, +0x07,0xE0,0x01,0xF0,0x00,0xFC,0x1A,0x07,0xC0,0xB0, +0x3E,0x00,0x1F,0x80,0x0F,0xE0,0x47,0xFE,0x01,0xFF, +0x00,0x7F,0x80,0x1F,0x80,0x00,0x0E,0x14,0x43,0xA1, +0x03,0xE0,0x00,0x00,0x7F,0xE0,0x00,0x47,0xFF,0xC0, +0x06,0x7F,0xFF,0x80,0x77,0xFF,0xFF,0x0F,0xBE,0x0F, +0xFF,0xFD,0xC0,0x1F,0xFF,0xCC,0x00,0x7F,0xFC,0x40, +0x00,0xFF,0xC0,0x00,0x01,0xF8,0x00,}; +/* font data size: 7477 bytes */ + +static const unsigned char Arial_40_index[] = { +0x00,0x00,0x01, +0x00,0x20,0x01,0xC0,0x32,0x03,0xD8,0x3B,0x62,0x79, +0x14,0x08,0xAF,0xC5,0xFA,0x32,0x31,0x9D,0x8D,0x14, +0x69,0x83,0x52,0x1B,0xF8,0xF4,0x07,0xF0,0x46,0xE2, +0x75,0x94,0xFC,0xB3,0xA6,0x12,0x32,0xD1,0xB1,0x0E, +0x64,0x73,0xC3,0xA5,0x1E,0xB4,0xF7,0xA8,0x20,0x44, +0x3A,0x79,0x14,0xDA,0xAE,0x75,0xBE,0xAF,0xBD,0x82, +0x0C,0x2F,0x66,0x43,0x3A,0x99,0xEA,0xD2,0x26,0xE2, +0xB7,0x79,0xC7,0x0E,0xB8,0x7A,0x83,0xEA,0x20,0x95, +0x0E,0x08,0xC0,0xC6,0x82,0x3C,0x92,0x5F,0x99,0xCC, +0xF7,0x28,0x8D,0x4C,0xBA,0x6F,0x54,0x2E,0xA3,0xD5, +0x48,0xAA,0x8D,0x57,0xEB,0x8D,0x62,0x0B,0x3B,0x5B, +0x36,0xE4,0xD7,0x46,0xBD,0xBD,0xFA,0x2F,0xE9,0x80, +0xCC,0x32,0x61,0xBF,0x16,0x38,0xDB,0xC9,0x76,0x60, +0xB3,0xB3,0x9F,0x6D,0x2A,0xE9,0xDB,0x54,0x1A,0xEA, +0xDA,0x8E,0xED,0x78,0x5B,0xC7,0x6E,0x5C,0x73,0x13, +0xA1,0x80, +}; +/* font index size: 155 bytes */ + +const ILI9341_t3_font_t Arial_40 = { + Arial_40_index, + 0, + Arial_40_data, + 1, + 0, + 32, + 126, + 0, + 0, + 13, + 6, + 6, + 4, + 7, + 6, + 61, + 40 +}; + + + +static const unsigned char Arial_48_data[] = { +0x00,0x00,0x00,0x02,0x60,0x01,0xB0,0x40,0x02,0xDB, +0xFE,0xFF,0x3F,0x9F,0xD7,0xAD,0xE1,0xD8,0x65,0x81, +0x9F,0x80,0x04,0x91,0x19,0xF3,0x1B,0xF8,0x1F,0xD7, +0xE0,0x7F,0x8F,0x00,0xF0,0x09,0x30,0x00,0x04,0xB0, +0x00,0x0F,0xC0,0x3F,0x00,0x00,0xFE,0x03,0xF0,0xA0, +0x00,0xFC,0x03,0xF0,0x00,0x0F,0xE0,0x3F,0x05,0x00, +0x0F,0xC0,0x3F,0x00,0x00,0xFE,0x03,0xF0,0x33,0xFF, +0xFF,0xFF,0xFF,0xE0,0x01,0xF8,0x07,0xE0,0x00,0x0F, +0xC0,0x7F,0x01,0x40,0x1F,0x80,0x7E,0x00,0x01,0xFC, +0x07,0xE0,0x08,0x01,0xF8,0x07,0xE0,0x0C,0xFF,0xFF, +0xFF,0xFF,0xF0,0x1F,0x80,0xFE,0x00,0x50,0x3F,0x00, +0xFC,0x00,0x01,0xF8,0x0F,0xE0,0x02,0x83,0xF0,0x0F, +0xC0,0x00,0x1F,0x80,0xFE,0x00,0x10,0x3F,0x00,0xFC, +0x00,0x00,0x07,0xFA,0x1F,0x94,0xB2,0x00,0x07,0x00, +0x00,0x00,0x3F,0xE0,0x00,0x01,0xFF,0xFC,0x00,0x07, +0xFF,0xFF,0x00,0x0F,0xFF,0xFF,0x80,0x1F,0xFF,0xFF, +0xC0,0x3F,0xFF,0xFF,0xE0,0x7F,0xE7,0x3F,0xE0,0x7F, +0x87,0x0F,0xF0,0x7F,0x07,0x07,0xF0,0xFE,0x07,0x03, +0xF0,0xFC,0x07,0x03,0xF8,0xFC,0x07,0x01,0xF8,0xFC, +0x07,0x01,0xC2,0x1F,0x80,0xE0,0x00,0x1F,0xC0,0xE0, +0x00,0x0F,0xC0,0xE0,0x00,0x0F,0xE0,0xE0,0x00,0x0F, +0xF8,0xE0,0x00,0x07,0xFE,0xE0,0x00,0x03,0xFF,0xE0, +0x00,0x01,0xFF,0xFC,0x00,0x00,0xFF,0xFF,0x80,0x00, +0x3F,0xFF,0xE0,0x00,0x0F,0xFF,0xF0,0x00,0x01,0xFF, +0xFC,0x00,0x00,0xFF,0xFC,0x00,0x00,0xE3,0xFE,0x00, +0x00,0xE0,0xFF,0x00,0x00,0xE0,0x7F,0x00,0x00,0xE0, +0x3F,0x00,0x00,0xE0,0x3F,0xC0,0x00,0x1C,0x03,0xF0, +0xE0,0x1C,0x03,0xF7,0xE0,0x1C,0x03,0xF7,0xF0,0x1C, +0x03,0xF7,0xF0,0x1C,0x07,0xF3,0xF0,0x1C,0x07,0xF3, +0xF8,0x1C,0x0F,0xE3,0xFC,0x1C,0x1F,0xE1,0xFE,0x1C, +0x3F,0xC1,0xFF,0x9C,0xFF,0xC0,0xFF,0xFF,0xFF,0x80, +0x7F,0xFF,0xFF,0x00,0x3F,0xFF,0xFE,0x00,0x1F,0xFF, +0xFC,0x00,0x07,0xFF,0xF0,0x00,0x00,0xFF,0x80,0x0C, +0x00,0x03,0x80,0x00,0x0D,0x32,0x27,0xF7,0x80,0x1F, +0x80,0x00,0x00,0x7E,0x00,0x03,0xFF,0x00,0x00,0x03, +0xE0,0x00,0x7F,0xFC,0x00,0x00,0x3F,0x00,0x03,0xFF, +0xF0,0x00,0x03,0xF0,0x00,0x3F,0x0F,0xC0,0x00,0x1F, +0x00,0x03,0xF0,0x3F,0x00,0x01,0xF8,0x00,0x1F,0x00, +0xF8,0x00,0x0F,0x80,0x00,0xF8,0x07,0xC0,0x00,0xFC, +0x00,0x0F,0x80,0x1F,0x00,0x07,0xC0,0x00,0x7C,0x00, +0xF8,0x00,0x7E,0x00,0x03,0xE0,0x07,0xC0,0x03,0xE0, +0x00,0x1F,0x00,0x3E,0x00,0x3F,0x00,0x01,0x1F,0x00, +0x3E,0x00,0x7E,0x00,0x00,0xF8,0x01,0xF0,0x07,0xE0, +0x00,0x07,0xC0,0x0F,0x80,0x3E,0x00,0x00,0x3E,0x00, +0x7C,0x03,0xF0,0x00,0x01,0xF0,0x03,0xE0,0x1F,0x00, +0x00,0x07,0xC0,0x3E,0x01,0xF8,0x00,0x00,0x3E,0x01, +0xF0,0x0F,0x80,0x00,0x01,0xF8,0x1F,0x00,0xFC,0x00, +0x00,0x07,0xE1,0xF8,0x07,0xC0,0x00,0x00,0x1F,0xFF, +0x80,0x7E,0x00,0x00,0x00,0x7F,0xF8,0x07,0xE0,0x00, +0x00,0x01,0xFF,0x80,0x3F,0x00,0x7E,0x00,0x03,0xF0, +0x03,0xF0,0x0F,0xFC,0x00,0x00,0x00,0x1F,0x01,0xFF, +0xF0,0x00,0x00,0x01,0xF8,0x0F,0xFF,0xC0,0x00,0x00, +0x0F,0x80,0xFC,0x3F,0x00,0x00,0x00,0xFC,0x0F,0xC0, +0xFC,0x00,0x00,0x07,0xC0,0x7C,0x03,0xE0,0x00,0x00, +0x7E,0x03,0xE0,0x1F,0x00,0x00,0x03,0xE0,0x3E,0x00, +0x7C,0x00,0x00,0x3F,0x01,0xF0,0x03,0xF0,0x00,0x00, +0x7E,0x01,0xF0,0x03,0xE0,0x00,0x07,0xE0,0x0F,0x80, +0x1F,0x00,0x00,0x3E,0x00,0x7C,0x00,0xF8,0x00,0x03, +0xF0,0x03,0xE0,0x07,0xC0,0x00,0x1F,0x00,0x1F,0x00, +0x3E,0x00,0x01,0xF8,0x00,0xF8,0x01,0xF0,0x00,0x0F, +0x80,0x07,0xC0,0x0F,0x80,0x00,0xFC,0x00,0x1F,0x00, +0xF8,0x00,0x07,0xC0,0x00,0xF8,0x07,0xC0,0x00,0x7E, +0x00,0x07,0xE0,0x7C,0x00,0x07,0xE0,0x00,0x1F,0x87, +0xE0,0x00,0x3E,0x00,0x00,0x7F,0xFE,0x00,0x03,0xF0, +0x00,0x01,0xFF,0xE0,0x00,0x1F,0x00,0x00,0x07,0xFE, +0x00,0x01,0xF8,0x00,0x00,0x0F,0xC0,0x00,0x0A,0x32, +0x1F,0xF5,0xA0,0x00,0x3F,0x80,0x00,0x00,0x00,0x7F, +0xF8,0x00,0x00,0x00,0xFF,0xFE,0x00,0x00,0x00,0xFF, +0xFF,0x80,0x00,0x00,0xFF,0xFF,0xE0,0x00,0x00,0xFF, +0xFF,0xF8,0x00,0x00,0x7F,0x83,0xFC,0x00,0x00,0x3F, +0x80,0xFF,0x00,0x00,0x3F,0x80,0x3F,0x80,0x0A,0x03, +0xF0,0x01,0xF8,0x00,0x01,0xFC,0x00,0xFC,0x00,0x00, +0x7E,0x00,0xFC,0x00,0x00,0x3F,0x80,0xFE,0x00,0x00, +0x0F,0xE0,0xFE,0x00,0x00,0x07,0xF0,0xFE,0x00,0x00, +0x01,0xFD,0xFE,0x00,0x00,0x00,0x7F,0xFE,0x00,0x00, +0x00,0x3F,0xFE,0x00,0x00,0x00,0x0F,0xFC,0x00,0x00, +0x00,0x1F,0xFC,0x00,0x00,0x00,0x1F,0xFE,0x00,0x00, +0x00,0x3F,0xFF,0x80,0x00,0x00,0x3F,0xEF,0xE0,0x00, +0x00,0x3F,0xC7,0xF8,0x00,0x00,0x3F,0xC1,0xFE,0x03, +0xC0,0x3F,0xC0,0x7F,0x03,0xF8,0x1F,0xC0,0x1F,0xC1, +0xFC,0x1F,0xC0,0x07,0xF0,0xFC,0x0F,0xC0,0x03,0xFC, +0xFE,0x0F,0xE0,0x00,0xFF,0x7E,0x07,0xE0,0x00,0x3F, +0xFF,0x03,0xF0,0x00,0x0F,0xFF,0x01,0xF8,0x00,0x03, +0xFF,0x80,0xFC,0x00,0x01,0xFF,0x80,0x7E,0x00,0x00, +0x7F,0xC0,0x3F,0x80,0x00,0x1F,0xE0,0x1F,0xC0,0x00, +0x1F,0xF8,0x07,0xF0,0x00,0x1F,0xFE,0x03,0xFC,0x00, +0x1F,0xFF,0x80,0xFF,0x00,0x1F,0xFF,0xE0,0x7F,0xE0, +0x7F,0xF7,0xF8,0x1F,0xFF,0xFF,0xF3,0xFE,0x07,0xFF, +0xFF,0xF0,0xFF,0x81,0xFF,0xFF,0xF0,0x3F,0x80,0x7F, +0xFF,0xE0,0x0F,0x80,0x0F,0xFF,0xC0,0x03,0x80,0x00, +0xFF,0x00,0x00,0x80,0x01,0x91,0x19,0xF1,0xBB,0xFD, +0x7F,0x8F,0x00,0x04,0x3D,0x27,0x32,0xC0,0x00,0xF0, +0x00,0xF0,0x00,0xF8,0x00,0xF8,0x00,0x78,0x00,0x7C, +0x40,0x0F,0x84,0x01,0xF0,0x40,0x3E,0x04,0x07,0xC0, +0x07,0xE0,0x03,0xE0,0x10,0x7E,0x00,0x3E,0x00,0xA7, +0xE0,0x03,0xE0,0x06,0xFE,0x00,0x67,0xE0,0x05,0xBF, +0x00,0x49,0xF8,0x00,0x7C,0x00,0x3F,0x01,0x01,0xF0, +0x10,0x0F,0x81,0x00,0x7C,0x10,0x03,0xE0,0x00,0xF8, +0x00,0x3C,0x00,0x1F,0x00,0x07,0x80,0x01,0xE0,0x00, +0x78,0x04,0x3D,0x17,0x32,0xCF,0x00,0x03,0xC0,0x01, +0xF0,0x00,0x7C,0x00,0x1E,0x00,0x0F,0x80,0x40,0x7C, +0x04,0x03,0xE0,0x40,0x1F,0x04,0x00,0xF8,0x00,0x7E, +0x00,0x1F,0x10,0x01,0xF8,0x00,0x7C,0xB0,0x07,0xED, +0x00,0x3F,0xC0,0x03,0xFA,0x00,0x7E,0x00,0x3E,0x48, +0x07,0xE0,0x03,0xE0,0x03,0xF1,0x00,0x3E,0x10,0x07, +0xC1,0x00,0xF8,0x10,0x1F,0x00,0x1F,0x00,0x0F,0x00, +0x0F,0x80,0x07,0x80,0x07,0x80,0x07,0x80,0x00,0x05, +0xD4,0x11,0xC3,0x56,0x00,0xF8,0x00,0xE0,0xF8,0x38, +0xFC,0x71,0xF8,0xFF,0x7F,0xF9,0xFF,0xFF,0xFC,0x7F, +0xFF,0xF0,0x03,0xFF,0x00,0x01,0xFC,0x00,0x03,0xFE, +0x00,0x07,0xDF,0x00,0x0F,0x9F,0x80,0x1F,0x8F,0xC2, +0x07,0xE0,0xFC,0x01,0xC0,0x70,0x00,0x80,0x20,0x00, +0x08,0x20,0x18,0x74,0xFA,0x00,0x0F,0xC0,0x01,0x80, +0x00,0xFC,0x00,0x19,0xFF,0xFF,0xFF,0xFF,0xA0,0x00, +0xFC,0x00,0x18,0x00,0x0F,0xC0,0x00,0x01,0x90,0x37, +0x62,0x79,0xFD,0x0E,0x3E,0x0E,0x38,0xF0,0xC0,0x04, +0x86,0x10,0xE2,0xD9,0xFF,0xFF,0x80,0x01,0x86,0x30, +0x02,0x79,0xF8,0x04,0xF0,0x00,0x02,0x70,0x00,0x07, +0xE4,0x00,0x1F,0x00,0x03,0xF4,0x80,0x07,0xC9,0x00, +0x1F,0x00,0x03,0xF1,0x00,0x07,0xC0,0x00,0xFC,0x24, +0x01,0xF0,0x48,0x07,0xC0,0x00,0xFC,0x09,0x01,0xF0, +0x12,0x07,0xC0,0x00,0xFC,0x02,0x41,0xF0,0x04,0x87, +0xC0,0x00,0xFC,0x00,0x81,0xF0,0x00,0x3F,0x00,0x12, +0x7C,0x00,0x25,0xF0,0x00,0x3F,0x00,0x03,0xE0,0x00, +0x00,0x07,0xF1,0x1F,0xF4,0xA0,0x01,0xFF,0x00,0x00, +0x07,0xFF,0xC0,0x00,0x1F,0xFF,0xF0,0x00,0x3F,0xFF, +0xF8,0x00,0x7F,0xFF,0xFC,0x00,0xFF,0xFF,0xFE,0x01, +0xFF,0x83,0xFE,0x01,0xFE,0x00,0xFF,0x03,0xF8,0x00, +0x7F,0x03,0xF8,0x00,0x3F,0x83,0xF0,0x00,0x1F,0x87, +0xF0,0x00,0x1F,0x94,0xFC,0x00,0x01,0xF9,0xF8,0x00, +0x00,0xFB,0x7F,0x00,0x00,0x1F,0xEF,0xE0,0x00,0x03, +0xF8,0xFC,0x00,0x00,0x7F,0x4F,0xC0,0x00,0x1F,0x8F, +0xE0,0x00,0x3F,0x87,0xE0,0x00,0x3F,0x07,0xF0,0x00, +0x7F,0x07,0xF8,0x00,0xFF,0x03,0xFC,0x01,0xFE,0x03, +0xFF,0x07,0xFE,0x01,0xFF,0xFF,0xFC,0x00,0xFF,0xFF, +0xF8,0x00,0x7F,0xFF,0xF0,0x00,0x3F,0xFF,0xE0,0x00, +0x1F,0xFF,0x80,0x00,0x03,0xFE,0x00,0x00,0x04,0x70, +0x38,0x04,0xA0,0x00,0x7C,0x00,0x07,0xC0,0x03,0xF0, +0x01,0xFC,0x00,0xFF,0x00,0x7F,0xC0,0x3F,0xF0,0x1F, +0xFC,0x1F,0xFF,0x0F,0xFF,0xCF,0xFB,0xF7,0xFC,0xFD, +0xFE,0x3F,0x7E,0x0F,0xDE,0x03,0xF7,0x00,0xFF,0x40, +0x07,0xFA,0x00,0x3F,0xD0,0x01,0xFE,0x80,0x0F,0xE4, +0x00,0x7E,0x07,0xF0,0x10,0x04,0xA0,0x00,0xFF,0x80, +0x00,0x07,0xFF,0xF0,0x00,0x1F,0xFF,0xF8,0x00,0x7F, +0xFF,0xFE,0x10,0x1F,0xFF,0xFF,0xE0,0x3F,0xF0,0x3F, +0xF0,0x7F,0x80,0x07,0xF8,0x7F,0x00,0x03,0xF8,0x7E, +0x00,0x01,0xF8,0xFE,0x00,0x01,0xFE,0x1F,0x80,0x00, +0x1F,0x83,0x80,0x00,0x1F,0xC8,0x00,0x00,0x03,0xF8, +0x00,0x00,0x00,0xFC,0x00,0x00,0x01,0xFC,0x00,0x00, +0x03,0xF8,0x00,0x00,0x07,0xF8,0x00,0x00,0x0F,0xF0, +0x00,0x00,0x1F,0xE0,0x00,0x00,0x3F,0xC0,0x00,0x00, +0x7F,0xC0,0x00,0x00,0xFF,0x80,0x00,0x01,0xFF,0x00, +0x00,0x03,0xFE,0x00,0x00,0x07,0xF8,0x00,0x00,0x0F, +0xF0,0x00,0x00,0x1F,0xE0,0x00,0x00,0x7F,0xC0,0x00, +0x00,0xFF,0x80,0x00,0x01,0xFF,0x00,0x00,0x03,0xFE, +0x00,0x00,0x07,0xF8,0x00,0x00,0x0F,0xF0,0x00,0x00, +0x0F,0xE0,0x00,0x00,0x1F,0xC0,0x00,0x01,0x07,0xF0, +0x00,0x00,0x21,0xFF,0xFF,0xFF,0xFD,0x7F,0xFF,0xFF, +0xFF,0x07,0xF1,0x1F,0xF4,0xA0,0x03,0xFC,0x00,0x00, +0x1F,0xFF,0x80,0x00,0x3F,0xFF,0xE0,0x00,0xFF,0xFF, +0xF0,0x01,0xFF,0xFF,0xF8,0x01,0xFF,0xFF,0xFC,0x03, +0xFE,0x03,0xFE,0x07,0xF8,0x01,0xFE,0x07,0xF0,0x00, +0x7E,0x07,0xE0,0x00,0x7F,0x0F,0xE0,0x00,0x3F,0x0F, +0xC0,0x00,0x3F,0x01,0xC0,0x00,0x3F,0x10,0x00,0x00, +0x07,0xE0,0x00,0x00,0x0F,0xC0,0x00,0x00,0x1F,0xC0, +0x00,0x00,0x3F,0x80,0x00,0x00,0xFF,0x00,0x00,0x1F, +0xFE,0x00,0x00,0x1F,0xFC,0x00,0x00,0x1F,0xF8,0x00, +0x00,0x1F,0xFF,0x00,0x00,0x1F,0xFF,0x80,0x00,0x18, +0xFF,0xC0,0x00,0x00,0x1F,0xE0,0x00,0x00,0x07,0xF0, +0x00,0x00,0x03,0xFA,0x00,0x00,0x00,0x3F,0x58,0x00, +0x00,0x03,0xF0,0xE0,0x00,0x03,0xF7,0xE0,0x00,0x03, +0xF7,0xF0,0x00,0x07,0xF7,0xF0,0x00,0x07,0xE3,0xF8, +0x00,0x0F,0xE3,0xFC,0x00,0x1F,0xC1,0xFE,0x00,0x3F, +0xC1,0xFF,0x80,0xFF,0x80,0xFF,0xFF,0xFF,0x00,0x7F, +0xFF,0xFE,0x00,0x3F,0xFF,0xFC,0x00,0x1F,0xFF,0xF8, +0x00,0x07,0xFF,0xE0,0x00,0x00,0xFF,0x00,0x00,0x08, +0x6F,0x08,0x04,0xA0,0x00,0x00,0x3E,0x00,0x00,0x00, +0x1F,0x80,0x00,0x00,0x0F,0xE0,0x40,0x00,0x00,0xFF, +0x00,0x00,0x00,0x7F,0xC0,0x00,0x00,0x3F,0xF0,0x20, +0x00,0x03,0xFF,0x80,0x00,0x01,0xFF,0xE0,0x40,0x00, +0x1F,0xFF,0x00,0x00,0x0F,0xEF,0xC0,0x00,0x07,0xF3, +0xF0,0x00,0x03,0xFC,0xFC,0x00,0x00,0xFE,0x3F,0x00, +0x00,0x7F,0x0F,0xC0,0x00,0x3F,0x83,0xF0,0x00,0x1F, +0xE0,0xFC,0x00,0x07,0xF0,0x3F,0x00,0x03,0xF8,0x0F, +0xC0,0x01,0xFC,0x03,0xF0,0x00,0xFF,0x00,0xFC,0x00, +0x3F,0x80,0x3F,0x00,0x1F,0xC0,0x0F,0xC0,0x0F,0xF0, +0x03,0xF0,0x03,0xF8,0x00,0xFC,0x01,0xFC,0x00,0x3F, +0x00,0xFE,0x00,0x0F,0xC0,0x7F,0x80,0x03,0xF0,0x33, +0xFF,0xFF,0xFF,0xFF,0xA0,0x00,0x00,0xFC,0x0A,0x00, +0x00,0x07,0xE0,0x00,0x07,0xF0,0x1F,0xF4,0xB0,0x07, +0xFF,0xFF,0xE2,0x81,0xFF,0xFF,0xFC,0x01,0xF8,0x00, +0x00,0x03,0xF8,0x00,0x00,0x50,0x7E,0x00,0x00,0x08, +0x1F,0xC0,0x00,0x00,0x1F,0x80,0x00,0x00,0x1F,0x83, +0xF8,0x00,0x1F,0x9F,0xFE,0x00,0x3F,0xBF,0xFF,0x80, +0x3F,0xFF,0xFF,0xC0,0x3F,0xFF,0xFF,0xE0,0x3F,0xFF, +0xFF,0xF0,0x3F,0xF0,0x1F,0xF8,0x7F,0xC0,0x07,0xF8, +0x7F,0x80,0x03,0xFC,0x7F,0x00,0x01,0xFC,0x0E,0x00, +0x00,0xFC,0x00,0x00,0x00,0xFF,0xA0,0x00,0x00,0x0F, +0xC0,0x00,0x00,0x0F,0xE3,0xF0,0x00,0x03,0xF3,0xF8, +0x00,0x03,0xF1,0xF8,0x00,0x07,0xE1,0xFC,0x00,0x0F, +0xE0,0xFE,0x00,0x1F,0xC0,0xFF,0x80,0x7F,0xC0,0x7F, +0xFF,0xFF,0x80,0x3F,0xFF,0xFF,0x00,0x1F,0xFF,0xFE, +0x00,0x0F,0xFF,0xFC,0x00,0x03,0xFF,0xF0,0x00,0x00, +0x7F,0x80,0x00,0x08,0x31,0x17,0xF4,0xA0,0x00,0x7F, +0x80,0x00,0x01,0xFF,0xF8,0x00,0x03,0xFF,0xFF,0x00, +0x03,0xFF,0xFF,0xC0,0x03,0xFF,0xFF,0xF0,0x03,0xFF, +0xFF,0xFC,0x03,0xFF,0x03,0xFE,0x01,0xFC,0x00,0x7F, +0x81,0xFC,0x00,0x1F,0xC0,0xFE,0x00,0x07,0xE0,0xFE, +0x00,0x03,0xF8,0x7E,0x00,0x00,0xFC,0x3F,0x00,0x00, +0x00,0xA7,0xE0,0x00,0x00,0x03,0xE0,0x1F,0xC0,0x03, +0xF0,0x7F,0xFC,0x01,0xF8,0x7F,0xFF,0x80,0xFC,0xFF, +0xFF,0xE0,0x7E,0xFF,0xFF,0xF8,0x3F,0x7F,0xFF,0xFE, +0x1F,0xFF,0x01,0xFF,0x8F,0xFC,0x00,0x3F,0xC7,0xFC, +0x00,0x0F,0xF3,0xFC,0x00,0x03,0xF9,0xFC,0x00,0x00, +0xFC,0xFE,0x00,0x00,0x7F,0xAF,0xC0,0x00,0x03,0xF9, +0x7C,0x00,0x00,0x3F,0x3F,0x00,0x00,0x3F,0x9F,0x80, +0x00,0x1F,0x87,0xE0,0x00,0x0F,0xC3,0xF0,0x00,0x0F, +0xE0,0xFC,0x00,0x0F,0xE0,0x7F,0x80,0x0F,0xF0,0x1F, +0xF0,0x1F,0xF1,0x00,0xFF,0xFF,0xFE,0x00,0x1F,0xFF, +0xFE,0x00,0x07,0xFF,0xFC,0x00,0x00,0xFF,0xFC,0x00, +0x00,0x0F,0xF0,0x00,0x07,0xEF,0x18,0x04,0xB7,0xFF, +0xFF,0xFF,0xFD,0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x00, +0xF8,0x00,0x00,0x01,0xF0,0x00,0x00,0x03,0xE0,0x00, +0x00,0x07,0xC0,0x00,0x00,0x0F,0xC0,0x00,0x00,0x1F, +0x80,0x00,0x00,0x1F,0x00,0x00,0x00,0x3F,0x00,0x00, +0x00,0x7E,0x00,0x00,0x00,0x7C,0x00,0x00,0x00,0xFC, +0x02,0x00,0x00,0x3F,0x00,0x40,0x00,0x0F,0xC0,0x08, +0x00,0x03,0xF0,0x01,0x00,0x00,0xFC,0x00,0x20,0x00, +0x3F,0x00,0x04,0x80,0x0F,0xC0,0x00,0x90,0x03,0xF0, +0x00,0x14,0x00,0xFC,0x00,0x02,0xC0,0x3F,0x00,0x00, +0x58,0x0F,0xC0,0x00,0x00,0x07,0xF1,0x1F,0xF4,0xA0, +0x01,0xFF,0x00,0x00,0x07,0xFF,0xC0,0x00,0x1F,0xFF, +0xF0,0x00,0x3F,0xFF,0xF8,0x00,0x7F,0xFF,0xFC,0x00, +0xFF,0xFF,0xFE,0x01,0xFF,0x01,0xFF,0x01,0xFC,0x00, +0x7F,0x01,0xF8,0x00,0x3F,0x03,0xF8,0x00,0x3F,0x96, +0x7E,0x00,0x03,0xF0,0x7F,0x00,0x07,0xF0,0x3F,0x00, +0x07,0xE0,0x3F,0x80,0x0F,0xE0,0x1F,0xE0,0x3F,0xC0, +0x0F,0xFF,0xFF,0x80,0x07,0xFF,0xFF,0x00,0x01,0xFF, +0xFC,0x00,0x03,0xFF,0xFE,0x00,0x0F,0xFF,0xFF,0x80, +0x1F,0xFF,0xFF,0xC0,0x3F,0xE0,0x3F,0xE0,0x7F,0x80, +0x0F,0xF0,0x7E,0x00,0x07,0xF0,0xFE,0x00,0x03,0xF8, +0xFC,0x00,0x01,0xF9,0xFC,0x00,0x01,0xFF,0x3F,0x00, +0x00,0x1F,0xBF,0x80,0x00,0x3F,0x9F,0x80,0x00,0x3F, +0x1F,0x80,0x00,0x7F,0x1F,0xC0,0x00,0x7F,0x0F,0xF0, +0x01,0xFE,0x0F,0xFC,0x07,0xFE,0x07,0xFF,0xFF,0xFC, +0x03,0xFF,0xFF,0xF8,0x01,0xFF,0xFF,0xF0,0x00,0xFF, +0xFF,0xE0,0x00,0x3F,0xFF,0x80,0x00,0x07,0xFC,0x00, +0x00,0x07,0xF1,0x1F,0xF4,0xA0,0x01,0xFE,0x00,0x00, +0x0F,0xFF,0x80,0x00,0x3F,0xFF,0xE0,0x00,0x7F,0xFF, +0xF0,0x00,0xFF,0xFF,0xFC,0x01,0xFF,0xFF,0xFC,0x01, +0xFF,0x01,0xFE,0x03,0xFC,0x00,0x7F,0x07,0xF8,0x00, +0x3F,0x07,0xF0,0x00,0x1F,0x87,0xF0,0x00,0x0F,0x8F, +0xE0,0x00,0x0F,0xCF,0xE0,0x00,0x07,0xD1,0xF8,0x00, +0x00,0xFA,0xFF,0x00,0x00,0x1F,0xBF,0x80,0x00,0x3F, +0x9F,0x80,0x00,0x3F,0x9F,0xC0,0x00,0x7F,0x9F,0xE0, +0x00,0xFF,0x8F,0xF0,0x01,0xFF,0x8F,0xFC,0x07,0xFF, +0x87,0xFF,0xFF,0xDF,0x83,0xFF,0xFF,0xDF,0x81,0xFF, +0xFF,0x9F,0x80,0xFF,0xFE,0x1F,0x80,0x3F,0xFC,0x1F, +0x80,0x0F,0xE0,0x1F,0xD0,0x00,0x00,0x07,0xE0,0x00, +0x00,0x0F,0xC8,0x7E,0x00,0x01,0xF8,0x7F,0x00,0x03, +0xF0,0x3F,0x00,0x07,0xF0,0x3F,0x80,0x0F,0xE0,0x1F, +0xE0,0x3F,0xE0,0x1F,0xFF,0xFF,0xC0,0x0F,0xFF,0xFF, +0x80,0x07,0xFF,0xFF,0x00,0x03,0xFF,0xFE,0x00,0x01, +0xFF,0xF8,0x00,0x00,0x3F,0xC0,0x00,0x01,0xA3,0x30, +0x02,0x79,0xFE,0x81,0xA0,0x68,0x10,0x06,0x7E,0x01, +0xAD,0x37,0x62,0x79,0xFE,0x81,0xA0,0x68,0x10,0x06, +0x7F,0x43,0x8F,0x1C,0x79,0xE1,0xC1,0x00,0x07,0xE1, +0x20,0x74,0xE0,0x00,0x00,0x00,0x20,0x00,0x00,0x00, +0xE0,0x00,0x00,0x07,0xE0,0x00,0x00,0x1F,0xE0,0x00, +0x00,0x7F,0xE0,0x00,0x01,0xFF,0xE0,0x00,0x07,0xFF, +0xC0,0x00,0x3F,0xFE,0x00,0x00,0xFF,0xF8,0x00,0x03, +0xFF,0xE0,0x00,0x0F,0xFF,0x00,0x00,0x3F,0xFC,0x00, +0x01,0xFF,0xF0,0x00,0x07,0xFF,0x80,0x00,0x0F,0xFE, +0x00,0x00,0x0F,0xF0,0x00,0x00,0x0F,0xC0,0x00,0x00, +0x0F,0xF0,0x00,0x00,0x0F,0xFE,0x00,0x00,0x07,0xFF, +0x80,0x00,0x01,0xFF,0xF0,0x00,0x00,0x3F,0xFC,0x00, +0x00,0x0F,0xFF,0x00,0x00,0x03,0xFF,0xE0,0x00,0x00, +0xFF,0xF8,0x00,0x00,0x3F,0xFE,0x00,0x00,0x07,0xFF, +0xC0,0x00,0x01,0xFF,0xE0,0x00,0x00,0x7F,0xE0,0x00, +0x00,0x1F,0xE0,0x00,0x00,0x07,0xE0,0x00,0x00,0x00, +0xE0,0x00,0x00,0x00,0x20,0x08,0x14,0x18,0xE4,0xF9, +0xFF,0xFF,0xFF,0xFF,0xA0,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x0C,0xFF,0xFF,0xFF,0xFF,0x07,0xE1,0x20, +0x74,0xE8,0x00,0x00,0x00,0x0E,0x00,0x00,0x00,0x0F, +0xC0,0x00,0x00,0x0F,0xF0,0x00,0x00,0x0F,0xFC,0x00, +0x00,0x0F,0xFF,0x00,0x00,0x07,0xFF,0xC0,0x00,0x00, +0xFF,0xF8,0x00,0x00,0x3F,0xFE,0x00,0x00,0x0F,0xFF, +0x80,0x00,0x01,0xFF,0xE0,0x00,0x00,0x7F,0xF8,0x00, +0x00,0x1F,0xFF,0x00,0x00,0x03,0xFF,0xC0,0x00,0x00, +0xFF,0xE0,0x00,0x00,0x1F,0xE0,0x00,0x00,0x07,0xE0, +0x00,0x00,0x1F,0xE0,0x00,0x00,0xFF,0xE0,0x00,0x03, +0xFF,0xC0,0x00,0x1F,0xFF,0x00,0x00,0x7F,0xF8,0x00, +0x01,0xFF,0xE0,0x00,0x0F,0xFF,0x80,0x00,0x3F,0xFE, +0x00,0x00,0xFF,0xF8,0x00,0x07,0xFF,0xC0,0x00,0x0F, +0xFF,0x00,0x00,0x0F,0xFC,0x00,0x00,0x0F,0xF0,0x00, +0x00,0x0F,0xC0,0x00,0x00,0x0E,0x00,0x00,0x00,0x08, +0x00,0x00,0x00,0x00,0x07,0xF1,0x18,0x04,0xA0,0x01, +0xFF,0x00,0x00,0x0F,0xFF,0xE0,0x00,0x3F,0xFF,0xF8, +0x00,0x7F,0xFF,0xFC,0x00,0xFF,0xFF,0xFE,0x01,0xFF, +0xFF,0xFF,0x03,0xFF,0x01,0xFF,0x83,0xFC,0x00,0x7F, +0xC7,0xF8,0x00,0x3F,0xC7,0xF0,0x00,0x1F,0xC7,0xE0, +0x00,0x0F,0xEF,0xE0,0x00,0x0F,0xEF,0xE0,0x00,0x07, +0xEF,0xC0,0x00,0x07,0xE1,0xC0,0x00,0x07,0xF0,0x00, +0x00,0x00,0xFC,0x00,0x00,0x01,0xF8,0x00,0x00,0x03, +0xF8,0x00,0x00,0x07,0xF0,0x00,0x00,0x0F,0xF0,0x00, +0x00,0x1F,0xE0,0x00,0x00,0x3F,0xC0,0x00,0x00,0x7F, +0x80,0x00,0x00,0xFF,0x00,0x00,0x01,0xFE,0x00,0x00, +0x03,0xFC,0x00,0x00,0x07,0xF8,0x00,0x00,0x07,0xF0, +0x00,0x00,0x0F,0xE0,0x00,0x00,0x0F,0xC0,0x02,0x00, +0x03,0xF8,0x00,0x58,0x00,0x7E,0x00,0x0B,0x00,0x00, +0x00,0x01,0x80,0x01,0xF8,0x00,0x00,0x0F,0xBF,0x1F, +0x28,0x80,0x00,0x00,0x03,0xFF,0xC0,0x00,0x00,0x00, +0x00,0x00,0x7F,0xFF,0xF8,0x00,0x00,0x00,0x00,0x07, +0xFF,0xFF,0xFE,0x00,0x00,0x00,0x00,0x3F,0xFF,0xFF, +0xFF,0x00,0x00,0x00,0x01,0xFF,0xFF,0xFF,0xFF,0x80, +0x00,0x00,0x0F,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x00, +0x3F,0xFF,0x00,0x1F,0xFF,0x80,0x00,0x00,0xFF,0xF0, +0x00,0x03,0xFF,0x80,0x00,0x03,0xFF,0x00,0x00,0x00, +0xFF,0x80,0x00,0x0F,0xF8,0x00,0x00,0x00,0xFF,0x80, +0x00,0x3F,0xC0,0x00,0x00,0x00,0x7F,0x80,0x00,0xFF, +0x00,0x00,0x00,0x00,0x7F,0x80,0x01,0xFC,0x00,0x00, +0x00,0x00,0x7F,0x00,0x07,0xF0,0x00,0x7E,0x00,0x00, +0x7F,0x00,0x1F,0xC0,0x07,0xFF,0x03,0xF0,0x7E,0x00, +0x3F,0x00,0x1F,0xFF,0x87,0xE0,0x7E,0x00,0xFC,0x00, +0xFF,0xFF,0x9F,0x80,0x7C,0x01,0xF0,0x03,0xFF,0xFF, +0xBF,0x00,0xFC,0x07,0xE0,0x0F,0xFF,0xFF,0xFE,0x00, +0xF8,0x0F,0x80,0x3F,0xF0,0x7F,0xFC,0x01,0xF0,0x3F, +0x00,0xFF,0x80,0x3F,0xF8,0x03,0xE0,0x7C,0x01,0xFC, +0x00,0x3F,0xE0,0x07,0xE0,0xF8,0x07,0xF0,0x00,0x3F, +0xC0,0x07,0xC3,0xF0,0x0F,0xE0,0x00,0x7F,0x80,0x0F, +0x87,0xC0,0x3F,0x80,0x00,0x7F,0x00,0x1F,0x0F,0x80, +0x7E,0x00,0x00,0xFC,0x00,0x3E,0x1F,0x01,0xFC,0x00, +0x01,0xF8,0x00,0x7C,0x7E,0x03,0xF0,0x00,0x03,0xF0, +0x00,0xF8,0xF8,0x07,0xE0,0x00,0x07,0xE0,0x01,0xF1, +0xF0,0x1F,0xC0,0x00,0x0F,0x80,0x03,0xE3,0xE0,0x3F, +0x00,0x00,0x1F,0x00,0x0F,0xC7,0xC0,0x7E,0x00,0x00, +0x3E,0x00,0x1F,0x0F,0x80,0xFC,0x00,0x00,0xFC,0x00, +0x3E,0x1F,0x01,0xF8,0x00,0x01,0xF8,0x00,0xFC,0x3E, +0x03,0xF0,0x00,0x03,0xE0,0x01,0xF0,0x7C,0x07,0xE0, +0x00,0x0F,0xC0,0x07,0xE0,0xF8,0x0F,0xC0,0x00,0x1F, +0x80,0x0F,0x81,0xF0,0x1F,0x80,0x00,0x7F,0x00,0x3F, +0x03,0xE0,0x3F,0x80,0x01,0xFC,0x00,0xFC,0x07,0xE0, +0x3F,0x00,0x07,0xF8,0x03,0xF8,0x07,0xC0,0x7F,0x00, +0x1F,0xF0,0x0F,0xE0,0x0F,0x80,0xFF,0x00,0x7F,0xE0, +0x7F,0x80,0x1F,0x80,0xFF,0x83,0xFF,0xE3,0xFE,0x00, +0x3F,0x00,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x3E,0x01, +0xFF,0xFF,0xBF,0xFF,0xE0,0x00,0x7E,0x01,0xFF,0xFE, +0x7F,0xFF,0x80,0x00,0x7E,0x01,0xFF,0xF8,0x7F,0xFE, +0x00,0x00,0xFC,0x00,0xFF,0xC0,0xFF,0xF0,0x00,0x00, +0xFC,0x00,0x7E,0x00,0x7F,0x00,0x0F,0xC1,0xFC,0x00, +0x00,0x00,0x00,0x00,0x3F,0x01,0xFC,0x00,0x00,0x00, +0x00,0x00,0xFE,0x03,0xFC,0x00,0x00,0x00,0x00,0x07, +0xF8,0x03,0xFE,0x00,0x00,0x00,0x00,0x1F,0xE0,0x03, +0xFF,0x00,0x00,0x00,0x00,0xFF,0x80,0x03,0xFF,0x80, +0x00,0x00,0x07,0xFE,0x00,0x03,0xFF,0xE0,0x00,0x00, +0x7F,0xF8,0x00,0x03,0xFF,0xFC,0x00,0x0F,0xFF,0xE0, +0x00,0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x01, +0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x00,0xFF,0xFF, +0xFF,0xFF,0xE0,0x00,0x00,0x00,0x3F,0xFF,0xFF,0xFF, +0x00,0x00,0x00,0x00,0x0F,0xFF,0xFF,0xF0,0x00,0x00, +0x00,0x00,0x00,0xFF,0xFC,0x00,0x00,0x00,0x0B,0x70, +0xF8,0x05,0xB0,0x00,0x00,0x7F,0xC0,0x00,0x09,0x00, +0x00,0x7F,0xF0,0x00,0x00,0x00,0x03,0xFF,0xE0,0x00, +0x00,0x00,0x0F,0xDF,0x80,0x00,0x40,0x00,0x0F,0xEF, +0xE0,0x00,0x00,0x00,0x3F,0x1F,0x80,0x00,0x00,0x01, +0xFC,0x7F,0x00,0x00,0x00,0x07,0xE1,0xFC,0x00,0x08, +0x00,0x07,0xF0,0x7F,0x00,0x00,0x00,0x1F,0x80,0xFC, +0x00,0x10,0x00,0x1F,0xC0,0x7F,0x00,0x00,0x00,0x7E, +0x00,0xFC,0x00,0x20,0x00,0x7F,0x00,0x7F,0x00,0x10, +0x00,0x7F,0x00,0x1F,0xC0,0x00,0x01,0xF8,0x00,0x3F, +0x00,0x20,0x01,0xFC,0x00,0x1F,0xC0,0x10,0x01,0xFC, +0x00,0x07,0xF0,0x00,0x07,0xFF,0xFF,0xFF,0xC0,0x20, +0x07,0xFF,0xFF,0xFF,0xF0,0x12,0x07,0xFF,0xFF,0xFF, +0xFC,0x08,0x07,0xF0,0x00,0x00,0x7F,0x00,0x3F,0xC0, +0x00,0x01,0xFE,0x10,0x1F,0xC0,0x00,0x00,0x7F,0x00, +0xFF,0x00,0x00,0x01,0xFE,0x20,0x7F,0x00,0x00,0x00, +0x7F,0x10,0x7F,0x00,0x00,0x00,0x1F,0xC3,0xFC,0x00, +0x00,0x00,0x7F,0xA1,0xFC,0x00,0x00,0x00,0x1F,0xCF, +0xF0,0x00,0x00,0x00,0x7F,0xBF,0x80,0x00,0x00,0x00, +0xFE,0x09,0x70,0x28,0x05,0xAF,0xFF,0xFF,0xF0,0x00, +0x3F,0xFF,0xFF,0xFC,0x00,0xFF,0xFF,0xFF,0xFC,0x03, +0xFF,0xFF,0xFF,0xF8,0x0F,0xFF,0xFF,0xFF,0xF0,0x3F, +0xFF,0xFF,0xFF,0xE0,0xFE,0x00,0x01,0xFF,0x83,0xF8, +0x00,0x01,0xFF,0x0F,0xE0,0x00,0x03,0xFC,0x3F,0x80, +0x00,0x07,0xF9,0x7F,0xC0,0x00,0x01,0xFC,0x7F,0x00, +0x00,0x07,0xE1,0xFC,0x00,0x00,0x3F,0x87,0xF0,0x00, +0x01,0xFC,0x1F,0xC0,0x00,0x0F,0xF0,0x7F,0x00,0x00, +0xFF,0x81,0xFF,0xFF,0xFF,0xF8,0x08,0xFF,0xFF,0xFF, +0xF8,0x03,0xFF,0xFF,0xFF,0xF8,0x0F,0xFF,0xFF,0xFF, +0xF8,0x3F,0xFF,0xFF,0xFF,0xF0,0xFE,0x00,0x00,0xFF, +0xE3,0xF8,0x00,0x00,0xFF,0x8F,0xE0,0x00,0x00,0xFF, +0x3F,0x80,0x00,0x01,0xFC,0xFE,0x00,0x00,0x07,0xFE, +0x7F,0x00,0x00,0x01,0xFD,0xFC,0x00,0x00,0x0F,0xF7, +0xF0,0x00,0x00,0x3F,0x9F,0xC0,0x00,0x01,0xFE,0x7F, +0x00,0x00,0x0F,0xF1,0xFC,0x00,0x01,0xFF,0xC7,0xFF, +0xFF,0xFF,0xFE,0x1F,0xFF,0xFF,0xFF,0xF0,0x7F,0xFF, +0xFF,0xFF,0x81,0xFF,0xFF,0xFF,0xFC,0x07,0xFF,0xFF, +0xFF,0xC0,0x1F,0xFF,0xFF,0xF0,0x00,0x0A,0xB2,0x1F, +0xF6,0x00,0x00,0x07,0xFE,0x00,0x00,0x00,0x07,0xFF, +0xF8,0x00,0x00,0x03,0xFF,0xFF,0xC0,0x00,0x01,0xFF, +0xFF,0xFE,0x00,0x00,0xFF,0xFF,0xFF,0xE0,0x00,0x3F, +0xFF,0xFF,0xFE,0x00,0x0F,0xFF,0x00,0xFF,0xE0,0x03, +0xFF,0x00,0x07,0xFE,0x00,0x7F,0x80,0x00,0x3F,0xC0, +0x1F,0xE0,0x00,0x03,0xFC,0x07,0xF8,0x00,0x00,0x7F, +0xC0,0xFE,0x00,0x00,0x07,0xF8,0x3F,0xC0,0x00,0x00, +0x7F,0x07,0xF0,0x00,0x00,0x0F,0xF0,0xFE,0x00,0x00, +0x00,0xFC,0x3F,0x80,0x00,0x00,0x18,0x12,0xFE,0x00, +0x00,0x00,0x00,0x6F,0xF0,0x00,0x00,0x00,0x01,0x7F, +0xC0,0x00,0x00,0x00,0x01,0xFC,0x00,0x00,0x00,0x00, +0x3F,0x80,0x00,0x00,0x0C,0x07,0xF0,0x00,0x00,0x01, +0xFC,0xFE,0x00,0x00,0x00,0x7F,0xC1,0xFC,0x00,0x00, +0x01,0xFC,0x3F,0xC0,0x00,0x00,0x7F,0x83,0xF8,0x00, +0x00,0x1F,0xE0,0x7F,0x80,0x00,0x03,0xFC,0x07,0xF8, +0x00,0x00,0xFF,0x00,0x7F,0x80,0x00,0x3F,0xE0,0x0F, +0xFC,0x00,0x1F,0xF8,0x00,0xFF,0xF0,0x1F,0xFE,0x00, +0x0F,0xFF,0xFF,0xFF,0x80,0x00,0xFF,0xFF,0xFF,0xE0, +0x00,0x0F,0xFF,0xFF,0xF8,0x00,0x00,0x7F,0xFF,0xFC, +0x00,0x00,0x03,0xFF,0xFE,0x00,0x00,0x00,0x07,0xFE, +0x00,0x00,0x0A,0x30,0x28,0x06,0x0F,0xFF,0xFF,0xF0, +0x00,0x07,0xFF,0xFF,0xFF,0x80,0x03,0xFF,0xFF,0xFF, +0xF0,0x01,0xFF,0xFF,0xFF,0xFE,0x00,0xFF,0xFF,0xFF, +0xFF,0x80,0x7F,0xFF,0xFF,0xFF,0xE0,0x3F,0x80,0x00, +0x7F,0xF8,0x1F,0xC0,0x00,0x07,0xFC,0x0F,0xE0,0x00, +0x01,0xFF,0x07,0xF0,0x00,0x00,0x7F,0xC3,0xF8,0x00, +0x00,0x1F,0xE1,0xFC,0x00,0x00,0x07,0xF9,0x1F,0xC0, +0x00,0x00,0x3F,0x95,0xFC,0x00,0x00,0x01,0xFD,0xBF, +0xC0,0x00,0x00,0x0F,0xF7,0xFC,0x00,0x00,0x00,0xFF, +0x3F,0xC0,0x00,0x00,0x1F,0xCF,0xE0,0x00,0x00,0x1F, +0xE8,0xFE,0x00,0x00,0x01,0xFC,0x7F,0x00,0x00,0x01, +0xFE,0x47,0xF0,0x00,0x00,0x3F,0xC3,0xF8,0x00,0x00, +0x7F,0xC1,0xFC,0x00,0x00,0x7F,0xC0,0xFE,0x00,0x01, +0xFF,0xE0,0x7F,0xFF,0xFF,0xFF,0xE0,0x3F,0xFF,0xFF, +0xFF,0xE0,0x1F,0xFF,0xFF,0xFF,0xC0,0x0F,0xFF,0xFF, +0xFF,0xC0,0x07,0xFF,0xFF,0xFF,0x80,0x03,0xFF,0xFF, +0xFC,0x00,0x00,0x09,0x30,0x28,0x05,0xB9,0xFF,0xFF, +0xFF,0xFF,0xDB,0xFC,0x00,0x00,0x00,0x1B,0xFC,0x00, +0x00,0x00,0x19,0xFF,0xFF,0xFF,0xFF,0x1B,0xFC,0x00, +0x00,0x00,0x1B,0xFC,0x00,0x00,0x00,0x11,0xFC,0x00, +0x00,0x00,0x19,0xFF,0xFF,0xFF,0xFF,0xE0,0x08,0x70, +0x28,0x05,0x39,0xFF,0xFF,0xFF,0xFF,0xDF,0xE0,0x00, +0x00,0x06,0xFF,0x00,0x00,0x00,0x33,0xFF,0xFF,0xFF, +0xE1,0xBF,0xC0,0x00,0x00,0x0D,0xFE,0x00,0x00,0x00, +0x6F,0xF0,0x00,0x00,0x01,0xFC,0x00,0x00,0x00,0x0B, +0x72,0x1F,0xF6,0x80,0x00,0x01,0xFF,0xC0,0x00,0x00, +0x00,0x7F,0xFF,0xE0,0x00,0x00,0x0F,0xFF,0xFF,0xE0, +0x00,0x00,0x7F,0xFF,0xFF,0xE0,0x00,0x07,0xFF,0xFF, +0xFF,0xC0,0x00,0x3F,0xFF,0xFF,0xFF,0x80,0x01,0xFF, +0xE0,0x0F,0xFF,0x00,0x0F,0xFC,0x00,0x07,0xFE,0x00, +0x7F,0xE0,0x00,0x07,0xFC,0x03,0xFE,0x00,0x00,0x0F, +0xF0,0x0F,0xF0,0x00,0x00,0x1F,0xE0,0x7F,0x80,0x00, +0x00,0x3F,0x81,0xFC,0x00,0x00,0x00,0xFE,0x0F,0xF0, +0x00,0x00,0x01,0xFC,0x3F,0x80,0x00,0x00,0x07,0xF0, +0xFE,0x00,0x00,0x00,0x1F,0x14,0xFE,0x00,0x00,0x00, +0x00,0x0B,0xFE,0x00,0x00,0x00,0x00,0x06,0x7F,0x00, +0x00,0x3F,0xFF,0xFE,0x5F,0xC0,0x00,0x00,0x00,0xFE, +0x7F,0x80,0x00,0x00,0x03,0xF8,0xFE,0x00,0x00,0x00, +0x0F,0xE3,0xFC,0x00,0x00,0x00,0x3F,0x87,0xF0,0x00, +0x00,0x00,0xFE,0x1F,0xE0,0x00,0x00,0x03,0xF8,0x3F, +0xC0,0x00,0x00,0x0F,0xE0,0xFF,0x80,0x00,0x00,0xFF, +0x81,0xFF,0x80,0x00,0x07,0xFE,0x03,0xFF,0x80,0x00, +0xFF,0xF8,0x07,0xFF,0xC0,0x1F,0xFF,0xC0,0x0F,0xFF, +0xFF,0xFF,0xFC,0x00,0x1F,0xFF,0xFF,0xFF,0xE0,0x00, +0x1F,0xFF,0xFF,0xFE,0x00,0x00,0x1F,0xFF,0xFF,0xE0, +0x00,0x00,0x1F,0xFF,0xFC,0x00,0x00,0x00,0x07,0xFF, +0x00,0x00,0x09,0xB0,0x28,0x06,0x1B,0xFC,0x00,0x00, +0x03,0xFE,0xFF,0x00,0x00,0x00,0xFF,0x7F,0xC0,0x00, +0x00,0x3F,0xE7,0xFF,0xFF,0xFF,0xFF,0xFB,0xFC,0x00, +0x00,0x03,0xFE,0xFF,0x00,0x00,0x00,0xFF,0xBF,0xC0, +0x00,0x00,0x3F,0xC7,0xF0,0x00,0x00,0x0F,0xE0,0x01, +0xF0,0x30,0x02,0x7B,0xFF,0x7F,0xEF,0xFD,0xFF,0xBF, +0xF7,0xFE,0x7F,0x06,0xF1,0x17,0xF4,0x5A,0x00,0x00, +0x1F,0xF4,0x00,0x00,0x3F,0xE8,0x00,0x00,0x7F,0xD0, +0x00,0x00,0xFF,0x80,0x00,0x01,0xFC,0x3C,0x00,0x1F, +0xE7,0xF8,0x00,0x3F,0xBF,0xC0,0x03,0xFB,0xFC,0x00, +0x7F,0x1F,0xC0,0x07,0xF1,0xFE,0x00,0xFF,0x1F,0xF8, +0x3F,0xE0,0xFF,0xFF,0xFE,0x0F,0xFF,0xFF,0xC0,0x7F, +0xFF,0xF8,0x03,0xFF,0xFF,0x00,0x0F,0xFF,0xC0,0x00, +0x1F,0xF0,0x00,0x0A,0x30,0x28,0x05,0xAF,0xE0,0x00, +0x00,0x7F,0xC7,0xF0,0x00,0x00,0x7F,0xC3,0xF8,0x00, +0x00,0x7F,0xC1,0xFC,0x00,0x00,0x7F,0xC0,0xFE,0x00, +0x00,0x7F,0xC0,0x7F,0x00,0x00,0x7F,0xC0,0x3F,0x80, +0x00,0x7F,0xC0,0x1F,0xC0,0x00,0x7F,0xC0,0x0F,0xE0, +0x00,0x7F,0xC0,0x07,0xF0,0x00,0x7F,0xC0,0x03,0xF8, +0x00,0x7F,0xC0,0x01,0xFC,0x00,0xFF,0xC0,0x00,0xFE, +0x00,0xFF,0xC0,0x00,0x7F,0x00,0xFF,0xC0,0x00,0x3F, +0x80,0xFF,0xC0,0x00,0x1F,0xC0,0xFF,0xC0,0x00,0x0F, +0xE0,0xFF,0xC0,0x00,0x07,0xF0,0xFF,0xC0,0x00,0x03, +0xF8,0xFF,0xC0,0x00,0x01,0xFC,0xFF,0xC0,0x00,0x00, +0xFE,0xFF,0xE0,0x00,0x00,0x7F,0xFF,0xF8,0x00,0x00, +0x3F,0xFF,0xFE,0x00,0x00,0x23,0xFF,0xFF,0xF0,0x00, +0x01,0xFF,0xF3,0xFC,0x00,0x00,0xFF,0xF1,0xFF,0x00, +0x00,0x7F,0xF0,0x7F,0xC0,0x00,0x3F,0xF0,0x1F,0xE0, +0x00,0x1F,0xF0,0x07,0xF8,0x00,0x0F,0xF0,0x03,0xFE, +0x00,0x07,0xF0,0x00,0xFF,0x80,0x03,0xF8,0x00,0x3F, +0xC0,0x01,0xFC,0x00,0x0F,0xF0,0x00,0xFE,0x00,0x07, +0xFC,0x00,0x7F,0x00,0x01,0xFF,0x00,0x3F,0x80,0x00, +0x7F,0x80,0x1F,0xC0,0x00,0x1F,0xE0,0x0F,0xE0,0x00, +0x0F,0xF8,0x07,0xF0,0x00,0x03,0xFE,0x03,0xF8,0x00, +0x00,0xFF,0x01,0xFC,0x00,0x00,0x3F,0xC0,0xFE,0x00, +0x00,0x1F,0xF0,0x7F,0x00,0x00,0x07,0xFC,0x3F,0x80, +0x00,0x01,0xFE,0x1F,0xC0,0x00,0x00,0x7F,0x8F,0xE0, +0x00,0x00,0x3F,0xE7,0xF0,0x00,0x00,0x0F,0xF8,0x07, +0xB0,0x28,0x04,0xBB,0xFC,0x00,0x00,0x06,0xFF,0x00, +0x00,0x01,0xBF,0xC0,0x00,0x00,0x6F,0xF0,0x00,0x00, +0x1B,0xFC,0x00,0x00,0x06,0xFF,0x00,0x00,0x01,0x9F, +0xFF,0xFF,0xFF,0x80,0x0B,0xF0,0x20,0x06,0xEF,0xFE, +0x00,0x00,0x00,0xFF,0xF3,0xFF,0xE0,0x00,0x00,0x3F, +0xFE,0x7F,0xFE,0x00,0x00,0x0F,0xFF,0xBF,0xFF,0x00, +0x00,0x1F,0xFF,0xCF,0xF7,0xE0,0x00,0x03,0xF7,0xF9, +0xFE,0x7E,0x00,0x00,0xFC,0xFF,0x3F,0xC7,0xE0,0x00, +0x3F,0x1F,0xDF,0xC7,0xF0,0x00,0x7F,0x1F,0xE7,0xF8, +0x7E,0x00,0x0F,0xC3,0xFC,0xFF,0x07,0xE0,0x03,0xF0, +0x7F,0x9F,0xE0,0x7E,0x00,0xFC,0x0F,0xEF,0xE0,0x7F, +0x01,0xFC,0x0F,0xF3,0xFC,0x07,0xE0,0x3F,0x01,0xFE, +0x7F,0x80,0x7E,0x0F,0xC0,0x3F,0xBF,0x80,0x7F,0x1F, +0xC0,0x3F,0xC7,0xF0,0x07,0xE3,0xF0,0x07,0xF7,0xF0, +0x07,0xE7,0xF0,0x07,0xF9,0xFE,0x00,0x7E,0xFC,0x00, +0xFF,0x5F,0xC0,0x07,0xFF,0x00,0x1F,0xE7,0xF8,0x00, +0x7F,0xC0,0x03,0xF8,0x09,0xB0,0x28,0x06,0x11,0xFE, +0x00,0x00,0x03,0xFB,0xFE,0x00,0x00,0x07,0xF8,0xFF, +0xC0,0x00,0x01,0xFD,0xFF,0xC0,0x00,0x03,0xFC,0x7F, +0xF8,0x00,0x00,0xFE,0xFF,0xF8,0x00,0x01,0xFE,0x3F, +0xFF,0x00,0x00,0x7F,0x7F,0xFF,0x00,0x00,0xFE,0xFF, +0xFF,0x00,0x01,0xFD,0xFD,0xFE,0x00,0x03,0xFB,0xFB, +0xFE,0x00,0x07,0xF7,0xF3,0xFE,0x00,0x0F,0xEF,0xE3, +0xFC,0x00,0x1F,0xDF,0xC7,0xFC,0x00,0x3F,0xBF,0x87, +0xFC,0x00,0x7F,0x7F,0x07,0xF8,0x00,0xFE,0xFE,0x0F, +0xF8,0x01,0xFD,0xFC,0x0F,0xF8,0x03,0xFB,0xF8,0x0F, +0xF0,0x07,0xF7,0xF0,0x1F,0xF0,0x0F,0xEF,0xE0,0x1F, +0xF0,0x1F,0xDF,0xC0,0x1F,0xE0,0x3F,0xBF,0x80,0x3F, +0xE0,0x7F,0x7F,0x00,0x3F,0xE0,0xFE,0xFE,0x00,0x3F, +0xC1,0xFD,0xFC,0x00,0x7F,0xC3,0xFB,0xF8,0x00,0x7F, +0xC7,0xF7,0xF0,0x00,0x7F,0x8F,0xEF,0xE0,0x00,0xFF, +0x9F,0xDF,0xC0,0x00,0xFF,0xBF,0xBF,0x80,0x00,0xFF, +0x7F,0x7F,0x00,0x01,0xFF,0xFE,0xFE,0x00,0x01,0xFF, +0xFE,0x3F,0x80,0x00,0x3F,0xFF,0x7F,0x00,0x00,0x3F, +0xFF,0x1F,0xC0,0x00,0x07,0xFF,0xBF,0x80,0x00,0x07, +0xFF,0x8F,0xE0,0x00,0x00,0xFF,0xDF,0xC0,0x00,0x00, +0xFF,0xC7,0xF0,0x00,0x00,0x1F,0xE0,0x0B,0xB2,0x1F, +0xF6,0x80,0x00,0x03,0xFF,0x00,0x00,0x00,0x00,0x7F, +0xFF,0xC0,0x00,0x00,0x03,0xFF,0xFF,0xF0,0x00,0x00, +0x1F,0xFF,0xFF,0xF0,0x00,0x00,0x7F,0xFF,0xFF,0xF8, +0x00,0x01,0xFF,0xFF,0xFF,0xF8,0x00,0x07,0xFF,0x80, +0x7F,0xF8,0x00,0x1F,0xF8,0x00,0x1F,0xF8,0x00,0x7F, +0xC0,0x00,0x0F,0xF8,0x01,0xFF,0x00,0x00,0x0F,0xF8, +0x03,0xFC,0x00,0x00,0x0F,0xF0,0x0F,0xF0,0x00,0x00, +0x0F,0xF0,0x1F,0xC0,0x00,0x00,0x0F,0xE0,0x7F,0x80, +0x00,0x00,0x1F,0xE0,0xFE,0x00,0x00,0x00,0x1F,0xC3, +0xFC,0x00,0x00,0x00,0x3F,0xD2,0xFE,0x00,0x00,0x00, +0x07,0xF3,0xF8,0x00,0x00,0x00,0x0F,0xFD,0xFE,0x00, +0x00,0x00,0x01,0xFE,0x7F,0x80,0x00,0x00,0x00,0x7F, +0x7F,0x00,0x00,0x00,0x01,0xFF,0x2F,0xE0,0x00,0x00, +0x00,0x7F,0x1F,0xE0,0x00,0x00,0x01,0xFE,0x1F,0xC0, +0x00,0x00,0x03,0xF8,0x3F,0xC0,0x00,0x00,0x0F,0xF0, +0x3F,0x80,0x00,0x00,0x1F,0xC0,0x7F,0x80,0x00,0x00, +0x7F,0x80,0x7F,0x80,0x00,0x01,0xFE,0x00,0xFF,0x80, +0x00,0x07,0xFC,0x00,0xFF,0x80,0x00,0x1F,0xF0,0x00, +0xFF,0xC0,0x00,0xFF,0xC0,0x00,0xFF,0xF0,0x0F,0xFF, +0x00,0x00,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0xFF,0xFF, +0xFF,0xF0,0x00,0x00,0x7F,0xFF,0xFF,0xC0,0x00,0x00, +0x7F,0xFF,0xFE,0x00,0x00,0x00,0x3F,0xFF,0xE0,0x00, +0x00,0x00,0x07,0xFE,0x00,0x00,0x00,0x09,0x70,0x28, +0x05,0xAF,0xFF,0xFF,0xFC,0x00,0x3F,0xFF,0xFF,0xFE, +0x00,0xFF,0xFF,0xFF,0xFE,0x03,0xFF,0xFF,0xFF,0xFE, +0x11,0xFF,0xFF,0xFF,0xFF,0x87,0xF0,0x00,0x03,0xFF, +0x1F,0xC0,0x00,0x03,0xFE,0x7F,0x00,0x00,0x07,0xF9, +0xFC,0x00,0x00,0x0F,0xE7,0xF0,0x00,0x00,0x3F,0xF7, +0xF8,0x00,0x00,0x0F,0xF1,0xFC,0x00,0x00,0x0F,0xE7, +0xF0,0x00,0x00,0x7F,0x9F,0xC0,0x00,0x07,0xFC,0x7F, +0x00,0x00,0x7F,0xF1,0xFF,0xFF,0xFF,0xFF,0x87,0xFF, +0xFF,0xFF,0xFC,0x1F,0xFF,0xFF,0xFF,0xE0,0x7F,0xFF, +0xFF,0xFF,0x01,0xFF,0xFF,0xFF,0xF0,0x07,0xFF,0xFF, +0xFC,0x00,0x37,0xF8,0x00,0x00,0x00,0x1B,0xFC,0x00, +0x00,0x00,0x0B,0xFE,0x00,0x00,0x00,0x00,0x0B,0xB5, +0x1F,0xC6,0x80,0x00,0x03,0xFE,0x00,0x00,0x00,0x00, +0x7F,0xFF,0xC0,0x00,0x00,0x03,0xFF,0xFF,0xE0,0x00, +0x00,0x1F,0xFF,0xFF,0xF0,0x00,0x00,0x7F,0xFF,0xFF, +0xF0,0x00,0x01,0xFF,0xFF,0xFF,0xF0,0x00,0x07,0xFF, +0x80,0xFF,0xF0,0x00,0x1F,0xF8,0x00,0x3F,0xF0,0x00, +0x7F,0xC0,0x00,0x1F,0xF0,0x01,0xFF,0x00,0x00,0x1F, +0xF0,0x03,0xFC,0x00,0x00,0x1F,0xE0,0x0F,0xF0,0x00, +0x00,0x1F,0xE0,0x1F,0xC0,0x00,0x00,0x1F,0xC0,0x7F, +0x00,0x00,0x00,0x3F,0xC0,0xFE,0x00,0x00,0x00,0x3F, +0x83,0xFC,0x00,0x00,0x00,0x7F,0x92,0xFE,0x00,0x00, +0x00,0x0F,0xE3,0xF8,0x00,0x00,0x00,0x1F,0xED,0xFE, +0x00,0x00,0x00,0x03,0xFA,0x7F,0x80,0x00,0x00,0x00, +0xFE,0x7F,0x00,0x00,0x00,0x03,0xF9,0x2F,0xE0,0x00, +0x00,0x00,0xFE,0x1F,0xE0,0x00,0x00,0x03,0xF8,0x1F, +0xC0,0x00,0x00,0x07,0xF0,0x3F,0xC0,0x00,0xE0,0x1F, +0xE0,0x3F,0x80,0x03,0xF0,0x3F,0x80,0x7F,0x80,0x07, +0xF8,0xFF,0x00,0x7F,0x80,0x0F,0xFB,0xFC,0x00,0xFF, +0x80,0x0F,0xFF,0xF0,0x00,0xFF,0x80,0x07,0xFF,0xC0, +0x00,0xFF,0xC0,0x03,0xFF,0x00,0x00,0xFF,0xE0,0x1F, +0xFC,0x00,0x00,0xFF,0xFF,0xFF,0xFE,0x00,0x00,0xFF, +0xFF,0xFF,0xFE,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0x00, +0x00,0x7F,0xFF,0xFD,0xFF,0x80,0x00,0x3F,0xFF,0xE1, +0xFF,0xC0,0x00,0x0F,0xFC,0x00,0xFF,0x80,0x00,0x00, +0x00,0x00,0x7E,0x00,0x00,0x00,0x00,0x00,0x3C,0x00, +0x00,0x00,0x00,0x00,0x10,0x0A,0xB0,0x28,0x06,0x0F, +0xFF,0xFF,0xFF,0x00,0x01,0xFF,0xFF,0xFF,0xFC,0x00, +0x3F,0xFF,0xFF,0xFF,0xE0,0x07,0xFF,0xFF,0xFF,0xFE, +0x00,0xFF,0xFF,0xFF,0xFF,0xE0,0x1F,0xFF,0xFF,0xFF, +0xFE,0x03,0xF8,0x00,0x00,0xFF,0xC0,0x7F,0x00,0x00, +0x07,0xFC,0x0F,0xE0,0x00,0x00,0x7F,0x82,0x3F,0x80, +0x00,0x00,0xFF,0x0B,0xFE,0x00,0x00,0x01,0xFC,0x1F, +0xC0,0x00,0x00,0x7F,0x83,0xF8,0x00,0x00,0x0F,0xE0, +0x7F,0x00,0x00,0x03,0xFC,0x0F,0xE0,0x00,0x00,0xFF, +0x01,0xFC,0x00,0x00,0xFF,0xE0,0x3F,0xFF,0xFF,0xFF, +0xF8,0x07,0xFF,0xFF,0xFF,0xFE,0x00,0xFF,0xFF,0xFF, +0xFF,0x00,0x1F,0xFF,0xFF,0xFF,0xC0,0x03,0xFF,0xFF, +0xFF,0xC0,0x00,0x7F,0xFF,0xFF,0xE0,0x00,0x0F,0xE0, +0x01,0xFF,0x00,0x01,0xFC,0x00,0x0F,0xF0,0x00,0x3F, +0x80,0x00,0xFF,0x00,0x07,0xF0,0x00,0x0F,0xF0,0x01, +0x1F,0xC0,0x00,0x1F,0xE0,0x03,0xF8,0x00,0x01,0xFE, +0x00,0x8F,0xE0,0x00,0x03,0xFC,0x01,0xFC,0x00,0x00, +0x3F,0xC0,0x47,0xF0,0x00,0x00,0x7F,0x81,0x1F,0xC0, +0x00,0x00,0xFF,0x03,0xF8,0x00,0x00,0x0F,0xF0,0x8F, +0xE0,0x00,0x00,0x1F,0xE1,0xFC,0x00,0x00,0x01,0xFE, +0x47,0xF0,0x00,0x00,0x03,0xFC,0xFE,0x00,0x00,0x00, +0x3F,0xC0,0x09,0xB2,0x1F,0xF5,0xA0,0x00,0x3F,0xF0, +0x00,0x00,0x03,0xFF,0xFE,0x00,0x00,0x3F,0xFF,0xFF, +0x00,0x00,0xFF,0xFF,0xFF,0x80,0x03,0xFF,0xFF,0xFF, +0x80,0x0F,0xFF,0xFF,0xFF,0x80,0x3F,0xF8,0x03,0xFF, +0x80,0xFF,0x80,0x01,0xFF,0x01,0xFE,0x00,0x01,0xFF, +0x03,0xF8,0x00,0x01,0xFE,0x0F,0xF0,0x00,0x01,0xFC, +0x1F,0xC0,0x00,0x03,0xFD,0x07,0xF0,0x00,0x00,0x7F, +0x41,0xFC,0x00,0x00,0x00,0x03,0xFC,0x00,0x00,0x00, +0x03,0xFC,0x00,0x00,0x00,0x07,0xFC,0x00,0x00,0x00, +0x07,0xFF,0x00,0x00,0x00,0x07,0xFF,0xE0,0x00,0x00, +0x07,0xFF,0xF8,0x00,0x00,0x07,0xFF,0xFF,0x00,0x00, +0x07,0xFF,0xFF,0xC0,0x00,0x01,0xFF,0xFF,0xE0,0x00, +0x00,0xFF,0xFF,0xF0,0x00,0x00,0x1F,0xFF,0xF0,0x00, +0x00,0x07,0xFF,0xF0,0x00,0x00,0x00,0xFF,0xF0,0x00, +0x00,0x00,0x3F,0xE0,0x00,0x00,0x00,0x3F,0xE0,0x00, +0x00,0x00,0x1F,0xC0,0x00,0x00,0x00,0x3F,0xE7,0xF8, +0x00,0x00,0x07,0xF7,0xF8,0x00,0x00,0x0F,0xE7,0xF0, +0x00,0x00,0x1F,0xCF,0xF0,0x00,0x00,0x3F,0x9F,0xE0, +0x00,0x00,0xFE,0x1F,0xE0,0x00,0x03,0xFC,0x3F,0xE0, +0x00,0x0F,0xF8,0x3F,0xF0,0x00,0x3F,0xE0,0x3F,0xFC, +0x03,0xFF,0x80,0x7F,0xFF,0xFF,0xFF,0x00,0x3F,0xFF, +0xFF,0xFC,0x00,0x3F,0xFF,0xFF,0xE0,0x00,0x3F,0xFF, +0xFF,0x80,0x00,0x0F,0xFF,0xFC,0x00,0x00,0x03,0xFF, +0x80,0x00,0x09,0xF0,0x08,0x05,0x39,0xFF,0xFF,0xFF, +0xFF,0xFF,0x40,0x00,0x3F,0x80,0x00,0x68,0x00,0x07, +0xF0,0x00,0x0D,0x00,0x00,0xFE,0x00,0x01,0xA0,0x00, +0x1F,0xC0,0x00,0x34,0x00,0x03,0xF8,0x00,0x06,0x80, +0x00,0x7F,0x00,0x00,0x09,0xB1,0x2F,0xF6,0x1B,0xFC, +0x00,0x00,0x03,0xFE,0xFF,0x00,0x00,0x00,0xFF,0xBF, +0xC0,0x00,0x00,0x3F,0xEF,0xF0,0x00,0x00,0x0F,0xF9, +0xFC,0x00,0x00,0x03,0xFB,0xF8,0x00,0x00,0x0F,0xF9, +0x7F,0x00,0x00,0x03,0xF8,0xFF,0x00,0x00,0x0F,0xF0, +0xFF,0x00,0x00,0x3F,0xC1,0xFF,0x00,0x00,0xFF,0x81, +0xFF,0x00,0x03,0xFE,0x03,0xFF,0xC0,0x3F,0xFC,0x03, +0xFF,0xFF,0xFF,0xF0,0x03,0xFF,0xFF,0xFF,0xC0,0x03, +0xFF,0xFF,0xFF,0x00,0x01,0xFF,0xFF,0xF8,0x00,0x00, +0xFF,0xFF,0xC0,0x00,0x00,0x3F,0xF8,0x00,0x00,0x0B, +0x70,0x00,0x05,0xAF,0xE0,0x00,0x00,0x00,0x3F,0xBF, +0xC0,0x00,0x00,0x01,0xFF,0x0F,0xE0,0x00,0x00,0x00, +0xFE,0x3F,0xC0,0x00,0x00,0x07,0xFA,0x0F,0xE0,0x00, +0x00,0x03,0xF8,0x1F,0xC0,0x00,0x00,0x1F,0xE0,0x7F, +0x00,0x00,0x00,0x7F,0x01,0xFE,0x00,0x00,0x03,0xFC, +0x40,0x7F,0x00,0x00,0x01,0xFC,0x01,0xFE,0x00,0x00, +0x0F,0xF0,0x80,0x7F,0x00,0x00,0x07,0xF0,0x40,0x1F, +0xC0,0x00,0x07,0xF0,0x00,0x7F,0x80,0x00,0x3F,0xC0, +0x80,0x1F,0xC0,0x00,0x1F,0xC0,0x48,0x07,0xF0,0x00, +0x1F,0xC0,0x20,0x01,0xFC,0x00,0x1F,0xC0,0x00,0x07, +0xF0,0x00,0xFF,0x00,0x40,0x01,0xFC,0x00,0x7F,0x00, +0x24,0x00,0x7F,0x00,0x7F,0x00,0x10,0x00,0x1F,0xC0, +0x7F,0x00,0x00,0x00,0x3F,0x03,0xF8,0x00,0x20,0x00, +0x1F,0xC1,0xFC,0x00,0x10,0x00,0x07,0xF1,0xFC,0x00, +0x00,0x00,0x0F,0xC7,0xE0,0x00,0x20,0x00,0x07,0xF7, +0xF0,0x00,0x00,0x00,0x0F,0xDF,0x80,0x00,0x40,0x00, +0x07,0xFF,0xC0,0x00,0x20,0x00,0x01,0xFF,0xC0,0x00, +0x10,0x00,0x00,0x7F,0xC0,0x00,0x00,0x10,0x70,0x00, +0x08,0x4F,0xE0,0x00,0x00,0xFF,0x80,0x00,0x03,0xFB, +0xFC,0x00,0x00,0x3F,0xE0,0x00,0x01,0xFF,0x2F,0xE0, +0x00,0x03,0xFF,0x80,0x00,0x0F,0xE3,0xF8,0x00,0x01, +0xFF,0xF0,0x00,0x03,0xFA,0x4F,0xE0,0x00,0x0F,0xDF, +0x80,0x00,0x3F,0x83,0xF8,0x00,0x07,0xE3,0xF0,0x00, +0x0F,0xE4,0x0F,0xE0,0x00,0x3F,0x1F,0x80,0x00,0xFE, +0x03,0xF8,0x00,0x1F,0xC7,0xE0,0x00,0x3F,0x80,0xFE, +0x00,0x07,0xE0,0xFC,0x00,0x0F,0xE0,0x1F,0x80,0x01, +0xF8,0x3F,0x00,0x03,0xF0,0x07,0xF0,0x00,0x7E,0x0F, +0xC0,0x01,0xFC,0x01,0xFC,0x00,0x3F,0x83,0xF8,0x00, +0x7F,0x00,0x7F,0x00,0x0F,0xC0,0x7E,0x00,0x1F,0xC0, +0x0F,0xC0,0x03,0xF0,0x1F,0x80,0x07,0xE0,0x03,0xF8, +0x00,0xFC,0x07,0xE0,0x03,0xF8,0x20,0x1F,0xC0,0x0F, +0xC0,0x1F,0x80,0x1F,0xC0,0x03,0xF0,0x03,0xF0,0x07, +0xE0,0x07,0xE0,0x00,0xFC,0x01,0xFC,0x01,0xFC,0x03, +0xF8,0x10,0x07,0xF0,0x0F,0xC0,0x07,0xE0,0x1F,0xC0, +0x00,0xFC,0x03,0xF0,0x01,0xF8,0x07,0xE0,0x00,0x3F, +0x01,0xF8,0x00,0x3F,0x01,0xF8,0x08,0x01,0xFC,0x0F, +0xC0,0x01,0xF8,0x1F,0xC0,0x00,0x3F,0x07,0xF0,0x00, +0x7E,0x07,0xE0,0x00,0x0F,0xC1,0xF8,0x00,0x0F,0xC1, +0xF8,0x04,0x00,0x7F,0x0F,0xC0,0x00,0x7E,0x1F,0xC0, +0x00,0x1F,0xC7,0xF0,0x00,0x0F,0xC7,0xF0,0x08,0x00, +0x7E,0x3F,0x00,0x00,0x7E,0x3F,0x00,0x00,0x1F,0xCF, +0xC0,0x00,0x1F,0x9F,0xC0,0x00,0x07,0xF7,0xE0,0x00, +0x03,0xF7,0xF0,0x04,0x00,0x1F,0xBF,0x00,0x00,0x1F, +0xBF,0x00,0x00,0x07,0xFF,0xC0,0x00,0x07,0xFF,0xC0, +0x00,0x01,0xFF,0xE0,0x00,0x00,0xFF,0xF0,0x02,0x00, +0x07,0xFF,0x00,0x00,0x07,0xFF,0x00,0x10,0x00,0x3F, +0xF0,0x00,0x00,0x1F,0xF8,0x00,0x00,0x07,0xFC,0x00, +0x00,0x07,0xFC,0x00,0x00,0x0A,0xF0,0xF8,0x05,0x63, +0xFE,0x00,0x00,0x0F,0xF8,0x1F,0xE0,0x00,0x01,0xFF, +0x00,0xFF,0x00,0x00,0x1F,0xE0,0x0F,0xF8,0x00,0x03, +0xFE,0x00,0x7F,0x80,0x00,0x7F,0xC0,0x03,0xFC,0x00, +0x07,0xF8,0x00,0x3F,0xE0,0x00,0xFF,0x80,0x01,0xFE, +0x00,0x1F,0xF0,0x00,0x0F,0xF0,0x01,0xFE,0x00,0x00, +0xFF,0x80,0x3F,0xE0,0x00,0x07,0xF8,0x07,0xFC,0x00, +0x00,0x3F,0xC0,0x7F,0x80,0x00,0x01,0xFE,0x0F,0xF8, +0x00,0x00,0x1F,0xE1,0xFF,0x00,0x00,0x00,0xFF,0x1F, +0xE0,0x00,0x00,0x07,0xFB,0xFE,0x00,0x00,0x00,0x7F, +0xFF,0xC0,0x00,0x00,0x03,0xFF,0xF8,0x00,0x00,0x00, +0x1F,0xFF,0x80,0x00,0x00,0x01,0xFF,0xF0,0x00,0x00, +0x00,0x0F,0xFE,0x00,0x01,0x20,0x00,0x0F,0xF8,0x00, +0x00,0x00,0x01,0xFF,0xC0,0x00,0x20,0x00,0x07,0xFF, +0xC0,0x00,0x00,0x00,0xFF,0xFE,0x00,0x00,0x00,0x1F, +0xFF,0xF0,0x00,0x00,0x01,0xFE,0xFF,0x00,0x00,0x00, +0x3F,0xC7,0xF8,0x00,0x00,0x07,0xFC,0x7F,0xC0,0x00, +0x00,0xFF,0x83,0xFC,0x00,0x00,0x0F,0xF0,0x1F,0xE0, +0x00,0x01,0xFF,0x00,0xFF,0x00,0x00,0x3F,0xE0,0x0F, +0xF0,0x00,0x03,0xFC,0x00,0x7F,0x80,0x00,0x7F,0xC0, +0x03,0xFC,0x00,0x0F,0xF8,0x00,0x3F,0xE0,0x00,0xFF, +0x00,0x01,0xFE,0x00,0x1F,0xF0,0x00,0x0F,0xF0,0x03, +0xFE,0x00,0x00,0xFF,0x80,0x3F,0xC0,0x00,0x07,0xF8, +0x07,0xFC,0x00,0x00,0x3F,0xC0,0xFF,0x80,0x00,0x03, +0xFE,0x0F,0xF0,0x00,0x00,0x1F,0xE1,0xFF,0x00,0x00, +0x00,0xFF,0x3F,0xE0,0x00,0x00,0x0F,0xF8,0x0A,0xF0, +0x08,0x05,0xAF,0xF0,0x00,0x00,0x01,0xFE,0x7F,0x80, +0x00,0x00,0x3F,0xD0,0x7F,0x80,0x00,0x00,0xFF,0x03, +0xFC,0x00,0x00,0x1F,0xE2,0x03,0xFC,0x00,0x00,0x7F, +0x80,0x1F,0xE0,0x00,0x0F,0xF0,0x40,0x1F,0xE0,0x00, +0x3F,0xC0,0x00,0xFF,0x00,0x07,0xF8,0x00,0x0F,0xF8, +0x00,0xFF,0x80,0x00,0x7F,0x80,0x0F,0xF0,0x00,0x03, +0xFC,0x01,0xFE,0x00,0x00,0x3F,0xE0,0x3F,0xE0,0x00, +0x01,0xFE,0x03,0xFC,0x00,0x00,0x0F,0xF0,0x7F,0x80, +0x00,0x00,0xFF,0x0F,0xF8,0x00,0x00,0x07,0xF8,0xFF, +0x00,0x08,0x00,0x07,0xFB,0xFC,0x00,0x00,0x00,0x3F, +0xFF,0x80,0x01,0x00,0x00,0x3F,0xFE,0x00,0x00,0x00, +0x01,0xFF,0xC0,0x00,0x20,0x00,0x01,0xFF,0x00,0x00, +0x68,0x00,0x01,0xFC,0x00,0x00,0xD0,0x00,0x03,0xF8, +0x00,0x01,0xA0,0x00,0x07,0xF0,0x00,0x00,0x09,0xB0, +0x08,0x05,0x38,0x3F,0xFF,0xFF,0xFF,0xF0,0x00,0x00, +0x00,0x3F,0xE0,0x00,0x00,0x00,0xFF,0x80,0x00,0x00, +0x03,0xFE,0x00,0x00,0x00,0x0F,0xF8,0x00,0x00,0x00, +0x1F,0xE0,0x00,0x00,0x00,0x7F,0xC0,0x00,0x00,0x01, +0xFF,0x00,0x00,0x00,0x07,0xFC,0x04,0x00,0x00,0x03, +0xFE,0x00,0x00,0x00,0x0F,0xF8,0x00,0x00,0x00,0x3F, +0xE0,0x00,0x00,0x00,0xFF,0x80,0x00,0x00,0x01,0xFE, +0x00,0x00,0x00,0x07,0xFC,0x00,0x00,0x00,0x1F,0xF0, +0x00,0x00,0x00,0x7F,0xC0,0x00,0x00,0x01,0xFF,0x00, +0x00,0x00,0x03,0xFC,0x00,0x00,0x00,0x0F,0xF8,0x00, +0x00,0x00,0x3F,0xE0,0x00,0x00,0x00,0xFF,0x80,0x00, +0x10,0x00,0x7F,0xC0,0x00,0x00,0x01,0xFF,0x00,0x00, +0x00,0x07,0xFC,0x00,0x00,0x00,0x1F,0xF0,0x00,0x00, +0x00,0x3F,0xC0,0x00,0x00,0x00,0xFF,0x80,0x00,0x00, +0x03,0xFE,0x00,0x00,0x00,0x0F,0xF8,0x00,0x00,0x00, +0x3F,0xE0,0x00,0x00,0x00,0x7F,0x80,0x00,0x00,0x01, +0xFF,0x00,0x00,0x00,0x07,0xFC,0x00,0x00,0x00,0x1F, +0xF0,0x00,0x00,0x00,0x67,0xFF,0xFF,0xFF,0xFF,0xE0, +0x03,0x7D,0x27,0x32,0x79,0xFF,0xFD,0xFC,0x06,0xFE, +0x03,0x7F,0x01,0xBF,0x80,0xDF,0xC0,0x6F,0xE0,0x37, +0xF0,0x19,0xFF,0xF0,0x04,0xF0,0x08,0x02,0x71,0xF0, +0x00,0x25,0xF0,0x00,0x1F,0x80,0x04,0x9F,0x00,0x09, +0x1F,0x00,0x01,0xF8,0x01,0x01,0xF0,0x00,0x1F,0x80, +0x24,0x1F,0x00,0x48,0x1F,0x00,0x01,0xF8,0x09,0x01, +0xF0,0x12,0x01,0xF0,0x00,0x1F,0x82,0x40,0x1F,0x04, +0x80,0x1F,0x00,0x01,0xF8,0x80,0x01,0xF0,0x00,0x1F, +0x92,0x00,0x1F,0x24,0x00,0x1F,0x00,0x01,0xF8,0x00, +0x0F,0x80,0x03,0x7D,0x17,0x32,0x79,0xFF,0xFD,0x01, +0xFE,0x80,0xFF,0x40,0x7F,0xA0,0x3F,0xD0,0x1F,0xE8, +0x0F,0xF4,0x07,0xF9,0xFF,0xF0,0x06,0xDA,0x09,0x73, +0xC0,0x01,0xF0,0x01,0x20,0x07,0xF0,0x02,0x00,0x1F, +0xF0,0x04,0x00,0x7D,0xF0,0x00,0x0F,0xDF,0x80,0x80, +0x1F,0x1F,0x01,0x00,0x7C,0x1F,0x00,0x0F,0xC1,0xF8, +0x00,0xF8,0x0F,0x82,0x03,0xF0,0x1F,0x80,0x3E,0x00, +0xF8,0x07,0xE0,0x0F,0xC0,0x7C,0x00,0x7C,0x41,0xF8, +0x00,0xFC,0x97,0xE0,0x00,0xFC,0xFC,0x00,0x07,0xE0, +0x09,0x86,0xFF,0x34,0xB9,0xFF,0xFF,0xFF,0xFF,0xF8, +0x03,0x09,0x1A,0x72,0xCF,0xF0,0x3F,0xC0,0xFE,0x03, +0xF8,0x0F,0xC0,0x3E,0x00,0xF8,0x03,0xC0,0x0F,0x07, +0xE5,0x1F,0xF4,0xA0,0x01,0xFF,0x80,0x00,0x0F,0xFF, +0xF0,0x00,0x3F,0xFF,0xFC,0x00,0x7F,0xFF,0xFE,0x00, +0xFF,0xFF,0xFE,0x01,0xFF,0xFF,0xFF,0x03,0xFF,0x01, +0xFF,0x03,0xF8,0x00,0x7F,0x83,0xF8,0x00,0x3F,0x87, +0xF0,0x00,0x1F,0x87,0xE0,0x00,0x1F,0x80,0xE0,0x00, +0x1F,0x90,0x00,0x00,0x03,0xF0,0x00,0x00,0x0F,0xF0, +0x00,0x00,0xFF,0xF0,0x00,0x7F,0xFF,0xF0,0x07,0xFF, +0xFF,0xF0,0x0F,0xFF,0xFF,0xF0,0x3F,0xFF,0xFF,0xF0, +0x7F,0xFF,0xF3,0xF0,0x7F,0xFE,0x03,0xF0,0xFF,0x80, +0x03,0xF0,0xFE,0x00,0x03,0xF1,0xFC,0x00,0x03,0xF2, +0x3F,0x00,0x00,0xFE,0x3F,0x00,0x01,0xFE,0x3F,0x80, +0x03,0xFE,0x3F,0x80,0x07,0xFE,0x1F,0xE0,0x3F,0xFE, +0x1F,0xFF,0xFF,0xFE,0x1F,0xFF,0xFF,0xFF,0x0F,0xFF, +0xFE,0x7F,0x07,0xFF,0xFC,0x3F,0x01,0xFF,0xF0,0x1F, +0x80,0x7F,0x80,0x00,0x00,0x07,0xB1,0x27,0xF4,0xBB, +0xF8,0x00,0x00,0x05,0xFE,0x00,0x00,0x00,0xFC,0x0F, +0xE0,0x01,0xF8,0x7F,0xF8,0x03,0xF1,0xFF,0xF8,0x07, +0xE7,0xFF,0xFC,0x0F,0xDF,0xFF,0xFC,0x1F,0xFF,0xFF, +0xF8,0x3F,0xFC,0x0F,0xF8,0x7F,0xF0,0x07,0xF8,0xFF, +0x80,0x07,0xF1,0xFE,0x00,0x07,0xE3,0xFC,0x00,0x0F, +0xE8,0xFE,0x00,0x01,0xF9,0xFC,0x00,0x03,0xFE,0xFE, +0x00,0x00,0x7F,0x1F,0x80,0x00,0x1F,0xBF,0x00,0x00, +0x7F,0x8F,0xE0,0x00,0x1F,0x9F,0xC0,0x00,0x7F,0x3F, +0xC0,0x00,0xFC,0x7F,0xC0,0x03,0xF8,0xFF,0xC0,0x0F, +0xE1,0xFF,0xE0,0x7F,0xC3,0xFF,0xFF,0xFF,0x07,0xEF, +0xFF,0xFC,0x0F,0xCF,0xFF,0xF0,0x1F,0x8F,0xFF,0xC0, +0x3F,0x0F,0xFE,0x00,0x00,0x07,0xF0,0x00,0x07,0xE5, +0x1F,0xF4,0x40,0x00,0xFF,0x00,0x00,0x07,0xFF,0xE0, +0x00,0x1F,0xFF,0xF8,0x00,0x3F,0xFF,0xFC,0x00,0x7F, +0xFF,0xFE,0x00,0xFF,0xFF,0xFF,0x01,0xFF,0x81,0xFF, +0x03,0xFE,0x00,0x7F,0x83,0xF8,0x00,0x3F,0x90,0xFE, +0x00,0x03,0xF8,0xFC,0x00,0x01,0xC0,0xFC,0x00,0x00, +0x01,0xFC,0x00,0x00,0x03,0x7F,0x00,0x00,0x00,0x47, +0xE0,0x00,0x00,0x07,0xF0,0x00,0x03,0x83,0xF0,0x00, +0x03,0xF3,0xF0,0x00,0x07,0xF3,0xF8,0x00,0x07,0xE3, +0xF8,0x00,0x0F,0xE1,0xFC,0x00,0x0F,0xE1,0xFE,0x00, +0x3F,0xC0,0xFF,0xC0,0xFF,0xC0,0x7F,0xFF,0xFF,0x80, +0x3F,0xFF,0xFF,0x00,0x1F,0xFF,0xFE,0x00,0x0F,0xFF, +0xFC,0x00,0x03,0xFF,0xF0,0x00,0x00,0x7F,0x80,0x00, +0x07,0xB1,0x17,0xF4,0xBA,0x00,0x00,0x01,0xFD,0x80, +0x00,0x00,0x7E,0x00,0x1F,0xC0,0xFC,0x01,0xFF,0xE1, +0xF8,0x07,0xFF,0xE3,0xF0,0x3F,0xFF,0xE7,0xE0,0xFF, +0xFF,0xEF,0xC1,0xFF,0xFF,0xFF,0x87,0xFC,0x0F,0xFF, +0x1F,0xE0,0x07,0xFE,0x3F,0x80,0x07,0xFE,0x1F,0xC0, +0x00,0xFF,0x87,0xE0,0x00,0x1F,0xDF,0x80,0x00,0x3F, +0xEF,0xE0,0x00,0x07,0xF1,0xF8,0x00,0x01,0xFB,0xF8, +0x00,0x03,0xF8,0x7E,0x00,0x01,0xFC,0xFE,0x00,0x07, +0xF8,0xFC,0x00,0x0F,0xF1,0xFC,0x00,0x3F,0xE3,0xFC, +0x00,0xFF,0xC3,0xFE,0x07,0xFF,0x83,0xFF,0xFF,0xFF, +0x03,0xFF,0xFF,0x7E,0x03,0xFF,0xFC,0xFC,0x03,0xFF, +0xF1,0xF8,0x03,0xFF,0xC3,0xF0,0x00,0xFE,0x00,0x00, +0x08,0x25,0x17,0xF4,0xA0,0x00,0xFF,0x00,0x00,0x03, +0xFF,0xF0,0x00,0x07,0xFF,0xFE,0x00,0x07,0xFF,0xFF, +0x80,0x07,0xFF,0xFF,0xE0,0x07,0xFF,0xFF,0xF8,0x07, +0xFE,0x03,0xFE,0x03,0xF8,0x00,0x7F,0x83,0xF8,0x00, +0x1F,0xC1,0xF8,0x00,0x07,0xE4,0x3F,0x00,0x00,0x3F, +0x1F,0x00,0x00,0x0F,0x9F,0x80,0x00,0x07,0xF9,0xFF, +0xFF,0xFF,0xFF,0x3F,0x80,0x00,0x00,0x0F,0xE0,0x00, +0x00,0x03,0xF0,0x00,0x00,0x01,0xF8,0x00,0x00,0xE0, +0xFE,0x00,0x00,0xFE,0x7F,0x80,0x00,0xFE,0x1F,0xE0, +0x00,0x7F,0x0F,0xF8,0x00,0xFF,0x03,0xFF,0x01,0xFF, +0x80,0xFF,0xFF,0xFF,0x80,0x3F,0xFF,0xFF,0x80,0x0F, +0xFF,0xFF,0x80,0x03,0xFF,0xFF,0x80,0x00,0x7F,0xFF, +0x00,0x00,0x07,0xFC,0x00,0x00,0x05,0x31,0x08,0x02, +0x60,0x01,0xFE,0x00,0x3F,0xF8,0x07,0xFF,0xE0,0x0F, +0xFF,0xC0,0xFF,0xFE,0x07,0xF8,0x00,0x3F,0x80,0x60, +0x3F,0x00,0x67,0xFF,0xFE,0x68,0x3F,0x00,0x68,0x3F, +0x00,0x68,0x3F,0x00,0x68,0x3F,0x00,0x01,0xF8,0x00, +0x07,0xB2,0x17,0x24,0xA0,0x01,0xFC,0x00,0x00,0x1F, +0xFE,0x1F,0x80,0xFF,0xFF,0x3F,0x03,0xFF,0xFF,0x7F, +0x01,0xFF,0xFF,0xFF,0x87,0xFC,0x0F,0xFF,0x1F,0xE0, +0x07,0xFE,0x3F,0x80,0x07,0xFE,0x1F,0xC0,0x00,0xFF, +0x87,0xE0,0x00,0x1F,0xDF,0x80,0x00,0x3F,0xEF,0xE0, +0x00,0x07,0xF1,0xF8,0x00,0x01,0xFC,0x3F,0x00,0x00, +0xFE,0x7E,0x00,0x03,0xFC,0xFE,0x00,0x07,0xF8,0xFE, +0x00,0x1F,0xF1,0xFE,0x00,0x7F,0xE1,0xFF,0x03,0xFF, +0xE0,0x3F,0xFF,0xFF,0xF0,0x3F,0xFF,0xF7,0xE0,0x3F, +0xFF,0xCF,0xC0,0x1F,0xFF,0x1F,0x80,0x07,0xF0,0x3F, +0x90,0x00,0x00,0x0F,0xCE,0x00,0x00,0x3F,0x1F,0x80, +0x00,0x7E,0x3F,0x80,0x01,0xFC,0x7F,0x00,0x07,0xF0, +0x7F,0xC0,0x3F,0xE0,0xFF,0xFF,0xFF,0x80,0xFF,0xFF, +0xFE,0x00,0xFF,0xFF,0xF8,0x00,0xFF,0xFF,0xE0,0x00, +0x7F,0xFF,0x00,0x00,0x1F,0xF0,0x00,0x06,0xF0,0x28, +0x04,0xBB,0xF8,0x00,0x00,0x2F,0xF0,0x00,0x00,0x3F, +0x03,0xF8,0x03,0xF0,0xFF,0xF0,0x3F,0x1F,0xFF,0x83, +0xF3,0xFF,0xFC,0x3F,0x7F,0xFF,0xE3,0xFF,0xFF,0xFF, +0x3F,0xFC,0x1F,0xF3,0xFF,0x00,0x7F,0x47,0xF8,0x00, +0x7F,0x8F,0xE0,0x00,0x7F,0xBF,0x80,0x00,0xFF,0x7F, +0x00,0x01,0xFE,0xFE,0x00,0x03,0xF9,0xFC,0x00,0x07, +0xE0,0x01,0xB0,0x28,0x01,0xF9,0xFE,0x81,0xBF,0xEF, +0xFB,0xFE,0xFF,0xBF,0x80,0x03,0x7E,0xEF,0x21,0xF8, +0x03,0xFD,0x00,0x06,0x80,0xFF,0x40,0x7F,0xA0,0x3F, +0xD0,0x1F,0xE8,0x0F,0xF0,0x07,0xE0,0x3F,0x81,0xFF, +0x0F,0xFE,0x3F,0xF1,0xFF,0xC7,0xFE,0x0F,0xE0,0x07, +0x70,0x20,0x04,0x5B,0xF8,0x00,0x00,0x0C,0xFC,0x00, +0x00,0x03,0xF0,0x00,0x7F,0x8F,0xC0,0x03,0xFC,0x3F, +0x00,0x1F,0xE0,0xFC,0x00,0xFF,0x03,0xF0,0x07,0xF8, +0x0F,0xC0,0x3F,0xC0,0x3F,0x01,0xFE,0x00,0xFC,0x0F, +0xF0,0x03,0xF0,0x7F,0x80,0x0F,0xC3,0xFC,0x00,0x3F, +0x1F,0xE0,0x00,0xFC,0xFF,0x00,0x03,0xF7,0xF8,0x00, +0x0F,0xFF,0xE0,0x00,0x47,0xFF,0xF8,0x00,0x1F,0xFF, +0xF0,0x00,0x7F,0xEF,0xE0,0x01,0xFF,0x3F,0x80,0x07, +0xF8,0x7F,0x00,0x1F,0xC0,0xFE,0x00,0x7E,0x03,0xF8, +0x01,0xF8,0x07,0xF0,0x07,0xE0,0x0F,0xC0,0x1F,0x80, +0x3F,0x80,0x8F,0xC0,0x0F,0xE0,0x3F,0x00,0x1F,0xC1, +0x1F,0x80,0x07,0xF0,0x7E,0x00,0x0F,0xE2,0x3F,0x00, +0x03,0xF8,0xFC,0x00,0x07,0xF3,0xF0,0x00,0x0F,0xE0, +0x01,0xB0,0x28,0x01,0xFB,0xFE,0xFF,0xBF,0xEF,0xFB, +0xFE,0xFF,0x9F,0x80,0x0C,0x24,0x20,0x07,0x20,0x00, +0x7F,0x00,0x03,0xF8,0x07,0xE0,0xFF,0xE0,0x0F,0xFF, +0x03,0xF1,0xFF,0xF8,0x0F,0xFF,0xE1,0xF9,0xFF,0xFE, +0x0F,0xFF,0xF8,0xFD,0xFF,0xFF,0x8F,0xFF,0xFC,0x7E, +0xFF,0xFF,0xEF,0xFF,0xFF,0x3F,0xFC,0x0F,0xFF,0xE0, +0xFF,0x9F,0xF8,0x03,0xFF,0xC0,0x1F,0xEF,0xF8,0x00, +0xFF,0x80,0x07,0xF7,0xF8,0x00,0x7F,0xC0,0x03,0xFC, +0x7F,0x00,0x03,0xF8,0x00,0x1F,0xBF,0x80,0x01,0xF8, +0x00,0x0F,0xF7,0xF0,0x00,0x1F,0x80,0x00,0xFF,0x7F, +0x00,0x01,0xF8,0x00,0x0F,0xF7,0xF0,0x00,0x1F,0x80, +0x00,0xFE,0x3F,0x00,0x01,0xF8,0x00,0x0F,0xC0,0x06, +0xE4,0x28,0x04,0xA0,0x00,0x7F,0x00,0xFC,0x3F,0xFC, +0x0F,0xC7,0xFF,0xF0,0xFC,0xFF,0xFF,0x8F,0xDF,0xFF, +0xF8,0xFF,0xFF,0xFF,0xCF,0xFF,0x07,0xFC,0xFF,0xC0, +0x1F,0xD1,0xFE,0x00,0x1F,0xE3,0xF8,0x00,0x1F,0xEF, +0xE0,0x00,0x3F,0xDF,0xC0,0x00,0x7F,0xBF,0x80,0x00, +0xFE,0x7F,0x00,0x01,0xF8,0x07,0xE5,0x1F,0xF4,0xA0, +0x01,0xFF,0x00,0x00,0x07,0xFF,0xC0,0x00,0x1F,0xFF, +0xF0,0x00,0x3F,0xFF,0xF8,0x00,0x7F,0xFF,0xFC,0x00, +0xFF,0xFF,0xFE,0x01,0xFF,0x83,0xFF,0x03,0xFE,0x00, +0xFF,0x83,0xF8,0x00,0x3F,0x90,0xFE,0x00,0x03,0xFA, +0x1F,0x80,0x00,0x3F,0x3F,0x80,0x00,0x3F,0xEF,0xE0, +0x00,0x03,0xF8,0xFC,0x00,0x00,0x7E,0xFE,0x00,0x00, +0xFF,0x0F,0xC0,0x00,0x1F,0xA1,0xFC,0x00,0x07,0xF0, +0xFE,0x00,0x0F,0xE0,0xFF,0x00,0x3F,0xE0,0x7F,0xC0, +0x7F,0xC0,0x3F,0xFF,0xFF,0x80,0x3F,0xFF,0xFF,0x00, +0x0F,0xFF,0xFE,0x00,0x07,0xFF,0xFC,0x00,0x03,0xFF, +0xF0,0x00,0x00,0x7F,0xC0,0x00,0x07,0xB1,0x27,0x34, +0xA0,0x00,0xFE,0x00,0x1F,0x87,0xFF,0x80,0x3F,0x1F, +0xFF,0xC0,0x7E,0x7F,0xFF,0xC1,0x1F,0xBF,0xFF,0xF8, +0x3F,0xFE,0x0F,0xF8,0x7F,0xF0,0x07,0xF8,0xFF,0xC0, +0x07,0xF1,0xFF,0x00,0x07,0xF3,0xFC,0x00,0x0F,0xE8, +0xFE,0x00,0x01,0xF9,0xFC,0x00,0x03,0xFE,0xFE,0x00, +0x00,0x7F,0x1F,0x80,0x00,0x1F,0xBF,0x00,0x00,0x7F, +0x8F,0xE0,0x00,0x1F,0x9F,0xE0,0x00,0x7F,0x3F,0xC0, +0x00,0xFC,0x7F,0xC0,0x03,0xF8,0xFF,0xC0,0x0F,0xE1, +0xFF,0xE0,0x7F,0xC3,0xFF,0xFF,0xFF,0x07,0xEF,0xFF, +0xFC,0x0F,0xDF,0xFF,0xF0,0x1F,0x8F,0xFF,0xC0,0x3F, +0x0F,0xFE,0x00,0x7E,0x07,0xF0,0x01,0xBF,0x80,0x00, +0x00,0x5F,0xE0,0x00,0x00,0x00,0x07,0xB1,0x17,0x34, +0xA0,0x01,0xF8,0x00,0x00,0x1F,0xFC,0x1F,0x80,0xFF, +0xFE,0x3F,0x03,0xFF,0xFE,0x7E,0x0F,0xFF,0xFE,0xFC, +0x3F,0xFF,0xFD,0xF8,0x7F,0xC1,0xFF,0xF1,0xFE,0x00, +0xFF,0xE3,0xF8,0x00,0x7F,0xCF,0xE0,0x00,0xFF,0x9F, +0xC0,0x00,0xFF,0x87,0xE0,0x00,0x1F,0xDF,0x80,0x00, +0x3F,0xEF,0xE0,0x00,0x07,0xF1,0xF8,0x00,0x01,0xFB, +0xF8,0x00,0x03,0xF8,0x7E,0x00,0x01,0xFC,0xFE,0x00, +0x07,0xF8,0xFC,0x00,0x0F,0xF1,0xFC,0x00,0x3F,0xE1, +0xFC,0x00,0xFF,0xC3,0xFE,0x07,0xFF,0x83,0xFF,0xFF, +0xFF,0x03,0xFF,0xFF,0x7E,0x03,0xFF,0xFE,0xFC,0x03, +0xFF,0xF1,0xF8,0x01,0xFF,0xC3,0xF0,0x00,0xFE,0x07, +0xFA,0x00,0x00,0x01,0xFD,0x80,0x00,0x00,0x7E,0x04, +0xA4,0x28,0x02,0xC0,0x03,0xE1,0xF1,0xFF,0x3E,0x7F, +0xF7,0xDF,0xFE,0xFB,0xFF,0x9F,0xFF,0xF3,0xFF,0x0C, +0x7F,0xC0,0x0F,0xF0,0x02,0x7F,0x80,0x0D,0xFC,0x00, +0x37,0xF0,0x00,0xDF,0xC0,0x02,0x7F,0x00,0x00,0x07, +0x65,0x17,0xF4,0x40,0x07,0xFC,0x00,0x00,0x7F,0xFE, +0x00,0x07,0xFF,0xFE,0x00,0x3F,0xFF,0xFC,0x01,0xFF, +0xFF,0xF8,0x0F,0xFF,0xFF,0xF0,0x3F,0xC0,0x7F,0xC1, +0xFC,0x00,0x7F,0x07,0xE0,0x00,0xFE,0x1F,0x80,0x01, +0xF8,0x7E,0x00,0x07,0x01,0xFC,0x00,0x00,0x07,0xF8, +0x00,0x00,0x1F,0xFC,0x00,0x00,0x3F,0xFE,0x00,0x00, +0xFF,0xFF,0x80,0x01,0xFF,0xFF,0x80,0x03,0xFF,0xFF, +0xC0,0x03,0xFF,0xFF,0xC0,0x03,0xFF,0xFF,0x80,0x01, +0xFF,0xFF,0x00,0x00,0xFF,0xFC,0x00,0x00,0x3F,0xF8, +0x00,0x00,0x1F,0xE0,0x00,0x00,0x3F,0x87,0x00,0x00, +0x7E,0xFC,0x00,0x01,0xFB,0xF8,0x00,0x07,0xE7,0xF0, +0x00,0x3F,0x9F,0xE0,0x01,0xFC,0x7F,0xE0,0x1F,0xF0, +0xFF,0xFF,0xFF,0x81,0xFF,0xFF,0xFC,0x03,0xFF,0xFF, +0xE0,0x07,0xFF,0xFF,0x00,0x07,0xFF,0xF0,0x00,0x03, +0xFE,0x00,0x00,0x04,0x70,0x0F,0xF2,0x60,0x04,0x00, +0x07,0x00,0x03,0xC0,0x68,0x7E,0x02,0x03,0xF0,0x19, +0xFF,0xFE,0xD0,0xFC,0x06,0x87,0xE0,0x34,0x3F,0x01, +0x01,0xF8,0x00,0x7F,0x02,0x03,0xFF,0xC0,0x7F,0xF0, +0x1F,0xFE,0x03,0xFF,0x80,0x3F,0xE0,0x06,0xE4,0x2F, +0xF4,0xBB,0xF8,0x00,0x0F,0xF7,0xF0,0x00,0x1F,0xEF, +0xE0,0x00,0x3F,0x9F,0xC0,0x00,0x7F,0x1F,0x80,0x01, +0xFE,0x3F,0x80,0x07,0xF9,0xFC,0x01,0xFF,0x9F,0xF0, +0x7F,0xF9,0xFF,0xFF,0xDF,0x8F,0xFF,0xFD,0xF8,0x7F, +0xFF,0x9F,0x83,0xFF,0xF1,0xF8,0x1F,0xFC,0x1F,0x80, +0x7F,0x00,0x00,0x07,0xE3,0x08,0x04,0x2F,0xE0,0x00, +0x07,0xEF,0xE0,0x00,0x0F,0xE7,0xE0,0x00,0x0F,0xC7, +0xF0,0x00,0x0F,0xC7,0xF0,0x00,0x1F,0xC3,0xF0,0x00, +0x1F,0x83,0xF8,0x00,0x1F,0x83,0xF8,0x00,0x3F,0x81, +0xF8,0x00,0x3F,0x01,0xFC,0x00,0x3F,0x01,0xFC,0x00, +0x7F,0x00,0xFC,0x00,0x7E,0x00,0xFE,0x00,0x7E,0x00, +0xFE,0x00,0xFE,0x00,0x7E,0x00,0xFC,0x00,0x7F,0x00, +0xFC,0x00,0x7F,0x01,0xFC,0x00,0x3F,0x01,0xF8,0x00, +0x3F,0x81,0xF8,0x00,0x3F,0x83,0xF8,0x10,0x03,0xF0, +0x7E,0x00,0x03,0xF8,0xFE,0x02,0x00,0x3F,0x1F,0x80, +0x00,0x3F,0xBF,0x80,0x40,0x03,0xF7,0xE0,0x00,0x03, +0xFF,0xE0,0x09,0x00,0x3F,0xF8,0x01,0x20,0x03,0xFE, +0x00,0x00,0x0B,0xE3,0x00,0x05,0xF1,0xF8,0x00,0x1F, +0xC0,0x00,0xFD,0xF8,0x00,0x1F,0xE0,0x00,0xFE,0x5F, +0x80,0x07,0xFC,0x00,0x3F,0x1F,0xC0,0x07,0xFE,0x00, +0x7F,0x0F,0xC0,0x0F,0xFE,0x00,0x7E,0x0F,0xC0,0x0F, +0xBE,0x00,0x7E,0x0F,0xC0,0x0F,0xBE,0x00,0xFE,0x07, +0xE0,0x0F,0xBF,0x00,0xFC,0x07,0xE0,0x1F,0xBF,0x00, +0xFC,0x07,0xE0,0x1F,0x3F,0x00,0xFC,0x03,0xF0,0x1F, +0x1F,0x01,0xF8,0x03,0xF0,0x1F,0x1F,0x81,0xF8,0x03, +0xF0,0x3F,0x1F,0x81,0xF8,0x03,0xF8,0x3F,0x1F,0x83, +0xF0,0x01,0xF8,0x3E,0x0F,0x83,0xF0,0x40,0x3F,0x0F, +0xC1,0xF8,0x7E,0x00,0x1F,0x8F,0xC1,0xF8,0xFC,0x00, +0x1F,0x8F,0x80,0xF8,0xFC,0x00,0x1F,0x9F,0x80,0xFC, +0xFC,0x00,0x0F,0x9F,0x80,0xFD,0xF8,0x00,0x0F,0xDF, +0x80,0xFD,0xF8,0x00,0x0F,0xDF,0x00,0x7D,0xF8,0x00, +0x07,0xDF,0x00,0x7D,0xF0,0x08,0x00,0xFF,0xE0,0x0F, +0xFE,0x00,0x00,0xFF,0xC0,0x07,0xFE,0x01,0x20,0x0F, +0xF8,0x00,0xFF,0x80,0x00,0x07,0xF0,0x00,0xFF,0x00, +0x00,0x07,0xF0,0x00,0x7F,0x00,0x00,0x08,0x23,0x00, +0x04,0x07,0xF8,0x00,0x07,0xF1,0xFC,0x00,0x07,0xF0, +0x7F,0x00,0x07,0xF0,0x3F,0xC0,0x07,0xF8,0x0F,0xE0, +0x03,0xF8,0x03,0xF8,0x03,0xF8,0x01,0xFE,0x03,0xFC, +0x00,0x7F,0x01,0xFC,0x00,0x1F,0xC1,0xFC,0x00,0x0F, +0xF1,0xFC,0x00,0x03,0xF9,0xFE,0x00,0x00,0xFE,0xFE, +0x01,0x00,0x07,0xFF,0xC0,0x00,0x01,0xFF,0xC0,0x00, +0x00,0x7F,0xC0,0x04,0x00,0x07,0xF8,0x00,0x00,0x03, +0xFE,0x00,0x00,0x03,0xFF,0x00,0x00,0x03,0xFF,0xC0, +0x00,0x01,0xFF,0xF0,0x00,0x01,0xFF,0xF8,0x00,0x01, +0xFC,0xFE,0x00,0x01,0xFE,0x3F,0x80,0x00,0xFE,0x1F, +0xE0,0x00,0xFE,0x07,0xF0,0x00,0xFF,0x01,0xFC,0x00, +0x7F,0x00,0xFF,0x00,0x7F,0x00,0x3F,0x80,0x7F,0x00, +0x0F,0xE0,0x7F,0x80,0x07,0xF8,0x3F,0x80,0x01,0xFC, +0x3F,0x80,0x00,0x7F,0x3F,0xC0,0x00,0x3F,0xC0,0x07, +0xF1,0x0F,0x24,0x2F,0xE0,0x00,0x07,0xE7,0xE0,0x00, +0x0F,0xE7,0xE0,0x00,0x0F,0xC7,0xF0,0x00,0x0F,0xC3, +0xF0,0x00,0x1F,0xC3,0xF0,0x00,0x1F,0x83,0xF8,0x00, +0x1F,0x81,0xF8,0x00,0x3F,0x81,0xFC,0x00,0x3F,0x00, +0xFC,0x00,0x3F,0x00,0xFC,0x00,0x7F,0x00,0xFE,0x00, +0x7E,0x00,0x7E,0x00,0x7E,0x00,0x7F,0x00,0xFE,0x00, +0x7F,0x00,0xFC,0x00,0x3F,0x00,0xFC,0x00,0x3F,0x81, +0xFC,0x10,0x03,0xF0,0x3F,0x00,0x03,0xF8,0x7F,0x00, +0x01,0xF8,0x7E,0x00,0x01,0xFC,0x7E,0x00,0x01,0xFC, +0xFE,0x00,0x00,0xFC,0xFC,0x00,0x00,0xFE,0xFC,0x00, +0x00,0x7F,0xFC,0x02,0x00,0x0F,0xFF,0x00,0x00,0x07, +0xFF,0x00,0x40,0x00,0xFF,0xC0,0x00,0x00,0x7F,0xC0, +0x00,0x00,0x7F,0x80,0x00,0x00,0x3F,0x80,0x08,0x00, +0x07,0xE0,0x00,0x00,0x0F,0xE0,0x01,0x00,0x01,0xF8, +0x00,0x00,0x03,0xF8,0x00,0x00,0x03,0xF0,0x00,0x00, +0x07,0xF0,0x00,0x00,0x1F,0xE0,0x00,0x07,0xFF,0xE0, +0x00,0x07,0xFF,0xC0,0x00,0x03,0xFF,0x80,0x00,0x03, +0xFF,0x00,0x00,0x03,0xFE,0x00,0x00,0x01,0xF8,0x00, +0x00,0x00,0x07,0xA3,0x08,0x04,0x38,0x7F,0xFF,0xFF, +0xF0,0x00,0x00,0x3F,0xC0,0x00,0x00,0xFF,0x00,0x00, +0x03,0xFC,0x00,0x00,0x0F,0xF0,0x00,0x00,0x1F,0xC0, +0x00,0x00,0x7F,0x00,0x00,0x01,0xFE,0x00,0x00,0x07, +0xF8,0x00,0x00,0x1F,0xE0,0x00,0x00,0x7F,0x80,0x00, +0x01,0xFE,0x00,0x00,0x07,0xF8,0x00,0x00,0x1F,0xE0, +0x00,0x00,0x3F,0x80,0x00,0x00,0xFE,0x00,0x00,0x03, +0xFC,0x00,0x00,0x0F,0xF0,0x00,0x00,0x3F,0xC0,0x00, +0x00,0xFF,0x00,0x00,0x03,0xFC,0x00,0x00,0x0F,0xF0, +0x00,0x00,0x1F,0xC0,0x00,0x00,0x7F,0x00,0x00,0x03, +0x3F,0xFF,0xFF,0xFF,0x05,0x3F,0x0F,0x22,0xC0,0x00, +0x7F,0x00,0x0F,0xF8,0x00,0xFF,0xC0,0x0F,0xFF,0x00, +0x1F,0xFE,0x01,0xFE,0x00,0x0F,0xE0,0x68,0x0F,0xC0, +0x68,0x0F,0xC0,0x00,0x7E,0x02,0x00,0xFC,0x00,0x0F, +0xE0,0x00,0xFE,0x00,0x0F,0xF0,0x03,0xFF,0x00,0x1F, +0xF0,0x01,0x1F,0xC0,0x00,0xFF,0x00,0x07,0xFE,0x00, +0x07,0xF8,0x00,0x1F,0xC0,0x00,0x7F,0x00,0x80,0x3F, +0x00,0xD0,0x1F,0x80,0xD0,0x1F,0x80,0x80,0x1F,0x80, +0x00,0xFE,0x00,0x03,0xF8,0x20,0x03,0xFF,0xC0,0x0F, +0xFE,0x00,0x3F,0xF0,0x00,0xFF,0x80,0x01,0xFC,0x01, +0x7F,0x37,0x12,0x3B,0xFD,0xFE,0xFF,0x7F,0xBF,0xDF, +0xEF,0xF7,0xFB,0xF0,0x05,0x3F,0x0F,0x22,0xCF,0xE0, +0x00,0x7F,0xC0,0x03,0xFF,0x00,0x1F,0xFC,0x01,0x1F, +0xFE,0x00,0x07,0xF0,0x00,0x1F,0xC0,0x68,0x0F,0xC0, +0x68,0x0F,0xC0,0x00,0x7E,0x02,0x00,0x3F,0x00,0x01, +0xFC,0x00,0x07,0xF0,0x00,0x3F,0xC0,0x00,0xFF,0xC0, +0x01,0xFF,0x00,0x00,0xFE,0x00,0x1F,0xF0,0x01,0xFF, +0x80,0x1F,0xE0,0x00,0xFE,0x00,0x0F,0xE0,0x00,0x7E, +0x00,0x07,0xF0,0x34,0x07,0xE0,0x34,0x07,0xE0,0x20, +0x07,0xE0,0x00,0x7F,0x00,0x07,0xF8,0x08,0xFF,0xF0, +0x07,0xFF,0x00,0x3F,0xF0,0x01,0xFF,0x00,0x0F,0xE0, +0x00,0x08,0x8D,0x11,0x04,0xE0,0x3F,0x00,0x00,0x00, +0x1F,0xFC,0x00,0x00,0x87,0xFF,0xE0,0x00,0x31,0xFF, +0xFF,0x00,0x0E,0x7F,0xFF,0xF8,0x03,0xDF,0xFF,0xFF, +0xC1,0xFB,0xFF,0xFF,0xFF,0xFF,0x7E,0x0F,0xFF,0xFF, +0xEF,0x00,0x3F,0xFF,0xF9,0xC0,0x03,0xFF,0xFE,0x30, +0x00,0x1F,0xFF,0x84,0x00,0x00,0xFF,0xE0,0x00,0x00, +0x07,0xF0,0x00,}; +/* font data size: 10693 bytes */ + +static const unsigned char Arial_48_index[] = { +0x00,0x00,0x00,0x50,0x05,0x80,0x23, +0x02,0x10,0x14,0xE0,0xA4,0x83,0x88,0x0E,0x44,0x3D, +0xF1,0x0B,0x44,0x60,0x11,0xEC,0x48,0x71,0x23,0xC4, +0x95,0x13,0x64,0x55,0x81,0x63,0x86,0x2D,0x1B,0x7C, +0x76,0x61,0xFC,0x48,0x9C,0x24,0x04,0x9A,0x72,0x93, +0x4A,0x59,0x29,0xB0,0xAF,0x52,0xC2,0xCB,0x94,0x30, +0x8C,0xE1,0x83,0xB3,0xCF,0x89,0x41,0x59,0x0F,0x74, +0x49,0x11,0x4D,0x48,0x89,0x25,0x14,0x97,0xD2,0xA5, +0x4E,0x6D,0x3B,0xE5,0x10,0x15,0x0B,0x57,0xC5,0x66, +0xA5,0xD8,0x58,0x30,0x64,0x59,0x94,0x06,0x67,0xDA, +0x51,0x6D,0xED,0xC7,0x87,0x41,0x1D,0xBA,0x77,0x49, +0xE1,0x67,0x8B,0x9E,0x6E,0x79,0xE1,0xE8,0xB7,0xC7, +0x5F,0x98,0x80,0x4A,0x08,0xA8,0x42,0x21,0x34,0x87, +0x1E,0x20,0x78,0x85,0x62,0x37,0x8A,0xEA,0x2C,0x88, +0xCC,0x63,0x69,0x8F,0x62,0x45,0x09,0x32,0xE4,0xF3, +0x96,0x0E,0x5A,0xF9,0x79,0xE6,0x5E,0x9C,0x36,0x79, +0xBA,0x14,0xA8,0xB8,0xA4,0x5E,0x92,0x6A,0x61,0xC0, +}; +/* font index size: 167 bytes */ + +const ILI9341_t3_font_t Arial_48 = { + Arial_48_index, + 0, + Arial_48_data, + 1, + 0, + 32, + 126, + 0, + 0, + 14, + 7, + 6, + 5, + 7, + 7, + 74, + 48 +}; + + + +static const unsigned char Arial_60_data[] = { +0x00,0x00,0x00,0x01,0x70,0x01,0xDE,0x24,0x01,0x9D, +0xFF,0xBF,0xF7,0xFB,0xF9,0xFE,0xBE,0xD7,0xD0,0xFB, +0x4E,0x0E,0x60,0x0D,0xFE,0x05,0x8A,0x8D,0x39,0xDD, +0xFE,0x01,0xFF,0x3F,0x80,0x7F,0xD7,0xC0,0x0F,0x87, +0x80,0x0E,0x00,0x0B,0x5E,0x00,0x02,0xE8,0x00,0x00, +0x7F,0x00,0x3F,0x80,0x00,0x03,0xFC,0x01,0xFC,0x12, +0x00,0x01,0xFC,0x00,0xFE,0x00,0x00,0x07,0xF0,0x07, +0xF8,0x00,0x00,0x3F,0xC0,0x1F,0xC0,0x90,0x00,0x1F, +0xC0,0x0F,0xE0,0x00,0x00,0xFF,0x00,0x7F,0x81,0x40, +0x00,0x7F,0x00,0x3F,0x80,0xDF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xC0,0x00,0x7F,0x00,0x3F,0x80,0x00,0x03,0xFC, +0x01,0xFC,0x00,0x90,0x01,0xFC,0x00,0xFE,0x00,0x00, +0x07,0xF0,0x07,0xF8,0x00,0x00,0x3F,0xC0,0x1F,0xC0, +0x04,0x80,0x1F,0xC0,0x0F,0xE0,0x00,0x00,0x7F,0x00, +0x7F,0x80,0x08,0x00,0x7F,0x00,0x3F,0x80,0x06,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFE,0x80,0x7F,0x00,0x3F,0x80, +0x00,0x03,0xFC,0x01,0xFE,0x00,0x04,0x81,0xFC,0x00, +0xFE,0x00,0x00,0x07,0xF0,0x07,0xF8,0x00,0x00,0x3F, +0xC0,0x1F,0xC0,0x00,0x24,0x1F,0xC0,0x0F,0xE0,0x00, +0x00,0x7F,0x00,0x7F,0x80,0x00,0x40,0x7F,0x00,0x3F, +0x80,0x00,0x00,0x09,0xE3,0x8F,0xC2,0xE9,0x00,0x00, +0x3C,0x00,0x00,0x00,0x03,0xFF,0x80,0x00,0x00,0x1F, +0xFF,0xF0,0x00,0x00,0x7F,0xFF,0xFC,0x00,0x01,0xFF, +0xFF,0xFE,0x00,0x03,0xFF,0xFF,0xFF,0x00,0x07,0xFF, +0xFF,0xFF,0x80,0x0F,0xFF,0xFF,0xFF,0xC0,0x1F,0xFE, +0x3F,0xFF,0xE0,0x1F,0xF8,0x3C,0xFF,0xE0,0x3F,0xE0, +0x3C,0x3F,0xF0,0x3F,0xC0,0x3C,0x1F,0xF0,0x7F,0x80, +0x3C,0x0F,0xF0,0x7F,0x80,0x3C,0x07,0xF8,0x7F,0x00, +0x3C,0x07,0xF8,0x7F,0x00,0x3C,0x03,0xF8,0x7F,0x00, +0x3C,0x03,0xC1,0x0F,0xE0,0x07,0x80,0x00,0x21,0xFE, +0x00,0xF0,0x00,0x00,0xFF,0x00,0xF0,0x00,0x00,0xFF, +0x80,0xF0,0x00,0x00,0x7F,0xE0,0xF0,0x00,0x00,0x7F, +0xF8,0xF0,0x00,0x00,0x3F,0xFF,0xF0,0x00,0x00,0x1F, +0xFF,0xF0,0x00,0x00,0x0F,0xFF,0xFF,0x00,0x00,0x03, +0xFF,0xFF,0xE0,0x00,0x01,0xFF,0xFF,0xF8,0x00,0x00, +0x3F,0xFF,0xFE,0x00,0x00,0x0F,0xFF,0xFF,0x00,0x00, +0x00,0xFF,0xFF,0x80,0x00,0x00,0xFF,0xFF,0xC0,0x00, +0x00,0xF1,0xFF,0xE0,0x00,0x00,0xF0,0x7F,0xE0,0x00, +0x00,0xF0,0x1F,0xF0,0x00,0x00,0xF0,0x0F,0xF0,0x00, +0x00,0xF0,0x07,0xF0,0x00,0x00,0xF0,0x07,0xFC,0x80, +0x00,0x1E,0x00,0x7F,0x0F,0x00,0x1E,0x00,0x7F,0x7F, +0x00,0x1E,0x00,0x7F,0x8F,0xF0,0x03,0xC0,0x0F,0xEF, +0xF0,0x03,0xC0,0x1F,0xE7,0xF8,0x03,0xC0,0x1F,0xC7, +0xF8,0x03,0xC0,0x3F,0xC7,0xFC,0x03,0xC0,0x7F,0xC3, +0xFE,0x03,0xC0,0xFF,0x83,0xFF,0x83,0xC1,0xFF,0x81, +0xFF,0xE3,0xCF,0xFF,0x01,0xFF,0xFF,0xFF,0xFE,0x00, +0xFF,0xFF,0xFF,0xFC,0x00,0x7F,0xFF,0xFF,0xF8,0x00, +0x3F,0xFF,0xFF,0xF0,0x00,0x1F,0xFF,0xFF,0xE0,0x00, +0x07,0xFF,0xFF,0x80,0x00,0x01,0xFF,0xFC,0x00,0x00, +0x00,0x1F,0xC0,0x00,0x1A,0x00,0x00,0x78,0x00,0x00, +0x10,0x1F,0x17,0xFC,0xA0,0x03,0xF8,0x00,0x00,0x00, +0x3F,0x80,0x00,0x0F,0xFF,0x00,0x00,0x00,0x1F,0x80, +0x00,0x0F,0xFF,0xE0,0x00,0x00,0x1F,0xC0,0x00,0x0F, +0xFF,0xF8,0x00,0x00,0x0F,0xC0,0x00,0x0F,0xFF,0xFE, +0x00,0x00,0x0F,0xE0,0x00,0x07,0xF0,0x7F,0x00,0x00, +0x07,0xE0,0x00,0x07,0xF0,0x1F,0xC0,0x00,0x07,0xF0, +0x00,0x07,0xF0,0x07,0xE0,0x00,0x07,0xF0,0x00,0x03, +0xF0,0x01,0xF8,0x00,0x03,0xF8,0x00,0x04,0x3F,0x00, +0x1F,0x80,0x00,0x7F,0x00,0x00,0x3F,0x00,0x07,0xE0, +0x00,0x7F,0x00,0x00,0x1F,0x80,0x03,0xF0,0x00,0x3F, +0x00,0x00,0x0F,0xC0,0x01,0xF8,0x00,0x3F,0x80,0x00, +0x07,0xE0,0x00,0xFC,0x00,0x1F,0x80,0x00,0x03,0xF0, +0x00,0x7E,0x00,0x1F,0xC0,0x00,0x01,0xF8,0x00,0x3F, +0x00,0x0F,0xC0,0x00,0x00,0xFC,0x00,0x1F,0x80,0x0F, +0xE0,0x00,0x00,0x7E,0x00,0x0F,0xC0,0x07,0xE0,0x00, +0x00,0x3F,0x00,0x07,0xE0,0x07,0xF0,0x00,0x00,0x1F, +0x80,0x03,0xF0,0x03,0xF0,0x00,0x00,0x07,0xC0,0x03, +0xF0,0x03,0xF8,0x00,0x00,0x08,0x7E,0x00,0x3F,0x00, +0x7F,0x00,0x00,0x00,0x3F,0x80,0x3F,0x00,0x7F,0x00, +0x00,0x00,0x0F,0xE0,0x3F,0x80,0x3F,0x80,0x00,0x00, +0x07,0xF8,0x3F,0x80,0x3F,0x80,0x00,0x00,0x01,0xFF, +0xFF,0xC0,0x1F,0x80,0x00,0x00,0x00,0x7F,0xFF,0xC0, +0x1F,0xC0,0x00,0x00,0x00,0x1F,0xFF,0xC0,0x0F,0xC0, +0x00,0x00,0x00,0x03,0xFF,0x80,0x0F,0xE0,0x01,0xFC, +0x00,0x00,0x7F,0x00,0x07,0xE0,0x07,0xFF,0x80,0x00, +0x00,0x00,0x07,0xF0,0x07,0xFF,0xF0,0x00,0x00,0x00, +0x03,0xF0,0x07,0xFF,0xFC,0x00,0x00,0x00,0x03,0xF8, +0x07,0xFF,0xFF,0x00,0x00,0x00,0x01,0xF8,0x03,0xF8, +0x3F,0x80,0x00,0x00,0x01,0xFC,0x03,0xF8,0x0F,0xE0, +0x00,0x00,0x00,0xFC,0x03,0xF8,0x03,0xF0,0x00,0x00, +0x00,0xFE,0x01,0xF8,0x00,0xFD,0x00,0x00,0x00,0x1F, +0xC0,0x1F,0x80,0x0F,0xD0,0x00,0x00,0x03,0xF8,0x03, +0xF0,0x00,0x7E,0x00,0x00,0x03,0xF8,0x01,0xF8,0x00, +0x3F,0x00,0x00,0x01,0xF8,0x00,0xFC,0x00,0x1F,0x80, +0x00,0x01,0xFC,0x00,0x7E,0x00,0x0F,0xC0,0x00,0x00, +0xFC,0x00,0x3F,0x00,0x07,0xE0,0x00,0x00,0xFE,0x00, +0x1F,0x80,0x03,0xF0,0x00,0x00,0x7E,0x00,0x0F,0xC0, +0x01,0xF8,0x00,0x00,0x7F,0x00,0x07,0xE0,0x00,0xFC, +0x00,0x00,0x3F,0x00,0x03,0xF0,0x00,0x7E,0x00,0x00, +0x3F,0x80,0x00,0xF8,0x00,0x7E,0x00,0x00,0x1F,0x80, +0x00,0x7E,0x00,0x3F,0x00,0x00,0x1F,0xC0,0x00,0x3F, +0x00,0x1F,0x80,0x00,0x1F,0xC0,0x00,0x1F,0xC0,0x1F, +0x80,0x00,0x0F,0xE0,0x00,0x07,0xF0,0x1F,0xC0,0x00, +0x0F,0xE0,0x00,0x03,0xFC,0x1F,0xC0,0x00,0x07,0xF0, +0x00,0x00,0xFF,0xFF,0xE0,0x00,0x07,0xF0,0x00,0x00, +0x3F,0xFF,0xE0,0x00,0x03,0xF0,0x00,0x00,0x0F,0xFF, +0xE0,0x00,0x03,0xF8,0x00,0x00,0x01,0xFF,0xC0,0x00, +0x01,0xF8,0x00,0x00,0x00,0x3F,0x80,0x00,0x0C,0x5F, +0x13,0xFB,0x70,0x00,0x03,0xFC,0x00,0x00,0x00,0x00, +0x03,0xFF,0xE0,0x00,0x00,0x00,0x03,0xFF,0xFE,0x00, +0x00,0x00,0x01,0xFF,0xFF,0xC0,0x00,0x00,0x00,0xFF, +0xFF,0xF8,0x00,0x00,0x00,0x7F,0xFF,0xFF,0x00,0x00, +0x00,0x3F,0xFF,0xFF,0xC0,0x00,0x00,0x1F,0xF8,0x1F, +0xF8,0x00,0x00,0x07,0xFC,0x03,0xFE,0x00,0x00,0x01, +0xFE,0x00,0x7F,0x80,0x00,0x00,0xFF,0x00,0x0F,0xF0, +0x00,0x2C,0x07,0xF0,0x00,0x3F,0x80,0x00,0x01,0xFE, +0x00,0x0F,0xE0,0x00,0x00,0x3F,0x80,0x07,0xF0,0x00, +0x00,0x0F,0xF0,0x01,0xFC,0x00,0x00,0x03,0xFC,0x00, +0xFE,0x00,0x00,0x00,0x7F,0x80,0x7F,0x80,0x00,0x00, +0x0F,0xF0,0x7F,0xC0,0x00,0x00,0x03,0xFE,0x3F,0xE0, +0x00,0x00,0x00,0x7F,0xFF,0xF0,0x00,0x00,0x00,0x0F, +0xFF,0xF8,0x00,0x00,0x00,0x01,0xFF,0xFC,0x00,0x00, +0x00,0x00,0x7F,0xFE,0x00,0x00,0x00,0x00,0x3F,0xFE, +0x00,0x00,0x00,0x00,0x1F,0xFF,0x00,0x00,0x00,0x00, +0x1F,0xFF,0xC0,0x00,0x00,0x00,0x0F,0xFF,0xF8,0x00, +0x00,0x00,0x0F,0xFF,0xFF,0x00,0x00,0x00,0x07,0xFF, +0x3F,0xE0,0x00,0x00,0x03,0xFF,0x07,0xFC,0x00,0x00, +0x00,0xFF,0x80,0xFF,0x00,0x3C,0x00,0x7F,0xC0,0x1F, +0xE0,0x1F,0xE0,0x3F,0xE0,0x07,0xFC,0x07,0xF8,0x0F, +0xF0,0x00,0xFF,0x81,0xFC,0x07,0xF8,0x00,0x1F,0xF0, +0xFF,0x01,0xFC,0x00,0x03,0xFC,0x3F,0xC0,0x7F,0x00, +0x00,0x7F,0x9F,0xE0,0x3F,0x80,0x00,0x1F,0xF7,0xF8, +0x0F,0xE0,0x00,0x03,0xFF,0xFE,0x03,0xF8,0x00,0x00, +0x7F,0xFF,0x00,0xFE,0x00,0x00,0x0F,0xFF,0xC0,0x47, +0xF0,0x00,0x00,0x3F,0xFC,0x01,0xFE,0x00,0x00,0x07, +0xFE,0x00,0x7F,0x80,0x00,0x00,0xFF,0xC0,0x0F,0xF0, +0x00,0x00,0x7F,0xF8,0x03,0xFC,0x00,0x00,0x3F,0xFE, +0x00,0xFF,0x80,0x00,0x1F,0xFF,0xC0,0x1F,0xF0,0x00, +0x1F,0xFF,0xF8,0x03,0xFE,0x00,0x1F,0xFF,0xFF,0x00, +0xFF,0xF0,0x1F,0xFF,0x3F,0xF0,0x1F,0xFF,0xFF,0xFF, +0x8F,0xFE,0x03,0xFF,0xFF,0xFF,0xC1,0xFF,0xC0,0x7F, +0xFF,0xFF,0xE0,0x3F,0xE0,0x0F,0xFF,0xFF,0xE0,0x07, +0xF0,0x00,0xFF,0xFF,0xF0,0x00,0xF8,0x00,0x0F,0xFF, +0xF0,0x00,0x1C,0x00,0x00,0x7F,0xE0,0x00,0x02,0x00, +0x01,0xCA,0x91,0x39,0x0D,0xFF,0x9F,0xF5,0xF1,0xE0, +0x04,0xE6,0x97,0x79,0xC0,0x00,0x1F,0x00,0x03,0xE0, +0x00,0x7E,0x00,0x07,0xC0,0x00,0xF8,0x00,0x1F,0x80, +0x01,0xF0,0x00,0x3F,0x08,0x00,0xFC,0x10,0x03,0xF0, +0x20,0x0F,0xC0,0x01,0xFC,0x00,0x1F,0x80,0x03,0xF8, +0x04,0x07,0xE0,0x00,0xFE,0x00,0x81,0xF8,0x01,0x07, +0xF0,0x00,0x7E,0x00,0x2D,0xFC,0x00,0x1F,0x80,0x06, +0xFF,0x00,0x0D,0xFE,0x00,0x0F,0xE0,0x00,0x7E,0x00, +0x14,0xFE,0x00,0x07,0xE0,0x02,0x4F,0xE0,0x00,0x7E, +0x00,0x40,0xFE,0x00,0x07,0xE0,0x00,0x7F,0x00,0x80, +0x7E,0x00,0x07,0xF0,0x10,0x07,0xE0,0x20,0x07,0xE0, +0x40,0x07,0xE0,0x00,0x3F,0x00,0x01,0xF0,0x00,0x1F, +0x80,0x00,0xF8,0x00,0x0F,0xC0,0x00,0x7C,0x00,0x03, +0xE0,0x00,0x1F,0x04,0xE6,0x93,0x79,0xC7,0xC0,0x00, +0x3E,0x00,0x03,0xF0,0x00,0x1F,0x00,0x00,0xF8,0x00, +0x0F,0xC0,0x00,0x7C,0x00,0x07,0xE0,0x08,0x07,0xE0, +0x10,0x07,0xE0,0x20,0x07,0xE0,0x00,0x7F,0x00,0x03, +0xF0,0x00,0x3F,0x84,0x00,0x3F,0x08,0x00,0x7F,0x00, +0x03,0xF1,0x20,0x07,0xF0,0x00,0x3F,0x2C,0x00,0x7F, +0x68,0x00,0x7F,0xD0,0x00,0xFE,0x00,0x0F,0xF6,0x00, +0x3F,0x80,0x03,0xF2,0x40,0x0F,0xE0,0x00,0xFC,0x40, +0x03,0xF8,0x00,0x3F,0x00,0x07,0xF0,0x80,0x0F,0xC0, +0x01,0xFC,0x10,0x03,0xF0,0x20,0x0F,0xC0,0x40,0x3F, +0x00,0x07,0xE0,0x00,0x7C,0x00,0x0F,0xC0,0x00,0xF8, +0x00,0x1F,0x80,0x03,0xF0,0x00,0x3E,0x00,0x07,0xC0, +0x00,0x07,0x0C,0x8D,0x1A,0x0C,0x00,0x1F,0x80,0x01, +0x00,0xF8,0x02,0x0F,0x03,0xC0,0xF0,0xFE,0x1E,0x1F, +0xC7,0xFC,0xF7,0xFE,0x7F,0xFF,0xFF,0xF3,0xFF,0xFF, +0xFF,0xC7,0xFF,0xFF,0xF8,0x01,0xFF,0xFC,0x00,0x01, +0xFE,0x00,0x00,0x1F,0xF8,0x00,0x01,0xFF,0xE0,0x00, +0x1F,0xBF,0x80,0x01,0xFC,0xFE,0x00,0x1F,0xC3,0xF8, +0x01,0xFE,0x1F,0xE0,0x1F,0xE0,0x7F,0x80,0x3E,0x01, +0xF0,0x00,0xF0,0x0F,0x00,0x01,0x00,0x20,0x00,0x09, +0xD3,0x90,0x53,0x0D,0x00,0x00,0xFE,0x00,0x01,0xA0, +0x00,0x1F,0xC0,0x00,0x20,0x00,0x03,0xF8,0x00,0x06, +0xFF,0xFF,0xFF,0xFF,0xFF,0xD0,0x00,0x0F,0xE0,0x00, +0x1A,0x00,0x01,0xFC,0x00,0x02,0x00,0x00,0x3F,0x80, +0x00,0x00,0x01,0xCA,0x1F,0x99,0x7D,0xFF,0x83,0xC3, +0xA0,0xF1,0xE3,0xE1,0xC0,0x80,0x05,0xC3,0x8C,0x91, +0xCD,0xFF,0xFF,0xFE,0x01,0xC3,0x9C,0x01,0x7D,0xFE, +0x05,0xDE,0x00,0x01,0x78,0x00,0x00,0x7F,0x20,0x00, +0x1F,0x80,0x00,0x3F,0xA4,0x00,0x07,0xE0,0x00,0x0F, +0xE4,0x00,0x01,0xF8,0x00,0x03,0xF8,0x90,0x00,0x7E, +0x00,0x00,0xFE,0x10,0x00,0x1F,0x80,0x00,0x3F,0x82, +0x40,0x07,0xE0,0x00,0x0F,0xE0,0x40,0x01,0xF8,0x00, +0x03,0xF8,0x09,0x00,0x7E,0x00,0x00,0xFE,0x01,0x00, +0x1F,0x80,0x00,0x3F,0x80,0x24,0x07,0xE0,0x00,0x0F, +0xE0,0x04,0x81,0xF8,0x00,0x90,0x7E,0x00,0x00,0xFE, +0x00,0x12,0x1F,0x80,0x02,0x47,0xE0,0x00,0x0F,0xE0, +0x00,0x49,0xF8,0x00,0x09,0x7E,0x00,0x00,0xFE,0x00, +0x00,0xFC,0x00,0x00,0x09,0x9E,0x93,0xFA,0xE0,0x00, +0x1F,0xF8,0x00,0x00,0x01,0xFF,0xFE,0x00,0x00,0x07, +0xFF,0xFE,0x00,0x00,0x3F,0xFF,0xFF,0x00,0x00,0xFF, +0xFF,0xFF,0x00,0x03,0xFF,0xFF,0xFF,0x00,0x0F,0xFF, +0xFF,0xFF,0x00,0x1F,0xFC,0x0F,0xFE,0x00,0x7F,0xC0, +0x07,0xFE,0x00,0xFF,0x00,0x03,0xFC,0x03,0xFC,0x00, +0x03,0xFC,0x07,0xF0,0x00,0x03,0xF8,0x1F,0xE0,0x00, +0x07,0xF1,0x07,0xF0,0x00,0x00,0xFE,0x1F,0xE0,0x00, +0x01,0xFC,0xB7,0xF0,0x00,0x00,0x3F,0xB7,0xF8,0x00, +0x00,0x07,0xFD,0xFE,0x00,0x00,0x01,0xFE,0xFF,0x80, +0x00,0x00,0x7F,0xB7,0xF0,0x00,0x00,0x3F,0x87,0xE0, +0x00,0x00,0xFE,0x41,0xFC,0x00,0x00,0x3F,0x83,0xFC, +0x00,0x00,0xFF,0x03,0xF8,0x00,0x01,0xFC,0x07,0xF8, +0x00,0x07,0xF8,0x07,0xF8,0x00,0x1F,0xE0,0x0F,0xFC, +0x00,0xFF,0xC0,0x0F,0xFE,0x07,0xFF,0x00,0x1F,0xFF, +0xFF,0xFE,0x00,0x1F,0xFF,0xFF,0xF8,0x00,0x1F,0xFF, +0xFF,0xE0,0x00,0x1F,0xFF,0xFF,0x80,0x00,0x1F,0xFF, +0xFE,0x00,0x00,0x0F,0xFF,0xF0,0x00,0x00,0x03,0xFF, +0x00,0x00,0x05,0x9E,0x24,0x02,0xE8,0x00,0x00,0x7C, +0x00,0x01,0xF8,0x00,0x07,0xF0,0x00,0x1F,0xE0,0x00, +0x7F,0xC0,0x01,0xFF,0x80,0x07,0xFF,0x00,0x1F,0xFE, +0x00,0x7F,0xFC,0x01,0xFF,0xF8,0x0F,0xFF,0xF0,0x3F, +0xFF,0xE1,0xFF,0xFF,0xCF,0xFF,0xBF,0xBF,0xFC,0x7F, +0x7F,0xF0,0xFE,0xFF,0x81,0xFD,0xFE,0x03,0xFB,0xF0, +0x07,0xF7,0x80,0x0F,0xEC,0x00,0x1F,0xF4,0x00,0x07, +0xFD,0x00,0x01,0xFF,0x40,0x00,0x7F,0xD0,0x00,0x1F, +0xF4,0x00,0x07,0xF9,0x00,0x01,0xFC,0x09,0xDE,0x08, +0x02,0xE0,0x00,0x0F,0xFC,0x00,0x00,0x00,0xFF,0xFF, +0x80,0x00,0x03,0xFF,0xFF,0xE0,0x00,0x07,0xFF,0xFF, +0xF8,0x00,0x0F,0xFF,0xFF,0xFC,0x00,0x3F,0xFF,0xFF, +0xFE,0x00,0x3F,0xFF,0xFF,0xFF,0x00,0x7F,0xF8,0x0F, +0xFF,0x00,0xFF,0xC0,0x01,0xFF,0x80,0xFF,0x80,0x00, +0xFF,0x81,0xFF,0x00,0x00,0x7F,0xC1,0xFE,0x00,0x00, +0x3F,0xC1,0xFC,0x00,0x00,0x1F,0xC1,0xFC,0x00,0x00, +0x1F,0xE9,0x7F,0x00,0x00,0x01,0xFC,0x0F,0x00,0x00, +0x01,0xFD,0x00,0x00,0x00,0x00,0x3F,0x80,0x00,0x00, +0x00,0x7F,0xA0,0x00,0x00,0x00,0x0F,0xE0,0x00,0x00, +0x00,0x1F,0xE0,0x00,0x00,0x00,0x1F,0xC0,0x00,0x00, +0x00,0x3F,0xC0,0x00,0x00,0x00,0x7F,0xC0,0x00,0x00, +0x00,0x7F,0x80,0x00,0x00,0x00,0xFF,0x00,0x00,0x00, +0x01,0xFF,0x00,0x00,0x00,0x03,0xFE,0x00,0x00,0x00, +0x07,0xFC,0x00,0x00,0x00,0x0F,0xF8,0x00,0x00,0x00, +0x1F,0xF0,0x00,0x00,0x00,0x3F,0xE0,0x00,0x00,0x00, +0x7F,0xE0,0x00,0x00,0x00,0xFF,0x80,0x00,0x00,0x01, +0xFF,0x00,0x00,0x00,0x07,0xFE,0x00,0x00,0x00,0x0F, +0xFC,0x00,0x00,0x00,0x1F,0xF8,0x00,0x00,0x00,0x3F, +0xF0,0x00,0x00,0x00,0x7F,0xE0,0x00,0x00,0x01,0xFF, +0xC0,0x00,0x00,0x03,0xFF,0x00,0x00,0x00,0x07,0xFE, +0x00,0x00,0x00,0x0F,0xFC,0x00,0x00,0x00,0x0F,0xF8, +0x00,0x00,0x00,0x1F,0xF0,0x00,0x00,0x00,0x3F,0xE0, +0x00,0x00,0x00,0x7F,0xC0,0x00,0x00,0x00,0x7F,0x80, +0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x04,0xBF,0xFF, +0xFF,0xFF,0xFF,0xAF,0xFF,0xFF,0xFF,0xFF,0xE0,0x09, +0x9E,0x93,0xFA,0xE0,0x00,0x1F,0xF0,0x00,0x00,0x01, +0xFF,0xFC,0x00,0x00,0x0F,0xFF,0xFE,0x00,0x00,0x7F, +0xFF,0xFE,0x00,0x01,0xFF,0xFF,0xFE,0x00,0x07,0xFF, +0xFF,0xFE,0x00,0x1F,0xFF,0xFF,0xFE,0x00,0x3F,0xF8, +0x0F,0xFE,0x00,0xFF,0xC0,0x07,0xFC,0x01,0xFE,0x00, +0x07,0xFC,0x07,0xF8,0x00,0x07,0xF8,0x0F,0xF0,0x00, +0x07,0xF0,0x1F,0xC0,0x00,0x0F,0xF0,0x7F,0x80,0x00, +0x0F,0xE0,0xFE,0x00,0x00,0x1F,0xC0,0x3C,0x00,0x00, +0x3F,0x89,0x00,0x00,0x00,0x0F,0xE2,0x00,0x00,0x00, +0x07,0xF0,0x00,0x00,0x00,0x1F,0xE0,0x00,0x00,0x00, +0x7F,0x80,0x00,0x00,0x03,0xFE,0x00,0x00,0x00,0x3F, +0xF8,0x00,0x00,0x0F,0xFF,0xE0,0x00,0x00,0x1F,0xFF, +0x80,0x00,0x00,0x3F,0xFC,0x00,0x00,0x00,0x7F,0xFF, +0x00,0x00,0x01,0xFF,0xFF,0x80,0x00,0x03,0xFF,0xFF, +0x80,0x00,0x06,0x07,0xFF,0x80,0x00,0x00,0x01,0xFF, +0x80,0x00,0x00,0x00,0xFF,0x80,0x00,0x00,0x00,0xFF, +0x20,0x00,0x00,0x00,0x1F,0xE0,0x00,0x00,0x00,0x1F, +0xC0,0x00,0x00,0x00,0x3F,0xE8,0x00,0x00,0x00,0x07, +0xF0,0xF0,0x00,0x00,0x0F,0xEF,0xE0,0x00,0x00,0x1F, +0xDF,0xE0,0x00,0x00,0x3F,0xBF,0xC0,0x00,0x00,0xFF, +0x3F,0x80,0x00,0x01,0xFD,0x0F,0xF0,0x00,0x00,0xFF, +0x0F,0xF0,0x00,0x03,0xFC,0x1F,0xF0,0x00,0x0F,0xF8, +0x1F,0xF0,0x00,0x7F,0xE0,0x3F,0xFC,0x03,0xFF,0x80, +0x3F,0xFF,0xFF,0xFE,0x00,0x3F,0xFF,0xFF,0xFC,0x00, +0x3F,0xFF,0xFF,0xE0,0x00,0x3F,0xFF,0xFF,0x80,0x00, +0x1F,0xFF,0xFE,0x00,0x00,0x0F,0xFF,0xF0,0x00,0x00, +0x03,0xFE,0x00,0x00,0x0A,0x5D,0x84,0x02,0xE0,0x00, +0x00,0x00,0x7E,0x00,0x00,0x00,0x00,0x3F,0x80,0x00, +0x00,0x00,0x1F,0xE0,0x20,0x00,0x00,0x01,0xFF,0x00, +0x00,0x00,0x00,0xFF,0xC0,0x00,0x00,0x00,0x7F,0xF0, +0x10,0x00,0x00,0x07,0xFF,0x80,0x00,0x00,0x03,0xFF, +0xE0,0x20,0x00,0x00,0x3F,0xFF,0x00,0x00,0x00,0x1F, +0xFF,0xC0,0x00,0x00,0x0F,0xFF,0xF0,0x00,0x00,0x07, +0xFD,0xFC,0x00,0x00,0x01,0xFE,0x7F,0x00,0x00,0x00, +0xFF,0x1F,0xC0,0x00,0x00,0x7F,0xC7,0xF0,0x00,0x00, +0x3F,0xE1,0xFC,0x00,0x00,0x0F,0xF0,0x7F,0x00,0x00, +0x07,0xF8,0x1F,0xC0,0x00,0x03,0xFE,0x07,0xF0,0x00, +0x01,0xFF,0x01,0xFC,0x00,0x00,0x7F,0x80,0x7F,0x00, +0x00,0x3F,0xC0,0x1F,0xC0,0x00,0x1F,0xF0,0x07,0xF0, +0x00,0x0F,0xF8,0x01,0xFC,0x00,0x03,0xFC,0x00,0x7F, +0x00,0x01,0xFE,0x00,0x1F,0xC0,0x00,0xFF,0x80,0x07, +0xF0,0x00,0x3F,0xC0,0x01,0xFC,0x00,0x1F,0xE0,0x00, +0x7F,0x00,0x0F,0xF8,0x00,0x1F,0xC0,0x07,0xFC,0x00, +0x07,0xF0,0x01,0xFE,0x00,0x01,0xFC,0x00,0xFF,0x00, +0x00,0x7F,0x00,0x7F,0xC0,0x00,0x1F,0xC0,0x3F,0xE0, +0x00,0x07,0xF0,0x1B,0xFF,0xFF,0xFF,0xFF,0xFF,0xD0, +0x00,0x00,0x01,0xFC,0x06,0x80,0x00,0x00,0x0F,0xE0, +0x00,0x09,0x9E,0x13,0xFA,0xE8,0x01,0xFF,0xFF,0xFF, +0xE2,0xC0,0xFF,0xFF,0xFF,0xF8,0x01,0xFC,0x00,0x00, +0x01,0x60,0xFE,0x00,0x00,0x00,0x03,0xFC,0x00,0x00, +0x00,0xA0,0xFE,0x00,0x00,0x00,0x03,0xFC,0x00,0x00, +0x00,0x07,0xF0,0x1F,0xE0,0x00,0x0F,0xE1,0xFF,0xF0, +0x00,0x1F,0xCF,0xFF,0xF8,0x00,0x3F,0xFF,0xFF,0xFC, +0x00,0xFF,0xFF,0xFF,0xFC,0x01,0xFF,0xFF,0xFF,0xFC, +0x03,0xFF,0xFF,0xFF,0xFC,0x07,0xFF,0xC0,0x3F,0xF8, +0x0F,0xFC,0x00,0x1F,0xF8,0x3F,0xF0,0x00,0x0F,0xF8, +0x7F,0xC0,0x00,0x0F,0xF0,0xFF,0x00,0x00,0x0F,0xF0, +0x3C,0x00,0x00,0x1F,0xE8,0x00,0x00,0x00,0x03,0xF8, +0x00,0x00,0x00,0x07,0xFE,0x80,0x00,0x00,0x00,0xFE, +0x1E,0x00,0x00,0x01,0xFD,0xFC,0x00,0x00,0x07,0xFC, +0x7F,0x80,0x00,0x01,0xFC,0x7F,0x00,0x00,0x07,0xF8, +0xFF,0x00,0x00,0x0F,0xE1,0xFE,0x00,0x00,0x3F,0xC1, +0xFE,0x00,0x00,0xFF,0x03,0xFE,0x00,0x03,0xFE,0x03, +0xFE,0x00,0x0F,0xF8,0x07,0xFF,0x80,0xFF,0xF0,0x07, +0xFF,0xFF,0xFF,0xC0,0x07,0xFF,0xFF,0xFF,0x00,0x07, +0xFF,0xFF,0xFC,0x00,0x07,0xFF,0xFF,0xF0,0x00,0x07, +0xFF,0xFF,0x80,0x00,0x03,0xFF,0xFC,0x00,0x00,0x00, +0x7F,0xC0,0x00,0x00,0x0A,0x1E,0x8B,0xFA,0xE0,0x00, +0x03,0xFE,0x00,0x00,0x00,0x0F,0xFF,0xF0,0x00,0x00, +0x1F,0xFF,0xFC,0x00,0x00,0x3F,0xFF,0xFF,0x80,0x00, +0x3F,0xFF,0xFF,0xE0,0x00,0x3F,0xFF,0xFF,0xF8,0x00, +0x3F,0xFF,0xFF,0xFE,0x00,0x3F,0xFC,0x07,0xFF,0x00, +0x3F,0xF0,0x00,0xFF,0xC0,0x1F,0xF0,0x00,0x1F,0xF0, +0x1F,0xF0,0x00,0x07,0xF8,0x0F,0xF0,0x00,0x03,0xFC, +0x0F,0xF0,0x00,0x00,0xFF,0x07,0xF0,0x00,0x00,0x7F, +0x87,0xF8,0x00,0x00,0x1F,0xC3,0xF8,0x00,0x00,0x0F, +0x01,0xFC,0x00,0x00,0x00,0x05,0x3F,0x80,0x00,0x00, +0x00,0x1F,0xC0,0x0F,0xF0,0x00,0x0F,0xC0,0x3F,0xFF, +0x00,0x0F,0xE0,0x7F,0xFF,0xE0,0x07,0xF0,0xFF,0xFF, +0xF8,0x03,0xF8,0xFF,0xFF,0xFF,0x01,0xFC,0xFF,0xFF, +0xFF,0xC0,0xFE,0xFF,0xFF,0xFF,0xF0,0x7F,0xFF,0x80, +0x7F,0xF8,0x3F,0xFF,0x00,0x07,0xFE,0x1F,0xFE,0x00, +0x00,0xFF,0x8F,0xFE,0x00,0x00,0x3F,0xC7,0xFE,0x00, +0x00,0x0F,0xF3,0xFE,0x00,0x00,0x07,0xFA,0x3F,0xC0, +0x00,0x00,0x3F,0x9F,0xE0,0x00,0x00,0x1F,0xF3,0xFC, +0x00,0x00,0x00,0xFF,0x4F,0xC0,0x00,0x00,0x0F,0xE7, +0xF0,0x00,0x00,0x07,0xF3,0xF8,0x00,0x00,0x07,0xF0, +0xFC,0x00,0x00,0x03,0xF8,0x7F,0x00,0x00,0x01,0xFC, +0x3F,0xC0,0x00,0x01,0xFE,0x0F,0xE0,0x00,0x01,0xFE, +0x07,0xF8,0x00,0x01,0xFF,0x01,0xFE,0x00,0x01,0xFF, +0x00,0x7F,0xC0,0x01,0xFF,0x80,0x3F,0xF8,0x07,0xFF, +0x80,0x0F,0xFF,0xFF,0xFF,0x80,0x03,0xFF,0xFF,0xFF, +0x80,0x00,0xFF,0xFF,0xFF,0x80,0x00,0x3F,0xFF,0xFF, +0x80,0x00,0x07,0xFF,0xFF,0x80,0x00,0x00,0xFF,0xFF, +0x00,0x00,0x00,0x0F,0xF8,0x00,0x00,0x09,0x9D,0x90, +0x02,0xEC,0xFF,0xFF,0xFF,0xFF,0xFD,0xFF,0xFF,0xFF, +0xFF,0xF0,0x00,0x00,0x00,0x07,0xC0,0x00,0x00,0x00, +0x1F,0x80,0x00,0x00,0x00,0x7E,0x00,0x00,0x00,0x01, +0xF8,0x00,0x00,0x00,0x07,0xE0,0x00,0x00,0x00,0x1F, +0xC0,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,0xFC, +0x00,0x00,0x00,0x03,0xF8,0x00,0x00,0x00,0x07,0xE0, +0x00,0x00,0x00,0x1F,0xC0,0x00,0x00,0x00,0x7F,0x00, +0x00,0x00,0x00,0xFC,0x00,0x00,0x00,0x03,0xF8,0x00, +0x00,0x00,0x07,0xE0,0x00,0x00,0x00,0x1F,0xC0,0x04, +0x00,0x00,0x0F,0xE0,0x01,0x00,0x00,0x07,0xF0,0x00, +0x40,0x00,0x03,0xF8,0x00,0x12,0x00,0x01,0xFC,0x00, +0x04,0x00,0x00,0xFE,0x00,0x01,0x20,0x00,0x7F,0x00, +0x00,0x48,0x00,0x3F,0x80,0x00,0x12,0x00,0x1F,0xC0, +0x00,0x05,0x00,0x0F,0xE0,0x00,0x00,0x00,0x3F,0xC0, +0x00,0x02,0xC0,0x0F,0xE0,0x00,0x00,0x00,0x3F,0xC0, +0x00,0x01,0x60,0x0F,0xE0,0x00,0x00,0x00,0x09,0x9E, +0x93,0xFA,0xE0,0x00,0x1F,0xF8,0x00,0x00,0x01,0xFF, +0xFE,0x00,0x00,0x0F,0xFF,0xFF,0x00,0x00,0x3F,0xFF, +0xFF,0x00,0x01,0xFF,0xFF,0xFF,0x00,0x03,0xFF,0xFF, +0xFF,0x00,0x0F,0xFF,0xFF,0xFF,0x00,0x3F,0xF8,0x07, +0xFF,0x00,0x7F,0xC0,0x03,0xFE,0x01,0xFF,0x00,0x03, +0xFE,0x03,0xFC,0x00,0x03,0xFC,0x0F,0xF0,0x00,0x03, +0xF8,0x1F,0xC0,0x00,0x07,0xF9,0x67,0xF0,0x00,0x00, +0xFE,0x0F,0xF0,0x00,0x03,0xFC,0x0F,0xE0,0x00,0x07, +0xF1,0x03,0xFC,0x00,0x03,0xFC,0x03,0xFE,0x00,0x1F, +0xF0,0x03,0xFF,0x00,0xFF,0xC0,0x03,0xFF,0xFF,0xFF, +0x00,0x03,0xFF,0xFF,0xFC,0x00,0x01,0xFF,0xFF,0xE0, +0x00,0x01,0xFF,0xFF,0x80,0x00,0x1F,0xFF,0xFF,0xC0, +0x00,0x7F,0xFF,0xFF,0xE0,0x01,0xFF,0xFF,0xFF,0xE0, +0x07,0xFF,0x00,0xFF,0xE0,0x1F,0xF0,0x00,0x7F,0xE0, +0x7F,0xC0,0x00,0x3F,0xE0,0xFF,0x00,0x00,0x3F,0xC3, +0xFC,0x00,0x00,0x3F,0xC7,0xF0,0x00,0x00,0x7F,0x8F, +0xE0,0x00,0x00,0x7F,0x3F,0xC0,0x00,0x00,0xFF,0xDF, +0xE0,0x00,0x00,0x1F,0xDF,0xE0,0x00,0x00,0x7F,0xC3, +0xF8,0x00,0x00,0x1F,0xC7,0xF8,0x00,0x00,0x7F,0x87, +0xF8,0x00,0x01,0xFE,0x0F,0xF8,0x00,0x07,0xFC,0x0F, +0xFC,0x00,0x1F,0xF0,0x1F,0xFE,0x01,0xFF,0xE0,0x1F, +0xFF,0xFF,0xFF,0x80,0x1F,0xFF,0xFF,0xFE,0x00,0x1F, +0xFF,0xFF,0xF8,0x00,0x1F,0xFF,0xFF,0xE0,0x00,0x0F, +0xFF,0xFF,0x00,0x00,0x07,0xFF,0xF8,0x00,0x00,0x01, +0xFF,0x80,0x00,0x09,0x9E,0x93,0xFA,0xE0,0x00,0x1F, +0xE0,0x00,0x00,0x01,0xFF,0xF8,0x00,0x00,0x0F,0xFF, +0xFC,0x00,0x00,0x7F,0xFF,0xFE,0x00,0x01,0xFF,0xFF, +0xFE,0x00,0x07,0xFF,0xFF,0xFE,0x00,0x1F,0xFF,0xFF, +0xFE,0x00,0x3F,0xFC,0x07,0xFE,0x00,0xFF,0xC0,0x03, +0xFE,0x03,0xFF,0x00,0x01,0xFC,0x07,0xFC,0x00,0x01, +0xFC,0x1F,0xF0,0x00,0x01,0xF8,0x3F,0xC0,0x00,0x03, +0xF8,0x7F,0x80,0x00,0x03,0xF0,0xFE,0x00,0x00,0x07, +0xE3,0xFC,0x00,0x00,0x0F,0xEA,0xFE,0x00,0x00,0x01, +0xFA,0xBF,0x80,0x00,0x00,0x7F,0x7F,0x00,0x00,0x01, +0xFE,0xFF,0x00,0x00,0x03,0xFC,0xFE,0x00,0x00,0x07, +0xFC,0x3F,0xC0,0x00,0x03,0xFE,0x3F,0xC0,0x00,0x0F, +0xFC,0x7F,0xC0,0x00,0x3F,0xF8,0x7F,0xE0,0x01,0xFF, +0xF0,0xFF,0xF0,0x0F,0xFF,0xE0,0xFF,0xFF,0xFF,0xDF, +0xC0,0xFF,0xFF,0xFF,0x3F,0x80,0xFF,0xFF,0xFC,0x7F, +0x00,0xFF,0xFF,0xF0,0xFE,0x00,0xFF,0xFF,0xC1,0xFC, +0x00,0x7F,0xFE,0x03,0xF0,0x00,0x1F,0xE0,0x07,0xEA, +0x00,0x00,0x00,0x03,0xF8,0x00,0x00,0x00,0x0F,0xE0, +0x3C,0x00,0x00,0x1F,0xC3,0xF8,0x00,0x00,0x3F,0x90, +0xFF,0x00,0x00,0x1F,0xC0,0xFE,0x00,0x00,0x7F,0x81, +0xFE,0x00,0x01,0xFE,0x03,0xFE,0x00,0x07,0xFC,0x03, +0xFE,0x00,0x1F,0xF0,0x07,0xFF,0x01,0xFF,0xC0,0x07, +0xFF,0xFF,0xFF,0x80,0x07,0xFF,0xFF,0xFE,0x00,0x07, +0xFF,0xFF,0xF8,0x00,0x07,0xFF,0xFF,0xC0,0x00,0x07, +0xFF,0xFF,0x00,0x00,0x03,0xFF,0xF8,0x00,0x00,0x00, +0xFF,0x80,0x00,0x00,0x01,0xD6,0x1C,0x01,0x7D,0xFF, +0xA0,0x34,0x06,0x80,0xD0,0x10,0x03,0x7F,0x80,0x01, +0xDC,0x9F,0x99,0x7D,0xFF,0xA0,0x34,0x06,0x80,0xD0, +0x10,0x03,0x7F,0xE0,0xF0,0xE1,0xE3,0xE8,0xF8,0x70, +0x20,0x09,0x93,0x94,0x53,0x00,0x00,0x00,0x00,0x00, +0x20,0x00,0x00,0x00,0x01,0xC0,0x00,0x00,0x00,0x1F, +0x80,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x07,0xFE, +0x00,0x00,0x00,0x3F,0xFC,0x00,0x00,0x03,0xFF,0xF8, +0x00,0x00,0x1F,0xFF,0xE0,0x00,0x00,0xFF,0xFE,0x00, +0x00,0x07,0xFF,0xF0,0x00,0x00,0x3F,0xFF,0x00,0x00, +0x03,0xFF,0xF8,0x00,0x00,0x1F,0xFF,0x80,0x00,0x00, +0xFF,0xFC,0x00,0x00,0x07,0xFF,0xC0,0x00,0x00,0x7F, +0xFE,0x00,0x00,0x03,0xFF,0xE0,0x00,0x00,0x0F,0xFF, +0x00,0x00,0x00,0x1F,0xF8,0x00,0x00,0x00,0x3F,0x80, +0x00,0x00,0x00,0x7F,0xC0,0x00,0x00,0x00,0xFF,0xF0, +0x00,0x00,0x00,0xFF,0xF8,0x00,0x00,0x00,0x7F,0xFE, +0x00,0x00,0x00,0x1F,0xFF,0x00,0x00,0x00,0x0F,0xFF, +0xC0,0x00,0x00,0x07,0xFF,0xE0,0x00,0x00,0x03,0xFF, +0xF8,0x00,0x00,0x00,0xFF,0xFC,0x00,0x00,0x00,0x7F, +0xFF,0x00,0x00,0x00,0x3F,0xFF,0x80,0x00,0x00,0x1F, +0xFF,0xE0,0x00,0x00,0x0F,0xFF,0xE0,0x00,0x00,0x03, +0xFF,0xC0,0x00,0x00,0x01,0xFF,0x80,0x00,0x00,0x00, +0xFF,0x00,0x00,0x00,0x00,0x7E,0x00,0x00,0x00,0x00, +0x1C,0x00,0x00,0x00,0x00,0x08,0x09,0xCC,0x90,0x8B, +0x0D,0xFF,0xFF,0xFF,0xFF,0xFF,0xA0,0x00,0x00,0x00, +0x00,0x28,0x00,0x00,0x00,0x00,0x06,0xFF,0xFF,0xFF, +0xFF,0xFF,0x09,0x93,0x94,0x53,0x04,0x00,0x00,0x00, +0x00,0x0E,0x00,0x00,0x00,0x00,0x1F,0x80,0x00,0x00, +0x00,0x3F,0xC0,0x00,0x00,0x00,0x7F,0xE0,0x00,0x00, +0x00,0xFF,0xF0,0x00,0x00,0x01,0xFF,0xFC,0x00,0x00, +0x01,0xFF,0xFE,0x00,0x00,0x00,0x7F,0xFF,0x00,0x00, +0x00,0x3F,0xFF,0x80,0x00,0x00,0x0F,0xFF,0xC0,0x00, +0x00,0x07,0xFF,0xF0,0x00,0x00,0x01,0xFF,0xF8,0x00, +0x00,0x00,0xFF,0xFC,0x00,0x00,0x00,0x3F,0xFE,0x00, +0x00,0x00,0x1F,0xFF,0x80,0x00,0x00,0x07,0xFF,0xC0, +0x00,0x00,0x03,0xFF,0xC0,0x00,0x00,0x00,0xFF,0x80, +0x00,0x00,0x00,0x7F,0x00,0x00,0x00,0x07,0xFE,0x00, +0x00,0x00,0x3F,0xFC,0x00,0x00,0x01,0xFF,0xF0,0x00, +0x00,0x1F,0xFF,0x80,0x00,0x00,0xFF,0xF8,0x00,0x00, +0x0F,0xFF,0xC0,0x00,0x00,0x7F,0xFE,0x00,0x00,0x07, +0xFF,0xF0,0x00,0x00,0x3F,0xFF,0x00,0x00,0x03,0xFF, +0xF8,0x00,0x00,0x1F,0xFF,0xC0,0x00,0x01,0xFF,0xFE, +0x00,0x00,0x07,0xFF,0xF0,0x00,0x00,0x0F,0xFF,0x00, +0x00,0x00,0x1F,0xF8,0x00,0x00,0x00,0x3F,0xC0,0x00, +0x00,0x00,0x7E,0x00,0x00,0x00,0x00,0xE0,0x00,0x00, +0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x9E,0x90, +0x02,0xE0,0x00,0x1F,0xF8,0x00,0x00,0x01,0xFF,0xFE, +0x00,0x00,0x0F,0xFF,0xFF,0x80,0x00,0x7F,0xFF,0xFF, +0x80,0x01,0xFF,0xFF,0xFF,0x80,0x07,0xFF,0xFF,0xFF, +0x80,0x1F,0xFF,0xFF,0xFF,0x80,0x3F,0xFC,0x07,0xFF, +0x80,0xFF,0xC0,0x03,0xFF,0x83,0xFF,0x00,0x01,0xFF, +0x07,0xFC,0x00,0x01,0xFF,0x1F,0xF0,0x00,0x01,0xFE, +0x3F,0xC0,0x00,0x03,0xFC,0x7F,0x80,0x00,0x03,0xFC, +0xFE,0x00,0x00,0x07,0xFC,0x7F,0x80,0x00,0x00,0xFE, +0xFE,0x00,0x00,0x01,0xFC,0x3C,0x00,0x00,0x03,0xFC, +0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x7F, +0x00,0x00,0x00,0x01,0xFE,0x00,0x00,0x00,0x07,0xF8, +0x00,0x00,0x00,0x1F,0xF0,0x00,0x00,0x00,0x7F,0xC0, +0x00,0x00,0x01,0xFF,0x00,0x00,0x00,0x07,0xFC,0x00, +0x00,0x00,0x1F,0xF0,0x00,0x00,0x00,0x7F,0xC0,0x00, +0x00,0x01,0xFF,0x00,0x00,0x00,0x07,0xFC,0x00,0x00, +0x00,0x1F,0xF0,0x00,0x00,0x00,0x7F,0xC0,0x00,0x00, +0x01,0xFF,0x00,0x00,0x00,0x03,0xFC,0x00,0x10,0x00, +0x01,0xFE,0x00,0x00,0x00,0x03,0xF8,0x00,0x08,0x00, +0x01,0xFE,0x00,0x03,0x00,0x00,0x7F,0x00,0x00,0xC0, +0x00,0x00,0x00,0x00,0x34,0x00,0x07,0xF0,0x00,0x00, +0x13,0x67,0x17,0x7D,0x40,0x00,0x00,0x00,0x03,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xFF, +0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xFF, +0xFF,0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xFF,0xFF, +0xFF,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF,0xFF, +0xFF,0x00,0x00,0x00,0x00,0x03,0xFF,0xFF,0xFF,0xFF, +0xFF,0x00,0x00,0x00,0x00,0x3F,0xFF,0xFF,0xFF,0xFF, +0xFE,0x00,0x00,0x00,0x01,0xFF,0xFF,0x80,0x07,0xFF, +0xFE,0x00,0x00,0x00,0x0F,0xFF,0xC0,0x00,0x01,0xFF, +0xFC,0x00,0x00,0x00,0xFF,0xF8,0x00,0x00,0x00,0xFF, +0xF8,0x00,0x00,0x07,0xFF,0x80,0x00,0x00,0x00,0xFF, +0xF0,0x00,0x00,0x3F,0xF8,0x00,0x00,0x00,0x00,0xFF, +0xE0,0x00,0x01,0xFF,0xC0,0x00,0x00,0x00,0x00,0xFF, +0x80,0x00,0x07,0xFC,0x00,0x00,0x00,0x00,0x01,0xFF, +0x00,0x00,0x3F,0xE0,0x00,0x00,0x00,0x00,0x03,0xFE, +0x00,0x01,0xFF,0x00,0x00,0x00,0x00,0x00,0x07,0xF8, +0x00,0x0F,0xF8,0x00,0x01,0xFC,0x00,0x00,0x0F,0xF0, +0x00,0x3F,0xC0,0x00,0x3F,0xFE,0x03,0xF8,0x1F,0xE0, +0x01,0xFE,0x00,0x03,0xFF,0xFC,0x0F,0xE0,0x3F,0x80, +0x07,0xF0,0x00,0x1F,0xFF,0xFC,0x3F,0x00,0xFF,0x00, +0x3F,0x80,0x01,0xFF,0xFF,0xF8,0xFC,0x01,0xFC,0x00, +0xFE,0x00,0x0F,0xFF,0xFF,0xF7,0xF0,0x07,0xF0,0x07, +0xF0,0x00,0x7F,0xFF,0xFF,0xDF,0xC0,0x0F,0xE0,0x1F, +0x80,0x03,0xFF,0xC0,0xFF,0xFF,0x00,0x3F,0x80,0xFE, +0x00,0x1F,0xF8,0x00,0xFF,0xF8,0x00,0x7E,0x03,0xF0, +0x00,0x7F,0xC0,0x00,0xFF,0xE0,0x01,0xF8,0x0F,0xC0, +0x03,0xFE,0x00,0x01,0xFF,0x80,0x07,0xF0,0x7F,0x00, +0x1F,0xF0,0x00,0x07,0xFE,0x00,0x0F,0xC1,0xF8,0x00, +0x7F,0x80,0x00,0x0F,0xF8,0x00,0x3F,0x07,0xE0,0x03, +0xFC,0x00,0x00,0x3F,0xC0,0x00,0xFC,0x3F,0x00,0x0F, +0xF0,0x00,0x00,0x7F,0x00,0x03,0xF2,0x1F,0x80,0x0F, +0xF0,0x00,0x00,0x3F,0x80,0x01,0xF8,0x7E,0x00,0x3F, +0x80,0x00,0x00,0xFE,0x00,0x07,0xE1,0xF8,0x01,0xFE, +0x00,0x00,0x03,0xF0,0x00,0x1F,0x91,0xF8,0x00,0xFE, +0x00,0x00,0x01,0xF8,0x00,0x0F,0xC7,0xE0,0x07,0xF8, +0x00,0x00,0x07,0xE0,0x00,0x7F,0x1F,0x80,0x1F,0xC0, +0x00,0x00,0x1F,0x80,0x01,0xF8,0x7E,0x00,0x7F,0x00, +0x00,0x00,0xFC,0x00,0x07,0xE2,0x3F,0x00,0x3F,0x80, +0x00,0x00,0x7E,0x00,0x07,0xF0,0xFC,0x00,0xFE,0x00, +0x00,0x03,0xF8,0x00,0x1F,0x83,0xF0,0x03,0xF8,0x00, +0x00,0x0F,0xC0,0x00,0xFE,0x0F,0xC0,0x0F,0xE0,0x00, +0x00,0x7F,0x00,0x03,0xF0,0x3F,0x00,0x3F,0x80,0x00, +0x01,0xFC,0x00,0x1F,0xC0,0xFC,0x00,0xFE,0x00,0x00, +0x0F,0xF0,0x00,0xFE,0x03,0xF8,0x01,0xFC,0x00,0x00, +0x3F,0xC0,0x03,0xF8,0x07,0xE0,0x07,0xF0,0x00,0x01, +0xFE,0x00,0x1F,0xC0,0x1F,0x80,0x1F,0xE0,0x00,0x0F, +0xF8,0x00,0xFF,0x00,0x7E,0x00,0x7F,0x80,0x00,0x7F, +0xE0,0x07,0xF8,0x01,0xFC,0x00,0xFF,0x00,0x07,0xFF, +0x80,0x7F,0xC0,0x07,0xF0,0x03,0xFE,0x00,0x3F,0xFE, +0x03,0xFE,0x00,0x0F,0xC0,0x07,0xFE,0x07,0xFF,0xFC, +0x3F,0xF0,0x00,0x3F,0x80,0x1F,0xFF,0xFF,0xFF,0xFF, +0xFF,0x80,0x00,0xFE,0x00,0x3F,0xFF,0xFF,0xBF,0xFF, +0xFC,0x00,0x01,0xFC,0x00,0x7F,0xFF,0xFC,0xFF,0xFF, +0xE0,0x00,0x07,0xF0,0x00,0xFF,0xFF,0xC1,0xFF,0xFF, +0x00,0x00,0x0F,0xE0,0x01,0xFF,0xFE,0x07,0xFF,0xF0, +0x00,0x00,0x3F,0xC0,0x01,0xFF,0xE0,0x0F,0xFF,0x80, +0x0F,0xE0,0x7F,0x80,0x00,0xFE,0x00,0x0F,0xF0,0x00, +0x7F,0x01,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x03, +0xFC,0x03,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x1F, +0xE0,0x07,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0xFF, +0x00,0x1F,0xF8,0x00,0x00,0x00,0x00,0x00,0x0F,0xF8, +0x00,0x3F,0xF0,0x00,0x00,0x00,0x00,0x00,0x7F,0xC0, +0x00,0x7F,0xF0,0x00,0x00,0x00,0x00,0x07,0xFF,0x00, +0x00,0xFF,0xF0,0x00,0x00,0x00,0x00,0x7F,0xF0,0x00, +0x01,0xFF,0xF8,0x00,0x00,0x00,0x07,0xFF,0x80,0x00, +0x03,0xFF,0xFC,0x00,0x00,0x00,0xFF,0xFC,0x00,0x00, +0x03,0xFF,0xFF,0xC0,0x00,0x7F,0xFF,0xE0,0x00,0x00, +0x07,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE,0x00,0x00,0x00, +0x07,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x00, +0x07,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00, +0x07,0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x00,0x00, +0x03,0xFF,0xFF,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00, +0x00,0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00, +0x00,0x1F,0xFF,0xE0,0x00,0x00,0x00,0x0D,0xDE,0x00, +0x03,0x70,0x00,0x00,0x07,0xF0,0x00,0x00,0x08,0x00, +0x00,0x01,0xFF,0x00,0x00,0x01,0x20,0x00,0x00,0x7F, +0xF0,0x00,0x00,0x00,0x00,0x00,0xFF,0xF8,0x00,0x00, +0x00,0x00,0x00,0xFD,0xF8,0x00,0x00,0x20,0x00,0x00, +0x3F,0xBF,0x80,0x00,0x04,0x00,0x00,0x0F,0xE3,0xF8, +0x00,0x00,0x00,0x00,0x0F,0xC3,0xF8,0x00,0x00,0x80, +0x00,0x03,0xF8,0x3F,0x80,0x00,0x12,0x00,0x00,0xFE, +0x03,0xF8,0x00,0x02,0x00,0x00,0x3F,0x80,0x3F,0x80, +0x00,0x00,0x00,0x7F,0x80,0x3F,0xC0,0x00,0x40,0x00, +0x0F,0xE0,0x03,0xF8,0x00,0x08,0x00,0x03,0xF8,0x00, +0x3F,0x80,0x00,0x00,0x07,0xF8,0x00,0x3F,0xC0,0x01, +0x00,0x00,0xFE,0x00,0x03,0xF8,0x00,0x00,0x01,0xFE, +0x00,0x03,0xFC,0x00,0x00,0x01,0xFC,0x00,0x01,0xFC, +0x00,0x00,0x03,0xFC,0x00,0x01,0xFE,0x00,0x20,0x00, +0x7F,0x00,0x00,0x1F,0xC0,0x00,0x00,0xFF,0x00,0x00, +0x1F,0xE0,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xE0,0x04, +0x80,0x3F,0xFF,0xFF,0xFF,0xFE,0x00,0x80,0x0F,0xFF, +0xFF,0xFF,0xFF,0xE0,0x00,0x1F,0xFF,0xFF,0xFF,0xFF, +0xF0,0x00,0x1F,0xE0,0x00,0x00,0x0F,0xF0,0x00,0x1F, +0xC0,0x00,0x00,0x07,0xF0,0x10,0x07,0xF8,0x00,0x00, +0x00,0xFF,0x02,0x41,0xFE,0x00,0x00,0x00,0x0F,0xF0, +0x40,0x7F,0x80,0x00,0x00,0x00,0xFF,0x00,0xFF,0x80, +0x00,0x00,0x00,0xFF,0x88,0x1F,0xE0,0x00,0x00,0x00, +0x0F,0xF1,0x07,0xF8,0x00,0x00,0x00,0x00,0xFF,0x0F, +0xF8,0x00,0x00,0x00,0x00,0xFF,0xA1,0xFE,0x00,0x00, +0x00,0x00,0x0F,0xF3,0xFE,0x00,0x00,0x00,0x00,0x0F, +0xFB,0xFC,0x00,0x00,0x00,0x00,0x07,0xF8,0x0B,0x1E, +0x1C,0x03,0x77,0xFF,0xFF,0xFF,0xC0,0x00,0x3F,0xFF, +0xFF,0xFF,0xC0,0x01,0xFF,0xFF,0xFF,0xFF,0xC0,0x0F, +0xFF,0xFF,0xFF,0xFF,0x00,0x7F,0xFF,0xFF,0xFF,0xFC, +0x03,0xFF,0xFF,0xFF,0xFF,0xF0,0x1F,0xFF,0xFF,0xFF, +0xFF,0xC0,0xFF,0x00,0x00,0x1F,0xFF,0x07,0xF8,0x00, +0x00,0x1F,0xF8,0x3F,0xC0,0x00,0x00,0x7F,0xE1,0xFE, +0x00,0x00,0x01,0xFF,0x0F,0xF0,0x00,0x00,0x07,0xF8, +0x7F,0x80,0x00,0x00,0x3F,0xE6,0x7F,0x80,0x00,0x00, +0x1F,0xE4,0x7F,0x80,0x00,0x00,0x3F,0xC3,0xFC,0x00, +0x00,0x03,0xFC,0x1F,0xE0,0x00,0x00,0x3F,0xE0,0xFF, +0x00,0x00,0x03,0xFE,0x07,0xF8,0x00,0x00,0xFF,0xE0, +0x3F,0xFF,0xFF,0xFF,0xFE,0x01,0xFF,0xFF,0xFF,0xFF, +0xE0,0x0F,0xFF,0xFF,0xFF,0xFC,0x00,0x7F,0xFF,0xFF, +0xFF,0xF0,0x03,0xFF,0xFF,0xFF,0xFF,0xE0,0x1F,0xFF, +0xFF,0xFF,0xFF,0x80,0xFF,0xFF,0xFF,0xFF,0xFF,0x07, +0xF8,0x00,0x00,0x7F,0xF8,0x3F,0xC0,0x00,0x00,0x7F, +0xE1,0xFE,0x00,0x00,0x00,0xFF,0x8F,0xF0,0x00,0x00, +0x03,0xFC,0x7F,0x80,0x00,0x00,0x1F,0xF3,0xFC,0x00, +0x00,0x00,0x7F,0x9F,0xE0,0x00,0x00,0x03,0xFF,0xBF, +0xE0,0x00,0x00,0x01,0xFE,0xFF,0x00,0x00,0x00,0x1F, +0xF7,0xF8,0x00,0x00,0x00,0xFF,0x47,0xF8,0x00,0x00, +0x01,0xFF,0x3F,0xC0,0x00,0x00,0x1F,0xF1,0xFE,0x00, +0x00,0x03,0xFF,0x8F,0xF0,0x00,0x00,0xFF,0xF8,0x8F, +0xFF,0xFF,0xFF,0xFF,0xF0,0x7F,0xFF,0xFF,0xFF,0xFF, +0x03,0xFF,0xFF,0xFF,0xFF,0xE0,0x1F,0xFF,0xFF,0xFF, +0xFE,0x00,0xFF,0xFF,0xFF,0xFF,0x80,0x07,0xFF,0xFF, +0xFF,0xC0,0x00,0x00,0x0D,0x1F,0x13,0xFB,0xC0,0x00, +0x00,0x1F,0xFC,0x00,0x00,0x00,0x00,0x0F,0xFF,0xFE, +0x00,0x00,0x00,0x01,0xFF,0xFF,0xFC,0x00,0x00,0x00, +0x3F,0xFF,0xFF,0xF8,0x00,0x00,0x07,0xFF,0xFF,0xFF, +0xE0,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xC0,0x00,0x0F, +0xFF,0xFF,0xFF,0xFF,0x00,0x00,0xFF,0xFE,0x00,0xFF, +0xFC,0x00,0x0F,0xFF,0x00,0x00,0xFF,0xE0,0x00,0x7F, +0xE0,0x00,0x03,0xFF,0x80,0x07,0xFE,0x00,0x00,0x07, +0xFE,0x00,0x7F,0xE0,0x00,0x00,0x1F,0xF0,0x07,0xFE, +0x00,0x00,0x00,0x7F,0xC0,0x3F,0xE0,0x00,0x00,0x03, +0xFF,0x03,0xFE,0x00,0x00,0x00,0x0F,0xF8,0x1F,0xE0, +0x00,0x00,0x00,0x7F,0xC1,0xFF,0x00,0x00,0x00,0x01, +0xFF,0x0F,0xF0,0x00,0x00,0x00,0x0F,0xF8,0x7F,0x80, +0x00,0x00,0x00,0x3C,0x07,0xFC,0x00,0x00,0x00,0x00, +0x00,0xA7,0xF8,0x00,0x00,0x00,0x00,0x00,0x7F,0xC0, +0x00,0x00,0x00,0x00,0x06,0xFF,0x80,0x00,0x00,0x00, +0x00,0x05,0xFF,0x80,0x00,0x00,0x00,0x00,0x04,0xBF, +0xC0,0x00,0x00,0x00,0x00,0x01,0xFE,0x00,0x00,0x00, +0x00,0x38,0x0F,0xF0,0x00,0x00,0x00,0x01,0xFD,0x07, +0xF8,0x00,0x00,0x00,0x03,0xFE,0x3F,0xC0,0x00,0x00, +0x00,0x1F,0xE8,0x1F,0xE0,0x00,0x00,0x00,0x3F,0xE0, +0xFF,0x80,0x00,0x00,0x03,0xFE,0x03,0xFE,0x00,0x00, +0x00,0x3F,0xF0,0x1F,0xF8,0x00,0x00,0x01,0xFF,0x00, +0x7F,0xE0,0x00,0x00,0x1F,0xF8,0x01,0xFF,0x80,0x00, +0x01,0xFF,0x80,0x0F,0xFE,0x00,0x00,0x3F,0xF8,0x00, +0x3F,0xFC,0x00,0x07,0xFF,0xC0,0x00,0xFF,0xFC,0x01, +0xFF,0xFC,0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xC0,0x00, +0x0F,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x3F,0xFF,0xFF, +0xFF,0x80,0x00,0x00,0x7F,0xFF,0xFF,0xF8,0x00,0x00, +0x00,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x01,0xFF,0xFF, +0xE0,0x00,0x00,0x00,0x00,0xFF,0xF0,0x00,0x00,0x0C, +0x5E,0x1C,0x03,0xC7,0xFF,0xFF,0xFF,0xC0,0x00,0x01, +0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x7F,0xFF,0xFF,0xFF, +0xF8,0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0x00,0x07,0xFF, +0xFF,0xFF,0xFF,0xF0,0x01,0xFF,0xFF,0xFF,0xFF,0xFE, +0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xC0,0x1F,0xE0,0x00, +0x01,0xFF,0xF8,0x07,0xF8,0x00,0x00,0x0F,0xFF,0x01, +0xFE,0x00,0x00,0x00,0xFF,0xE0,0x7F,0x80,0x00,0x00, +0x1F,0xF8,0x1F,0xE0,0x00,0x00,0x03,0xFF,0x07,0xF8, +0x00,0x00,0x00,0x7F,0xC1,0xFE,0x00,0x00,0x00,0x0F, +0xF8,0x7F,0x80,0x00,0x00,0x01,0xFE,0x1F,0xE0,0x00, +0x00,0x00,0x7F,0xC8,0xFF,0x00,0x00,0x00,0x01,0xFE, +0x3F,0xC0,0x00,0x00,0x00,0x7F,0xD5,0xFE,0x00,0x00, +0x00,0x01,0xFE,0xDF,0xF0,0x00,0x00,0x00,0x07,0xFE, +0x7F,0x80,0x00,0x00,0x00,0x3F,0xDF,0xE0,0x00,0x00, +0x00,0x1F,0xFA,0xFF,0x00,0x00,0x00,0x00,0xFF,0x3F, +0xC0,0x00,0x00,0x00,0x7F,0xD1,0xFE,0x00,0x00,0x00, +0x03,0xFC,0x7F,0x80,0x00,0x00,0x01,0xFF,0x1F,0xE0, +0x00,0x00,0x00,0x7F,0x87,0xF8,0x00,0x00,0x00,0x3F, +0xE1,0xFE,0x00,0x00,0x00,0x1F,0xF0,0x7F,0x80,0x00, +0x00,0x0F,0xFC,0x1F,0xE0,0x00,0x00,0x07,0xFE,0x07, +0xF8,0x00,0x00,0x03,0xFF,0x01,0xFE,0x00,0x00,0x03, +0xFF,0xC0,0x7F,0x80,0x00,0x0F,0xFF,0xE0,0x1F,0xFF, +0xFF,0xFF,0xFF,0xF0,0x07,0xFF,0xFF,0xFF,0xFF,0xF8, +0x01,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x7F,0xFF,0xFF, +0xFF,0xFC,0x00,0x1F,0xFF,0xFF,0xFF,0xFC,0x00,0x07, +0xFF,0xFF,0xFF,0xFC,0x00,0x01,0xFF,0xFF,0xFF,0xE0, +0x00,0x00,0x0B,0x1E,0x1C,0x03,0x7D,0xFF,0xFF,0xFF, +0xFF,0xFF,0xED,0xFF,0x00,0x00,0x00,0x00,0x0D,0xFF, +0x00,0x00,0x00,0x00,0x0A,0xFF,0x00,0x00,0x00,0x00, +0x0D,0xFF,0xFF,0xFF,0xFF,0xFF,0x8D,0xFF,0x00,0x00, +0x00,0x00,0x0D,0xFF,0x00,0x00,0x00,0x00,0x0D,0xFF, +0x00,0x00,0x00,0x00,0x0D,0xFF,0xFF,0xFF,0xFF,0xFF, +0xF0,0x0A,0x1E,0x1C,0x03,0x3D,0xFF,0xFF,0xFF,0xFF, +0xFF,0xDF,0xF0,0x00,0x00,0x00,0x0D,0xFF,0x00,0x00, +0x00,0x00,0xBF,0xF0,0x00,0x00,0x00,0x0D,0xFF,0xFF, +0xFF,0xFF,0xE0,0xDF,0xF0,0x00,0x00,0x00,0x0D,0xFF, +0x00,0x00,0x00,0x00,0xDF,0xF0,0x00,0x00,0x00,0x0C, +0xFF,0x00,0x00,0x00,0x00,0x0E,0x1F,0x13,0xFC,0x10, +0x00,0x00,0x07,0xFF,0x80,0x00,0x00,0x00,0x00,0x3F, +0xFF,0xFC,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xC0, +0x00,0x00,0x01,0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x03, +0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x07,0xFF,0xFF,0xFF, +0xFF,0xC0,0x00,0x07,0xFF,0xFF,0xFF,0xFF,0xF0,0x00, +0x07,0xFF,0xF8,0x01,0xFF,0xFC,0x00,0x07,0xFF,0xC0, +0x00,0x1F,0xFF,0x00,0x07,0xFF,0x80,0x00,0x03,0xFF, +0xC0,0x07,0xFF,0x00,0x00,0x00,0x7F,0xE0,0x03,0xFF, +0x00,0x00,0x00,0x1F,0xF8,0x03,0xFF,0x00,0x00,0x00, +0x07,0xFC,0x03,0xFF,0x00,0x00,0x00,0x01,0xFF,0x01, +0xFF,0x00,0x00,0x00,0x00,0x7F,0x81,0xFF,0x00,0x00, +0x00,0x00,0x3F,0xC0,0xFF,0x80,0x00,0x00,0x00,0x0F, +0xF0,0x7F,0x80,0x00,0x00,0x00,0x07,0xF8,0x7F,0xC0, +0x00,0x00,0x00,0x03,0xE0,0x3F,0xC0,0x00,0x00,0x00, +0x00,0x00,0x3F,0xE0,0x00,0x00,0x00,0x00,0x00,0x53, +0xFC,0x00,0x00,0x00,0x00,0x00,0x05,0xFF,0x80,0x00, +0x00,0x00,0x00,0x00,0x6F,0xF8,0x00,0x00,0x1F,0xFF, +0xFF,0xFB,0xFE,0x00,0x00,0x00,0x00,0x03,0xFE,0x5F, +0xE0,0x00,0x00,0x00,0x00,0x3F,0xCF,0xF8,0x00,0x00, +0x00,0x00,0x1F,0xF0,0x7F,0x80,0x00,0x00,0x00,0x01, +0xFE,0x3F,0xE0,0x00,0x00,0x00,0x00,0xFF,0x0F,0xF0, +0x00,0x00,0x00,0x00,0x7F,0x87,0xFC,0x00,0x00,0x00, +0x00,0x3F,0xC1,0xFF,0x00,0x00,0x00,0x00,0x1F,0xE0, +0xFF,0xC0,0x00,0x00,0x00,0x0F,0xF0,0x3F,0xF0,0x00, +0x00,0x00,0x0F,0xF8,0x0F,0xFC,0x00,0x00,0x00,0x1F, +0xFC,0x07,0xFF,0x00,0x00,0x00,0x1F,0xFE,0x01,0xFF, +0xE0,0x00,0x00,0x3F,0xFF,0x00,0x7F,0xFC,0x00,0x00, +0xFF,0xFF,0x00,0x1F,0xFF,0xE0,0x07,0xFF,0xFE,0x00, +0x07,0xFF,0xFF,0xFF,0xFF,0xFE,0x00,0x00,0xFF,0xFF, +0xFF,0xFF,0xFC,0x00,0x00,0x3F,0xFF,0xFF,0xFF,0xF8, +0x00,0x00,0x07,0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x00, +0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x00,0x0F,0xFF,0xFF, +0x80,0x00,0x00,0x00,0x00,0x3F,0xFC,0x00,0x00,0x00, +0x0B,0x9E,0x1C,0x03,0xCD,0xFF,0x00,0x00,0x00,0x03, +0xFF,0x7F,0xC0,0x00,0x00,0x00,0xFF,0xDF,0xF0,0x00, +0x00,0x00,0x3F,0xEB,0xFC,0x00,0x00,0x00,0x0F,0xFD, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x7F,0xC0,0x00,0x00, +0x00,0xFF,0xDF,0xF0,0x00,0x00,0x00,0x3F,0xF7,0xFC, +0x00,0x00,0x00,0x0F,0xFD,0xFF,0x00,0x00,0x00,0x03, +0xFC,0x02,0x1E,0x1C,0x01,0x7D,0xFF,0xDF,0xFD,0xFF, +0xDF,0xFD,0xFF,0xDF,0xFD,0xFF,0xDF,0xFA,0xFF,0x08, +0x1E,0x8F,0xFA,0xAD,0x00,0x00,0x00,0xFF,0xD0,0x00, +0x00,0x0F,0xFD,0x00,0x00,0x00,0xFF,0xD0,0x00,0x00, +0x0F,0xFD,0x00,0x00,0x00,0xFF,0xD0,0x00,0x00,0x0F, +0xF0,0x78,0x00,0x07,0xFD,0x7F,0x80,0x00,0x7F,0xBF, +0xE0,0x00,0x3F,0xDF,0xF0,0x00,0x3F,0xC7,0xF8,0x00, +0x1F,0xE3,0xFE,0x00,0x0F,0xF1,0xFF,0x00,0x0F,0xF8, +0xFF,0xC0,0x0F,0xF8,0x3F,0xF8,0x1F,0xFC,0x1F,0xFF, +0xFF,0xFC,0x07,0xFF,0xFF,0xFC,0x01,0xFF,0xFF,0xFE, +0x00,0x7F,0xFF,0xFE,0x00,0x1F,0xFF,0xFC,0x00,0x03, +0xFF,0xF8,0x00,0x00,0x3F,0xE0,0x00,0x0C,0x5E,0x1C, +0x03,0x77,0xF8,0x00,0x00,0x00,0x7F,0xF1,0xFE,0x00, +0x00,0x00,0x3F,0xF8,0x7F,0x80,0x00,0x00,0x1F,0xFC, +0x1F,0xE0,0x00,0x00,0x0F,0xFE,0x07,0xF8,0x00,0x00, +0x07,0xFF,0x01,0xFE,0x00,0x00,0x03,0xFF,0x80,0x7F, +0x80,0x00,0x01,0xFF,0xC0,0x1F,0xE0,0x00,0x00,0xFF, +0xE0,0x07,0xF8,0x00,0x00,0x7F,0xF0,0x01,0xFE,0x00, +0x00,0x3F,0xF8,0x00,0x7F,0x80,0x00,0x1F,0xFC,0x00, +0x1F,0xE0,0x00,0x0F,0xFE,0x00,0x07,0xF8,0x00,0x07, +0xFF,0x00,0x01,0xFE,0x00,0x03,0xFF,0x80,0x00,0x7F, +0x80,0x01,0xFF,0xC0,0x00,0x1F,0xE0,0x00,0xFF,0xE0, +0x00,0x07,0xF8,0x00,0x7F,0xF0,0x00,0x01,0xFE,0x00, +0x3F,0xF8,0x00,0x00,0x7F,0x80,0x1F,0xFC,0x00,0x00, +0x1F,0xE0,0x0F,0xFE,0x00,0x00,0x07,0xF8,0x07,0xFF, +0x00,0x00,0x01,0xFE,0x03,0xFF,0x80,0x00,0x00,0x7F, +0x81,0xFF,0xC0,0x00,0x00,0x1F,0xE0,0xFF,0xE0,0x00, +0x00,0x07,0xF8,0x7F,0xF0,0x00,0x00,0x01,0xFE,0x3F, +0xFC,0x00,0x00,0x00,0x7F,0x9F,0xFF,0x80,0x00,0x00, +0x1F,0xEF,0xFF,0xE0,0x00,0x00,0x07,0xFF,0xFF,0xFC, +0x00,0x00,0x01,0xFF,0xFF,0xFF,0x80,0x00,0x00,0x7F, +0xFF,0xFF,0xF0,0x00,0x00,0x1F,0xFF,0xE7,0xFC,0x00, +0x00,0x07,0xFF,0xF1,0xFF,0x80,0x00,0x01,0xFF,0xF8, +0x3F,0xF0,0x00,0x00,0x7F,0xFC,0x07,0xFE,0x00,0x00, +0x1F,0xFE,0x00,0xFF,0x80,0x00,0x07,0xFF,0x00,0x3F, +0xF0,0x00,0x01,0xFF,0x80,0x07,0xFE,0x00,0x00,0x7F, +0xC0,0x00,0xFF,0xC0,0x00,0x1F,0xE0,0x00,0x1F,0xF0, +0x00,0x07,0xF8,0x00,0x07,0xFE,0x00,0x01,0xFE,0x00, +0x00,0xFF,0xC0,0x00,0x7F,0x80,0x00,0x1F,0xF8,0x00, +0x1F,0xE0,0x00,0x03,0xFE,0x00,0x07,0xF8,0x00,0x00, +0xFF,0xC0,0x01,0xFE,0x00,0x00,0x1F,0xF8,0x00,0x7F, +0x80,0x00,0x03,0xFF,0x00,0x1F,0xE0,0x00,0x00,0x7F, +0xE0,0x07,0xF8,0x00,0x00,0x0F,0xF8,0x01,0xFE,0x00, +0x00,0x03,0xFF,0x00,0x7F,0x80,0x00,0x00,0x7F,0xE0, +0x1F,0xE0,0x00,0x00,0x0F,0xFC,0x07,0xF8,0x00,0x00, +0x01,0xFF,0x01,0xFE,0x00,0x00,0x00,0x7F,0xE0,0x7F, +0x80,0x00,0x00,0x0F,0xFC,0x1F,0xE0,0x00,0x00,0x01, +0xFF,0x87,0xF8,0x00,0x00,0x00,0x3F,0xE1,0xFE,0x00, +0x00,0x00,0x0F,0xFC,0x7F,0x80,0x00,0x00,0x01,0xFF, +0x9F,0xE0,0x00,0x00,0x00,0x3F,0xF0,0x09,0x1E,0x1C, +0x02,0xED,0xFF,0x00,0x00,0x00,0x0D,0xFF,0x00,0x00, +0x00,0x0D,0xFF,0x00,0x00,0x00,0x0D,0xFF,0x00,0x00, +0x00,0x0D,0xFF,0x00,0x00,0x00,0x0D,0xFF,0x00,0x00, +0x00,0x0D,0xFF,0x00,0x00,0x00,0x0A,0xFF,0x00,0x00, +0x00,0x0D,0xFF,0xFF,0xFF,0xFF,0xF0,0x0E,0x5E,0x18, +0x04,0x58,0xFF,0xF8,0x00,0x00,0x00,0x0F,0xFF,0xCF, +0xFF,0xE0,0x00,0x00,0x00,0xFF,0xFE,0x7F,0xFF,0x80, +0x00,0x00,0x0F,0xFF,0xEF,0xFF,0xF0,0x00,0x00,0x07, +0xFF,0xFC,0x7F,0xBF,0x80,0x00,0x00,0x3F,0xBF,0xDF, +0xEF,0xF0,0x00,0x00,0x0F,0xEF,0xF9,0xFF,0x3F,0x80, +0x00,0x00,0xFE,0x7F,0xCF,0xF8,0xFE,0x00,0x00,0x0F, +0xE3,0xFD,0xFE,0x3F,0xC0,0x00,0x07,0xF8,0xFF,0x8F, +0xF0,0xFE,0x00,0x00,0x3F,0x87,0xFB,0xFC,0x3F,0xC0, +0x00,0x1F,0xE1,0xFF,0x1F,0xE0,0xFE,0x00,0x00,0xFE, +0x0F,0xF7,0xF8,0x3F,0xC0,0x00,0x3F,0x83,0xFE,0x7F, +0xC0,0xFE,0x00,0x03,0xF8,0x1F,0xEF,0xF0,0x3F,0xC0, +0x01,0xFC,0x07,0xFC,0x7F,0x80,0xFE,0x00,0x0F,0xE0, +0x3F,0xDF,0xE0,0x3F,0xC0,0x07,0xF8,0x0F,0xF8,0xFF, +0x00,0xFE,0x00,0x3F,0x80,0x7F,0xBF,0xC0,0x3F,0xC0, +0x1F,0xE0,0x1F,0xF1,0xFE,0x00,0xFE,0x00,0xFE,0x00, +0xFF,0x7F,0x80,0x3F,0xC0,0x3F,0x80,0x3F,0xDF,0xE0, +0x0F,0xF0,0x1F,0xC0,0x0F,0xF8,0xFF,0x00,0x3F,0x80, +0xFE,0x00,0x7F,0xBF,0xC0,0x0F,0xF0,0x7F,0x80,0x1F, +0xF1,0xFE,0x00,0x3F,0x83,0xF8,0x00,0xFF,0x7F,0x80, +0x0F,0xF1,0xFE,0x00,0x3F,0xE3,0xFC,0x00,0x3F,0x8F, +0xE0,0x01,0xFE,0xFF,0x00,0x0F,0xF7,0xF8,0x00,0x7F, +0xBF,0xC0,0x03,0xFD,0xFC,0x00,0x1F,0xF1,0xFE,0x00, +0x0F,0xEF,0xE0,0x00,0xFF,0x7F,0x80,0x03,0xFF,0xF8, +0x00,0x3F,0xE7,0xFC,0x00,0x0F,0xFF,0x80,0x01,0xFF, +0x3F,0xE0,0x00,0x3F,0xF8,0x00,0x0F,0xF7,0xF8,0x00, +0x0F,0xFC,0x00,0x03,0xFD,0xFE,0x00,0x01,0xFF,0x00, +0x00,0xFF,0x0B,0x9E,0x1C,0x03,0xC8,0xFF,0x80,0x00, +0x00,0x03,0xFD,0xFF,0x80,0x00,0x00,0x07,0xFC,0x7F, +0xF0,0x00,0x00,0x01,0xFE,0xFF,0xF0,0x00,0x00,0x03, +0xFE,0x3F,0xFE,0x00,0x00,0x00,0xFF,0x7F,0xFE,0x00, +0x00,0x01,0xFF,0x1F,0xFF,0xC0,0x00,0x00,0x7F,0xBF, +0xFF,0xC0,0x00,0x00,0xFF,0x8F,0xFF,0xF8,0x00,0x00, +0x3F,0xDF,0xFF,0xF8,0x00,0x00,0x7F,0xBF,0xDF,0xF0, +0x00,0x00,0xFF,0x7F,0x9F,0xF0,0x00,0x01,0xFE,0xFF, +0x3F,0xF0,0x00,0x03,0xFD,0xFE,0x3F,0xE0,0x00,0x07, +0xFB,0xFC,0x3F,0xE0,0x00,0x0F,0xF7,0xF8,0x7F,0xE0, +0x00,0x1F,0xEF,0xF0,0x7F,0xC0,0x00,0x3F,0xDF,0xE0, +0xFF,0xC0,0x00,0x7F,0xBF,0xC0,0xFF,0xC0,0x00,0xFF, +0x7F,0x80,0xFF,0x80,0x01,0xFE,0xFF,0x01,0xFF,0x80, +0x03,0xFD,0xFE,0x01,0xFF,0x00,0x07,0xFB,0xFC,0x01, +0xFF,0x00,0x0F,0xF7,0xF8,0x03,0xFF,0x00,0x1F,0xEF, +0xF0,0x03,0xFE,0x00,0x3F,0xDF,0xE0,0x03,0xFE,0x00, +0x7F,0xBF,0xC0,0x07,0xFE,0x00,0xFF,0x7F,0x80,0x07, +0xFC,0x01,0xFE,0xFF,0x00,0x07,0xFC,0x03,0xFD,0xFE, +0x00,0x0F,0xFC,0x07,0xFB,0xFC,0x00,0x0F,0xF8,0x0F, +0xF7,0xF8,0x00,0x1F,0xF8,0x1F,0xEF,0xF0,0x00,0x1F, +0xF8,0x3F,0xDF,0xE0,0x00,0x1F,0xF0,0x7F,0xBF,0xC0, +0x00,0x3F,0xF0,0xFF,0x7F,0x80,0x00,0x3F,0xE1,0xFE, +0xFF,0x00,0x00,0x3F,0xE3,0xFD,0xFE,0x00,0x00,0x7F, +0xE7,0xFB,0xFC,0x00,0x00,0x7F,0xCF,0xF7,0xF8,0x00, +0x00,0x7F,0xDF,0xEF,0xF0,0x00,0x00,0xFF,0xFF,0xE3, +0xFC,0x00,0x00,0x1F,0xFF,0xF7,0xF8,0x00,0x00,0x1F, +0xFF,0xF1,0xFE,0x00,0x00,0x03,0xFF,0xFB,0xFC,0x00, +0x00,0x03,0xFF,0xF8,0xFF,0x00,0x00,0x00,0x7F,0xFD, +0xFE,0x00,0x00,0x00,0x7F,0xFC,0x7F,0x80,0x00,0x00, +0x0F,0xFE,0xFF,0x00,0x00,0x00,0x0F,0xFE,0x3F,0xC0, +0x00,0x00,0x01,0xFF,0x0E,0x5F,0x13,0xFC,0x10,0x00, +0x00,0x0F,0xFE,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF, +0xF8,0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF,0xC0,0x00, +0x00,0x00,0x7F,0xFF,0xFF,0xFC,0x00,0x00,0x00,0x3F, +0xFF,0xFF,0xFF,0x80,0x00,0x00,0x3F,0xFF,0xFF,0xFF, +0xF8,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0x00,0x00, +0x0F,0xFF,0xE0,0x0F,0xFF,0xE0,0x00,0x07,0xFF,0xC0, +0x00,0x7F,0xFC,0x00,0x03,0xFF,0xC0,0x00,0x07,0xFF, +0x80,0x01,0xFF,0xC0,0x00,0x00,0x7F,0xF0,0x00,0xFF, +0xE0,0x00,0x00,0x0F,0xFC,0x00,0x3F,0xE0,0x00,0x00, +0x01,0xFF,0x80,0x1F,0xF0,0x00,0x00,0x00,0x3F,0xF0, +0x07,0xF8,0x00,0x00,0x00,0x07,0xFC,0x03,0xFE,0x00, +0x00,0x00,0x00,0xFF,0x80,0xFF,0x00,0x00,0x00,0x00, +0x1F,0xE0,0x7F,0xC0,0x00,0x00,0x00,0x07,0xFC,0x83, +0xFC,0x00,0x00,0x00,0x00,0x1F,0xE1,0xFE,0x00,0x00, +0x00,0x00,0x07,0xFD,0x4F,0xF0,0x00,0x00,0x00,0x00, +0x1F,0xED,0xFF,0x00,0x00,0x00,0x00,0x00,0x7F,0xDF, +0xF8,0x00,0x00,0x00,0x00,0x03,0xFD,0xFE,0x00,0x00, +0x00,0x00,0x01,0xFF,0x97,0xF8,0x00,0x00,0x00,0x00, +0x0F,0xF1,0xFE,0x00,0x00,0x00,0x00,0x07,0xFD,0x07, +0xF8,0x00,0x00,0x00,0x00,0x3F,0xC1,0xFF,0x00,0x00, +0x00,0x00,0x1F,0xF0,0x3F,0xC0,0x00,0x00,0x00,0x07, +0xF8,0x0F,0xF8,0x00,0x00,0x00,0x03,0xFE,0x01,0xFF, +0x00,0x00,0x00,0x01,0xFF,0x00,0x7F,0xE0,0x00,0x00, +0x00,0xFF,0xC0,0x0F,0xF8,0x00,0x00,0x00,0x7F,0xE0, +0x01,0xFF,0x80,0x00,0x00,0x3F,0xF8,0x00,0x7F,0xF0, +0x00,0x00,0x1F,0xFC,0x00,0x0F,0xFE,0x00,0x00,0x0F, +0xFE,0x00,0x01,0xFF,0xE0,0x00,0x1F,0xFF,0x00,0x00, +0x3F,0xFF,0x80,0x3F,0xFF,0x80,0x00,0x07,0xFF,0xFF, +0xFF,0xFF,0xC0,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xE0, +0x00,0x00,0x0F,0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x01, +0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x00,0x1F,0xFF,0xFF, +0xF0,0x00,0x00,0x00,0x00,0xFF,0xFF,0xE0,0x00,0x00, +0x00,0x00,0x03,0xFF,0x80,0x00,0x00,0x0B,0x1E,0x1C, +0x03,0x77,0xFF,0xFF,0xFF,0xE0,0x00,0x3F,0xFF,0xFF, +0xFF,0xF0,0x01,0xFF,0xFF,0xFF,0xFF,0xE0,0x0F,0xFF, +0xFF,0xFF,0xFF,0xC0,0x7F,0xFF,0xFF,0xFF,0xFF,0x03, +0xFF,0xFF,0xFF,0xFF,0xFC,0x1F,0xFF,0xFF,0xFF,0xFF, +0xF0,0xFF,0x00,0x00,0x07,0xFF,0x87,0xF8,0x00,0x00, +0x07,0xFE,0x3F,0xC0,0x00,0x00,0x1F,0xF2,0x3F,0xC0, +0x00,0x00,0x0F,0xF9,0xFE,0x00,0x00,0x00,0x3F,0xCF, +0xF0,0x00,0x00,0x01,0xFF,0xDF,0xF0,0x00,0x00,0x00, +0xFF,0x7F,0x80,0x00,0x00,0x07,0xFC,0x7F,0x80,0x00, +0x00,0x0F,0xF3,0xFC,0x00,0x00,0x00,0xFF,0x9F,0xE0, +0x00,0x00,0x0F,0xFC,0xFF,0x00,0x00,0x00,0xFF,0xC7, +0xF8,0x00,0x00,0x0F,0xFE,0x3F,0xC0,0x00,0x03,0xFF, +0xE1,0xFF,0xFF,0xFF,0xFF,0xFE,0x11,0xFF,0xFF,0xFF, +0xFF,0xFC,0x0F,0xFF,0xFF,0xFF,0xFF,0x80,0x7F,0xFF, +0xFF,0xFF,0xF8,0x03,0xFF,0xFF,0xFF,0xFE,0x00,0x1F, +0xFF,0xFF,0xFF,0x00,0x01,0xBF,0xE0,0x00,0x00,0x00, +0x01,0xBF,0xE0,0x00,0x00,0x00,0x01,0xBF,0xE0,0x00, +0x00,0x00,0x01,0x3F,0xE0,0x00,0x00,0x00,0x00,0x0E, +0x60,0x93,0xDC,0x10,0x00,0x00,0x0F,0xFC,0x00,0x00, +0x00,0x00,0x00,0x3F,0xFF,0xF0,0x00,0x00,0x00,0x00, +0x7F,0xFF,0xFF,0x80,0x00,0x00,0x00,0x7F,0xFF,0xFF, +0xF8,0x00,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0x80,0x00, +0x00,0x3F,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x1F,0xFF, +0xFF,0xFF,0xFE,0x00,0x00,0x0F,0xFF,0xC0,0x0F,0xFF, +0xC0,0x00,0x07,0xFF,0x80,0x00,0x7F,0xF8,0x00,0x03, +0xFF,0x80,0x00,0x07,0xFF,0x00,0x01,0xFF,0xC0,0x00, +0x00,0xFF,0xE0,0x00,0xFF,0xC0,0x00,0x00,0x0F,0xFC, +0x00,0x3F,0xE0,0x00,0x00,0x01,0xFF,0x00,0x1F,0xF0, +0x00,0x00,0x00,0x3F,0xE0,0x07,0xF8,0x00,0x00,0x00, +0x0F,0xF8,0x03,0xFE,0x00,0x00,0x00,0x01,0xFF,0x00, +0xFF,0x00,0x00,0x00,0x00,0x3F,0xC0,0x7F,0xC0,0x00, +0x00,0x00,0x0F,0xF8,0x83,0xFC,0x00,0x00,0x00,0x00, +0x3F,0xC1,0xFE,0x00,0x00,0x00,0x00,0x0F,0xF9,0x2F, +0xF0,0x00,0x00,0x00,0x00,0x3F,0xC7,0xF8,0x00,0x00, +0x00,0x00,0x0F,0xFB,0x7F,0xC0,0x00,0x00,0x00,0x00, +0x3F,0xD7,0xFE,0x00,0x00,0x00,0x00,0x01,0xFE,0x7F, +0x80,0x00,0x00,0x00,0x00,0xFF,0xA5,0xFE,0x00,0x00, +0x00,0x00,0x07,0xF8,0x7F,0x80,0x00,0x00,0x00,0x03, +0xFE,0x41,0xFE,0x00,0x00,0x00,0x00,0x1F,0xE0,0x7F, +0xC0,0x00,0x04,0x00,0x0F,0xF8,0x0F,0xF0,0x00,0x01, +0xE0,0x03,0xFC,0x03,0xFE,0x00,0x00,0xFE,0x01,0xFF, +0x00,0x7F,0xC0,0x00,0x3F,0xE0,0xFF,0x80,0x1F,0xF0, +0x00,0x0F,0xFC,0x3F,0xE0,0x03,0xFE,0x00,0x07,0xFF, +0xDF,0xF0,0x00,0xFF,0xC0,0x00,0x7F,0xFF,0xF8,0x00, +0x1F,0xFC,0x00,0x07,0xFF,0xFE,0x00,0x03,0xFF,0x80, +0x00,0x7F,0xFF,0x00,0x00,0x7F,0xF8,0x00,0x07,0xFF, +0x80,0x00,0x0F,0xFF,0xC0,0x0F,0xFF,0xC0,0x00,0x01, +0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x3F,0xFF,0xFF, +0xFF,0xFF,0x80,0x00,0x07,0xFF,0xFF,0xFF,0xFF,0xF8, +0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x07, +0xFF,0xFF,0xFC,0xFF,0xF0,0x00,0x00,0x7F,0xFF,0xF8, +0x0F,0xFF,0x00,0x00,0x01,0xFF,0xE0,0x01,0xFF,0x80, +0x00,0x00,0x00,0x00,0x00,0x1F,0xE0,0x00,0x00,0x00, +0x00,0x00,0x01,0xF8,0x00,0x00,0x00,0x00,0x00,0x00, +0x1C,0x0C,0x9E,0x1C,0x03,0xC7,0xFF,0xFF,0xFF,0xFC, +0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x1F,0xFF, +0xFF,0xFF,0xFF,0xC0,0x03,0xFF,0xFF,0xFF,0xFF,0xFC, +0x00,0x8F,0xFF,0xFF,0xFF,0xFF,0xFC,0x01,0xFF,0xFF, +0xFF,0xFF,0xFF,0xC0,0x3F,0xC0,0x00,0x00,0x7F,0xFC, +0x07,0xF8,0x00,0x00,0x03,0xFF,0x80,0xFF,0x00,0x00, +0x00,0x1F,0xF8,0x1F,0xE0,0x00,0x00,0x01,0xFF,0x03, +0xFC,0x00,0x00,0x00,0x1F,0xE0,0x7F,0x80,0x00,0x00, +0x03,0xFE,0x19,0xFE,0x00,0x00,0x00,0x07,0xF8,0x3F, +0xC0,0x00,0x00,0x01,0xFF,0x07,0xF8,0x00,0x00,0x00, +0x3F,0xC1,0x1F,0xE0,0x00,0x00,0x01,0xFF,0x03,0xFC, +0x00,0x00,0x00,0x7F,0xC0,0x7F,0x80,0x00,0x00,0x3F, +0xF8,0x0F,0xF0,0x00,0x00,0x3F,0xFE,0x01,0xFF,0xFF, +0xFF,0xFF,0xFF,0x80,0x3F,0xFF,0xFF,0xFF,0xFF,0xE0, +0x07,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0xFF,0xFF,0xFF, +0xFF,0xFC,0x00,0x1F,0xFF,0xFF,0xFF,0xFE,0x00,0x03, +0xFF,0xFF,0xFF,0xFE,0x00,0x00,0x7F,0xFF,0xFF,0xFF, +0x00,0x00,0x0F,0xF0,0x00,0x3F,0xF0,0x00,0x01,0xFE, +0x00,0x01,0xFF,0x80,0x00,0x3F,0xC0,0x00,0x1F,0xF8, +0x00,0x07,0xF8,0x00,0x01,0xFF,0x80,0x00,0xFF,0x00, +0x00,0x1F,0xF0,0x00,0x1F,0xE0,0x00,0x01,0xFF,0x00, +0x03,0xFC,0x00,0x00,0x1F,0xF0,0x00,0x7F,0x80,0x00, +0x03,0xFF,0x00,0x0F,0xF0,0x00,0x00,0x3F,0xE0,0x01, +0xFE,0x00,0x00,0x03,0xFE,0x00,0x3F,0xC0,0x00,0x00, +0x7F,0xE0,0x07,0xF8,0x00,0x00,0x07,0xFC,0x01,0x1F, +0xE0,0x00,0x00,0x0F,0xF8,0x03,0xFC,0x00,0x00,0x00, +0xFF,0x80,0x7F,0x80,0x00,0x00,0x1F,0xF8,0x0F,0xF0, +0x00,0x00,0x01,0xFF,0x02,0x3F,0xC0,0x00,0x00,0x03, +0xFE,0x07,0xF8,0x00,0x00,0x00,0x3F,0xE0,0xFF,0x00, +0x00,0x00,0x07,0xFE,0x1F,0xE0,0x00,0x00,0x00,0x7F, +0xC4,0x7F,0x80,0x00,0x00,0x00,0xFF,0x91,0xFE,0x00, +0x00,0x00,0x01,0xFF,0x3F,0xC0,0x00,0x00,0x00,0x1F, +0xF0,0x0B,0xDF,0x13,0xFB,0x70,0x00,0x01,0xFF,0xC0, +0x00,0x00,0x00,0x1F,0xFF,0xFC,0x00,0x00,0x00,0xFF, +0xFF,0xFF,0x80,0x00,0x03,0xFF,0xFF,0xFF,0xE0,0x00, +0x07,0xFF,0xFF,0xFF,0xF0,0x00,0x0F,0xFF,0xFF,0xFF, +0xF8,0x00,0x1F,0xFF,0xFF,0xFF,0xFC,0x00,0x3F,0xFE, +0x00,0x3F,0xFE,0x00,0x7F,0xF0,0x00,0x07,0xFF,0x00, +0x7F,0xC0,0x00,0x01,0xFF,0x80,0xFF,0x80,0x00,0x00, +0xFF,0x88,0x1F,0xE0,0x00,0x00,0x0F,0xF8,0x3F,0xC0, +0x00,0x00,0x07,0xF8,0x3F,0xC0,0x00,0x00,0x07,0xFD, +0x27,0xF8,0x00,0x00,0x00,0x7F,0x87,0xF8,0x00,0x00, +0x00,0x00,0x07,0xFC,0x00,0x00,0x00,0x00,0x03,0xFC, +0x00,0x00,0x00,0x00,0x03,0xFE,0x00,0x00,0x00,0x00, +0x03,0xFF,0x80,0x00,0x00,0x00,0x01,0xFF,0xE0,0x00, +0x00,0x00,0x01,0xFF,0xFE,0x00,0x00,0x00,0x00,0xFF, +0xFF,0xC0,0x00,0x00,0x00,0x7F,0xFF,0xFE,0x00,0x00, +0x00,0x3F,0xFF,0xFF,0xC0,0x00,0x00,0x0F,0xFF,0xFF, +0xFC,0x00,0x00,0x07,0xFF,0xFF,0xFF,0x00,0x00,0x00, +0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x3F,0xFF,0xFF,0xF0, +0x00,0x00,0x03,0xFF,0xFF,0xF8,0x00,0x00,0x00,0x3F, +0xFF,0xFC,0x00,0x00,0x00,0x03,0xFF,0xFE,0x00,0x00, +0x00,0x00,0x7F,0xFF,0x00,0x00,0x00,0x00,0x0F,0xFF, +0x00,0x00,0x00,0x00,0x03,0xFF,0x80,0x00,0x00,0x00, +0x00,0xFF,0x80,0x00,0x00,0x00,0x00,0x7F,0x80,0x00, +0x00,0x00,0x00,0x7F,0xDF,0xE0,0x00,0x00,0x00,0x7F, +0xE3,0xFC,0x00,0x00,0x00,0x07,0xFB,0xFE,0x00,0x00, +0x00,0x07,0xFC,0x3F,0xC0,0x00,0x00,0x00,0xFF,0x3F, +0xE0,0x00,0x00,0x00,0xFF,0x3F,0xE0,0x00,0x00,0x01, +0xFE,0x1F,0xF0,0x00,0x00,0x01,0xFE,0x1F,0xF8,0x00, +0x00,0x03,0xFE,0x0F,0xFC,0x00,0x00,0x07,0xFC,0x0F, +0xFF,0x00,0x00,0x0F,0xFC,0x07,0xFF,0xC0,0x00,0x3F, +0xF8,0x03,0xFF,0xF8,0x01,0xFF,0xF0,0x01,0xFF,0xFF, +0xFF,0xFF,0xE0,0x00,0xFF,0xFF,0xFF,0xFF,0xC0,0x00, +0x7F,0xFF,0xFF,0xFF,0x80,0x00,0x1F,0xFF,0xFF,0xFF, +0x00,0x00,0x07,0xFF,0xFF,0xFC,0x00,0x00,0x01,0xFF, +0xFF,0xE0,0x00,0x00,0x00,0x0F,0xFF,0x00,0x00,0x0C, +0x1E,0x08,0x03,0x4D,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xD0,0x00,0x00,0xFF,0x00,0x00,0x0D,0x00,0x00,0x0F, +0xF0,0x00,0x00,0xD0,0x00,0x00,0xFF,0x00,0x00,0x0D, +0x00,0x00,0x0F,0xF0,0x00,0x00,0xD0,0x00,0x00,0xFF, +0x00,0x00,0x0D,0x00,0x00,0x0F,0xF0,0x00,0x00,0xD0, +0x00,0x00,0xFF,0x00,0x00,0x0A,0x00,0x00,0x0F,0xF0, +0x00,0x00,0x0B,0x9E,0x9F,0xFB,0xCD,0xFF,0x00,0x00, +0x00,0x03,0xFF,0x7F,0xC0,0x00,0x00,0x00,0xFF,0xDF, +0xF0,0x00,0x00,0x00,0x3F,0xF7,0xFC,0x00,0x00,0x00, +0x0F,0xFD,0xFF,0x00,0x00,0x00,0x03,0xFF,0x7F,0xC0, +0x00,0x00,0x00,0xFF,0x7F,0x80,0x00,0x00,0x03,0xFF, +0x2F,0xF0,0x00,0x00,0x00,0xFF,0x1F,0xE0,0x00,0x00, +0x03,0xFE,0x3F,0xE0,0x00,0x00,0x07,0xFC,0x3F,0xC0, +0x00,0x00,0x1F,0xF0,0x7F,0xC0,0x00,0x00,0x3F,0xE0, +0x7F,0xC0,0x00,0x00,0xFF,0x80,0xFF,0xC0,0x00,0x03, +0xFF,0x00,0xFF,0xE0,0x00,0x1F,0xFC,0x01,0xFF,0xF8, +0x01,0xFF,0xF0,0x01,0xFF,0xFF,0xFF,0xFF,0xE0,0x01, +0xFF,0xFF,0xFF,0xFF,0x80,0x01,0xFF,0xFF,0xFF,0xFC, +0x00,0x00,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0xFF,0xFF, +0xFF,0x80,0x00,0x00,0x3F,0xFF,0xFC,0x00,0x00,0x00, +0x07,0xFF,0x80,0x00,0x00,0x0D,0xDE,0x00,0x03,0x77, +0xF8,0x00,0x00,0x00,0x00,0x0F,0xF8,0xFF,0x80,0x00, +0x00,0x00,0x03,0xFE,0x7F,0x80,0x00,0x00,0x00,0x03, +0xFC,0x7F,0xC0,0x00,0x00,0x00,0x07,0xFC,0x3F,0xC0, +0x00,0x00,0x00,0x07,0xFC,0x3F,0xC0,0x00,0x00,0x00, +0x07,0xF8,0x3F,0xE0,0x00,0x00,0x00,0x0F,0xF8,0x1F, +0xE0,0x00,0x00,0x00,0x0F,0xF0,0x1F,0xF0,0x00,0x00, +0x00,0x1F,0xF0,0x0F,0xF0,0x00,0x00,0x00,0x1F,0xF0, +0x0F,0xF0,0x00,0x00,0x00,0x1F,0xE0,0x0F,0xF8,0x00, +0x00,0x00,0x3F,0xE0,0x07,0xF8,0x00,0x00,0x00,0x3F, +0xC0,0x07,0xF8,0x00,0x00,0x00,0x7F,0xC0,0x03,0xFC, +0x00,0x00,0x00,0x7F,0xC0,0x03,0xFC,0x00,0x00,0x00, +0x7F,0x80,0x01,0xFE,0x00,0x00,0x00,0xFF,0x81,0x00, +0x3F,0xC0,0x00,0x00,0x1F,0xE0,0x00,0x1F,0xE0,0x00, +0x00,0x3F,0xE0,0x00,0x1F,0xE0,0x00,0x00,0x3F,0xC0, +0x00,0x0F,0xF0,0x00,0x00,0x7F,0xC0,0x20,0x01,0xFE, +0x00,0x00,0x0F,0xF0,0x00,0x00,0xFF,0x00,0x00,0x1F, +0xF0,0x00,0x00,0xFF,0x00,0x00,0x1F,0xE0,0x00,0x00, +0x7F,0x00,0x00,0x1F,0xE0,0x04,0x00,0x0F,0xF0,0x00, +0x07,0xF8,0x00,0x00,0x07,0xF8,0x00,0x0F,0xF8,0x00, +0x00,0x07,0xF8,0x00,0x0F,0xF0,0x00,0x00,0x03,0xF8, +0x00,0x0F,0xF0,0x00,0x00,0x03,0xFC,0x00,0x1F,0xF0, +0x00,0x80,0x00,0x3F,0x80,0x03,0xFC,0x00,0x00,0x00, +0x3F,0xC0,0x07,0xF8,0x00,0x00,0x00,0x1F,0xC0,0x07, +0xF8,0x00,0x00,0x00,0x1F,0xE0,0x0F,0xF8,0x00,0x10, +0x00,0x01,0xFC,0x01,0xFE,0x00,0x00,0x00,0x01,0xFE, +0x03,0xFC,0x00,0x00,0x00,0x00,0xFE,0x03,0xFC,0x00, +0x00,0x00,0x00,0xFE,0x07,0xFC,0x00,0x02,0x00,0x00, +0x0F,0xE0,0xFF,0x00,0x00,0x00,0x00,0x0F,0xF1,0xFE, +0x00,0x00,0x40,0x00,0x00,0xFE,0x3F,0xC0,0x00,0x08, +0x00,0x00,0x0F,0xEF,0xF0,0x00,0x00,0x00,0x00,0x0F, +0xEF,0xE0,0x00,0x01,0x00,0x00,0x00,0xFF,0xFC,0x00, +0x00,0x20,0x00,0x00,0x0F,0xFF,0x00,0x00,0x04,0x80, +0x00,0x00,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x7F, +0x80,0x00,0x00,0x14,0x5E,0x04,0x05,0x37,0xF8,0x00, +0x00,0x00,0xFF,0xE0,0x00,0x00,0x03,0xFD,0xFF,0x00, +0x00,0x00,0x3F,0xF8,0x00,0x00,0x01,0xFF,0x3F,0xC0, +0x00,0x00,0x0F,0xFE,0x00,0x00,0x00,0x7F,0xA1,0xFE, +0x00,0x00,0x00,0xFF,0xF8,0x00,0x00,0x03,0xFC,0x7F, +0xC0,0x00,0x00,0x3F,0xFE,0x00,0x00,0x01,0xFF,0x0F, +0xF0,0x00,0x00,0x1F,0xFF,0x80,0x00,0x00,0x7F,0x90, +0x7F,0x80,0x00,0x00,0xFE,0xFE,0x00,0x00,0x03,0xFC, +0x0F,0xF0,0x00,0x00,0x3F,0xBF,0x80,0x00,0x01,0xFF, +0x03,0xFC,0x00,0x00,0x1F,0xEF,0xF0,0x00,0x00,0x7F, +0x88,0x1F,0xE0,0x00,0x00,0xFE,0x3F,0x80,0x00,0x03, +0xFC,0x03,0xF8,0x00,0x00,0x7F,0x8F,0xE0,0x00,0x00, +0xFF,0x12,0x1F,0xE0,0x00,0x03,0xF8,0x3F,0x80,0x00, +0x0F,0xF0,0x03,0xF8,0x00,0x01,0xFE,0x0F,0xF0,0x00, +0x03,0xFC,0x20,0x1F,0xE0,0x00,0x0F,0xE0,0x3F,0x80, +0x00,0x3F,0xC0,0x03,0xF8,0x00,0x07,0xF8,0x0F,0xE0, +0x00,0x0F,0xF0,0x00,0xFE,0x00,0x01,0xFC,0x01,0xFC, +0x00,0x03,0xFC,0x10,0x07,0xF8,0x00,0x0F,0xE0,0x0F, +0xE0,0x00,0x3F,0xC0,0x00,0xFE,0x00,0x07,0xF8,0x03, +0xFC,0x00,0x0F,0xF0,0x00,0x3F,0x80,0x01,0xFC,0x00, +0x7F,0x00,0x03,0xFC,0x00,0x0F,0xF0,0x00,0x7F,0x00, +0x1F,0xC0,0x01,0xFE,0x00,0x03,0xFC,0x00,0x3F,0xC0, +0x07,0xF8,0x00,0x7F,0x80,0x80,0x0F,0xE0,0x01,0xFC, +0x00,0x1F,0xC0,0x03,0xFC,0x00,0x03,0xFC,0x00,0x7F, +0x00,0x07,0xF0,0x01,0xFE,0x00,0x00,0x7F,0x00,0x3F, +0xC0,0x00,0xFE,0x00,0x7F,0x80,0x00,0x1F,0xC0,0x0F, +0xE0,0x00,0x3F,0x80,0x1F,0xE0,0x00,0x07,0xF0,0x03, +0xF8,0x00,0x0F,0xF0,0x07,0xF8,0x00,0x01,0xFC,0x01, +0xFE,0x00,0x03,0xFC,0x01,0xFC,0x00,0x00,0x3F,0x80, +0x7F,0x00,0x00,0x7F,0x00,0xFF,0x00,0x00,0x0F,0xE0, +0x1F,0xC0,0x00,0x1F,0xE0,0x3F,0xC0,0x00,0x03,0xF8, +0x07,0xF0,0x00,0x07,0xF8,0x0F,0xE0,0x00,0x00,0xFE, +0x03,0xF8,0x00,0x00,0xFE,0x03,0xF8,0x00,0x00,0x1F, +0xC0,0xFE,0x00,0x00,0x3F,0x81,0xFE,0x00,0x00,0x07, +0xF0,0x3F,0x80,0x00,0x0F,0xF0,0x7F,0x80,0x00,0x01, +0xFC,0x1F,0xE0,0x00,0x03,0xFC,0x1F,0xC0,0x00,0x00, +0x3F,0x07,0xF0,0x00,0x00,0x7F,0x07,0xF0,0x01,0x00, +0x01,0xFC,0x3F,0x80,0x00,0x03,0xFC,0x7F,0x80,0x00, +0x00,0x7F,0x1F,0xC0,0x00,0x00,0x7F,0x1F,0xC0,0x00, +0x00,0x0F,0xC7,0xF0,0x00,0x00,0x1F,0xC7,0xF0,0x00, +0x00,0x03,0xF1,0xFC,0x00,0x00,0x07,0xFB,0xFC,0x00, +0x00,0x00,0xFE,0xFF,0x00,0x00,0x01,0xFE,0xFF,0x00, +0x00,0x00,0x3F,0xBF,0x80,0x00,0x00,0x3F,0xBF,0x80, +0x02,0x00,0x00,0xFD,0xFC,0x00,0x00,0x01,0xFD,0xFC, +0x00,0x00,0x00,0x3F,0xFE,0x00,0x00,0x00,0x3F,0xFF, +0x00,0x04,0x80,0x00,0xFF,0xF0,0x00,0x00,0x01,0xFF, +0xF0,0x00,0x00,0x00,0x3F,0xF8,0x00,0x00,0x00,0x3F, +0xFC,0x00,0x08,0x00,0x00,0xFF,0xC0,0x00,0x00,0x01, +0xFF,0xC0,0x00,0x00,0x00,0x3F,0xE0,0x00,0x00,0x00, +0x3F,0xF0,0x00,0x00,0x0D,0xDE,0x00,0x03,0x80,0x7F, +0xE0,0x00,0x00,0x03,0xFF,0x00,0x3F,0xF0,0x00,0x00, +0x07,0xFE,0x00,0x1F,0xF0,0x00,0x00,0x07,0xFC,0x00, +0x1F,0xF8,0x00,0x00,0x0F,0xFC,0x00,0x0F,0xFC,0x00, +0x00,0x1F,0xF8,0x00,0x07,0xFC,0x00,0x00,0x3F,0xF0, +0x00,0x07,0xFE,0x00,0x00,0x3F,0xF0,0x00,0x03,0xFF, +0x00,0x00,0x7F,0xE0,0x00,0x01,0xFF,0x00,0x00,0xFF, +0xC0,0x00,0x00,0xFF,0x80,0x00,0xFF,0x80,0x00,0x00, +0xFF,0xC0,0x01,0xFF,0x80,0x00,0x00,0x7F,0xE0,0x03, +0xFF,0x00,0x00,0x00,0x3F,0xE0,0x03,0xFE,0x00,0x00, +0x00,0x3F,0xF0,0x07,0xFE,0x00,0x00,0x00,0x1F,0xF8, +0x0F,0xFC,0x00,0x00,0x00,0x0F,0xF8,0x0F,0xF8,0x00, +0x00,0x00,0x0F,0xFC,0x1F,0xF8,0x00,0x00,0x00,0x07, +0xFE,0x3F,0xF0,0x00,0x00,0x00,0x03,0xFE,0x3F,0xE0, +0x00,0x00,0x00,0x03,0xFF,0x7F,0xE0,0x00,0x00,0x00, +0x01,0xFF,0xFF,0xC0,0x00,0x00,0x00,0x00,0xFF,0xFF, +0x80,0x00,0x00,0x00,0x00,0x7F,0xFF,0x80,0x00,0x00, +0x00,0x00,0x7F,0xFF,0x00,0x00,0x00,0x00,0x00,0x3F, +0xFE,0x00,0x00,0x0A,0x00,0x00,0x03,0xFF,0x80,0x00, +0x00,0x00,0x00,0x07,0xFF,0xC0,0x00,0x01,0x00,0x00, +0x01,0xFF,0xFC,0x00,0x00,0x00,0x00,0x03,0xFF,0xFE, +0x00,0x00,0x00,0x00,0x07,0xFF,0xFF,0x00,0x00,0x00, +0x00,0x07,0xFD,0xFF,0x00,0x00,0x00,0x00,0x0F,0xFD, +0xFF,0x80,0x00,0x00,0x00,0x1F,0xF8,0xFF,0xC0,0x00, +0x00,0x00,0x3F,0xF0,0x7F,0xC0,0x00,0x00,0x00,0x3F, +0xF0,0x3F,0xE0,0x00,0x00,0x00,0x7F,0xE0,0x3F,0xF0, +0x00,0x00,0x00,0xFF,0xC0,0x1F,0xF8,0x00,0x00,0x00, +0xFF,0x80,0x0F,0xF8,0x00,0x00,0x01,0xFF,0x80,0x0F, +0xFC,0x00,0x00,0x03,0xFF,0x00,0x07,0xFE,0x00,0x00, +0x03,0xFE,0x00,0x03,0xFE,0x00,0x00,0x07,0xFE,0x00, +0x03,0xFF,0x00,0x00,0x0F,0xFC,0x00,0x01,0xFF,0x80, +0x00,0x0F,0xF8,0x00,0x00,0xFF,0x80,0x00,0x1F,0xF8, +0x00,0x00,0xFF,0xC0,0x00,0x3F,0xF0,0x00,0x00,0x7F, +0xE0,0x00,0x3F,0xE0,0x00,0x00,0x3F,0xE0,0x00,0x7F, +0xE0,0x00,0x00,0x1F,0xF0,0x00,0xFF,0xC0,0x00,0x00, +0x1F,0xF8,0x01,0xFF,0x80,0x00,0x00,0x0F,0xFC,0x01, +0xFF,0x80,0x00,0x00,0x07,0xFC,0x03,0xFF,0x00,0x00, +0x00,0x07,0xFE,0x07,0xFE,0x00,0x00,0x00,0x03,0xFF, +0x07,0xFC,0x00,0x00,0x00,0x01,0xFF,0x0F,0xFC,0x00, +0x00,0x00,0x01,0xFF,0x9F,0xF8,0x00,0x00,0x00,0x00, +0xFF,0xC0,0x0D,0x9E,0x00,0x03,0x67,0xFE,0x00,0x00, +0x00,0x00,0x7F,0xE7,0xFC,0x00,0x00,0x00,0x00,0xFF, +0x87,0xFC,0x00,0x00,0x00,0x03,0xFE,0x0F,0xFC,0x00, +0x00,0x00,0x0F,0xFC,0x0F,0xF8,0x00,0x00,0x00,0x1F, +0xF0,0x0F,0xF8,0x00,0x00,0x00,0x7F,0xC0,0x1F,0xF8, +0x00,0x00,0x00,0xFF,0x80,0x1F,0xF0,0x00,0x00,0x03, +0xFE,0x00,0x1F,0xF0,0x00,0x00,0x0F,0xF8,0x00,0x3F, +0xF0,0x00,0x00,0x1F,0xF0,0x00,0x3F,0xE0,0x00,0x00, +0x7F,0xC0,0x00,0x3F,0xE0,0x00,0x01,0xFF,0x00,0x00, +0x7F,0xE0,0x00,0x03,0xFE,0x00,0x00,0x7F,0xC0,0x00, +0x0F,0xF8,0x00,0x00,0x7F,0xC0,0x00,0x1F,0xE0,0x00, +0x00,0xFF,0xC0,0x00,0x7F,0xC0,0x00,0x00,0xFF,0x80, +0x01,0xFF,0x00,0x00,0x00,0xFF,0x80,0x03,0xFC,0x00, +0x00,0x01,0xFF,0x80,0x0F,0xF8,0x00,0x00,0x01,0xFF, +0x00,0x3F,0xE0,0x00,0x00,0x01,0xFF,0x00,0x7F,0x80, +0x00,0x00,0x03,0xFF,0x01,0xFF,0x00,0x00,0x00,0x03, +0xFE,0x03,0xFC,0x00,0x00,0x00,0x03,0xFE,0x0F,0xF0, +0x00,0x00,0x00,0x07,0xFE,0x3F,0xE0,0x00,0x00,0x00, +0x07,0xFC,0x7F,0x80,0x00,0x00,0x00,0x07,0xFD,0xFE, +0x00,0x00,0x00,0x00,0x0F,0xFF,0xFC,0x00,0x00,0x00, +0x00,0x0F,0xFF,0xF0,0x00,0x01,0x00,0x00,0x01,0xFF, +0xF8,0x00,0x00,0x00,0x00,0x01,0xFF,0xE0,0x00,0x00, +0x80,0x00,0x00,0x3F,0xF0,0x00,0x00,0x34,0x00,0x00, +0x07,0xF8,0x00,0x00,0x0D,0x00,0x00,0x01,0xFE,0x00, +0x00,0x03,0x40,0x00,0x00,0x7F,0x80,0x00,0x00,0xB0, +0x00,0x00,0x1F,0xE0,0x00,0x00,0x00,0x0B,0xDE,0x08, +0x03,0x3D,0x0F,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x00, +0x00,0x00,0x0F,0xFC,0x00,0x00,0x00,0x00,0x1F,0xF8, +0x00,0x00,0x00,0x00,0x3F,0xF0,0x00,0x00,0x00,0x00, +0x7F,0xE1,0x00,0x00,0x00,0x00,0x1F,0xF8,0x00,0x00, +0x00,0x00,0x3F,0xF0,0x00,0x00,0x00,0x00,0x7F,0xE0, +0x00,0x00,0x00,0x00,0xFF,0xC0,0x00,0x00,0x00,0x01, +0xFF,0xC0,0x00,0x00,0x00,0x01,0xFF,0x80,0x00,0x00, +0x00,0x03,0xFF,0x00,0x00,0x00,0x00,0x07,0xFE,0x00, +0x20,0x00,0x00,0x01,0xFF,0x80,0x00,0x00,0x00,0x03, +0xFF,0x00,0x00,0x00,0x00,0x07,0xFE,0x00,0x00,0x00, +0x00,0x0F,0xFC,0x00,0x04,0x00,0x00,0x03,0xFF,0x00, +0x00,0x00,0x00,0x07,0xFE,0x00,0x00,0x00,0x00,0x0F, +0xFC,0x00,0x00,0x00,0x00,0x1F,0xF8,0x00,0x00,0x00, +0x00,0x3F,0xF8,0x00,0x00,0x00,0x00,0x3F,0xF0,0x00, +0x00,0x00,0x00,0x7F,0xE0,0x00,0x00,0x00,0x00,0xFF, +0xC0,0x00,0x00,0x80,0x00,0x3F,0xF0,0x00,0x00,0x00, +0x00,0x7F,0xE0,0x00,0x00,0x00,0x00,0xFF,0xC0,0x00, +0x00,0x00,0x01,0xFF,0x80,0x00,0x00,0x10,0x00,0x7F, +0xE0,0x00,0x00,0x00,0x00,0xFF,0xC0,0x00,0x00,0x00, +0x01,0xFF,0x80,0x00,0x00,0x00,0x03,0xFF,0x00,0x00, +0x00,0x02,0x00,0xFF,0xC0,0x00,0x00,0x00,0x01,0xFF, +0x80,0x00,0x00,0x00,0x03,0xFF,0x00,0x00,0x00,0x00, +0x40,0xFF,0xC0,0x00,0x00,0x00,0x01,0xFF,0x80,0x00, +0x00,0x00,0x03,0xFF,0x00,0x00,0x00,0x00,0x07,0xFE, +0x00,0x00,0x00,0x00,0x0D,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFE,0x03,0xE6,0x97,0x79,0x7D,0xFF,0xFF,0xBF,0xC0, +0x37,0xF8,0x06,0xFF,0x00,0xDF,0xE0,0x1B,0xFC,0x03, +0x7F,0x80,0x6F,0xF0,0x0D,0xFE,0x01,0xBF,0xC0,0x37, +0xFF,0xF8,0x05,0xDE,0x04,0x01,0x78,0xFC,0x00,0x01, +0x2F,0xC0,0x00,0x0F,0xE0,0x00,0x24,0xFC,0x00,0x04, +0x8F,0xC0,0x00,0x0F,0xE0,0x00,0x90,0xFC,0x00,0x00, +0xFE,0x00,0x10,0x0F,0xC0,0x00,0x0F,0xE0,0x02,0x40, +0xFC,0x00,0x00,0xFE,0x00,0x40,0x0F,0xC0,0x00,0x0F, +0xE0,0x09,0x00,0xFC,0x00,0x00,0xFE,0x01,0x20,0x0F, +0xC0,0x24,0x00,0xFC,0x00,0x00,0xFE,0x04,0x80,0x0F, +0xC0,0x90,0x00,0xFC,0x00,0x00,0xFE,0x12,0x00,0x0F, +0xC2,0x40,0x00,0xFC,0x00,0x00,0xFE,0x48,0x00,0x0F, +0xC9,0x00,0x00,0xFC,0x00,0x00,0xFE,0x00,0x00,0x7E, +0x03,0xE6,0x8F,0x79,0x7D,0xFF,0xFF,0xA0,0x1F,0xF4, +0x03,0xFE,0x80,0x7F,0xD0,0x0F,0xFA,0x01,0xFF,0x40, +0x3F,0xE8,0x07,0xFD,0x00,0xFF,0xA0,0x1F,0xF7,0xFF, +0xF8,0x08,0x90,0x08,0xE2,0x60,0x00,0x1F,0x80,0x01, +0x00,0x00,0xFF,0x00,0x04,0x80,0x07,0xFE,0x00,0x10, +0x00,0x3F,0xFC,0x00,0x40,0x01,0xF9,0xF8,0x00,0x00, +0x7F,0x3F,0x80,0x20,0x01,0xF8,0x7E,0x00,0x80,0x0F, +0xC0,0xFC,0x00,0x03,0xF8,0x1F,0xC0,0x00,0x7E,0x01, +0xF8,0x00,0x1F,0xC0,0x3F,0x80,0x03,0xF0,0x03,0xF0, +0x20,0x1F,0xC0,0x0F,0xE0,0x03,0xF0,0x00,0xFC,0x00, +0xFE,0x00,0x1F,0xC0,0x1F,0x80,0x01,0xF8,0x40,0xFE, +0x00,0x07,0xF1,0x07,0xF0,0x00,0x0F,0xE0,0xFC,0x00, +0x00,0xFC,0x87,0xF0,0x00,0x03,0xF9,0xFC,0x00,0x00, +0x3F,0x80,0x0C,0x03,0xFF,0x7A,0xED,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0x03,0x85,0x91,0x89,0xC7,0xFE,0x07, +0xFE,0x07,0xFC,0x07,0xF8,0x07,0xF9,0x00,0xFE,0x00, +0xFE,0x00,0xFC,0x00,0xF8,0x00,0xF8,0x0A,0x17,0x0F, +0xFA,0xE0,0x00,0x0F,0xFF,0x00,0x00,0x00,0x7F,0xFF, +0xF8,0x00,0x00,0xFF,0xFF,0xFF,0x00,0x01,0xFF,0xFF, +0xFF,0xC0,0x03,0xFF,0xFF,0xFF,0xF0,0x03,0xFF,0xFF, +0xFF,0xFC,0x01,0xFF,0xFF,0xFF,0xFF,0x01,0xFF,0xE0, +0x07,0xFF,0x80,0xFF,0x80,0x00,0xFF,0xC0,0xFF,0x80, +0x00,0x1F,0xF0,0x7F,0x80,0x00,0x07,0xF8,0x7F,0x80, +0x00,0x03,0xFC,0x3F,0xC0,0x00,0x00,0xFE,0x03,0xC0, +0x00,0x00,0x7F,0x24,0x00,0x00,0x00,0x07,0xF0,0x00, +0x00,0x00,0x0F,0xF8,0x00,0x00,0x00,0x7F,0xFC,0x00, +0x00,0x1F,0xFF,0xFE,0x00,0x03,0xFF,0xFF,0xFF,0x00, +0x1F,0xFF,0xFF,0xFF,0x80,0x3F,0xFF,0xFF,0xFF,0xC0, +0x3F,0xFF,0xFF,0xFF,0xE0,0x3F,0xFF,0xFF,0xE7,0xF0, +0x3F,0xFF,0xFF,0x03,0xF8,0x3F,0xFF,0xC0,0x01,0xFC, +0x3F,0xF8,0x00,0x00,0xFE,0x1F,0xF0,0x00,0x00,0x7F, +0x0F,0xE0,0x00,0x00,0x3F,0x8F,0xF0,0x00,0x00,0x3F, +0xC8,0xFE,0x00,0x00,0x03,0xFC,0x7F,0x00,0x00,0x03, +0xFE,0x3F,0x80,0x00,0x03,0xFF,0x1F,0xE0,0x00,0x03, +0xFF,0x8F,0xF0,0x00,0x03,0xFF,0xC3,0xFE,0x00,0x07, +0xFF,0xE1,0xFF,0xC0,0x1F,0xFF,0xF0,0xFF,0xFF,0xFF, +0xFF,0xF8,0x3F,0xFF,0xFF,0xFD,0xFE,0x0F,0xFF,0xFF, +0xFC,0xFF,0x03,0xFF,0xFF,0xFC,0x3F,0x80,0xFF,0xFF, +0xF8,0x1F,0xC0,0x1F,0xFF,0xF0,0x07,0xF0,0x01,0xFF, +0x80,0x00,0x00,0x09,0x5E,0x9B,0xFA,0xED,0xFE,0x00, +0x00,0x00,0x06,0xFF,0x00,0x00,0x00,0x01,0xFC,0x00, +0x00,0x00,0x07,0xF0,0x0F,0xF0,0x00,0x1F,0xC0,0xFF, +0xF8,0x00,0x7F,0x0F,0xFF,0xF8,0x01,0xFC,0x7F,0xFF, +0xF0,0x07,0xF3,0xFF,0xFF,0xE0,0x1F,0xDF,0xFF,0xFF, +0xC0,0x7F,0xFF,0xFF,0xFF,0x81,0xFF,0xFE,0x07,0xFF, +0x07,0xFF,0xC0,0x07,0xFE,0x1F,0xFE,0x00,0x0F,0xF8, +0x7F,0xF0,0x00,0x1F,0xF1,0xFF,0x80,0x00,0x3F,0xC7, +0xFC,0x00,0x00,0x7F,0x1F,0xF0,0x00,0x01,0xFE,0x9F, +0xF0,0x00,0x00,0x7F,0x6F,0xF0,0x00,0x00,0x1F,0xEB, +0xF8,0x00,0x00,0x0F,0xEF,0xE0,0x00,0x00,0x7F,0xCF, +0xF8,0x00,0x00,0x3F,0x9F,0xF0,0x00,0x01,0xFE,0x7F, +0xC0,0x00,0x07,0xF1,0xFF,0x80,0x00,0x3F,0xC7,0xFF, +0x00,0x01,0xFE,0x1F,0xFE,0x00,0x0F,0xF8,0x7F,0xFC, +0x00,0x7F,0xC1,0xFF,0xFC,0x0F,0xFF,0x07,0xF7,0xFF, +0xFF,0xF8,0x1F,0xDF,0xFF,0xFF,0xC0,0x7F,0x3F,0xFF, +0xFE,0x01,0xFC,0x7F,0xFF,0xF0,0x07,0xF0,0xFF,0xFF, +0x00,0x1F,0xC0,0xFF,0xF8,0x00,0x00,0x00,0xFF,0x00, +0x00,0x09,0x97,0x0F,0xFA,0xA0,0x00,0x0F,0xF8,0x00, +0x00,0x00,0xFF,0xFF,0x00,0x00,0x07,0xFF,0xFF,0x80, +0x00,0x3F,0xFF,0xFF,0x80,0x00,0xFF,0xFF,0xFF,0x80, +0x03,0xFF,0xFF,0xFF,0x80,0x0F,0xFF,0xFF,0xFF,0x80, +0x3F,0xFC,0x07,0xFF,0x80,0xFF,0xE0,0x03,0xFF,0x01, +0xFF,0x00,0x01,0xFF,0x07,0xFC,0x00,0x01,0xFE,0x0F, +0xF0,0x00,0x01,0xFC,0x1F,0xC0,0x00,0x03,0xFC,0x7F, +0x80,0x00,0x07,0xF8,0xFE,0x00,0x00,0x07,0x84,0x3F, +0x80,0x00,0x00,0x01,0xBF,0xC0,0x00,0x00,0x00,0x5F, +0xF0,0x00,0x00,0x00,0x07,0xF0,0x00,0x00,0x1E,0x0F, +0xE0,0x00,0x00,0x3F,0x9F,0xC0,0x00,0x00,0xFF,0x3F, +0xC0,0x00,0x01,0xFC,0x3F,0x80,0x00,0x03,0xF8,0x7F, +0x80,0x00,0x0F,0xF0,0xFF,0x80,0x00,0x3F,0xC0,0xFF, +0x80,0x00,0xFF,0x81,0xFF,0x80,0x03,0xFE,0x01,0xFF, +0xE0,0x3F,0xFC,0x01,0xFF,0xFF,0xFF,0xF0,0x01,0xFF, +0xFF,0xFF,0xC0,0x01,0xFF,0xFF,0xFF,0x00,0x01,0xFF, +0xFF,0xFC,0x00,0x00,0xFF,0xFF,0xE0,0x00,0x00,0x7F, +0xFF,0x80,0x00,0x00,0x1F,0xF0,0x00,0x00,0x09,0x5E, +0x8F,0xFA,0xED,0x00,0x00,0x00,0x03,0xFE,0x80,0x00, +0x00,0x01,0xFC,0x00,0x00,0x00,0x07,0xF0,0x00,0x1F, +0xE0,0x1F,0xC0,0x03,0xFF,0xE0,0x7F,0x00,0x3F,0xFF, +0xE1,0xFC,0x01,0xFF,0xFF,0xC7,0xF0,0x1F,0xFF,0xFF, +0x9F,0xC0,0x7F,0xFF,0xFF,0x7F,0x03,0xFF,0xFF,0xFF, +0xFC,0x1F,0xFC,0x0F,0xFF,0xF0,0xFF,0xC0,0x07,0xFF, +0xC3,0xFE,0x00,0x0F,0xFF,0x1F,0xF0,0x00,0x1F,0xFC, +0x7F,0x80,0x00,0x3F,0xF1,0xFC,0x00,0x00,0x7F,0xCF, +0xF0,0x00,0x01,0xFF,0x97,0xF0,0x00,0x00,0x7F,0xBF, +0x80,0x00,0x01,0xFF,0xBF,0xC0,0x00,0x00,0x7F,0xAF, +0xE0,0x00,0x00,0x3F,0xCB,0xF8,0x00,0x00,0x3F,0xCF, +0xF0,0x00,0x01,0xFF,0x1F,0xC0,0x00,0x07,0xFC,0x7F, +0x80,0x00,0x3F,0xF0,0xFF,0x00,0x01,0xFF,0xC3,0xFE, +0x00,0x0F,0xFF,0x07,0xFC,0x00,0x7F,0xFC,0x1F,0xFC, +0x07,0xFF,0xF0,0x3F,0xFF,0xFF,0xDF,0xC0,0x7F,0xFF, +0xFF,0x7F,0x00,0xFF,0xFF,0xF9,0xFC,0x01,0xFF,0xFF, +0xC7,0xF0,0x03,0xFF,0xFE,0x1F,0xC0,0x03,0xFF,0xE0, +0x7F,0x00,0x01,0xFE,0x00,0x00,0x0A,0x17,0x0F,0xFA, +0xE0,0x00,0x0F,0xFC,0x00,0x00,0x00,0x3F,0xFF,0xC0, +0x00,0x00,0x7F,0xFF,0xF8,0x00,0x00,0x7F,0xFF,0xFF, +0x00,0x00,0xFF,0xFF,0xFF,0xC0,0x00,0xFF,0xFF,0xFF, +0xF0,0x00,0xFF,0xFF,0xFF,0xFC,0x00,0xFF,0xF0,0x0F, +0xFF,0x00,0x7F,0xC0,0x00,0xFF,0x80,0x7F,0xC0,0x00, +0x1F,0xE0,0x3F,0xC0,0x00,0x07,0xF0,0x3F,0xC0,0x00, +0x01,0xFC,0x1F,0xC0,0x00,0x00,0xFE,0x43,0xF8,0x00, +0x00,0x07,0xF4,0x3F,0x00,0x00,0x00,0x3F,0x3F,0x80, +0x00,0x00,0x1F,0xF7,0xFF,0xFF,0xFF,0xFF,0xFE,0xBF, +0x80,0x00,0x00,0x00,0x25,0xFC,0x00,0x00,0x00,0x00, +0xFF,0x00,0x00,0x00,0xE0,0x3F,0xC0,0x00,0x00,0xFF, +0x1F,0xE0,0x00,0x00,0xFF,0x0F,0xF8,0x00,0x00,0xFF, +0x83,0xFF,0x00,0x00,0xFF,0x80,0xFF,0xC0,0x00,0xFF, +0xC0,0x7F,0xFC,0x03,0xFF,0xC0,0x1F,0xFF,0xFF,0xFF, +0xC0,0x07,0xFF,0xFF,0xFF,0xE0,0x01,0xFF,0xFF,0xFF, +0xE0,0x00,0x7F,0xFF,0xFF,0xC0,0x00,0x0F,0xFF,0xFF, +0xC0,0x00,0x01,0xFF,0xFF,0x80,0x00,0x00,0x0F,0xFC, +0x00,0x00,0x06,0x1E,0x88,0x01,0x80,0x00,0x3F,0xF0, +0x00,0x7F,0xFC,0x00,0xFF,0xFF,0x00,0x1F,0xFF,0xF0, +0x03,0xFF,0xFE,0x03,0xFF,0x00,0x80,0x3F,0xC0,0x0D, +0x03,0xF8,0x00,0xDF,0xFF,0xFF,0xCD,0x03,0xF8,0x00, +0xD0,0x3F,0x80,0x0D,0x03,0xF8,0x00,0xD0,0x3F,0x80, +0x0D,0x03,0xF8,0x00,0x80,0x3F,0x80,0x00,0x09,0x5F, +0x8F,0x72,0xE0,0x00,0x1F,0xE0,0x00,0x00,0x03,0xFF, +0xF0,0x7F,0x00,0x3F,0xFF,0xE1,0xFC,0x01,0xFF,0xFF, +0xE7,0xF0,0x1F,0xFF,0xFF,0xDF,0xE0,0x1F,0xFF,0xFF, +0xFF,0xE0,0xFF,0xE0,0x3F,0xFF,0x87,0xFE,0x00,0x3F, +0xFE,0x1F,0xF0,0x00,0x7F,0xF8,0xFF,0x80,0x00,0xFF, +0xE3,0xFC,0x00,0x01,0xFF,0x8F,0xE0,0x00,0x03,0xFE, +0x7F,0x80,0x00,0x0F,0xFC,0xBF,0x80,0x00,0x03,0xFF, +0x7F,0x80,0x00,0x00,0xFF,0x5F,0xC0,0x00,0x00,0x7F, +0x97,0xF0,0x00,0x00,0x7F,0x9F,0xE0,0x00,0x03,0xFE, +0x3F,0x80,0x00,0x0F,0xF8,0xFF,0x00,0x00,0x7F,0xE3, +0xFC,0x00,0x03,0xFF,0x87,0xF8,0x00,0x1F,0xFE,0x1F, +0xF8,0x00,0xFF,0xF8,0x3F,0xF8,0x0F,0xFF,0xE0,0x7F, +0xFF,0xFF,0xFF,0xC0,0x1F,0xFF,0xFF,0xFF,0xC0,0x1F, +0xFF,0xFE,0x7F,0x00,0x3F,0xFF,0xF1,0xFC,0x00,0x3F, +0xFF,0x07,0xF0,0x00,0x1F,0xE0,0x1F,0xE4,0x00,0x00, +0x00,0x0F,0xE0,0x00,0x00,0x00,0x3F,0x1E,0x00,0x00, +0x01,0xFC,0x7F,0x00,0x00,0x07,0xF1,0xFC,0x00,0x00, +0x3F,0xC7,0xF8,0x00,0x00,0xFE,0x1F,0xF0,0x00,0x07, +0xF8,0x3F,0xE0,0x00,0x7F,0xE0,0xFF,0xE0,0x0F,0xFF, +0x01,0xFF,0xFF,0xFF,0xF8,0x07,0xFF,0xFF,0xFF,0xC0, +0x0F,0xFF,0xFF,0xFE,0x00,0x1F,0xFF,0xFF,0xF0,0x00, +0x1F,0xFF,0xFF,0x80,0x00,0x1F,0xFF,0xF8,0x00,0x00, +0x0F,0xFE,0x00,0x00,0x08,0x9E,0x18,0x02,0xED,0xFE, +0x00,0x00,0x00,0x37,0xF8,0x00,0x00,0x00,0x7F,0x00, +0x00,0x00,0x0F,0xE0,0x0F,0xF0,0x01,0xFC,0x0F,0xFF, +0xC0,0x3F,0x87,0xFF,0xFC,0x07,0xF1,0xFF,0xFF,0xE0, +0xFE,0x7F,0xFF,0xFE,0x1F,0xDF,0xFF,0xFF,0xE3,0xFF, +0xFF,0xFF,0xFC,0x7F,0xFF,0x03,0xFF,0xCF,0xFF,0x80, +0x1F,0xF9,0xFF,0xC0,0x00,0xFF,0x3F,0xF0,0x00,0x1F, +0xE8,0xFF,0x80,0x00,0x3F,0xE7,0xFC,0x00,0x00,0x7F, +0xDF,0xE0,0x00,0x01,0xFF,0x7F,0x80,0x00,0x07,0xFD, +0xFE,0x00,0x00,0x1F,0xF7,0xF8,0x00,0x00,0x7F,0x7F, +0x00,0x00,0x0F,0xE0,0x01,0xDE,0x18,0x01,0x2D,0xFF, +0xA0,0x20,0x06,0xFF,0xDF,0xFB,0xFF,0x7F,0xEF,0xFD, +0xFF,0x1F,0xC0,0x04,0x67,0x73,0x71,0x3D,0x00,0x3F, +0xE8,0x00,0x02,0x00,0x00,0x1A,0x00,0x7F,0xD0,0x03, +0xFE,0x80,0x1F,0xF4,0x00,0xFF,0xA0,0x07,0xFD,0x00, +0x3F,0xE8,0x01,0xFE,0x40,0x0F,0xE0,0x07,0xF8,0x01, +0xFC,0x00,0xFF,0x43,0xFF,0xF8,0xFF,0xFC,0x87,0xFF, +0xC3,0xFF,0xC0,0x3F,0xC0,0x00,0x09,0x1E,0x18,0x02, +0xBD,0xFE,0x00,0x00,0x00,0x0D,0xFE,0x00,0x00,0x00, +0x08,0xFE,0x00,0x00,0x00,0x07,0xF0,0x00,0x03,0xFE, +0x3F,0x80,0x00,0x3F,0xE1,0xFC,0x00,0x03,0xFE,0x0F, +0xE0,0x00,0x7F,0xE0,0x7F,0x00,0x07,0xFE,0x03,0xF8, +0x00,0x7F,0xE0,0x1F,0xC0,0x07,0xFE,0x00,0xFE,0x00, +0x7F,0xE0,0x07,0xF0,0x07,0xFE,0x00,0x3F,0x80,0x7F, +0xE0,0x01,0xFC,0x07,0xFE,0x00,0x0F,0xE0,0x7F,0xE0, +0x00,0x7F,0x07,0xFE,0x00,0x03,0xF8,0x7F,0xE0,0x00, +0x1F,0xC7,0xFE,0x00,0x00,0xFE,0x7F,0xE0,0x00,0x07, +0xF7,0xFE,0x00,0x00,0x3F,0xFF,0xF0,0x00,0x02,0x3F, +0xFF,0xF8,0x00,0x01,0xFF,0xFF,0xE0,0x00,0x0F,0xFF, +0xFF,0x80,0x00,0x7F,0xF3,0xFC,0x00,0x03,0xFF,0x0F, +0xF0,0x00,0x1F,0xF0,0x7F,0xC0,0x00,0xFF,0x01,0xFE, +0x00,0x07,0xF0,0x07,0xF8,0x00,0x3F,0x80,0x3F,0xE0, +0x01,0xFC,0x00,0xFF,0x00,0x0F,0xE0,0x03,0xFC,0x00, +0x7F,0x00,0x1F,0xF0,0x03,0xF8,0x00,0x7F,0x80,0x1F, +0xC0,0x01,0xFE,0x00,0xFE,0x00,0x07,0xF8,0x07,0xF0, +0x00,0x3F,0xE0,0x3F,0x80,0x00,0xFF,0x01,0xFC,0x00, +0x03,0xFC,0x0F,0xE0,0x00,0x1F,0xF0,0x7F,0x00,0x00, +0x7F,0x83,0xF8,0x00,0x01,0xFE,0x1F,0xC0,0x00,0x0F, +0xF8,0xFE,0x00,0x00,0x3F,0xC7,0xF0,0x00,0x00,0xFF, +0x3F,0x80,0x00,0x07,0xFC,0x01,0xDE,0x18,0x01,0x2D, +0xFF,0xBF,0xF7,0xFE,0xFF,0xDF,0xFB,0xFF,0x7F,0xEF, +0xFA,0xFE,0x0E,0xD6,0x98,0x04,0x70,0x00,0x07,0xF8, +0x00,0x01,0xFE,0x00,0x7F,0x03,0xFF,0xF0,0x00,0xFF, +0xFC,0x07,0xF0,0x7F,0xFF,0x80,0x3F,0xFF,0xE0,0x7F, +0x1F,0xFF,0xFC,0x07,0xFF,0xFF,0x07,0xF3,0xFF,0xFF, +0xE0,0xFF,0xFF,0xF8,0x7F,0x7F,0xFF,0xFF,0x1F,0xFF, +0xFF,0xC7,0xF7,0xFF,0xFF,0xF3,0xFF,0xFF,0xFC,0x7F, +0xFF,0x03,0xFF,0xFF,0x80,0xFF,0xE7,0xFF,0x80,0x0F, +0xFF,0xE0,0x03,0xFE,0x7F,0xF0,0x00,0x7F,0xFC,0x00, +0x1F,0xE7,0xFE,0x00,0x03,0xFF,0x80,0x00,0xFF,0x7F, +0xC0,0x00,0x3F,0xF0,0x00,0x0F,0xF7,0xFC,0x00,0x01, +0xFE,0x00,0x00,0x7F,0x8F,0xF0,0x00,0x03,0xFC,0x00, +0x00,0xFE,0xFF,0x00,0x00,0x3F,0x80,0x00,0x0F,0xFB, +0xFC,0x00,0x00,0x7F,0x00,0x00,0x1F,0xF7,0xF8,0x00, +0x00,0xFE,0x00,0x00,0x3F,0xEF,0xF0,0x00,0x01,0xFC, +0x00,0x00,0x7F,0xDF,0xE0,0x00,0x03,0xF8,0x00,0x00, +0xFE,0xFE,0x00,0x00,0x3F,0x80,0x00,0x0F,0xE0,0x08, +0x96,0x98,0x02,0xE0,0x00,0x07,0xF8,0x00,0xFE,0x07, +0xFF,0xE0,0x1F,0xC3,0xFF,0xFF,0x03,0xF8,0xFF,0xFF, +0xF0,0x7F,0x3F,0xFF,0xFF,0x0F,0xEF,0xFF,0xFF,0xF1, +0xFF,0xFF,0xFF,0xFE,0x3F,0xFF,0x81,0xFF,0xE7,0xFF, +0x80,0x0F,0xFC,0xFF,0xE0,0x00,0x7F,0x9F,0xF8,0x00, +0x0F,0xFC,0x7F,0xC0,0x00,0x1F,0xF3,0xFE,0x00,0x00, +0x3F,0xEF,0xF0,0x00,0x00,0xFF,0xBF,0xC0,0x00,0x03, +0xFE,0xFF,0x00,0x00,0x0F,0xFB,0xFC,0x00,0x00,0x3F, +0xBF,0x80,0x00,0x07,0xF0,0x0A,0x17,0x0F,0xFA,0xE0, +0x00,0x0F,0xFC,0x00,0x00,0x00,0x3F,0xFF,0xC0,0x00, +0x00,0x7F,0xFF,0xF8,0x00,0x00,0xFF,0xFF,0xFF,0x00, +0x00,0xFF,0xFF,0xFF,0xC0,0x00,0xFF,0xFF,0xFF,0xF0, +0x00,0xFF,0xFF,0xFF,0xFC,0x00,0xFF,0xF0,0x0F,0xFF, +0x00,0x7F,0xE0,0x01,0xFF,0x80,0x7F,0xC0,0x00,0x3F, +0xE0,0x7F,0xC0,0x00,0x0F,0xF9,0x07,0xF8,0x00,0x00, +0x7F,0x87,0xF8,0x00,0x00,0x1F,0xE9,0x7F,0x00,0x00, +0x00,0xFE,0x7F,0x80,0x00,0x00,0x7F,0xEF,0xF0,0x00, +0x00,0x03,0xFC,0xFF,0x00,0x00,0x00,0x3F,0xBF,0xC0, +0x00,0x00,0x3F,0xE1,0xFC,0x00,0x00,0x03,0xF8,0xFE, +0x00,0x00,0x03,0xFC,0x7F,0x80,0x00,0x01,0xFE,0x83, +0xFC,0x00,0x00,0x3F,0xC1,0xFF,0x00,0x00,0x3F,0xE0, +0x7F,0xC0,0x00,0x3F,0xE0,0x1F,0xF8,0x00,0x7F,0xF0, +0x0F,0xFF,0x00,0xFF,0xF0,0x03,0xFF,0xFF,0xFF,0xF0, +0x00,0xFF,0xFF,0xFF,0xF0,0x00,0x3F,0xFF,0xFF,0xF0, +0x00,0x0F,0xFF,0xFF,0xF0,0x00,0x01,0xFF,0xFF,0xE0, +0x00,0x00,0x3F,0xFF,0xC0,0x00,0x00,0x03,0xFF,0x00, +0x00,0x09,0x5F,0x1B,0x7A,0xE0,0x00,0x0F,0xF0,0x00, +0x1F,0xC0,0xFF,0xF8,0x00,0x7F,0x0F,0xFF,0xF8,0x01, +0xFC,0x7F,0xFF,0xF0,0x07,0xF3,0xFF,0xFF,0xF0,0x1F, +0xCF,0xFF,0xFF,0xE0,0x7F,0x7F,0xFF,0xFF,0x81,0xFF, +0xFE,0x07,0xFF,0x07,0xFF,0xE0,0x07,0xFE,0x1F,0xFE, +0x00,0x0F,0xF8,0x7F,0xF0,0x00,0x1F,0xF1,0xFF,0x80, +0x00,0x3F,0xC7,0xFE,0x00,0x00,0x7F,0x1F,0xF0,0x00, +0x01,0xFE,0x7F,0xC0,0x00,0x03,0xFA,0x3F,0xC0,0x00, +0x01,0xFC,0xFF,0x00,0x00,0x03,0xFE,0xFF,0x00,0x00, +0x01,0xFE,0x7F,0x80,0x00,0x00,0xFE,0xFE,0x00,0x00, +0x07,0xFC,0xFF,0x80,0x00,0x03,0xF9,0xFF,0x00,0x00, +0x1F,0xE7,0xFC,0x00,0x00,0x7F,0x1F,0xF8,0x00,0x03, +0xFC,0x7F,0xF0,0x00,0x1F,0xE1,0xFF,0xE0,0x00,0xFF, +0x87,0xFF,0xC0,0x07,0xFC,0x1F,0xFF,0xC0,0x7F,0xF0, +0x7F,0xFF,0xFF,0xFF,0x81,0xFD,0xFF,0xFF,0xFC,0x07, +0xF7,0xFF,0xFF,0xE0,0x1F,0xCF,0xFF,0xFF,0x00,0x7F, +0x0F,0xFF,0xF0,0x01,0xFC,0x1F,0xFF,0x00,0x07,0xF0, +0x0F,0xE0,0x00,0x37,0xF8,0x00,0x00,0x00,0x1B,0xFC, +0x00,0x00,0x00,0x08,0xFE,0x00,0x00,0x00,0x00,0x09, +0x5F,0x0F,0x7A,0xE0,0x00,0x1F,0xC0,0x00,0x00,0x03, +0xFF,0xE0,0x7F,0x00,0x3F,0xFF,0xC1,0xFC,0x03,0xFF, +0xFF,0xC7,0xF0,0x1F,0xFF,0xFF,0x9F,0xC0,0xFF,0xFF, +0xFE,0x7F,0x03,0xFF,0xFF,0xFD,0xFC,0x1F,0xFC,0x0F, +0xFF,0xF0,0xFF,0xC0,0x0F,0xFF,0xC3,0xFE,0x00,0x0F, +0xFF,0x1F,0xF0,0x00,0x1F,0xFC,0x7F,0x80,0x00,0x3F, +0xF3,0xFC,0x00,0x00,0xFF,0xCF,0xF0,0x00,0x01,0xFF, +0x3F,0x80,0x00,0x07,0xFE,0x1F,0xC0,0x00,0x01,0xFE, +0xFE,0x00,0x00,0x07,0xFE,0xFF,0x00,0x00,0x01,0xFE, +0xBF,0x80,0x00,0x00,0xFF,0x2F,0xE0,0x00,0x00,0xFF, +0x3F,0xC0,0x00,0x07,0xFC,0x7F,0x00,0x00,0x1F,0xF1, +0xFE,0x00,0x00,0xFF,0xC3,0xFC,0x00,0x07,0xFF,0x0F, +0xF8,0x00,0x3F,0xFC,0x1F,0xF0,0x01,0xFF,0xF0,0x7F, +0xF8,0x1F,0xFF,0xC0,0xFF,0xFF,0xFF,0xFF,0x01,0xFF, +0xFF,0xFD,0xFC,0x03,0xFF,0xFF,0xF7,0xF0,0x07,0xFF, +0xFF,0x9F,0xC0,0x07,0xFF,0xF8,0x7F,0x00,0x07,0xFF, +0xC1,0xFC,0x00,0x03,0xF8,0x07,0xFD,0x00,0x00,0x00, +0x03,0xFE,0x80,0x00,0x00,0x01,0xFE,0x00,0x00,0x00, +0x00,0xFE,0x05,0xD6,0x98,0x01,0xC0,0x00,0x3F,0x07, +0xE1,0xFF,0xE7,0xE3,0xFF,0xF7,0xE7,0xFF,0xF7,0xE7, +0xFF,0xE7,0xEF,0xFF,0xE7,0xFF,0xFF,0xC7,0xFF,0xC1, +0xC7,0xFF,0x00,0x47,0xFE,0x00,0x08,0xFF,0x80,0x01, +0x5F,0xE0,0x00,0x37,0xF8,0x00,0x06,0xFF,0x00,0x00, +0xDF,0xE0,0x00,0x1B,0xFC,0x00,0x01,0xFC,0x00,0x00, +0x09,0x17,0x0F,0xFA,0xA0,0x00,0x7F,0xE0,0x00,0x00, +0x1F,0xFF,0xF0,0x00,0x03,0xFF,0xFF,0xE0,0x00,0x7F, +0xFF,0xFF,0xC0,0x07,0xFF,0xFF,0xFF,0x04,0x0F,0xFF, +0xFF,0xFF,0x80,0xFF,0xE0,0x0F,0xFE,0x07,0xF8,0x00, +0x1F,0xF0,0x7F,0x80,0x00,0x7F,0x83,0xF8,0x00,0x01, +0xFE,0x1F,0xC0,0x00,0x07,0xF0,0xFE,0x00,0x00,0x3C, +0x07,0xF0,0x00,0x00,0x00,0x3F,0xC0,0x00,0x00,0x01, +0xFF,0x00,0x00,0x00,0x07,0xFF,0x00,0x00,0x00,0x3F, +0xFF,0x00,0x00,0x01,0xFF,0xFF,0x80,0x00,0x07,0xFF, +0xFF,0xC0,0x00,0x1F,0xFF,0xFF,0xC0,0x00,0x7F,0xFF, +0xFF,0x80,0x01,0xFF,0xFF,0xFF,0x00,0x03,0xFF,0xFF, +0xFC,0x00,0x03,0xFF,0xFF,0xF0,0x00,0x03,0xFF,0xFF, +0xC0,0x00,0x03,0xFF,0xFF,0x00,0x00,0x01,0xFF,0xF8, +0x00,0x00,0x00,0xFF,0xE0,0x00,0x00,0x01,0xFF,0x00, +0x00,0x00,0x07,0xF8,0x78,0x00,0x00,0x1F,0xDF,0xC0, +0x00,0x00,0xFE,0xFF,0x00,0x00,0x07,0xF3,0xF8,0x00, +0x00,0x3F,0x9F,0xE0,0x00,0x03,0xF8,0xFF,0x80,0x00, +0x3F,0xC3,0xFE,0x00,0x03,0xFE,0x1F,0xFE,0x00,0xFF, +0xE0,0x7F,0xFF,0xFF,0xFF,0x01,0xFF,0xFF,0xFF,0xF0, +0x07,0xFF,0xFF,0xFF,0x00,0x1F,0xFF,0xFF,0xF0,0x00, +0x7F,0xFF,0xFE,0x00,0x00,0xFF,0xFF,0xC0,0x00,0x00, +0x7F,0xF0,0x00,0x05,0x5E,0x0B,0xF9,0x70,0x00,0x80, +0x00,0x06,0x00,0x00,0x78,0x00,0x07,0xE0,0x0D,0x07, +0xF0,0x05,0x03,0xF8,0x03,0x7F,0xFF,0xFD,0xA0,0xFE, +0x00,0xD0,0x7F,0x00,0x68,0x3F,0x80,0x34,0x1F,0xC0, +0x00,0x7F,0x00,0x01,0xFE,0x00,0x07,0xFC,0x00,0x1F, +0xFF,0xD0,0x07,0xFF,0xE0,0x1F,0xFF,0xC0,0x3F,0xFF, +0x00,0x3F,0xFC,0x00,0x3F,0xE0,0x08,0x96,0x9B,0xFA, +0xED,0xFE,0x00,0x00,0x1F,0xF7,0xF8,0x00,0x00,0x7F, +0xDF,0xE0,0x00,0x01,0xFF,0x7F,0x80,0x00,0x07,0xF7, +0xF0,0x00,0x00,0xFF,0x3F,0xC0,0x00,0x07,0xFC,0x7F, +0x80,0x00,0x3F,0xEF,0xF8,0x00,0x0F,0xFC,0xFF,0x00, +0x03,0xFF,0x9F,0xF8,0x01,0xFF,0xF3,0xFF,0x80,0xFF, +0xFE,0x3F,0xFF,0xFF,0xDF,0xC7,0xFF,0xFF,0xF3,0xF8, +0x7F,0xFF,0xFC,0x7F,0x07,0xFF,0xFF,0x0F,0xE0,0x7F, +0xFF,0xC1,0xFC,0x03,0xFF,0xE0,0x3F,0x80,0x0F,0xF0, +0x00,0x00,0x09,0xD6,0x04,0x02,0x97,0xF8,0x00,0x00, +0x0F,0xF8,0x7F,0x00,0x00,0x01,0xFC,0x7F,0x80,0x00, +0x03,0xFD,0x07,0xF0,0x00,0x00,0x7F,0x07,0xF8,0x00, +0x00,0xFF,0x20,0x7F,0x00,0x00,0x1F,0xC0,0x7F,0x80, +0x00,0x3F,0xC4,0x07,0xF0,0x00,0x07,0xF0,0x07,0xF8, +0x00,0x0F,0xF0,0x03,0xF8,0x00,0x0F,0xE0,0x03,0xFC, +0x00,0x0F,0xE0,0x03,0xFC,0x00,0x1F,0xE0,0x01,0xFC, +0x00,0x1F,0xC0,0x80,0x3F,0xC0,0x07,0xF8,0x00,0x1F, +0xC0,0x07,0xF0,0x00,0x1F,0xE0,0x0F,0xF0,0x00,0x0F, +0xE0,0x0F,0xF0,0x00,0x0F,0xE0,0x0F,0xE0,0x00,0x0F, +0xF0,0x1F,0xE0,0x00,0x07,0xF0,0x1F,0xE0,0x00,0x07, +0xF0,0x1F,0xC0,0x00,0x07,0xF8,0x3F,0xC0,0x10,0x00, +0x7F,0x07,0xF0,0x00,0x00,0x7F,0x8F,0xF0,0x02,0x00, +0x07,0xF1,0xFC,0x00,0x00,0x07,0xFB,0xFC,0x00,0x40, +0x00,0x7F,0x7F,0x00,0x00,0x00,0x7F,0xFF,0x00,0x09, +0x00,0x07,0xFF,0xC0,0x01,0x00,0x00,0x7F,0xF0,0x00, +0x00,0x00,0x3F,0xF0,0x00,0x20,0x00,0x07,0xFC,0x00, +0x00,0x0E,0xD6,0x00,0x03,0xB8,0xFE,0x00,0x00,0x7F, +0xC0,0x00,0x0F,0xEF,0xF0,0x00,0x07,0xFC,0x00,0x01, +0xFE,0x7F,0x00,0x00,0x7F,0xC0,0x00,0x1F,0xC7,0xF0, +0x00,0x0F,0xFE,0x00,0x01,0xFC,0x7F,0x80,0x00,0xFF, +0xE0,0x00,0x3F,0xD0,0x7F,0x00,0x01,0xFF,0xC0,0x00, +0x7F,0x07,0xF0,0x00,0x1F,0xFE,0x00,0x0F,0xF0,0x3F, +0x80,0x03,0xFF,0xE0,0x00,0xFE,0x20,0x7F,0x00,0x07, +0xEF,0xC0,0x01,0xFC,0x03,0xF8,0x00,0x7E,0xFE,0x00, +0x3F,0x84,0x07,0xF0,0x01,0xFD,0xFC,0x00,0x7F,0x08, +0x07,0xF0,0x03,0xF1,0xF8,0x01,0xFC,0x00,0x7F,0x00, +0x7F,0x1F,0xC0,0x1F,0xC0,0x03,0xF8,0x07,0xF1,0xFC, +0x03,0xF8,0x10,0x07,0xF0,0x0F,0xC1,0xF8,0x07,0xF0, +0x20,0x07,0xF0,0x3F,0x83,0xF8,0x1F,0xC0,0x00,0x7F, +0x03,0xF0,0x3F,0x81,0xFC,0x00,0x07,0xF8,0x3F,0x01, +0xF8,0x3F,0x80,0x40,0x07,0xF0,0xFE,0x03,0xF8,0x7F, +0x00,0x00,0x7F,0x0F,0xE0,0x3F,0x8F,0xE0,0x00,0x03, +0xF8,0xFC,0x01,0xF8,0xFE,0x00,0x00,0x3F,0x9F,0xC0, +0x1F,0xCF,0xE0,0x00,0x03,0xF9,0xFC,0x01,0xFC,0xFC, +0x00,0x00,0x1F,0x9F,0xC0,0x1F,0xDF,0xC0,0x00,0x01, +0xFD,0xF8,0x00,0xFD,0xFC,0x00,0x00,0x1F,0xDF,0x80, +0x0F,0xDF,0x80,0x08,0x00,0x1F,0xFF,0x00,0x1F,0xFF, +0x00,0x00,0x01,0xFF,0xF0,0x00,0xFF,0xF0,0x01,0x20, +0x01,0xFF,0xC0,0x01,0xFF,0xC0,0x00,0x00,0x0F,0xFC, +0x00,0x1F,0xF8,0x00,0x20,0x00,0x1F,0xF0,0x00,0x1F, +0xF0,0x00,0x00,0x00,0xFF,0x00,0x01,0xFE,0x00,0x00, +0x0A,0x16,0x04,0x02,0xA3,0xFE,0x00,0x00,0x07,0xF8, +0xFF,0x00,0x00,0x07,0xF8,0x3F,0xC0,0x00,0x07,0xFC, +0x1F,0xF0,0x00,0x07,0xFC,0x07,0xFC,0x00,0x03,0xFC, +0x01,0xFE,0x00,0x03,0xFC,0x00,0x7F,0x80,0x03,0xFE, +0x00,0x3F,0xE0,0x01,0xFE,0x00,0x0F,0xF0,0x01,0xFE, +0x00,0x03,0xFC,0x01,0xFF,0x00,0x01,0xFF,0x01,0xFF, +0x00,0x00,0x7F,0x80,0xFF,0x00,0x00,0x1F,0xE0,0xFF, +0x00,0x00,0x0F,0xF8,0xFF,0x80,0x00,0x03,0xFC,0xFF, +0x80,0x00,0x00,0xFF,0x7F,0x80,0x00,0x00,0x7F,0xFF, +0x80,0x00,0x00,0x1F,0xFF,0xC0,0x00,0x00,0x07,0xFF, +0xC0,0x01,0x00,0x00,0x3F,0xF8,0x00,0x10,0x00,0x01, +0xFF,0x00,0x00,0x00,0x01,0xFF,0xC0,0x00,0x00,0x01, +0xFF,0xE0,0x00,0x00,0x01,0xFF,0xF8,0x00,0x00,0x00, +0xFF,0xFE,0x00,0x00,0x00,0xFF,0xFF,0x80,0x00,0x00, +0xFF,0xBF,0xC0,0x00,0x00,0x7F,0x8F,0xF0,0x00,0x00, +0x7F,0x87,0xFC,0x00,0x00,0x7F,0xC1,0xFE,0x00,0x00, +0x7F,0xC0,0x7F,0x80,0x00,0x3F,0xC0,0x3F,0xE0,0x00, +0x3F,0xC0,0x0F,0xF0,0x00,0x3F,0xE0,0x03,0xFC,0x00, +0x3F,0xE0,0x01,0xFF,0x00,0x1F,0xE0,0x00,0x7F,0x80, +0x1F,0xE0,0x00,0x1F,0xE0,0x1F,0xF0,0x00,0x0F,0xF8, +0x0F,0xF0,0x00,0x03,0xFE,0x0F,0xF0,0x00,0x00,0xFF, +0x0F,0xF8,0x00,0x00,0x3F,0xCF,0xF8,0x00,0x00,0x1F, +0xF0,0x09,0x5F,0x07,0x72,0x77,0xF0,0x00,0x00,0x1F, +0xCF,0xE0,0x00,0x00,0xFF,0x87,0xF0,0x00,0x00,0x7F, +0x0F,0xE0,0x00,0x03,0xFD,0x07,0xF0,0x00,0x01,0xFC, +0x0F,0xE0,0x00,0x0F,0xF2,0x07,0xF0,0x00,0x07,0xF0, +0x0F,0xE0,0x00,0x3F,0xC4,0x07,0xF0,0x00,0x1F,0xC0, +0x0F,0xE0,0x00,0xFF,0x08,0x07,0xF0,0x00,0x7F,0x00, +0x0F,0xE0,0x03,0xFC,0x10,0x07,0xF0,0x01,0xFC,0x00, +0x0F,0xE0,0x0F,0xF0,0x20,0x07,0xF0,0x07,0xF0,0x00, +0x0F,0xE0,0x3F,0xC0,0x40,0x07,0xF0,0x1F,0xC0,0x00, +0x0F,0xE0,0xFF,0x00,0x80,0x07,0xF0,0x7F,0x00,0x00, +0x0F,0xC3,0xFC,0x01,0x00,0x07,0xF1,0xFC,0x00,0x00, +0x0F,0xCF,0xF0,0x02,0x00,0x07,0xF7,0xF0,0x00,0x00, +0x0F,0xFF,0xC0,0x04,0x00,0x07,0xFF,0xC0,0x00,0x00, +0x0F,0xFF,0x00,0x08,0x00,0x07,0xFF,0x00,0x00,0x00, +0x0F,0xFC,0x00,0x10,0x00,0x07,0xFC,0x00,0x00,0x00, +0x0F,0xF0,0x00,0x20,0x00,0x07,0xF0,0x00,0x00,0x00, +0x3F,0xC0,0x00,0x40,0x00,0x1F,0xC0,0x00,0x24,0x00, +0x1F,0xC0,0x00,0x00,0x00,0xFE,0x00,0x00,0x00,0x07, +0xF8,0x00,0x00,0x10,0x3F,0xC0,0x00,0x00,0x7F,0xFF, +0x00,0x00,0x10,0x3F,0xFF,0x00,0x00,0x00,0x7F,0xF8, +0x00,0x00,0x01,0xFF,0xC0,0x00,0x00,0x07,0xFE,0x00, +0x00,0x00,0x0F,0xE0,0x00,0x00,0x00,0x09,0x56,0x04, +0x02,0x8D,0x3F,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x00, +0xFF,0x80,0x00,0x00,0x07,0xFC,0x00,0x00,0x00,0x3F, +0xE0,0x00,0x00,0x01,0xFF,0x00,0x00,0x00,0x0F,0xF8, +0x10,0x00,0x00,0x0F,0xF8,0x00,0x00,0x00,0x7F,0xC0, +0x00,0x00,0x03,0xFE,0x00,0x00,0x00,0x1F,0xF0,0x00, +0x00,0x00,0xFF,0x80,0x00,0x00,0x07,0xFC,0x00,0x00, +0x00,0x3F,0xE0,0x00,0x00,0x00,0xFF,0x00,0x00,0x00, +0x07,0xFC,0x00,0x00,0x00,0x3F,0xE0,0x00,0x00,0x01, +0xFF,0x00,0x00,0x00,0x0F,0xF8,0x00,0x00,0x00,0x7F, +0xC0,0x00,0x00,0x03,0xFE,0x00,0x00,0x00,0x0F,0xF0, +0x00,0x00,0x00,0x7F,0xC0,0x00,0x00,0x03,0xFE,0x00, +0x00,0x00,0x1F,0xF0,0x00,0x00,0x00,0xFF,0x80,0x00, +0x00,0x07,0xFC,0x00,0x00,0x00,0x3F,0xE0,0x00,0x00, +0x08,0x3F,0xE0,0x00,0x00,0x01,0xFF,0x00,0x00,0x00, +0x1B,0xFF,0xFF,0xFF,0xFF,0xF0,0x05,0xE7,0x8B,0x71, +0xC0,0x00,0x0F,0xF0,0x00,0x3F,0xF0,0x00,0x7F,0xF0, +0x00,0xFF,0xF0,0x01,0xFF,0xF8,0x00,0x7F,0xFE,0x00, +0x7F,0xC1,0x00,0x1F,0xE0,0x34,0x03,0xF8,0x06,0x80, +0x7F,0x00,0xB0,0x0F,0xE0,0x12,0x03,0xF8,0x00,0x07, +0xF8,0x00,0x07,0xF0,0x00,0x0F,0xF0,0x00,0x3F,0xE0, +0x01,0xFF,0xC0,0x01,0xFF,0x80,0x01,0xFE,0x00,0x01, +0xFC,0x00,0x01,0xFE,0x00,0x01,0xFF,0x80,0x01,0xFF, +0xC0,0x00,0x3F,0xE0,0x00,0x0F,0xF0,0x00,0x07,0xF0, +0x00,0x07,0xF8,0x02,0x40,0x7F,0x00,0x68,0x07,0xF0, +0x0D,0x00,0xFE,0x01,0x60,0x1F,0xC0,0x00,0x1F,0xE0, +0x00,0x0F,0xE0,0x00,0x0F,0xF8,0x00,0x0F,0xFF,0xE0, +0x00,0xFF,0xF8,0x00,0x7F,0xF8,0x00,0x3F,0xF8,0x00, +0x1F,0xF8,0x00,0x03,0xF8,0x01,0xA7,0x1F,0x71,0x4D, +0xFF,0x7F,0xDF,0xF7,0xFD,0xFF,0x7F,0xDF,0xF7,0xFD, +0xFF,0x7F,0xDF,0xDF,0x80,0x05,0xE7,0x8F,0x71,0xC7, +0xF0,0x00,0x07,0xFE,0x00,0x07,0xFF,0x00,0x07,0xFF, +0x80,0x08,0xFF,0xF8,0x00,0xFF,0xFC,0x00,0x07,0xFC, +0x00,0x01,0xFC,0x00,0x01,0xFE,0x01,0xA0,0x1F,0xC0, +0x34,0x03,0xF8,0x05,0x80,0x7F,0x00,0x90,0x07,0xF0, +0x00,0x07,0xF8,0x00,0x03,0xF8,0x00,0x03,0xFC,0x00, +0x01,0xFF,0x00,0x00,0xFF,0xE0,0x00,0x7F,0xE0,0x00, +0x1F,0xE0,0x00,0x0F,0xE0,0x00,0x3F,0xE0,0x00,0x7F, +0xE0,0x00,0xFF,0xE0,0x01,0xFF,0x00,0x03,0xFC,0x00, +0x03,0xF8,0x00,0x07,0xF8,0x00,0x07,0xF0,0x10,0x01, +0xFE,0x03,0x40,0x3F,0x80,0x68,0x07,0xF0,0x0B,0x00, +0xFE,0x01,0x00,0x3F,0xC0,0x00,0xFF,0x80,0x23,0xFF, +0xF0,0x03,0xFF,0xE0,0x03,0xFF,0xC0,0x03,0xFF,0x80, +0x03,0xFF,0x00,0x03,0xFC,0x00,0x00,0x0A,0x47,0x90, +0xAB,0x00,0x07,0xF0,0x00,0x00,0x00,0x0F,0xFF,0x80, +0x00,0x01,0x07,0xFF,0xF8,0x00,0x00,0xC3,0xFF,0xFF, +0x80,0x00,0x71,0xFF,0xFF,0xF8,0x00,0x3C,0xFF,0xFF, +0xFF,0x00,0x3F,0x7F,0xFF,0xFF,0xF8,0x3F,0xDF,0xFF, +0xFF,0xFF,0xFF,0xF7,0xF8,0x3F,0xFF,0xFF,0xFD,0xF8, +0x01,0xFF,0xFF,0xFE,0x78,0x00,0x1F,0xFF,0xFF,0x1C, +0x00,0x01,0xFF,0xFF,0x86,0x00,0x00,0x3F,0xFF,0xC1, +0x00,0x00,0x03,0xFF,0xE0,0x00,0x00,0x00,0x1F,0xC0, +0x00,}; +/* font data size: 16081 bytes */ + +static const unsigned char Arial_60_index[] = { +0x00,0x00,0x00,0x50,0x06,0x40,0x2B,0x03,0x2C, +0x1F,0x40,0xF4,0x85,0x3C,0x15,0x18,0x5C,0x11,0x8D, +0xC6,0x85,0x1A,0xC0,0x6B,0xE1,0xB1,0x86,0xCC,0x1C, +0xD0,0x7E,0x62,0x0E,0xC9,0x41,0x29,0x28,0xB1,0x92, +0xF9,0x0C,0xF5,0x36,0x58,0xE8,0xB3,0xE1,0x8F,0x95, +0x3E,0xAD,0x06,0xE4,0x22,0x11,0x4B,0x48,0x59,0x4F, +0x75,0x81,0x97,0x10,0x61,0x05,0x94,0x86,0x60,0xD9, +0xB9,0x6C,0x21,0xB4,0x56,0xD5,0xDB,0xB9,0x74,0xD5, +0xD6,0x77,0x9C,0x1F,0x9E,0x83,0xAE,0x1A,0x18,0xC2, +0xE4,0x4B,0x96,0x9E,0x5E,0x69,0x9D,0x67,0xC7,0xA6, +0xCA,0xB4,0x0B,0x0F,0xED,0x3D,0xB5,0x72,0xDB,0xEB, +0x77,0x6E,0x42,0xB9,0x36,0xE6,0x5B,0xD1,0xEF,0xF9, +0xC2,0xAB,0x15,0xCC,0x83,0x32,0x44,0xCC,0x9B,0x38, +0xAC,0xE7,0x73,0xD2,0xD2,0xB7,0x4B,0xED,0x56,0xF5, +0xB1,0xD9,0x87,0x71,0xDD,0xF5,0x38,0x0E,0xE3,0x8F, +0x92,0x2E,0x5E,0x3A,0x21,0xEC,0x6B,0xBF,0x7F,0x33, +0xFD,0x64,0xF7,0x97,0xDF,0x9F,0x9F,0x40, +}; +/* font index size: 167 bytes */ + +const ILI9341_t3_font_t Arial_60 = { + Arial_60_index, + 0, + Arial_60_data, + 1, + 0, + 32, + 126, + 0, + 0, + 14, + 7, + 7, + 5, + 7, + 7, + 92, + 60 +}; + + + +static const unsigned char Arial_72_data[] = { +0x00,0x00,0x00,0x01,0xC0,0x02,0x64,0x2C,0x01,0xCD, +0xFF,0xEF,0xFF,0x7F,0xF9,0xFF,0xD7,0xF6,0xBF,0xAD, +0xFD,0xA7,0xC9,0x3E,0x68,0x03,0x7F,0xF1,0xFF,0x06, +0xCD,0x11,0x72,0x4D,0xFF,0x80,0x3F,0xFB,0xFF,0x00, +0x7F,0xDF,0xF0,0x07,0xFC,0xFF,0x00,0x3F,0xB1,0xFC, +0x00,0x7F,0x0F,0xC0,0x03,0xE4,0x9F,0x00,0x07,0xC0, +0x0D,0x64,0x04,0x03,0x88,0x00,0x00,0x1F,0xF0,0x00, +0xFF,0x80,0x00,0x00,0xFF,0xC0,0x07,0xFC,0x12,0x00, +0x00,0x7F,0xC0,0x03,0xFE,0x00,0x00,0x01,0xFF,0x00, +0x1F,0xF8,0x00,0x00,0x0F,0xFC,0x00,0x7F,0xC0,0x90, +0x00,0x07,0xFC,0x00,0x3F,0xE0,0x00,0x00,0x1F,0xF0, +0x01,0xFF,0x80,0x00,0x00,0xFF,0xC0,0x07,0xFC,0x04, +0x80,0x00,0x7F,0xC0,0x03,0xFE,0x00,0x00,0x01,0xFF, +0x00,0x1F,0xF8,0x00,0x00,0x0F,0xFC,0x00,0x7F,0xC0, +0x00,0x00,0x3F,0xE0,0x01,0xFF,0x00,0xDF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xC7,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xE0,0x00,0x1F,0xF0,0x00,0xFF,0x80,0x00,0x00, +0x7F,0xC0,0x07,0xFE,0x00,0x00,0x03,0xFF,0x00,0x1F, +0xF0,0x01,0x20,0x01,0xFF,0x00,0x0F,0xF8,0x00,0x00, +0x07,0xFC,0x00,0x7F,0xE0,0x00,0x00,0x3F,0xF0,0x01, +0xFF,0x00,0x09,0x00,0x1F,0xF0,0x00,0xFF,0x80,0x00, +0x00,0x7F,0xC0,0x07,0xFE,0x00,0x00,0x03,0xFF,0x00, +0x1F,0xF0,0x00,0x40,0x01,0xFF,0x00,0x0F,0xF8,0x00, +0x37,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF1,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xF0,0x07,0xFC,0x00,0x3F,0xE0, +0x00,0x00,0x1F,0xF0,0x01,0xFF,0x80,0x00,0x00,0xFF, +0xC0,0x07,0xFC,0x00,0x02,0x40,0x7F,0xC0,0x03,0xFE, +0x00,0x00,0x01,0xFF,0x00,0x1F,0xF8,0x00,0x00,0x0F, +0xFC,0x00,0x7F,0xC0,0x00,0x12,0x07,0xFC,0x00,0x3F, +0xE0,0x00,0x00,0x1F,0xF0,0x01,0xFF,0x80,0x00,0x00, +0xFF,0xC0,0x07,0xFC,0x00,0x00,0x90,0x7F,0xC0,0x03, +0xFE,0x00,0x00,0x01,0xFF,0x00,0x1F,0xF8,0x00,0x01, +0x01,0xFF,0x00,0x0F,0xF8,0x00,0x00,0x0B,0xEB,0x13, +0xB3,0x8A,0x00,0x00,0x07,0xC0,0x00,0x00,0x00,0x00, +0x3F,0xF8,0x00,0x00,0x00,0x03,0xFF,0xFF,0x80,0x00, +0x00,0x1F,0xFF,0xFF,0xE0,0x00,0x00,0x3F,0xFF,0xFF, +0xF8,0x00,0x00,0xFF,0xFF,0xFF,0xFC,0x00,0x01,0xFF, +0xFF,0xFF,0xFE,0x00,0x03,0xFF,0xFF,0xFF,0xFF,0x00, +0x03,0xFF,0xFF,0xFF,0xFF,0x80,0x07,0xFF,0xE7,0xFF, +0xFF,0xC0,0x0F,0xFF,0x07,0xCF,0xFF,0xC0,0x0F,0xFE, +0x07,0xC3,0xFF,0xE0,0x1F,0xFC,0x07,0xC0,0xFF,0xE0, +0x1F,0xF8,0x07,0xC0,0x7F,0xF0,0x1F,0xF0,0x07,0xC0, +0x3F,0xF0,0x3F,0xF0,0x07,0xC0,0x3F,0xF1,0x07,0xFC, +0x00,0xF8,0x03,0xFF,0x07,0xFC,0x00,0xF8,0x01,0xFF, +0x07,0xFC,0x00,0xF8,0x01,0xF0,0x24,0xFF,0x80,0x1F, +0x00,0x00,0x00,0xFF,0xC0,0x1F,0x00,0x00,0x00,0x7F, +0xC0,0x1F,0x00,0x00,0x00,0x7F,0xE0,0x1F,0x00,0x00, +0x00,0x7F,0xF0,0x1F,0x00,0x00,0x00,0x3F,0xF8,0x1F, +0x00,0x00,0x00,0x3F,0xFE,0x1F,0x00,0x00,0x00,0x1F, +0xFF,0x9F,0x00,0x00,0x00,0x1F,0xFF,0xFF,0x00,0x00, +0x00,0x0F,0xFF,0xFF,0x00,0x00,0x00,0x07,0xFF,0xFF, +0xE0,0x00,0x00,0x03,0xFF,0xFF,0xFE,0x00,0x00,0x00, +0xFF,0xFF,0xFF,0x80,0x00,0x00,0x3F,0xFF,0xFF,0xE0, +0x00,0x00,0x1F,0xFF,0xFF,0xF8,0x00,0x00,0x03,0xFF, +0xFF,0xFC,0x00,0x00,0x00,0xFF,0xFF,0xFF,0x00,0x00, +0x00,0x1F,0xFF,0xFF,0x00,0x00,0x00,0x1F,0xFF,0xFF, +0x80,0x00,0x00,0x1F,0x1F,0xFF,0xC0,0x00,0x00,0x1F, +0x07,0xFF,0xE0,0x00,0x00,0x1F,0x01,0xFF,0xE0,0x00, +0x00,0x1F,0x00,0x7F,0xF4,0x00,0x00,0x03,0xE0,0x07, +0xFE,0x80,0x00,0x00,0x7C,0x00,0x7F,0xF2,0x00,0x00, +0x0F,0x80,0x07,0xFC,0x1F,0x00,0x0F,0x80,0x07,0xFE, +0x3F,0xE0,0x01,0xF0,0x00,0xFF,0xBF,0xF0,0x01,0xF0, +0x00,0xFF,0xBF,0xF0,0x01,0xF0,0x01,0xFF,0x9F,0xF0, +0x01,0xF0,0x01,0xFF,0x1F,0xF8,0x01,0xF0,0x03,0xFF, +0x1F,0xFC,0x01,0xF0,0x03,0xFF,0x0F,0xFC,0x01,0xF0, +0x07,0xFE,0x0F,0xFE,0x01,0xF0,0x0F,0xFE,0x0F,0xFF, +0x01,0xF0,0x1F,0xFC,0x07,0xFF,0xC1,0xF0,0x7F,0xFC, +0x03,0xFF,0xF1,0xF1,0xFF,0xF8,0x03,0xFF,0xFF,0xFF, +0xFF,0xF0,0x01,0xFF,0xFF,0xFF,0xFF,0xE0,0x00,0xFF, +0xFF,0xFF,0xFF,0xC0,0x00,0x7F,0xFF,0xFF,0xFF,0x80, +0x00,0x3F,0xFF,0xFF,0xFF,0x00,0x00,0x1F,0xFF,0xFF, +0xFC,0x00,0x00,0x07,0xFF,0xFF,0xF0,0x00,0x00,0x00, +0xFF,0xFF,0x00,0x00,0x00,0x00,0x0F,0xF0,0x00,0x00, +0x68,0x00,0x00,0x3E,0x00,0x00,0x08,0x00,0x00,0x07, +0xC0,0x00,0x00,0x13,0x65,0x1B,0xFD,0x90,0x00,0xFF, +0x00,0x00,0x00,0x00,0x1F,0xE0,0x00,0x00,0x1F,0xFF, +0x00,0x00,0x00,0x00,0x7F,0x80,0x00,0x00,0xFF,0xFF, +0x00,0x00,0x00,0x03,0xFC,0x00,0x00,0x0F,0xFF,0xFE, +0x00,0x00,0x00,0x0F,0xE0,0x00,0x00,0x3F,0xFF,0xFC, +0x00,0x00,0x00,0x7F,0x80,0x00,0x01,0xFF,0xFF,0xF8, +0x00,0x00,0x01,0xFC,0x00,0x00,0x0F,0xF8,0x1F,0xF0, +0x00,0x00,0x0F,0xF0,0x00,0x00,0x3F,0xC0,0x3F,0xC0, +0x00,0x00,0x3F,0x80,0x00,0x01,0xFE,0x00,0x7F,0x80, +0x00,0x01,0xFE,0x00,0x00,0x07,0xF0,0x00,0xFE,0x00, +0x00,0x0F,0xF0,0x00,0x00,0x3F,0x80,0x01,0xFC,0x00, +0x00,0x3F,0xC0,0x00,0x02,0x1F,0xC0,0x00,0xFE,0x00, +0x00,0x3F,0xC0,0x00,0x00,0x7F,0x00,0x01,0xF8,0x00, +0x01,0xFE,0x00,0x00,0x03,0xF8,0x00,0x07,0xF0,0x00, +0x07,0xF8,0x00,0x00,0x11,0xFC,0x00,0x03,0xF8,0x00, +0x07,0xF8,0x00,0x00,0x07,0xF0,0x00,0x0F,0xE0,0x00, +0x3F,0xC0,0x00,0x00,0x1F,0xC0,0x00,0x3F,0x80,0x00, +0xFE,0x00,0x00,0x00,0x7F,0x00,0x00,0xFE,0x00,0x07, +0xF8,0x00,0x00,0x01,0xFC,0x00,0x03,0xF8,0x00,0x1F, +0xC0,0x00,0x00,0x07,0xF0,0x00,0x0F,0xE0,0x00,0xFF, +0x00,0x00,0x00,0x1F,0xC0,0x00,0x3F,0x80,0x03,0xF8, +0x00,0x00,0x00,0x7F,0x00,0x00,0xFE,0x00,0x1F,0xE0, +0x00,0x00,0x01,0xFC,0x00,0x03,0xF8,0x00,0xFF,0x00, +0x00,0x00,0x03,0xF0,0x00,0x1F,0xC0,0x03,0xFC,0x00, +0x00,0x00,0x21,0xFC,0x00,0x0F,0xE0,0x03,0xFC,0x00, +0x00,0x00,0x07,0xF0,0x00,0x3F,0x80,0x1F,0xE0,0x00, +0x00,0x00,0x0F,0xE0,0x01,0xFC,0x00,0x7F,0x80,0x00, +0x00,0x00,0x3F,0xC0,0x0F,0xF0,0x03,0xFC,0x00,0x00, +0x00,0x00,0x7F,0x80,0x7F,0x80,0x0F,0xF0,0x00,0x00, +0x00,0x01,0xFF,0x03,0xFE,0x00,0x7F,0x80,0x00,0x00, +0x00,0x03,0xFF,0xFF,0xF0,0x01,0xFC,0x00,0x00,0x00, +0x00,0x07,0xFF,0xFF,0x80,0x0F,0xF0,0x00,0x00,0x00, +0x00,0x0F,0xFF,0xFC,0x00,0x3F,0x80,0x00,0xFF,0x00, +0x00,0x1F,0xFF,0xE0,0x01,0xFE,0x00,0x1F,0xFF,0x00, +0x00,0x3F,0xFE,0x00,0x07,0xF0,0x00,0xFF,0xFF,0x00, +0x00,0x1F,0xE0,0x00,0x3F,0xC0,0x0F,0xFF,0xFE,0x00, +0x00,0x00,0x00,0x01,0xFE,0x00,0x3F,0xFF,0xFC,0x00, +0x00,0x00,0x00,0x07,0xF8,0x01,0xFF,0xFF,0xF8,0x00, +0x00,0x00,0x00,0x3F,0xC0,0x0F,0xF8,0x1F,0xF0,0x00, +0x00,0x00,0x00,0xFF,0x00,0x3F,0xC0,0x3F,0xC0,0x00, +0x00,0x00,0x07,0xF8,0x01,0xFE,0x00,0x7F,0x80,0x00, +0x00,0x00,0x1F,0xE0,0x07,0xF0,0x00,0xFE,0x40,0x00, +0x00,0x00,0x1F,0xE0,0x07,0xF0,0x00,0x3F,0x80,0x00, +0x00,0x00,0xFF,0x00,0x1F,0xC0,0x00,0xFE,0x00,0x00, +0x00,0x03,0xF8,0x00,0xFF,0x00,0x01,0xF8,0x00,0x00, +0x00,0x1F,0xE0,0x03,0xF8,0x00,0x07,0xF0,0x00,0x00, +0x00,0x7F,0x00,0x0F,0xE0,0x00,0x1F,0xC0,0x00,0x00, +0x03,0xFC,0x00,0x3F,0x80,0x00,0x7F,0x80,0x00,0x00, +0x03,0xFC,0x00,0x1F,0xC0,0x00,0x3F,0xC0,0x00,0x00, +0x03,0xFC,0x00,0x0F,0xE0,0x00,0x1F,0xE0,0x00,0x00, +0x03,0xFC,0x00,0x07,0xF0,0x00,0x0F,0xF0,0x00,0x00, +0x03,0xFC,0x00,0x03,0xF8,0x00,0x07,0xF0,0x00,0x00, +0x1F,0xE0,0x00,0x07,0xE0,0x00,0x3F,0x80,0x00,0x00, +0x7F,0x80,0x00,0x1F,0xC0,0x00,0xFE,0x00,0x00,0x03, +0xFC,0x00,0x00,0x7F,0x00,0x03,0xF8,0x00,0x00,0x0F, +0xE0,0x00,0x01,0xFC,0x00,0x0F,0xE0,0x00,0x00,0x7F, +0x80,0x00,0x03,0xF8,0x00,0x7F,0x00,0x00,0x01,0xFC, +0x00,0x00,0x0F,0xF0,0x03,0xFC,0x00,0x00,0x0F,0xF0, +0x00,0x00,0x1F,0xE0,0x1F,0xE0,0x00,0x00,0x7F,0x80, +0x00,0x00,0x7F,0xC0,0xFF,0x80,0x00,0x01,0xFE,0x00, +0x00,0x00,0xFF,0xFF,0xFC,0x00,0x00,0x0F,0xF0,0x00, +0x00,0x01,0xFF,0xFF,0xE0,0x00,0x00,0x3F,0xC0,0x00, +0x00,0x03,0xFF,0xFF,0x00,0x00,0x01,0xFE,0x00,0x00, +0x00,0x07,0xFF,0xF8,0x00,0x00,0x07,0xF8,0x00,0x00, +0x00,0x0F,0xFF,0x80,0x00,0x00,0x3F,0xC0,0x00,0x00, +0x00,0x07,0xF8,0x00,0x0F,0x25,0x17,0xFC,0x30,0x00, +0x00,0x1F,0xF8,0x00,0x00,0x00,0x00,0x00,0x07,0xFF, +0xF8,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xF0,0x00, +0x00,0x00,0x00,0x0F,0xFF,0xFF,0xC0,0x00,0x00,0x00, +0x01,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x1F,0xFF, +0xFF,0xFC,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xF0, +0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFF,0xC0,0x00,0x00, +0x00,0xFF,0xF8,0x1F,0xFE,0x00,0x00,0x00,0x07,0xFE, +0x00,0x3F,0xF8,0x00,0x00,0x00,0x7F,0xE0,0x00,0xFF, +0xC0,0x00,0x00,0x03,0xFE,0x00,0x03,0xFE,0x00,0x00, +0x00,0x3F,0xF0,0x00,0x1F,0xF8,0x00,0x06,0x00,0x3F, +0xE0,0x00,0x0F,0xF8,0x00,0x00,0x01,0xFF,0x80,0x00, +0xFF,0x80,0x00,0x00,0x07,0xFC,0x00,0x07,0xFC,0x00, +0x00,0x00,0x3F,0xF0,0x00,0x7F,0xE0,0x00,0x00,0x01, +0xFF,0x80,0x07,0xFE,0x00,0x00,0x00,0x07,0xFE,0x00, +0x7F,0xE0,0x00,0x00,0x00,0x3F,0xF8,0x07,0xFF,0x00, +0x00,0x00,0x00,0xFF,0xE0,0xFF,0xF0,0x00,0x00,0x00, +0x07,0xFF,0x1F,0xFF,0x00,0x00,0x00,0x00,0x1F,0xFF, +0xFF,0xF0,0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF,0x00, +0x00,0x00,0x00,0x03,0xFF,0xFF,0xE0,0x00,0x00,0x00, +0x00,0x0F,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x3F, +0xFF,0xC0,0x00,0x00,0x00,0x00,0x03,0xFF,0xF8,0x00, +0x00,0x00,0x00,0x00,0x7F,0xFF,0x80,0x00,0x00,0x00, +0x00,0x07,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0xFF, +0xFF,0xF0,0x00,0x00,0x00,0x00,0x0F,0xFF,0xFF,0xC0, +0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0x00,0x00,0x00, +0x00,0x0F,0xFF,0x1F,0xFC,0x00,0x00,0x00,0x00,0xFF, +0xF0,0xFF,0xF0,0x00,0x00,0x00,0x0F,0xFF,0x03,0xFF, +0xC0,0x03,0xC0,0x00,0xFF,0xE0,0x0F,0xFE,0x00,0x3F, +0xF0,0x0F,0xFE,0x00,0x3F,0xF8,0x01,0xFF,0x80,0x7F, +0xE0,0x00,0xFF,0xE0,0x1F,0xF8,0x07,0xFE,0x00,0x07, +0xFF,0x80,0xFF,0xC0,0x3F,0xE0,0x00,0x1F,0xFE,0x0F, +0xFE,0x03,0xFF,0x00,0x00,0x7F,0xF0,0x7F,0xE0,0x1F, +0xF0,0x00,0x01,0xFF,0xC7,0xFF,0x00,0xFF,0x80,0x00, +0x07,0xFF,0x7F,0xF8,0x0F,0xF8,0x00,0x00,0x3F,0xFF, +0xFF,0x80,0x7F,0xC0,0x00,0x00,0xFF,0xFF,0xFC,0x03, +0xFE,0x00,0x00,0x03,0xFF,0xFF,0xC0,0x1F,0xF0,0x00, +0x00,0x0F,0xFF,0xFE,0x00,0xFF,0x80,0x00,0x00,0x3F, +0xFF,0xE0,0x07,0xFC,0x00,0x00,0x01,0xFF,0xFE,0x00, +0x3F,0xE0,0x00,0x00,0x07,0xFF,0xF0,0x01,0xFF,0x80, +0x00,0x00,0x1F,0xFF,0x00,0x0F,0xFC,0x00,0x00,0x00, +0x7F,0xFC,0x00,0x3F,0xF0,0x00,0x00,0x07,0xFF,0xE0, +0x01,0xFF,0x80,0x00,0x00,0x7F,0xFF,0x80,0x0F,0xFE, +0x00,0x00,0x03,0xFF,0xFE,0x00,0x3F,0xF8,0x00,0x00, +0x7F,0xFF,0xF8,0x01,0xFF,0xC0,0x00,0x07,0xFF,0xFF, +0xE0,0x07,0xFF,0x00,0x00,0x7F,0xFF,0xFF,0x80,0x1F, +0xFE,0x00,0x0F,0xFF,0xDF,0xFE,0x00,0xFF,0xFC,0x03, +0xFF,0xFC,0x7F,0xFC,0x03,0xFF,0xFF,0xFF,0xFF,0xC1, +0xFF,0xF0,0x0F,0xFF,0xFF,0xFF,0xFC,0x07,0xFF,0xC0, +0x3F,0xFF,0xFF,0xFF,0x80,0x3F,0xFC,0x00,0xFF,0xFF, +0xFF,0xF8,0x00,0x7F,0xC0,0x01,0xFF,0xFF,0xFF,0x80, +0x01,0xFC,0x00,0x07,0xFF,0xFF,0xF0,0x00,0x07,0xC0, +0x00,0x07,0xFF,0xFC,0x00,0x00,0x1C,0x00,0x00,0x07, +0xFF,0x00,0x00,0x00,0x40,0x02,0x4D,0x15,0x71,0x3D, +0xFF,0xEF,0xFE,0x3F,0xF8,0xFE,0x3F,0x24,0xF8,0x06, +0x2E,0x1B,0x62,0x10,0x00,0x01,0xF8,0x00,0x01,0xF8, +0x00,0x01,0xF8,0x00,0x01,0xFC,0x00,0x00,0xFC,0x00, +0x00,0xFE,0x20,0x00,0x1F,0xC0,0x00,0x1F,0xC1,0x00, +0x03,0xF8,0x00,0x03,0xF8,0x00,0x03,0xFC,0x00,0x01, +0xFC,0x00,0x01,0xFE,0x00,0x00,0xFE,0x00,0x80,0x1F, +0xE0,0x08,0x03,0xFC,0x00,0x90,0x7F,0x80,0x08,0x0F, +0xF0,0x00,0x81,0xFF,0x00,0x00,0xFF,0x00,0x04,0x9F, +0xF0,0x00,0x0F,0xF0,0x00,0x2D,0xFF,0x00,0x00,0xFF, +0x00,0x01,0xBF,0xF0,0x00,0x1B,0xFF,0x00,0x01,0x1F, +0xF0,0x00,0x07,0xF8,0x00,0x0B,0x7F,0xC0,0x00,0x1F, +0xE0,0x00,0x49,0xFF,0x00,0x00,0x7F,0x80,0x02,0x07, +0xFC,0x00,0x01,0xFE,0x00,0x00,0xFF,0x80,0x08,0x07, +0xF8,0x00,0x03,0xFE,0x00,0x40,0x1F,0xE0,0x04,0x00, +0xFF,0x00,0x40,0x07,0xF8,0x00,0x01,0xFC,0x00,0x00, +0xFF,0x00,0x00,0x3F,0x80,0x80,0x01,0xFC,0x08,0x00, +0x0F,0xE0,0x00,0x03,0xF8,0x40,0x00,0x1F,0xC0,0x00, +0x07,0xF0,0x00,0x01,0xF8,0x00,0x00,0x7E,0x00,0x00, +0x1F,0x80,0x06,0x2E,0x0F,0x62,0x17,0xE0,0x00,0x01, +0xF8,0x00,0x00,0xFE,0x00,0x00,0x3F,0x80,0x00,0x0F, +0xC0,0x00,0x07,0xF0,0x00,0x20,0x3F,0x80,0x00,0x0F, +0xE0,0x01,0x00,0x7F,0x00,0x00,0x1F,0xC0,0x00,0x0F, +0xF0,0x00,0x03,0xF8,0x00,0x01,0xFE,0x00,0x00,0x7F, +0x00,0x80,0x07,0xF8,0x08,0x00,0x3F,0xC0,0x90,0x01, +0xFE,0x08,0x00,0x0F,0xF0,0x80,0x00,0xFF,0x80,0x00, +0x3F,0xC4,0x80,0x03,0xFE,0x00,0x00,0xFF,0x30,0x00, +0x0F,0xFB,0x40,0x00,0x7F,0xF4,0x00,0x07,0xFE,0x00, +0x00,0x7F,0xF0,0x00,0x0F,0xFA,0x40,0x01,0xFF,0x20, +0x00,0x1F,0xE0,0x00,0x1F,0xF1,0x00,0x01,0xFE,0x00, +0x01,0xFF,0x08,0x00,0x1F,0xE0,0x00,0x1F,0xF0,0x40, +0x01,0xFE,0x04,0x00,0x3F,0xC0,0x40,0x07,0xF8,0x04, +0x00,0xFF,0x00,0x00,0x7F,0x00,0x20,0x0F,0xE0,0x00, +0x0F,0xE0,0x00,0x0F,0xF0,0x00,0x07,0xF0,0x00,0x07, +0xF0,0x00,0x03,0xF0,0x00,0x03,0xF8,0x00,0x01,0xF8, +0x00,0x01,0xF8,0x00,0x01,0xF8,0x00,0x00,0x08,0x4F, +0x0D,0x52,0x7D,0x00,0x07,0xF0,0x00,0x08,0x01,0xF8, +0x00,0x83,0xC0,0x3E,0x01,0xE0,0xFE,0x0F,0x83,0xF8, +0x7F,0xE3,0xE3,0xFF,0x1F,0xFE,0xFB,0xFF,0xC7,0xFF, +0xFF,0xFF,0xF3,0xFF,0xFF,0xFF,0xFE,0x3F,0xFF,0xFF, +0xFE,0x00,0xFF,0xFF,0xFC,0x00,0x01,0xFF,0xC0,0x00, +0x00,0x3F,0xE0,0x00,0x00,0x1F,0xFC,0x00,0x00,0x0F, +0xFF,0x80,0x00,0x07,0xF7,0xF0,0x00,0x03,0xF9,0xFE, +0x00,0x01,0xFE,0x3F,0xC0,0x00,0xFF,0x07,0xF8,0x00, +0x7F,0xC1,0xFF,0x00,0x3F,0xE0,0x3F,0xE0,0x07,0xF0, +0x07,0xF0,0x00,0xFC,0x01,0xF8,0x00,0x0E,0x00,0x38, +0x00,0x01,0x00,0x04,0x00,0x0C,0x18,0x14,0x5B,0xAD, +0x00,0x00,0x0F,0xF0,0x00,0x00,0xD0,0x00,0x00,0xFF, +0x00,0x00,0x0C,0x00,0x00,0x0F,0xF0,0x00,0x00,0xDF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xF7,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFE,0x80,0x00,0x07,0xF8,0x00,0x00,0x68,0x00, +0x00,0x7F,0x80,0x00,0x06,0x00,0x00,0x07,0xF8,0x00, +0x00,0x00,0x02,0x4C,0x27,0x89,0xCD,0xFF,0xC7,0xFF, +0x03,0xE0,0xF4,0x0F,0x87,0xC3,0xF1,0xF8,0x3C,0x0E, +0x01,0x00,0x06,0xC4,0x0C,0xAA,0x1D,0xFF,0xFF,0xFF, +0xEF,0xFF,0xFF,0xFE,0x02,0x44,0xA4,0x01,0xCD,0xFF, +0xC7,0xFC,0x07,0x64,0x00,0x01,0xC8,0x00,0x00,0x07, +0xF8,0x00,0x00,0x3F,0xF0,0x00,0x00,0x1F,0xE0,0x00, +0x00,0xFF,0xA4,0x00,0x00,0x7F,0x80,0x00,0x03,0xFE, +0x40,0x00,0x01,0xFE,0x00,0x00,0x0F,0xF8,0x80,0x00, +0x07,0xF8,0x00,0x00,0x3F,0xE1,0x20,0x00,0x1F,0xE0, +0x00,0x00,0xFF,0x82,0x00,0x00,0x7F,0x80,0x00,0x03, +0xFE,0x04,0x80,0x01,0xFE,0x00,0x00,0x0F,0xF8,0x08, +0x00,0x07,0xF8,0x00,0x00,0x3F,0xE0,0x12,0x00,0x1F, +0xE0,0x00,0x00,0xFF,0x80,0x20,0x00,0x7F,0x80,0x00, +0x03,0xFE,0x00,0x40,0x01,0xFE,0x00,0x00,0x0F,0xF8, +0x00,0x90,0x07,0xF8,0x00,0x00,0x3F,0xE0,0x01,0x00, +0x1F,0xE0,0x00,0x00,0xFF,0x80,0x02,0x40,0x7F,0x80, +0x00,0x03,0xFE,0x00,0x04,0x01,0xFE,0x00,0x00,0x0F, +0xF8,0x00,0x09,0x07,0xF8,0x00,0x00,0x3F,0xE0,0x00, +0x10,0x1F,0xE0,0x00,0x00,0xFF,0x80,0x00,0x20,0x7F, +0x80,0x00,0x03,0xFE,0x00,0x00,0x49,0xFE,0x00,0x00, +0x0F,0xF8,0x00,0x00,0x87,0xF8,0x00,0x00,0x3F,0xE0, +0x00,0x00,0xFF,0x00,0x00,0x00,0x0B,0xA4,0x97,0xFB, +0x80,0x00,0x01,0xFF,0x80,0x00,0x00,0x00,0x1F,0xFF, +0xE0,0x00,0x00,0x01,0xFF,0xFF,0xF8,0x00,0x00,0x07, +0xFF,0xFF,0xF8,0x00,0x00,0x1F,0xFF,0xFF,0xF8,0x01, +0x00,0x1F,0xFF,0xFF,0xFF,0x80,0x00,0x7F,0xFF,0xFF, +0xFF,0x80,0x01,0xFF,0xF0,0x1F,0xFF,0x80,0x07,0xFF, +0x80,0x07,0xFF,0x80,0x0F,0xFE,0x00,0x07,0xFF,0x00, +0x3F,0xF0,0x00,0x07,0xFF,0x00,0x7F,0xE0,0x00,0x07, +0xFE,0x01,0xFF,0x80,0x00,0x07,0xFC,0x20,0x7F,0xC0, +0x00,0x00,0xFF,0x8A,0x3F,0xE0,0x00,0x00,0x1F,0xF3, +0x1F,0xF0,0x00,0x00,0x03,0xFE,0xDF,0xF8,0x00,0x00, +0x00,0x7F,0xF7,0xFE,0x00,0x00,0x00,0x1F,0xFD,0xFF, +0x80,0x00,0x00,0x07,0xFC,0xFF,0x00,0x00,0x00,0x1F, +0xF5,0xBF,0xE0,0x00,0x00,0x07,0xFC,0x3F,0xC0,0x00, +0x00,0x1F,0xF2,0x4F,0xF8,0x00,0x00,0x07,0xFC,0x81, +0xFF,0x00,0x00,0x03,0xFE,0x03,0xFF,0x00,0x00,0x0F, +0xFC,0x03,0xFF,0x00,0x00,0x3F,0xF0,0x07,0xFF,0x00, +0x00,0xFF,0xE0,0x07,0xFF,0x00,0x03,0xFF,0x80,0x0F, +0xFF,0x00,0x0F,0xFF,0x00,0x0F,0xFF,0xC0,0xFF,0xFC, +0x00,0x0F,0xFF,0xFF,0xFF,0xF0,0x00,0x1F,0xFF,0xFF, +0xFF,0xC0,0x00,0x1F,0xFF,0xFF,0xFF,0x80,0x00,0x1F, +0xFF,0xFF,0xFE,0x00,0x00,0x0F,0xFF,0xFF,0xF0,0x00, +0x00,0x0F,0xFF,0xFF,0xC0,0x00,0x00,0x07,0xFF,0xFE, +0x00,0x00,0x00,0x00,0xFF,0xC0,0x00,0x00,0x06,0xE4, +0x2C,0x03,0x80,0x00,0x00,0x3F,0x80,0x00,0x00,0xFE, +0x00,0x00,0x1F,0xE0,0x00,0x03,0xFE,0x00,0x00,0x7F, +0xE0,0x00,0x0F,0xFE,0x00,0x01,0xFF,0xE0,0x00,0x3F, +0xFE,0x00,0x07,0xFF,0xE0,0x00,0xFF,0xFE,0x00,0x1F, +0xFF,0xE0,0x03,0xFF,0xFE,0x00,0xFF,0xFF,0xE0,0x1F, +0xFF,0xFE,0x07,0xFF,0xFF,0xE1,0xFF,0xFB,0xFE,0x7F, +0xFF,0x3F,0xEF,0xFF,0xE3,0xFE,0xFF,0xF8,0x3F,0xEF, +0xFF,0x03,0xFE,0xFF,0xC0,0x3F,0xEF,0xF8,0x03,0xFE, +0xFE,0x00,0x3F,0xEF,0x80,0x03,0xFE,0xE0,0x00,0x3F, +0xFA,0x00,0x00,0x7F,0xF4,0x00,0x00,0xFF,0xE8,0x00, +0x01,0xFF,0xD0,0x00,0x03,0xFF,0xA0,0x00,0x07,0xFF, +0x40,0x00,0x0F,0xFD,0x00,0x00,0x1F,0xF0,0x0B,0xE4, +0x0C,0x03,0x80,0x00,0x01,0xFF,0xC0,0x00,0x00,0x00, +0x1F,0xFF,0xFC,0x00,0x00,0x00,0x7F,0xFF,0xFF,0x00, +0x00,0x01,0xFF,0xFF,0xFF,0xC0,0x00,0x03,0xFF,0xFF, +0xFF,0xF0,0x00,0x0F,0xFF,0xFF,0xFF,0xF8,0x00,0x1F, +0xFF,0xFF,0xFF,0xFC,0x00,0x1F,0xFF,0xFF,0xFF,0xFE, +0x00,0x3F,0xFF,0x00,0x7F,0xFE,0x00,0x7F,0xFC,0x00, +0x0F,0xFF,0x00,0x7F,0xF0,0x00,0x07,0xFF,0x80,0xFF, +0xE0,0x00,0x03,0xFF,0x80,0xFF,0xC0,0x00,0x01,0xFF, +0xC1,0xFF,0x80,0x00,0x00,0xFF,0xC1,0xFF,0x00,0x00, +0x00,0x7F,0xC1,0xFF,0x00,0x00,0x00,0x7F,0xE3,0xFF, +0x00,0x00,0x00,0x3F,0xE9,0x7F,0xC0,0x00,0x00,0x07, +0xFC,0x07,0xC0,0x00,0x00,0x07,0xFD,0x00,0x00,0x00, +0x00,0x00,0xFF,0xA0,0x00,0x00,0x00,0x00,0x3F,0xF0, +0x00,0x00,0x00,0x00,0x3F,0xE4,0x00,0x00,0x00,0x00, +0x0F,0xFC,0x80,0x00,0x00,0x00,0x03,0xFF,0x00,0x00, +0x00,0x00,0x07,0xFE,0x00,0x00,0x00,0x00,0x0F,0xFE, +0x00,0x00,0x00,0x00,0x1F,0xFC,0x00,0x00,0x00,0x00, +0x3F,0xFC,0x00,0x00,0x00,0x00,0x7F,0xF8,0x00,0x00, +0x00,0x00,0x7F,0xF0,0x00,0x00,0x00,0x00,0xFF,0xF0, +0x00,0x00,0x00,0x03,0xFF,0xE0,0x00,0x00,0x00,0x07, +0xFF,0xC0,0x00,0x00,0x00,0x0F,0xFF,0x80,0x00,0x00, +0x00,0x1F,0xFF,0x00,0x00,0x00,0x00,0x3F,0xFE,0x00, +0x00,0x00,0x00,0x7F,0xFC,0x00,0x00,0x00,0x00,0xFF, +0xF8,0x00,0x00,0x00,0x01,0xFF,0xF0,0x00,0x00,0x00, +0x03,0xFF,0xE0,0x00,0x00,0x00,0x0F,0xFF,0xC0,0x00, +0x00,0x00,0x1F,0xFF,0x80,0x00,0x00,0x00,0x3F,0xFE, +0x00,0x00,0x00,0x00,0x7F,0xFC,0x00,0x00,0x00,0x00, +0xFF,0xF8,0x00,0x00,0x00,0x01,0xFF,0xF0,0x00,0x00, +0x00,0x03,0xFF,0xE0,0x00,0x00,0x00,0x07,0xFF,0x80, +0x00,0x00,0x00,0x0F,0xFF,0x00,0x00,0x00,0x00,0x1F, +0xFE,0x00,0x00,0x00,0x00,0x3F,0xFC,0x00,0x00,0x00, +0x00,0x7F,0xF8,0x00,0x00,0x00,0x00,0x7F,0xF0,0x00, +0x00,0x00,0x00,0xFF,0xE0,0x00,0x00,0x00,0x01,0xFF, +0xC0,0x00,0x00,0x00,0x01,0xFF,0x80,0x00,0x00,0x00, +0x03,0xFF,0x00,0x00,0x00,0x00,0x03,0xFF,0xFF,0xFF, +0xFF,0xFF,0xF2,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x0B,0xA4,0x97,0xFB, +0x80,0x00,0x03,0xFE,0x00,0x00,0x00,0x00,0x3F,0xFF, +0xC0,0x00,0x00,0x01,0xFF,0xFF,0xE0,0x00,0x00,0x0F, +0xFF,0xFF,0xF0,0x00,0x00,0x3F,0xFF,0xFF,0xF0,0x00, +0x01,0xFF,0xFF,0xFF,0xF0,0x00,0x03,0xFF,0xFF,0xFF, +0xF0,0x00,0x0F,0xFF,0xFF,0xFF,0xF0,0x00,0x3F,0xFE, +0x01,0xFF,0xF0,0x00,0xFF,0xF0,0x00,0xFF,0xF0,0x01, +0xFF,0xC0,0x00,0xFF,0xE0,0x07,0xFF,0x00,0x00,0xFF, +0xE0,0x0F,0xFC,0x00,0x00,0xFF,0xC0,0x3F,0xF0,0x00, +0x00,0xFF,0x80,0x7F,0xE0,0x00,0x01,0xFF,0x80,0xFF, +0x80,0x00,0x01,0xFF,0x08,0x7F,0xE0,0x00,0x00,0x7F, +0xC0,0xFF,0x80,0x00,0x00,0xFF,0x80,0x1F,0x00,0x00, +0x01,0xFF,0x08,0x00,0x00,0x00,0x00,0x7F,0xC0,0x00, +0x00,0x00,0x01,0xFF,0x84,0x00,0x00,0x00,0x00,0x7F, +0xC0,0x00,0x00,0x00,0x01,0xFF,0x00,0x00,0x00,0x00, +0x07,0xFE,0x00,0x00,0x00,0x00,0x1F,0xF8,0x00,0x00, +0x00,0x00,0xFF,0xE0,0x00,0x00,0x00,0x0F,0xFF,0x80, +0x00,0x00,0x07,0xFF,0xFE,0x00,0x00,0x00,0x0F,0xFF, +0xF8,0x00,0x00,0x00,0x1F,0xFF,0xC0,0x00,0x00,0x00, +0x3F,0xFF,0xC0,0x00,0x00,0x00,0x7F,0xFF,0xF0,0x00, +0x00,0x00,0xFF,0xFF,0xF0,0x00,0x00,0x03,0xFF,0xFF, +0xF8,0x00,0x00,0x07,0x01,0xFF,0xF8,0x00,0x00,0x00, +0x00,0x7F,0xF8,0x00,0x00,0x00,0x00,0x7F,0xF8,0x00, +0x00,0x00,0x00,0x3F,0xF0,0x00,0x00,0x00,0x00,0x3F, +0xF0,0x00,0x00,0x00,0x00,0x3F,0xE0,0x00,0x00,0x00, +0x00,0x7F,0xE8,0x00,0x00,0x00,0x00,0x0F,0xF8,0x00, +0x00,0x00,0x00,0x1F,0xFD,0x80,0x00,0x00,0x00,0x03, +0xFE,0x0F,0x80,0x00,0x00,0x07,0xFD,0xFF,0x00,0x00, +0x00,0x0F,0xFB,0xFF,0x00,0x00,0x00,0x1F,0xF7,0xFE, +0x00,0x00,0x00,0x7F,0xE7,0xFC,0x00,0x00,0x00,0xFF, +0xA1,0xFF,0x80,0x00,0x00,0x7F,0xE3,0xFF,0x80,0x00, +0x01,0xFF,0x83,0xFF,0x00,0x00,0x07,0xFF,0x07,0xFF, +0x00,0x00,0x1F,0xFC,0x07,0xFF,0x00,0x00,0x7F,0xF8, +0x07,0xFF,0x80,0x01,0xFF,0xE0,0x0F,0xFF,0xC0,0x1F, +0xFF,0x80,0x0F,0xFF,0xFF,0xFF,0xFE,0x00,0x0F,0xFF, +0xFF,0xFF,0xF8,0x00,0x0F,0xFF,0xFF,0xFF,0xE0,0x00, +0x0F,0xFF,0xFF,0xFF,0x80,0x00,0x07,0xFF,0xFF,0xFC, +0x00,0x00,0x07,0xFF,0xFF,0xF0,0x00,0x00,0x01,0xFF, +0xFF,0x00,0x00,0x00,0x00,0x7F,0xF0,0x00,0x00,0x0C, +0xA3,0x84,0x03,0x80,0x00,0x00,0x00,0x01,0xFC,0x00, +0x00,0x00,0x00,0x00,0x7F,0x80,0x00,0x00,0x00,0x00, +0x1F,0xF0,0x04,0x00,0x00,0x00,0x00,0xFF,0xC0,0x00, +0x00,0x00,0x00,0x3F,0xF8,0x00,0x00,0x00,0x00,0x0F, +0xFF,0x00,0x40,0x00,0x00,0x00,0x7F,0xFC,0x00,0x00, +0x00,0x00,0x1F,0xFF,0x80,0x00,0x00,0x00,0x07,0xFF, +0xF0,0x04,0x00,0x00,0x00,0x3F,0xFF,0xC0,0x00,0x00, +0x00,0x0F,0xFF,0xF8,0x00,0x00,0x00,0x03,0xFF,0xFF, +0x00,0x40,0x00,0x00,0x1F,0xFF,0xFC,0x00,0x00,0x00, +0x07,0xFF,0xFF,0x80,0x00,0x00,0x01,0xFF,0xDF,0xF0, +0x00,0x00,0x00,0x7F,0xF3,0xFE,0x00,0x00,0x00,0x1F, +0xFE,0x7F,0xC0,0x00,0x00,0x03,0xFF,0x8F,0xF8,0x00, +0x00,0x00,0xFF,0xE1,0xFF,0x00,0x00,0x00,0x3F,0xF8, +0x3F,0xE0,0x00,0x00,0x0F,0xFF,0x07,0xFC,0x00,0x00, +0x01,0xFF,0xC0,0xFF,0x80,0x00,0x00,0x7F,0xF0,0x1F, +0xF0,0x00,0x00,0x1F,0xFC,0x03,0xFE,0x00,0x80,0x00, +0xFF,0xE0,0x0F,0xF8,0x00,0x00,0x3F,0xF8,0x01,0xFF, +0x00,0x00,0x0F,0xFE,0x00,0x3F,0xE0,0x08,0x00,0x7F, +0xF0,0x00,0xFF,0x80,0x00,0x1F,0xFC,0x00,0x1F,0xF0, +0x00,0x07,0xFF,0x00,0x03,0xFE,0x00,0x80,0x3F,0xF8, +0x00,0x0F,0xF8,0x00,0x0F,0xFE,0x00,0x01,0xFF,0x00, +0x03,0xFF,0x80,0x00,0x3F,0xE0,0x08,0x1F,0xFC,0x00, +0x00,0xFF,0x80,0x07,0xFF,0x00,0x00,0x1F,0xF0,0x01, +0xFF,0xC0,0x00,0x03,0xFE,0x00,0x7F,0xF0,0x00,0x00, +0x7F,0xC0,0x1B,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xC7, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xA0,0x00,0x00,0x00, +0x1F,0xF0,0x06,0x80,0x00,0x00,0x00,0x7F,0xC0,0x12, +0x00,0x00,0x00,0x01,0xFF,0x00,0x00,0x0B,0xA4,0x17, +0xFB,0x89,0x00,0xFF,0xFF,0xFF,0xFF,0xC2,0xC0,0x7F, +0xFF,0xFF,0xFF,0xF0,0x01,0xFF,0xFF,0xFF,0xFF,0xE1, +0x40,0x7F,0xC0,0x00,0x00,0x00,0x01,0xFF,0x80,0x00, +0x00,0x00,0xA0,0x7F,0xC0,0x00,0x00,0x00,0x01,0xFF, +0x80,0x00,0x00,0x00,0x50,0x7F,0xC0,0x00,0x00,0x00, +0x00,0xFF,0x80,0x7F,0x80,0x00,0x03,0xFF,0x0F,0xFF, +0xF0,0x00,0x07,0xFC,0x7F,0xFF,0xF8,0x00,0x0F,0xF9, +0xFF,0xFF,0xF8,0x00,0x1F,0xFF,0xFF,0xFF,0xFC,0x00, +0x3F,0xFF,0xFF,0xFF,0xFC,0x00,0xFF,0xFF,0xFF,0xFF, +0xFC,0x01,0xFF,0xFF,0xFF,0xFF,0xFC,0x03,0xFF,0xFC, +0x01,0xFF,0xF8,0x07,0xFF,0xE0,0x00,0x7F,0xF8,0x0F, +0xFF,0x00,0x00,0x7F,0xF8,0x3F,0xFC,0x00,0x00,0x3F, +0xF0,0x7F,0xF0,0x00,0x00,0x3F,0xF0,0xFF,0xC0,0x00, +0x00,0x7F,0xE0,0x1F,0x00,0x00,0x00,0x7F,0xE0,0x00, +0x00,0x00,0x00,0xFF,0xD0,0x00,0x00,0x00,0x00,0x1F, +0xF0,0x00,0x00,0x00,0x00,0x3F,0xFD,0x00,0x00,0x00, +0x00,0x07,0xFE,0x00,0x00,0x00,0x00,0x01,0xFF,0x07, +0xC0,0x00,0x00,0x03,0xFF,0x1F,0xF0,0x00,0x00,0x01, +0xFF,0x3F,0xF0,0x00,0x00,0x03,0xFE,0x3F,0xE0,0x00, +0x00,0x0F,0xFC,0x7F,0xC0,0x00,0x00,0x1F,0xF0,0xFF, +0xC0,0x00,0x00,0x7F,0xE1,0xFF,0xC0,0x00,0x00,0xFF, +0x81,0xFF,0x80,0x00,0x03,0xFF,0x03,0xFF,0x80,0x00, +0x0F,0xFC,0x03,0xFF,0x80,0x00,0x3F,0xF8,0x07,0xFF, +0xC0,0x01,0xFF,0xE0,0x07,0xFF,0xE0,0x1F,0xFF,0x80, +0x07,0xFF,0xFF,0xFF,0xFE,0x00,0x07,0xFF,0xFF,0xFF, +0xFC,0x00,0x07,0xFF,0xFF,0xFF,0xF0,0x00,0x07,0xFF, +0xFF,0xFF,0x80,0x00,0x07,0xFF,0xFF,0xFE,0x00,0x00, +0x03,0xFF,0xFF,0xF0,0x00,0x00,0x01,0xFF,0xFF,0x80, +0x00,0x00,0x00,0x3F,0xF0,0x00,0x00,0x0C,0x24,0x8F, +0xFB,0x80,0x00,0x00,0x3F,0xF0,0x00,0x00,0x00,0x01, +0xFF,0xFF,0x80,0x00,0x00,0x03,0xFF,0xFF,0xF0,0x00, +0x00,0x07,0xFF,0xFF,0xFC,0x00,0x00,0x07,0xFF,0xFF, +0xFF,0x80,0x00,0x0F,0xFF,0xFF,0xFF,0xE0,0x00,0x0F, +0xFF,0xFF,0xFF,0xF8,0x00,0x0F,0xFF,0xFF,0xFF,0xFE, +0x00,0x07,0xFF,0xE0,0x3F,0xFF,0x00,0x07,0xFF,0x80, +0x03,0xFF,0xC0,0x07,0xFF,0x00,0x00,0xFF,0xE0,0x07, +0xFF,0x00,0x00,0x3F,0xF8,0x03,0xFF,0x00,0x00,0x0F, +0xFC,0x40,0x7F,0xE0,0x00,0x00,0x7F,0xE0,0x3F,0xE0, +0x00,0x00,0x1F,0xF0,0x3F,0xF0,0x00,0x00,0x0F,0xFC, +0x1F,0xF0,0x00,0x00,0x07,0xFE,0x1F,0xF8,0x00,0x00, +0x01,0xFF,0x0F,0xF8,0x00,0x00,0x00,0xF8,0x07,0xFC, +0x00,0x00,0x00,0x00,0x03,0xFC,0x00,0x00,0x00,0x00, +0x09,0x7F,0xC0,0x00,0x00,0x00,0x00,0x3F,0xE0,0x01, +0xFF,0x00,0x00,0x1F,0xE0,0x07,0xFF,0xF0,0x00,0x0F, +0xF0,0x0F,0xFF,0xFF,0x00,0x0F,0xF8,0x1F,0xFF,0xFF, +0xC0,0x07,0xFC,0x1F,0xFF,0xFF,0xF8,0x03,0xFE,0x3F, +0xFF,0xFF,0xFE,0x01,0xFF,0x3F,0xFF,0xFF,0xFF,0x80, +0xFF,0xBF,0xFF,0xFF,0xFF,0xE0,0x7F,0xDF,0xF8,0x07, +0xFF,0xF0,0x3F,0xFF,0xE0,0x00,0x7F,0xFC,0x1F,0xFF, +0xE0,0x00,0x0F,0xFF,0x0F,0xFF,0xC0,0x00,0x03,0xFF, +0x87,0xFF,0xC0,0x00,0x00,0xFF,0xE3,0xFF,0xC0,0x00, +0x00,0x3F,0xF2,0x3F,0xF8,0x00,0x00,0x01,0xFF,0xA3, +0xFF,0x00,0x00,0x00,0x0F,0xF9,0xFF,0x80,0x00,0x00, +0x07,0xFF,0x3F,0xF0,0x00,0x00,0x00,0x3F,0xF8,0xFF, +0x00,0x00,0x00,0x03,0xFE,0x3F,0xC0,0x00,0x00,0x03, +0xFF,0x83,0xFC,0x00,0x00,0x00,0x3F,0xE1,0xFF,0x00, +0x00,0x00,0x1F,0xF0,0x7F,0x80,0x00,0x00,0x1F,0xF8, +0x3F,0xE0,0x00,0x00,0x0F,0xF8,0x0F,0xF8,0x00,0x00, +0x0F,0xFC,0x07,0xFE,0x00,0x00,0x0F,0xFC,0x01,0xFF, +0x80,0x00,0x0F,0xFE,0x00,0xFF,0xE0,0x00,0x0F,0xFE, +0x00,0x3F,0xFC,0x00,0x1F,0xFF,0x00,0x0F,0xFF,0x80, +0x3F,0xFF,0x00,0x03,0xFF,0xFF,0xFF,0xFF,0x00,0x01, +0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x3F,0xFF,0xFF,0xFF, +0x00,0x00,0x0F,0xFF,0xFF,0xFF,0x00,0x00,0x03,0xFF, +0xFF,0xFF,0x00,0x00,0x00,0x7F,0xFF,0xFE,0x00,0x00, +0x00,0x0F,0xFF,0xFC,0x00,0x00,0x00,0x00,0x7F,0xE0, +0x00,0x00,0x0B,0xE3,0x90,0x03,0x8D,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x00,0x00,0x03, +0xF8,0x00,0x00,0x00,0x00,0x07,0xF0,0x00,0x00,0x00, +0x00,0x0F,0xE0,0x00,0x00,0x00,0x00,0x1F,0xE0,0x00, +0x00,0x00,0x00,0x3F,0xC0,0x00,0x00,0x00,0x00,0x7F, +0x81,0x00,0x00,0x00,0x00,0x1F,0xE0,0x00,0x00,0x00, +0x00,0x3F,0xC0,0x20,0x00,0x00,0x00,0x0F,0xF0,0x00, +0x00,0x00,0x00,0x1F,0xE0,0x00,0x00,0x00,0x00,0x3F, +0xE0,0x00,0x00,0x00,0x00,0x3F,0xC0,0x00,0x00,0x00, +0x00,0x7F,0x80,0x00,0x00,0x00,0x00,0xFF,0x80,0x00, +0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x01,0xFF, +0x00,0x04,0x00,0x00,0x00,0x7F,0xC0,0x00,0x80,0x00, +0x00,0x1F,0xF0,0x00,0x10,0x00,0x00,0x07,0xFC,0x00, +0x02,0x00,0x00,0x01,0xFF,0x00,0x00,0x40,0x00,0x00, +0x7F,0xC0,0x00,0x08,0x00,0x00,0x1F,0xF0,0x00,0x01, +0x20,0x00,0x07,0xFC,0x00,0x00,0x24,0x00,0x01,0xFF, +0x00,0x00,0x04,0x80,0x00,0x7F,0xC0,0x00,0x00,0x90, +0x00,0x1F,0xF0,0x00,0x00,0x12,0x00,0x07,0xFC,0x00, +0x00,0x00,0x00,0x07,0xF8,0x00,0x00,0x02,0x80,0x01, +0xFF,0x00,0x00,0x00,0x58,0x00,0x7F,0xC0,0x00,0x00, +0x08,0x00,0x1F,0xF8,0x00,0x00,0x01,0x60,0x03,0xFE, +0x00,0x00,0x00,0x00,0x0B,0xA4,0x97,0xFB,0x80,0x00, +0x01,0xFF,0x80,0x00,0x00,0x00,0x3F,0xFF,0xF0,0x00, +0x00,0x01,0xFF,0xFF,0xF8,0x00,0x00,0x0F,0xFF,0xFF, +0xFC,0x00,0x00,0x3F,0xFF,0xFF,0xFC,0x00,0x01,0xFF, +0xFF,0xFF,0xFC,0x00,0x07,0xFF,0xFF,0xFF,0xFC,0x00, +0x0F,0xFF,0xFF,0xFF,0xFC,0x00,0x3F,0xFF,0x00,0xFF, +0xFC,0x00,0xFF,0xF0,0x00,0x3F,0xFC,0x01,0xFF,0xC0, +0x00,0x3F,0xF8,0x07,0xFF,0x00,0x00,0x3F,0xF8,0x0F, +0xFC,0x00,0x00,0x3F,0xF0,0x1F,0xF0,0x00,0x00,0x3F, +0xE0,0x7F,0xE0,0x00,0x00,0x7F,0xE6,0x9F,0xF0,0x00, +0x00,0x0F,0xF8,0x3F,0xF0,0x00,0x00,0x3F,0xF0,0x3F, +0xE0,0x00,0x00,0x7F,0xC0,0x7F,0xE0,0x00,0x01,0xFF, +0x80,0x7F,0xE0,0x00,0x07,0xFE,0x00,0xFF,0xE0,0x00, +0x1F,0xFC,0x00,0xFF,0xE0,0x00,0x7F,0xF0,0x00,0xFF, +0xF8,0x07,0xFF,0xC0,0x00,0xFF,0xFF,0xFF,0xFF,0x00, +0x00,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x7F,0xFF,0xFF, +0xE0,0x00,0x00,0x3F,0xFF,0xFF,0x00,0x00,0x00,0xFF, +0xFF,0xFF,0x00,0x00,0x07,0xFF,0xFF,0xFF,0x80,0x00, +0x3F,0xFF,0xFF,0xFF,0xC0,0x00,0xFF,0xFF,0xFF,0xFF, +0xC0,0x03,0xFF,0xF0,0x0F,0xFF,0xC0,0x0F,0xFF,0x00, +0x03,0xFF,0xC0,0x3F,0xF8,0x00,0x03,0xFF,0xC0,0xFF, +0xE0,0x00,0x01,0xFF,0x81,0xFF,0x80,0x00,0x01,0xFF, +0x87,0xFE,0x00,0x00,0x03,0xFF,0x0F,0xFC,0x00,0x00, +0x03,0xFF,0x43,0xFE,0x00,0x00,0x00,0x7F,0xCF,0xFC, +0x00,0x00,0x00,0xFF,0xF7,0xFE,0x00,0x00,0x00,0x1F, +0xF7,0xFC,0x00,0x00,0x00,0x3F,0xEF,0xFC,0x00,0x00, +0x00,0xFF,0xE1,0xFF,0x00,0x00,0x00,0x3F,0xE3,0xFF, +0x00,0x00,0x00,0xFF,0xC3,0xFE,0x00,0x00,0x01,0xFF, +0x07,0xFE,0x00,0x00,0x07,0xFE,0x0F,0xFE,0x00,0x00, +0x1F,0xFC,0x0F,0xFE,0x00,0x00,0x7F,0xF0,0x0F,0xFF, +0x00,0x03,0xFF,0xC0,0x1F,0xFF,0xC0,0x3F,0xFF,0x80, +0x1F,0xFF,0xFF,0xFF,0xFE,0x00,0x1F,0xFF,0xFF,0xFF, +0xF8,0x00,0x1F,0xFF,0xFF,0xFF,0xE0,0x00,0x1F,0xFF, +0xFF,0xFF,0x80,0x00,0x0F,0xFF,0xFF,0xFC,0x00,0x00, +0x0F,0xFF,0xFF,0xE0,0x00,0x00,0x03,0xFF,0xFF,0x00, +0x00,0x00,0x00,0x7F,0xE0,0x00,0x00,0x0B,0xA4,0x97, +0xFB,0x80,0x00,0x03,0xFF,0x00,0x00,0x00,0x00,0x3F, +0xFF,0xC0,0x00,0x00,0x01,0xFF,0xFF,0xE0,0x00,0x00, +0x0F,0xFF,0xFF,0xF0,0x00,0x00,0x3F,0xFF,0xFF,0xF0, +0x00,0x01,0xFF,0xFF,0xFF,0xF8,0x00,0x07,0xFF,0xFF, +0xFF,0xF8,0x00,0x0F,0xFF,0xFF,0xFF,0xF8,0x00,0x3F, +0xFF,0x80,0xFF,0xF8,0x00,0xFF,0xF8,0x00,0x3F,0xF0, +0x03,0xFF,0xC0,0x00,0x3F,0xF0,0x07,0xFF,0x00,0x00, +0x3F,0xF0,0x1F,0xFC,0x00,0x00,0x3F,0xE0,0x3F,0xF0, +0x00,0x00,0x3F,0xE0,0x7F,0xE0,0x00,0x00,0x3F,0xC1, +0xFF,0x80,0x00,0x00,0x7F,0x83,0xFF,0x00,0x00,0x00, +0x7F,0x87,0xFC,0x00,0x00,0x00,0xFF,0x1F,0xF8,0x00, +0x00,0x01,0xFE,0x3F,0xF0,0x00,0x00,0x01,0xFE,0xBF, +0xF8,0x00,0x00,0x00,0x7F,0xAB,0xFE,0x00,0x00,0x00, +0x1F,0xF7,0xFC,0x00,0x00,0x00,0x7F,0xF0,0xFF,0x80, +0x00,0x00,0x1F,0xFC,0x3F,0xF0,0x00,0x00,0x0F,0xFE, +0x3F,0xF0,0x00,0x00,0x3F,0xFC,0x7F,0xF0,0x00,0x00, +0xFF,0xF8,0xFF,0xE0,0x00,0x03,0xFF,0xF0,0xFF,0xF0, +0x00,0x0F,0xFF,0xE0,0xFF,0xF0,0x00,0x3F,0xFF,0xC1, +0xFF,0xFC,0x03,0xFE,0xFF,0x81,0xFF,0xFF,0xFF,0xFD, +0xFF,0x01,0xFF,0xFF,0xFF,0xF3,0xFE,0x01,0xFF,0xFF, +0xFF,0xC7,0xFC,0x01,0xFF,0xFF,0xFF,0x0F,0xF8,0x01, +0xFF,0xFF,0xF8,0x1F,0xF0,0x00,0xFF,0xFF,0xE0,0x3F, +0xC0,0x00,0x7F,0xFF,0x00,0x7F,0x80,0x00,0x1F,0xF0, +0x01,0xFF,0x48,0x00,0x00,0x00,0x00,0x7F,0xC0,0x00, +0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x03,0xFE, +0x01,0xF0,0x00,0x00,0x07,0xFC,0x3F,0xE0,0x00,0x00, +0x0F,0xF8,0x7F,0xC0,0x00,0x00,0x3F,0xE0,0xFF,0xC0, +0x00,0x00,0x7F,0xC0,0xFF,0x80,0x00,0x01,0xFF,0x81, +0xFF,0x00,0x00,0x03,0xFE,0x03,0xFF,0x00,0x00,0x0F, +0xFC,0x07,0xFF,0x00,0x00,0x1F,0xF0,0x07,0xFE,0x00, +0x00,0x7F,0xE0,0x0F,0xFE,0x00,0x03,0xFF,0x80,0x0F, +0xFF,0x00,0x0F,0xFE,0x00,0x1F,0xFF,0x80,0xFF,0xFC, +0x00,0x1F,0xFF,0xFF,0xFF,0xF0,0x00,0x1F,0xFF,0xFF, +0xFF,0xC0,0x00,0x1F,0xFF,0xFF,0xFF,0x00,0x00,0x1F, +0xFF,0xFF,0xFC,0x00,0x00,0x1F,0xFF,0xFF,0xE0,0x00, +0x00,0x0F,0xFF,0xFF,0x80,0x00,0x00,0x07,0xFF,0xF8, +0x00,0x00,0x00,0x01,0xFF,0x80,0x00,0x00,0x02,0x5A, +0x24,0x01,0xCD,0xFF,0xC7,0xFF,0x40,0x1A,0x00,0xD0, +0x06,0x80,0x30,0x01,0xBF,0xF8,0xFF,0x80,0x02,0x61, +0xA7,0x89,0xCD,0xFF,0xC7,0xFF,0x40,0x1A,0x00,0xD0, +0x06,0x80,0x30,0x01,0xBF,0xF8,0xFF,0xE0,0x7C,0x1E, +0x81,0xF0,0xF8,0x7E,0x3F,0x07,0x81,0xC0,0x20,0x00, +0x0B,0x97,0x98,0x63,0xA0,0x00,0x00,0x00,0x00,0x00, +0x20,0x00,0x00,0x00,0x00,0x01,0xC0,0x00,0x00,0x00, +0x00,0x1F,0x80,0x00,0x00,0x00,0x00,0xFF,0x00,0x00, +0x00,0x00,0x07,0xFE,0x00,0x00,0x00,0x00,0x7F,0xFC, +0x00,0x00,0x00,0x03,0xFF,0xF8,0x00,0x00,0x00,0x1F, +0xFF,0xF0,0x00,0x00,0x01,0xFF,0xFF,0xE0,0x00,0x00, +0x0F,0xFF,0xFF,0x80,0x00,0x00,0x7F,0xFF,0xF8,0x00, +0x00,0x03,0xFF,0xFF,0xC0,0x00,0x00,0x3F,0xFF,0xFC, +0x00,0x00,0x01,0xFF,0xFF,0xE0,0x00,0x00,0x0F,0xFF, +0xFE,0x00,0x00,0x00,0xFF,0xFF,0xE0,0x00,0x00,0x07, +0xFF,0xFF,0x00,0x00,0x00,0x3F,0xFF,0xF0,0x00,0x00, +0x03,0xFF,0xFF,0x80,0x00,0x00,0x1F,0xFF,0xF8,0x00, +0x00,0x00,0x7F,0xFF,0xC0,0x00,0x00,0x00,0xFF,0xFC, +0x00,0x00,0x00,0x01,0xFF,0xE0,0x00,0x00,0x00,0x03, +0xFE,0x00,0x00,0x00,0x00,0x07,0xFF,0x80,0x00,0x00, +0x00,0x0F,0xFF,0xC0,0x00,0x00,0x00,0x1F,0xFF,0xF0, +0x00,0x00,0x00,0x1F,0xFF,0xF8,0x00,0x00,0x00,0x0F, +0xFF,0xFE,0x00,0x00,0x00,0x03,0xFF,0xFF,0x00,0x00, +0x00,0x01,0xFF,0xFF,0xC0,0x00,0x00,0x00,0xFF,0xFF, +0xE0,0x00,0x00,0x00,0x3F,0xFF,0xF8,0x00,0x00,0x00, +0x1F,0xFF,0xFE,0x00,0x00,0x00,0x0F,0xFF,0xFF,0x00, +0x00,0x00,0x03,0xFF,0xFF,0xC0,0x00,0x00,0x01,0xFF, +0xFF,0xE0,0x00,0x00,0x00,0xFF,0xFF,0xF8,0x00,0x00, +0x00,0x7F,0xFF,0xF8,0x00,0x00,0x00,0x1F,0xFF,0xF0, +0x00,0x00,0x00,0x0F,0xFF,0xE0,0x00,0x00,0x00,0x07, +0xFF,0xC0,0x00,0x00,0x00,0x01,0xFF,0x80,0x00,0x00, +0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x7E,0x00, +0x00,0x00,0x00,0x00,0x1C,0x00,0x00,0x00,0x00,0x00, +0x08,0x0B,0xCF,0x14,0xA3,0xAD,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0xF4,0x00, +0x00,0x00,0x00,0x00,0x05,0x80,0x00,0x00,0x00,0x00, +0x00,0xDF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF1,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFC,0x0B,0x97,0x98,0x63,0xA4,0x00, +0x00,0x00,0x00,0x00,0x0E,0x00,0x00,0x00,0x00,0x00, +0x1F,0x80,0x00,0x00,0x00,0x00,0x3F,0xC0,0x00,0x00, +0x00,0x00,0x7F,0xE0,0x00,0x00,0x00,0x00,0xFF,0xF8, +0x00,0x00,0x00,0x01,0xFF,0xFC,0x00,0x00,0x00,0x03, +0xFF,0xFE,0x00,0x00,0x00,0x07,0xFF,0xFF,0x80,0x00, +0x00,0x07,0xFF,0xFF,0xC0,0x00,0x00,0x01,0xFF,0xFF, +0xE0,0x00,0x00,0x00,0xFF,0xFF,0xF0,0x00,0x00,0x00, +0x3F,0xFF,0xFC,0x00,0x00,0x00,0x1F,0xFF,0xFE,0x00, +0x00,0x00,0x07,0xFF,0xFF,0x00,0x00,0x00,0x01,0xFF, +0xFF,0xC0,0x00,0x00,0x00,0xFF,0xFF,0xE0,0x00,0x00, +0x00,0x3F,0xFF,0xF0,0x00,0x00,0x00,0x1F,0xFF,0xFC, +0x00,0x00,0x00,0x07,0xFF,0xFE,0x00,0x00,0x00,0x03, +0xFF,0xFE,0x00,0x00,0x00,0x00,0xFF,0xFC,0x00,0x00, +0x00,0x00,0x7F,0xF8,0x00,0x00,0x00,0x00,0x1F,0xF0, +0x00,0x00,0x00,0x01,0xFF,0xE0,0x00,0x00,0x00,0x0F, +0xFF,0xC0,0x00,0x00,0x00,0xFF,0xFF,0x80,0x00,0x00, +0x07,0xFF,0xFE,0x00,0x00,0x00,0x7F,0xFF,0xF0,0x00, +0x00,0x03,0xFF,0xFF,0x00,0x00,0x00,0x3F,0xFF,0xF8, +0x00,0x00,0x01,0xFF,0xFF,0xC0,0x00,0x00,0x1F,0xFF, +0xFC,0x00,0x00,0x01,0xFF,0xFF,0xE0,0x00,0x00,0x0F, +0xFF,0xFF,0x00,0x00,0x00,0xFF,0xFF,0xF0,0x00,0x00, +0x07,0xFF,0xFF,0x80,0x00,0x00,0x7F,0xFF,0xFC,0x00, +0x00,0x01,0xFF,0xFF,0xE0,0x00,0x00,0x03,0xFF,0xFE, +0x00,0x00,0x00,0x07,0xFF,0xF0,0x00,0x00,0x00,0x0F, +0xFF,0x80,0x00,0x00,0x00,0x1F,0xF8,0x00,0x00,0x00, +0x00,0x3F,0xC0,0x00,0x00,0x00,0x00,0x7E,0x00,0x00, +0x00,0x00,0x00,0xE0,0x00,0x00,0x00,0x00,0x01,0x00, +0x00,0x00,0x00,0x00,0x00,0x0B,0xA4,0x94,0x03,0x80, +0x00,0x01,0xFF,0xC0,0x00,0x00,0x00,0x3F,0xFF,0xF8, +0x00,0x00,0x01,0xFF,0xFF,0xFC,0x00,0x00,0x0F,0xFF, +0xFF,0xFE,0x00,0x00,0x7F,0xFF,0xFF,0xFE,0x00,0x01, +0xFF,0xFF,0xFF,0xFE,0x00,0x07,0xFF,0xFF,0xFF,0xFE, +0x00,0x1F,0xFF,0xFF,0xFF,0xFE,0x00,0x7F,0xFF,0x00, +0xFF,0xFE,0x00,0xFF,0xF8,0x00,0x3F,0xFE,0x03,0xFF, +0xC0,0x00,0x3F,0xFC,0x07,0xFF,0x00,0x00,0x1F,0xFC, +0x1F,0xFC,0x00,0x00,0x1F,0xFC,0x3F,0xF0,0x00,0x00, +0x3F,0xF8,0xFF,0xC0,0x00,0x00,0x3F,0xF1,0xFF,0x80, +0x00,0x00,0x3F,0xE3,0xFE,0x00,0x00,0x00,0x7F,0xE7, +0xFC,0x00,0x00,0x00,0x7F,0xE3,0xFF,0x00,0x00,0x00, +0x1F,0xF7,0xFC,0x00,0x00,0x00,0x3F,0xE0,0xF8,0x00, +0x00,0x00,0x7F,0xE0,0x00,0x00,0x00,0x00,0x1F,0xF8, +0x00,0x00,0x00,0x00,0x0F,0xF8,0x00,0x00,0x00,0x00, +0x3F,0xF0,0x00,0x00,0x00,0x00,0xFF,0xC0,0x00,0x00, +0x00,0x03,0xFF,0x80,0x00,0x00,0x00,0x0F,0xFE,0x00, +0x00,0x00,0x00,0x3F,0xFC,0x00,0x00,0x00,0x00,0xFF, +0xF0,0x00,0x00,0x00,0x03,0xFF,0xC0,0x00,0x00,0x00, +0x0F,0xFF,0x00,0x00,0x00,0x00,0x3F,0xFC,0x00,0x00, +0x00,0x00,0xFF,0xF0,0x00,0x00,0x00,0x03,0xFF,0xC0, +0x00,0x00,0x00,0x0F,0xFF,0x00,0x00,0x00,0x00,0x3F, +0xFC,0x00,0x00,0x00,0x00,0xFF,0xF0,0x00,0x00,0x00, +0x03,0xFF,0xC0,0x00,0x00,0x00,0x0F,0xFF,0x00,0x00, +0x00,0x00,0x1F,0xFC,0x00,0x00,0x00,0x00,0x7F,0xF0, +0x00,0x00,0x00,0x00,0xFF,0xC0,0x00,0x10,0x00,0x00, +0x7F,0xE0,0x00,0x00,0x00,0x00,0xFF,0x80,0x00,0x08, +0x00,0x00,0x7F,0xE0,0x00,0x03,0x40,0x00,0x1F,0xF0, +0x00,0x00,0xD0,0x00,0x00,0x00,0x00,0x00,0x34,0x00, +0x01,0xFF,0x00,0x00,0x08,0x00,0x00,0x7F,0xC0,0x00, +0x00,0x17,0x2F,0x17,0x5E,0x60,0x00,0x00,0x00,0x00, +0x07,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x07,0xFF,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x03,0xFF,0xFF,0xFF,0xFE,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFE,0x00, +0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xFF, +0xFC,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xFF,0xFF, +0xFF,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF, +0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x00,0x00,0x07, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x00, +0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x00, +0x00,0x00,0x0F,0xFF,0xFF,0xE0,0x00,0x7F,0xFF,0xFE, +0x00,0x00,0x00,0x00,0xFF,0xFF,0xE0,0x00,0x00,0x3F, +0xFF,0xF8,0x00,0x00,0x00,0x0F,0xFF,0xF8,0x00,0x00, +0x00,0x1F,0xFF,0xE0,0x00,0x00,0x00,0xFF,0xFE,0x00, +0x00,0x00,0x00,0x3F,0xFF,0x80,0x00,0x00,0x0F,0xFF, +0xC0,0x00,0x00,0x00,0x00,0x7F,0xFE,0x00,0x00,0x00, +0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0xFF,0xF8,0x00, +0x00,0x0F,0xFF,0x80,0x00,0x00,0x00,0x00,0x01,0xFF, +0xC0,0x00,0x00,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00, +0x07,0xFF,0x00,0x00,0x07,0xFF,0x00,0x00,0x00,0x00, +0x00,0x00,0x1F,0xFC,0x00,0x00,0x7F,0xF0,0x00,0x00, +0x00,0x00,0x00,0x00,0x7F,0xF0,0x00,0x07,0xFE,0x00, +0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0x80,0x00,0x3F, +0xE0,0x00,0x00,0x7F,0x00,0x00,0x00,0x07,0xFE,0x00, +0x03,0xFE,0x00,0x00,0x1F,0xFF,0x00,0x3F,0xE0,0x1F, +0xF0,0x00,0x3F,0xF0,0x00,0x03,0xFF,0xFE,0x01,0xFF, +0x00,0x7F,0xC0,0x01,0xFF,0x00,0x00,0x7F,0xFF,0xF8, +0x1F,0xF0,0x01,0xFE,0x00,0x1F,0xF0,0x00,0x07,0xFF, +0xFF,0xE0,0xFF,0x80,0x0F,0xF8,0x00,0xFF,0x00,0x00, +0xFF,0xFF,0xFF,0x87,0xFC,0x00,0x3F,0xC0,0x0F,0xF8, +0x00,0x0F,0xFF,0xFF,0xFE,0x3F,0xE0,0x01,0xFE,0x00, +0x7F,0x80,0x00,0xFF,0xFF,0xFF,0xFB,0xFF,0x00,0x07, +0xF8,0x07,0xF8,0x00,0x0F,0xFF,0xFF,0xFF,0xFF,0xF0, +0x00,0x3F,0xC0,0x3F,0xC0,0x00,0x7F,0xFE,0x07,0xFF, +0xFF,0x80,0x01,0xFE,0x01,0xFC,0x00,0x07,0xFF,0x80, +0x07,0xFF,0xFC,0x00,0x07,0xF0,0x1F,0xE0,0x00,0x7F, +0xF8,0x00,0x1F,0xFF,0xE0,0x00,0x3F,0x80,0xFE,0x00, +0x03,0xFF,0x80,0x00,0x7F,0xFE,0x00,0x01,0xFE,0x0F, +0xF0,0x00,0x3F,0xF8,0x00,0x01,0xFF,0xF0,0x00,0x07, +0xF0,0x7F,0x80,0x03,0xFF,0x80,0x00,0x0F,0xFF,0x80, +0x00,0x3F,0x83,0xF8,0x00,0x1F,0xF8,0x00,0x00,0x3F, +0xFC,0x00,0x01,0xFC,0x1F,0xC0,0x01,0xFF,0x80,0x00, +0x01,0xFF,0xC0,0x00,0x0F,0xE1,0xFE,0x00,0x0F,0xFC, +0x00,0x00,0x07,0xFE,0x00,0x00,0x7F,0x0F,0xE0,0x00, +0x7F,0xC0,0x00,0x00,0x3F,0xF0,0x00,0x03,0xF8,0x7F, +0x00,0x07,0xFE,0x00,0x00,0x01,0xFF,0x80,0x00,0x1F, +0xC3,0xF8,0x00,0x3F,0xE0,0x00,0x00,0x0F,0xFC,0x00, +0x00,0xFE,0x1F,0xC0,0x03,0xFF,0x00,0x00,0x00,0x7F, +0xC0,0x00,0x07,0xF1,0xFE,0x00,0x1F,0xF8,0x00,0x00, +0x03,0xFE,0x00,0x00,0x3F,0x8F,0xE0,0x00,0xFF,0x80, +0x00,0x00,0x1F,0xF0,0x00,0x03,0xFC,0x7F,0x00,0x07, +0xFC,0x00,0x00,0x00,0xFF,0x80,0x00,0x1F,0xC3,0xF8, +0x00,0x7F,0xE0,0x00,0x00,0x07,0xF8,0x00,0x00,0xFE, +0x1F,0xC0,0x03,0xFF,0x00,0x00,0x00,0x7F,0xC0,0x00, +0x07,0xF1,0x1F,0xC0,0x03,0xFE,0x00,0x00,0x00,0x7F, +0xC0,0x00,0x0F,0xF0,0xFE,0x00,0x1F,0xF0,0x00,0x00, +0x03,0xFC,0x00,0x00,0xFF,0x07,0xF0,0x00,0xFF,0x80, +0x00,0x00,0x3F,0xE0,0x00,0x07,0xF8,0x47,0xF0,0x00, +0xFF,0x80,0x00,0x00,0x3F,0xE0,0x00,0x0F,0xF0,0x3F, +0x80,0x07,0xFC,0x00,0x00,0x03,0xFF,0x00,0x00,0xFF, +0x81,0xFC,0x00,0x3F,0xE0,0x00,0x00,0x1F,0xF0,0x00, +0x07,0xF8,0x0F,0xE0,0x01,0xFF,0x00,0x00,0x01,0xFF, +0x80,0x00,0x7F,0xC0,0x7F,0x80,0x0F,0xFC,0x00,0x00, +0x1F,0xFC,0x00,0x07,0xFC,0x01,0xFC,0x00,0x3F,0xE0, +0x00,0x00,0xFF,0xE0,0x00,0x7F,0xC0,0x0F,0xE0,0x01, +0xFF,0x80,0x00,0x0F,0xFE,0x00,0x07,0xFE,0x00,0x7F, +0x00,0x0F,0xFC,0x00,0x00,0xFF,0xF0,0x00,0x7F,0xE0, +0x03,0xF8,0x00,0x3F,0xF0,0x00,0x0F,0xFF,0x80,0x07, +0xFE,0x00,0x1F,0xE0,0x01,0xFF,0xC0,0x01,0xFF,0xFC, +0x00,0xFF,0xE0,0x00,0xFF,0x00,0x0F,0xFF,0x00,0x3F, +0xFF,0xF0,0x1F,0xFF,0x00,0x03,0xF8,0x00,0x3F,0xFE, +0x07,0xFF,0xFF,0xC3,0xFF,0xF0,0x00,0x1F,0xE0,0x01, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0xFF, +0x00,0x07,0xFF,0xFF,0xFF,0x7F,0xFF,0xFF,0xF0,0x00, +0x03,0xFC,0x00,0x1F,0xFF,0xFF,0xFB,0xFF,0xFF,0xFF, +0x00,0x00,0x1F,0xE0,0x00,0x7F,0xFF,0xFF,0x9F,0xFF, +0xFF,0xE0,0x00,0x00,0xFF,0x80,0x03,0xFF,0xFF,0xF0, +0x7F,0xFF,0xFE,0x00,0x00,0x03,0xFE,0x00,0x07,0xFF, +0xFF,0x03,0xFF,0xFF,0xE0,0x00,0x00,0x1F,0xF0,0x00, +0x1F,0xFF,0xF0,0x0F,0xFF,0xFC,0x00,0x00,0x00,0x7F, +0xC0,0x00,0x3F,0xFE,0x00,0x3F,0xFF,0x80,0x01,0xFF, +0x03,0xFF,0x00,0x00,0x3F,0x80,0x00,0x7F,0xC0,0x00, +0x1F,0xF0,0x0F,0xFC,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x01,0xFF,0x80,0x7F,0xF0,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x1F,0xF8,0x01,0xFF,0xC0,0x00,0x00, +0x00,0x00,0x00,0x00,0x01,0xFF,0x80,0x07,0xFF,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFC,0x00,0x1F, +0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xC0, +0x00,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x3F, +0xFC,0x00,0x03,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00, +0x07,0xFF,0xC0,0x00,0x0F,0xFF,0xE0,0x00,0x00,0x00, +0x00,0x00,0xFF,0xFC,0x00,0x00,0x3F,0xFF,0xC0,0x00, +0x00,0x00,0x00,0x1F,0xFF,0xC0,0x00,0x00,0xFF,0xFF, +0xC0,0x00,0x00,0x00,0x07,0xFF,0xFC,0x00,0x00,0x03, +0xFF,0xFF,0xE0,0x00,0x00,0x01,0xFF,0xFF,0xC0,0x00, +0x00,0x07,0xFF,0xFF,0xFC,0x00,0x03,0xFF,0xFF,0xF8, +0x00,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0x80,0x00,0x00,0x00,0x3F,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xF8,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x01,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x00,0x00, +0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x00, +0x00,0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x00, +0x00,0x00,0x00,0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xE0, +0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xFF,0xFF, +0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F, +0xFF,0xF0,0x00,0x00,0x00,0x00,0x10,0xE4,0x7C,0x04, +0x30,0x00,0x00,0x00,0x7F,0xF0,0x00,0x00,0x00,0x90, +0x00,0x00,0x01,0xFF,0xF0,0x00,0x00,0x01,0x00,0x00, +0x00,0x07,0xFF,0xF0,0x00,0x00,0x02,0x00,0x00,0x00, +0x1F,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x01,0xFE, +0xFF,0x00,0x00,0x00,0x40,0x00,0x00,0x07,0xFD,0xFF, +0x00,0x00,0x00,0x80,0x00,0x00,0x1F,0xF1,0xFF,0x00, +0x00,0x00,0x00,0x00,0x01,0xFE,0x1F,0xF0,0x00,0x00, +0x10,0x00,0x00,0x07,0xFC,0x1F,0xF0,0x00,0x00,0x24, +0x00,0x00,0x1F,0xF0,0x1F,0xF0,0x00,0x00,0x40,0x00, +0x00,0x7F,0xC0,0x1F,0xF0,0x00,0x00,0x00,0x00,0x0F, +0xFC,0x01,0xFF,0x80,0x00,0x08,0x00,0x00,0x1F,0xF0, +0x01,0xFF,0x00,0x00,0x10,0x00,0x00,0x7F,0xC0,0x01, +0xFF,0x00,0x00,0x00,0x00,0x0F,0xFC,0x00,0x1F,0xF8, +0x00,0x02,0x00,0x00,0x1F,0xF0,0x00,0x1F,0xF0,0x00, +0x00,0x00,0x03,0xFF,0x00,0x01,0xFF,0x80,0x00,0x00, +0x00,0x3F,0xE0,0x00,0x0F,0xF8,0x00,0x04,0x00,0x00, +0xFF,0xC0,0x00,0x1F,0xF8,0x00,0x00,0x00,0x0F,0xF8, +0x00,0x00,0xFF,0x80,0x00,0x00,0x01,0xFF,0x80,0x00, +0x0F,0xFC,0x00,0x00,0x00,0x1F,0xF0,0x00,0x00,0x7F, +0xC0,0x00,0x80,0x00,0x7F,0xE0,0x00,0x00,0xFF,0xC0, +0x00,0x00,0x07,0xFC,0x00,0x00,0x07,0xFC,0x00,0x10, +0x00,0x1F,0xF8,0x00,0x00,0x0F,0xFC,0x00,0x00,0x01, +0xFF,0x00,0x00,0x00,0x7F,0xC0,0x02,0x00,0x07,0xFF, +0xFF,0xFF,0xFF,0xFF,0xC0,0x04,0x80,0x1F,0xFF,0xFF, +0xFF,0xFF,0xFF,0xC0,0x08,0x00,0x7F,0xFF,0xFF,0xFF, +0xFF,0xFF,0xC0,0x00,0x0F,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFE,0x01,0x00,0x1F,0xF8,0x00,0x00,0x00,0x0F,0xFC, +0x02,0x00,0x7F,0xE0,0x00,0x00,0x00,0x0F,0xFC,0x04, +0x81,0xFF,0x80,0x00,0x00,0x00,0x0F,0xFC,0x08,0x07, +0xFE,0x00,0x00,0x00,0x00,0x0F,0xFC,0x00,0xFF,0xE0, +0x00,0x00,0x00,0x00,0xFF,0xE1,0x01,0xFF,0x80,0x00, +0x00,0x00,0x00,0xFF,0xC2,0x07,0xFE,0x00,0x00,0x00, +0x00,0x00,0xFF,0xC0,0xFF,0xE0,0x00,0x00,0x00,0x00, +0x0F,0xFE,0x41,0xFF,0x80,0x00,0x00,0x00,0x00,0x0F, +0xFC,0x3F,0xF8,0x00,0x00,0x00,0x00,0x00,0xFF,0xE3, +0xFF,0x00,0x00,0x00,0x00,0x00,0x07,0xFE,0x8F,0xFE, +0x00,0x00,0x00,0x00,0x00,0x0F,0xFE,0xFF,0xC0,0x00, +0x00,0x00,0x00,0x00,0x7F,0xE0,0x0D,0xA4,0x20,0x04, +0x37,0xFF,0xFF,0xFF,0xFE,0x00,0x00,0x0F,0xFF,0xFF, +0xFF,0xFF,0xC0,0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xF0, +0x00,0x3F,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x7F,0xFF, +0xFF,0xFF,0xFF,0xF8,0x00,0xFF,0xFF,0xFF,0xFF,0xFF, +0xF8,0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xF8,0x03,0xFF, +0xFF,0xFF,0xFF,0xFF,0xF8,0x07,0xFE,0x00,0x00,0x07, +0xFF,0xF8,0x0F,0xFC,0x00,0x00,0x00,0xFF,0xF0,0x1F, +0xF8,0x00,0x00,0x00,0xFF,0xF0,0x3F,0xF0,0x00,0x00, +0x00,0xFF,0xE0,0x7F,0xE0,0x00,0x00,0x00,0xFF,0xE1, +0x1F,0xF8,0x00,0x00,0x00,0x1F,0xF8,0x3F,0xF0,0x00, +0x00,0x00,0x3F,0xF8,0xDF,0xFC,0x00,0x00,0x00,0x07, +0xFE,0x23,0xFF,0x00,0x00,0x00,0x03,0xFF,0x07,0xFE, +0x00,0x00,0x00,0x07,0xFC,0x0F,0xFC,0x00,0x00,0x00, +0x1F,0xF8,0x1F,0xF8,0x00,0x00,0x00,0x7F,0xE0,0x3F, +0xF0,0x00,0x00,0x01,0xFF,0xC0,0x7F,0xE0,0x00,0x00, +0x0F,0xFF,0x00,0xFF,0xC0,0x00,0x00,0xFF,0xFC,0x01, +0xFF,0xFF,0xFF,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xFF, +0xFF,0xFF,0x80,0x07,0xFF,0xFF,0xFF,0xFF,0xFC,0x00, +0x0F,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x1F,0xFF,0xFF, +0xFF,0xFF,0xFE,0x00,0x3F,0xFF,0xFF,0xFF,0xFF,0xFF, +0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0x81,0xFF,0x80,0x00,0x00,0xFF, +0xFF,0x83,0xFF,0x00,0x00,0x00,0x1F,0xFF,0x07,0xFE, +0x00,0x00,0x00,0x0F,0xFF,0x0F,0xFC,0x00,0x00,0x00, +0x0F,0xFF,0x1F,0xF8,0x00,0x00,0x00,0x0F,0xFE,0x3F, +0xF0,0x00,0x00,0x00,0x0F,0xFE,0x8F,0xFC,0x00,0x00, +0x00,0x01,0xFF,0x9F,0xF8,0x00,0x00,0x00,0x03,0xFF, +0xEF,0xFE,0x00,0x00,0x00,0x00,0x7F,0xEF,0xFC,0x00, +0x00,0x00,0x01,0xFF,0xE3,0xFF,0x00,0x00,0x00,0x00, +0x7F,0xE7,0xFE,0x00,0x00,0x00,0x01,0xFF,0xD1,0xFF, +0x80,0x00,0x00,0x00,0xFF,0xE3,0xFF,0x00,0x00,0x00, +0x07,0xFF,0x87,0xFE,0x00,0x00,0x00,0x1F,0xFF,0x0F, +0xFC,0x00,0x00,0x03,0xFF,0xFC,0x23,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFE,0x07,0xFF,0xFF,0xFF,0xFF,0xFF,0xF8, +0x0F,0xFF,0xFF,0xFF,0xFF,0xFF,0xC0,0x1F,0xFF,0xFF, +0xFF,0xFF,0xFF,0x00,0x3F,0xFF,0xFF,0xFF,0xFF,0xF8, +0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0xFF,0xFF, +0xFF,0xFF,0xE0,0x00,0x00,0x0F,0xA5,0x17,0xFC,0x80, +0x00,0x00,0x00,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00, +0x3F,0xFF,0xFE,0x00,0x00,0x00,0x00,0x01,0xFF,0xFF, +0xFF,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0x80, +0x00,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xC0,0x00,0x00, +0x03,0xFF,0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x0F,0xFF, +0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x7F,0xFF,0xFF,0xFF, +0xFF,0xC0,0x00,0x01,0xFF,0xFF,0x00,0x3F,0xFF,0xC0, +0x00,0x07,0xFF,0xF0,0x00,0x0F,0xFF,0xC0,0x00,0x1F, +0xFF,0x80,0x00,0x07,0xFF,0xC0,0x00,0x3F,0xFC,0x00, +0x00,0x07,0xFF,0xC0,0x00,0xFF,0xF0,0x00,0x00,0x07, +0xFF,0x80,0x03,0xFF,0xC0,0x00,0x00,0x07,0xFF,0x80, +0x0F,0xFF,0x00,0x00,0x00,0x07,0xFF,0x80,0x1F,0xFC, +0x00,0x00,0x00,0x07,0xFF,0x00,0x7F,0xF0,0x00,0x00, +0x00,0x0F,0xFE,0x00,0xFF,0xC0,0x00,0x00,0x00,0x0F, +0xFE,0x03,0xFF,0x80,0x00,0x00,0x00,0x1F,0xFC,0x40, +0xFF,0xC0,0x00,0x00,0x00,0x03,0xFF,0x83,0xFF,0x00, +0x00,0x00,0x00,0x03,0xF8,0x07,0xFE,0x00,0x00,0x00, +0x00,0x06,0x00,0x0F,0xFC,0x00,0x00,0x00,0x00,0x00, +0x00,0x3F,0xF8,0x00,0x00,0x00,0x00,0x00,0x01,0x4F, +0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xF8,0x00, +0x00,0x00,0x00,0x00,0x00,0xDF,0xFC,0x00,0x00,0x00, +0x00,0x00,0x00,0x37,0xFF,0x00,0x00,0x00,0x00,0x00, +0x00,0x0A,0x7F,0xE0,0x00,0x00,0x00,0x00,0x00,0x00, +0xFF,0xC0,0x00,0x00,0x00,0x00,0x1C,0x00,0xFF,0xC0, +0x00,0x00,0x00,0x00,0x3F,0x88,0x3F,0xF0,0x00,0x00, +0x00,0x00,0x1F,0xFC,0x7F,0xF0,0x00,0x00,0x00,0x00, +0x3F,0xF4,0x0F,0xFC,0x00,0x00,0x00,0x00,0x1F,0xFD, +0x01,0xFF,0x80,0x00,0x00,0x00,0x0F,0xFE,0x03,0xFF, +0x80,0x00,0x00,0x00,0x3F,0xF8,0x03,0xFF,0x80,0x00, +0x00,0x00,0x7F,0xF0,0x03,0xFF,0x80,0x00,0x00,0x01, +0xFF,0xC0,0x07,0xFF,0x80,0x00,0x00,0x07,0xFF,0x80, +0x07,0xFF,0x80,0x00,0x00,0x1F,0xFE,0x00,0x0F,0xFF, +0x80,0x00,0x00,0xFF,0xFC,0x00,0x0F,0xFF,0xC0,0x00, +0x03,0xFF,0xF0,0x00,0x0F,0xFF,0xE0,0x00,0x1F,0xFF, +0xC0,0x00,0x0F,0xFF,0xF8,0x01,0xFF,0xFF,0x00,0x00, +0x0F,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x0F,0xFF, +0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x0F,0xFF,0xFF,0xFF, +0xFF,0xC0,0x00,0x00,0x07,0xFF,0xFF,0xFF,0xFE,0x00, +0x00,0x00,0x07,0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x00, +0x01,0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x00,0x00,0xFF, +0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0x80, +0x00,0x00,0x0E,0xE4,0x20,0x04,0x87,0xFF,0xFF,0xFF, +0xFE,0x00,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0x00, +0x00,0x07,0xFF,0xFF,0xFF,0xFF,0xFE,0x00,0x00,0x7F, +0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x07,0xFF,0xFF,0xFF, +0xFF,0xFF,0xC0,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF, +0x00,0x07,0xFF,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x7F, +0xFF,0xFF,0xFF,0xFF,0xFF,0xC0,0x07,0xFE,0x00,0x00, +0x03,0xFF,0xFE,0x00,0x7F,0xE0,0x00,0x00,0x03,0xFF, +0xF0,0x07,0xFE,0x00,0x00,0x00,0x0F,0xFF,0x80,0x7F, +0xE0,0x00,0x00,0x00,0x7F,0xFC,0x07,0xFE,0x00,0x00, +0x00,0x03,0xFF,0xC0,0x7F,0xE0,0x00,0x00,0x00,0x1F, +0xFE,0x07,0xFE,0x00,0x00,0x00,0x00,0xFF,0xE0,0x7F, +0xE0,0x00,0x00,0x00,0x07,0xFF,0x07,0xFE,0x00,0x00, +0x00,0x00,0x3F,0xF0,0x7F,0xE0,0x00,0x00,0x00,0x03, +0xFF,0x87,0xFE,0x00,0x00,0x00,0x00,0x1F,0xF8,0x7F, +0xE0,0x00,0x00,0x00,0x01,0xFF,0xC9,0xFF,0xC0,0x00, +0x00,0x00,0x01,0xFF,0x97,0xFF,0x80,0x00,0x00,0x00, +0x01,0xFF,0xB7,0xFF,0x00,0x00,0x00,0x00,0x01,0xFF, +0xEF,0xFE,0x00,0x00,0x00,0x00,0x03,0xFF,0x7F,0xE0, +0x00,0x00,0x00,0x00,0x3F,0xF7,0xFE,0x00,0x00,0x00, +0x00,0x07,0xFF,0xAF,0xFC,0x00,0x00,0x00,0x00,0x0F, +0xFC,0xFF,0xC0,0x00,0x00,0x00,0x01,0xFF,0xD1,0xFF, +0x80,0x00,0x00,0x00,0x03,0xFF,0x1F,0xF8,0x00,0x00, +0x00,0x00,0x7F,0xF2,0x3F,0xF0,0x00,0x00,0x00,0x00, +0xFF,0xC3,0xFF,0x00,0x00,0x00,0x00,0x1F,0xFC,0x3F, +0xF0,0x00,0x00,0x00,0x01,0xFF,0x83,0xFF,0x00,0x00, +0x00,0x00,0x3F,0xF8,0x3F,0xF0,0x00,0x00,0x00,0x07, +0xFF,0x03,0xFF,0x00,0x00,0x00,0x00,0xFF,0xF0,0x3F, +0xF0,0x00,0x00,0x00,0x1F,0xFE,0x03,0xFF,0x00,0x00, +0x00,0x03,0xFF,0xC0,0x3F,0xF0,0x00,0x00,0x00,0xFF, +0xFC,0x03,0xFF,0x00,0x00,0x00,0x3F,0xFF,0x80,0x3F, +0xF0,0x00,0x00,0x3F,0xFF,0xF0,0x03,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFE,0x00,0x3F,0xFF,0xFF,0xFF,0xFF,0xFF, +0xC0,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x3F, +0xFF,0xFF,0xFF,0xFF,0xFE,0x00,0x03,0xFF,0xFF,0xFF, +0xFF,0xFF,0x80,0x00,0x3F,0xFF,0xFF,0xFF,0xFF,0xE0, +0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x3F, +0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x00,0x0D,0xA4,0x20, +0x04,0x3D,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF1,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xE6,0xFF,0xE0,0x00,0x00, +0x00,0x00,0x01,0xBF,0xF8,0x00,0x00,0x00,0x00,0x00, +0x6F,0xFE,0x00,0x00,0x00,0x00,0x00,0x11,0xFF,0x80, +0x00,0x00,0x00,0x00,0x06,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xC0,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x83,0x7F, +0xF0,0x00,0x00,0x00,0x00,0x00,0xDF,0xFC,0x00,0x00, +0x00,0x00,0x00,0x37,0xFF,0x00,0x00,0x00,0x00,0x00, +0x0A,0xFF,0xC0,0x00,0x00,0x00,0x00,0x03,0x7F,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0x7F,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFE,0x0C,0x24,0x20,0x03,0xDD,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xEF, +0xFE,0x00,0x00,0x00,0x00,0x06,0xFF,0xE0,0x00,0x00, +0x00,0x00,0x6F,0xFE,0x00,0x00,0x00,0x00,0x04,0x7F, +0xE0,0x00,0x00,0x00,0x00,0x6F,0xFF,0xFF,0xFF,0xFF, +0xFE,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0x03,0x7F,0xF0, +0x00,0x00,0x00,0x00,0x37,0xFF,0x00,0x00,0x00,0x00, +0x03,0x7F,0xF0,0x00,0x00,0x00,0x00,0x37,0xFF,0x00, +0x00,0x00,0x00,0x02,0xFF,0xF0,0x00,0x00,0x00,0x00, +0x00,0x10,0xE5,0x17,0xFC,0xE0,0x00,0x00,0x00,0x3F, +0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF, +0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xFF,0xFE,0x00, +0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFF,0xFC,0x00,0x00, +0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x00, +0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x00,0x1F,0xFF, +0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x07,0xFF,0xFF,0xFF, +0xFF,0xFF,0xF0,0x00,0x00,0xFF,0xFF,0xE0,0x03,0xFF, +0xFF,0x80,0x00,0x1F,0xFF,0xE0,0x00,0x03,0xFF,0xF8, +0x00,0x03,0xFF,0xF8,0x00,0x00,0x0F,0xFF,0xC0,0x00, +0x7F,0xFE,0x00,0x00,0x00,0x3F,0xFE,0x00,0x07,0xFF, +0x80,0x00,0x00,0x01,0xFF,0xE0,0x00,0xFF,0xF0,0x00, +0x00,0x00,0x0F,0xFF,0x00,0x1F,0xFE,0x00,0x00,0x00, +0x00,0x7F,0xF0,0x01,0xFF,0xC0,0x00,0x00,0x00,0x03, +0xFF,0x80,0x3F,0xF8,0x00,0x00,0x00,0x00,0x1F,0xF8, +0x03,0xFF,0x00,0x00,0x00,0x00,0x01,0xFF,0xC0,0x7F, +0xF0,0x00,0x00,0x00,0x00,0x0F,0xFC,0x07,0xFE,0x00, +0x00,0x00,0x00,0x00,0xFF,0xC0,0xFF,0xE0,0x00,0x00, +0x00,0x00,0x07,0xFE,0x0F,0xFC,0x00,0x00,0x00,0x00, +0x00,0x7F,0x81,0xFF,0xC0,0x00,0x00,0x00,0x00,0x07, +0x80,0x93,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x01, +0x4F,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x3F, +0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0xFF,0xE0, +0x00,0x00,0x07,0xFF,0xFF,0xFF,0xF7,0xFE,0x00,0x00, +0x00,0x7F,0xFF,0xFF,0xFF,0xB7,0xFE,0x00,0x00,0x00, +0x00,0x00,0x07,0xFF,0x07,0xFE,0x00,0x00,0x00,0x00, +0x00,0x0F,0xFC,0x7F,0xF0,0x00,0x00,0x00,0x00,0x00, +0xFF,0xE0,0x7F,0xE0,0x00,0x00,0x00,0x00,0x01,0xFF, +0x87,0xFF,0x00,0x00,0x00,0x00,0x00,0x1F,0xFC,0x07, +0xFF,0x00,0x00,0x00,0x00,0x00,0x3F,0xF0,0x3F,0xF8, +0x00,0x00,0x00,0x00,0x03,0xFF,0x01,0xFF,0xC0,0x00, +0x00,0x00,0x00,0x3F,0xF0,0x1F,0xFE,0x00,0x00,0x00, +0x00,0x0F,0xFF,0x00,0xFF,0xF0,0x00,0x00,0x00,0x01, +0xFF,0xF0,0x07,0xFF,0x80,0x00,0x00,0x00,0x7F,0xFF, +0x00,0x3F,0xFE,0x00,0x00,0x00,0x1F,0xFF,0xF0,0x03, +0xFF,0xF8,0x00,0x00,0x07,0xFF,0xFE,0x00,0x1F,0xFF, +0xF0,0x00,0x03,0xFF,0xFF,0xC0,0x00,0x7F,0xFF,0xF0, +0x03,0xFF,0xFF,0xF0,0x00,0x03,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFE,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xFF, +0x80,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xE0,0x00, +0x00,0x01,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x00, +0x07,0xFF,0xFF,0xFF,0xFE,0x00,0x00,0x00,0x00,0x1F, +0xFF,0xFF,0xFF,0x80,0x00,0x00,0x00,0x00,0x3F,0xFF, +0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0x00, +0x00,0x00,0x0E,0x24,0x20,0x04,0x8D,0xFF,0xC0,0x00, +0x00,0x00,0x03,0xFF,0xDF,0xFC,0x00,0x00,0x00,0x00, +0x3F,0xFD,0xFF,0xC0,0x00,0x00,0x00,0x03,0xFF,0xDF, +0xFC,0x00,0x00,0x00,0x00,0x3F,0xF8,0xFF,0xC0,0x00, +0x00,0x00,0x03,0xFF,0xDF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xF7,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE,0xFF, +0xE0,0x00,0x00,0x00,0x01,0xFF,0xEF,0xFE,0x00,0x00, +0x00,0x00,0x1F,0xFE,0xFF,0xE0,0x00,0x00,0x00,0x01, +0xFF,0xEF,0xFE,0x00,0x00,0x00,0x00,0x1F,0xFE,0x7F, +0xE0,0x00,0x00,0x00,0x01,0xFF,0x80,0x02,0xA4,0x24, +0x01,0xCD,0xFF,0xF7,0xFF,0xDF,0xFF,0x7F,0xFD,0xFF, +0xF7,0xFF,0xDF,0xFF,0x7F,0xFD,0xFF,0xF7,0xFF,0x8F, +0xFC,0x09,0xE4,0x8F,0xFB,0x2D,0x00,0x00,0x00,0x07, +0xFF,0xA0,0x00,0x00,0x00,0xFF,0xF4,0x00,0x00,0x00, +0x1F,0xFE,0x80,0x00,0x00,0x03,0xFF,0xD0,0x00,0x00, +0x00,0x7F,0xFA,0x00,0x00,0x00,0x0F,0xFF,0x40,0x00, +0x00,0x01,0xFF,0x80,0x00,0x00,0x01,0xFF,0x80,0xF0, +0x00,0x01,0xFF,0xDF,0xFE,0x00,0x00,0x3F,0xF7,0xFF, +0x00,0x00,0x3F,0xF7,0xFF,0x00,0x00,0x7F,0xE8,0x7F, +0xE0,0x00,0x0F,0xFC,0x7F,0xF0,0x00,0x1F,0xFC,0x7F, +0xF0,0x00,0x1F,0xF8,0x3F,0xF8,0x00,0x3F,0xF8,0x3F, +0xFC,0x00,0x7F,0xF8,0x1F,0xFF,0x01,0xFF,0xF0,0x1F, +0xFF,0xFF,0xFF,0xE0,0x0F,0xFF,0xFF,0xFF,0xE0,0x07, +0xFF,0xFF,0xFF,0xC0,0x03,0xFF,0xFF,0xFF,0x80,0x01, +0xFF,0xFF,0xFE,0x00,0x00,0xFF,0xFF,0xFC,0x00,0x00, +0x3F,0xFF,0xF0,0x00,0x00,0x03,0xFF,0x00,0x00,0x0E, +0xE4,0x20,0x04,0x37,0xFE,0x00,0x00,0x00,0x00,0xFF, +0xFC,0x7F,0xE0,0x00,0x00,0x00,0x1F,0xFF,0x87,0xFE, +0x00,0x00,0x00,0x03,0xFF,0xF0,0x7F,0xE0,0x00,0x00, +0x00,0x7F,0xFE,0x07,0xFE,0x00,0x00,0x00,0x0F,0xFF, +0xC0,0x7F,0xE0,0x00,0x00,0x01,0xFF,0xF8,0x07,0xFE, +0x00,0x00,0x00,0x3F,0xFF,0x00,0x7F,0xE0,0x00,0x00, +0x07,0xFF,0xE0,0x07,0xFE,0x00,0x00,0x00,0xFF,0xFC, +0x00,0x7F,0xE0,0x00,0x00,0x1F,0xFF,0x80,0x07,0xFE, +0x00,0x00,0x03,0xFF,0xF0,0x00,0x7F,0xE0,0x00,0x00, +0x7F,0xFE,0x00,0x07,0xFE,0x00,0x00,0x0F,0xFF,0xC0, +0x00,0x7F,0xE0,0x00,0x01,0xFF,0xF8,0x00,0x07,0xFE, +0x00,0x00,0x3F,0xFF,0x00,0x00,0x7F,0xE0,0x00,0x07, +0xFF,0xE0,0x00,0x07,0xFE,0x00,0x00,0xFF,0xFC,0x00, +0x00,0x7F,0xE0,0x00,0x1F,0xFF,0x80,0x00,0x07,0xFE, +0x00,0x03,0xFF,0xF0,0x00,0x00,0x7F,0xE0,0x00,0x7F, +0xFE,0x00,0x00,0x07,0xFE,0x00,0x0F,0xFF,0xC0,0x00, +0x00,0x7F,0xE0,0x01,0xFF,0xF8,0x00,0x00,0x07,0xFE, +0x00,0x3F,0xFF,0x00,0x00,0x00,0x7F,0xE0,0x07,0xFF, +0xE0,0x00,0x00,0x07,0xFE,0x00,0xFF,0xFC,0x00,0x00, +0x00,0x7F,0xE0,0x1F,0xFF,0x80,0x00,0x00,0x07,0xFE, +0x03,0xFF,0xF0,0x00,0x00,0x00,0x7F,0xE0,0x7F,0xFE, +0x00,0x00,0x00,0x07,0xFE,0x0F,0xFF,0xC0,0x00,0x00, +0x00,0x7F,0xE1,0xFF,0xF8,0x00,0x00,0x00,0x07,0xFE, +0x3F,0xFF,0x80,0x00,0x00,0x00,0x7F,0xE7,0xFF,0xFC, +0x00,0x00,0x00,0x07,0xFE,0xFF,0xFF,0xC0,0x00,0x00, +0x00,0x7F,0xFF,0xFF,0xFE,0x00,0x00,0x00,0x07,0xFF, +0xFF,0xFF,0xF0,0x00,0x00,0x00,0x8F,0xFF,0xFF,0xFF, +0xF0,0x00,0x00,0x00,0xFF,0xFF,0xF7,0xFF,0x80,0x00, +0x00,0x0F,0xFF,0xFE,0x3F,0xFC,0x00,0x00,0x00,0xFF, +0xFF,0xC3,0xFF,0xE0,0x00,0x00,0x0F,0xFF,0xF8,0x1F, +0xFE,0x00,0x00,0x00,0xFF,0xFF,0x00,0xFF,0xF0,0x00, +0x00,0x0F,0xFF,0xE0,0x07,0xFF,0x80,0x00,0x00,0xFF, +0xFC,0x00,0x7F,0xFC,0x00,0x00,0x0F,0xFF,0x80,0x03, +0xFF,0xC0,0x00,0x00,0xFF,0xF0,0x00,0x1F,0xFE,0x00, +0x00,0x0F,0xFE,0x00,0x00,0xFF,0xF0,0x00,0x00,0xFF, +0xC0,0x00,0x0F,0xFF,0x80,0x00,0x0F,0xFC,0x00,0x00, +0x7F,0xF8,0x00,0x00,0xFF,0xC0,0x00,0x03,0xFF,0xC0, +0x00,0x0F,0xFC,0x00,0x00,0x1F,0xFE,0x00,0x00,0xFF, +0xC0,0x00,0x01,0xFF,0xF0,0x00,0x0F,0xFC,0x00,0x00, +0x0F,0xFF,0x00,0x00,0xFF,0xC0,0x00,0x00,0x7F,0xF8, +0x00,0x0F,0xFC,0x00,0x00,0x03,0xFF,0xC0,0x00,0xFF, +0xC0,0x00,0x00,0x3F,0xFE,0x00,0x0F,0xFC,0x00,0x00, +0x01,0xFF,0xE0,0x00,0xFF,0xC0,0x00,0x00,0x0F,0xFF, +0x00,0x0F,0xFC,0x00,0x00,0x00,0x7F,0xF8,0x00,0xFF, +0xC0,0x00,0x00,0x07,0xFF,0xC0,0x0F,0xFC,0x00,0x00, +0x00,0x3F,0xFC,0x00,0xFF,0xC0,0x00,0x00,0x01,0xFF, +0xE0,0x0F,0xFC,0x00,0x00,0x00,0x0F,0xFF,0x00,0xFF, +0xC0,0x00,0x00,0x00,0xFF,0xF8,0x0F,0xFC,0x00,0x00, +0x00,0x07,0xFF,0x80,0xFF,0xC0,0x00,0x00,0x00,0x3F, +0xFC,0x0F,0xFC,0x00,0x00,0x00,0x01,0xFF,0xE0,0xFF, +0xC0,0x00,0x00,0x00,0x1F,0xFF,0x0F,0xFC,0x00,0x00, +0x00,0x00,0xFF,0xF0,0xFF,0xC0,0x00,0x00,0x00,0x07, +0xFF,0x8F,0xFC,0x00,0x00,0x00,0x00,0x3F,0xFC,0xFF, +0xC0,0x00,0x00,0x00,0x03,0xFF,0xE0,0x0B,0x64,0x20, +0x03,0x8D,0xFF,0xC0,0x00,0x00,0x00,0x06,0xFF,0xE0, +0x00,0x00,0x00,0x03,0x7F,0xF0,0x00,0x00,0x00,0x01, +0xBF,0xF8,0x00,0x00,0x00,0x00,0xDF,0xFC,0x00,0x00, +0x00,0x00,0x6F,0xFE,0x00,0x00,0x00,0x00,0x37,0xFF, +0x00,0x00,0x00,0x00,0x1B,0xFF,0x80,0x00,0x00,0x00, +0x0D,0xFF,0xC0,0x00,0x00,0x00,0x03,0xFF,0x00,0x00, +0x00,0x00,0x1B,0xFF,0xFF,0xFF,0xFF,0xFF,0xF7,0xFF, +0xFF,0xFF,0xFF,0xFF,0xC0,0x11,0x64,0x1C,0x05,0x38, +0xFF,0xFE,0x00,0x00,0x00,0x00,0x03,0xFF,0xFC,0xFF, +0xFF,0x80,0x00,0x00,0x00,0x03,0xFF,0xFE,0x7F,0xFF, +0xE0,0x00,0x00,0x00,0x03,0xFF,0xFF,0x3F,0xFF,0xF8, +0x00,0x00,0x00,0x03,0xFF,0xFF,0x7F,0xFF,0xF0,0x00, +0x00,0x00,0x0F,0xFF,0xFD,0xFF,0xFF,0xC0,0x00,0x00, +0x00,0x7F,0xFF,0xF7,0xFE,0xFF,0x00,0x00,0x00,0x01, +0xFE,0xFF,0xDF,0xFB,0xFE,0x00,0x00,0x00,0x07,0xFB, +0xFF,0x7F,0xEF,0xF8,0x00,0x00,0x00,0x3F,0xEF,0xFD, +0xFF,0x9F,0xE0,0x00,0x00,0x00,0xFF,0x3F,0xF7,0xFE, +0x7F,0xC0,0x00,0x00,0x03,0xFC,0xFF,0xDF,0xF9,0xFF, +0x00,0x00,0x00,0x1F,0xF3,0xFF,0x8F,0xFC,0x7F,0x80, +0x00,0x00,0x0F,0xF1,0xFF,0xBF,0xF1,0xFF,0x00,0x00, +0x00,0x7F,0xC7,0xFF,0x1F,0xF8,0x7F,0x80,0x00,0x00, +0x3F,0xC3,0xFF,0x7F,0xE1,0xFF,0x00,0x00,0x01,0xFF, +0x0F,0xFE,0x3F,0xF0,0x7F,0x80,0x00,0x00,0xFF,0x07, +0xFE,0xFF,0xC1,0xFF,0x00,0x00,0x07,0xFC,0x1F,0xFC, +0x7F,0xE0,0x7F,0x80,0x00,0x03,0xFC,0x0F,0xFD,0xFF, +0x81,0xFF,0x00,0x00,0x1F,0xF0,0x3F,0xF8,0xFF,0xC0, +0x7F,0x80,0x00,0x0F,0xF0,0x1F,0xFB,0xFF,0x01,0xFF, +0x00,0x00,0x7F,0xC0,0x7F,0xEF,0xFC,0x07,0xFC,0x00, +0x01,0xFE,0x01,0xFF,0xBF,0xF0,0x0F,0xF0,0x00,0x07, +0xF8,0x07,0xFF,0x1F,0xF8,0x07,0xFC,0x00,0x07,0xFC, +0x03,0xFF,0x7F,0xE0,0x0F,0xF0,0x00,0x1F,0xE0,0x0F, +0xFE,0x3F,0xF0,0x07,0xFC,0x00,0x1F,0xF0,0x07,0xFE, +0xFF,0xC0,0x0F,0xF0,0x00,0x7F,0x80,0x1F,0xFC,0x7F, +0xE0,0x07,0xFC,0x00,0x7F,0xC0,0x0F,0xFD,0xFF,0x80, +0x0F,0xF0,0x01,0xFE,0x00,0x3F,0xF8,0xFF,0xC0,0x07, +0xFC,0x01,0xFF,0x00,0x1F,0xFB,0xFF,0x00,0x0F,0xF0, +0x07,0xF8,0x00,0x7F,0xEF,0xFC,0x00,0x3F,0xC0,0x3F, +0xE0,0x01,0xFF,0xBF,0xF0,0x00,0xFF,0x80,0xFF,0x80, +0x07,0xFF,0x1F,0xF8,0x00,0x3F,0xC0,0x7F,0x80,0x03, +0xFF,0x7F,0xE0,0x00,0xFF,0x83,0xFE,0x00,0x0F,0xFE, +0x3F,0xF0,0x00,0x3F,0xC1,0xFE,0x00,0x07,0xFE,0xFF, +0xC0,0x00,0xFF,0x8F,0xF8,0x00,0x1F,0xFB,0xFF,0x00, +0x03,0xFE,0x3F,0xC0,0x00,0x7F,0xEF,0xFC,0x00,0x07, +0xF8,0xFF,0x00,0x01,0xFF,0xBF,0xF0,0x00,0x1F,0xF7, +0xFC,0x00,0x07,0xFE,0xFF,0xC0,0x00,0x7F,0xDF,0xE0, +0x00,0x1F,0xFB,0xFF,0x00,0x00,0xFF,0x7F,0x80,0x00, +0x7F,0xF1,0xFF,0x80,0x00,0x7F,0xFF,0xC0,0x00,0x3F, +0xF9,0xFF,0xC0,0x00,0x1F,0xFF,0xC0,0x00,0x1F,0xFC, +0xFF,0xE0,0x00,0x07,0xFF,0xC0,0x00,0x0F,0xFE,0x7F, +0xF0,0x00,0x01,0xFF,0xC0,0x00,0x07,0xFE,0x0E,0x24, +0x20,0x04,0x87,0xFF,0x00,0x00,0x00,0x00,0x1F,0xFC, +0x7F,0xF8,0x00,0x00,0x00,0x01,0xFF,0xBF,0xFE,0x00, +0x00,0x00,0x00,0xFF,0xE3,0xFF,0xF0,0x00,0x00,0x00, +0x0F,0xFE,0x3F,0xFF,0x80,0x00,0x00,0x00,0xFF,0xDF, +0xFF,0xE0,0x00,0x00,0x00,0x7F,0xF1,0xFF,0xFF,0x00, +0x00,0x00,0x07,0xFE,0xFF,0xFF,0xC0,0x00,0x00,0x03, +0xFF,0x8F,0xFF,0xFE,0x00,0x00,0x00,0x3F,0xF7,0xFF, +0xFF,0x80,0x00,0x00,0x1F,0xFC,0x7F,0xFF,0xFC,0x00, +0x00,0x01,0xFF,0xBF,0xFF,0xFF,0x00,0x00,0x00,0xFF, +0xE3,0xFF,0x7F,0xF8,0x00,0x00,0x0F,0xFD,0xFF,0x9F, +0xFE,0x00,0x00,0x07,0xFF,0x1F,0xF8,0xFF,0xF0,0x00, +0x00,0x7F,0xEF,0xFC,0x3F,0xFC,0x00,0x00,0x3F,0xF7, +0xFE,0x1F,0xFF,0x00,0x00,0x1F,0xFB,0xFF,0x07,0xFF, +0x80,0x00,0x0F,0xFD,0xFF,0x81,0xFF,0xE0,0x00,0x07, +0xFE,0xFF,0xC0,0xFF,0xF8,0x00,0x03,0xFF,0x7F,0xE0, +0x3F,0xFC,0x00,0x01,0xFF,0xC7,0xFE,0x01,0xFF,0xE0, +0x00,0x1F,0xFB,0xFF,0x00,0x7F,0xF8,0x00,0x0F,0xFE, +0x3F,0xF0,0x03,0xFF,0xC0,0x00,0xFF,0xDF,0xF8,0x00, +0xFF,0xF0,0x00,0x7F,0xF1,0xFF,0x80,0x07,0xFF,0x80, +0x07,0xFE,0xFF,0xC0,0x01,0xFF,0xE0,0x03,0xFF,0x8F, +0xFC,0x00,0x0F,0xFF,0x00,0x3F,0xF7,0xFE,0x00,0x03, +0xFF,0xC0,0x1F,0xFC,0x7F,0xE0,0x00,0x1F,0xFE,0x01, +0xFF,0xBF,0xF0,0x00,0x07,0xFF,0x80,0xFF,0xDF,0xF8, +0x00,0x03,0xFF,0xE0,0x7F,0xEF,0xFC,0x00,0x00,0xFF, +0xF0,0x3F,0xF7,0xFE,0x00,0x00,0x3F,0xFC,0x1F,0xFB, +0xFF,0x00,0x00,0x1F,0xFF,0x0F,0xFD,0xFF,0x80,0x00, +0x07,0xFF,0x87,0xFF,0x1F,0xF8,0x00,0x00,0x3F,0xFC, +0x7F,0xEF,0xFC,0x00,0x00,0x0F,0xFF,0x3F,0xF8,0xFF, +0xC0,0x00,0x00,0x7F,0xFB,0xFF,0x7F,0xE0,0x00,0x00, +0x1F,0xFF,0xFF,0xC7,0xFE,0x00,0x00,0x00,0xFF,0xFF, +0xFB,0xFF,0x00,0x00,0x00,0x3F,0xFF,0xFE,0x3F,0xF0, +0x00,0x00,0x01,0xFF,0xFF,0xDF,0xF8,0x00,0x00,0x00, +0x7F,0xFF,0xF1,0xFF,0x80,0x00,0x00,0x03,0xFF,0xFE, +0xFF,0xC0,0x00,0x00,0x00,0xFF,0xFF,0x8F,0xFC,0x00, +0x00,0x00,0x07,0xFF,0xF8,0xFF,0xC0,0x00,0x00,0x00, +0x3F,0xFF,0x7F,0xE0,0x00,0x00,0x00,0x0F,0xFF,0xC7, +0xFE,0x00,0x00,0x00,0x00,0x7F,0xFB,0xFF,0x00,0x00, +0x00,0x00,0x1F,0xFC,0x11,0x25,0x17,0xFC,0xE0,0x00, +0x00,0x00,0x7F,0xF8,0x00,0x00,0x00,0x00,0x00,0x00, +0x7F,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF, +0xFF,0xFC,0x00,0x00,0x00,0x00,0x03,0xFF,0xFF,0xFF, +0xF8,0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xF0, +0x00,0x00,0x00,0x07,0xFF,0xFF,0xFF,0xFF,0xE0,0x00, +0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x00, +0x0F,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0xFF, +0xFF,0xC0,0x0F,0xFF,0xFC,0x00,0x00,0x0F,0xFF,0xF0, +0x00,0x0F,0xFF,0xF0,0x00,0x00,0xFF,0xFC,0x00,0x00, +0x0F,0xFF,0xC0,0x00,0x0F,0xFF,0x80,0x00,0x00,0x3F, +0xFF,0x00,0x00,0xFF,0xF8,0x00,0x00,0x00,0x7F,0xF8, +0x00,0x07,0xFF,0x80,0x00,0x00,0x01,0xFF,0xE0,0x00, +0x7F,0xF8,0x00,0x00,0x00,0x07,0xFF,0x80,0x07,0xFF, +0x80,0x00,0x00,0x00,0x1F,0xFC,0x00,0x3F,0xF8,0x00, +0x00,0x00,0x00,0x7F,0xF0,0x03,0xFF,0x80,0x00,0x00, +0x00,0x01,0xFF,0xC0,0x1F,0xF8,0x00,0x00,0x00,0x00, +0x0F,0xFE,0x01,0xFF,0xC0,0x00,0x00,0x00,0x00,0x3F, +0xF8,0x0F,0xFC,0x00,0x00,0x00,0x00,0x01,0xFF,0xC0, +0x7F,0xE0,0x00,0x00,0x00,0x00,0x07,0xFE,0x07,0xFE, +0x00,0x00,0x00,0x00,0x00,0x3F,0xF9,0x07,0xFE,0x00, +0x00,0x00,0x00,0x00,0x1F,0xF8,0x7F,0xE0,0x00,0x00, +0x00,0x00,0x00,0xFF,0xEA,0x7F,0xE0,0x00,0x00,0x00, +0x00,0x00,0x7F,0xED,0xFF,0xC0,0x00,0x00,0x00,0x00, +0x00,0x3F,0xFD,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00, +0x3F,0xF3,0xFE,0x00,0x00,0x00,0x00,0x00,0x03,0xFF, +0x53,0xFF,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0x49, +0xFF,0x80,0x00,0x00,0x00,0x00,0x07,0xFE,0x40,0xFF, +0xC0,0x00,0x00,0x00,0x00,0x0F,0xFC,0x07,0xFF,0x00, +0x00,0x00,0x00,0x00,0xFF,0xE0,0x1F,0xF8,0x00,0x00, +0x00,0x00,0x0F,0xFE,0x00,0xFF,0xE0,0x00,0x00,0x00, +0x00,0x7F,0xF0,0x03,0xFF,0x80,0x00,0x00,0x00,0x07, +0xFF,0x00,0x1F,0xFE,0x00,0x00,0x00,0x00,0x7F,0xF8, +0x00,0x7F,0xF8,0x00,0x00,0x00,0x07,0xFF,0x80,0x01, +0xFF,0xE0,0x00,0x00,0x00,0x7F,0xF8,0x00,0x07,0xFF, +0x80,0x00,0x00,0x07,0xFF,0xC0,0x00,0x3F,0xFE,0x00, +0x00,0x00,0x7F,0xFC,0x00,0x00,0xFF,0xFC,0x00,0x00, +0x0F,0xFF,0xC0,0x00,0x03,0xFF,0xF8,0x00,0x01,0xFF, +0xFC,0x00,0x00,0x0F,0xFF,0xFC,0x00,0xFF,0xFF,0xC0, +0x00,0x00,0x3F,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x00, +0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x01, +0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x00,0x03,0xFF, +0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x0F,0xFF,0xFF, +0xFF,0xF0,0x00,0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFC, +0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF,0x00,0x00, +0x00,0x00,0x00,0x00,0x07,0xFF,0x80,0x00,0x00,0x00, +0x0D,0xA4,0x20,0x04,0x37,0xFF,0xFF,0xFF,0xFF,0x80, +0x00,0x0F,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x1F,0xFF, +0xFF,0xFF,0xFF,0xFE,0x00,0x3F,0xFF,0xFF,0xFF,0xFF, +0xFE,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0x01,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x07, +0xFE,0x00,0x00,0x00,0xFF,0xFE,0x0F,0xFC,0x00,0x00, +0x00,0x3F,0xFE,0x1F,0xF8,0x00,0x00,0x00,0x1F,0xFE, +0x3F,0xF0,0x00,0x00,0x00,0x1F,0xFC,0x7F,0xE0,0x00, +0x00,0x00,0x3F,0xFC,0xFF,0xC0,0x00,0x00,0x00,0x3F, +0xFA,0x3F,0xF0,0x00,0x00,0x00,0x07,0xFE,0x7F,0xE0, +0x00,0x00,0x00,0x0F,0xFF,0xBF,0xF8,0x00,0x00,0x00, +0x01,0xFF,0xBF,0xF0,0x00,0x00,0x00,0x03,0xFF,0x7F, +0xE0,0x00,0x00,0x00,0x0F,0xFF,0x1F,0xF8,0x00,0x00, +0x00,0x03,0xFF,0x3F,0xF0,0x00,0x00,0x00,0x0F,0xFE, +0x7F,0xE0,0x00,0x00,0x00,0x3F,0xF8,0xFF,0xC0,0x00, +0x00,0x00,0xFF,0xF1,0xFF,0x80,0x00,0x00,0x03,0xFF, +0xC3,0xFF,0x00,0x00,0x00,0x1F,0xFF,0x87,0xFE,0x00, +0x00,0x01,0xFF,0xFE,0x11,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xFC,0x07,0xFF, +0xFF,0xFF,0xFF,0xFF,0xE0,0x0F,0xFF,0xFF,0xFF,0xFF, +0xFF,0x80,0x1F,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x3F, +0xFF,0xFF,0xFF,0xFF,0xC0,0x00,0x7F,0xFF,0xFF,0xFF, +0xF0,0x00,0x01,0xBF,0xF8,0x00,0x00,0x00,0x00,0x00, +0x6F,0xFE,0x00,0x00,0x00,0x00,0x00,0x1B,0xFF,0x80, +0x00,0x00,0x00,0x00,0x06,0xFF,0xE0,0x00,0x00,0x00, +0x00,0x01,0x1F,0xF8,0x00,0x00,0x00,0x00,0x00,0x00, +0x11,0x27,0x17,0xDC,0xE0,0x00,0x00,0x00,0xFF,0xF0, +0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0xF8,0x00, +0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF,0xF8,0x00,0x00, +0x00,0x00,0x03,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x00, +0x00,0x7F,0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x00,0x0F, +0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x00,0x00,0xFF,0xFF, +0xFF,0xFF,0xFF,0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFF, +0xFF,0xFC,0x00,0x00,0x00,0xFF,0xFF,0x80,0x1F,0xFF, +0xF0,0x00,0x00,0x0F,0xFF,0xE0,0x00,0x1F,0xFF,0xC0, +0x00,0x00,0xFF,0xFC,0x00,0x00,0x3F,0xFF,0x00,0x00, +0x0F,0xFF,0x80,0x00,0x00,0x7F,0xFC,0x00,0x00,0xFF, +0xF8,0x00,0x00,0x01,0xFF,0xF0,0x00,0x07,0xFF,0x00, +0x00,0x00,0x07,0xFF,0x80,0x00,0x7F,0xF0,0x00,0x00, +0x00,0x1F,0xFE,0x00,0x07,0xFF,0x00,0x00,0x00,0x00, +0x7F,0xF8,0x00,0x3F,0xF8,0x00,0x00,0x00,0x01,0xFF, +0xC0,0x03,0xFF,0x80,0x00,0x00,0x00,0x07,0xFF,0x00, +0x1F,0xF8,0x00,0x00,0x00,0x00,0x1F,0xF8,0x01,0xFF, +0xC0,0x00,0x00,0x00,0x00,0xFF,0xE0,0x81,0xFF,0x80, +0x00,0x00,0x00,0x00,0x7F,0xE0,0x93,0xFF,0x00,0x00, +0x00,0x00,0x00,0x3F,0xF0,0xB7,0xFE,0x00,0x00,0x00, +0x00,0x00,0x1F,0xF8,0xDF,0xFC,0x00,0x00,0x00,0x00, +0x00,0x0F,0xFC,0xDF,0xFC,0x00,0x00,0x00,0x00,0x00, +0x0F,0xFC,0xB7,0xFE,0x00,0x00,0x00,0x00,0x00,0x1F, +0xF8,0x93,0xFF,0x00,0x00,0x00,0x00,0x00,0x3F,0xF0, +0x0F,0xFC,0x00,0x00,0x00,0x00,0x03,0xFF,0x00,0x7F, +0xE0,0x00,0x00,0x60,0x00,0x1F,0xF8,0x03,0xFF,0x80, +0x00,0x03,0xC0,0x01,0xFF,0xC0,0x0F,0xFC,0x00,0x00, +0x1F,0xC0,0x0F,0xFC,0x00,0x7F,0xF0,0x00,0x01,0xFF, +0x00,0xFF,0xE0,0x01,0xFF,0xC0,0x00,0x0F,0xFE,0x0F, +0xFE,0x00,0x0F,0xFE,0x00,0x00,0x7F,0xF8,0xFF,0xF0, +0x00,0x3F,0xF8,0x00,0x07,0xFF,0xF7,0xFF,0x00,0x00, +0xFF,0xE0,0x00,0x0F,0xFF,0xFF,0xF0,0x00,0x07,0xFF, +0xC0,0x00,0x0F,0xFF,0xFF,0x00,0x00,0x1F,0xFF,0x00, +0x00,0x3F,0xFF,0xF8,0x00,0x00,0x7F,0xFE,0x00,0x00, +0x7F,0xFF,0x80,0x00,0x01,0xFF,0xFC,0x00,0x03,0xFF, +0xF8,0x00,0x00,0x07,0xFF,0xFC,0x00,0xFF,0xFF,0x80, +0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00, +0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xFE,0x00,0x00,0x01, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x03,0xFF, +0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x07,0xFF,0xFF, +0xFF,0xF7,0xFF,0xF0,0x00,0x00,0x0F,0xFF,0xFF,0xFE, +0x1F,0xFF,0xE0,0x00,0x00,0x0F,0xFF,0xFF,0x80,0x7F, +0xFF,0x80,0x00,0x00,0x07,0xFF,0x80,0x00,0xFF,0xF8, +0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xC0,0x00, +0x00,0x00,0x00,0x00,0x00,0x03,0xFC,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x07,0xE0,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x0E,0x00,0x0F,0x64,0x20,0x04,0x87, +0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x1F,0xFF,0xFF, +0xFF,0xFF,0xFE,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFF, +0xFF,0x00,0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE,0x00, +0x07,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE,0x00,0x1F,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x8F,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0x00,0x3F,0xF0,0x00,0x00,0x01,0xFF, +0xFE,0x00,0xFF,0xC0,0x00,0x00,0x00,0xFF,0xFC,0x03, +0xFF,0x00,0x00,0x00,0x00,0xFF,0xF0,0x0F,0xFC,0x00, +0x00,0x00,0x01,0xFF,0xC0,0x47,0xFE,0x00,0x00,0x00, +0x00,0x7F,0xF0,0x1F,0xF8,0x00,0x00,0x00,0x00,0xFF, +0xC0,0x7F,0xE0,0x00,0x00,0x00,0x03,0xFF,0x83,0x7F, +0xF0,0x00,0x00,0x00,0x00,0xFF,0xC0,0xFF,0xC0,0x00, +0x00,0x00,0x07,0xFF,0x04,0x7F,0xE0,0x00,0x00,0x00, +0x03,0xFF,0x01,0xFF,0x80,0x00,0x00,0x00,0x1F,0xFC, +0x08,0xFF,0xC0,0x00,0x00,0x00,0x1F,0xFC,0x03,0xFF, +0x00,0x00,0x00,0x01,0xFF,0xE0,0x0F,0xFC,0x00,0x00, +0x00,0x0F,0xFF,0x80,0x3F,0xF0,0x00,0x00,0x03,0xFF, +0xFC,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xE0,0x03, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x0F,0xFF,0xFF, +0xFF,0xFF,0xFF,0xF8,0x00,0x3F,0xFF,0xFF,0xFF,0xFF, +0xFF,0x80,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFC,0x00, +0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x0F,0xFF, +0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x3F,0xFF,0xFF,0xFF, +0xFF,0x00,0x00,0x00,0xFF,0xC0,0x00,0x3F,0xFE,0x00, +0x00,0x03,0xFF,0x00,0x00,0x1F,0xFE,0x00,0x00,0x0F, +0xFC,0x00,0x00,0x3F,0xFC,0x00,0x00,0x3F,0xF0,0x00, +0x00,0x7F,0xF8,0x00,0x00,0xFF,0xC0,0x00,0x00,0xFF, +0xF0,0x00,0x03,0xFF,0x00,0x00,0x01,0xFF,0xE0,0x00, +0x0F,0xFC,0x00,0x00,0x03,0xFF,0xC0,0x00,0x3F,0xF0, +0x00,0x00,0x07,0xFF,0x00,0x00,0xFF,0xC0,0x00,0x00, +0x0F,0xFE,0x00,0x03,0xFF,0x00,0x00,0x00,0x3F,0xFC, +0x00,0x0F,0xFC,0x00,0x00,0x00,0x7F,0xF8,0x00,0x3F, +0xF0,0x00,0x00,0x00,0xFF,0xE0,0x00,0xFF,0xC0,0x00, +0x00,0x03,0xFF,0xC0,0x03,0xFF,0x00,0x00,0x00,0x07, +0xFF,0x00,0x0F,0xFC,0x00,0x00,0x00,0x0F,0xFE,0x00, +0x3F,0xF0,0x00,0x00,0x00,0x3F,0xFC,0x00,0xFF,0xC0, +0x00,0x00,0x00,0x7F,0xF0,0x03,0xFF,0x00,0x00,0x00, +0x01,0xFF,0xE0,0x0F,0xFC,0x00,0x00,0x00,0x03,0xFF, +0x80,0x3F,0xF0,0x00,0x00,0x00,0x07,0xFF,0x00,0xFF, +0xC0,0x00,0x00,0x00,0x1F,0xFE,0x03,0xFF,0x00,0x00, +0x00,0x00,0x3F,0xF8,0x0F,0xFC,0x00,0x00,0x00,0x00, +0xFF,0xF0,0x3F,0xF0,0x00,0x00,0x00,0x01,0xFF,0xE0, +0xFF,0xC0,0x00,0x00,0x00,0x03,0xFF,0x83,0xFF,0x00, +0x00,0x00,0x00,0x0F,0xFF,0x0F,0xFC,0x00,0x00,0x00, +0x00,0x1F,0xFC,0x3F,0xF0,0x00,0x00,0x00,0x00,0x7F, +0xF8,0xFF,0xC0,0x00,0x00,0x00,0x00,0xFF,0xF3,0xFF, +0x00,0x00,0x00,0x00,0x01,0xFF,0xCF,0xFC,0x00,0x00, +0x00,0x00,0x07,0xFF,0xBF,0xF0,0x00,0x00,0x00,0x00, +0x0F,0xFE,0x0E,0x65,0x17,0xFC,0x30,0x00,0x00,0x1F, +0xFF,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0xFC,0x00, +0x00,0x00,0x00,0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x00, +0xFF,0xFF,0xFF,0xFE,0x00,0x00,0x00,0xFF,0xFF,0xFF, +0xFF,0xE0,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFC,0x00, +0x00,0x3F,0xFF,0xFF,0xFF,0xFF,0xC0,0x00,0x1F,0xFF, +0xFF,0xFF,0xFF,0xF8,0x00,0x0F,0xFF,0xF0,0x01,0xFF, +0xFE,0x00,0x07,0xFF,0xE0,0x00,0x0F,0xFF,0xC0,0x03, +0xFF,0xE0,0x00,0x00,0xFF,0xF8,0x00,0xFF,0xE0,0x00, +0x00,0x0F,0xFE,0x08,0x0F,0xFE,0x00,0x00,0x00,0x3F, +0xF8,0x03,0xFF,0x00,0x00,0x00,0x07,0xFF,0x01,0xFF, +0xC0,0x00,0x00,0x00,0xFF,0xC0,0x7F,0xE0,0x00,0x00, +0x00,0x3F,0xF0,0x1F,0xF8,0x00,0x00,0x00,0x0F,0xFE, +0x48,0xFF,0xC0,0x00,0x00,0x00,0x3F,0xF0,0x3F,0xF0, +0x00,0x00,0x00,0x00,0x00,0x81,0xFF,0xC0,0x00,0x00, +0x00,0x00,0x00,0x3F,0xF8,0x00,0x00,0x00,0x00,0x00, +0x0F,0xFF,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xE0, +0x00,0x00,0x00,0x00,0x00,0x7F,0xFE,0x00,0x00,0x00, +0x00,0x00,0x1F,0xFF,0xF0,0x00,0x00,0x00,0x00,0x03, +0xFF,0xFF,0x80,0x00,0x00,0x00,0x00,0x7F,0xFF,0xFE, +0x00,0x00,0x00,0x00,0x0F,0xFF,0xFF,0xF8,0x00,0x00, +0x00,0x01,0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x00,0x3F, +0xFF,0xFF,0xFF,0x00,0x00,0x00,0x03,0xFF,0xFF,0xFF, +0xF8,0x00,0x00,0x00,0x3F,0xFF,0xFF,0xFF,0x80,0x00, +0x00,0x03,0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x00,0x1F, +0xFF,0xFF,0xFF,0x80,0x00,0x00,0x00,0xFF,0xFF,0xFF, +0xF0,0x00,0x00,0x00,0x03,0xFF,0xFF,0xFE,0x00,0x00, +0x00,0x00,0x1F,0xFF,0xFF,0xC0,0x00,0x00,0x00,0x00, +0x7F,0xFF,0xF8,0x00,0x00,0x00,0x00,0x03,0xFF,0xFF, +0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xE0,0x00,0x00, +0x00,0x00,0x01,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00, +0x1F,0xFF,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xC0, +0x00,0x00,0x00,0x00,0x00,0x7F,0xF4,0x7F,0xE0,0x00, +0x00,0x00,0x01,0xFF,0xDF,0xF8,0x00,0x00,0x00,0x00, +0x3F,0xF8,0xFF,0xE0,0x00,0x00,0x00,0x01,0xFF,0xC3, +0xFF,0x00,0x00,0x00,0x00,0x0F,0xFC,0xFF,0xE0,0x00, +0x00,0x00,0x03,0xFF,0x3F,0xF8,0x00,0x00,0x00,0x01, +0xFF,0xE0,0xFF,0xE0,0x00,0x00,0x00,0x0F,0xFC,0x1F, +0xFC,0x00,0x00,0x00,0x07,0xFF,0x07,0xFF,0x80,0x00, +0x00,0x03,0xFF,0x80,0xFF,0xF0,0x00,0x00,0x01,0xFF, +0xE0,0x3F,0xFF,0x00,0x00,0x00,0xFF,0xF0,0x07,0xFF, +0xE0,0x00,0x00,0x7F,0xFC,0x00,0xFF,0xFF,0x00,0x00, +0x7F,0xFE,0x00,0x1F,0xFF,0xF8,0x01,0xFF,0xFF,0x00, +0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x7F,0xFF, +0xFF,0xFF,0xFF,0xC0,0x00,0x0F,0xFF,0xFF,0xFF,0xFF, +0xE0,0x00,0x01,0xFF,0xFF,0xFF,0xFF,0xE0,0x00,0x00, +0x1F,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x01,0xFF,0xFF, +0xFF,0xF0,0x00,0x00,0x00,0x0F,0xFF,0xFF,0xE0,0x00, +0x00,0x00,0x00,0x1F,0xFF,0x80,0x00,0x00,0x0E,0xA4, +0x08,0x03,0xED,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xDF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE,0x80,0x00, +0x00,0x7F,0xE0,0x00,0x00,0x1A,0x00,0x00,0x01,0xFF, +0x80,0x00,0x00,0x68,0x00,0x00,0x07,0xFE,0x00,0x00, +0x01,0xA0,0x00,0x00,0x1F,0xF8,0x00,0x00,0x06,0x80, +0x00,0x00,0x7F,0xE0,0x00,0x00,0x1A,0x00,0x00,0x01, +0xFF,0x80,0x00,0x00,0x68,0x00,0x00,0x07,0xFE,0x00, +0x00,0x01,0xA0,0x00,0x00,0x1F,0xF8,0x00,0x00,0x06, +0x80,0x00,0x00,0x7F,0xE0,0x00,0x00,0x00,0x00,0x00, +0x0F,0xFC,0x00,0x00,0x00,0x0E,0x24,0xA3,0xFC,0x8D, +0xFF,0xC0,0x00,0x00,0x00,0x03,0xFF,0xDF,0xFC,0x00, +0x00,0x00,0x00,0x3F,0xFD,0xFF,0xC0,0x00,0x00,0x00, +0x03,0xFF,0xDF,0xFC,0x00,0x00,0x00,0x00,0x3F,0xFD, +0xFF,0xC0,0x00,0x00,0x00,0x03,0xFF,0xDF,0xFC,0x00, +0x00,0x00,0x00,0x3F,0xFD,0xFF,0xC0,0x00,0x00,0x00, +0x03,0xFF,0x7F,0xE0,0x00,0x00,0x00,0x03,0xFF,0xD3, +0xFF,0x00,0x00,0x00,0x00,0x3F,0xF4,0x3F,0xF8,0x00, +0x00,0x00,0x07,0xFF,0x0F,0xFC,0x00,0x00,0x00,0x03, +0xFF,0x07,0xFF,0x00,0x00,0x00,0x03,0xFF,0x83,0xFF, +0xC0,0x00,0x00,0x03,0xFF,0xC0,0xFF,0xF0,0x00,0x00, +0x03,0xFF,0xC0,0x7F,0xFC,0x00,0x00,0x03,0xFF,0xE0, +0x1F,0xFF,0x00,0x00,0x03,0xFF,0xE0,0x0F,0xFF,0xE0, +0x00,0x07,0xFF,0xF0,0x03,0xFF,0xFE,0x00,0x3F,0xFF, +0xF0,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x3F, +0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x0F,0xFF,0xFF,0xFF, +0xFF,0xF0,0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xF0,0x00, +0x00,0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x1F,0xFF, +0xFF,0xFF,0xE0,0x00,0x00,0x03,0xFF,0xFF,0xFF,0xC0, +0x00,0x00,0x00,0x3F,0xFF,0xFF,0x00,0x00,0x00,0x00, +0x01,0xFF,0xF8,0x00,0x00,0x00,0x11,0x64,0x7C,0x04, +0x37,0xFF,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xE1, +0xFF,0xC0,0x00,0x00,0x00,0x00,0x01,0xFF,0xC3,0xFF, +0x00,0x00,0x00,0x00,0x00,0x07,0xFE,0x41,0xFF,0xC0, +0x00,0x00,0x00,0x00,0x07,0xFF,0x03,0xFF,0x00,0x00, +0x00,0x00,0x00,0x1F,0xF8,0x0F,0xFE,0x00,0x00,0x00, +0x00,0x00,0xFF,0xE0,0x1F,0xF8,0x00,0x00,0x00,0x00, +0x03,0xFF,0x08,0x0F,0xFE,0x00,0x00,0x00,0x00,0x03, +0xFF,0x80,0x1F,0xF8,0x00,0x00,0x00,0x00,0x0F,0xFC, +0x00,0x7F,0xF0,0x00,0x00,0x00,0x00,0x7F,0xF0,0x00, +0xFF,0xC0,0x00,0x00,0x00,0x01,0xFF,0xC0,0x03,0xFF, +0x00,0x00,0x00,0x00,0x07,0xFE,0x00,0x0F,0xFE,0x00, +0x00,0x00,0x00,0x3F,0xF8,0x00,0x1F,0xF8,0x00,0x00, +0x00,0x00,0xFF,0xC0,0x00,0x7F,0xF0,0x00,0x00,0x00, +0x07,0xFF,0x00,0x00,0xFF,0xC0,0x00,0x00,0x00,0x1F, +0xFC,0x00,0x03,0xFF,0x00,0x00,0x00,0x00,0x7F,0xE0, +0x00,0x0F,0xFE,0x00,0x00,0x00,0x03,0xFF,0x80,0x00, +0x1F,0xF8,0x00,0x00,0x00,0x0F,0xFC,0x00,0x00,0x7F, +0xE0,0x00,0x00,0x00,0x7F,0xF0,0x00,0x00,0xFF,0xC0, +0x00,0x00,0x01,0xFF,0xC0,0x00,0x03,0xFF,0x00,0x00, +0x00,0x07,0xFE,0x00,0x40,0x00,0xFF,0xC0,0x00,0x00, +0x07,0xFF,0x00,0x00,0x03,0xFF,0x00,0x00,0x00,0x1F, +0xF8,0x00,0x00,0x07,0xFE,0x00,0x00,0x00,0xFF,0xE0, +0x00,0x00,0x1F,0xF8,0x00,0x00,0x03,0xFF,0x00,0x08, +0x00,0x07,0xFE,0x00,0x00,0x03,0xFF,0x80,0x00,0x00, +0x1F,0xF8,0x00,0x00,0x0F,0xFC,0x00,0x00,0x00,0x3F, +0xF0,0x00,0x00,0x7F,0xF0,0x00,0x00,0x00,0xFF,0xC0, +0x00,0x01,0xFF,0x80,0x00,0x00,0x01,0xFF,0x00,0x00, +0x07,0xFE,0x00,0x00,0x00,0x07,0xFE,0x00,0x00,0x3F, +0xF8,0x00,0x00,0x00,0x1F,0xF8,0x00,0x00,0xFF,0xC0, +0x00,0x00,0x00,0x3F,0xF0,0x00,0x07,0xFF,0x00,0x00, +0x00,0x00,0xFF,0xC0,0x00,0x1F,0xF8,0x00,0x00,0x00, +0x01,0xFF,0x00,0x00,0x7F,0xE0,0x00,0x00,0x00,0x07, +0xFE,0x00,0x03,0xFF,0x80,0x00,0x00,0x00,0x1F,0xF8, +0x00,0x0F,0xFC,0x00,0x00,0x00,0x00,0x3F,0xE0,0x00, +0x3F,0xF0,0x00,0x00,0x00,0x00,0xFF,0xC0,0x01,0xFF, +0xC0,0x00,0x00,0x00,0x01,0xFF,0x00,0x07,0xFE,0x00, +0x00,0x00,0x00,0x07,0xFE,0x00,0x3F,0xF8,0x00,0x00, +0x00,0x00,0x1F,0xF8,0x00,0xFF,0xC0,0x00,0x00,0x00, +0x00,0x3F,0xE0,0x03,0xFF,0x00,0x00,0x00,0x00,0x00, +0xFF,0xC0,0x1F,0xFC,0x00,0x00,0x40,0x00,0x00,0x3F, +0xE0,0x0F,0xFC,0x00,0x00,0x00,0x00,0x00,0xFF,0xC0, +0x7F,0xE0,0x00,0x00,0x00,0x00,0x01,0xFF,0x01,0xFF, +0x80,0x00,0x00,0x00,0x00,0x07,0xFC,0x0F,0xFE,0x00, +0x00,0x08,0x00,0x00,0x01,0xFF,0x07,0xFE,0x00,0x00, +0x00,0x00,0x00,0x07,0xFE,0x3F,0xF0,0x00,0x00,0x10, +0x00,0x00,0x01,0xFF,0x1F,0xF8,0x00,0x00,0x09,0x00, +0x00,0x00,0x7F,0xDF,0xF8,0x00,0x00,0x04,0x00,0x00, +0x00,0x1F,0xFF,0xF8,0x00,0x00,0x02,0x40,0x00,0x00, +0x07,0xFF,0xF8,0x00,0x00,0x01,0x00,0x00,0x00,0x01, +0xFF,0xF8,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x7F, +0xF8,0x00,0x00,0x00,0x00,0x18,0x64,0x04,0x06,0x37, +0xFE,0x00,0x00,0x00,0x00,0xFF,0xE0,0x00,0x00,0x00, +0x0F,0xFD,0xFF,0xC0,0x00,0x00,0x00,0x7F,0xFC,0x00, +0x00,0x00,0x07,0xFF,0x87,0xFE,0x00,0x00,0x00,0x03, +0xFF,0xE0,0x00,0x00,0x00,0x3F,0xF1,0xFF,0x80,0x00, +0x00,0x01,0xFF,0xFC,0x00,0x00,0x00,0x0F,0xFC,0x7F, +0xF0,0x00,0x00,0x00,0x7F,0xFF,0x00,0x00,0x00,0x07, +0xFF,0x41,0xFF,0x80,0x00,0x00,0x03,0xFF,0xF8,0x00, +0x00,0x00,0x3F,0xF0,0x7F,0xE0,0x00,0x00,0x01,0xFF, +0xFF,0x00,0x00,0x00,0x0F,0xFC,0x1F,0xF8,0x00,0x00, +0x00,0x7F,0xBF,0xC0,0x00,0x00,0x07,0xFF,0x03,0xFF, +0x00,0x00,0x00,0x1F,0xEF,0xF0,0x00,0x00,0x01,0xFF, +0x80,0xFF,0xC0,0x00,0x00,0x0F,0xFB,0xFE,0x00,0x00, +0x00,0x7F,0xE2,0x07,0xFE,0x00,0x00,0x00,0x7F,0x8F, +0xF0,0x00,0x00,0x03,0xFF,0x00,0xFF,0xC0,0x00,0x00, +0x3F,0xE3,0xFC,0x00,0x00,0x01,0xFF,0x84,0x07,0xFE, +0x00,0x00,0x01,0xFE,0x0F,0xF0,0x00,0x00,0x0F,0xFC, +0x00,0xFF,0x80,0x00,0x00,0x7F,0x83,0xFC,0x00,0x00, +0x03,0xFF,0x00,0x3F,0xF0,0x00,0x00,0x3F,0xE0,0x7F, +0x80,0x00,0x01,0xFF,0x82,0x01,0xFF,0x80,0x00,0x01, +0xFE,0x03,0xFC,0x00,0x00,0x0F,0xFC,0x00,0x3F,0xE0, +0x00,0x00,0xFF,0x80,0xFF,0x80,0x00,0x03,0xFE,0x00, +0x0F,0xF8,0x00,0x00,0x3F,0xC0,0x1F,0xE0,0x00,0x00, +0xFF,0x81,0x00,0x7F,0xE0,0x00,0x01,0xFE,0x00,0xFF, +0x00,0x00,0x0F,0xFC,0x00,0x0F,0xF8,0x00,0x00,0xFF, +0x80,0x1F,0xE0,0x00,0x03,0xFE,0x00,0x03,0xFE,0x00, +0x00,0x3F,0xC0,0x07,0xF8,0x00,0x00,0xFF,0x80,0x00, +0xFF,0xC0,0x00,0x0F,0xF0,0x01,0xFE,0x00,0x00,0x7F, +0xE0,0x00,0x3F,0xF0,0x00,0x07,0xFC,0x00,0x3F,0xC0, +0x00,0x1F,0xF8,0x08,0x00,0xFF,0x80,0x00,0x3F,0xC0, +0x01,0xFE,0x00,0x00,0xFF,0x80,0x00,0x3F,0xF0,0x00, +0x1F,0xF0,0x00,0x3F,0x80,0x00,0x7F,0xE0,0x00,0x0F, +0xFC,0x00,0x07,0xFC,0x00,0x0F,0xF0,0x00,0x1F,0xF8, +0x00,0x01,0xFF,0x00,0x01,0xFE,0x00,0x03,0xFC,0x00, +0x07,0xFC,0x00,0x00,0x7F,0xC0,0x00,0x7F,0x80,0x00, +0x7F,0x00,0x01,0xFF,0x00,0x00,0x1F,0xF0,0x00,0x3F, +0xE0,0x00,0x1F,0xE0,0x00,0x7F,0xC0,0x00,0x07,0xFE, +0x00,0x0F,0xF0,0x00,0x07,0xF8,0x00,0x3F,0xF0,0x00, +0x00,0xFF,0x80,0x03,0xFC,0x00,0x01,0xFE,0x00,0x0F, +0xF8,0x00,0x00,0x3F,0xE0,0x01,0xFF,0x00,0x00,0x3F, +0xC0,0x03,0xFE,0x00,0x00,0x0F,0xF8,0x00,0x7F,0x80, +0x00,0x0F,0xF0,0x00,0xFF,0x80,0x00,0x03,0xFF,0x00, +0x1F,0xE0,0x00,0x03,0xFC,0x00,0x7F,0xE0,0x04,0x00, +0x0F,0xF8,0x01,0xFF,0x00,0x00,0x0F,0xF0,0x03,0xFE, +0x00,0x00,0x03,0xFE,0x00,0x7F,0x80,0x00,0x03,0xFC, +0x00,0xFF,0x80,0x00,0x00,0xFF,0xC0,0x1F,0xE0,0x00, +0x00,0x7F,0x80,0x7F,0xE0,0x00,0x00,0x1F,0xF0,0x0F, +0xF8,0x00,0x00,0x1F,0xE0,0x1F,0xF0,0x00,0x00,0x07, +0xFC,0x03,0xFC,0x00,0x00,0x07,0xF8,0x07,0xFC,0x00, +0x00,0x01,0xFF,0x00,0xFF,0x00,0x00,0x00,0xFF,0x01, +0xFF,0x00,0x00,0x00,0x7F,0xC0,0x7F,0xC0,0x00,0x00, +0x3F,0xC0,0x7F,0xC0,0x00,0x00,0x0F,0xF8,0x1F,0xE0, +0x00,0x00,0x0F,0xF0,0x3F,0xE0,0x00,0x80,0x00,0x7F, +0xC0,0xFF,0x00,0x00,0x00,0x3F,0xC1,0xFF,0x00,0x00, +0x00,0x0F,0xF0,0x7F,0xC0,0x00,0x00,0x0F,0xF0,0x7F, +0xC0,0x00,0x00,0x03,0xFE,0x1F,0xE0,0x00,0x00,0x03, +0xFC,0x3F,0xE0,0x00,0x00,0x00,0xFF,0x87,0xF8,0x00, +0x00,0x00,0x7F,0x8F,0xF8,0x00,0x00,0x00,0x3F,0xE3, +0xFE,0x00,0x00,0x00,0x1F,0xE3,0xFE,0x00,0x00,0x00, +0x07,0xF8,0xFF,0x00,0x00,0x00,0x07,0xF8,0xFF,0x00, +0x00,0x00,0x01,0xFE,0x3F,0xC0,0x00,0x00,0x00,0xFE, +0x7F,0xC0,0x00,0x40,0x00,0x0F,0xFB,0xFE,0x00,0x00, +0x00,0x07,0xFB,0xFE,0x00,0x02,0x00,0x00,0x3F,0xDF, +0xE0,0x00,0x00,0x00,0x1F,0xDF,0xE0,0x00,0x00,0x00, +0x0F,0xFF,0xF8,0x00,0x00,0x00,0x07,0xFF,0xF8,0x00, +0x00,0x00,0x03,0xFF,0xFC,0x00,0x00,0x00,0x00,0xFF, +0xFE,0x00,0x01,0x00,0x00,0x0F,0xFF,0xE0,0x00,0x00, +0x00,0x07,0xFF,0xE0,0x00,0x08,0x00,0x00,0x7F,0xFE, +0x00,0x00,0x00,0x00,0x1F,0xFF,0x00,0x00,0x40,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x00,0xFF,0xF0,0x00, +0x02,0x00,0x00,0x0F,0xFF,0x00,0x00,0x00,0x00,0x03, +0xFF,0x80,0x00,0x00,0x10,0x64,0x00,0x04,0x20,0x7F, +0xF8,0x00,0x00,0x00,0x07,0xFF,0xC0,0x0F,0xFF,0x00, +0x00,0x00,0x01,0xFF,0xE0,0x01,0xFF,0xE0,0x00,0x00, +0x00,0xFF,0xF0,0x00,0x7F,0xF8,0x00,0x00,0x00,0x7F, +0xFC,0x00,0x0F,0xFF,0x00,0x00,0x00,0x1F,0xFE,0x00, +0x01,0xFF,0xE0,0x00,0x00,0x0F,0xFF,0x00,0x00,0x7F, +0xF8,0x00,0x00,0x07,0xFF,0xC0,0x00,0x0F,0xFF,0x00, +0x00,0x01,0xFF,0xE0,0x00,0x01,0xFF,0xE0,0x00,0x00, +0xFF,0xF0,0x00,0x00,0x7F,0xF8,0x00,0x00,0x7F,0xFC, +0x00,0x00,0x0F,0xFF,0x00,0x00,0x1F,0xFE,0x00,0x00, +0x01,0xFF,0xE0,0x00,0x0F,0xFF,0x00,0x00,0x00,0x3F, +0xF8,0x00,0x07,0xFF,0xC0,0x00,0x00,0x0F,0xFF,0x00, +0x01,0xFF,0xE0,0x00,0x00,0x01,0xFF,0xE0,0x00,0xFF, +0xF0,0x00,0x00,0x00,0x3F,0xFC,0x00,0x7F,0xFC,0x00, +0x00,0x00,0x0F,0xFF,0x00,0x1F,0xFE,0x00,0x00,0x00, +0x01,0xFF,0xE0,0x0F,0xFF,0x00,0x00,0x80,0x00,0x07, +0xFF,0x80,0xFF,0xF0,0x00,0x00,0x00,0x00,0xFF,0xF0, +0x7F,0xF8,0x00,0x00,0x00,0x00,0x1F,0xFC,0x3F,0xFC, +0x00,0x00,0x00,0x00,0x07,0xFF,0x8F,0xFF,0x00,0x00, +0x00,0x00,0x00,0xFF,0xF7,0xFF,0x80,0x00,0x04,0x00, +0x00,0x03,0xFF,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00, +0x7F,0xFF,0xFC,0x00,0x00,0x08,0x00,0x00,0x01,0xFF, +0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xE0, +0x00,0x00,0x10,0x00,0x00,0x00,0xFF,0xFE,0x00,0x00, +0x00,0x80,0x00,0x00,0x03,0xFF,0xE0,0x00,0x00,0x00, +0x00,0x00,0x01,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00, +0x00,0x7F,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x3F, +0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xF8, +0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xFF,0x00,0x00, +0x00,0x00,0x00,0x03,0xFF,0xFF,0xE0,0x00,0x00,0x40, +0x00,0x00,0x3F,0xFF,0xFF,0x80,0x00,0x00,0x00,0x00, +0x1F,0xFE,0xFF,0xF0,0x00,0x00,0x00,0x00,0x0F,0xFF, +0x9F,0xFE,0x00,0x00,0x00,0x00,0x03,0xFF,0xC7,0xFF, +0x80,0x00,0x00,0x00,0x01,0xFF,0xE0,0xFF,0xF0,0x00, +0x00,0x00,0x00,0xFF,0xF8,0x1F,0xFE,0x00,0x00,0x00, +0x00,0x3F,0xFC,0x07,0xFF,0x80,0x00,0x00,0x00,0x1F, +0xFE,0x00,0xFF,0xF0,0x00,0x08,0x00,0x01,0xFF,0xE0, +0x03,0xFF,0xC0,0x00,0x00,0x00,0xFF,0xF0,0x00,0x7F, +0xF8,0x00,0x10,0x00,0x0F,0xFF,0x00,0x01,0xFF,0xE0, +0x00,0x00,0x07,0xFF,0x80,0x00,0x3F,0xFC,0x00,0x00, +0x03,0xFF,0xC0,0x00,0x07,0xFF,0x80,0x00,0x01,0xFF, +0xF0,0x00,0x01,0xFF,0xE0,0x00,0x00,0x7F,0xF8,0x00, +0x00,0x3F,0xFC,0x00,0x00,0x3F,0xFC,0x00,0x00,0x07, +0xFF,0x80,0x00,0x1F,0xFF,0x00,0x00,0x00,0xFF,0xE0, +0x00,0x07,0xFF,0x80,0x00,0x00,0x3F,0xFC,0x00,0x03, +0xFF,0xC0,0x00,0x00,0x07,0xFF,0x80,0x01,0xFF,0xF0, +0x00,0x00,0x00,0xFF,0xF0,0x00,0x7F,0xF8,0x00,0x00, +0x00,0x3F,0xFC,0x00,0x3F,0xFC,0x00,0x00,0x00,0x07, +0xFF,0x80,0x1F,0xFF,0x00,0x00,0x00,0x00,0xFF,0xF0, +0x07,0xFF,0x80,0x00,0x00,0x00,0x3F,0xFC,0x03,0xFF, +0xC0,0x00,0x00,0x00,0x07,0xFF,0x81,0xFF,0xF0,0x00, +0x00,0x00,0x00,0xFF,0xF0,0x7F,0xF8,0x00,0x00,0x00, +0x00,0x3F,0xFC,0x3F,0xFC,0x00,0x00,0x00,0x00,0x07, +0xFF,0x9F,0xFF,0x00,0x00,0x00,0x00,0x00,0xFF,0xF0, +0x10,0xA4,0x00,0x04,0x27,0xFF,0x80,0x00,0x00,0x00, +0x00,0x1F,0xFE,0x7F,0xF8,0x00,0x00,0x00,0x00,0x07, +0xFF,0x87,0xFF,0x80,0x00,0x00,0x00,0x00,0xFF,0xE0, +0xFF,0xF0,0x00,0x00,0x00,0x00,0x3F,0xFC,0x0F,0xFF, +0x00,0x00,0x00,0x00,0x0F,0xFF,0x00,0xFF,0xF0,0x00, +0x00,0x00,0x01,0xFF,0xC0,0x1F,0xFE,0x00,0x00,0x00, +0x00,0x7F,0xF8,0x01,0xFF,0xE0,0x00,0x00,0x00,0x1F, +0xFE,0x00,0x1F,0xFE,0x00,0x00,0x00,0x03,0xFF,0x80, +0x03,0xFF,0xC0,0x00,0x00,0x00,0xFF,0xF0,0x00,0x3F, +0xFC,0x00,0x00,0x00,0x3F,0xFC,0x00,0x03,0xFF,0xC0, +0x00,0x00,0x07,0xFF,0x00,0x00,0x7F,0xF8,0x00,0x00, +0x01,0xFF,0xE0,0x00,0x07,0xFF,0x80,0x00,0x00,0x3F, +0xF8,0x00,0x00,0x7F,0xF8,0x00,0x00,0x0F,0xFE,0x00, +0x00,0x0F,0xFF,0x00,0x00,0x03,0xFF,0xC0,0x00,0x00, +0xFF,0xF0,0x00,0x00,0x7F,0xF0,0x00,0x00,0x0F,0xFF, +0x00,0x00,0x1F,0xFC,0x00,0x00,0x01,0xFF,0xE0,0x00, +0x07,0xFF,0x80,0x00,0x00,0x1F,0xFE,0x00,0x00,0xFF, +0xE0,0x00,0x00,0x01,0xFF,0xE0,0x00,0x3F,0xF8,0x00, +0x00,0x00,0x1F,0xFC,0x00,0x0F,0xFF,0x00,0x00,0x00, +0x03,0xFF,0xC0,0x01,0xFF,0xC0,0x00,0x00,0x00,0x3F, +0xFC,0x00,0x7F,0xF0,0x00,0x00,0x00,0x03,0xFF,0x80, +0x0F,0xFC,0x00,0x00,0x00,0x00,0x7F,0xF8,0x03,0xFF, +0x80,0x00,0x00,0x00,0x07,0xFF,0x80,0xFF,0xE0,0x00, +0x00,0x00,0x00,0x7F,0xF0,0x1F,0xF8,0x00,0x00,0x00, +0x00,0x0F,0xFF,0x07,0xFF,0x00,0x00,0x00,0x00,0x00, +0xFF,0xF1,0xFF,0xC0,0x00,0x00,0x00,0x00,0x0F,0xFE, +0x3F,0xF0,0x00,0x00,0x00,0x00,0x01,0xFF,0xEF,0xFE, +0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF,0x80,0x00, +0x01,0x00,0x00,0x00,0x3F,0xFF,0xFC,0x00,0x00,0x00, +0x00,0x00,0x03,0xFF,0xFF,0x00,0x00,0x00,0x80,0x00, +0x00,0x07,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x00, +0x7F,0xFE,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0xFF, +0xF0,0x00,0x00,0x01,0xA0,0x00,0x00,0x01,0xFF,0x80, +0x00,0x00,0x06,0x80,0x00,0x00,0x07,0xFE,0x00,0x00, +0x00,0x1A,0x00,0x00,0x00,0x1F,0xF8,0x00,0x00,0x00, +0x68,0x00,0x00,0x00,0x7F,0xE0,0x00,0x00,0x01,0x20, +0x00,0x00,0x01,0xFF,0x80,0x00,0x00,0x00,0x0E,0x64, +0x08,0x03,0xDD,0x07,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE, +0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x00, +0x00,0x00,0x03,0xFF,0xE0,0x00,0x00,0x00,0x00,0x01, +0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x7F,0xF8,0x00, +0x00,0x00,0x00,0x00,0x3F,0xFC,0x00,0x00,0x00,0x00, +0x00,0x1F,0xFF,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF, +0x80,0x00,0x00,0x00,0x00,0x03,0xFF,0xC0,0x00,0x00, +0x00,0x00,0x01,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00, +0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x7F,0xFC,0x00, +0x00,0x00,0x00,0x00,0x1F,0xFE,0x00,0x00,0x00,0x00, +0x00,0x0F,0xFF,0x00,0x00,0x00,0x00,0x00,0x07,0xFF, +0x80,0x00,0x00,0x00,0x00,0x03,0xFF,0xE0,0x00,0x00, +0x00,0x00,0x01,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00, +0x7F,0xF8,0x00,0x00,0x00,0x00,0x00,0x3F,0xFC,0x00, +0x00,0x00,0x00,0x00,0x1F,0xFF,0x00,0x00,0x00,0x00, +0x00,0x0F,0xFF,0x80,0x00,0x00,0x00,0x00,0x03,0xFF, +0xC0,0x00,0x00,0x00,0x00,0x01,0xFF,0xE0,0x00,0x00, +0x00,0x00,0x00,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00, +0x7F,0xFC,0x00,0x00,0x00,0x00,0x00,0x1F,0xFE,0x00, +0x00,0x00,0x00,0x00,0x0F,0xFF,0x00,0x00,0x00,0x00, +0x00,0x07,0xFF,0xC0,0x00,0x00,0x00,0x00,0x03,0xFF, +0xE0,0x00,0x00,0x00,0x00,0x00,0xFF,0xF0,0x00,0x00, +0x00,0x00,0x00,0x7F,0xF8,0x00,0x00,0x00,0x00,0x00, +0x3F,0xFC,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0x00, +0x00,0x00,0x00,0x00,0x0F,0xFF,0x80,0x00,0x00,0x00, +0x00,0x03,0xFF,0xC0,0x00,0x00,0x00,0x00,0x01,0xFF, +0xE0,0x00,0x00,0x00,0x00,0x00,0xFF,0xF8,0x00,0x00, +0x00,0x00,0x00,0x7F,0xFC,0x00,0x00,0x00,0x00,0x00, +0x1F,0xFE,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0x00, +0x00,0x00,0x00,0x00,0x07,0xFF,0xC0,0x00,0x00,0x00, +0x00,0x03,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x00,0x7F,0xF8,0x00,0x00, +0x00,0x00,0x00,0x3F,0xFE,0x00,0x00,0x00,0x00,0x00, +0x1F,0xFF,0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0x80, +0x00,0x00,0x00,0x00,0x03,0xFF,0xC0,0x00,0x00,0x00, +0x00,0x01,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0xFF, +0xF8,0x00,0x00,0x00,0x00,0x00,0x7F,0xFC,0x00,0x00, +0x00,0x00,0x00,0x1F,0xFE,0x00,0x00,0x00,0x00,0x00, +0x0F,0xFF,0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xC0, +0x00,0x00,0x00,0x00,0x03,0xFF,0xE0,0x00,0x00,0x00, +0x00,0x00,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x7F, +0xF8,0x00,0x00,0x00,0x00,0x00,0x3F,0xFE,0x00,0x00, +0x00,0x00,0x00,0x1B,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xC0,0x04, +0xEE,0x1B,0x61,0xCD,0xFF,0xFF,0xEF,0xFF,0xFF,0xBF, +0xF0,0x03,0x7F,0xE0,0x06,0xFF,0xC0,0x0D,0xFF,0x80, +0x1B,0xFF,0x00,0x37,0xFE,0x00,0x6F,0xFC,0x00,0xDF, +0xF8,0x01,0xBF,0xF0,0x03,0x7F,0xE0,0x06,0x7F,0xC0, +0x0D,0xFF,0xFF,0xEF,0xFF,0xFE,0x07,0x64,0x00,0x01, +0xC8,0xFF,0x00,0x00,0x03,0xFE,0x00,0x00,0x10,0xFF, +0x00,0x00,0x03,0xFE,0x00,0x00,0x24,0xFF,0x00,0x00, +0x03,0xFE,0x00,0x00,0x40,0xFF,0x00,0x00,0x03,0xFE, +0x00,0x00,0x80,0xFF,0x00,0x00,0x03,0xFE,0x00,0x01, +0x20,0xFF,0x00,0x00,0x03,0xFE,0x00,0x02,0x00,0xFF, +0x00,0x00,0x03,0xFE,0x00,0x04,0x80,0xFF,0x00,0x00, +0x03,0xFE,0x00,0x08,0x00,0xFF,0x00,0x00,0x03,0xFE, +0x00,0x12,0x00,0xFF,0x00,0x00,0x03,0xFE,0x00,0x20, +0x00,0xFF,0x00,0x00,0x03,0xFE,0x00,0x40,0x00,0xFF, +0x00,0x00,0x03,0xFE,0x00,0x90,0x00,0xFF,0x00,0x00, +0x03,0xFE,0x01,0x00,0x00,0xFF,0x00,0x00,0x03,0xFE, +0x02,0x40,0x00,0xFF,0x00,0x00,0x03,0xFE,0x04,0x00, +0x00,0xFF,0x00,0x00,0x03,0xFE,0x09,0x00,0x00,0xFF, +0x00,0x00,0x03,0xFE,0x10,0x00,0x00,0xFF,0x00,0x00, +0x03,0xFE,0x20,0x00,0x00,0xFF,0x00,0x00,0x03,0xFE, +0x48,0x00,0x00,0xFF,0x00,0x00,0x03,0xFE,0x80,0x00, +0x00,0xFF,0x00,0x00,0x03,0xFE,0x00,0x00,0x07,0xF8, +0x04,0xEE,0x0F,0x61,0xCD,0xFF,0xFF,0xEF,0xFF,0xFF, +0xA0,0x07,0xFF,0x40,0x0F,0xFE,0x80,0x1F,0xFD,0x00, +0x3F,0xFA,0x00,0x7F,0xF4,0x00,0xFF,0xE8,0x01,0xFF, +0xD0,0x03,0xFF,0xA0,0x07,0xFF,0x40,0x0F,0xFE,0x00, +0x1F,0xFD,0xFF,0xFF,0xEF,0xFF,0xFE,0x09,0xD3,0x89, +0x12,0xB0,0x00,0x07,0xF0,0x00,0x09,0x00,0x01,0xFF, +0x00,0x01,0x00,0x00,0x7F,0xF0,0x00,0x20,0x00,0x1F, +0xFF,0x00,0x00,0x00,0x3F,0xFF,0x00,0x04,0x00,0x07, +0xF7,0xF0,0x00,0x00,0x0F,0xF7,0xF8,0x00,0x00,0x0F, +0xE3,0xF8,0x00,0x80,0x03,0xFC,0x7F,0x80,0x00,0x03, +0xF8,0x3F,0x80,0x10,0x00,0xFF,0x07,0xF8,0x02,0x00, +0x3F,0xC0,0x7F,0x80,0x00,0x3F,0x80,0x3F,0x80,0x40, +0x0F,0xF0,0x07,0xF8,0x09,0x03,0xFC,0x00,0x7F,0x81, +0x00,0xFF,0x00,0x07,0xF8,0x01,0xFF,0x00,0x07,0xFC, +0x01,0xFE,0x00,0x03,0xFC,0x20,0x7F,0xC0,0x00,0x7F, +0xC0,0x7F,0x80,0x00,0x3F,0xC4,0x1F,0xF0,0x00,0x07, +0xFC,0x97,0xFC,0x00,0x00,0x7F,0xCF,0xF8,0x00,0x00, +0x3F,0xE0,0x0E,0x83,0x7F,0x63,0x8C,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xC0,0x04,0x87,0x11,0xD2,0x17, +0xFF,0x80,0x7F,0xF8,0x07,0xFF,0x00,0x7F,0xF0,0x80, +0xFF,0xC0,0x0F,0xFC,0x00,0xFF,0x88,0x01,0xFF,0x00, +0x1F,0xF0,0x01,0xFE,0x00,0x1F,0xC0,0x01,0xFC,0x0C, +0x1B,0x13,0xFB,0x80,0x00,0x01,0xFF,0xF0,0x00,0x00, +0x00,0x0F,0xFF,0xFF,0x80,0x00,0x00,0x3F,0xFF,0xFF, +0xF8,0x00,0x00,0x7F,0xFF,0xFF,0xFE,0x00,0x00,0x7F, +0xFF,0xFF,0xFF,0xC0,0x00,0xFF,0xFF,0xFF,0xFF,0xF0, +0x00,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x7F,0xFF,0xFF, +0xFF,0xFE,0x00,0x7F,0xFE,0x00,0x7F,0xFF,0x80,0x7F, +0xF8,0x00,0x07,0xFF,0xC0,0x3F,0xF8,0x00,0x01,0xFF, +0xE0,0x3F,0xF8,0x00,0x00,0x7F,0xF8,0x1F,0xF8,0x00, +0x00,0x1F,0xFC,0x0F,0xF8,0x00,0x00,0x0F,0xFE,0x0F, +0xFC,0x00,0x00,0x03,0xFF,0x07,0xFC,0x00,0x00,0x01, +0xFF,0x80,0x3E,0x00,0x00,0x00,0xFF,0xC4,0x80,0x00, +0x00,0x00,0x0F,0xFC,0x00,0x00,0x00,0x00,0x1F,0xFE, +0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x0F, +0xFF,0xFF,0x80,0x00,0x07,0xFF,0xFF,0xFF,0xC0,0x00, +0x3F,0xFF,0xFF,0xFF,0xE0,0x00,0xFF,0xFF,0xFF,0xFF, +0xF0,0x01,0xFF,0xFF,0xFF,0xFF,0xF8,0x01,0xFF,0xFF, +0xFF,0xFF,0xFC,0x01,0xFF,0xFF,0xFF,0xF7,0xFE,0x01, +0xFF,0xFF,0xFF,0x83,0xFF,0x01,0xFF,0xFF,0xF0,0x01, +0xFF,0x81,0xFF,0xFE,0x00,0x00,0xFF,0xC0,0xFF,0xF0, +0x00,0x00,0x7F,0xE0,0xFF,0xE0,0x00,0x00,0x3F,0xF0, +0x7F,0xE0,0x00,0x00,0x1F,0xF8,0x7F,0xE0,0x00,0x00, +0x0F,0xFC,0x47,0xFC,0x00,0x00,0x01,0xFF,0xC4,0x7F, +0xC0,0x00,0x00,0x3F,0xFC,0x3F,0xE0,0x00,0x00,0x3F, +0xFE,0x1F,0xF8,0x00,0x00,0x3F,0xFF,0x0F,0xFC,0x00, +0x00,0x3F,0xFF,0x83,0xFF,0x00,0x00,0x3F,0xFF,0xC1, +0xFF,0xC0,0x00,0x7F,0xFF,0xE0,0xFF,0xFC,0x01,0xFF, +0xFF,0xF0,0x3F,0xFF,0xFF,0xFF,0xEF,0xFC,0x1F,0xFF, +0xFF,0xFF,0xE7,0xFE,0x07,0xFF,0xFF,0xFF,0xE1,0xFF, +0x01,0xFF,0xFF,0xFF,0xC0,0xFF,0x80,0x7F,0xFF,0xFF, +0xC0,0x7F,0xE0,0x0F,0xFF,0xFF,0x80,0x1F,0xF0,0x01, +0xFF,0xFF,0x00,0x07,0xFC,0x00,0x1F,0xF8,0x00,0x00, +0x00,0x0B,0x64,0x9B,0xFB,0x8D,0xFF,0x80,0x00,0x00, +0x00,0x06,0xFF,0xC0,0x00,0x00,0x00,0x02,0xFF,0xE0, +0x00,0x00,0x00,0x00,0xFF,0x80,0x1F,0xF0,0x00,0x03, +0xFE,0x03,0xFF,0xF8,0x00,0x0F,0xF8,0x3F,0xFF,0xF8, +0x00,0x3F,0xE1,0xFF,0xFF,0xF8,0x00,0xFF,0x8F,0xFF, +0xFF,0xF0,0x03,0xFE,0x7F,0xFF,0xFF,0xE0,0x0F,0xFB, +0xFF,0xFF,0xFF,0xC0,0x3F,0xFF,0xFF,0xFF,0xFF,0x80, +0xFF,0xFF,0xE0,0x3F,0xFF,0x03,0xFF,0xFE,0x00,0x3F, +0xFE,0x0F,0xFF,0xE0,0x00,0x3F,0xF8,0x3F,0xFF,0x00, +0x00,0x7F,0xF0,0xFF,0xF8,0x00,0x00,0xFF,0xC3,0xFF, +0xE0,0x00,0x01,0xFF,0x8F,0xFF,0x00,0x00,0x07,0xFE, +0x3F,0xF8,0x00,0x00,0x0F,0xF8,0xFF,0xE0,0x00,0x00, +0x3F,0xF4,0xFF,0xE0,0x00,0x00,0x0F,0xF9,0xFF,0x80, +0x00,0x00,0x3F,0xFD,0xFF,0x80,0x00,0x00,0x0F,0xFD, +0xFF,0xC0,0x00,0x00,0x07,0xFD,0xFF,0x00,0x00,0x00, +0x3F,0xE9,0xFF,0xC0,0x00,0x00,0x1F,0xF3,0xFF,0x00, +0x00,0x00,0xFF,0xCF,0xFE,0x00,0x00,0x03,0xFE,0x3F, +0xF8,0x00,0x00,0x1F,0xF8,0xFF,0xF0,0x00,0x00,0xFF, +0xC3,0xFF,0xE0,0x00,0x03,0xFF,0x0F,0xFF,0xC0,0x00, +0x1F,0xF8,0x3F,0xFF,0x80,0x00,0xFF,0xE0,0xFF,0xFF, +0x00,0x0F,0xFF,0x03,0xFF,0xFF,0x80,0xFF,0xFC,0x0F, +0xFB,0xFF,0xFF,0xFF,0xE0,0x3F,0xEF,0xFF,0xFF,0xFF, +0x00,0xFF,0x9F,0xFF,0xFF,0xF8,0x03,0xFE,0x3F,0xFF, +0xFF,0xC0,0x0F,0xF8,0x7F,0xFF,0xFC,0x00,0x3F,0xE0, +0xFF,0xFF,0xE0,0x00,0xFF,0x80,0xFF,0xFE,0x00,0x00, +0x00,0x00,0x7F,0xC0,0x00,0x00,0x0B,0x5B,0x13,0xFB, +0x20,0x00,0x01,0xFF,0xC0,0x00,0x00,0x00,0x3F,0xFF, +0xE0,0x00,0x00,0x07,0xFF,0xFF,0xE0,0x00,0x00,0x3F, +0xFF,0xFF,0xE0,0x00,0x03,0xFF,0xFF,0xFF,0xC0,0x00, +0x1F,0xFF,0xFF,0xFF,0x80,0x00,0xFF,0xFF,0xFF,0xFF, +0x00,0x07,0xFF,0xFF,0xFF,0xFE,0x00,0x3F,0xFF,0x80, +0xFF,0xFC,0x01,0xFF,0xF0,0x00,0xFF,0xF0,0x07,0xFF, +0x00,0x00,0xFF,0xE0,0x3F,0xF8,0x00,0x01,0xFF,0x80, +0xFF,0xC0,0x00,0x03,0xFF,0x07,0xFE,0x00,0x00,0x0F, +0xFC,0x1F,0xF8,0x00,0x00,0x1F,0xF0,0x7F,0xC0,0x00, +0x00,0x7F,0xE3,0xFF,0x00,0x00,0x00,0xFF,0x8F,0xF8, +0x00,0x00,0x03,0xE0,0x87,0xFC,0x00,0x00,0x00,0x00, +0x3F,0xF0,0x00,0x00,0x00,0x01,0xBF,0xF0,0x00,0x00, +0x00,0x00,0xCF,0xF8,0x00,0x00,0x00,0x00,0x1F,0xF0, +0x00,0x00,0x03,0xE0,0x7F,0xC0,0x00,0x00,0x0F,0xF9, +0xFF,0x00,0x00,0x00,0x7F,0xE7,0xFE,0x00,0x00,0x01, +0xFF,0x0F,0xF8,0x00,0x00,0x07,0xFD,0x07,0xFE,0x00, +0x00,0x07,0xFE,0x0F,0xFC,0x00,0x00,0x3F,0xF0,0x3F, +0xF8,0x00,0x01,0xFF,0xC0,0x7F,0xF0,0x00,0x0F,0xFE, +0x01,0xFF,0xF0,0x00,0x7F,0xF8,0x03,0xFF,0xF0,0x0F, +0xFF,0xC0,0x07,0xFF,0xFF,0xFF,0xFE,0x00,0x0F,0xFF, +0xFF,0xFF,0xF0,0x00,0x1F,0xFF,0xFF,0xFF,0x80,0x00, +0x3F,0xFF,0xFF,0xFC,0x00,0x00,0x7F,0xFF,0xFF,0xE0, +0x00,0x00,0x7F,0xFF,0xFE,0x00,0x00,0x00,0x7F,0xFF, +0xE0,0x00,0x00,0x00,0x1F,0xF8,0x00,0x00,0x0B,0x64, +0x8F,0xFB,0x8D,0x00,0x00,0x00,0x00,0x0F,0xFE,0x80, +0x00,0x00,0x00,0x07,0xFE,0xC0,0x00,0x00,0x00,0x03, +0xFE,0x00,0x00,0x7F,0xC0,0x0F,0xF8,0x00,0x0F,0xFF, +0xE0,0x3F,0xE0,0x00,0xFF,0xFF,0xE0,0xFF,0x80,0x0F, +0xFF,0xFF,0xC3,0xFE,0x00,0x7F,0xFF,0xFF,0x8F,0xF8, +0x03,0xFF,0xFF,0xFF,0x3F,0xE0,0x1F,0xFF,0xFF,0xFE, +0xFF,0x80,0xFF,0xFF,0xFF,0xFF,0xFE,0x07,0xFF,0xE0, +0x3F,0xFF,0xF8,0x3F,0xFC,0x00,0x3F,0xFF,0xE0,0xFF, +0xE0,0x00,0x3F,0xFF,0x87,0xFF,0x00,0x00,0x7F,0xFE, +0x1F,0xF8,0x00,0x00,0xFF,0xFC,0x1F,0xF8,0x00,0x00, +0x3F,0xFC,0x7F,0xC0,0x00,0x00,0x7F,0xF3,0xFF,0x00, +0x00,0x01,0xFF,0xE5,0xFF,0x00,0x00,0x00,0x7F,0xEF, +0xFC,0x00,0x00,0x01,0xFF,0xEF,0xFC,0x00,0x00,0x00, +0x7F,0xEF,0xFE,0x00,0x00,0x00,0x3F,0xEF,0xFC,0x00, +0x00,0x00,0xFF,0xCB,0xFE,0x00,0x00,0x00,0xFF,0xCF, +0xFC,0x00,0x00,0x07,0xFF,0x1F,0xF0,0x00,0x00,0x1F, +0xFC,0x7F,0xE0,0x00,0x00,0xFF,0xF0,0xFF,0x80,0x00, +0x03,0xFF,0xC3,0xFF,0x00,0x00,0x1F,0xFF,0x0F,0xFE, +0x00,0x00,0xFF,0xFC,0x1F,0xFC,0x00,0x07,0xFF,0xF0, +0x3F,0xFC,0x00,0x7F,0xFF,0xC0,0xFF,0xFC,0x07,0xFF, +0xFF,0x01,0xFF,0xFF,0xFF,0xF7,0xFC,0x03,0xFF,0xFF, +0xFF,0xDF,0xF0,0x07,0xFF,0xFF,0xFE,0x7F,0xC0,0x0F, +0xFF,0xFF,0xF1,0xFF,0x00,0x0F,0xFF,0xFF,0x87,0xFC, +0x00,0x1F,0xFF,0xFC,0x1F,0xF0,0x00,0x1F,0xFF,0xC0, +0x7F,0xC0,0x00,0x0F,0xF8,0x00,0x00,0x0C,0x5B,0x0F, +0xFB,0x80,0x00,0x00,0xFF,0xE0,0x00,0x00,0x00,0x01, +0xFF,0xFF,0x80,0x00,0x00,0x03,0xFF,0xFF,0xF8,0x00, +0x00,0x03,0xFF,0xFF,0xFF,0x80,0x00,0x01,0xFF,0xFF, +0xFF,0xF0,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0x00,0x00, +0x7F,0xFF,0xFF,0xFF,0xE0,0x00,0x3F,0xFF,0xFF,0xFF, +0xFC,0x00,0x1F,0xFF,0x80,0x3F,0xFF,0x80,0x0F,0xFF, +0x00,0x01,0xFF,0xE0,0x07,0xFF,0x00,0x00,0x1F,0xFC, +0x01,0xFF,0x80,0x00,0x03,0xFF,0x80,0xFF,0xC0,0x00, +0x00,0x7F,0xE0,0x3F,0xE0,0x00,0x00,0x0F,0xFC,0x1F, +0xF0,0x00,0x00,0x01,0xFF,0x07,0xFC,0x00,0x00,0x00, +0x3F,0xC8,0x7F,0xC0,0x00,0x00,0x01,0xFF,0x43,0xFC, +0x00,0x00,0x00,0x07,0xF8,0xFF,0x00,0x00,0x00,0x01, +0xFF,0xDF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFB,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0x5F,0xF0,0x00,0x00,0x00,0x00, +0x07,0xFE,0x00,0x00,0x00,0x00,0x02,0x1F,0xF0,0x00, +0x00,0x00,0x00,0x07,0xFE,0x00,0x00,0x00,0x00,0x01, +0xFF,0x80,0x00,0x00,0x03,0xC0,0x3F,0xF0,0x00,0x00, +0x01,0xFF,0x8F,0xFC,0x00,0x00,0x00,0x7F,0xC3,0xFF, +0x80,0x00,0x00,0x3F,0xF0,0x7F,0xF0,0x00,0x00,0x1F, +0xF8,0x1F,0xFE,0x00,0x00,0x0F,0xFE,0x03,0xFF,0xC0, +0x00,0x07,0xFF,0x00,0x7F,0xFC,0x00,0x07,0xFF,0xC0, +0x1F,0xFF,0xE0,0x0F,0xFF,0xE0,0x03,0xFF,0xFF,0xFF, +0xFF,0xF0,0x00,0x7F,0xFF,0xFF,0xFF,0xF8,0x00,0x0F, +0xFF,0xFF,0xFF,0xFC,0x00,0x00,0xFF,0xFF,0xFF,0xFE, +0x00,0x00,0x1F,0xFF,0xFF,0xFF,0x00,0x00,0x01,0xFF, +0xFF,0xFF,0x00,0x00,0x00,0x0F,0xFF,0xFE,0x00,0x00, +0x00,0x00,0x7F,0xF8,0x00,0x00,0x07,0xE4,0x84,0x01, +0xD0,0x00,0x01,0xFF,0xC0,0x00,0x0F,0xFF,0xF0,0x00, +0x3F,0xFF,0xF0,0x00,0x7F,0xFF,0xE0,0x00,0xFF,0xFF, +0xE0,0x01,0xFF,0xFF,0xE8,0x00,0x7F,0xFF,0xFC,0x00, +0x7F,0xF8,0x04,0x00,0xFF,0xE0,0x01,0x00,0x1F,0xF8, +0x00,0x34,0x03,0xFE,0x00,0x04,0x00,0x7F,0xC0,0x00, +0xDF,0xFF,0xFF,0xFE,0x0F,0xFF,0xFF,0xFE,0x1A,0x01, +0xFF,0x00,0x03,0x40,0x3F,0xE0,0x00,0x68,0x07,0xFC, +0x00,0x0D,0x00,0xFF,0x80,0x01,0xA0,0x1F,0xF0,0x00, +0x34,0x03,0xFE,0x00,0x04,0x00,0x7F,0xC0,0x00,0x0B, +0x65,0x0F,0x5B,0x70,0x00,0x03,0xFE,0x00,0x00,0x00, +0x00,0x7F,0xFF,0x01,0xFF,0x00,0x07,0xFF,0xFE,0x07, +0xFC,0x00,0x7F,0xFF,0xFE,0x1F,0xF0,0x03,0xFF,0xFF, +0xFC,0x7F,0xC0,0x1F,0xFF,0xFF,0xF9,0xFF,0x00,0xFF, +0xFF,0xFF,0xF7,0xFC,0x07,0xFF,0xFF,0xFF,0xFF,0xF0, +0x3F,0xFF,0x01,0xFF,0xFF,0xC1,0xFF,0xF0,0x01,0xFF, +0xFF,0x07,0xFF,0x00,0x01,0xFF,0xFC,0x3F,0xF8,0x00, +0x03,0xFF,0xF0,0xFF,0xC0,0x00,0x07,0xFF,0xE0,0xFF, +0xC0,0x00,0x01,0xFF,0xE3,0xFE,0x00,0x00,0x03,0xFF, +0x9F,0xF8,0x00,0x00,0x0F,0xFF,0x2F,0xF8,0x00,0x00, +0x03,0xFF,0x7F,0xC0,0x00,0x00,0x0F,0xFF,0x7F,0xE0, +0x00,0x00,0x03,0xFF,0x5F,0xF0,0x00,0x00,0x01,0xFF, +0x7F,0xC0,0x00,0x00,0x0F,0xFE,0x5F,0xF0,0x00,0x00, +0x07,0xFE,0x7F,0xE0,0x00,0x00,0x3F,0xF8,0xFF,0x80, +0x00,0x00,0xFF,0xE3,0xFE,0x00,0x00,0x07,0xFF,0x8F, +0xFC,0x00,0x00,0x1F,0xFE,0x1F,0xF8,0x00,0x00,0xFF, +0xF8,0x7F,0xF0,0x00,0x07,0xFF,0xE0,0xFF,0xE0,0x00, +0x3F,0xFF,0x83,0xFF,0xC0,0x03,0xFF,0xFE,0x07,0xFF, +0xE0,0x3F,0xFF,0xF8,0x0F,0xFF,0xFF,0xFF,0xFF,0xE0, +0x1F,0xFF,0xFF,0xFF,0xFF,0x80,0x3F,0xFF,0xFF,0xFB, +0xFE,0x00,0x7F,0xFF,0xFF,0xCF,0xF8,0x00,0xFF,0xFF, +0xFC,0x3F,0xE0,0x01,0xFF,0xFF,0xE0,0xFF,0x80,0x00, +0xFF,0xFE,0x03,0xFE,0x00,0x00,0x7F,0xC0,0x0F,0xFC, +0x00,0x00,0x00,0x00,0x07,0xFC,0x00,0x00,0x00,0x00, +0x1F,0xE0,0x00,0x00,0x00,0x00,0xFF,0x8F,0x80,0x00, +0x00,0x03,0xFE,0x3F,0xE0,0x00,0x00,0x0F,0xF8,0xFF, +0x80,0x00,0x00,0x7F,0xE3,0xFF,0x00,0x00,0x01,0xFF, +0x0F,0xFC,0x00,0x00,0x0F,0xFC,0x1F,0xF8,0x00,0x00, +0x7F,0xF0,0x7F,0xF0,0x00,0x03,0xFF,0x81,0xFF,0xE0, +0x00,0x3F,0xFE,0x03,0xFF,0xF0,0x07,0xFF,0xF0,0x0F, +0xFF,0xFF,0xFF,0xFF,0x80,0x1F,0xFF,0xFF,0xFF,0xFC, +0x00,0x3F,0xFF,0xFF,0xFF,0xE0,0x00,0x7F,0xFF,0xFF, +0xFF,0x00,0x00,0x7F,0xFF,0xFF,0xF8,0x00,0x00,0xFF, +0xFF,0xFF,0x80,0x00,0x00,0x7F,0xFF,0xF0,0x00,0x00, +0x00,0x1F,0xFC,0x00,0x00,0x0A,0xA4,0x1C,0x03,0x8D, +0xFF,0x80,0x00,0x00,0x00,0x37,0xFE,0x00,0x00,0x00, +0x00,0xBF,0xF8,0x00,0x00,0x00,0x01,0xFF,0x00,0x1F, +0xF0,0x00,0x3F,0xE0,0x1F,0xFF,0xE0,0x07,0xFC,0x0F, +0xFF,0xFF,0x00,0xFF,0x87,0xFF,0xFF,0xF0,0x1F,0xF1, +0xFF,0xFF,0xFF,0x03,0xFE,0x7F,0xFF,0xFF,0xF0,0x7F, +0xDF,0xFF,0xFF,0xFF,0x0F,0xFF,0xFF,0xFF,0xFF,0xF1, +0xFF,0xFF,0xC0,0x7F,0xFE,0x3F,0xFF,0xC0,0x03,0xFF, +0xE7,0xFF,0xE0,0x00,0x1F,0xFC,0xFF,0xF8,0x00,0x01, +0xFF,0x9F,0xFE,0x00,0x00,0x3F,0xF4,0x7F,0xF0,0x00, +0x00,0x7F,0xEF,0xFC,0x00,0x00,0x0F,0xFE,0x7F,0xF0, +0x00,0x00,0x1F,0xFD,0xFF,0x80,0x00,0x00,0x7F,0xF7, +0xFE,0x00,0x00,0x01,0xFF,0xDF,0xF8,0x00,0x00,0x07, +0xFF,0x7F,0xE0,0x00,0x00,0x1F,0xFC,0xFF,0x80,0x00, +0x00,0x7F,0xC0,0x02,0x64,0x1C,0x01,0x6D,0xFF,0xC7, +0xFF,0x40,0x14,0x00,0xDF,0xFE,0xFF,0xF7,0xFF,0xBF, +0xFD,0xFF,0xEF,0xFF,0x7F,0xF3,0xFF,0x04,0xEE,0xF3, +0x59,0x6D,0x00,0x3F,0xF0,0x00,0x7F,0xF4,0x00,0x00, +0x50,0x00,0x00,0xD0,0x03,0xFF,0xA0,0x07,0xFF,0x40, +0x0F,0xFE,0x80,0x1F,0xFD,0x00,0x3F,0xFA,0x00,0x7F, +0xF4,0x00,0xFF,0xE8,0x01,0xFF,0xB0,0x03,0xFE,0x00, +0x7F,0xF0,0x00,0xFF,0x88,0x3F,0xF8,0xFF,0xFF,0x8F, +0xFF,0xF1,0xFF,0xFF,0x1F,0xFF,0xE1,0xFF,0xFC,0x1F, +0xFF,0x81,0xFF,0xF0,0x0F,0xF8,0x00,0x0A,0xE4,0x18, +0x03,0x2D,0xFF,0x80,0x00,0x00,0x00,0x1B,0xFF,0x00, +0x00,0x00,0x00,0x33,0xFE,0x00,0x00,0x00,0x00,0x3F, +0xE0,0x00,0x01,0xFF,0xE3,0xFE,0x00,0x00,0x3F,0xFC, +0x3F,0xE0,0x00,0x07,0xFF,0x83,0xFE,0x00,0x00,0xFF, +0xF0,0x3F,0xE0,0x00,0x1F,0xFE,0x03,0xFE,0x00,0x03, +0xFF,0xC0,0x3F,0xE0,0x00,0x7F,0xF8,0x03,0xFE,0x00, +0x0F,0xFF,0x00,0x3F,0xE0,0x01,0xFF,0xE0,0x03,0xFE, +0x00,0x3F,0xFC,0x00,0x3F,0xE0,0x07,0xFF,0x80,0x03, +0xFE,0x00,0xFF,0xF0,0x00,0x3F,0xE0,0x3F,0xFE,0x00, +0x03,0xFE,0x07,0xFF,0xC0,0x00,0x3F,0xE0,0xFF,0xF8, +0x00,0x03,0xFE,0x1F,0xFF,0x00,0x00,0x3F,0xE3,0xFF, +0xE0,0x00,0x03,0xFE,0x7F,0xFC,0x00,0x00,0x3F,0xEF, +0xFF,0x80,0x00,0x03,0xFF,0xFF,0xF0,0x00,0x00,0x47, +0xFF,0xFF,0xF0,0x00,0x00,0x7F,0xFF,0xFF,0x80,0x00, +0x08,0xFF,0xFF,0xFF,0x80,0x00,0x0F,0xFF,0xFF,0xFC, +0x00,0x00,0xFF,0xFE,0xFF,0xC0,0x00,0x0F,0xFF,0x87, +0xFE,0x00,0x00,0xFF,0xF0,0x7F,0xF0,0x00,0x0F,0xFE, +0x03,0xFF,0x00,0x00,0xFF,0xC0,0x1F,0xF8,0x00,0x0F, +0xF8,0x01,0xFF,0xC0,0x00,0xFF,0x80,0x0F,0xFC,0x00, +0x0F,0xF8,0x00,0xFF,0xE0,0x00,0xFF,0x80,0x07,0xFF, +0x00,0x0F,0xF8,0x00,0x3F,0xF0,0x00,0xFF,0x80,0x03, +0xFF,0x80,0x0F,0xF8,0x00,0x1F,0xFC,0x00,0xFF,0x80, +0x00,0xFF,0xC0,0x0F,0xF8,0x00,0x0F,0xFE,0x00,0xFF, +0x80,0x00,0x7F,0xF0,0x0F,0xF8,0x00,0x03,0xFF,0x00, +0xFF,0x80,0x00,0x3F,0xF8,0x0F,0xF8,0x00,0x01,0xFF, +0x80,0xFF,0x80,0x00,0x0F,0xFC,0x0F,0xF8,0x00,0x00, +0xFF,0xE0,0xFF,0x80,0x00,0x07,0xFE,0x0F,0xF8,0x00, +0x00,0x3F,0xF0,0xFF,0x80,0x00,0x03,0xFF,0x8F,0xF8, +0x00,0x00,0x1F,0xF8,0xFF,0x80,0x00,0x01,0xFF,0xCF, +0xF8,0x00,0x00,0x0F,0xFE,0x02,0x64,0x1C,0x01,0x6D, +0xFF,0xEF,0xFF,0x7F,0xFB,0xFF,0xDF,0xFE,0xFF,0xF7, +0xFF,0xBF,0xFD,0xFF,0xEF,0xFE,0x3F,0xE0,0x11,0xDA, +0x98,0x05,0x40,0x00,0x00,0x7F,0xC0,0x00,0x00,0xFF, +0x80,0x07,0xFC,0x03,0xFF,0xF8,0x00,0x0F,0xFF,0xF0, +0x07,0xFC,0x0F,0xFF,0xFE,0x00,0x1F,0xFF,0xFC,0x07, +0xFC,0x1F,0xFF,0xFF,0x00,0x7F,0xFF,0xFE,0x07,0xFC, +0x3F,0xFF,0xFF,0x80,0xFF,0xFF,0xFF,0x07,0xFC,0x7F, +0xFF,0xFF,0xC1,0xFF,0xFF,0xFF,0x87,0xFC,0xFF,0xFF, +0xFF,0xC3,0xFF,0xFF,0xFF,0x87,0xFD,0xFF,0xFF,0xFF, +0xE7,0xFF,0xFF,0xFF,0xC7,0xFF,0xFE,0x03,0xFF,0xEF, +0xFC,0x07,0xFF,0xC7,0xFF,0xF8,0x00,0xFF,0xFF,0xE0, +0x01,0xFF,0xE7,0xFF,0xE0,0x00,0x7F,0xFF,0xC0,0x00, +0xFF,0xE7,0xFF,0xC0,0x00,0x3F,0xFF,0x80,0x00,0x7F, +0xE7,0xFF,0x80,0x00,0x1F,0xFF,0x00,0x00,0x3F,0xF7, +0xFF,0x00,0x00,0x1F,0xFE,0x00,0x00,0x3F,0xF7,0xFF, +0x00,0x00,0x1F,0xFE,0x00,0x00,0x1F,0xF9,0xFF,0xC0, +0x00,0x01,0xFF,0x80,0x00,0x03,0xFE,0xFF,0xC0,0x00, +0x01,0xFF,0x00,0x00,0x03,0xFF,0xBF,0xF0,0x00,0x00, +0x3F,0xE0,0x00,0x00,0x7F,0xF7,0xFE,0x00,0x00,0x07, +0xFC,0x00,0x00,0x0F,0xFE,0xFF,0xC0,0x00,0x00,0xFF, +0x80,0x00,0x01,0xFF,0xDF,0xF8,0x00,0x00,0x1F,0xF0, +0x00,0x00,0x3F,0xF9,0xFF,0x00,0x00,0x03,0xFE,0x00, +0x00,0x07,0xFC,0x0A,0x9A,0x9C,0x03,0x80,0x00,0x00, +0x7F,0xE0,0x00,0xFF,0x80,0x7F,0xFF,0x80,0x1F,0xF0, +0x3F,0xFF,0xFC,0x03,0xFE,0x1F,0xFF,0xFF,0xC0,0x7F, +0xC7,0xFF,0xFF,0xFC,0x0F,0xF9,0xFF,0xFF,0xFF,0xC1, +0xFF,0x7F,0xFF,0xFF,0xFC,0x3F,0xEF,0xFF,0xFF,0xFF, +0xC7,0xFF,0xFF,0x01,0xFF,0xF8,0xFF,0xFF,0x00,0x0F, +0xFF,0x9F,0xFF,0x80,0x00,0x7F,0xF3,0xFF,0xE0,0x00, +0x07,0xFE,0x7F,0xF8,0x00,0x00,0xFF,0xF1,0xFF,0xC0, +0x00,0x01,0xFF,0xBF,0xF0,0x00,0x00,0x3F,0xF9,0xFF, +0xC0,0x00,0x00,0x7F,0xF7,0xFE,0x00,0x00,0x01,0xFF, +0xDF,0xF8,0x00,0x00,0x07,0xFF,0x7F,0xE0,0x00,0x00, +0x1F,0xFD,0xFF,0x80,0x00,0x00,0x7F,0xF3,0xFE,0x00, +0x00,0x01,0xFF,0x0C,0x1B,0x13,0xFB,0x80,0x00,0x00, +0xFF,0xC0,0x00,0x00,0x00,0x07,0xFF,0xFE,0x00,0x00, +0x00,0x0F,0xFF,0xFF,0xC0,0x00,0x00,0x1F,0xFF,0xFF, +0xF8,0x00,0x00,0x3F,0xFF,0xFF,0xFE,0x00,0x00,0x3F, +0xFF,0xFF,0xFF,0xC0,0x00,0x3F,0xFF,0xFF,0xFF,0xF0, +0x00,0x3F,0xFF,0xFF,0xFF,0xFC,0x00,0x3F,0xFF,0x80, +0x7F,0xFF,0x00,0x1F,0xFE,0x00,0x0F,0xFF,0x80,0x1F, +0xFE,0x00,0x01,0xFF,0xE0,0x1F,0xFE,0x00,0x00,0x7F, +0xF8,0x0F,0xFC,0x00,0x00,0x1F,0xFC,0x0F,0xFE,0x00, +0x00,0x07,0xFF,0x07,0xFE,0x00,0x00,0x01,0xFF,0x83, +0xFE,0x00,0x00,0x00,0x7F,0xC3,0xFF,0x00,0x00,0x00, +0x3F,0xF4,0xBF,0xE0,0x00,0x00,0x01,0xFF,0x3F,0xF0, +0x00,0x00,0x00,0xFF,0xF7,0xFE,0x00,0x00,0x00,0x07, +0xFE,0xBF,0xE0,0x00,0x00,0x00,0x7F,0xDF,0xF0,0x00, +0x00,0x00,0x7F,0xEF,0xFC,0x00,0x00,0x00,0x3F,0xF8, +0x7F,0xC0,0x00,0x00,0x03,0xFE,0x3F,0xE0,0x00,0x00, +0x03,0xFF,0x1F,0xF8,0x00,0x00,0x01,0xFF,0x87,0xFC, +0x00,0x00,0x00,0xFF,0x83,0xFF,0x00,0x00,0x00,0xFF, +0xC1,0xFF,0xC0,0x00,0x00,0xFF,0xE0,0x7F,0xE0,0x00, +0x00,0xFF,0xE0,0x3F,0xF8,0x00,0x00,0xFF,0xF0,0x0F, +0xFF,0x00,0x00,0xFF,0xF0,0x03,0xFF,0xC0,0x00,0xFF, +0xF0,0x01,0xFF,0xFC,0x03,0xFF,0xF8,0x00,0x7F,0xFF, +0xFF,0xFF,0xF8,0x00,0x1F,0xFF,0xFF,0xFF,0xF8,0x00, +0x07,0xFF,0xFF,0xFF,0xF8,0x00,0x01,0xFF,0xFF,0xFF, +0xF8,0x00,0x00,0x3F,0xFF,0xFF,0xF0,0x00,0x00,0x07, +0xFF,0xFF,0xE0,0x00,0x00,0x00,0xFF,0xFF,0xC0,0x00, +0x00,0x00,0x07,0xFE,0x00,0x00,0x00,0x0B,0x64,0x9B, +0x63,0x80,0x00,0x00,0xFF,0x80,0x00,0x1F,0xF0,0x0F, +0xFF,0xC0,0x00,0x7F,0xC0,0xFF,0xFF,0xE0,0x01,0xFF, +0x07,0xFF,0xFF,0xC0,0x07,0xFC,0x7F,0xFF,0xFF,0x80, +0x1F,0xF1,0xFF,0xFF,0xFF,0x80,0x7F,0xCF,0xFF,0xFF, +0xFE,0x01,0xFF,0x7F,0xFF,0xFF,0xFC,0x07,0xFF,0xFF, +0x01,0xFF,0xF8,0x1F,0xFF,0xF0,0x01,0xFF,0xF0,0x7F, +0xFF,0x80,0x01,0xFF,0xC1,0xFF,0xFC,0x00,0x03,0xFF, +0x87,0xFF,0xE0,0x00,0x07,0xFE,0x1F,0xFF,0x00,0x00, +0x0F,0xFC,0x7F,0xF8,0x00,0x00,0x3F,0xF1,0xFF,0xC0, +0x00,0x00,0x7F,0xC7,0xFF,0x00,0x00,0x01,0xFF,0x9F, +0xFC,0x00,0x00,0x03,0xFE,0x8F,0xFC,0x00,0x00,0x01, +0xFF,0x3F,0xF0,0x00,0x00,0x07,0xFF,0xBF,0xF0,0x00, +0x00,0x01,0xFF,0xBF,0xF8,0x00,0x00,0x00,0xFF,0xBF, +0xE0,0x00,0x00,0x07,0xFD,0x3F,0xF8,0x00,0x00,0x03, +0xFE,0x8F,0xFE,0x00,0x00,0x03,0xFE,0x3F,0xF8,0x00, +0x00,0x1F,0xF8,0xFF,0xF0,0x00,0x00,0x7F,0xC3,0xFF, +0xE0,0x00,0x03,0xFF,0x0F,0xFF,0xC0,0x00,0x1F,0xF8, +0x3F,0xFF,0x80,0x00,0xFF,0xE0,0xFF,0xFF,0x00,0x0F, +0xFF,0x03,0xFF,0xFF,0x80,0xFF,0xF8,0x0F,0xFF,0xFF, +0xFF,0xFF,0xE0,0x3F,0xEF,0xFF,0xFF,0xFF,0x00,0xFF, +0xBF,0xFF,0xFF,0xF8,0x03,0xFE,0x7F,0xFF,0xFF,0xC0, +0x0F,0xF8,0x7F,0xFF,0xFC,0x00,0x3F,0xE0,0xFF,0xFF, +0xC0,0x00,0xFF,0x80,0xFF,0xFC,0x00,0x03,0xFE,0x00, +0xFF,0x80,0x00,0x1B,0xFF,0x00,0x00,0x00,0x00,0x0D, +0xFF,0x80,0x00,0x00,0x00,0x05,0xFF,0xC0,0x00,0x00, +0x00,0x00,0x0B,0x64,0x8F,0x63,0x70,0x00,0x03,0xFC, +0x00,0x00,0x00,0x00,0x7F,0xFE,0x01,0xFF,0x00,0x0F, +0xFF,0xFE,0x07,0xFC,0x00,0x7F,0xFF,0xFC,0x1F,0xF0, +0x07,0xFF,0xFF,0xF8,0x7F,0xC0,0x3F,0xFF,0xFF,0xF1, +0xFF,0x01,0xFF,0xFF,0xFF,0xE7,0xFC,0x07,0xFF,0xFF, +0xFF,0xDF,0xF0,0x3F,0xFF,0x03,0xFF,0xFF,0xC1,0xFF, +0xE0,0x01,0xFF,0xFF,0x07,0xFF,0x00,0x03,0xFF,0xFC, +0x3F,0xF8,0x00,0x07,0xFF,0xF0,0xFF,0xC0,0x00,0x0F, +0xFF,0xC7,0xFE,0x00,0x00,0x1F,0xFF,0x1F,0xF8,0x00, +0x00,0x3F,0xFC,0x7F,0xC0,0x00,0x00,0x7F,0xF3,0xFF, +0x00,0x00,0x01,0xFF,0xCF,0xF8,0x00,0x00,0x07,0xFF, +0x87,0xFC,0x00,0x00,0x01,0xFF,0xBF,0xF0,0x00,0x00, +0x07,0xFE,0xFF,0x80,0x00,0x00,0x1F,0xFE,0xFF,0xC0, +0x00,0x00,0x07,0xFE,0xBF,0xE0,0x00,0x00,0x03,0xFE, +0x7F,0xC0,0x00,0x00,0x0F,0xFC,0xBF,0xE0,0x00,0x00, +0x0F,0xFC,0xFF,0xC0,0x00,0x00,0x7F,0xF1,0xFF,0x00, +0x00,0x01,0xFF,0xC7,0xFE,0x00,0x00,0x0F,0xFF,0x0F, +0xF8,0x00,0x00,0x3F,0xFC,0x3F,0xF0,0x00,0x01,0xFF, +0xF0,0x7F,0xE0,0x00,0x0F,0xFF,0xC1,0xFF,0xC0,0x00, +0x7F,0xFF,0x03,0xFF,0xC0,0x07,0xFF,0xFC,0x07,0xFF, +0xC0,0x7F,0xFF,0xF0,0x1F,0xFF,0xFF,0xFF,0xFF,0xC0, +0x3F,0xFF,0xFF,0xFD,0xFF,0x00,0x7F,0xFF,0xFF,0xF7, +0xFC,0x00,0x7F,0xFF,0xFF,0x9F,0xF0,0x00,0xFF,0xFF, +0xF8,0x7F,0xC0,0x00,0xFF,0xFF,0xC1,0xFF,0x00,0x00, +0xFF,0xFC,0x07,0xFC,0x00,0x00,0x7F,0x80,0x1F,0xFD, +0x00,0x00,0x00,0x00,0x0F,0xFE,0x80,0x00,0x00,0x00, +0x07,0xFE,0xC0,0x00,0x00,0x00,0x03,0xFE,0x06,0xDA, +0x9C,0x02,0x10,0x00,0x0F,0xE0,0x7F,0x83,0xFF,0xC7, +0xF8,0x7F,0xFF,0x7F,0x8F,0xFF,0xF8,0xFF,0x3F,0xFF, +0xCF,0xF7,0xFF,0xFC,0xFF,0xFF,0xFF,0x8F,0xFF,0xF0, +0x78,0xFF,0xFC,0x01,0x0F,0xFF,0x80,0x00,0xFF,0xF0, +0x00,0x11,0xFF,0xC0,0x00,0x2F,0xFF,0x00,0x00,0x6F, +0xFC,0x00,0x00,0xDF,0xF8,0x00,0x01,0xBF,0xF0,0x00, +0x03,0x7F,0xE0,0x00,0x06,0x7F,0xC0,0x00,0x00,0x0A, +0xDB,0x0F,0xFB,0x20,0x00,0x0F,0xFE,0x00,0x00,0x00, +0x0F,0xFF,0xFC,0x00,0x00,0x03,0xFF,0xFF,0xF8,0x00, +0x00,0xFF,0xFF,0xFF,0xE0,0x00,0x1F,0xFF,0xFF,0xFF, +0x00,0x03,0xFF,0xFF,0xFF,0xF8,0x00,0x7F,0xFF,0xFF, +0xFF,0xC0,0x0F,0xFF,0xFF,0xFF,0xFC,0x00,0xFF,0xF8, +0x03,0xFF,0xE0,0x1F,0xFC,0x00,0x0F,0xFE,0x01,0xFF, +0x80,0x00,0x7F,0xF0,0x3F,0xF0,0x00,0x03,0xFF,0x03, +0xFE,0x00,0x00,0x1F,0xF0,0x3F,0xE0,0x00,0x01,0xFF, +0x83,0xFE,0x00,0x00,0x0F,0xF8,0x3F,0xE0,0x00,0x00, +0xF8,0x03,0xFF,0x00,0x00,0x00,0x00,0x3F,0xF8,0x00, +0x00,0x00,0x03,0xFF,0xC0,0x00,0x00,0x00,0x1F,0xFF, +0x00,0x00,0x00,0x01,0xFF,0xFF,0x00,0x00,0x00,0x0F, +0xFF,0xFF,0x00,0x00,0x00,0xFF,0xFF,0xFE,0x00,0x00, +0x07,0xFF,0xFF,0xFC,0x00,0x00,0x3F,0xFF,0xFF,0xF8, +0x00,0x01,0xFF,0xFF,0xFF,0xF0,0x00,0x07,0xFF,0xFF, +0xFF,0xC0,0x00,0x1F,0xFF,0xFF,0xFE,0x00,0x00,0x7F, +0xFF,0xFF,0xF0,0x00,0x00,0xFF,0xFF,0xFF,0x80,0x00, +0x00,0xFF,0xFF,0xFC,0x00,0x00,0x01,0xFF,0xFF,0xE0, +0x00,0x00,0x01,0xFF,0xFE,0x00,0x00,0x00,0x03,0xFF, +0xE0,0x00,0x00,0x00,0x0F,0xFF,0x00,0x00,0x00,0x00, +0x3F,0xF0,0x7C,0x00,0x00,0x03,0xFF,0x7F,0xC0,0x00, +0x00,0x1F,0xF7,0xFE,0x00,0x00,0x01,0xFF,0x87,0xFC, +0x00,0x00,0x03,0xFE,0x7F,0xE0,0x00,0x00,0x7F,0xC3, +0xFF,0x00,0x00,0x0F,0xFC,0x3F,0xF8,0x00,0x01,0xFF, +0xC3,0xFF,0xE0,0x00,0x3F,0xF8,0x1F,0xFF,0xC0,0x1F, +0xFF,0x80,0xFF,0xFF,0xFF,0xFF,0xF0,0x0F,0xFF,0xFF, +0xFF,0xFE,0x00,0x7F,0xFF,0xFF,0xFF,0xC0,0x03,0xFF, +0xFF,0xFF,0xF8,0x00,0x0F,0xFF,0xFF,0xFF,0x00,0x00, +0x7F,0xFF,0xFF,0xC0,0x00,0x00,0xFF,0xFF,0xE0,0x00, +0x00,0x00,0xFF,0xF0,0x00,0x00,0x06,0xA3,0x87,0xF9, +0xC0,0x00,0x08,0x00,0x00,0x07,0x00,0x00,0x01,0xE0, +0x00,0x00,0xFC,0x00,0x00,0x7F,0x80,0x1A,0x03,0xFE, +0x00,0x60,0x0F,0xF8,0x01,0xBF,0xFF,0xFF,0xF3,0xFF, +0xFF,0xFE,0xD0,0x1F,0xF0,0x03,0x40,0x7F,0xC0,0x0D, +0x01,0xFF,0x00,0x34,0x07,0xFC,0x00,0xD0,0x1F,0xF0, +0x00,0x03,0xFF,0x00,0x00,0x7F,0xF0,0x00,0x0F,0xFF, +0xFD,0x00,0x1F,0xFF,0xF4,0x00,0x3F,0xFF,0xE0,0x03, +0xFF,0xFC,0x00,0x1F,0xFF,0x80,0x00,0x7F,0xE0,0x0A, +0x9A,0x9F,0xFB,0x8D,0xFF,0x80,0x00,0x00,0x7F,0xF7, +0xFE,0x00,0x00,0x01,0xFF,0xDF,0xF8,0x00,0x00,0x07, +0xFF,0x7F,0xE0,0x00,0x00,0x1F,0xFC,0xFF,0x80,0x00, +0x00,0x7F,0xEB,0xFE,0x00,0x00,0x03,0xFF,0x8F,0xFC, +0x00,0x00,0x1F,0xFC,0xFF,0xC0,0x00,0x07,0xFF,0x9F, +0xF8,0x00,0x01,0xFF,0xF3,0xFF,0x80,0x00,0x7F,0xFE, +0x7F,0xFC,0x00,0x3F,0xFF,0xC7,0xFF,0xE0,0x3F,0xFF, +0xF8,0xFF,0xFF,0xFF,0xFD,0xFF,0x0F,0xFF,0xFF,0xFF, +0x3F,0xE0,0xFF,0xFF,0xFF,0xC7,0xFC,0x0F,0xFF,0xFF, +0xF0,0xFF,0x80,0xFF,0xFF,0xFC,0x1F,0xF0,0x0F,0xFF, +0xFE,0x03,0xFE,0x00,0x7F,0xFF,0x80,0x7F,0xC0,0x00, +0xFF,0x80,0x00,0x00,0x0B,0xDA,0x04,0x03,0x17,0xFE, +0x00,0x00,0x00,0x3F,0xF3,0xFE,0x00,0x00,0x00,0x3F, +0xF3,0xFE,0x00,0x00,0x00,0x3F,0xE3,0xFF,0x00,0x00, +0x00,0x7F,0xE8,0x3F,0xE0,0x00,0x00,0x0F,0xF8,0x3F, +0xF0,0x00,0x00,0x1F,0xF9,0x03,0xFE,0x00,0x00,0x03, +0xFE,0x03,0xFF,0x00,0x00,0x07,0xFE,0x20,0x3F,0xE0, +0x00,0x00,0xFF,0x80,0x1F,0xF0,0x00,0x01,0xFF,0x80, +0x1F,0xF0,0x00,0x01,0xFF,0x00,0x1F,0xF8,0x00,0x01, +0xFF,0x00,0x0F,0xF8,0x00,0x03,0xFF,0x00,0x0F,0xF8, +0x00,0x03,0xFE,0x00,0x0F,0xFC,0x00,0x03,0xFE,0x00, +0x07,0xFC,0x00,0x07,0xFE,0x00,0x07,0xFC,0x00,0x07, +0xFC,0x00,0x07,0xFE,0x00,0x07,0xFC,0x00,0x03,0xFE, +0x00,0x0F,0xFC,0x00,0x03,0xFE,0x00,0x0F,0xF8,0x04, +0x00,0x3F,0xE0,0x03,0xFF,0x00,0x00,0x3F,0xE0,0x03, +0xFE,0x00,0x80,0x03,0xFE,0x00,0xFF,0xC0,0x00,0x03, +0xFE,0x00,0xFF,0x80,0x10,0x00,0x3F,0xE0,0x3F,0xF0, +0x00,0x00,0x3F,0xE0,0x3F,0xE0,0x02,0x00,0x03,0xFE, +0x0F,0xFC,0x00,0x00,0x01,0xFE,0x0F,0xF8,0x00,0x40, +0x00,0x3F,0xE3,0xFF,0x00,0x00,0x00,0x1F,0xE3,0xFE, +0x00,0x08,0x00,0x03,0xFE,0xFF,0xC0,0x01,0x00,0x00, +0x3F,0xDF,0xF0,0x00,0x00,0x00,0x3F,0xFF,0xF0,0x00, +0x20,0x00,0x03,0xFF,0xFC,0x00,0x00,0x00,0x01,0xFF, +0xFC,0x00,0x04,0x00,0x00,0x3F,0xFF,0x00,0x00,0x00, +0x00,0x1F,0xFF,0x00,0x00,0x80,0x00,0x03,0xFF,0xC0, +0x00,0x00,0x00,0x01,0xFF,0xC0,0x00,0x00,0x11,0xDA, +0x00,0x04,0x78,0xFF,0x80,0x00,0x01,0xFF,0x00,0x00, +0x03,0xFE,0xFF,0xC0,0x00,0x01,0xFF,0x80,0x00,0x07, +0xFF,0x0F,0xF8,0x00,0x00,0x7F,0xF0,0x00,0x00,0xFF, +0x8F,0xF8,0x00,0x00,0x7F,0xF0,0x00,0x01,0xFF,0x8F, +0xFC,0x00,0x00,0xFF,0xF8,0x00,0x01,0xFF,0xA0,0xFF, +0x80,0x00,0x1F,0xFF,0x00,0x00,0x3F,0xE0,0xFF,0xC0, +0x00,0x1F,0xFF,0x80,0x00,0x7F,0xE4,0x0F,0xF8,0x00, +0x07,0xFF,0xF0,0x00,0x0F,0xF8,0x0F,0xFC,0x00,0x07, +0xF7,0xF0,0x00,0x1F,0xF8,0x07,0xFC,0x00,0x07,0xF7, +0xF8,0x00,0x1F,0xF0,0x80,0xFF,0x80,0x01,0xFE,0xFF, +0x00,0x03,0xFE,0x00,0xFF,0xC0,0x01,0xFC,0x7F,0x00, +0x07,0xFE,0x10,0x0F,0xF8,0x00,0x7F,0x8F,0xF0,0x00, +0xFF,0x80,0x0F,0xFC,0x00,0x7F,0x8F,0xF0,0x01,0xFF, +0x80,0x07,0xFC,0x00,0x7F,0x07,0xF0,0x01,0xFF,0x00, +0x07,0xFC,0x00,0xFF,0x07,0xF8,0x01,0xFF,0x00,0x07, +0xFC,0x00,0xFF,0x07,0xF8,0x03,0xFF,0x00,0x03,0xFE, +0x00,0xFF,0x07,0xF8,0x03,0xFE,0x00,0x03,0xFE,0x00, +0xFE,0x03,0xFC,0x03,0xFE,0x00,0x03,0xFE,0x01,0xFE, +0x03,0xFC,0x03,0xFE,0x00,0x03,0xFF,0x01,0xFE,0x03, +0xFC,0x07,0xFE,0x00,0x01,0xFF,0x01,0xFC,0x03,0xFC, +0x07,0xFC,0x00,0x01,0xFF,0x03,0xFC,0x01,0xFE,0x07, +0xFC,0x00,0x01,0xFF,0x03,0xFC,0x01,0xFE,0x0F,0xFC, +0x00,0x00,0xFF,0x83,0xFC,0x01,0xFE,0x0F,0xF8,0x00, +0x00,0xFF,0x83,0xF8,0x01,0xFE,0x0F,0xF8,0x00,0x00, +0xFF,0x87,0xF8,0x00,0xFF,0x0F,0xF8,0x00,0x00,0x7F, +0x87,0xF8,0x00,0xFF,0x1F,0xF0,0x00,0x00,0x7F,0xC7, +0xF8,0x00,0xFF,0x1F,0xF0,0x00,0x00,0x7F,0xC7,0xF0, +0x00,0xFF,0x1F,0xF0,0x00,0x00,0x7F,0xCF,0xF0,0x00, +0x7F,0xBF,0xF0,0x00,0x00,0x3F,0xCF,0xF0,0x00,0x7F, +0xBF,0xE0,0x00,0x00,0x3F,0xEF,0xF0,0x00,0x7F,0xBF, +0xE0,0x00,0x00,0x3F,0xEF,0xE0,0x00,0x3F,0xBF,0xE0, +0x02,0x40,0x03,0xFF,0xFC,0x00,0x07,0xFF,0xF8,0x00, +0x48,0x00,0x3F,0xFF,0x00,0x00,0x7F,0xFE,0x00,0x00, +0x00,0x3F,0xFF,0x00,0x00,0x7F,0xFC,0x00,0x09,0x00, +0x03,0xFF,0xC0,0x00,0x07,0xFF,0x80,0x00,0x00,0x01, +0xFF,0xC0,0x00,0x07,0xFF,0x00,0x00,0x00,0x01,0xFF, +0x80,0x00,0x03,0xFF,0x00,0x00,0x0B,0xDA,0x04,0x03, +0x13,0xFF,0x80,0x00,0x00,0x3F,0xF1,0xFF,0xC0,0x00, +0x00,0x7F,0xF0,0xFF,0xE0,0x00,0x00,0xFF,0xE0,0xFF, +0xE0,0x00,0x01,0xFF,0xC0,0x7F,0xF0,0x00,0x01,0xFF, +0xC0,0x3F,0xF8,0x00,0x03,0xFF,0x80,0x3F,0xF8,0x00, +0x07,0xFF,0x00,0x1F,0xFC,0x00,0x07,0xFF,0x00,0x0F, +0xFE,0x00,0x0F,0xFE,0x00,0x0F,0xFE,0x00,0x1F,0xFC, +0x00,0x07,0xFF,0x00,0x1F,0xF8,0x00,0x03,0xFF,0x80, +0x3F,0xF8,0x00,0x03,0xFF,0x80,0x7F,0xF0,0x00,0x01, +0xFF,0xC0,0xFF,0xE0,0x00,0x00,0xFF,0xE0,0xFF,0xE0, +0x00,0x00,0xFF,0xE1,0xFF,0xC0,0x00,0x00,0x7F,0xF3, +0xFF,0x80,0x00,0x00,0x3F,0xFB,0xFF,0x00,0x00,0x00, +0x1F,0xFF,0xFF,0x00,0x00,0x00,0x1F,0xFF,0xFE,0x00, +0x00,0x00,0x0F,0xFF,0xFC,0x00,0x00,0x00,0x07,0xFF, +0xFC,0x00,0x00,0x00,0x07,0xFF,0xF8,0x00,0x00,0x00, +0x03,0xFF,0xF0,0x00,0x09,0x00,0x00,0x3F,0xFC,0x00, +0x00,0x00,0x00,0x7F,0xFC,0x00,0x00,0x00,0x00,0x7F, +0xFE,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00, +0x01,0xFF,0xFF,0x00,0x00,0x00,0x01,0xFF,0xFF,0x80, +0x00,0x00,0x03,0xFF,0xFF,0xC0,0x00,0x00,0x07,0xFF, +0xFF,0xC0,0x00,0x00,0x0F,0xFE,0xFF,0xE0,0x00,0x00, +0x0F,0xFE,0x7F,0xF0,0x00,0x00,0x1F,0xFC,0x3F,0xF8, +0x00,0x00,0x3F,0xF8,0x3F,0xF8,0x00,0x00,0x3F,0xF0, +0x1F,0xFC,0x00,0x00,0x7F,0xF0,0x0F,0xFE,0x00,0x00, +0xFF,0xE0,0x0F,0xFE,0x00,0x01,0xFF,0xC0,0x07,0xFF, +0x00,0x01,0xFF,0xC0,0x03,0xFF,0x80,0x03,0xFF,0x80, +0x03,0xFF,0x80,0x07,0xFF,0x00,0x01,0xFF,0xC0,0x07, +0xFE,0x00,0x00,0xFF,0xE0,0x0F,0xFE,0x00,0x00,0xFF, +0xE0,0x1F,0xFC,0x00,0x00,0x7F,0xF1,0x07,0xFF,0x00, +0x00,0x07,0xFF,0x0F,0xFE,0x00,0x00,0x03,0xFF,0x9F, +0xFC,0x00,0x00,0x01,0xFF,0xC0,0x0B,0xE4,0x87,0x5B, +0x17,0xFE,0x00,0x00,0x00,0x1F,0xF8,0x7F,0xC0,0x00, +0x00,0x07,0xFE,0x7F,0xE0,0x00,0x00,0x07,0xFD,0x07, +0xFC,0x00,0x00,0x01,0xFF,0x87,0xFE,0x00,0x00,0x01, +0xFF,0x03,0xFE,0x00,0x00,0x03,0xFF,0x20,0x7F,0xE0, +0x00,0x00,0x7F,0xC0,0x3F,0xE0,0x00,0x00,0xFF,0xC0, +0x3F,0xF0,0x00,0x00,0xFF,0x84,0x03,0xFE,0x00,0x00, +0x3F,0xF0,0x03,0xFF,0x00,0x00,0x3F,0xE0,0x80,0x3F, +0xE0,0x00,0x0F,0xFC,0x00,0x3F,0xF0,0x00,0x0F,0xF8, +0x00,0x1F,0xF0,0x00,0x1F,0xF8,0x00,0x1F,0xF0,0x00, +0x1F,0xF0,0x00,0x1F,0xF8,0x00,0x1F,0xF0,0x00,0x0F, +0xF8,0x00,0x3F,0xF0,0x00,0x0F,0xF8,0x00,0x3F,0xE0, +0x10,0x00,0xFF,0x80,0x0F,0xFC,0x00,0x00,0xFF,0x80, +0x0F,0xF8,0x00,0x00,0x7F,0xC0,0x1F,0xF8,0x00,0x00, +0x7F,0xC0,0x1F,0xF0,0x00,0x00,0x7F,0xE0,0x1F,0xF0, +0x00,0x00,0x3F,0xE0,0x3F,0xF0,0x00,0x00,0x3F,0xE0, +0x3F,0xE0,0x00,0x00,0x3F,0xF0,0x7F,0xE0,0x00,0x00, +0x1F,0xF0,0x7F,0xE0,0x00,0x00,0x1F,0xF0,0x7F,0xC0, +0x02,0x00,0x01,0xFF,0x1F,0xF8,0x00,0x00,0x01,0xFF, +0x1F,0xF0,0x00,0x00,0x00,0xFF,0x3F,0xF0,0x00,0x40, +0x00,0x1F,0xF7,0xFC,0x00,0x00,0x00,0x0F,0xFF,0xFC, +0x00,0x08,0x00,0x01,0xFF,0xFF,0x00,0x00,0x00,0x00, +0xFF,0xFF,0x00,0x01,0x00,0x00,0x1F,0xFF,0xC0,0x00, +0x00,0x00,0x0F,0xFF,0xC0,0x00,0x00,0x00,0x0F,0xFF, +0x80,0x00,0x00,0x00,0x07,0xFF,0x80,0x00,0x20,0x00, +0x00,0xFF,0xE0,0x00,0x00,0x00,0x00,0x7F,0xE0,0x00, +0x04,0x00,0x00,0x0F,0xF8,0x00,0x00,0x00,0x00,0x1F, +0xF8,0x00,0x00,0x80,0x00,0x03,0xFE,0x00,0x00,0x00, +0x00,0x07,0xFE,0x00,0x00,0x10,0x00,0x00,0xFF,0x80, +0x00,0x02,0x00,0x00,0x3F,0xE0,0x00,0x00,0x00,0x00, +0x7F,0xE0,0x00,0x00,0x00,0x00,0xFF,0xC0,0x00,0x00, +0x01,0x03,0xFF,0xC0,0x00,0x00,0x01,0xFF,0xFF,0x80, +0x00,0x00,0x40,0x3F,0xFF,0xE0,0x00,0x00,0x00,0x1F, +0xFF,0xC0,0x00,0x00,0x00,0x1F,0xFF,0x80,0x00,0x00, +0x00,0x1F,0xFF,0x00,0x00,0x00,0x00,0x1F,0xFE,0x00, +0x00,0x00,0x00,0x07,0xF0,0x00,0x00,0x00,0x00,0x0B, +0x5A,0x08,0x03,0x1D,0x1F,0xFF,0xFF,0xFF,0xFF,0xF0, +0x7F,0xFF,0xFF,0xE7,0xFF,0x80,0x00,0x00,0x00,0x3F, +0xFC,0x00,0x00,0x00,0x01,0xFF,0xE0,0x00,0x00,0x00, +0x07,0xFF,0x00,0x00,0x00,0x00,0x3F,0xF8,0x00,0x00, +0x00,0x01,0xFF,0xC0,0x00,0x00,0x00,0x0F,0xFF,0x00, +0x00,0x00,0x00,0x7F,0xF8,0x00,0x00,0x00,0x03,0xFF, +0xC0,0x00,0x00,0x00,0x0F,0xFE,0x00,0x00,0x00,0x00, +0x7F,0xF0,0x00,0x00,0x00,0x03,0xFF,0x80,0x00,0x00, +0x00,0x1F,0xFE,0x00,0x00,0x00,0x00,0xFF,0xF0,0x00, +0x00,0x00,0x07,0xFF,0x80,0x00,0x00,0x00,0x1F,0xFC, +0x00,0x00,0x00,0x00,0xFF,0xE0,0x00,0x00,0x00,0x07, +0xFF,0x00,0x00,0x00,0x00,0x3F,0xFC,0x00,0x00,0x00, +0x01,0xFF,0xE0,0x00,0x00,0x00,0x0F,0xFF,0x00,0x00, +0x00,0x00,0x7F,0xF8,0x00,0x00,0x00,0x01,0xFF,0xC0, +0x00,0x00,0x00,0x0F,0xFE,0x00,0x00,0x00,0x00,0x7F, +0xF0,0x00,0x00,0x00,0x03,0xFF,0xC0,0x00,0x00,0x00, +0x1F,0xFE,0x00,0x00,0x00,0x00,0xFF,0xF0,0x00,0x00, +0x00,0x03,0xFF,0x80,0x00,0x00,0x00,0x1F,0xFC,0x00, +0x00,0x00,0x00,0xFF,0xE0,0x00,0x00,0x00,0x07,0xFF, +0x80,0x00,0x00,0x00,0x3F,0xFC,0x00,0x00,0x00,0x01, +0xFF,0xE0,0x00,0x00,0x00,0x0F,0xFF,0x00,0x00,0x00, +0x00,0x3F,0xF8,0x00,0x00,0x00,0x01,0xFF,0xC0,0x00, +0x00,0x00,0x0F,0xFE,0x3F,0xFF,0xFF,0xFF,0xEF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xC0,0x07,0x6F,0x0B,0x5A,0x10, +0x00,0x00,0x7F,0xC0,0x00,0x0F,0xFF,0x00,0x00,0xFF, +0xFC,0x00,0x07,0xFF,0xF0,0x00,0x3F,0xFF,0xE0,0x00, +0x3F,0xFF,0xF0,0x00,0x3F,0xFF,0xF0,0x00,0xFF,0xF0, +0x00,0x07,0xFF,0x00,0x80,0x03,0xFF,0x00,0x68,0x01, +0xFF,0x00,0x34,0x00,0xFF,0x80,0x1A,0x00,0x7F,0xC0, +0x0A,0x00,0x7F,0xC0,0x00,0x03,0xFE,0x00,0x00,0x1F, +0xF8,0x00,0x00,0x7F,0xC0,0x00,0x07,0xFF,0x00,0x00, +0x7F,0xF8,0x00,0x0F,0xFF,0xC0,0x00,0x3F,0xFE,0x00, +0x00,0xFF,0xE0,0x00,0x04,0x7F,0xC0,0x00,0x01,0xFF, +0xC0,0x00,0x07,0xFF,0xC0,0x00,0x1F,0xFF,0x80,0x00, +0x0F,0xFF,0x00,0x00,0x0F,0xFE,0x00,0x00,0x0F,0xF8, +0x00,0x00,0x3F,0xF0,0x00,0x00,0x7F,0xC0,0x02,0x80, +0x1F,0xF0,0x00,0x00,0x3F,0xC0,0x06,0x80,0x1F,0xF0, +0x03,0x40,0x0F,0xF8,0x01,0x80,0x07,0xFC,0x00,0x00, +0x1F,0xF8,0x00,0x00,0x3F,0xE0,0x00,0x00,0xFF,0xC0, +0x00,0x03,0xFF,0xC0,0x00,0x0F,0xFF,0xFE,0x00,0x03, +0xFF,0xFF,0x00,0x00,0xFF,0xFF,0x00,0x01,0xFF,0xFC, +0x00,0x01,0xFF,0xF0,0x00,0x03,0xFF,0xC0,0x00,0x01, +0xFF,0x02,0x2F,0x27,0x51,0xAD,0xFF,0xDF,0xFD,0xFF, +0xDF,0xFD,0xFF,0xDF,0xFD,0xFF,0xDF,0xFD,0xFF,0xDF, +0xFD,0xFF,0xDF,0xFD,0xFF,0x9F,0xF0,0x07,0x6F,0x0B, +0x5A,0x17,0xFC,0x00,0x00,0x1F,0xFE,0x00,0x00,0x7F, +0xFC,0x00,0x01,0xFF,0xFC,0x00,0x08,0xFF,0xFF,0x00, +0x04,0x7F,0xFF,0xC0,0x01,0xFF,0xFF,0x80,0x00,0x1F, +0xFE,0x00,0x00,0x1F,0xF8,0x00,0x00,0x3F,0xE0,0x03, +0x40,0x0F,0xF8,0x01,0xA0,0x07,0xFC,0x00,0xD0,0x03, +0xFE,0x00,0x00,0x0F,0xF8,0x01,0x40,0x03,0xFE,0x00, +0x80,0x00,0xFF,0x80,0x00,0x01,0xFF,0x00,0x00,0x07, +0xFF,0x00,0x00,0x0F,0xFF,0x00,0x00,0x1F,0xFF,0x80, +0x00,0x3F,0xFE,0x00,0x00,0x3F,0xFC,0x00,0x00,0x07, +0xFC,0x00,0x00,0x7F,0xF0,0x00,0x07,0xFF,0xC0,0x00, +0x3F,0xFF,0x00,0x01,0xFF,0xE0,0x00,0x0F,0xFE,0x08, +0x00,0x0F,0xFC,0x00,0x00,0x7F,0xE0,0x10,0x00,0x3F, +0xE0,0x08,0x00,0x3F,0xF0,0x06,0x80,0x1F,0xF0,0x03, +0x40,0x0F,0xF8,0x01,0xA0,0x07,0xFC,0x00,0x80,0x07, +0xFE,0x00,0x00,0x3F,0xF8,0x00,0x03,0xFF,0xC0,0x04, +0x7F,0xFF,0xE0,0x02,0x3F,0xFF,0xE0,0x00,0xFF,0xFF, +0x00,0x03,0xFF,0xF8,0x00,0x0F,0xFF,0xC0,0x00,0x3F, +0xFC,0x00,0x00,0xFF,0x80,0x00,0x00,0x0C,0x89,0x10, +0xCB,0xA0,0x01,0xFE,0x00,0x00,0x00,0x00,0x01,0xFF, +0xF8,0x00,0x00,0x00,0x40,0xFF,0xFF,0xC0,0x00,0x00, +0x18,0x3F,0xFF,0xFF,0x00,0x00,0x07,0x0F,0xFF,0xFF, +0xF8,0x00,0x01,0xE3,0xFF,0xFF,0xFF,0xC0,0x00,0xFC, +0xFF,0xFF,0xFF,0xFE,0x00,0x3F,0xBF,0xFF,0xFF,0xFF, +0xF0,0x3F,0xF8,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xDF, +0xF0,0x1F,0xFF,0xFF,0xFF,0xFB,0xF8,0x00,0x7F,0xFF, +0xFF,0xFE,0x7E,0x00,0x03,0xFF,0xFF,0xFF,0x8F,0x00, +0x00,0x1F,0xFF,0xFF,0xE1,0xC0,0x00,0x00,0xFF,0xFF, +0xF8,0x30,0x00,0x00,0x07,0xFF,0xFE,0x04,0x00,0x00, +0x00,0x3F,0xFF,0x00,0x00,0x00,0x00,0x00,0xFF,0x00, +0x00,}; +/* font data size: 23001 bytes */ + +static const unsigned char Arial_72_index[] = { +0x00,0x00,0x00,0x14,0x00,0xE8,0x03,0xC0,0x28, +0xE0,0xB9,0xC2,0xB9,0x07,0x85,0x0F,0x26,0x21,0x00, +0x47,0x30,0x95,0x11,0x31,0x42,0x67,0x84,0xD5,0x09, +0xB2,0x14,0xC0,0x2D,0x20,0x5E,0x00,0xD3,0x01,0xD5, +0xE3,0xF1,0x48,0x73,0x92,0x5E,0x26,0x78,0x52,0x74, +0xB0,0x81,0x62,0x42,0xC8,0x85,0xD7,0x4B,0xC4,0x18, +0xA1,0x33,0x92,0x77,0xF0,0xFB,0xC2,0x0F,0x34,0x52, +0x89,0x02,0xD2,0x3A,0x24,0xCD,0x4D,0x0C,0x9B,0x95, +0x37,0xEA,0x78,0x75,0x34,0x2A,0x7B,0xD5,0xCB,0x2D, +0x0E,0x5D,0xAC,0xBF,0x91,0x8D,0xAB,0x39,0xC6,0xB0, +0x4D,0x78,0xDB,0x56,0x38,0xA9,0x76,0xDC,0xF6,0x19, +0xF7,0xB4,0x0A,0xF8,0x1B,0xD0,0x63,0x20,0xDD,0xC2, +0x38,0x84,0x8B,0x09,0x9E,0x1C,0xFC,0x49,0xE8,0xB2, +0x11,0xA2,0x63,0xCB,0x47,0xF3,0x92,0x9B,0x27,0x5E, +0x4F,0x7C,0xA3,0x59,0x6B,0xF2,0xDD,0xA6,0x21,0xCC, +0xBB,0x9B,0x87,0x3B,0x0A,0x7E,0x65,0x01,0x3A,0x27, +0x94,0x63,0xE9,0x01,0x52,0xF6,0xA8,0xCD,0x56,0x4A, +0xB7,0x9D,0x7D,0xFB,0x13,0x36,0x2C,0xEC,0xB3,0x80, +}; +/* font index size: 179 bytes */ + +const ILI9341_t3_font_t Arial_72 = { + Arial_72_index, + 0, + Arial_72_data, + 1, + 0, + 32, + 126, + 0, + 0, + 15, + 7, + 7, + 5, + 7, + 7, + 111, + 72 +}; + + + +static const unsigned char Arial_96_data[] = { +0x00,0x00,0x00,0x00,0x94,0x03,0x2F,0xAC,0x00,0x8B, +0x7F,0xFF,0x7F,0xFF,0x7F,0xFF,0x7F,0xFE,0x3F,0xFF, +0x5F,0xFB,0x5F,0xFA,0x5F,0xFB,0x4F,0xF3,0x4F,0xF2, +0x4F,0xF0,0x3F,0x9A,0x3F,0x01,0xF8,0xD0,0x00,0x90, +0x00,0xDF,0xFF,0xBF,0xFF,0x09,0x11,0x18,0xF4,0xBF, +0x7F,0xFC,0x00,0x3F,0xFF,0x7F,0xFC,0x00,0x3F,0xFE, +0xFF,0xFC,0x00,0x3F,0xFF,0x1F,0xF8,0x00,0x1F,0xF8, +0x7F,0xC0,0x00,0x7F,0xD6,0x7F,0x80,0x00,0x7F,0x81, +0xFC,0x00,0x03,0xFC,0x0F,0xE0,0x00,0x0F,0xC0,0x7E, +0x00,0x00,0x7E,0x00,0x12,0x6F,0x80,0x01,0x28,0x00, +0x00,0x00,0x7F,0xF8,0x00,0x03,0xFF,0xC0,0x00,0x00, +0x00,0x1F,0xFE,0x00,0x01,0xFF,0xF0,0x00,0x00,0x00, +0x0F,0xFF,0x80,0x00,0x7F,0xF8,0x09,0x00,0x00,0x00, +0x7F,0xF8,0x00,0x03,0xFF,0xC0,0x00,0x00,0x00,0x1F, +0xFE,0x00,0x01,0xFF,0xF0,0x00,0x00,0x00,0x0F,0xFF, +0x80,0x00,0x7F,0xF8,0x04,0x80,0x00,0x00,0x7F,0xF8, +0x00,0x03,0xFF,0xC0,0x00,0x00,0x00,0x1F,0xFE,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x0F,0xFF,0x80,0x00, +0x7F,0xF8,0x02,0x40,0x00,0x00,0x7F,0xF8,0x00,0x03, +0xFF,0xC0,0x00,0x00,0x00,0x1F,0xFE,0x00,0x01,0xFF, +0xF0,0x00,0x00,0x00,0x0F,0xFF,0x80,0x00,0x7F,0xF8, +0x01,0x00,0x00,0x00,0x7F,0xF8,0x00,0x03,0xFF,0xC0, +0x00,0x00,0x00,0x1F,0xFE,0x00,0x01,0xFF,0xF0,0x00, +0x00,0x00,0x0F,0xFF,0x80,0x00,0x7F,0xF8,0x00,0x90, +0x00,0x00,0x7F,0xF8,0x00,0x03,0xFF,0xC0,0x00,0x00, +0x00,0x1F,0xFE,0x00,0x01,0xFF,0xF0,0x01,0xBF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFB,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x0F, +0xFF,0x00,0x00,0x7F,0xF8,0x00,0x00,0x00,0x03,0xFF, +0xC0,0x00,0x3F,0xFE,0x00,0x00,0x00,0x01,0xFF,0xF0, +0x00,0x0F,0xFF,0x00,0x01,0x20,0x00,0x0F,0xFF,0x00, +0x00,0x7F,0xF8,0x00,0x00,0x00,0x03,0xFF,0xC0,0x00, +0x3F,0xFE,0x00,0x00,0x00,0x01,0xFF,0xF0,0x00,0x0F, +0xFF,0x00,0x00,0x90,0x00,0x0F,0xFF,0x00,0x00,0x7F, +0xF8,0x00,0x00,0x00,0x03,0xFF,0xC0,0x00,0x3F,0xFE, +0x00,0x00,0x00,0x01,0xFF,0xF0,0x00,0x0F,0xFF,0x00, +0x00,0x48,0x00,0x0F,0xFF,0x00,0x00,0x7F,0xF8,0x00, +0x00,0x00,0x03,0xFF,0xC0,0x00,0x3F,0xFE,0x00,0x00, +0x00,0x01,0xFF,0xF0,0x00,0x0F,0xFF,0x00,0x00,0x20, +0x00,0x0F,0xFF,0x00,0x00,0x7F,0xF8,0x00,0x01,0xBF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFB,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xC8,0x00, +0xFF,0xF0,0x00,0x07,0xFF,0x80,0x00,0x00,0x00,0x3F, +0xFC,0x00,0x03,0xFF,0xE0,0x00,0x00,0x00,0x1F,0xFF, +0x00,0x00,0xFF,0xF0,0x00,0x00,0x20,0x00,0xFF,0xF0, +0x00,0x07,0xFF,0x80,0x00,0x00,0x00,0x3F,0xFC,0x00, +0x03,0xFF,0xE0,0x00,0x00,0x00,0x1F,0xFF,0x00,0x00, +0xFF,0xF0,0x00,0x00,0x12,0x00,0xFF,0xF0,0x00,0x07, +0xFF,0x80,0x00,0x00,0x00,0x3F,0xFC,0x00,0x03,0xFF, +0xE0,0x00,0x00,0x00,0x1F,0xFF,0x00,0x00,0xFF,0xF0, +0x00,0x00,0x09,0x00,0xFF,0xF0,0x00,0x07,0xFF,0x80, +0x00,0x00,0x00,0x3F,0xFC,0x00,0x03,0xFF,0xE0,0x00, +0x00,0x00,0x1F,0xFF,0x00,0x00,0xFF,0xF0,0x00,0x00, +0x04,0x80,0xFF,0xF0,0x00,0x07,0xFF,0x80,0x00,0x00, +0x00,0x3F,0xFC,0x00,0x03,0xFF,0xE0,0x00,0x00,0x00, +0x1F,0xFF,0x00,0x00,0xFF,0xF0,0x00,0x00,0x00,0x07, +0xFF,0x80,0x00,0x3F,0xFC,0x00,0x00,0x00,0x0F,0xFA, +0x1B,0xCD,0x2A,0xC0,0x00,0x00,0x03,0xF8,0x00,0x00, +0x00,0x00,0x00,0x00,0x3F,0xFF,0x00,0x00,0x00,0x00, +0x00,0x03,0xFF,0xFF,0xF8,0x00,0x00,0x00,0x00,0x1F, +0xFF,0xFF,0xFE,0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF, +0xFF,0xC0,0x00,0x00,0x01,0xFF,0xFF,0xFF,0xFF,0xE0, +0x00,0x00,0x07,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x00, +0x0F,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x1F,0xFF, +0xFF,0xFF,0xFF,0xFE,0x00,0x00,0x3F,0xFF,0xFF,0xFF, +0xFF,0xFF,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF, +0x80,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xC0,0x00, +0xFF,0xFF,0xF3,0xFF,0xFF,0xFF,0xC0,0x01,0xFF,0xFF, +0x83,0xF9,0xFF,0xFF,0xE0,0x01,0xFF,0xFE,0x03,0xF8, +0x3F,0xFF,0xF0,0x03,0xFF,0xF8,0x03,0xF8,0x0F,0xFF, +0xF0,0x03,0xFF,0xF0,0x03,0xF8,0x07,0xFF,0xF8,0x07, +0xFF,0xE0,0x03,0xF8,0x01,0xFF,0xF8,0x07,0xFF,0xC0, +0x03,0xF8,0x01,0xFF,0xF8,0x07,0xFF,0xC0,0x03,0xF8, +0x00,0xFF,0xFC,0x07,0xFF,0x80,0x03,0xF8,0x00,0x7F, +0xFC,0x0F,0xFF,0x80,0x03,0xF8,0x00,0x7F,0xFC,0x49, +0xFF,0xE0,0x00,0x7F,0x00,0x07,0xFF,0xC1,0xFF,0xE0, +0x00,0x7F,0x00,0x03,0xFE,0x01,0xFF,0xE0,0x00,0x7F, +0x00,0x03,0x80,0x09,0x3F,0xFC,0x00,0x0F,0xE0,0x00, +0x00,0x01,0x07,0xFF,0xC0,0x01,0xFC,0x00,0x00,0x00, +0x03,0xFF,0xC0,0x01,0xFC,0x00,0x00,0x00,0x20,0x7F, +0xFC,0x00,0x3F,0x80,0x00,0x00,0x00,0x7F,0xFE,0x00, +0x3F,0x80,0x00,0x00,0x00,0x3F,0xFF,0x00,0x3F,0x80, +0x00,0x00,0x00,0x3F,0xFF,0xC0,0x3F,0x80,0x00,0x00, +0x00,0x1F,0xFF,0xE0,0x3F,0x80,0x00,0x00,0x00,0x1F, +0xFF,0xFC,0x3F,0x80,0x00,0x00,0x00,0x0F,0xFF,0xFF, +0xBF,0x80,0x00,0x00,0x04,0x00,0xFF,0xFF,0xFF,0xF0, +0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF,0xFE,0x00,0x00, +0x00,0x00,0x3F,0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x00, +0x0F,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x00,0x07,0xFF, +0xFF,0xFF,0xFF,0x00,0x00,0x00,0x01,0xFF,0xFF,0xFF, +0xFF,0xC0,0x00,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xF0, +0x00,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xFC,0x00,0x00, +0x00,0x07,0xFF,0xFF,0xFF,0xFE,0x00,0x00,0x00,0x00, +0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x1F,0xFF, +0xFF,0xFF,0x80,0x00,0x00,0x00,0x07,0xFF,0xFF,0xFF, +0xC0,0x00,0x00,0x00,0x07,0xFF,0xFF,0xFF,0xE0,0x00, +0x00,0x00,0x07,0xF7,0xFF,0xFF,0xF0,0x00,0x00,0x00, +0x07,0xF0,0xFF,0xFF,0xF0,0x00,0x00,0x00,0x07,0xF0, +0x1F,0xFF,0xF8,0x00,0x00,0x00,0x07,0xF0,0x0F,0xFF, +0xF8,0x00,0x00,0x00,0x07,0xF0,0x03,0xFF,0xFC,0x00, +0x00,0x00,0x07,0xF0,0x01,0xFF,0xFC,0x80,0x00,0x00, +0x00,0xFE,0x00,0x0F,0xFF,0xC0,0x00,0x00,0x00,0xFE, +0x00,0x07,0xFF,0xC0,0x00,0x00,0x00,0xFE,0x00,0x03, +0xFF,0xD0,0x00,0x00,0x00,0x1F,0xC0,0x00,0x7F,0xFE, +0x40,0x00,0x00,0x03,0xF8,0x00,0x07,0xFF,0x80,0x1C, +0x00,0x03,0xF8,0x00,0x07,0xFF,0x87,0xFC,0x00,0x03, +0xF8,0x00,0x07,0xFF,0xBF,0xFC,0x00,0x03,0xF8,0x00, +0x07,0xFF,0xC7,0xFF,0xC0,0x00,0x7F,0x00,0x00,0xFF, +0xF7,0xFF,0xC0,0x00,0x7F,0x00,0x01,0xFF,0xF8,0x7F, +0xFC,0x00,0x0F,0xE0,0x00,0x3F,0xFC,0x7F,0xFC,0x00, +0x0F,0xE0,0x00,0x7F,0xFC,0x7F,0xFE,0x00,0x0F,0xE0, +0x00,0x7F,0xFC,0x3F,0xFE,0x00,0x0F,0xE0,0x00,0xFF, +0xF8,0x3F,0xFF,0x00,0x0F,0xE0,0x01,0xFF,0xF8,0x3F, +0xFF,0x80,0x0F,0xE0,0x03,0xFF,0xF8,0x1F,0xFF,0xC0, +0x0F,0xE0,0x07,0xFF,0xF0,0x1F,0xFF,0xE0,0x0F,0xE0, +0x0F,0xFF,0xF0,0x0F,0xFF,0xF8,0x0F,0xE0,0x1F,0xFF, +0xE0,0x0F,0xFF,0xFC,0x0F,0xE0,0x7F,0xFF,0xC0,0x07, +0xFF,0xFF,0x8F,0xE3,0xFF,0xFF,0xC0,0x07,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0x80,0x03,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0x00,0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE, +0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x00, +0x7F,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x3F,0xFF, +0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x1F,0xFF,0xFF,0xFF, +0xFF,0xC0,0x00,0x00,0x07,0xFF,0xFF,0xFF,0xFF,0x00, +0x00,0x00,0x01,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x00, +0x00,0x7F,0xFF,0xFF,0xF0,0x00,0x00,0x00,0x00,0x0F, +0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xE0, +0x00,0x00,0x01,0xA0,0x00,0x00,0x01,0xFC,0x00,0x00, +0x00,0x2C,0x00,0x00,0x00,0x3F,0x80,0x00,0x00,0x00, +0x19,0xF0,0x9F,0xFD,0xD8,0x00,0x03,0xFF,0x00,0x00, +0x00,0x00,0x00,0x01,0xFF,0xE0,0x00,0x00,0x00,0x1F, +0xFF,0xE0,0x00,0x00,0x00,0x00,0x01,0xFF,0xC0,0x00, +0x00,0x00,0x7F,0xFF,0xF8,0x00,0x00,0x00,0x00,0x03, +0xFF,0xC0,0x00,0x00,0x00,0xFF,0xFF,0xFE,0x00,0x00, +0x00,0x00,0x03,0xFF,0x80,0x00,0x00,0x01,0xFF,0xFF, +0xFF,0x00,0x00,0x00,0x00,0x07,0xFF,0x80,0x00,0x00, +0x03,0xFF,0xFF,0xFF,0x80,0x00,0x00,0x00,0x07,0xFF, +0x00,0x00,0x00,0x07,0xFF,0xFF,0xFF,0xC0,0x00,0x00, +0x00,0x0F,0xFE,0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFF, +0xE0,0x00,0x00,0x00,0x0F,0xFE,0x00,0x00,0x00,0x1F, +0xFF,0x83,0xFF,0xF0,0x00,0x00,0x00,0x1F,0xFC,0x00, +0x00,0x00,0x1F,0xFC,0x00,0xFF,0xF0,0x00,0x00,0x00, +0x1F,0xFC,0x00,0x00,0x00,0x3F,0xF8,0x00,0x3F,0xF8, +0x00,0x00,0x00,0x3F,0xF8,0x00,0x00,0x00,0x3F,0xF0, +0x00,0x1F,0xF8,0x00,0x00,0x00,0x3F,0xF8,0x00,0x00, +0x00,0x7F,0xF0,0x00,0x1F,0xFC,0x00,0x00,0x00,0x7F, +0xF0,0x00,0x00,0x00,0x7F,0xE0,0x00,0x0F,0xFC,0x00, +0x00,0x00,0xFF,0xF0,0x00,0x00,0x00,0xFF,0xE0,0x00, +0x0F,0xFE,0x00,0x00,0x00,0xFF,0xE0,0x00,0x00,0x00, +0xFF,0xC0,0x00,0x07,0xFE,0x00,0x00,0x01,0xFF,0xE0, +0x00,0x00,0x00,0xFF,0xC0,0x00,0x07,0xFE,0x00,0x00, +0x01,0xFF,0xC0,0x00,0x00,0x00,0xFF,0xC0,0x00,0x07, +0xFE,0x00,0x00,0x03,0xFF,0xC0,0x00,0x00,0x00,0xFF, +0xC0,0x00,0x07,0xFE,0x00,0x00,0x03,0xFF,0x80,0x00, +0x00,0x02,0x3F,0xF0,0x00,0x00,0x7F,0xE0,0x00,0x00, +0xFF,0xE0,0x00,0x00,0x00,0x47,0xFE,0x00,0x00,0x0F, +0xFC,0x00,0x00,0x3F,0xF8,0x00,0x00,0x00,0x08,0xFF, +0xC0,0x00,0x01,0xFF,0x80,0x00,0x0F,0xFE,0x00,0x00, +0x00,0x00,0xFF,0xC0,0x00,0x01,0xFF,0x80,0x00,0x1F, +0xFC,0x00,0x00,0x00,0x00,0xFF,0xC0,0x00,0x01,0xFF, +0x80,0x00,0x3F,0xFC,0x00,0x00,0x00,0x00,0xFF,0xC0, +0x00,0x01,0xFF,0x80,0x00,0x3F,0xF8,0x00,0x00,0x00, +0x00,0xFF,0xC0,0x00,0x01,0xFF,0x80,0x00,0x7F,0xF8, +0x00,0x00,0x00,0x00,0xFF,0xC0,0x00,0x01,0xFF,0x80, +0x00,0x7F,0xF0,0x00,0x00,0x00,0x00,0xFF,0xC0,0x00, +0x01,0xFF,0x80,0x00,0xFF,0xF0,0x00,0x00,0x00,0x00, +0xFF,0xC0,0x00,0x01,0xFF,0x80,0x00,0xFF,0xE0,0x00, +0x00,0x00,0x00,0x7F,0xC0,0x00,0x03,0xFF,0x00,0x01, +0xFF,0xC0,0x00,0x00,0x00,0x00,0x7F,0xE0,0x00,0x03, +0xFF,0x00,0x01,0xFF,0xC0,0x00,0x00,0x00,0x01,0x0F, +0xFC,0x00,0x00,0x7F,0xE0,0x00,0x7F,0xF0,0x00,0x00, +0x00,0x00,0x0F,0xFC,0x00,0x00,0xFF,0xC0,0x00,0xFF, +0xE0,0x00,0x00,0x00,0x00,0x07,0xFE,0x00,0x00,0xFF, +0xC0,0x00,0xFF,0xE0,0x00,0x00,0x00,0x00,0x07,0xFE, +0x00,0x01,0xFF,0xC0,0x01,0xFF,0xC0,0x00,0x00,0x00, +0x00,0x03,0xFF,0x00,0x01,0xFF,0x80,0x03,0xFF,0xC0, +0x00,0x00,0x00,0x00,0x03,0xFF,0x80,0x03,0xFF,0x80, +0x03,0xFF,0x80,0x00,0x00,0x00,0x00,0x01,0xFF,0xC0, +0x07,0xFF,0x00,0x07,0xFF,0x80,0x00,0x00,0x00,0x00, +0x01,0xFF,0xF0,0x1F,0xFF,0x00,0x07,0xFF,0x00,0x00, +0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFE,0x00,0x0F, +0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF, +0xFC,0x00,0x0F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00, +0x3F,0xFF,0xFF,0xF8,0x00,0x1F,0xFC,0x00,0x00,0x00, +0x00,0x00,0x00,0x1F,0xFF,0xFF,0xF0,0x00,0x1F,0xFC, +0x00,0x00,0xFF,0xC0,0x00,0x00,0x0F,0xFF,0xFF,0xE0, +0x00,0x3F,0xF8,0x00,0x07,0xFF,0xF8,0x00,0x00,0x03, +0xFF,0xFF,0x80,0x00,0x3F,0xF8,0x00,0x1F,0xFF,0xFE, +0x00,0x00,0x00,0xFF,0xFE,0x00,0x00,0x7F,0xF0,0x00, +0x3F,0xFF,0xFF,0x80,0x00,0x00,0x1F,0xF0,0x00,0x00, +0x7F,0xF0,0x00,0x7F,0xFF,0xFF,0xC0,0x00,0x00,0x00, +0x00,0x00,0x00,0xFF,0xE0,0x00,0xFF,0xFF,0xFF,0xE0, +0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xE0,0x01,0xFF, +0xFF,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x01,0xFF, +0xC0,0x03,0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x00,0x00, +0x00,0x03,0xFF,0xC0,0x07,0xFF,0xE0,0xFF,0xFC,0x00, +0x00,0x00,0x00,0x00,0x03,0xFF,0x80,0x07,0xFF,0x00, +0x3F,0xFC,0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0x80, +0x0F,0xFE,0x00,0x0F,0xFE,0x00,0x00,0x00,0x00,0x00, +0x07,0xFF,0x00,0x0F,0xFC,0x00,0x07,0xFE,0x00,0x00, +0x00,0x00,0x00,0x0F,0xFE,0x00,0x1F,0xFC,0x00,0x07, +0xFF,0x00,0x00,0x00,0x00,0x00,0x0F,0xFE,0x00,0x1F, +0xF8,0x00,0x03,0xFF,0x00,0x00,0x00,0x00,0x00,0x1F, +0xFC,0x00,0x3F,0xF8,0x00,0x03,0xFF,0x80,0x00,0x00, +0x00,0x00,0x1F,0xFC,0x00,0x3F,0xF0,0x00,0x01,0xFF, +0xA0,0x00,0x00,0x00,0x00,0x07,0xFF,0x00,0x07,0xFE, +0x00,0x00,0x3F,0xF0,0x00,0x00,0x00,0x00,0x0F,0xFE, +0x00,0x0F,0xFE,0x00,0x00,0x3F,0xF0,0x00,0x00,0x00, +0x00,0x1F,0xFE,0x00,0x0F,0xFC,0x00,0x00,0x1F,0xF8, +0x00,0x00,0x00,0x00,0x1F,0xFC,0x00,0x0F,0xFC,0x00, +0x00,0x1F,0xF8,0x00,0x00,0x00,0x00,0x3F,0xFC,0x00, +0x0F,0xFC,0x00,0x00,0x1F,0xF8,0x00,0x00,0x00,0x00, +0x3F,0xF8,0x00,0x0F,0xFC,0x00,0x00,0x1F,0xF8,0x00, +0x00,0x00,0x00,0x7F,0xF8,0x00,0x0F,0xFC,0x00,0x00, +0x1F,0xF8,0x00,0x00,0x00,0x00,0x7F,0xF0,0x00,0x0F, +0xFC,0x00,0x00,0x1F,0xFC,0x00,0x00,0x00,0x00,0x1F, +0xFC,0x00,0x01,0xFF,0x80,0x00,0x03,0xFF,0x80,0x00, +0x00,0x00,0x07,0xFF,0x00,0x00,0x3F,0xF0,0x00,0x00, +0x7F,0xF0,0x00,0x00,0x00,0x01,0xFF,0xC0,0x00,0x07, +0xFE,0x00,0x00,0x0F,0xFC,0x00,0x00,0x00,0x03,0xFF, +0x80,0x00,0x07,0xFE,0x00,0x00,0x0F,0xFC,0x00,0x00, +0x00,0x07,0xFF,0x80,0x00,0x03,0xFE,0x00,0x00,0x1F, +0xF8,0x00,0x00,0x00,0x07,0xFF,0x00,0x00,0x03,0xFF, +0x00,0x00,0x1F,0xF8,0x00,0x00,0x00,0x0F,0xFF,0x00, +0x00,0x03,0xFF,0x00,0x00,0x1F,0xF8,0x00,0x00,0x00, +0x0F,0xFE,0x00,0x00,0x03,0xFF,0x00,0x00,0x1F,0xF8, +0x00,0x00,0x00,0x1F,0xFE,0x00,0x00,0x03,0xFF,0x80, +0x00,0x3F,0xF0,0x00,0x00,0x00,0x1F,0xFC,0x00,0x00, +0x01,0xFF,0x80,0x00,0x3F,0xF0,0x00,0x00,0x00,0x3F, +0xF8,0x00,0x00,0x01,0xFF,0xC0,0x00,0x7F,0xF0,0x00, +0x00,0x00,0x3F,0xF8,0x00,0x00,0x00,0xFF,0xC0,0x00, +0x7F,0xE0,0x00,0x00,0x00,0x7F,0xF0,0x00,0x00,0x00, +0xFF,0xE0,0x00,0xFF,0xE0,0x00,0x00,0x00,0x7F,0xF0, +0x00,0x00,0x00,0x7F,0xF0,0x01,0xFF,0xC0,0x00,0x00, +0x00,0xFF,0xE0,0x00,0x00,0x00,0x7F,0xFC,0x07,0xFF, +0xC0,0x00,0x00,0x00,0xFF,0xE0,0x00,0x00,0x00,0x3F, +0xFF,0xFF,0xFF,0x80,0x00,0x00,0x01,0xFF,0xC0,0x00, +0x00,0x00,0x1F,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x03, +0xFF,0xC0,0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFE,0x00, +0x00,0x00,0x03,0xFF,0x80,0x00,0x00,0x00,0x07,0xFF, +0xFF,0xFC,0x00,0x00,0x00,0x07,0xFF,0x80,0x00,0x00, +0x00,0x03,0xFF,0xFF,0xF8,0x00,0x00,0x00,0x07,0xFF, +0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xE0,0x00,0x00, +0x00,0x0F,0xFF,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF, +0x80,0x00,0x00,0x00,0x0F,0xFE,0x00,0x00,0x00,0x00, +0x00,0x07,0xFC,0x00,0x00,0x14,0x30,0x9B,0xFD,0x64, +0x00,0x00,0x00,0x07,0xFF,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x1F,0xFF,0xF8,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x7F,0xFF,0xFF,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x00, +0x00,0x00,0x00,0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x00, +0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFE,0x00,0x00,0x00, +0x00,0x00,0x01,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x00, +0x00,0x00,0x01,0xFF,0xFF,0xFF,0xFF,0xE0,0x00,0x00, +0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x00, +0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFE,0x00,0x00, +0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00, +0x00,0x00,0x00,0xFF,0xFF,0x80,0x7F,0xFF,0xC0,0x00, +0x00,0x00,0x00,0x7F,0xFF,0x00,0x0F,0xFF,0xE0,0x00, +0x00,0x00,0x00,0x7F,0xFF,0x00,0x03,0xFF,0xF8,0x00, +0x00,0x00,0x00,0x3F,0xFF,0x00,0x00,0xFF,0xFC,0x00, +0x00,0x00,0x00,0x1F,0xFF,0x00,0x00,0x3F,0xFE,0x00, +0x00,0x02,0x00,0x03,0xFF,0xE0,0x00,0x01,0xFF,0xF0, +0x00,0x00,0x30,0x00,0x3F,0xFC,0x00,0x00,0x0F,0xFF, +0x00,0x00,0x00,0x00,0x1F,0xFF,0x00,0x00,0x07,0xFF, +0x00,0x00,0x00,0x00,0x07,0xFF,0x80,0x00,0x07,0xFF, +0x80,0x00,0x00,0x00,0x03,0xFF,0xE0,0x00,0x03,0xFF, +0xC0,0x00,0x00,0x00,0x01,0xFF,0xF0,0x00,0x03,0xFF, +0xC0,0x00,0x00,0x00,0x00,0x7F,0xFC,0x00,0x03,0xFF, +0xE0,0x00,0x00,0x00,0x00,0x3F,0xFF,0x00,0x03,0xFF, +0xE0,0x00,0x00,0x00,0x00,0x0F,0xFF,0xC0,0x03,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x07,0xFF,0xE0,0x03,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x01,0xFF,0xF8,0x07,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x00,0xFF,0xFE,0x07,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0x8F,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xFF,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xFF,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF, +0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xFF, +0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xFF, +0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xFF, +0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0xFF, +0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF, +0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF, +0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xFF, +0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xFF, +0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xFF, +0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xF7, +0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xE1, +0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xC0, +0x7F,0xFF,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xC0, +0x3F,0xFF,0x80,0x00,0x7C,0x00,0x00,0x3F,0xFF,0x80, +0x0F,0xFF,0xE0,0x00,0x7F,0xF0,0x00,0x3F,0xFF,0x80, +0x03,0xFF,0xF8,0x00,0x3F,0xFE,0x00,0x3F,0xFF,0x80, +0x00,0xFF,0xFE,0x00,0x1F,0xFF,0x00,0x1F,0xFF,0x80, +0x00,0x3F,0xFF,0x80,0x1F,0xFF,0x00,0x1F,0xFF,0x80, +0x00,0x1F,0xFF,0xC0,0x0F,0xFF,0x80,0x1F,0xFF,0x80, +0x00,0x07,0xFF,0xF0,0x07,0xFF,0xC0,0x0F,0xFF,0x80, +0x00,0x01,0xFF,0xFC,0x07,0xFF,0xC0,0x07,0xFF,0x80, +0x00,0x00,0x7F,0xFF,0x03,0xFF,0xE0,0x07,0xFF,0xC0, +0x00,0x00,0x1F,0xFF,0xC3,0xFF,0xF0,0x03,0xFF,0xC0, +0x00,0x00,0x0F,0xFF,0xE1,0xFF,0xF0,0x01,0xFF,0xE0, +0x00,0x00,0x03,0xFF,0xF9,0xFF,0xF8,0x01,0xFF,0xF0, +0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFC,0x00,0xFF,0xF0, +0x00,0x00,0x00,0x3F,0xFF,0xFF,0xFC,0x00,0x7F,0xF8, +0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFE,0x00,0x3F,0xFC, +0x00,0x00,0x00,0x07,0xFF,0xFF,0xFE,0x00,0x1F,0xFE, +0x00,0x00,0x00,0x01,0xFF,0xFF,0xFF,0x00,0x0F,0xFF, +0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF,0x00,0x07,0xFF, +0x80,0x00,0x00,0x00,0x1F,0xFF,0xFF,0x80,0x03,0xFF, +0xC0,0x00,0x00,0x00,0x07,0xFF,0xFF,0x80,0x01,0xFF, +0xF0,0x00,0x00,0x00,0x03,0xFF,0xFF,0x80,0x00,0xFF, +0xF8,0x00,0x00,0x00,0x00,0xFF,0xFF,0xC0,0x00,0x7F, +0xFC,0x00,0x00,0x00,0x00,0x3F,0xFF,0xE0,0x00,0x1F, +0xFF,0x00,0x00,0x00,0x00,0x0F,0xFF,0xF0,0x00,0x0F, +0xFF,0x80,0x00,0x00,0x00,0x0F,0xFF,0xFC,0x00,0x07, +0xFF,0xE0,0x00,0x00,0x00,0x0F,0xFF,0xFF,0x00,0x01, +0xFF,0xF8,0x00,0x00,0x00,0x0F,0xFF,0xFF,0xC0,0x00, +0xFF,0xFC,0x00,0x00,0x00,0x0F,0xFF,0xFF,0xF0,0x00, +0x7F,0xFF,0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFC,0x00, +0x1F,0xFF,0xC0,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0x00, +0x0F,0xFF,0xF0,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xC0, +0x03,0xFF,0xFC,0x00,0x00,0x3F,0xFF,0xFF,0xFF,0xF0, +0x00,0xFF,0xFF,0x80,0x00,0x7F,0xFF,0xF7,0xFF,0xFC, +0x00,0x7F,0xFF,0xF8,0x03,0xFF,0xFF,0xF3,0xFF,0xFF, +0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0xF8,0xFF,0xFF, +0xE0,0x07,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0x3F,0xFF, +0xF8,0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0x0F,0xFF, +0xFE,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xF0,0x03,0xFF, +0xFE,0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0xFF, +0xFE,0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xE0,0x00,0x1F, +0xFE,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xE0,0x00,0x07, +0xFE,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xC0,0x00,0x01, +0xFE,0x00,0x00,0x03,0xFF,0xFF,0xFF,0x00,0x00,0x00, +0x7E,0x00,0x00,0x00,0x3F,0xFF,0xFE,0x00,0x00,0x00, +0x0E,0x00,0x00,0x00,0x01,0xFF,0xE0,0x00,0x00,0x00, +0x02,0x00,0x03,0x11,0x18,0xF4,0x67,0x7F,0xFF,0x7F, +0xFE,0xFF,0xFF,0x5F,0xFB,0x0F,0xF0,0x7F,0x01,0xF8, +0x08,0x3C,0xA3,0x98,0xB0,0x00,0x00,0x01,0xFE,0x00, +0x00,0x01,0xFE,0x00,0x00,0x01,0xFE,0x00,0x00,0x01, +0xFF,0x20,0x00,0x00,0x3F,0xE0,0x00,0x00,0x3F,0xE1, +0x00,0x00,0x07,0xFC,0x00,0x00,0x07,0xFC,0x00,0x00, +0x07,0xFE,0x00,0x00,0x03,0xFE,0x00,0x00,0x03,0xFF, +0x00,0x00,0x03,0xFF,0x00,0x00,0x01,0xFF,0x00,0x00, +0x01,0xFF,0x80,0x00,0x00,0xFF,0x80,0x00,0x00,0xFF, +0xC0,0x08,0x00,0x1F,0xF8,0x00,0x80,0x03,0xFF,0x00, +0x00,0x03,0xFF,0x80,0x00,0x01,0xFF,0x80,0x00,0x01, +0xFF,0xC0,0x00,0x00,0xFF,0xC0,0x00,0x80,0x1F,0xFC, +0x00,0x09,0x03,0xFF,0x80,0x00,0x90,0x7F,0xF0,0x00, +0x09,0x0F,0xFE,0x00,0x00,0x0F,0xFF,0x00,0x00,0x40, +0xFF,0xE0,0x00,0x04,0x9F,0xFE,0x00,0x00,0x41,0xFF, +0xC0,0x00,0x06,0x3F,0xFC,0x00,0x00,0x6F,0xFF,0x80, +0x00,0x06,0xFF,0xF8,0x00,0x00,0x5F,0xFF,0x80,0x00, +0x06,0x3F,0xFC,0x00,0x00,0x0F,0xFE,0x00,0x00,0x28, +0xFF,0xF0,0x00,0x00,0x3F,0xF8,0x00,0x01,0x03,0xFF, +0xC0,0x00,0x10,0x1F,0xFC,0x00,0x00,0x0F,0xFF,0x00, +0x00,0x80,0x7F,0xF0,0x00,0x00,0x3F,0xFC,0x00,0x04, +0x01,0xFF,0xC0,0x00,0x48,0x0F,0xFE,0x00,0x04,0x00, +0x7F,0xF0,0x00,0x00,0x1F,0xF8,0x00,0x00,0x0F,0xFE, +0x00,0x00,0x03,0xFF,0x00,0x00,0x01,0xFF,0xC0,0x00, +0x00,0x7F,0xE0,0x00,0x00,0x3F,0xF8,0x00,0x00,0x0F, +0xFC,0x00,0x80,0x00,0x7F,0xE0,0x08,0x00,0x03,0xFF, +0x00,0x80,0x00,0x1F,0xF8,0x00,0x00,0x07,0xFE,0x00, +0x00,0x01,0xFF,0x00,0x00,0x00,0xFF,0xC0,0x00,0x00, +0x3F,0xE0,0x00,0x00,0x0F,0xF8,0x40,0x00,0x00,0x7F, +0xC0,0x00,0x00,0x1F,0xF0,0x00,0x00,0x07,0xF8,0x00, +0x00,0x01,0xFE,0x00,0x00,0x00,0x7F,0x80,0x08,0x3C, +0x9F,0x98,0xB1,0xFE,0x00,0x00,0x00,0x7F,0x80,0x00, +0x00,0x3F,0xE0,0x00,0x00,0x0F,0xF8,0x00,0x00,0x03, +0xFC,0x00,0x00,0x01,0xFF,0x00,0x00,0x00,0x7F,0xC0, +0x00,0x00,0x3F,0xF0,0x00,0x00,0x0F,0xF8,0x00,0x00, +0x03,0xFE,0x00,0x00,0x01,0xFF,0x80,0x00,0x00,0x7F, +0xC0,0x00,0x00,0x3F,0xF0,0x00,0x10,0x01,0xFF,0x80, +0x00,0x00,0x7F,0xE0,0x00,0x00,0x1F,0xF0,0x00,0x00, +0x0F,0xFC,0x00,0x20,0x00,0x7F,0xE0,0x00,0x00,0x3F, +0xF8,0x00,0x00,0x0F,0xFC,0x00,0x00,0x07,0xFF,0x00, +0x00,0x01,0xFF,0x80,0x00,0x00,0xFF,0xE0,0x00,0x00, +0x3F,0xF0,0x08,0x00,0x03,0xFF,0x80,0x00,0x00,0xFF, +0xC0,0x40,0x00,0x0F,0xFE,0x04,0x80,0x00,0x7F,0xF0, +0x00,0x00,0x3F,0xFC,0x20,0x00,0x01,0xFF,0xC2,0x00, +0x00,0x1F,0xFE,0x00,0x00,0x07,0xFF,0x14,0x00,0x00, +0x7F,0xF8,0x00,0x00,0x1F,0xFC,0xC0,0x00,0x01,0xFF, +0xE0,0x00,0x00,0x7F,0xF6,0x80,0x00,0x07,0xFF,0xE8, +0x00,0x00,0x7F,0xFD,0x00,0x00,0x07,0xFF,0xE0,0x00, +0x00,0xFF,0xF0,0x00,0x00,0x7F,0xF2,0x40,0x00,0x0F, +0xFF,0x20,0x00,0x00,0xFF,0xE2,0x00,0x00,0x1F,0xFE, +0x20,0x00,0x01,0xFF,0xC0,0x00,0x01,0xFF,0xE1,0x00, +0x00,0x1F,0xFC,0x00,0x00,0x1F,0xFE,0x08,0x00,0x01, +0xFF,0xC0,0x80,0x00,0x3F,0xF8,0x00,0x00,0x1F,0xF8, +0x04,0x00,0x03,0xFF,0x80,0x00,0x01,0xFF,0x80,0x00, +0x01,0xFF,0xC0,0x00,0x00,0xFF,0xC0,0x00,0x00,0xFF, +0xE0,0x00,0x00,0x7F,0xE0,0x00,0x00,0x7F,0xF0,0x00, +0x00,0x3F,0xF0,0x00,0x80,0x07,0xFE,0x00,0x08,0x00, +0xFF,0xC0,0x00,0x00,0xFF,0xC0,0x00,0x00,0x7F,0xC0, +0x00,0x00,0x7F,0xE0,0x00,0x00,0x3F,0xE0,0x00,0x08, +0x07,0xFC,0x00,0x00,0x07,0xFC,0x00,0x00,0x40,0xFF, +0x80,0x00,0x00,0xFF,0x80,0x00,0x00,0x7F,0x80,0x00, +0x00,0x7F,0x80,0x00,0x00,0x7F,0x80,0x00,0x00,0x00, +0x0B,0x14,0x10,0xDC,0xD3,0x40,0x00,0x1F,0xF8,0x00, +0x00,0x00,0x00,0xFF,0x80,0x00,0x10,0x00,0x00,0x7F, +0x80,0x00,0x01,0x80,0x03,0xFC,0x00,0x18,0x1F,0x80, +0x1F,0xE0,0x07,0xE0,0xFF,0x00,0xFF,0x00,0xFF,0x07, +0xFF,0x07,0xF8,0x3F,0xF8,0x7F,0xFE,0x3F,0xC7,0xFF, +0xE3,0xFF,0xFD,0xFC,0xFF,0xFF,0x1F,0xFF,0xFF,0xFF, +0xFF,0xFA,0x3F,0xFF,0xFF,0xFF,0xFF,0xFC,0x7F,0xFF, +0xFF,0xFF,0xFF,0x80,0x3F,0xFF,0xFF,0xFF,0xE0,0x00, +0x0F,0xFF,0xFF,0xF0,0x00,0x00,0x03,0xFF,0xC0,0x00, +0x00,0x00,0x3F,0xFF,0x00,0x00,0x00,0x03,0xFF,0xFC, +0x00,0x00,0x00,0x3F,0xFF,0xF0,0x00,0x00,0x03,0xFF, +0xFF,0xC0,0x00,0x00,0x3F,0xF3,0xFF,0x00,0x00,0x03, +0xFF,0x9F,0xFC,0x00,0x00,0x1F,0xF8,0x7F,0xF0,0x00, +0x01,0xFF,0x83,0xFF,0x80,0x00,0x1F,0xFC,0x0F,0xFE, +0x00,0x01,0xFF,0xC0,0x3F,0xF8,0x00,0x1F,0xFE,0x01, +0xFF,0xE0,0x01,0xFF,0xE0,0x07,0xFF,0x80,0x03,0xFE, +0x00,0x1F,0xF8,0x00,0x0F,0xF0,0x00,0xFF,0x00,0x00, +0x3F,0x00,0x03,0xF0,0x00,0x00,0x70,0x00,0x0E,0x00, +0x00,0x01,0x00,0x00,0x20,0x00,0x0F,0xDF,0x9C,0x3D, +0x3B,0x40,0x00,0x00,0x0F,0xFE,0x00,0x00,0x00,0x68, +0x00,0x00,0x01,0xFF,0xC0,0x00,0x00,0x0D,0x00,0x00, +0x00,0x3F,0xF8,0x00,0x00,0x01,0x60,0x00,0x00,0x07, +0xFF,0x00,0x00,0x00,0x37,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFD,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xD0,0x00,0x00,0x03,0xFF,0x80,0x00,0x00,0x1A, +0x00,0x00,0x00,0x7F,0xF0,0x00,0x00,0x03,0x40,0x00, +0x00,0x0F,0xFE,0x00,0x00,0x00,0x58,0x00,0x00,0x01, +0xFF,0xC0,0x00,0x00,0x00,0x03,0x10,0x33,0xB0,0x97, +0x7F,0xFE,0xFF,0xFE,0xC0,0xFE,0x01,0xFE,0x01,0xFA, +0x03,0xF8,0x1F,0x81,0xFC,0x1F,0xC1,0xFE,0x1F,0xE0, +0x7E,0x01,0xE0,0x0E,0x00,0x20,0x00,0x09,0x05,0x90, +0x74,0xB3,0x7F,0xFF,0xFF,0xFF,0xFE,0xBF,0xFF,0xFF, +0xFF,0xFC,0x03,0x06,0x30,0x00,0x97,0x7F,0xFE,0xFF, +0xFC,0x09,0xAF,0x80,0x00,0x96,0x00,0x00,0x00,0x03, +0xFF,0x00,0x00,0x00,0x0F,0xFF,0x00,0x00,0x00,0x03, +0xFF,0x00,0x00,0x00,0x0F,0xFE,0x80,0x00,0x00,0x03, +0xFF,0x20,0x00,0x00,0x01,0xFF,0xC8,0x00,0x00,0x00, +0x7F,0xE0,0x00,0x00,0x01,0xFF,0xC4,0x00,0x00,0x00, +0x7F,0xE1,0x00,0x00,0x00,0x3F,0xF8,0x40,0x00,0x00, +0x0F,0xFC,0x00,0x00,0x00,0x3F,0xF8,0x20,0x00,0x00, +0x0F,0xFC,0x00,0x00,0x00,0x3F,0xF8,0x10,0x00,0x00, +0x0F,0xFC,0x04,0x00,0x00,0x07,0xFF,0x01,0x00,0x00, +0x01,0xFF,0x80,0x00,0x00,0x07,0xFF,0x00,0x80,0x00, +0x01,0xFF,0x80,0x20,0x00,0x00,0xFF,0xE0,0x08,0x00, +0x00,0x3F,0xF0,0x00,0x00,0x00,0xFF,0xE0,0x04,0x00, +0x00,0x3F,0xF0,0x00,0x00,0x00,0xFF,0xE0,0x02,0x00, +0x00,0x3F,0xF0,0x00,0x80,0x00,0x1F,0xFC,0x00,0x20, +0x00,0x07,0xFE,0x00,0x00,0x00,0x1F,0xFC,0x00,0x10, +0x00,0x07,0xFE,0x00,0x04,0x00,0x03,0xFF,0x80,0x01, +0x00,0x00,0xFF,0xC0,0x00,0x00,0x03,0xFF,0x80,0x00, +0x80,0x00,0xFF,0xC0,0x00,0x00,0x03,0xFF,0x80,0x00, +0x40,0x00,0xFF,0xC0,0x00,0x10,0x00,0x7F,0xF0,0x00, +0x04,0x00,0x1F,0xF8,0x00,0x00,0x00,0x7F,0xF0,0x00, +0x02,0x00,0x1F,0xF8,0x00,0x00,0x80,0x0F,0xFE,0x00, +0x00,0x00,0x1F,0xF8,0x00,0x00,0x40,0x0F,0xFE,0x00, +0x00,0x10,0x03,0xFF,0x00,0x00,0x00,0x0F,0xFE,0x00, +0x00,0x08,0x03,0xFF,0x00,0x00,0x02,0x01,0xFF,0xC0, +0x00,0x00,0x80,0x7F,0xE0,0x00,0x00,0x01,0xFF,0xC0, +0x00,0x00,0x40,0x7F,0xE0,0x00,0x00,0x01,0xFF,0xC0, +0x00,0x00,0x20,0x7F,0xE0,0x00,0x00,0x08,0x3F,0xF8, +0x00,0x00,0x02,0x0F,0xFC,0x00,0x00,0x00,0x3F,0xF8, +0x00,0x00,0x01,0x0F,0xFC,0x00,0x00,0x00,0x47,0xFF, +0x00,0x00,0x00,0x00,0x0F,0xB0,0x1B,0xFD,0x28,0x00, +0x00,0x00,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x1F, +0xFF,0xFE,0x00,0x00,0x00,0x00,0x01,0xFF,0xFF,0xFF, +0x00,0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFF,0x80,0x00, +0x00,0x00,0x3F,0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x01, +0xFF,0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x07,0xFF,0xFF, +0xFF,0xFF,0xE0,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xFF, +0xE0,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xE0,0x04, +0x00,0x3F,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0xFF, +0xFF,0xE0,0x1F,0xFF,0xFC,0x00,0x03,0xFF,0xFE,0x00, +0x07,0xFF,0xFC,0x00,0x07,0xFF,0xF0,0x00,0x03,0xFF, +0xF8,0x00,0x1F,0xFF,0xC0,0x00,0x03,0xFF,0xF8,0x00, +0x3F,0xFF,0x00,0x00,0x03,0xFF,0xF0,0x00,0xFF,0xFC, +0x00,0x00,0x03,0xFF,0xF0,0x01,0xFF,0xF0,0x00,0x00, +0x03,0xFF,0xE0,0x07,0xFF,0xC0,0x00,0x00,0x03,0xFF, +0xC0,0x0F,0xFF,0x80,0x00,0x00,0x07,0xFF,0xC0,0x1F, +0xFE,0x00,0x00,0x00,0x07,0xFF,0x80,0x7F,0xFC,0x00, +0x00,0x00,0x0F,0xFF,0x88,0x1F,0xFE,0x00,0x00,0x00, +0x01,0xFF,0xE0,0x7F,0xFC,0x00,0x00,0x00,0x03,0xFF, +0xC5,0x1F,0xFE,0x00,0x00,0x00,0x00,0x7F,0xF9,0xAF, +0xFF,0x00,0x00,0x00,0x00,0x0F,0xFF,0x6F,0xFF,0x80, +0x00,0x00,0x00,0x01,0xFF,0xFB,0xFF,0xE0,0x00,0x00, +0x00,0x00,0x7F,0xFE,0xFF,0xF8,0x00,0x00,0x00,0x00, +0x1F,0xFF,0x3F,0xFE,0x00,0x00,0x00,0x00,0x07,0xFF, +0x9F,0xFC,0x00,0x00,0x00,0x00,0x1F,0xFE,0xC7,0xFF, +0x80,0x00,0x00,0x00,0x07,0xFF,0x87,0xFF,0x00,0x00, +0x00,0x00,0x1F,0xFE,0x49,0xFF,0xE0,0x00,0x00,0x00, +0x07,0xFF,0x83,0xFF,0xC0,0x00,0x00,0x00,0x1F,0xFF, +0x20,0x7F,0xF8,0x00,0x00,0x00,0x07,0xFF,0x80,0xFF, +0xF8,0x00,0x00,0x00,0x1F,0xFF,0x00,0xFF,0xF0,0x00, +0x00,0x00,0x3F,0xFC,0x20,0x3F,0xFE,0x00,0x00,0x00, +0x1F,0xFF,0x00,0x3F,0xFE,0x00,0x00,0x00,0x7F,0xFC, +0x00,0x7F,0xFE,0x00,0x00,0x01,0xFF,0xF8,0x00,0x7F, +0xFE,0x00,0x00,0x07,0xFF,0xE0,0x00,0xFF,0xFE,0x00, +0x00,0x1F,0xFF,0xC0,0x00,0xFF,0xFE,0x00,0x00,0x7F, +0xFF,0x00,0x01,0xFF,0xFF,0x00,0x03,0xFF,0xFE,0x00, +0x01,0xFF,0xFF,0xC0,0x3F,0xFF,0xF8,0x00,0x03,0xFF, +0xFF,0xFF,0xFF,0xFF,0xE0,0x00,0x03,0xFF,0xFF,0xFF, +0xFF,0xFF,0xC0,0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xFF, +0x00,0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x00, +0x03,0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x03,0xFF, +0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x01,0xFF,0xFF,0xFF, +0xFE,0x00,0x00,0x00,0x01,0xFF,0xFF,0xFF,0xF8,0x00, +0x00,0x00,0x00,0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x00, +0x00,0x3F,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x07, +0xFF,0x80,0x00,0x00,0x00,0x08,0xEF,0xB8,0x01,0x28, +0x00,0x00,0x00,0x3F,0xE0,0x00,0x00,0x00,0xFF,0x80, +0x00,0x00,0x1F,0xFC,0x00,0x00,0x00,0x7F,0xF0,0x00, +0x00,0x0F,0xFF,0x00,0x00,0x01,0xFF,0xF0,0x00,0x00, +0x3F,0xFF,0x00,0x00,0x07,0xFF,0xF0,0x00,0x00,0xFF, +0xFF,0x00,0x00,0x1F,0xFF,0xF0,0x00,0x03,0xFF,0xFF, +0x00,0x00,0x7F,0xFF,0xF0,0x00,0x0F,0xFF,0xFF,0x00, +0x01,0xFF,0xFF,0xF0,0x00,0x7F,0xFF,0xFF,0x00,0x0F, +0xFF,0xFF,0xF0,0x03,0xFF,0xFF,0xFF,0x00,0x7F,0xFF, +0xFF,0xF0,0x1F,0xFF,0xFF,0xFF,0x07,0xFF,0xFE,0xFF, +0xF0,0xFF,0xFF,0xCF,0xFF,0x3F,0xFF,0xF8,0xFF,0xF7, +0xFF,0xFF,0x0F,0xFF,0x7F,0xFF,0xC0,0xFF,0xF7,0xFF, +0xF8,0x0F,0xFF,0x7F,0xFF,0x00,0xFF,0xF7,0xFF,0xC0, +0x0F,0xFF,0x7F,0xF0,0x00,0xFF,0xF7,0xFC,0x00,0x0F, +0xFF,0x7F,0x80,0x00,0xFF,0xF7,0xE0,0x00,0x0F,0xFF, +0x78,0x00,0x00,0xFF,0xF4,0x00,0x00,0x0F,0xFF,0xD0, +0x00,0x00,0x1F,0xFF,0xA0,0x00,0x00,0x3F,0xFF,0x40, +0x00,0x00,0x7F,0xFE,0x80,0x00,0x00,0xFF,0xFD,0x00, +0x00,0x01,0xFF,0xFA,0x00,0x00,0x03,0xFF,0xF4,0x00, +0x00,0x07,0xFF,0xE8,0x00,0x00,0x0F,0xFF,0xA0,0x00, +0x00,0x1F,0xFE,0x0F,0xAF,0x90,0x01,0x28,0x00,0x00, +0x00,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF, +0xFF,0x80,0x00,0x00,0x00,0x01,0xFF,0xFF,0xFF,0xE0, +0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFF,0xF0,0x00,0x00, +0x00,0x7F,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x01,0xFF, +0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x07,0xFF,0xFF,0xFF, +0xFF,0xF8,0x00,0x00,0x3F,0xFF,0xFF,0xFF,0xFF,0xF8, +0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x01, +0xFF,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x07,0xFF,0xFF, +0xFF,0xFF,0xFF,0xF8,0x00,0x1F,0xFF,0xFE,0x00,0xFF, +0xFF,0xF8,0x00,0x7F,0xFF,0xE0,0x00,0x1F,0xFF,0xF0, +0x00,0xFF,0xFF,0x00,0x00,0x0F,0xFF,0xF0,0x03,0xFF, +0xF8,0x00,0x00,0x0F,0xFF,0xE0,0x07,0xFF,0xE0,0x00, +0x00,0x0F,0xFF,0xE0,0x1F,0xFF,0x80,0x00,0x00,0x0F, +0xFF,0xC0,0x3F,0xFE,0x00,0x00,0x00,0x0F,0xFF,0xC0, +0x7F,0xFC,0x00,0x00,0x00,0x0F,0xFF,0x81,0xFF,0xF0, +0x00,0x00,0x00,0x1F,0xFF,0x03,0xFF,0xE0,0x00,0x00, +0x00,0x1F,0xFE,0x40,0xFF,0xF0,0x00,0x00,0x00,0x07, +0xFF,0xC3,0xFF,0xE0,0x00,0x00,0x00,0x07,0xFF,0xA4, +0xFF,0xF0,0x00,0x00,0x00,0x01,0xFF,0xE0,0x3F,0xE0, +0x00,0x00,0x00,0x03,0xFF,0xC0,0x01,0xC0,0x00,0x00, +0x00,0x07,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x0F, +0xFF,0x40,0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xC0, +0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0x24,0x00,0x00, +0x00,0x00,0x00,0x07,0xFF,0xC0,0x00,0x00,0x00,0x00, +0x00,0x1F,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x7F, +0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xF8,0x00, +0x00,0x00,0x00,0x00,0x03,0xFF,0xF0,0x00,0x00,0x00, +0x00,0x00,0x0F,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00, +0x3F,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x7F,0xFE, +0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xFC,0x00,0x00, +0x00,0x00,0x00,0x07,0xFF,0xF0,0x00,0x00,0x00,0x00, +0x00,0x1F,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x7F, +0xFF,0x80,0x00,0x00,0x00,0x00,0x01,0xFF,0xFE,0x00, +0x00,0x00,0x00,0x00,0x07,0xFF,0xF8,0x00,0x00,0x00, +0x00,0x00,0x1F,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00, +0x7F,0xFF,0x80,0x00,0x00,0x00,0x00,0x01,0xFF,0xFE, +0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0xF8,0x00,0x00, +0x00,0x00,0x00,0x3F,0xFF,0xE0,0x00,0x00,0x00,0x00, +0x00,0xFF,0xFF,0x80,0x00,0x00,0x00,0x00,0x03,0xFF, +0xFE,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0xF8,0x00, +0x00,0x00,0x00,0x00,0x3F,0xFF,0xE0,0x00,0x00,0x00, +0x00,0x00,0xFF,0xFF,0x80,0x00,0x00,0x00,0x00,0x07, +0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xF8, +0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0xE0,0x00,0x00, +0x00,0x00,0x01,0xFF,0xFF,0x80,0x00,0x00,0x00,0x00, +0x07,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xC0,0x00, +0x00,0x00,0x00,0x03,0xFF,0xFF,0x00,0x00,0x00,0x00, +0x00,0x0F,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x3F, +0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x80, +0x00,0x00,0x00,0x00,0x03,0xFF,0xFE,0x00,0x00,0x00, +0x00,0x00,0x0F,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00, +0x3F,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF, +0x80,0x00,0x00,0x00,0x00,0x01,0xFF,0xFE,0x00,0x00, +0x00,0x00,0x00,0x07,0xFF,0xF8,0x00,0x00,0x00,0x00, +0x08,0x03,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x0F, +0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0x80, +0x00,0x00,0x00,0x00,0x00,0x7F,0xFE,0x00,0x00,0x00, +0x00,0x00,0x10,0x3F,0xFF,0x00,0x00,0x00,0x00,0x00, +0x04,0x9F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x2F, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xE7,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xE0,0x0F,0xB0,0x1B,0xFD, +0x28,0x00,0x00,0x01,0xFF,0xC0,0x00,0x00,0x00,0x00, +0x00,0x3F,0xFF,0xF8,0x00,0x00,0x00,0x00,0x03,0xFF, +0xFF,0xFE,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF,0xFF, +0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0x80,0x00, +0x00,0x03,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x00,0x0F, +0xFF,0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x3F,0xFF,0xFF, +0xFF,0xFF,0xC0,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF, +0xC0,0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xC0,0x00, +0x0F,0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x3F,0xFF, +0xF8,0x03,0xFF,0xFF,0x80,0x00,0x7F,0xFF,0x80,0x00, +0xFF,0xFF,0x80,0x01,0xFF,0xFE,0x00,0x00,0x7F,0xFF, +0x00,0x07,0xFF,0xF0,0x00,0x00,0x7F,0xFF,0x00,0x0F, +0xFF,0xC0,0x00,0x00,0x7F,0xFE,0x00,0x3F,0xFF,0x00, +0x00,0x00,0x7F,0xFE,0x00,0x7F,0xFE,0x00,0x00,0x00, +0x7F,0xFC,0x00,0xFF,0xF8,0x00,0x00,0x00,0x7F,0xF8, +0x03,0xFF,0xE0,0x00,0x00,0x00,0xFF,0xF0,0x07,0xFF, +0xC0,0x00,0x00,0x01,0xFF,0xF0,0x41,0xFF,0xE0,0x00, +0x00,0x00,0x3F,0xFC,0x07,0xFF,0xC0,0x00,0x00,0x00, +0x7F,0xF8,0x0F,0xFF,0x00,0x00,0x00,0x00,0xFF,0xF0, +0x03,0xFE,0x00,0x00,0x00,0x01,0xFF,0xE0,0x00,0x1C, +0x00,0x00,0x00,0x03,0xFF,0xC1,0x00,0x00,0x00,0x00, +0x00,0x00,0xFF,0xF0,0x40,0x00,0x00,0x00,0x00,0x00, +0x7F,0xF8,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xF0, +0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xC0,0x00,0x00, +0x00,0x00,0x00,0x0F,0xFF,0x80,0x00,0x00,0x00,0x00, +0x00,0x3F,0xFE,0x00,0x00,0x00,0x00,0x00,0x01,0xFF, +0xF8,0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xF0,0x00, +0x00,0x00,0x00,0x00,0x7F,0xFF,0xC0,0x00,0x00,0x00, +0x00,0x07,0xFF,0xFF,0x00,0x00,0x00,0x00,0x07,0xFF, +0xFF,0xFC,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF,0xE0, +0x00,0x00,0x00,0x00,0x3F,0xFF,0xFF,0x80,0x00,0x00, +0x00,0x00,0x7F,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00, +0xFF,0xFF,0xFC,0x00,0x00,0x00,0x00,0x01,0xFF,0xFF, +0xFE,0x00,0x00,0x00,0x00,0x03,0xFF,0xFF,0xFF,0x80, +0x00,0x00,0x00,0x07,0xFF,0xFF,0xFF,0x80,0x00,0x00, +0x00,0x0F,0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x00,0x3F, +0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x00,0x60,0x01,0xFF, +0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0xC0, +0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0x80,0x00,0x00, +0x00,0x00,0x00,0x3F,0xFF,0x80,0x00,0x00,0x00,0x00, +0x00,0x1F,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x1F, +0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0x00, +0x00,0x00,0x00,0x00,0x00,0x3F,0xFE,0x40,0x00,0x00, +0x00,0x00,0x00,0x07,0xFF,0xD0,0x00,0x00,0x00,0x00, +0x00,0x00,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x01, +0xFF,0xFB,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFC, +0x00,0xE0,0x00,0x00,0x00,0x00,0x7F,0xF8,0x7F,0xC0, +0x00,0x00,0x00,0x00,0xFF,0xF8,0xFF,0xF8,0x00,0x00, +0x00,0x00,0x3F,0xFD,0xFF,0xF0,0x00,0x00,0x00,0x00, +0xFF,0xF9,0xFF,0xE0,0x00,0x00,0x00,0x01,0xFF,0xE3, +0xFF,0xE0,0x00,0x00,0x00,0x03,0xFF,0xC7,0xFF,0xC0, +0x00,0x00,0x00,0x0F,0xFF,0x8F,0xFF,0xC0,0x00,0x00, +0x00,0x1F,0xFF,0x0F,0xFF,0x80,0x00,0x00,0x00,0x7F, +0xFC,0x1F,0xFF,0x80,0x00,0x00,0x01,0xFF,0xF8,0x3F, +0xFF,0x80,0x00,0x00,0x03,0xFF,0xE0,0x3F,0xFF,0x00, +0x00,0x00,0x0F,0xFF,0xC0,0x7F,0xFF,0x00,0x00,0x00, +0x3F,0xFF,0x00,0x7F,0xFF,0x00,0x00,0x01,0xFF,0xFE, +0x00,0xFF,0xFF,0x80,0x00,0x07,0xFF,0xF8,0x00,0xFF, +0xFF,0xC0,0x00,0x3F,0xFF,0xE0,0x00,0xFF,0xFF,0xF0, +0x07,0xFF,0xFF,0xC0,0x00,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0x00,0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xFC,0x00, +0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x01,0xFF, +0xFF,0xFF,0xFF,0xFF,0xC0,0x00,0x00,0xFF,0xFF,0xFF, +0xFF,0xFE,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xF8, +0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xE0,0x00,0x00, +0x00,0x7F,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x3F, +0xFF,0xFF,0xF8,0x00,0x00,0x00,0x00,0x0F,0xFF,0xFF, +0x80,0x00,0x00,0x00,0x00,0x01,0xFF,0xE0,0x00,0x00, +0x00,0x10,0xAF,0x08,0x01,0x28,0x00,0x00,0x00,0x00, +0x00,0x0F,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x03, +0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xE0, +0x01,0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0x80,0x00, +0x00,0x00,0x00,0x00,0x01,0xFF,0xF0,0x00,0x00,0x00, +0x00,0x00,0x00,0x7F,0xFE,0x00,0x00,0x00,0x00,0x00, +0x00,0x1F,0xFF,0xC0,0x02,0x00,0x00,0x00,0x00,0x00, +0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF, +0xE0,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0xFC,0x00, +0x20,0x00,0x00,0x00,0x00,0x7F,0xFF,0xF0,0x00,0x00, +0x00,0x00,0x00,0x1F,0xFF,0xFE,0x00,0x00,0x00,0x00, +0x00,0x07,0xFF,0xFF,0xC0,0x02,0x00,0x00,0x00,0x00, +0x3F,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF, +0xFF,0xE0,0x00,0x00,0x00,0x00,0x03,0xFF,0xFF,0xFC, +0x00,0x20,0x00,0x00,0x00,0x1F,0xFF,0xFF,0xF0,0x00, +0x00,0x00,0x00,0x07,0xFF,0xFF,0xFE,0x00,0x00,0x00, +0x00,0x01,0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x00,0x00, +0x7F,0xFF,0x7F,0xF8,0x00,0x00,0x00,0x00,0x0F,0xFF, +0xCF,0xFF,0x00,0x00,0x00,0x00,0x03,0xFF,0xF9,0xFF, +0xE0,0x00,0x00,0x00,0x00,0xFF,0xFE,0x3F,0xFC,0x00, +0x00,0x00,0x00,0x3F,0xFF,0x87,0xFF,0x80,0x04,0x00, +0x00,0x01,0xFF,0xFC,0x1F,0xFE,0x00,0x00,0x00,0x00, +0x7F,0xFF,0x03,0xFF,0xC0,0x00,0x00,0x00,0x1F,0xFF, +0xC0,0x7F,0xF8,0x00,0x40,0x00,0x00,0xFF,0xFE,0x01, +0xFF,0xE0,0x00,0x00,0x00,0x3F,0xFF,0x80,0x3F,0xFC, +0x00,0x00,0x00,0x0F,0xFF,0xE0,0x07,0xFF,0x80,0x00, +0x00,0x03,0xFF,0xF8,0x00,0xFF,0xF0,0x00,0x00,0x00, +0x7F,0xFE,0x00,0x1F,0xFE,0x00,0x00,0x00,0x1F,0xFF, +0xC0,0x03,0xFF,0xC0,0x00,0x00,0x07,0xFF,0xF0,0x00, +0x7F,0xF8,0x00,0x00,0x01,0xFF,0xFC,0x00,0x0F,0xFF, +0x00,0x00,0x00,0x3F,0xFF,0x00,0x01,0xFF,0xE0,0x00, +0x00,0x0F,0xFF,0xE0,0x00,0x3F,0xFC,0x00,0x00,0x03, +0xFF,0xF8,0x00,0x07,0xFF,0x80,0x00,0x00,0xFF,0xFE, +0x00,0x00,0xFF,0xF0,0x00,0x00,0x1F,0xFF,0x80,0x00, +0x1F,0xFE,0x00,0x00,0x07,0xFF,0xF0,0x00,0x03,0xFF, +0xC0,0x00,0x01,0xFF,0xFC,0x00,0x00,0x7F,0xF8,0x00, +0x00,0x7F,0xFF,0x00,0x00,0x0F,0xFF,0x00,0x08,0x03, +0xFF,0xF8,0x00,0x00,0x3F,0xFC,0x00,0x00,0xFF,0xFE, +0x00,0x00,0x07,0xFF,0x80,0x00,0x3F,0xFF,0x80,0x00, +0x00,0xFF,0xF0,0x00,0x0F,0xFF,0xE0,0x00,0x00,0x1F, +0xFE,0x00,0x01,0xFF,0xF8,0x00,0x00,0x03,0xFF,0xC0, +0x00,0x7F,0xFF,0x00,0x00,0x00,0x7F,0xF8,0x00,0x1F, +0xFF,0xC0,0x00,0x00,0x0F,0xFF,0x00,0x07,0xFF,0xF0, +0x00,0x00,0x01,0xFF,0xE0,0x01,0xBF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFD,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFA,0x00,0x00,0x00,0x00,0x00,0x7F, +0xF8,0x00,0x68,0x00,0x00,0x00,0x00,0x01,0xFF,0xE0, +0x01,0xA0,0x00,0x00,0x00,0x00,0x07,0xFF,0x80,0x04, +0x00,0x00,0x00,0x00,0x00,0x1F,0xFE,0x00,0x00,0x0F, +0xAF,0x9B,0xFD,0x2A,0x00,0x03,0xFF,0xFF,0xFF,0xFF, +0xFF,0xE0,0xB0,0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xF8, +0x2C,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE,0x00,0x03, +0xFF,0xE0,0x00,0x00,0x00,0x00,0x14,0x00,0xFF,0xF0, +0x00,0x00,0x00,0x00,0x04,0x00,0x7F,0xFC,0x00,0x00, +0x00,0x00,0x01,0x20,0x1F,0xFE,0x00,0x00,0x00,0x00, +0x00,0x40,0x0F,0xFF,0x80,0x00,0x00,0x00,0x00,0x12, +0x03,0xFF,0xC0,0x00,0x00,0x00,0x00,0x04,0x01,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x01,0x00,0x7F,0xF8,0x00, +0x00,0x00,0x00,0x00,0x00,0xFF,0xF0,0x01,0xFF,0x80, +0x00,0x00,0x03,0xFF,0xE0,0x1F,0xFF,0xF0,0x00,0x00, +0x07,0xFF,0xC1,0xFF,0xFF,0xFC,0x00,0x00,0x0F,0xFF, +0x8F,0xFF,0xFF,0xFC,0x00,0x00,0x1F,0xFE,0x3F,0xFF, +0xFF,0xFE,0x00,0x00,0x3F,0xFD,0xFF,0xFF,0xFF,0xFE, +0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x01, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x03,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0x00,0x07,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0x00,0x0F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0x00,0x3F,0xFF,0xFF,0x80,0x1F,0xFF,0xFE,0x00,0x7F, +0xFF,0xF8,0x00,0x07,0xFF,0xFE,0x00,0xFF,0xFF,0xC0, +0x00,0x03,0xFF,0xFE,0x01,0xFF,0xFE,0x00,0x00,0x01, +0xFF,0xFC,0x03,0xFF,0xF8,0x00,0x00,0x01,0xFF,0xFC, +0x0F,0xFF,0xE0,0x00,0x00,0x01,0xFF,0xF8,0x1F,0xFF, +0x80,0x00,0x00,0x01,0xFF,0xF8,0x07,0xFE,0x00,0x00, +0x00,0x01,0xFF,0xF0,0x00,0x38,0x00,0x00,0x00,0x03, +0xFF,0xE4,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFD, +0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0x40,0x00, +0x00,0x00,0x00,0x00,0x03,0xFF,0xFA,0x00,0x00,0x00, +0x00,0x00,0x00,0x7F,0xFC,0x80,0x00,0x00,0x00,0x00, +0x00,0x1F,0xFE,0x03,0xF0,0x00,0x00,0x00,0x00,0x3F, +0xFE,0x3F,0xFC,0x00,0x00,0x00,0x00,0x1F,0xFE,0x7F, +0xFC,0x00,0x00,0x00,0x00,0x3F,0xFC,0xFF,0xF8,0x00, +0x00,0x00,0x00,0xFF,0xF8,0xFF,0xF0,0x00,0x00,0x00, +0x01,0xFF,0xE1,0xFF,0xF0,0x00,0x00,0x00,0x03,0xFF, +0xC3,0xFF,0xE0,0x00,0x00,0x00,0x0F,0xFF,0x87,0xFF, +0xE0,0x00,0x00,0x00,0x3F,0xFE,0x07,0xFF,0xC0,0x00, +0x00,0x00,0x7F,0xFC,0x0F,0xFF,0xC0,0x00,0x00,0x01, +0xFF,0xF0,0x0F,0xFF,0xC0,0x00,0x00,0x07,0xFF,0xE0, +0x1F,0xFF,0xC0,0x00,0x00,0x1F,0xFF,0x80,0x1F,0xFF, +0xC0,0x00,0x00,0x7F,0xFF,0x00,0x3F,0xFF,0xC0,0x00, +0x03,0xFF,0xFC,0x00,0x3F,0xFF,0xE0,0x00,0x1F,0xFF, +0xF0,0x00,0x7F,0xFF,0xF8,0x01,0xFF,0xFF,0xE0,0x00, +0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x7F,0xFF, +0xFF,0xFF,0xFF,0xFE,0x00,0x00,0x7F,0xFF,0xFF,0xFF, +0xFF,0xF8,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xE0, +0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x00, +0x7F,0xFF,0xFF,0xFF,0xFE,0x00,0x00,0x00,0x3F,0xFF, +0xFF,0xFF,0xF0,0x00,0x00,0x00,0x1F,0xFF,0xFF,0xFF, +0x80,0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFC,0x00,0x00, +0x00,0x00,0x07,0xFF,0xFF,0xC0,0x00,0x00,0x00,0x00, +0x00,0x7F,0xF8,0x00,0x00,0x00,0x10,0x30,0x13,0xFD, +0x28,0x00,0x00,0x00,0x1F,0xFE,0x00,0x00,0x00,0x00, +0x00,0x00,0xFF,0xFF,0xF0,0x00,0x00,0x00,0x00,0x03, +0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x07,0xFF,0xFF, +0xFF,0xE0,0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFF,0xFC, +0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFF,0xFF,0x00,0x00, +0x00,0x0F,0xFF,0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x1F, +0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x1F,0xFF,0xFF, +0xFF,0xFF,0xFC,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xFF, +0xFF,0x00,0x00,0x0F,0xFF,0xFF,0xFF,0xFF,0xFF,0xC0, +0x00,0x0F,0xFF,0xFE,0x00,0xFF,0xFF,0xE0,0x00,0x0F, +0xFF,0xF8,0x00,0x0F,0xFF,0xF8,0x00,0x0F,0xFF,0xF0, +0x00,0x01,0xFF,0xFE,0x00,0x07,0xFF,0xF0,0x00,0x00, +0x7F,0xFF,0x00,0x07,0xFF,0xF0,0x00,0x00,0x1F,0xFF, +0x80,0x07,0xFF,0xF0,0x00,0x00,0x07,0xFF,0xE0,0x03, +0xFF,0xF0,0x00,0x00,0x01,0xFF,0xF0,0x01,0xFF,0xF0, +0x00,0x00,0x00,0xFF,0xFC,0x01,0xFF,0xF0,0x00,0x00, +0x00,0x3F,0xFE,0x00,0xFF,0xF0,0x00,0x00,0x00,0x1F, +0xFF,0x00,0xFF,0xF8,0x00,0x00,0x00,0x07,0xFF,0x88, +0x0F,0xFF,0x00,0x00,0x00,0x00,0x7F,0xFC,0x0F,0xFF, +0x00,0x00,0x00,0x00,0x1F,0xFE,0x07,0xFF,0x80,0x00, +0x00,0x00,0x0F,0xC0,0x03,0xFF,0xC0,0x00,0x00,0x00, +0x00,0x00,0x12,0x7F,0xF8,0x00,0x00,0x00,0x00,0x00, +0x01,0x07,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x07, +0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xC0, +0x00,0x1F,0xFC,0x00,0x00,0x01,0xFF,0xE0,0x00,0xFF, +0xFF,0xE0,0x00,0x00,0xFF,0xF0,0x01,0xFF,0xFF,0xFC, +0x00,0x00,0x7F,0xF0,0x03,0xFF,0xFF,0xFF,0x80,0x00, +0x3F,0xF8,0x07,0xFF,0xFF,0xFF,0xF0,0x00,0x1F,0xFC, +0x07,0xFF,0xFF,0xFF,0xFC,0x00,0x1F,0xFE,0x0F,0xFF, +0xFF,0xFF,0xFF,0x00,0x0F,0xFF,0x0F,0xFF,0xFF,0xFF, +0xFF,0xE0,0x07,0xFF,0x8F,0xFF,0xFF,0xFF,0xFF,0xF8, +0x03,0xFF,0xCF,0xFF,0xFF,0xFF,0xFF,0xFC,0x01,0xFF, +0xE7,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0xFF,0xF7,0xFF, +0xE0,0x07,0xFF,0xFF,0xC0,0x7F,0xFF,0xFF,0x80,0x00, +0x3F,0xFF,0xF0,0x3F,0xFF,0xFF,0x00,0x00,0x07,0xFF, +0xF8,0x1F,0xFF,0xFE,0x00,0x00,0x01,0xFF,0xFE,0x0F, +0xFF,0xFE,0x00,0x00,0x00,0x3F,0xFF,0x87,0xFF,0xFE, +0x00,0x00,0x00,0x0F,0xFF,0xC3,0xFF,0xFE,0x00,0x00, +0x00,0x03,0xFF,0xF1,0xFF,0xFE,0x00,0x00,0x00,0x01, +0xFF,0xF8,0xFF,0xFE,0x00,0x00,0x00,0x00,0x7F,0xFC, +0x7F,0xFF,0x00,0x00,0x00,0x00,0x1F,0xFF,0x3F,0xFF, +0x00,0x00,0x00,0x00,0x0F,0xFF,0x9F,0xFF,0x80,0x00, +0x00,0x00,0x03,0xFF,0xCF,0xFF,0x80,0x00,0x00,0x00, +0x01,0xFF,0xE8,0xFF,0xF8,0x00,0x00,0x00,0x00,0x1F, +0xFF,0x8F,0xFF,0x00,0x00,0x00,0x00,0x00,0xFF,0xFD, +0x7F,0xF0,0x00,0x00,0x00,0x00,0x0F,0xFF,0x1F,0xFC, +0x00,0x00,0x00,0x00,0x07,0xFF,0x8F,0xFE,0x00,0x00, +0x00,0x00,0x07,0xFF,0xE0,0xFF,0xE0,0x00,0x00,0x00, +0x00,0x7F,0xF8,0x3F,0xF8,0x00,0x00,0x00,0x00,0x3F, +0xFC,0x1F,0xFC,0x00,0x00,0x00,0x00,0x3F,0xFE,0x0F, +0xFF,0x00,0x00,0x00,0x00,0x1F,0xFE,0x03,0xFF,0x80, +0x00,0x00,0x00,0x1F,0xFF,0x01,0xFF,0xE0,0x00,0x00, +0x00,0x0F,0xFF,0x80,0xFF,0xF8,0x00,0x00,0x00,0x0F, +0xFF,0x80,0x3F,0xFE,0x00,0x00,0x00,0x0F,0xFF,0xC0, +0x1F,0xFF,0x00,0x00,0x00,0x0F,0xFF,0xC0,0x07,0xFF, +0xE0,0x00,0x00,0x0F,0xFF,0xE0,0x03,0xFF,0xF8,0x00, +0x00,0x0F,0xFF,0xE0,0x00,0xFF,0xFF,0x00,0x00,0x0F, +0xFF,0xF0,0x00,0x3F,0xFF,0xE0,0x00,0x1F,0xFF,0xF0, +0x00,0x0F,0xFF,0xFE,0x00,0xFF,0xFF,0xF0,0x00,0x07, +0xFF,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x01,0xFF,0xFF, +0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x7F,0xFF,0xFF,0xFF, +0xFF,0xF8,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xF8, +0x00,0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x00, +0x00,0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x00,0x1F, +0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x00,0x07,0xFF,0xFF, +0xFF,0xE0,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xC0, +0x00,0x00,0x00,0x00,0x0F,0xFF,0xFF,0x80,0x00,0x00, +0x00,0x00,0x00,0x3F,0xFC,0x00,0x00,0x00,0x0F,0xAF, +0x18,0x01,0x2B,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0x9F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xDF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x3F,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00, +0x00,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x03,0xFF, +0xE0,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0x80,0x00, +0x00,0x00,0x00,0x00,0x3F,0xFE,0x08,0x00,0x00,0x00, +0x00,0x00,0x1F,0xFF,0x00,0x00,0x00,0x00,0x00,0x00, +0x7F,0xFC,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xF0, +0x08,0x00,0x00,0x00,0x00,0x00,0xFF,0xF8,0x00,0x00, +0x00,0x00,0x00,0x03,0xFF,0xE0,0x04,0x00,0x00,0x00, +0x00,0x01,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x07, +0xFF,0xC0,0x02,0x00,0x00,0x00,0x00,0x03,0xFF,0xE0, +0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0x80,0x00,0x00, +0x00,0x00,0x00,0x3F,0xFF,0x00,0x00,0x00,0x00,0x00, +0x00,0x7F,0xFC,0x00,0x04,0x00,0x00,0x00,0x00,0x3F, +0xFE,0x00,0x01,0x00,0x00,0x00,0x00,0x1F,0xFF,0x00, +0x00,0x00,0x00,0x00,0x00,0x7F,0xFC,0x00,0x00,0x80, +0x00,0x00,0x00,0x3F,0xFE,0x00,0x00,0x20,0x00,0x00, +0x00,0x1F,0xFF,0x00,0x00,0x08,0x00,0x00,0x00,0x0F, +0xFF,0x80,0x00,0x02,0x00,0x00,0x00,0x07,0xFF,0xC0, +0x00,0x00,0x80,0x00,0x00,0x03,0xFF,0xE0,0x00,0x00, +0x00,0x00,0x00,0x07,0xFF,0x80,0x00,0x00,0x40,0x00, +0x00,0x03,0xFF,0xE0,0x00,0x00,0x10,0x00,0x00,0x01, +0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xC0, +0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0x80,0x00,0x00, +0x00,0x00,0x00,0x1F,0xFE,0x00,0x00,0x00,0x20,0x00, +0x00,0x0F,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x1F, +0xFE,0x00,0x00,0x00,0x10,0x00,0x00,0x0F,0xFF,0x80, +0x00,0x00,0x00,0x00,0x00,0x1F,0xFE,0x00,0x00,0x00, +0x00,0x00,0x00,0x7F,0xFC,0x00,0x00,0x00,0x10,0x00, +0x00,0x1F,0xFE,0x00,0x00,0x00,0x04,0x00,0x00,0x0F, +0xFF,0x80,0x00,0x00,0x01,0x00,0x00,0x03,0xFF,0xC0, +0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0x80,0x00,0x00, +0x00,0x80,0x00,0x03,0xFF,0xC0,0x00,0x00,0x00,0x00, +0x00,0x0F,0xFF,0x80,0x00,0x00,0x00,0x50,0x00,0x03, +0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0x80, +0x00,0x00,0x00,0x28,0x00,0x03,0xFF,0xC0,0x00,0x00, +0x00,0x00,0x00,0x0F,0xFF,0x80,0x00,0x00,0x00,0x16, +0x00,0x03,0xFF,0xC0,0x00,0x00,0x00,0x04,0x00,0x01, +0xFF,0xF0,0x00,0x00,0x00,0x01,0x80,0x00,0x7F,0xF8, +0x00,0x00,0x00,0x00,0x00,0x0F,0xB0,0x1B,0xFD,0x28, +0x00,0x00,0x01,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00, +0x3F,0xFF,0xFE,0x00,0x00,0x00,0x00,0x03,0xFF,0xFF, +0xFF,0x80,0x00,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xC0, +0x00,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xE0,0x00,0x00, +0x03,0xFF,0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x0F,0xFF, +0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x3F,0xFF,0xFF,0xFF, +0xFF,0xF0,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0, +0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x0F, +0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x3F,0xFF,0xFC, +0x00,0xFF,0xFF,0xE0,0x00,0x7F,0xFF,0xC0,0x00,0x3F, +0xFF,0xE0,0x01,0xFF,0xFE,0x00,0x00,0x1F,0xFF,0xC0, +0x03,0xFF,0xF8,0x00,0x00,0x1F,0xFF,0xC0,0x0F,0xFF, +0xC0,0x00,0x00,0x1F,0xFF,0x80,0x1F,0xFF,0x80,0x00, +0x00,0x1F,0xFF,0x80,0x3F,0xFE,0x00,0x00,0x00,0x1F, +0xFF,0x00,0xFF,0xF8,0x00,0x00,0x00,0x1F,0xFE,0x01, +0xFF,0xF0,0x00,0x00,0x00,0x3F,0xFE,0x03,0xFF,0xC0, +0x00,0x00,0x00,0x7F,0xFC,0x68,0xFF,0xF0,0x00,0x00, +0x00,0x0F,0xFF,0x10,0x1F,0xFE,0x00,0x00,0x00,0x07, +0xFF,0x80,0x3F,0xFE,0x00,0x00,0x00,0x1F,0xFF,0x08, +0x07,0xFF,0xC0,0x00,0x00,0x0F,0xFF,0x80,0x07,0xFF, +0xC0,0x00,0x00,0x3F,0xFE,0x00,0x0F,0xFF,0xE0,0x00, +0x01,0xFF,0xFC,0x00,0x0F,0xFF,0xF0,0x00,0x0F,0xFF, +0xF0,0x00,0x0F,0xFF,0xFC,0x00,0xFF,0xFF,0xC0,0x00, +0x0F,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x0F,0xFF, +0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x07,0xFF,0xFF,0xFF, +0xFF,0xE0,0x00,0x00,0x07,0xFF,0xFF,0xFF,0xFF,0x80, +0x00,0x00,0x01,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x00, +0x03,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x00,0x1F,0xFF, +0xFF,0xFF,0xF8,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF, +0xFC,0x00,0x00,0x07,0xFF,0xFF,0xFF,0xFF,0xFE,0x00, +0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xFE,0x00,0x00,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFE,0x00,0x03,0xFF,0xFF,0xC0, +0x0F,0xFF,0xFE,0x00,0x07,0xFF,0xFC,0x00,0x03,0xFF, +0xFE,0x00,0x1F,0xFF,0xE0,0x00,0x01,0xFF,0xFE,0x00, +0x7F,0xFF,0x00,0x00,0x00,0xFF,0xFE,0x01,0xFF,0xFC, +0x00,0x00,0x00,0xFF,0xFC,0x03,0xFF,0xF0,0x00,0x00, +0x00,0xFF,0xFC,0x0F,0xFF,0xC0,0x00,0x00,0x00,0xFF, +0xF8,0x83,0xFF,0xE0,0x00,0x00,0x00,0x1F,0xFF,0x21, +0xFF,0xF0,0x00,0x00,0x00,0x03,0xFF,0xE3,0xFF,0xC0, +0x00,0x00,0x00,0x03,0xFF,0xCF,0xFF,0x80,0x00,0x00, +0x00,0x07,0xFF,0x9F,0xFF,0x00,0x00,0x00,0x00,0x0F, +0xFF,0xEF,0xFF,0x80,0x00,0x00,0x00,0x01,0xFF,0xF1, +0xFF,0xE0,0x00,0x00,0x00,0x00,0x7F,0xFB,0xFF,0xE0, +0x00,0x00,0x00,0x01,0xFF,0xF3,0xFF,0xC0,0x00,0x00, +0x00,0x03,0xFF,0xE7,0xFF,0x80,0x00,0x00,0x00,0x07, +0xFF,0xA1,0xFF,0xF0,0x00,0x00,0x00,0x03,0xFF,0xE1, +0xFF,0xE0,0x00,0x00,0x00,0x0F,0xFF,0x83,0xFF,0xE0, +0x00,0x00,0x00,0x1F,0xFF,0x07,0xFF,0xE0,0x00,0x00, +0x00,0x7F,0xFE,0x07,0xFF,0xE0,0x00,0x00,0x01,0xFF, +0xF8,0x0F,0xFF,0xE0,0x00,0x00,0x07,0xFF,0xF0,0x0F, +0xFF,0xE0,0x00,0x00,0x1F,0xFF,0xC0,0x1F,0xFF,0xF0, +0x00,0x00,0xFF,0xFF,0x80,0x1F,0xFF,0xF8,0x00,0x07, +0xFF,0xFE,0x00,0x1F,0xFF,0xFF,0x00,0x7F,0xFF,0xF8, +0x10,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x03, +0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x01,0xFF,0xFF, +0xFF,0xFF,0xFF,0x80,0x00,0x01,0xFF,0xFF,0xFF,0xFF, +0xFE,0x00,0x00,0x01,0xFF,0xFF,0xFF,0xFF,0xF8,0x00, +0x00,0x01,0xFF,0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x00, +0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x7F,0xFF, +0xFF,0xF8,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF,0x80, +0x00,0x00,0x00,0x00,0x03,0xFF,0xE0,0x00,0x00,0x00, +0x0F,0xB0,0x1B,0xFD,0x28,0x00,0x00,0x01,0xFF,0xC0, +0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xF8,0x00,0x00, +0x00,0x00,0x03,0xFF,0xFF,0xFE,0x00,0x00,0x00,0x00, +0x1F,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x7F,0xFF, +0xFF,0xFF,0x80,0x00,0x00,0x03,0xFF,0xFF,0xFF,0xFF, +0x80,0x00,0x00,0x0F,0xFF,0xFF,0xFF,0xFF,0xC0,0x00, +0x00,0x3F,0xFF,0xFF,0xFF,0xFF,0xC0,0x00,0x00,0xFF, +0xFF,0xFF,0xFF,0xFF,0xC0,0x00,0x03,0xFF,0xFF,0xFF, +0xFF,0xFF,0xC0,0x00,0x0F,0xFF,0xFF,0xFF,0xFF,0xFF, +0xC0,0x00,0x3F,0xFF,0xFE,0x00,0xFF,0xFF,0xC0,0x00, +0xFF,0xFF,0xE0,0x00,0x3F,0xFF,0x80,0x01,0xFF,0xFF, +0x00,0x00,0x1F,0xFF,0x80,0x07,0xFF,0xF8,0x00,0x00, +0x1F,0xFF,0x80,0x0F,0xFF,0xE0,0x00,0x00,0x0F,0xFF, +0x00,0x3F,0xFF,0x80,0x00,0x00,0x0F,0xFF,0x00,0x7F, +0xFE,0x00,0x00,0x00,0x0F,0xFE,0x01,0xFF,0xF8,0x00, +0x00,0x00,0x1F,0xFE,0x03,0xFF,0xF0,0x00,0x00,0x00, +0x1F,0xFC,0x07,0xFF,0xC0,0x00,0x00,0x00,0x1F,0xFC, +0x43,0xFF,0xE0,0x00,0x00,0x00,0x07,0xFF,0x07,0xFF, +0xC0,0x00,0x00,0x00,0x07,0xFF,0x0F,0xFF,0x00,0x00, +0x00,0x00,0x0F,0xFE,0x3F,0xFE,0x00,0x00,0x00,0x00, +0x1F,0xFC,0x7F,0xFC,0x00,0x00,0x00,0x00,0x1F,0xF9, +0xBF,0xFE,0x00,0x00,0x00,0x00,0x07,0xFF,0x4F,0xFF, +0x80,0x00,0x00,0x00,0x01,0xFF,0xEF,0xFF,0x00,0x00, +0x00,0x00,0x07,0xFF,0xDF,0xFF,0x00,0x00,0x00,0x00, +0x0F,0xFF,0xC3,0xFF,0xC0,0x00,0x00,0x00,0x03,0xFF, +0xF0,0xFF,0xF8,0x00,0x00,0x00,0x01,0xFF,0xF8,0xFF, +0xF8,0x00,0x00,0x00,0x07,0xFF,0xF1,0xFF,0xF0,0x00, +0x00,0x00,0x1F,0xFF,0xE3,0xFF,0xF0,0x00,0x00,0x00, +0x3F,0xFF,0xC3,0xFF,0xF0,0x00,0x00,0x00,0xFF,0xFF, +0x87,0xFF,0xF0,0x00,0x00,0x03,0xFF,0xFF,0x07,0xFF, +0xF0,0x00,0x00,0x0F,0xFF,0xFE,0x0F,0xFF,0xF8,0x00, +0x00,0x7F,0xFF,0xFC,0x0F,0xFF,0xFC,0x00,0x03,0xFF, +0xFF,0xF8,0x0F,0xFF,0xFF,0x00,0x3F,0xFE,0xFF,0xF0, +0x1F,0xFF,0xFF,0xFF,0xFF,0xFD,0xFF,0xE0,0x1F,0xFF, +0xFF,0xFF,0xFF,0xF3,0xFF,0xC0,0x1F,0xFF,0xFF,0xFF, +0xFF,0xC7,0xFF,0x80,0x1F,0xFF,0xFF,0xFF,0xFF,0x0F, +0xFF,0x00,0x1F,0xFF,0xFF,0xFF,0xFC,0x1F,0xFE,0x00, +0x1F,0xFF,0xFF,0xFF,0xF0,0x3F,0xF8,0x00,0x0F,0xFF, +0xFF,0xFF,0x80,0x7F,0xF0,0x00,0x0F,0xFF,0xFF,0xFE, +0x00,0xFF,0xE0,0x00,0x07,0xFF,0xFF,0xF0,0x01,0xFF, +0xC0,0x00,0x01,0xFF,0xFF,0x00,0x07,0xFF,0x80,0x00, +0x00,0x7F,0xF0,0x00,0x0F,0xFF,0x40,0x00,0x00,0x00, +0x00,0x00,0x03,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00, +0x07,0xFF,0x28,0x00,0x00,0x00,0x00,0x00,0x03,0xFF, +0xC0,0x07,0xE0,0x00,0x00,0x00,0x0F,0xFF,0x10,0x7F, +0xF8,0x00,0x00,0x00,0x03,0xFF,0xC0,0xFF,0xF8,0x00, +0x00,0x00,0x0F,0xFF,0x00,0xFF,0xF0,0x00,0x00,0x00, +0x1F,0xFE,0x01,0xFF,0xE0,0x00,0x00,0x00,0x7F,0xFC, +0x03,0xFF,0xE0,0x00,0x00,0x00,0xFF,0xF0,0x07,0xFF, +0xC0,0x00,0x00,0x03,0xFF,0xE0,0x07,0xFF,0xC0,0x00, +0x00,0x0F,0xFF,0x80,0x0F,0xFF,0x80,0x00,0x00,0x3F, +0xFF,0x00,0x1F,0xFF,0x80,0x00,0x00,0xFF,0xFC,0x00, +0x1F,0xFF,0x80,0x00,0x03,0xFF,0xF8,0x00,0x3F,0xFF, +0x80,0x00,0x0F,0xFF,0xE0,0x00,0x3F,0xFF,0xC0,0x00, +0x7F,0xFF,0x80,0x00,0x7F,0xFF,0xF0,0x07,0xFF,0xFF, +0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x00, +0x7F,0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x7F,0xFF, +0xFF,0xFF,0xFF,0xC0,0x00,0x00,0xFF,0xFF,0xFF,0xFF, +0xFF,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFC,0x00, +0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x00, +0x7F,0xFF,0xFF,0xFF,0x80,0x00,0x00,0x00,0x7F,0xFF, +0xFF,0xFC,0x00,0x00,0x00,0x00,0x3F,0xFF,0xFF,0xE0, +0x00,0x00,0x00,0x00,0x0F,0xFF,0xFE,0x00,0x00,0x00, +0x00,0x00,0x01,0xFF,0xC0,0x00,0x00,0x00,0x03,0x22, +0xB0,0x00,0x97,0x7F,0xFE,0xFF,0xFF,0x40,0x03,0x40, +0x03,0x40,0x03,0x40,0x03,0x40,0x03,0x40,0x02,0x40, +0x03,0x7F,0xFE,0xFF,0xFC,0x03,0x2C,0xB3,0xB0,0x97, +0x7F,0xFE,0xFF,0xFF,0x40,0x03,0x40,0x03,0x40,0x03, +0x40,0x03,0x40,0x03,0x40,0x02,0x40,0x03,0x7F,0xFE, +0xFF,0xFE,0xC0,0xFE,0x01,0xFE,0x01,0xFA,0x03,0xF8, +0x1F,0x81,0xFC,0x1F,0xC1,0xFE,0x1F,0xE0,0x7E,0x01, +0xE0,0x0E,0x00,0x20,0x00,0x0F,0xDF,0x9C,0x41,0x38, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x3C,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0xFC,0x00,0x00,0x00,0x00,0x00,0x00, +0x03,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xFC, +0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFC,0x00,0x00, +0x00,0x00,0x00,0x01,0xFF,0xFC,0x00,0x00,0x00,0x00, +0x00,0x0F,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x3F, +0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFC, +0x00,0x00,0x00,0x00,0x07,0xFF,0xFF,0xFC,0x00,0x00, +0x00,0x00,0x1F,0xFF,0xFF,0xFC,0x00,0x00,0x00,0x00, +0x7F,0xFF,0xFF,0xF8,0x00,0x00,0x00,0x03,0xFF,0xFF, +0xFF,0xC0,0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFE,0x00, +0x00,0x00,0x00,0x3F,0xFF,0xFF,0xF8,0x00,0x00,0x00, +0x01,0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x00,0x07,0xFF, +0xFF,0xFF,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF,0xF8, +0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xC0,0x00,0x00, +0x00,0x03,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x0F, +0xFF,0xFF,0xF8,0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF, +0xE0,0x00,0x00,0x00,0x01,0xFF,0xFF,0xFF,0x00,0x00, +0x00,0x00,0x07,0xFF,0xFF,0xF8,0x00,0x00,0x00,0x00, +0x3F,0xFF,0xFF,0xE0,0x00,0x00,0x00,0x00,0xFF,0xFF, +0xFF,0x00,0x00,0x00,0x00,0x01,0xFF,0xFF,0xF8,0x00, +0x00,0x00,0x00,0x01,0xFF,0xFF,0xE0,0x00,0x00,0x00, +0x00,0x01,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x01, +0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xE0, +0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xFC,0x00,0x00, +0x00,0x00,0x00,0x01,0xFF,0xFF,0x00,0x00,0x00,0x00, +0x00,0x01,0xFF,0xFF,0xE0,0x00,0x00,0x00,0x00,0x01, +0xFF,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF, +0xFF,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xFF,0xE0, +0x00,0x00,0x00,0x00,0x07,0xFF,0xFF,0xF8,0x00,0x00, +0x00,0x00,0x01,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00, +0x00,0x7F,0xFF,0xFF,0xE0,0x00,0x00,0x00,0x00,0x0F, +0xFF,0xFF,0xF8,0x00,0x00,0x00,0x00,0x03,0xFF,0xFF, +0xFF,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xC0, +0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF,0xF8,0x00,0x00, +0x00,0x00,0x07,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00, +0x01,0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x00,0x00,0x3F, +0xFF,0xFF,0xF8,0x00,0x00,0x00,0x00,0x0F,0xFF,0xFF, +0xFE,0x00,0x00,0x00,0x00,0x03,0xFF,0xFF,0xFF,0xC0, +0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF,0xF8,0x00,0x00, +0x00,0x00,0x1F,0xFF,0xFF,0xFC,0x00,0x00,0x00,0x00, +0x07,0xFF,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0xFF, +0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xFC, +0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0xFC,0x00,0x00, +0x00,0x00,0x00,0x01,0xFF,0xFC,0x00,0x00,0x00,0x00, +0x00,0x00,0x7F,0xFC,0x00,0x00,0x00,0x00,0x00,0x00, +0x1F,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xFC, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFC,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x3C,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x04,0x0F,0xD4,0x1C,0x6D,0x3B,0x7F, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xDF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFD,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x01,0xA0,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x06,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xBF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xE0,0x0F,0xDF, +0x9C,0x41,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x01,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xF8, +0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xFE,0x00,0x00, +0x00,0x00,0x00,0x00,0x01,0xFF,0xC0,0x00,0x00,0x00, +0x00,0x00,0x01,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00, +0x01,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x01,0xFF, +0xFF,0x80,0x00,0x00,0x00,0x00,0x01,0xFF,0xFF,0xE0, +0x00,0x00,0x00,0x00,0x01,0xFF,0xFF,0xF8,0x00,0x00, +0x00,0x00,0x01,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00, +0x01,0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x00,0x00,0xFF, +0xFF,0xFF,0xF0,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF, +0xFE,0x00,0x00,0x00,0x00,0x03,0xFF,0xFF,0xFF,0x80, +0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xE0,0x00,0x00, +0x00,0x00,0x1F,0xFF,0xFF,0xFC,0x00,0x00,0x00,0x00, +0x07,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0xFF, +0xFF,0xFF,0xC0,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF, +0xF8,0x00,0x00,0x00,0x00,0x07,0xFF,0xFF,0xFE,0x00, +0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0x80,0x00,0x00, +0x00,0x00,0x3F,0xFF,0xFF,0xF0,0x00,0x00,0x00,0x00, +0x07,0xFF,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0xFF, +0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xFF, +0xE0,0x00,0x00,0x00,0x00,0x07,0xFF,0xFF,0xF8,0x00, +0x00,0x00,0x00,0x00,0xFF,0xFF,0xFC,0x00,0x00,0x00, +0x00,0x00,0x3F,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00, +0x07,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x01,0xFF, +0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFC,0x00, +0x00,0x00,0x00,0x00,0x01,0xFF,0xFC,0x00,0x00,0x00, +0x00,0x00,0x07,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00, +0x3F,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF, +0xFC,0x00,0x00,0x00,0x00,0x07,0xFF,0xFF,0xF8,0x00, +0x00,0x00,0x00,0x3F,0xFF,0xFF,0xE0,0x00,0x00,0x00, +0x00,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x07,0xFF, +0xFF,0xFC,0x00,0x00,0x00,0x00,0x3F,0xFF,0xFF,0xF0, +0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0x80,0x00,0x00, +0x00,0x07,0xFF,0xFF,0xFE,0x00,0x00,0x00,0x00,0x1F, +0xFF,0xFF,0xF8,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF, +0xC0,0x00,0x00,0x00,0x07,0xFF,0xFF,0xFF,0x00,0x00, +0x00,0x00,0x1F,0xFF,0xFF,0xFC,0x00,0x00,0x00,0x00, +0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x00,0x03,0xFF,0xFF, +0xFF,0x80,0x00,0x00,0x00,0x1F,0xFF,0xFF,0xFE,0x00, +0x00,0x00,0x00,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x00, +0x01,0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x00,0x01,0xFF, +0xFF,0xFF,0x00,0x00,0x00,0x00,0x01,0xFF,0xFF,0xF8, +0x00,0x00,0x00,0x00,0x01,0xFF,0xFF,0xE0,0x00,0x00, +0x00,0x00,0x01,0xFF,0xFF,0x80,0x00,0x00,0x00,0x00, +0x01,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x01,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xC0,0x00, +0x00,0x00,0x00,0x00,0x01,0xFE,0x00,0x00,0x00,0x00, +0x00,0x00,0x01,0xF8,0x00,0x00,0x00,0x00,0x00,0x00, +0x01,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0xB0,0x18, +0x01,0x28,0x00,0x00,0x00,0xFF,0xF8,0x00,0x00,0x00, +0x00,0x00,0x3F,0xFF,0xFF,0x00,0x00,0x00,0x00,0x03, +0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x00,0x1F,0xFF,0xFF, +0xFF,0xE0,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xF0, +0x00,0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x00, +0x0F,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x7F,0xFF, +0xFF,0xFF,0xFF,0xF8,0x00,0x01,0xFF,0xFF,0xFF,0xFF, +0xFF,0xF8,0x00,0x07,0xFF,0xFF,0xFF,0xFF,0xFF,0xF8, +0x00,0x0F,0xFF,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x3F, +0xFF,0xFE,0x00,0xFF,0xFF,0xF8,0x00,0xFF,0xFF,0xE0, +0x00,0x3F,0xFF,0xF8,0x01,0xFF,0xFF,0x00,0x00,0x1F, +0xFF,0xF0,0x07,0xFF,0xF8,0x00,0x00,0x0F,0xFF,0xF0, +0x1F,0xFF,0xE0,0x00,0x00,0x0F,0xFF,0xE0,0x3F,0xFF, +0x80,0x00,0x00,0x0F,0xFF,0xE0,0x7F,0xFE,0x00,0x00, +0x00,0x0F,0xFF,0xC8,0x3F,0xFF,0x00,0x00,0x00,0x01, +0xFF,0xF8,0x7F,0xFC,0x00,0x00,0x00,0x01,0xFF,0xF4, +0xBF,0xFE,0x00,0x00,0x00,0x00,0x3F,0xFE,0x7F,0xF8, +0x00,0x00,0x00,0x00,0x3F,0xFE,0x3F,0xFE,0x00,0x00, +0x00,0x00,0x0F,0xFF,0x7F,0xF8,0x00,0x00,0x00,0x00, +0x1F,0xFE,0x1F,0xF0,0x00,0x00,0x00,0x00,0x3F,0xFC, +0x00,0xE0,0x00,0x00,0x00,0x00,0x7F,0xF8,0x00,0x00, +0x00,0x00,0x00,0x00,0xFF,0xF0,0x00,0x00,0x00,0x00, +0x00,0x03,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x00, +0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xE0, +0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0x80,0x00,0x00, +0x00,0x00,0x00,0x1F,0xFF,0x00,0x00,0x00,0x00,0x00, +0x00,0x7F,0xFC,0x00,0x00,0x00,0x00,0x00,0x01,0xFF, +0xF8,0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xE0,0x00, +0x00,0x00,0x00,0x00,0x1F,0xFF,0xC0,0x00,0x00,0x00, +0x00,0x00,0x7F,0xFF,0x00,0x00,0x00,0x00,0x00,0x01, +0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0xF0, +0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xC0,0x00,0x00, +0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00, +0x03,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xC0,0x00, +0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00, +0x00,0x03,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x0F, +0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xC0, +0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00, +0x00,0x00,0x03,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00, +0x07,0xFF,0xE0,0x00,0x01,0x00,0x00,0x00,0x03,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0xC0,0x00, +0x00,0x00,0x00,0x00,0x1F,0xFF,0x00,0x00,0x01,0x00, +0x00,0x00,0x0F,0xFF,0x80,0x00,0x00,0x40,0x00,0x00, +0x03,0xFF,0xC0,0x00,0x00,0x10,0x00,0x00,0x01,0xFF, +0xF0,0x00,0x00,0x06,0x80,0x00,0x00,0x7F,0xF8,0x00, +0x00,0x00,0x00,0x00,0x00,0xFF,0xF0,0x00,0x00,0x03, +0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x90,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x34,0x00,0x00,0x03, +0xFF,0xC0,0x00,0x00,0x0B,0x00,0x00,0x00,0xFF,0xF0, +0x00,0x00,0x00,0x1E,0xFE,0x1F,0x92,0x1C,0x00,0x00, +0x00,0x00,0x00,0x00,0x03,0xFF,0xFF,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F, +0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFF,0xFF,0xC0, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F, +0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x07,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xC0,0x00, +0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF8, +0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x00,0x00, +0x00,0x07,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xFF,0xFF, +0xFE,0x00,0x03,0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x00, +0x00,0x00,0x3F,0xFF,0xFF,0xF8,0x00,0x00,0x00,0xFF, +0xFF,0xFF,0xE0,0x00,0x00,0x00,0x00,0x07,0xFF,0xFF, +0xF8,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0x00,0x00, +0x00,0x00,0x00,0xFF,0xFF,0xFC,0x00,0x00,0x00,0x00, +0x01,0xFF,0xFF,0xF8,0x00,0x00,0x00,0x00,0x1F,0xFF, +0xFF,0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xFF,0xC0, +0x00,0x00,0x00,0x03,0xFF,0xFF,0xC0,0x00,0x00,0x00, +0x00,0x00,0x1F,0xFF,0xFE,0x00,0x00,0x00,0x00,0x7F, +0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF, +0xF0,0x00,0x00,0x00,0x0F,0xFF,0xFC,0x00,0x00,0x00, +0x00,0x00,0x00,0x01,0xFF,0xFF,0x00,0x00,0x00,0x01, +0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F, +0xFF,0xF8,0x00,0x00,0x00,0x3F,0xFF,0xE0,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xC0,0x00,0x00, +0x03,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x01,0xFF,0xFE,0x00,0x00,0x00,0x7F,0xFF,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0xE0,0x00, +0x00,0x0F,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x3F,0xFF,0x00,0x00,0x01,0xFF,0xFC,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xF0, +0x00,0x00,0x1F,0xFF,0x80,0x00,0x00,0x07,0xFC,0x00, +0x00,0x00,0x00,0x0F,0xFF,0x80,0x00,0x03,0xFF,0xF0, +0x00,0x00,0x07,0xFF,0xF8,0x00,0x00,0x00,0x00,0xFF, +0xFC,0x00,0x00,0x7F,0xFE,0x00,0x00,0x01,0xFF,0xFF, +0xE0,0x01,0xFF,0xE0,0x07,0xFF,0xC0,0x00,0x07,0xFF, +0xC0,0x00,0x00,0x7F,0xFF,0xFF,0x80,0x1F,0xFE,0x00, +0x3F,0xFE,0x00,0x00,0xFF,0xF8,0x00,0x00,0x1F,0xFF, +0xFF,0xFC,0x03,0xFF,0xC0,0x01,0xFF,0xE0,0x00,0x0F, +0xFF,0x00,0x00,0x03,0xFF,0xFF,0xFF,0xF0,0x3F,0xFC, +0x00,0x1F,0xFE,0x00,0x01,0xFF,0xE0,0x00,0x00,0xFF, +0xFF,0xFF,0xFF,0x83,0xFF,0xC0,0x00,0xFF,0xF0,0x00, +0x1F,0xFE,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xFC,0x3F, +0xFC,0x00,0x07,0xFF,0x00,0x03,0xFF,0xC0,0x00,0x03, +0xFF,0xFF,0xFF,0xFF,0xC3,0xFF,0xC0,0x00,0x7F,0xF8, +0x00,0x3F,0xF8,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFE, +0x7F,0xF8,0x00,0x03,0xFF,0x80,0x07,0xFF,0x80,0x00, +0x0F,0xFF,0xFF,0xFF,0xFF,0xF7,0xFF,0x80,0x00,0x3F, +0xF8,0x00,0x7F,0xF0,0x00,0x01,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xF8,0x00,0x03,0xFF,0x80,0x0F,0xFF,0x00, +0x00,0x3F,0xFF,0xFC,0x03,0xFF,0xFF,0xFF,0x80,0x00, +0x1F,0xFC,0x00,0xFF,0xE0,0x00,0x03,0xFF,0xFE,0x00, +0x07,0xFF,0xFF,0xF0,0x00,0x01,0xFF,0xC0,0x0F,0xFE, +0x00,0x00,0x7F,0xFF,0x80,0x00,0x3F,0xFF,0xFF,0x00, +0x00,0x1F,0xFC,0x01,0xFF,0xC0,0x00,0x0F,0xFF,0xF0, +0x00,0x00,0xFF,0xFF,0xF0,0x00,0x00,0xFF,0xC0,0x1F, +0xFC,0x00,0x00,0xFF,0xFE,0x00,0x00,0x07,0xFF,0xFF, +0x00,0x00,0x0F,0xFC,0x01,0xFF,0x80,0x00,0x1F,0xFF, +0xC0,0x00,0x00,0x3F,0xFF,0xE0,0x00,0x00,0xFF,0xE0, +0x3F,0xF8,0x00,0x03,0xFF,0xF8,0x00,0x00,0x03,0xFF, +0xFE,0x00,0x00,0x0F,0xFE,0x03,0xFF,0x00,0x00,0x3F, +0xFF,0x00,0x00,0x00,0x1F,0xFF,0xE0,0x00,0x00,0x7F, +0xE0,0x3F,0xF0,0x00,0x07,0xFF,0xE0,0x00,0x00,0x01, +0xFF,0xFE,0x00,0x00,0x07,0xFE,0x07,0xFF,0x00,0x00, +0x7F,0xFC,0x00,0x00,0x00,0x0F,0xFF,0xE0,0x00,0x00, +0x7F,0xE0,0x7F,0xE0,0x00,0x0F,0xFF,0xC0,0x00,0x00, +0x00,0xFF,0xFC,0x00,0x00,0x07,0xFE,0x07,0xFE,0x00, +0x00,0xFF,0xF8,0x00,0x00,0x00,0x0F,0xFF,0xC0,0x00, +0x00,0x7F,0xE0,0x7F,0xE0,0x00,0x1F,0xFF,0x80,0x00, +0x00,0x00,0x7F,0xFC,0x00,0x00,0x07,0xFE,0x0F,0xFE, +0x00,0x01,0xFF,0xF0,0x00,0x00,0x00,0x07,0xFF,0xC0, +0x00,0x00,0x7F,0xE0,0xFF,0xC0,0x00,0x1F,0xFF,0x00, +0x00,0x00,0x00,0x7F,0xF8,0x00,0x00,0x07,0xFE,0x21, +0xFF,0x80,0x00,0x7F,0xFC,0x00,0x00,0x00,0x00,0xFF, +0xF0,0x00,0x00,0x0F,0xFC,0x1F,0xF8,0x00,0x07,0xFF, +0x80,0x00,0x00,0x00,0x0F,0xFF,0x00,0x00,0x00,0xFF, +0xC1,0xFF,0x80,0x00,0xFF,0xF8,0x00,0x00,0x00,0x00, +0xFF,0xE0,0x00,0x00,0x0F,0xFC,0x3F,0xF0,0x00,0x0F, +0xFF,0x80,0x00,0x00,0x00,0x0F,0xFE,0x00,0x00,0x01, +0xFF,0x84,0x7F,0xE0,0x00,0x1F,0xFE,0x00,0x00,0x00, +0x00,0x1F,0xFC,0x00,0x00,0x03,0xFF,0x07,0xFE,0x00, +0x03,0xFF,0xE0,0x00,0x00,0x00,0x03,0xFF,0x80,0x00, +0x00,0x3F,0xF0,0x7F,0xE0,0x00,0x3F,0xFE,0x00,0x00, +0x00,0x00,0x3F,0xF8,0x00,0x00,0x07,0xFF,0x08,0xFF, +0xC0,0x00,0x7F,0xF8,0x00,0x00,0x00,0x00,0x7F,0xF0, +0x00,0x00,0x0F,0xFC,0x0F,0xFC,0x00,0x07,0xFF,0x80, +0x00,0x00,0x00,0x0F,0xFF,0x00,0x00,0x01,0xFF,0xC0, +0xFF,0xC0,0x00,0x7F,0xF8,0x00,0x00,0x00,0x00,0xFF, +0xE0,0x00,0x00,0x1F,0xF8,0x0F,0xFC,0x00,0x07,0xFF, +0x80,0x00,0x00,0x00,0x0F,0xFE,0x00,0x00,0x03,0xFF, +0x80,0xFF,0xC0,0x00,0x7F,0xF8,0x00,0x00,0x00,0x01, +0xFF,0xE0,0x00,0x00,0x3F,0xF8,0x0F,0xFC,0x00,0x07, +0xFF,0x80,0x00,0x00,0x00,0x1F,0xFE,0x00,0x00,0x07, +0xFF,0x00,0xFF,0xC0,0x00,0x7F,0xF8,0x00,0x00,0x00, +0x03,0xFF,0xC0,0x00,0x00,0x7F,0xF0,0x0F,0xFC,0x00, +0x07,0xFF,0x80,0x00,0x00,0x00,0x3F,0xFC,0x00,0x00, +0x0F,0xFE,0x00,0xFF,0xC0,0x00,0x7F,0xF8,0x00,0x00, +0x00,0x07,0xFF,0xC0,0x00,0x00,0xFF,0xE0,0x0F,0xFC, +0x00,0x07,0xFF,0xC0,0x00,0x00,0x00,0x7F,0xFC,0x00, +0x00,0x1F,0xFC,0x00,0xFF,0xE0,0x00,0x3F,0xFC,0x00, +0x00,0x00,0x0F,0xFF,0x80,0x00,0x03,0xFF,0xC0,0x07, +0xFE,0x00,0x03,0xFF,0xC0,0x00,0x00,0x01,0xFF,0xF8, +0x00,0x00,0x7F,0xF8,0x00,0x7F,0xE0,0x00,0x3F,0xFC, +0x00,0x00,0x00,0x3F,0xFF,0x80,0x00,0x0F,0xFF,0x80, +0x07,0xFE,0x00,0x03,0xFF,0xE0,0x00,0x00,0x03,0xFF, +0xF8,0x00,0x00,0xFF,0xF0,0x00,0x7F,0xE0,0x00,0x3F, +0xFF,0x00,0x00,0x00,0x7F,0xFF,0x80,0x00,0x3F,0xFE, +0x00,0x07,0xFF,0x00,0x01,0xFF,0xF0,0x00,0x00,0x1F, +0xFF,0xF0,0x00,0x07,0xFF,0xC0,0x00,0x7F,0xF0,0x00, +0x1F,0xFF,0x80,0x00,0x03,0xFF,0xFF,0x00,0x00,0xFF, +0xFC,0x00,0x03,0xFF,0x00,0x00,0xFF,0xFC,0x00,0x00, +0x7F,0xFF,0xF0,0x00,0x1F,0xFF,0x80,0x00,0x3F,0xF0, +0x00,0x0F,0xFF,0xE0,0x00,0x1F,0xFF,0xFF,0x00,0x07, +0xFF,0xF0,0x00,0x03,0xFF,0x80,0x00,0xFF,0xFF,0x80, +0x07,0xFF,0xFF,0xF0,0x00,0xFF,0xFE,0x00,0x00,0x3F, +0xF8,0x00,0x07,0xFF,0xFE,0x03,0xFF,0xFF,0xFF,0x80, +0x3F,0xFF,0xC0,0x00,0x01,0xFF,0xC0,0x00,0x7F,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFC,0x1F,0xFF,0xF8,0x00,0x00, +0x1F,0xFC,0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0x00,0x00,0x01,0xFF,0xC0,0x00,0x1F, +0xFF,0xFF,0xFF,0xFE,0xFF,0xFF,0xFF,0xFF,0xE0,0x00, +0x00,0x0F,0xFE,0x00,0x01,0xFF,0xFF,0xFF,0xFF,0xCF, +0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x00,0xFF,0xE0,0x00, +0x0F,0xFF,0xFF,0xFF,0xF8,0xFF,0xFF,0xFF,0xFF,0x80, +0x00,0x00,0x0F,0xFF,0x00,0x00,0x7F,0xFF,0xFF,0xFF, +0x07,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x00,0x7F,0xF8, +0x00,0x03,0xFF,0xFF,0xFF,0xE0,0x7F,0xFF,0xFF,0xFC, +0x00,0x00,0x00,0x07,0xFF,0x80,0x00,0x1F,0xFF,0xFF, +0xF8,0x03,0xFF,0xFF,0xFF,0x80,0x00,0x00,0x00,0x3F, +0xFC,0x00,0x00,0x7F,0xFF,0xFF,0x00,0x3F,0xFF,0xFF, +0xE0,0x00,0x00,0x00,0x03,0xFF,0xE0,0x00,0x01,0xFF, +0xFF,0xC0,0x01,0xFF,0xFF,0xF8,0x00,0x00,0x00,0x00, +0x3F,0xFF,0x00,0x00,0x07,0xFF,0xF0,0x00,0x07,0xFF, +0xFC,0x00,0x00,0x1F,0xFE,0x01,0xFF,0xF0,0x00,0x00, +0x0F,0xF8,0x00,0x00,0x0F,0xFC,0x00,0x00,0x03,0xFF, +0xC0,0x0F,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x7F,0xFC,0x00,0xFF,0xFC,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F, +0xFF,0x80,0x07,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x01,0xFF,0xF0,0x00,0x3F,0xFF, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x3F,0xFF,0x00,0x03,0xFF,0xFC,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0xE0,0x00,0x1F, +0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x01,0xFF,0xFC,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0x80,0x00, +0x07,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x0F,0xFF,0xF0,0x00,0x00,0x7F,0xFF,0xF0,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xFF,0x00, +0x00,0x03,0xFF,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0xFF,0xFF,0xE0,0x00,0x00,0x1F,0xFF,0xFF, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xFC, +0x00,0x00,0x00,0xFF,0xFF,0xFC,0x00,0x00,0x00,0x00, +0x00,0x00,0x0F,0xFF,0xFF,0x00,0x00,0x00,0x07,0xFF, +0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xFF, +0xE0,0x00,0x00,0x00,0x1F,0xFF,0xFF,0xF8,0x00,0x00, +0x00,0x00,0x03,0xFF,0xFF,0xFC,0x00,0x00,0x00,0x00, +0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x00,0x03,0xFF,0xFF, +0xFF,0x80,0x00,0x00,0x00,0x07,0xFF,0xFF,0xFF,0xFF, +0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x00, +0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x00, +0x00,0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x00, +0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x01, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xC0,0x00, +0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x0F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF8,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xFE,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F, +0xFF,0xFF,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xFF,0xF0,0x00, +0x00,0x00,0x00,0x00,0x00,0x16,0xEF,0xF8,0x01,0x64, +0x00,0x00,0x00,0x00,0x03,0xFF,0xE0,0x00,0x00,0x00, +0x00,0x24,0x00,0x00,0x00,0x00,0x0F,0xFF,0xE0,0x00, +0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x3F,0xFF, +0xE0,0x00,0x00,0x00,0x00,0x90,0x00,0x00,0x00,0x00, +0xFF,0xFF,0xE0,0x00,0x00,0x00,0x01,0x00,0x00,0x00, +0x00,0x03,0xFF,0xFF,0xE0,0x00,0x00,0x00,0x02,0x00, +0x00,0x00,0x00,0x0F,0xFE,0xFF,0xE0,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x01,0xFF,0xEF,0xFE,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xFE,0x7F,0xF0, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xC7, +0xFF,0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x07, +0xFF,0x87,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0xFF,0xF0,0x7F,0xF8,0x00,0x00,0x00,0x08,0x00, +0x00,0x00,0x01,0xFF,0xE0,0x7F,0xF0,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x3F,0xFC,0x07,0xFF,0x80,0x00, +0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xC0,0x3F,0xF8, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFC,0x03, +0xFF,0xC0,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0xFF, +0xF0,0x03,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x00, +0x1F,0xFF,0x00,0x3F,0xFC,0x00,0x00,0x00,0x00,0x00, +0x00,0x01,0xFF,0xE0,0x01,0xFF,0xC0,0x00,0x00,0x02, +0x00,0x00,0x00,0x07,0xFF,0xC0,0x03,0xFF,0xC0,0x00, +0x00,0x00,0x00,0x00,0x00,0x7F,0xF8,0x00,0x1F,0xFC, +0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0x80,0x01, +0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xF0, +0x00,0x0F,0xFE,0x00,0x00,0x00,0x40,0x00,0x00,0x03, +0xFF,0xE0,0x00,0x1F,0xFE,0x00,0x00,0x00,0x00,0x00, +0x00,0x3F,0xFC,0x00,0x00,0xFF,0xE0,0x00,0x00,0x00, +0x00,0x00,0x07,0xFF,0xC0,0x00,0x0F,0xFF,0x00,0x00, +0x00,0x00,0x00,0x00,0x7F,0xF8,0x00,0x00,0xFF,0xF0, +0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0x80,0x00,0x07, +0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0xFF,0xF0,0x00, +0x00,0x7F,0xF8,0x00,0x00,0x08,0x00,0x00,0x03,0xFF, +0xE0,0x00,0x00,0x7F,0xF8,0x00,0x00,0x00,0x00,0x00, +0x3F,0xFC,0x00,0x00,0x07,0xFF,0x80,0x00,0x00,0x00, +0x00,0x07,0xFF,0xC0,0x00,0x00,0x3F,0xFC,0x00,0x00, +0x00,0x00,0x00,0x7F,0xF8,0x00,0x00,0x03,0xFF,0xC0, +0x00,0x00,0x00,0x00,0x0F,0xFF,0x80,0x00,0x00,0x3F, +0xFE,0x00,0x00,0x00,0x00,0x00,0xFF,0xF8,0x00,0x00, +0x01,0xFF,0xE0,0x00,0x00,0x00,0x00,0x0F,0xFF,0x00, +0x00,0x00,0x1F,0xFE,0x00,0x00,0x00,0x00,0x01,0xFF, +0xF0,0x00,0x00,0x00,0xFF,0xF0,0x00,0x00,0x00,0x00, +0x1F,0xFE,0x00,0x00,0x00,0x0F,0xFF,0x00,0x00,0x00, +0x00,0x03,0xFF,0xE0,0x00,0x00,0x00,0xFF,0xF8,0x00, +0x01,0x00,0x00,0x07,0xFF,0x80,0x00,0x00,0x00,0xFF, +0xF0,0x00,0x00,0x00,0x00,0xFF,0xF8,0x00,0x00,0x00, +0x0F,0xFF,0x80,0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xF8,0x00,0x02,0x40,0x00,0x3F,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x04,0x00,0x00, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x08, +0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF8, +0x00,0x12,0x00,0x0F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xF8,0x00,0x20,0x00,0x3F,0xFE,0x00,0x00,0x00, +0x00,0x00,0xFF,0xF8,0x00,0x48,0x00,0xFF,0xF8,0x00, +0x00,0x00,0x00,0x00,0xFF,0xF8,0x00,0x80,0x03,0xFF, +0xE0,0x00,0x00,0x00,0x00,0x00,0xFF,0xF8,0x01,0x20, +0x0F,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0xFF,0xF8, +0x02,0x00,0x3F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00, +0xFF,0xF8,0x00,0x07,0xFF,0xE0,0x00,0x00,0x00,0x00, +0x00,0x0F,0xFF,0xC0,0x40,0x0F,0xFF,0x80,0x00,0x00, +0x00,0x00,0x00,0x0F,0xFF,0x80,0x80,0x3F,0xFE,0x00, +0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0x80,0x07,0xFF, +0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFC,0x00, +0x7F,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xFF, +0xC1,0x01,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x00, +0x0F,0xFF,0xC0,0x1F,0xFF,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x7F,0xFC,0x03,0xFF,0xF0,0x00,0x00,0x00, +0x00,0x00,0x00,0x07,0xFF,0xE0,0x3F,0xFE,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x3F,0xFE,0x20,0xFF,0xFC, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFE,0x0F, +0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xFF, +0xE4,0x3F,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x07,0xFF,0xE7,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x3F,0xFF,0x12,0x2F,0xAC,0x01,0x65,0xFF, +0xFF,0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x00,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x7F,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x3F,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0x80,0x00,0x1F,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xF0,0x00,0x0F,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFC,0x00,0x07,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0x80,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xE0,0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF8, +0x01,0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xC0, +0x0F,0xFF,0x80,0x00,0x00,0x03,0xFF,0xFF,0xF0,0x07, +0xFF,0xC0,0x00,0x00,0x00,0x0F,0xFF,0xFC,0x03,0xFF, +0xE0,0x00,0x00,0x00,0x01,0xFF,0xFE,0x01,0xFF,0xF0, +0x00,0x00,0x00,0x00,0x7F,0xFF,0x80,0xFF,0xF8,0x00, +0x00,0x00,0x00,0x1F,0xFF,0xC0,0x7F,0xFC,0x00,0x00, +0x00,0x00,0x07,0xFF,0xF0,0x47,0xFF,0xC0,0x00,0x00, +0x00,0x00,0x3F,0xFF,0x03,0xFF,0xE0,0x00,0x00,0x00, +0x00,0x0F,0xFF,0x82,0x3F,0xFE,0x00,0x00,0x00,0x00, +0x00,0xFF,0xFC,0x37,0xFF,0xE0,0x00,0x00,0x00,0x00, +0x07,0xFF,0xC1,0xFF,0xF0,0x00,0x00,0x00,0x00,0x03, +0xFF,0xC1,0x1F,0xFF,0x00,0x00,0x00,0x00,0x00,0x7F, +0xFC,0x0F,0xFF,0x80,0x00,0x00,0x00,0x00,0x3F,0xFC, +0x07,0xFF,0xC0,0x00,0x00,0x00,0x00,0x3F,0xFE,0x03, +0xFF,0xE0,0x00,0x00,0x00,0x00,0x3F,0xFE,0x01,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x3F,0xFE,0x00,0xFF,0xF8, +0x00,0x00,0x00,0x00,0x3F,0xFF,0x00,0x7F,0xFC,0x00, +0x00,0x00,0x00,0x3F,0xFF,0x00,0x3F,0xFE,0x00,0x00, +0x00,0x00,0x7F,0xFF,0x00,0x1F,0xFF,0x00,0x00,0x00, +0x07,0xFF,0xFF,0x00,0x0F,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0x00,0x07,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFE,0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE, +0x00,0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFC,0x00, +0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00, +0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xE0,0x00,0x3F, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x1F,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x0F,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xE0,0x07,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xF8,0x03,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFE,0x01,0xFF,0xF0,0x00,0x00,0x00, +0x1F,0xFF,0xFF,0x80,0xFF,0xF8,0x00,0x00,0x00,0x00, +0xFF,0xFF,0xE0,0x7F,0xFC,0x00,0x00,0x00,0x00,0x0F, +0xFF,0xF8,0x3F,0xFE,0x00,0x00,0x00,0x00,0x01,0xFF, +0xFE,0x1F,0xFF,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF, +0x0F,0xFF,0x80,0x00,0x00,0x00,0x00,0x1F,0xFF,0xC8, +0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0xFF,0xFC,0x7F, +0xFC,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0x47,0xFF, +0xC0,0x00,0x00,0x00,0x00,0x01,0xFF,0xF3,0xFF,0xE0, +0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x7F,0xFE,0x00, +0x00,0x00,0x00,0x00,0x07,0xFF,0xE3,0xFF,0xE0,0x00, +0x00,0x00,0x00,0x00,0x7F,0xFD,0xFF,0xF0,0x00,0x00, +0x00,0x00,0x00,0x7F,0xFF,0x1F,0xFF,0x00,0x00,0x00, +0x00,0x00,0x07,0xFF,0xD1,0xFF,0xF0,0x00,0x00,0x00, +0x00,0x00,0xFF,0xFC,0xFF,0xF8,0x00,0x00,0x00,0x00, +0x00,0xFF,0xFC,0x7F,0xFC,0x00,0x00,0x00,0x00,0x00, +0xFF,0xFE,0x3F,0xFE,0x00,0x00,0x00,0x00,0x00,0xFF, +0xFE,0x1F,0xFF,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF, +0x0F,0xFF,0x80,0x00,0x00,0x00,0x01,0xFF,0xFF,0x07, +0xFF,0xC0,0x00,0x00,0x00,0x03,0xFF,0xFF,0x83,0xFF, +0xE0,0x00,0x00,0x00,0x1F,0xFF,0xFF,0x81,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x81,0x1F,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0x0F,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xF0,0x07,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xE0,0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xC0,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0x80,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00, +0x00,0x3F,0xFF,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x00, +0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00, +0x15,0x30,0x9B,0xFD,0x80,0x00,0x00,0x00,0x00,0x07, +0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F, +0xFF,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x03, +0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x00, +0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00, +0x1F,0xFF,0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x00,0x00, +0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x00, +0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00, +0x00,0x07,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE,0x00,0x00, +0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF8,0x00, +0x00,0x00,0x0F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xE0, +0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0x80,0x00,0x00,0x0F,0xFF,0xFF,0xF0,0x00,0xFF,0xFF, +0xFE,0x00,0x00,0x00,0xFF,0xFF,0xF8,0x00,0x00,0x7F, +0xFF,0xF8,0x00,0x00,0x0F,0xFF,0xFE,0x00,0x00,0x00, +0xFF,0xFF,0xE0,0x00,0x00,0xFF,0xFF,0xC0,0x00,0x00, +0x01,0xFF,0xFF,0x80,0x00,0x0F,0xFF,0xF8,0x00,0x00, +0x00,0x07,0xFF,0xFC,0x00,0x00,0xFF,0xFF,0x80,0x00, +0x00,0x00,0x0F,0xFF,0xF0,0x00,0x0F,0xFF,0xF0,0x00, +0x00,0x00,0x00,0x3F,0xFF,0xC0,0x00,0x7F,0xFF,0x00, +0x00,0x00,0x00,0x00,0xFF,0xFE,0x00,0x07,0xFF,0xF0, +0x00,0x00,0x00,0x00,0x07,0xFF,0xF8,0x00,0x3F,0xFF, +0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xC0,0x03,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0x00,0x3F, +0xFF,0x80,0x00,0x00,0x00,0x00,0x01,0xFF,0xF8,0x01, +0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0xE0, +0x0F,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF, +0x00,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x01,0xFF, +0xF8,0x07,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x07, +0xFF,0xE0,0x7F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00, +0x3F,0xFF,0x03,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00, +0x01,0xFF,0x80,0x1F,0xFF,0x00,0x00,0x00,0x00,0x00, +0x00,0x07,0x80,0x01,0xFF,0xF8,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x49,0xFF,0xF0,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0x80,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x02,0x9F,0xFF,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xF8,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1B,0xFF,0xF0, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1B,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x11, +0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x18,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x03,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x00, +0x10,0x00,0x1F,0xFF,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0xF8,0x00,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00, +0x00,0x0F,0xFC,0x07,0xFF,0xC0,0x00,0x00,0x00,0x00, +0x00,0x00,0x7F,0xFE,0x1F,0xFF,0x00,0x00,0x00,0x00, +0x00,0x00,0x03,0xFF,0xF0,0xFF,0xF8,0x00,0x00,0x00, +0x00,0x00,0x00,0x1F,0xFF,0x07,0xFF,0xE0,0x00,0x00, +0x00,0x00,0x00,0x01,0xFF,0xF8,0x1F,0xFF,0x00,0x00, +0x00,0x00,0x00,0x00,0x0F,0xFF,0xC0,0xFF,0xF8,0x00, +0x00,0x00,0x00,0x00,0x00,0xFF,0xFC,0x07,0xFF,0xE0, +0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xE0,0x1F,0xFF, +0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0x00,0xFF, +0xFC,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xF0,0x03, +0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0x80, +0x1F,0xFF,0x80,0x00,0x00,0x00,0x00,0x03,0xFF,0xF8, +0x00,0x7F,0xFE,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF, +0xC0,0x03,0xFF,0xF8,0x00,0x00,0x00,0x00,0x01,0xFF, +0xFC,0x00,0x0F,0xFF,0xE0,0x00,0x00,0x00,0x00,0x1F, +0xFF,0xE0,0x00,0x7F,0xFF,0x80,0x00,0x00,0x00,0x01, +0xFF,0xFE,0x00,0x01,0xFF,0xFF,0x00,0x00,0x00,0x00, +0x1F,0xFF,0xF0,0x00,0x07,0xFF,0xFC,0x00,0x00,0x00, +0x03,0xFF,0xFF,0x00,0x00,0x1F,0xFF,0xF8,0x00,0x00, +0x00,0x3F,0xFF,0xF0,0x00,0x00,0xFF,0xFF,0xF0,0x00, +0x00,0x07,0xFF,0xFF,0x00,0x00,0x03,0xFF,0xFF,0xF0, +0x00,0x01,0xFF,0xFF,0xF0,0x00,0x00,0x0F,0xFF,0xFF, +0xF8,0x00,0xFF,0xFF,0xFF,0x80,0x00,0x00,0x3F,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x00,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x03, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x00, +0x07,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00, +0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x00, +0x00,0x00,0x3F,0xFF,0xFF,0xFF,0xFF,0xFE,0x00,0x00, +0x00,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xC0,0x00, +0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xF8,0x00, +0x00,0x00,0x00,0x00,0x01,0xFF,0xFF,0xFF,0xFF,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xC0, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xC0, +0x00,0x00,0x00,0x00,0x13,0xEF,0xAC,0x01,0x81,0xFF, +0xFF,0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x00,0x01,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x00,0x01,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x01,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFE,0x00,0x00,0x01,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x01,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xE0,0x00,0x01,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x01,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x01,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE,0x00,0x01,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x01,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x01,0xFF, +0xF0,0x00,0x00,0x00,0x3F,0xFF,0xFF,0xC0,0x01,0xFF, +0xF0,0x00,0x00,0x00,0x01,0xFF,0xFF,0xE0,0x01,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x7F,0xFF,0xF0,0x01,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x1F,0xFF,0xF8,0x01,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x07,0xFF,0xFC,0x01,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x03,0xFF,0xFC,0x01,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x01,0xFF,0xFE,0x01,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x00,0xFF,0xFE,0x01,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0x01,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0x82,0x3F, +0xFE,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xF0,0x3F, +0xFE,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xF8,0x3F, +0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xF8,0x3F, +0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFC,0x47, +0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0x87, +0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0xC9, +0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xF8, +0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFD, +0x7F,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF, +0xB7,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0xFF, +0xFE,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x1F, +0xFF,0xAF,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x03, +0xFF,0xF9,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x00, +0xFF,0xFA,0x7F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00, +0x3F,0xFE,0x3F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00, +0x7F,0xFE,0x47,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00, +0x0F,0xFF,0x87,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00, +0x1F,0xFF,0x87,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00, +0x1F,0xFF,0x08,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00, +0x07,0xFF,0xE1,0x1F,0xFF,0x00,0x00,0x00,0x00,0x00, +0x01,0xFF,0xF8,0x1F,0xFF,0x00,0x00,0x00,0x00,0x00, +0x03,0xFF,0xF0,0x1F,0xFF,0x00,0x00,0x00,0x00,0x00, +0x07,0xFF,0xF0,0x1F,0xFF,0x00,0x00,0x00,0x00,0x00, +0x0F,0xFF,0xE0,0x1F,0xFF,0x00,0x00,0x00,0x00,0x00, +0x1F,0xFF,0xE0,0x1F,0xFF,0x00,0x00,0x00,0x00,0x00, +0x3F,0xFF,0xC0,0x1F,0xFF,0x00,0x00,0x00,0x00,0x00, +0x7F,0xFF,0x80,0x1F,0xFF,0x00,0x00,0x00,0x00,0x01, +0xFF,0xFF,0x80,0x1F,0xFF,0x00,0x00,0x00,0x00,0x07, +0xFF,0xFF,0x00,0x1F,0xFF,0x00,0x00,0x00,0x00,0x3F, +0xFF,0xFE,0x00,0x1F,0xFF,0x00,0x00,0x00,0x07,0xFF, +0xFF,0xFC,0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xF8,0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xF0,0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xE0,0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xC0,0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFE,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xF8,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xE0,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0x00,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0, +0x00,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xFC,0x00, +0x00,0x00,0x00,0x00,0x11,0xEF,0xAC,0x01,0x67,0x7F, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE,0x57,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xCD,0xFF,0xF8, +0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xBF,0xFF,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x37,0xFF,0xE0,0x00, +0x00,0x00,0x00,0x00,0x00,0x06,0xFF,0xFC,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x7F,0xFC,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0xDF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xF8,0x15,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0x03,0x7F,0xFE,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x6F,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00, +0x00,0x0D,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x00, +0x01,0xBF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x2F,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x06, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xAF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xE0,0x10, +0x2F,0xAC,0x01,0x47,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xEB,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0x7F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x37, +0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x03,0x7F,0xFE, +0x00,0x00,0x00,0x00,0x00,0x00,0x37,0xFF,0xE0,0x00, +0x00,0x00,0x00,0x00,0x02,0x3F,0xFE,0x00,0x00,0x00, +0x00,0x00,0x00,0x37,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFC,0x02,0xBF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xC0, +0x37,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x03,0x7F, +0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x37,0xFF,0xE0, +0x00,0x00,0x00,0x00,0x00,0x03,0x7F,0xFE,0x00,0x00, +0x00,0x00,0x00,0x00,0x37,0xFF,0xE0,0x00,0x00,0x00, +0x00,0x00,0x03,0x7F,0xFE,0x00,0x00,0x00,0x00,0x00, +0x00,0x1F,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x16,0x70,0x9B,0xFD,0x9C,0x00,0x00,0x00,0x00,0x01, +0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x1F,0xFF,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x3F,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x00,0x00, +0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00, +0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xF8,0x00, +0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0x80,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xF0,0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x00,0x3F,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x00,0x1F, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x00, +0x0F,0xFF,0xFF,0xFC,0x00,0x1F,0xFF,0xFF,0xF0,0x00, +0x00,0x07,0xFF,0xFF,0xE0,0x00,0x00,0x7F,0xFF,0xFE, +0x00,0x00,0x03,0xFF,0xFF,0xC0,0x00,0x00,0x03,0xFF, +0xFF,0xC0,0x00,0x01,0xFF,0xFF,0xC0,0x00,0x00,0x00, +0x3F,0xFF,0xF8,0x00,0x00,0xFF,0xFF,0xC0,0x00,0x00, +0x00,0x03,0xFF,0xFE,0x00,0x00,0x7F,0xFF,0xC0,0x00, +0x00,0x00,0x00,0x3F,0xFF,0xC0,0x00,0x3F,0xFF,0xE0, +0x00,0x00,0x00,0x00,0x07,0xFF,0xF0,0x00,0x0F,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x00,0xFF,0xFE,0x00,0x07, +0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0x80, +0x03,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x03,0xFF, +0xF0,0x00,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x00, +0xFF,0xFC,0x00,0x7F,0xFF,0x00,0x00,0x00,0x00,0x00, +0x00,0x1F,0xFF,0x80,0x1F,0xFF,0x80,0x00,0x00,0x00, +0x00,0x00,0x07,0xFF,0xE0,0x0F,0xFF,0xC0,0x00,0x00, +0x00,0x00,0x00,0x00,0xFF,0xF8,0x03,0xFF,0xF0,0x00, +0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0x20,0x3F,0xFF, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xF8,0x0F, +0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xFE, +0x07,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x07, +0xF8,0x01,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x00, +0x01,0xE0,0x00,0x7F,0xFC,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x3F,0xFF,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x41,0xFF,0xF0,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFC,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xB7,0xFF, +0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06, +0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x37,0xFF,0xE0,0x00,0x00,0x00,0x01,0xFF,0xFF, +0xFF,0xFF,0xFF,0x1F,0xFF,0x00,0x00,0x00,0x00,0x0F, +0xFF,0xFF,0xFF,0xFF,0xF8,0x7F,0xFC,0x00,0x00,0x00, +0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xCB,0xFF,0xE0,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFE,0x4F,0xFF, +0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xE3, +0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF, +0xFC,0x0F,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x00, +0x07,0xFF,0xC3,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00, +0x00,0x01,0xFF,0xF0,0x7F,0xFC,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x7F,0xFC,0x1F,0xFF,0x80,0x00,0x00, +0x00,0x00,0x00,0x00,0x1F,0xFF,0x80,0x7F,0xFE,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xF8,0x0F,0xFF, +0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFE,0x03, +0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF, +0x80,0x7F,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x03, +0xFF,0xE0,0x1F,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00, +0x00,0xFF,0xF8,0x03,0xFF,0xFC,0x00,0x00,0x00,0x00, +0x00,0x00,0x7F,0xFE,0x00,0x7F,0xFF,0x80,0x00,0x00, +0x00,0x00,0x00,0x7F,0xFF,0x80,0x1F,0xFF,0xF0,0x00, +0x00,0x00,0x00,0x00,0x7F,0xFF,0xE0,0x03,0xFF,0xFF, +0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xF8,0x00,0x7F, +0xFF,0xE0,0x00,0x00,0x00,0x00,0x3F,0xFF,0xFE,0x00, +0x0F,0xFF,0xFE,0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF, +0x80,0x01,0xFF,0xFF,0xF0,0x00,0x00,0x00,0x7F,0xFF, +0xFF,0xC0,0x00,0x3F,0xFF,0xFF,0x80,0x00,0x01,0xFF, +0xFF,0xFF,0xC0,0x00,0x07,0xFF,0xFF,0xFF,0x00,0x07, +0xFF,0xFF,0xFF,0xE0,0x00,0x00,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x0F,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x01,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x00, +0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x00, +0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0x00, +0x00,0x00,0x00,0x3F,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0, +0x00,0x00,0x00,0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF,0xFF, +0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF, +0xFF,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x07, +0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x07,0xFF,0xF8,0x00,0x00,0x00,0x00,0x12,0xAF, +0xAC,0x01,0x83,0x7F,0xFE,0x00,0x00,0x00,0x00,0x00, +0x01,0xFF,0xFD,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00, +0x07,0xFF,0xF7,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00, +0x1F,0xFF,0xDF,0xFF,0x80,0x00,0x00,0x00,0x00,0x00, +0x7F,0xFF,0x7F,0xFE,0x00,0x00,0x00,0x00,0x00,0x01, +0xFF,0xFA,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x07, +0xFF,0xF7,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xAF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0x7F,0xFE,0x00,0x00,0x00,0x00,0x00,0x01,0xFF, +0xFD,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x07,0xFF, +0xF7,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF, +0xDF,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF, +0x7F,0xFE,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xFD, +0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xE7, +0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0x03, +0x6F,0xB0,0x00,0x97,0x7F,0xFF,0xBF,0xFF,0xDF,0xFF, +0xEF,0xFF,0xF7,0xFF,0xFB,0xFF,0xFD,0xFF,0xFE,0xFF, +0xFF,0x7F,0xFF,0xBF,0xFF,0xDF,0xFF,0xEF,0xFF,0xF7, +0xFF,0xF5,0xFF,0xF0,0x0D,0x30,0x13,0xFD,0x0F,0x40, +0x00,0x00,0x00,0x00,0x7F,0xFF,0x40,0x00,0x00,0x00, +0x00,0x7F,0xFF,0x40,0x00,0x00,0x00,0x00,0x7F,0xFF, +0x40,0x00,0x00,0x00,0x00,0x7F,0xFF,0x40,0x00,0x00, +0x00,0x00,0x7F,0xFF,0x40,0x00,0x00,0x00,0x00,0x7F, +0xFF,0x40,0x00,0x00,0x00,0x00,0x7F,0xFF,0x40,0x00, +0x00,0x00,0x00,0x7F,0xFF,0x40,0x00,0x00,0x00,0x00, +0x7F,0xFE,0x40,0x00,0x00,0x00,0x00,0x7F,0xFC,0x00, +0xF0,0x00,0x00,0x03,0xFF,0xF7,0xFF,0xF0,0x00,0x00, +0x03,0xFF,0xEF,0xFF,0xC0,0x00,0x00,0x1F,0xFF,0x7F, +0xFE,0x00,0x00,0x00,0xFF,0xF4,0x7F,0xFE,0x00,0x00, +0x01,0xFF,0xF1,0xFF,0xF0,0x00,0x00,0x0F,0xFF,0x8F, +0xFF,0xC0,0x00,0x00,0x7F,0xFC,0x7F,0xFE,0x00,0x00, +0x07,0xFF,0xE3,0xFF,0xF8,0x00,0x00,0x3F,0xFE,0x0F, +0xFF,0xC0,0x00,0x03,0xFF,0xF0,0x7F,0xFF,0x00,0x00, +0x3F,0xFF,0x83,0xFF,0xFC,0x00,0x03,0xFF,0xF8,0x0F, +0xFF,0xF8,0x00,0x7F,0xFF,0xC0,0x7F,0xFF,0xF0,0x0F, +0xFF,0xFC,0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xE0,0x0F, +0xFF,0xFF,0xFF,0xFF,0xFE,0x00,0x3F,0xFF,0xFF,0xFF, +0xFF,0xE0,0x00,0xFF,0xFF,0xFF,0xFF,0xFE,0x00,0x03, +0xFF,0xFF,0xFF,0xFF,0xE0,0x00,0x0F,0xFF,0xFF,0xFF, +0xFE,0x00,0x00,0x3F,0xFF,0xFF,0xFF,0xE0,0x00,0x00, +0x7F,0xFF,0xFF,0xFC,0x00,0x00,0x00,0xFF,0xFF,0xFF, +0x80,0x00,0x00,0x01,0xFF,0xFF,0xF0,0x00,0x00,0x00, +0x00,0xFF,0xF0,0x00,0x00,0x00,0x13,0xEF,0xAC,0x01, +0x65,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF, +0xE1,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF, +0xC1,0xFF,0xF0,0x00,0x00,0x00,0x00,0x01,0xFF,0xFF, +0x81,0xFF,0xF0,0x00,0x00,0x00,0x00,0x03,0xFF,0xFF, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x00,0x07,0xFF,0xFE, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x00,0x0F,0xFF,0xFC, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x00,0x1F,0xFF,0xF8, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x00,0x3F,0xFF,0xF0, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x00,0x7F,0xFF,0xE0, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x00,0xFF,0xFF,0xC0, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x01,0xFF,0xFF,0x80, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x03,0xFF,0xFF,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x07,0xFF,0xFE,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x0F,0xFF,0xFC,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x1F,0xFF,0xF8,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x3F,0xFF,0xF0,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x7F,0xFF,0xE0,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x00,0xFF,0xFF,0xC0,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x01,0xFF,0xFF,0x80,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x03,0xFF,0xFF,0x00,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x07,0xFF,0xFE,0x00,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x0F,0xFF,0xFC,0x00,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x1F,0xFF,0xF8,0x00,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x3F,0xFF,0xF0,0x00,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x7F,0xFF,0xE0,0x00,0x00, +0x01,0xFF,0xF0,0x00,0x00,0xFF,0xFF,0xC0,0x00,0x00, +0x01,0xFF,0xF0,0x00,0x01,0xFF,0xFF,0x80,0x00,0x00, +0x01,0xFF,0xF0,0x00,0x03,0xFF,0xFF,0x00,0x00,0x00, +0x01,0xFF,0xF0,0x00,0x07,0xFF,0xFE,0x00,0x00,0x00, +0x01,0xFF,0xF0,0x00,0x0F,0xFF,0xFC,0x00,0x00,0x00, +0x01,0xFF,0xF0,0x00,0x1F,0xFF,0xF8,0x00,0x00,0x00, +0x01,0xFF,0xF0,0x00,0x3F,0xFF,0xF0,0x00,0x00,0x00, +0x01,0xFF,0xF0,0x00,0x7F,0xFF,0xC0,0x00,0x00,0x00, +0x01,0xFF,0xF0,0x00,0xFF,0xFF,0x80,0x00,0x00,0x00, +0x01,0xFF,0xF0,0x01,0xFF,0xFF,0x00,0x00,0x00,0x00, +0x01,0xFF,0xF0,0x03,0xFF,0xFE,0x00,0x00,0x00,0x00, +0x01,0xFF,0xF0,0x07,0xFF,0xFC,0x00,0x00,0x00,0x00, +0x01,0xFF,0xF0,0x0F,0xFF,0xF8,0x00,0x00,0x00,0x00, +0x01,0xFF,0xF0,0x1F,0xFF,0xF0,0x00,0x00,0x00,0x00, +0x01,0xFF,0xF0,0x3F,0xFF,0xF0,0x00,0x00,0x00,0x00, +0x01,0xFF,0xF0,0x7F,0xFF,0xF0,0x00,0x00,0x00,0x00, +0x01,0xFF,0xF0,0xFF,0xFF,0xF8,0x00,0x00,0x00,0x00, +0x01,0xFF,0xF1,0xFF,0xFF,0xFC,0x00,0x00,0x00,0x00, +0x01,0xFF,0xF3,0xFF,0xFF,0xFE,0x00,0x00,0x00,0x00, +0x01,0xFF,0xF7,0xFF,0xFF,0xFE,0x00,0x00,0x00,0x00, +0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00, +0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x00,0x00, +0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x00, +0x01,0xFF,0xFF,0xFF,0xCF,0xFF,0xC0,0x00,0x00,0x00, +0x01,0xFF,0xFF,0xFF,0x8F,0xFF,0xE0,0x00,0x00,0x00, +0x01,0xFF,0xFF,0xFF,0x07,0xFF,0xF0,0x00,0x00,0x00, +0x01,0xFF,0xFF,0xFE,0x03,0xFF,0xF8,0x00,0x00,0x00, +0x01,0xFF,0xFF,0xFC,0x01,0xFF,0xFC,0x00,0x00,0x00, +0x01,0xFF,0xFF,0xF8,0x01,0xFF,0xFC,0x00,0x00,0x00, +0x01,0xFF,0xFF,0xF0,0x00,0xFF,0xFE,0x00,0x00,0x00, +0x01,0xFF,0xFF,0xE0,0x00,0x7F,0xFF,0x00,0x00,0x00, +0x01,0xFF,0xFF,0xC0,0x00,0x3F,0xFF,0x80,0x00,0x00, +0x01,0xFF,0xFF,0x80,0x00,0x3F,0xFF,0x80,0x00,0x00, +0x01,0xFF,0xFF,0x00,0x00,0x1F,0xFF,0xC0,0x00,0x00, +0x01,0xFF,0xFE,0x00,0x00,0x0F,0xFF,0xE0,0x00,0x00, +0x01,0xFF,0xFC,0x00,0x00,0x0F,0xFF,0xF0,0x00,0x00, +0x01,0xFF,0xF8,0x00,0x00,0x07,0xFF,0xF0,0x00,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x03,0xFF,0xF8,0x00,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x01,0xFF,0xFC,0x00,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x01,0xFF,0xFE,0x00,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x00,0xFF,0xFE,0x00,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x7F,0xFF,0x00,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x3F,0xFF,0x80,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x3F,0xFF,0xC0,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x1F,0xFF,0xE0,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x0F,0xFF,0xE0,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x07,0xFF,0xF0,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x07,0xFF,0xF8,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x03,0xFF,0xFC,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x01,0xFF,0xFC,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x00,0xFF,0xFE,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x00,0x7F,0xFF,0x80, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x00,0x3F,0xFF,0x80, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x00,0x3F,0xFF,0xC0, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x00,0x1F,0xFF,0xE0, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x00,0x0F,0xFF,0xF0, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x00,0x07,0xFF,0xF0, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x00,0x07,0xFF,0xF8, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x00,0x03,0xFF,0xFC, +0x01,0xFF,0xF0,0x00,0x00,0x00,0x00,0x01,0xFF,0xFE, +0x02,0x3F,0xFE,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF, +0xE0,0x3F,0xFE,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF, +0xF0,0x3F,0xFE,0x00,0x00,0x00,0x00,0x00,0x07,0xFF, +0xF8,0x47,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x7F, +0xFF,0x87,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x3F, +0xFF,0xC7,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x1F, +0xFF,0xE7,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x0F, +0xFF,0xF0,0x0E,0xEF,0xAC,0x01,0x2B,0x7F,0xFE,0x00, +0x00,0x00,0x00,0x00,0x06,0xFF,0xFC,0x00,0x00,0x00, +0x00,0x00,0x0D,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00, +0x1B,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x37,0xFF, +0xE0,0x00,0x00,0x00,0x00,0x00,0x6F,0xFF,0xC0,0x00, +0x00,0x00,0x00,0x00,0xDF,0xFF,0x80,0x00,0x00,0x00, +0x00,0x01,0xBF,0xFF,0x00,0x00,0x00,0x00,0x00,0x03, +0x7F,0xFE,0x00,0x00,0x00,0x00,0x00,0x06,0xFF,0xFC, +0x00,0x00,0x00,0x00,0x00,0x0D,0xFF,0xF8,0x00,0x00, +0x00,0x00,0x00,0x1B,0xFF,0xF0,0x00,0x00,0x00,0x00, +0x00,0x37,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xD7, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x16,0xEF,0xA4, +0x01,0xB6,0x3F,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00, +0x00,0x7F,0xFF,0xFC,0xFF,0xFF,0xFC,0x00,0x00,0x00, +0x00,0x00,0x01,0xFF,0xFF,0xF9,0xFF,0xFF,0xFC,0x00, +0x00,0x00,0x00,0x00,0x07,0xFF,0xFF,0xF3,0xFF,0xFF, +0xFC,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF,0xDF, +0xFF,0xFF,0xE0,0x00,0x00,0x00,0x00,0x01,0xFF,0xFF, +0xFE,0x3F,0xFF,0xFF,0xC0,0x00,0x00,0x00,0x00,0x07, +0xFF,0xFF,0xFB,0xFF,0xFF,0xFE,0x00,0x00,0x00,0x00, +0x00,0x7F,0xFF,0xFF,0xBF,0xFF,0xFF,0xE0,0x00,0x00, +0x00,0x00,0x0F,0xFF,0xFF,0xFC,0x7F,0xFD,0xFF,0xC0, +0x00,0x00,0x00,0x00,0x1F,0xFD,0xFF,0xF7,0xFF,0xDF, +0xFE,0x00,0x00,0x00,0x00,0x03,0xFF,0xDF,0xFF,0x8F, +0xFF,0x9F,0xFC,0x00,0x00,0x00,0x00,0x07,0xFF,0x3F, +0xFE,0xFF,0xF9,0xFF,0xE0,0x00,0x00,0x00,0x00,0xFF, +0xF3,0xFF,0xF1,0xFF,0xF1,0xFF,0xC0,0x00,0x00,0x00, +0x01,0xFF,0xC7,0xFF,0xDF,0xFF,0x1F,0xFE,0x00,0x00, +0x00,0x00,0x3F,0xFC,0x7F,0xFE,0x3F,0xFE,0x1F,0xFC, +0x00,0x00,0x00,0x00,0x7F,0xF0,0xFF,0xFB,0xFF,0xE1, +0xFF,0xE0,0x00,0x00,0x00,0x0F,0xFF,0x0F,0xFF,0xC7, +0xFF,0xC1,0xFF,0xC0,0x00,0x00,0x00,0x1F,0xFC,0x1F, +0xFF,0x7F,0xFC,0x1F,0xFE,0x00,0x00,0x00,0x03,0xFF, +0xC1,0xFF,0xF7,0xFF,0xC1,0xFF,0xE0,0x00,0x00,0x00, +0x3F,0xF8,0x1F,0xFF,0x7F,0xFC,0x0F,0xFE,0x00,0x00, +0x00,0x03,0xFF,0x81,0xFF,0xF7,0xFF,0xC0,0xFF,0xF0, +0x00,0x00,0x00,0x3F,0xF8,0x1F,0xFF,0x7F,0xFC,0x0F, +0xFF,0x00,0x00,0x00,0x07,0xFF,0x81,0xFF,0xF8,0xFF, +0xF8,0x0F,0xFE,0x00,0x00,0x00,0x0F,0xFE,0x03,0xFF, +0xEF,0xFF,0x80,0xFF,0xF0,0x00,0x00,0x01,0xFF,0xE0, +0x3F,0xFF,0x1F,0xFF,0x00,0xFF,0xE0,0x00,0x00,0x03, +0xFF,0x80,0x7F,0xFD,0xFF,0xF0,0x0F,0xFF,0x00,0x00, +0x00,0x7F,0xF8,0x07,0xFF,0xE3,0xFF,0xE0,0x0F,0xFE, +0x00,0x00,0x00,0xFF,0xE0,0x0F,0xFF,0xBF,0xFE,0x00, +0xFF,0xF0,0x00,0x00,0x1F,0xFE,0x00,0xFF,0xFC,0x7F, +0xFC,0x00,0xFF,0xE0,0x00,0x00,0x3F,0xF8,0x01,0xFF, +0xF7,0xFF,0xC0,0x0F,0xFF,0x00,0x00,0x07,0xFF,0x80, +0x1F,0xFF,0x8F,0xFF,0x80,0x0F,0xFE,0x00,0x00,0x0F, +0xFE,0x00,0x3F,0xFE,0xFF,0xF8,0x00,0xFF,0xF0,0x00, +0x01,0xFF,0xE0,0x03,0xFF,0xEF,0xFF,0x80,0x0F,0xFF, +0x00,0x00,0x1F,0xFC,0x00,0x3F,0xFE,0xFF,0xF8,0x00, +0x7F,0xF0,0x00,0x01,0xFF,0xC0,0x03,0xFF,0xEF,0xFF, +0x80,0x07,0xFF,0x80,0x00,0x1F,0xFC,0x00,0x3F,0xFE, +0xFF,0xF8,0x00,0x7F,0xF8,0x00,0x03,0xFF,0xC0,0x03, +0xFF,0xF1,0xFF,0xF0,0x00,0x7F,0xF0,0x00,0x07,0xFF, +0x00,0x07,0xFF,0xDF,0xFF,0x00,0x07,0xFF,0x80,0x00, +0xFF,0xF0,0x00,0x7F,0xFE,0x3F,0xFE,0x00,0x07,0xFF, +0x00,0x01,0xFF,0xC0,0x00,0xFF,0xFB,0xFF,0xE0,0x00, +0x7F,0xF8,0x00,0x3F,0xFC,0x00,0x0F,0xFF,0xC7,0xFF, +0xC0,0x00,0x7F,0xF0,0x00,0x7F,0xF0,0x00,0x1F,0xFF, +0x7F,0xFC,0x00,0x07,0xFF,0x80,0x0F,0xFF,0x00,0x01, +0xFF,0xF8,0xFF,0xF8,0x00,0x07,0xFF,0x00,0x1F,0xFC, +0x00,0x03,0xFF,0xEF,0xFF,0x80,0x00,0x7F,0xF8,0x03, +0xFF,0xC0,0x00,0x3F,0xFE,0xFF,0xF8,0x00,0x07,0xFF, +0x80,0x3F,0xF8,0x00,0x03,0xFF,0xEF,0xFF,0x80,0x00, +0x3F,0xF8,0x03,0xFF,0x80,0x00,0x3F,0xFE,0xFF,0xF8, +0x00,0x03,0xFF,0xC0,0x7F,0xF8,0x00,0x03,0xFF,0xEF, +0xFF,0x80,0x00,0x3F,0xFC,0x07,0xFF,0x00,0x00,0x3F, +0xFE,0xFF,0xF8,0x00,0x01,0xFF,0xC0,0x7F,0xF0,0x00, +0x03,0xFF,0xEF,0xFF,0x80,0x00,0x1F,0xFC,0x0F,0xFF, +0x00,0x00,0x3F,0xFE,0xFF,0xF8,0x00,0x01,0xFF,0xE0, +0xFF,0xF0,0x00,0x03,0xFF,0xF1,0xFF,0xF0,0x00,0x01, +0xFF,0xC1,0xFF,0xC0,0x00,0x07,0xFF,0xDF,0xFF,0x00, +0x00,0x1F,0xFE,0x3F,0xFC,0x00,0x00,0x7F,0xFE,0x3F, +0xFE,0x00,0x00,0x1F,0xFC,0x7F,0xF0,0x00,0x00,0xFF, +0xFB,0xFF,0xE0,0x00,0x01,0xFF,0xEF,0xFF,0x00,0x00, +0x0F,0xFF,0xC7,0xFF,0xC0,0x00,0x01,0xFF,0xDF,0xFC, +0x00,0x00,0x1F,0xFF,0x7F,0xFC,0x00,0x00,0x1F,0xFF, +0xFF,0xC0,0x00,0x01,0xFF,0xF9,0xFF,0xF8,0x00,0x00, +0x1F,0xFF,0xFF,0x00,0x00,0x03,0xFF,0xEF,0xFF,0x80, +0x00,0x01,0xFF,0xFF,0xE0,0x00,0x00,0x3F,0xFF,0x1F, +0xFF,0x00,0x00,0x01,0xFF,0xFF,0xC0,0x00,0x00,0x7F, +0xFD,0xFF,0xF0,0x00,0x00,0x1F,0xFF,0xF8,0x00,0x00, +0x07,0xFF,0xE7,0xFF,0xE0,0x00,0x00,0x1F,0xFF,0xF0, +0x00,0x00,0x0F,0xFF,0xCF,0xFF,0xC0,0x00,0x00,0x1F, +0xFF,0xC0,0x00,0x00,0x1F,0xFF,0x12,0xAF,0xAC,0x01, +0x81,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF, +0xC7,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x3F,0xFE, +0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xE3, +0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0x7F, +0xFF,0xE0,0x00,0x00,0x00,0x00,0x03,0xFF,0xF1,0xFF, +0xFF,0xC0,0x00,0x00,0x00,0x00,0x0F,0xFF,0xBF,0xFF, +0xFC,0x00,0x00,0x00,0x00,0x01,0xFF,0xF8,0xFF,0xFF, +0xF8,0x00,0x00,0x00,0x00,0x07,0xFF,0xDF,0xFF,0xFF, +0x80,0x00,0x00,0x00,0x00,0xFF,0xFC,0x7F,0xFF,0xFF, +0x00,0x00,0x00,0x00,0x03,0xFF,0xEF,0xFF,0xFF,0xF0, +0x00,0x00,0x00,0x00,0x7F,0xFE,0x3F,0xFF,0xFF,0xE0, +0x00,0x00,0x00,0x01,0xFF,0xF7,0xFF,0xFF,0xFE,0x00, +0x00,0x00,0x00,0x3F,0xFF,0x1F,0xFF,0xFF,0xFC,0x00, +0x00,0x00,0x00,0xFF,0xFB,0xFF,0xFF,0xFF,0xC0,0x00, +0x00,0x00,0x1F,0xFF,0x8F,0xFF,0xFF,0xFF,0x80,0x00, +0x00,0x00,0x7F,0xFD,0xFF,0xF7,0xFF,0xF8,0x00,0x00, +0x00,0x0F,0xFF,0xBF,0xFE,0x7F,0xFF,0x00,0x00,0x00, +0x01,0xFF,0xF7,0xFF,0xCF,0xFF,0xF0,0x00,0x00,0x00, +0x3F,0xFE,0xFF,0xF8,0xFF,0xFF,0x00,0x00,0x00,0x07, +0xFF,0xDF,0xFF,0x0F,0xFF,0xE0,0x00,0x00,0x00,0xFF, +0xFB,0xFF,0xE1,0xFF,0xFE,0x00,0x00,0x00,0x1F,0xFF, +0x7F,0xFC,0x1F,0xFF,0xE0,0x00,0x00,0x03,0xFF,0xEF, +0xFF,0x81,0xFF,0xFC,0x00,0x00,0x00,0x7F,0xFD,0xFF, +0xF0,0x3F,0xFF,0xC0,0x00,0x00,0x0F,0xFF,0xBF,0xFE, +0x03,0xFF,0xFC,0x00,0x00,0x01,0xFF,0xF7,0xFF,0xC0, +0x3F,0xFF,0x80,0x00,0x00,0x3F,0xFE,0xFF,0xF8,0x07, +0xFF,0xF8,0x00,0x00,0x07,0xFF,0xDF,0xFF,0x00,0x7F, +0xFF,0x80,0x00,0x00,0xFF,0xFB,0xFF,0xE0,0x07,0xFF, +0xF0,0x00,0x00,0x1F,0xFF,0x7F,0xFC,0x00,0xFF,0xFF, +0x00,0x00,0x03,0xFF,0xEF,0xFF,0x80,0x0F,0xFF,0xF0, +0x00,0x00,0x7F,0xFD,0xFF,0xF0,0x00,0xFF,0xFE,0x00, +0x00,0x0F,0xFF,0xBF,0xFE,0x00,0x1F,0xFF,0xE0,0x00, +0x01,0xFF,0xF7,0xFF,0xC0,0x01,0xFF,0xFE,0x00,0x00, +0x3F,0xFE,0xFF,0xF8,0x00,0x1F,0xFF,0xC0,0x00,0x07, +0xFF,0xDF,0xFF,0x00,0x03,0xFF,0xFC,0x00,0x00,0xFF, +0xFB,0xFF,0xE0,0x00,0x3F,0xFF,0xC0,0x00,0x1F,0xFF, +0x7F,0xFC,0x00,0x03,0xFF,0xF8,0x00,0x03,0xFF,0xEF, +0xFF,0x80,0x00,0x7F,0xFF,0x80,0x00,0x7F,0xFD,0xFF, +0xF0,0x00,0x07,0xFF,0xF0,0x00,0x0F,0xFF,0xBF,0xFE, +0x00,0x00,0xFF,0xFF,0x00,0x01,0xFF,0xF7,0xFF,0xC0, +0x00,0x0F,0xFF,0xF0,0x00,0x3F,0xFE,0xFF,0xF8,0x00, +0x00,0xFF,0xFE,0x00,0x07,0xFF,0xDF,0xFF,0x00,0x00, +0x1F,0xFF,0xE0,0x00,0xFF,0xFB,0xFF,0xE0,0x00,0x01, +0xFF,0xFE,0x00,0x1F,0xFF,0x7F,0xFC,0x00,0x00,0x1F, +0xFF,0xC0,0x03,0xFF,0xEF,0xFF,0x80,0x00,0x03,0xFF, +0xFC,0x00,0x7F,0xFD,0xFF,0xF0,0x00,0x00,0x3F,0xFF, +0xC0,0x0F,0xFF,0xBF,0xFE,0x00,0x00,0x03,0xFF,0xF8, +0x01,0xFF,0xF7,0xFF,0xC0,0x00,0x00,0x7F,0xFF,0x80, +0x3F,0xFE,0xFF,0xF8,0x00,0x00,0x07,0xFF,0xF8,0x07, +0xFF,0xDF,0xFF,0x00,0x00,0x00,0x7F,0xFF,0x00,0xFF, +0xFB,0xFF,0xE0,0x00,0x00,0x0F,0xFF,0xF0,0x1F,0xFF, +0x7F,0xFC,0x00,0x00,0x00,0xFF,0xFF,0x03,0xFF,0xEF, +0xFF,0x80,0x00,0x00,0x0F,0xFF,0xE0,0x7F,0xFD,0xFF, +0xF0,0x00,0x00,0x01,0xFF,0xFE,0x0F,0xFF,0xBF,0xFE, +0x00,0x00,0x00,0x1F,0xFF,0xE1,0xFF,0xF7,0xFF,0xC0, +0x00,0x00,0x01,0xFF,0xFC,0x3F,0xFE,0xFF,0xF8,0x00, +0x00,0x00,0x3F,0xFF,0xC7,0xFF,0xDF,0xFF,0x00,0x00, +0x00,0x03,0xFF,0xFC,0xFF,0xFB,0xFF,0xE0,0x00,0x00, +0x00,0x3F,0xFF,0x9F,0xFF,0x7F,0xFC,0x00,0x00,0x00, +0x07,0xFF,0xFB,0xFF,0xF1,0xFF,0xF0,0x00,0x00,0x00, +0x0F,0xFF,0xFF,0xFF,0xBF,0xFE,0x00,0x00,0x00,0x00, +0xFF,0xFF,0xFF,0xF8,0xFF,0xF8,0x00,0x00,0x00,0x01, +0xFF,0xFF,0xFF,0xDF,0xFF,0x00,0x00,0x00,0x00,0x1F, +0xFF,0xFF,0xFC,0x7F,0xFC,0x00,0x00,0x00,0x00,0x3F, +0xFF,0xFF,0xEF,0xFF,0x80,0x00,0x00,0x00,0x03,0xFF, +0xFF,0xFE,0x3F,0xFE,0x00,0x00,0x00,0x00,0x07,0xFF, +0xFF,0xF7,0xFF,0xC0,0x00,0x00,0x00,0x00,0x7F,0xFF, +0xFF,0x1F,0xFF,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF, +0xFB,0xFF,0xE0,0x00,0x00,0x00,0x00,0x0F,0xFF,0xFF, +0x8F,0xFF,0x80,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFD, +0xFF,0xF0,0x00,0x00,0x00,0x00,0x01,0xFF,0xFF,0xC7, +0xFF,0xC0,0x00,0x00,0x00,0x00,0x03,0xFF,0xFE,0xFF, +0xF8,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xE3,0xFF, +0xE0,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0x7F,0xFC, +0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xE0,0x16,0xF0, +0x9B,0xFD,0x9C,0x00,0x00,0x00,0x00,0x07,0xFF,0xF0, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF, +0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F, +0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x00, +0x03,0xFF,0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x00,0x00, +0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x00, +0x00,0x00,0x00,0x3F,0xFF,0xFF,0xFF,0xFF,0xFE,0x00, +0x00,0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFF,0xFF,0xFF, +0xF8,0x00,0x00,0x00,0x00,0x03,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xC0,0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x0F,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x00,0x01, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xC0,0x00,0x00, +0x00,0x7F,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xFE,0x00, +0x00,0x00,0x0F,0xFF,0xFF,0xC0,0x00,0x01,0xFF,0xFF, +0xF0,0x00,0x00,0x01,0xFF,0xFF,0xF0,0x00,0x00,0x07, +0xFF,0xFF,0x80,0x00,0x00,0x1F,0xFF,0xF8,0x00,0x00, +0x00,0x1F,0xFF,0xFC,0x00,0x00,0x03,0xFF,0xFF,0x00, +0x00,0x00,0x00,0x7F,0xFF,0xE0,0x00,0x00,0x7F,0xFF, +0xC0,0x00,0x00,0x00,0x01,0xFF,0xFF,0x00,0x00,0x0F, +0xFF,0xF8,0x00,0x00,0x00,0x00,0x0F,0xFF,0xF8,0x00, +0x01,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF, +0x80,0x00,0x1F,0xFF,0xC0,0x00,0x00,0x00,0x00,0x01, +0xFF,0xFC,0x00,0x03,0xFF,0xF8,0x00,0x00,0x00,0x00, +0x00,0x0F,0xFF,0xE0,0x00,0x3F,0xFF,0x00,0x00,0x00, +0x00,0x00,0x00,0xFF,0xFE,0x00,0x07,0xFF,0xE0,0x00, +0x00,0x00,0x00,0x00,0x07,0xFF,0xF0,0x00,0xFF,0xFE, +0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0x00,0x0F, +0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xF8, +0x00,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x1F, +0xFF,0x80,0x1F,0xFF,0x80,0x00,0x00,0x00,0x00,0x00, +0x00,0xFF,0xFC,0x01,0xFF,0xF0,0x00,0x00,0x00,0x00, +0x00,0x00,0x0F,0xFF,0xC0,0x3F,0xFF,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x7F,0xFE,0x03,0xFF,0xE0,0x00, +0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xE0,0x3F,0xFE, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFE,0x07, +0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xFF, +0xF2,0x4F,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x00, +0x03,0xFF,0xE1,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x3F,0xFF,0x5B,0xFF,0xE0,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x3F,0xFE,0xDF,0xFF,0x80,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xBF,0xFF, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFD, +0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07, +0xFF,0xDF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0xFF,0xFE,0xDF,0xFF,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x01,0xFF,0xF4,0x9F,0xFF,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x07,0xFF,0xC1,0xFF,0xF0,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFC,0x81,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xF0, +0x1F,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x3F, +0xFF,0x00,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x00, +0x03,0xFF,0xE0,0x0F,0xFF,0xC0,0x00,0x00,0x00,0x00, +0x00,0x00,0x7F,0xFE,0x00,0x7F,0xFC,0x00,0x00,0x00, +0x00,0x00,0x00,0x0F,0xFF,0xC0,0x07,0xFF,0xE0,0x00, +0x00,0x00,0x00,0x00,0x00,0xFF,0xFC,0x00,0x3F,0xFF, +0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xC0,0x03, +0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xF8, +0x00,0x1F,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x7F, +0xFF,0x00,0x01,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00, +0x07,0xFF,0xF0,0x00,0x0F,0xFF,0xE0,0x00,0x00,0x00, +0x00,0x00,0xFF,0xFE,0x00,0x00,0x7F,0xFF,0x00,0x00, +0x00,0x00,0x00,0x3F,0xFF,0xE0,0x00,0x07,0xFF,0xFC, +0x00,0x00,0x00,0x00,0x07,0xFF,0xFC,0x00,0x00,0x3F, +0xFF,0xE0,0x00,0x00,0x00,0x00,0xFF,0xFF,0x80,0x00, +0x01,0xFF,0xFF,0x80,0x00,0x00,0x00,0x3F,0xFF,0xF0, +0x00,0x00,0x0F,0xFF,0xFC,0x00,0x00,0x00,0x07,0xFF, +0xFF,0x00,0x00,0x00,0x7F,0xFF,0xF0,0x00,0x00,0x01, +0xFF,0xFF,0xE0,0x00,0x00,0x03,0xFF,0xFF,0xE0,0x00, +0x00,0xFF,0xFF,0xFC,0x00,0x00,0x00,0x1F,0xFF,0xFF, +0xE0,0x01,0xFF,0xFF,0xFF,0x80,0x00,0x00,0x00,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x00, +0x07,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x00, +0x00,0x00,0x3F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x80, +0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x07,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF, +0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x7F, +0xFF,0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00, +0x01,0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x00,0x00, +0x00,0x00,0x03,0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x07,0xFF,0xFF,0xFC,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xF8,0x00, +0x00,0x00,0x00,0x00,0x12,0x2F,0xAC,0x01,0x65,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x00,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x7F,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x3F,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xF0,0x00,0x1F,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFE,0x00,0x0F,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xC0,0x07,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xF0,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFC,0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xC0, +0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0x3F, +0xFE,0x00,0x00,0x00,0x00,0xFF,0xFF,0xF8,0x1F,0xFF, +0x00,0x00,0x00,0x00,0x07,0xFF,0xFE,0x0F,0xFF,0x80, +0x00,0x00,0x00,0x00,0xFF,0xFF,0x87,0xFF,0xC0,0x00, +0x00,0x00,0x00,0x3F,0xFF,0xC3,0xFF,0xE0,0x00,0x00, +0x00,0x00,0x0F,0xFF,0xF1,0xFF,0xF0,0x00,0x00,0x00, +0x00,0x03,0xFF,0xF8,0xFF,0xF8,0x00,0x00,0x00,0x00, +0x00,0xFF,0xFC,0x8F,0xFF,0x80,0x00,0x00,0x00,0x00, +0x07,0xFF,0xE8,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00, +0x3F,0xFE,0x7F,0xFC,0x00,0x00,0x00,0x00,0x00,0x1F, +0xFF,0xEF,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0xFF, +0xFC,0x7F,0xFC,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF, +0xBF,0xFE,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0xE7, +0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0xFF,0xF9,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x00,0xFF,0xFD,0x1F,0xFF, +0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0x8F,0xFF,0x80, +0x00,0x00,0x00,0x00,0x1F,0xFF,0xC7,0xFF,0xC0,0x00, +0x00,0x00,0x00,0x1F,0xFF,0xC3,0xFF,0xE0,0x00,0x00, +0x00,0x00,0x1F,0xFF,0xE1,0xFF,0xF0,0x00,0x00,0x00, +0x00,0x3F,0xFF,0xE0,0xFF,0xF8,0x00,0x00,0x00,0x00, +0xFF,0xFF,0xF0,0x7F,0xFC,0x00,0x00,0x00,0x07,0xFF, +0xFF,0xF0,0x3F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xF0,0x23,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE, +0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE,0x00, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x7F, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x3F,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x1F,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x0F,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xE0,0x00,0x07,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0x80,0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xFF, +0xF0,0x00,0x00,0x03,0x7F,0xFE,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x37,0xFF,0xE0,0x00,0x00,0x00,0x00, +0x00,0x00,0x03,0x7F,0xFE,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x37,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00, +0x00,0x03,0x7F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x2B,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x16,0xF3,0x9B,0xE5,0x9C,0x00,0x00,0x00,0x00, +0x0F,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x1F,0xFF,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x0F,0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x00, +0x00,0x00,0x00,0x07,0xFF,0xFF,0xFF,0xFF,0xC0,0x00, +0x00,0x00,0x00,0x00,0x01,0xFF,0xFF,0xFF,0xFF,0xFF, +0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF,0xFF, +0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0xFF, +0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x00,0x00,0x03,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x00,0x00,0x00, +0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x00, +0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0x00, +0x00,0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0x80,0x00,0x00,0x00,0x7F,0xFF,0xFF,0xC0,0x07,0xFF, +0xFF,0xFC,0x00,0x00,0x00,0x0F,0xFF,0xFF,0xC0,0x00, +0x07,0xFF,0xFF,0xE0,0x00,0x00,0x01,0xFF,0xFF,0xE0, +0x00,0x00,0x0F,0xFF,0xFF,0x00,0x00,0x00,0x3F,0xFF, +0xF8,0x00,0x00,0x00,0x3F,0xFF,0xF8,0x00,0x00,0x07, +0xFF,0xFE,0x00,0x00,0x00,0x00,0xFF,0xFF,0xC0,0x00, +0x00,0x7F,0xFF,0xC0,0x00,0x00,0x00,0x07,0xFF,0xFC, +0x00,0x00,0x0F,0xFF,0xF0,0x00,0x00,0x00,0x00,0x1F, +0xFF,0xE0,0x00,0x01,0xFF,0xFE,0x00,0x00,0x00,0x00, +0x00,0xFF,0xFF,0x00,0x00,0x1F,0xFF,0xC0,0x00,0x00, +0x00,0x00,0x07,0xFF,0xF0,0x00,0x03,0xFF,0xF8,0x00, +0x00,0x00,0x00,0x00,0x3F,0xFF,0x80,0x00,0x7F,0xFF, +0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xFC,0x00,0x07, +0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xC0, +0x00,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0xFF, +0xFE,0x00,0x0F,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00, +0x07,0xFF,0xE0,0x00,0xFF,0xF8,0x00,0x00,0x00,0x00, +0x00,0x00,0x7F,0xFF,0x00,0x1F,0xFF,0x80,0x00,0x00, +0x00,0x00,0x00,0x03,0xFF,0xF0,0x01,0xFF,0xF0,0x00, +0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0x00,0x3F,0xFF, +0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xF8,0x03, +0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF, +0x80,0x3F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0xFF,0xF8,0x07,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00, +0x00,0x0F,0xFF,0xC2,0x4F,0xFF,0x80,0x00,0x00,0x00, +0x00,0x00,0x00,0x0F,0xFF,0x85,0xBF,0xFE,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0x87,0xFF,0xC0, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFC,0xDF, +0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF, +0xF9,0xBF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x01,0xFF,0xF1,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x1F,0xFF,0x1F,0xFF,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x03,0xFF,0xF2,0xDF,0xFF,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xC4,0x9F,0xFF, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0x01, +0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xFF, +0xF0,0x81,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x00, +0x07,0xFF,0xC0,0x1F,0xFF,0x80,0x00,0x00,0x00,0x00, +0x00,0x00,0xFF,0xFC,0x00,0xFF,0xF8,0x00,0x00,0x00, +0x08,0x00,0x00,0x0F,0xFF,0x80,0x0F,0xFF,0xC0,0x00, +0x00,0x01,0xF0,0x00,0x01,0xFF,0xF8,0x00,0x7F,0xFC, +0x00,0x00,0x00,0x1F,0xE0,0x00,0x1F,0xFF,0x00,0x07, +0xFF,0xE0,0x00,0x00,0x01,0xFF,0x80,0x03,0xFF,0xF0, +0x00,0x7F,0xFF,0x00,0x00,0x00,0x3F,0xFE,0x00,0x7F, +0xFE,0x00,0x03,0xFF,0xF0,0x00,0x00,0x03,0xFF,0xF0, +0x07,0xFF,0xE0,0x00,0x1F,0xFF,0x80,0x00,0x00,0x3F, +0xFF,0xC0,0xFF,0xFC,0x00,0x01,0xFF,0xFC,0x00,0x00, +0x07,0xFF,0xFE,0x1F,0xFF,0xC0,0x00,0x0F,0xFF,0xE0, +0x00,0x00,0x7F,0xFF,0xF3,0xFF,0xF8,0x00,0x00,0xFF, +0xFF,0x00,0x00,0x03,0xFF,0xFF,0xFF,0xFF,0x00,0x00, +0x07,0xFF,0xF8,0x00,0x00,0x07,0xFF,0xFF,0xFF,0xF0, +0x00,0x00,0x3F,0xFF,0xE0,0x00,0x00,0x1F,0xFF,0xFF, +0xFE,0x00,0x00,0x01,0xFF,0xFF,0x00,0x00,0x00,0x7F, +0xFF,0xFF,0xC0,0x00,0x00,0x1F,0xFF,0xFC,0x00,0x00, +0x01,0xFF,0xFF,0xF8,0x00,0x00,0x00,0xFF,0xFF,0xF0, +0x00,0x00,0x07,0xFF,0xFF,0x00,0x00,0x00,0x07,0xFF, +0xFF,0xC0,0x00,0x03,0xFF,0xFF,0xE0,0x00,0x00,0x00, +0x3F,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xFE,0x00,0x00, +0x00,0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF8, +0x00,0x00,0x00,0x07,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xC0,0x00,0x00,0x00,0x3F,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0x00,0x00,0x00,0x01,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x00,0x07,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x00, +0x3F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x00, +0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xDF,0xFF,0xFE, +0x00,0x00,0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xF0,0x7F, +0xFF,0xFC,0x00,0x00,0x00,0x07,0xFF,0xFF,0xFF,0xF8, +0x03,0xFF,0xFF,0xE0,0x00,0x00,0x00,0x0F,0xFF,0xFF, +0xFC,0x00,0x0F,0xFF,0xFC,0x00,0x00,0x00,0x00,0x07, +0xFF,0xF0,0x00,0x00,0x7F,0xFF,0xC0,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xF8,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0x80, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F, +0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x7F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0xF0,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x02,0x00,0x14,0x6F,0xAC,0x01, +0x81,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xC0,0x00,0x00, +0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xC0,0x00, +0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE,0x00, +0x00,0x07,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xE0, +0x00,0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE, +0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xC0,0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xF8,0x00,0x07,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0x00,0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xE0,0x00,0x8F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0x80,0x03,0xFF,0xE0,0x00,0x00,0x00,0x03, +0xFF,0xFF,0xF0,0x00,0xFF,0xF8,0x00,0x00,0x00,0x00, +0x0F,0xFF,0xFE,0x00,0x3F,0xFE,0x00,0x00,0x00,0x00, +0x00,0xFF,0xFF,0x80,0x0F,0xFF,0x80,0x00,0x00,0x00, +0x00,0x1F,0xFF,0xF0,0x03,0xFF,0xE0,0x00,0x00,0x00, +0x00,0x01,0xFF,0xFC,0x00,0xFF,0xF8,0x00,0x00,0x00, +0x00,0x00,0x3F,0xFF,0x00,0x3F,0xFE,0x00,0x00,0x00, +0x00,0x00,0x0F,0xFF,0xE0,0x0F,0xFF,0x80,0x00,0x00, +0x00,0x00,0x01,0xFF,0xF8,0x04,0x7F,0xFC,0x00,0x00, +0x00,0x00,0x00,0x07,0xFF,0xC0,0x1F,0xFF,0x00,0x00, +0x00,0x00,0x00,0x01,0xFF,0xF8,0x0D,0xFF,0xF8,0x00, +0x00,0x00,0x00,0x00,0x07,0xFF,0xC0,0x3F,0xFE,0x00, +0x00,0x00,0x00,0x00,0x01,0xFF,0xF0,0x0F,0xFF,0x80, +0x00,0x00,0x00,0x00,0x00,0xFF,0xFC,0x04,0x7F,0xFC, +0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xC0,0x23,0xFF, +0xE0,0x00,0x00,0x00,0x00,0x00,0x7F,0xFE,0x00,0xFF, +0xF8,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0x00,0x3F, +0xFE,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xC0,0x0F, +0xFF,0x80,0x00,0x00,0x00,0x00,0x0F,0xFF,0xF0,0x03, +0xFF,0xE0,0x00,0x00,0x00,0x00,0x07,0xFF,0xF8,0x00, +0xFF,0xF8,0x00,0x00,0x00,0x00,0x07,0xFF,0xFC,0x00, +0x3F,0xFE,0x00,0x00,0x00,0x00,0x07,0xFF,0xFF,0x00, +0x0F,0xFF,0x80,0x00,0x00,0x00,0x1F,0xFF,0xFF,0x80, +0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xC0, +0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xE0, +0x00,0x3F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0, +0x00,0x0F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF8, +0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFC, +0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFC, +0x00,0x00,0x3F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFC, +0x00,0x00,0x0F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFC, +0x00,0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF8, +0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xE0, +0x00,0x00,0x00,0x3F,0xFF,0xFF,0xFF,0xFF,0xFF,0xE0, +0x00,0x00,0x00,0x0F,0xFF,0x80,0x00,0x03,0xFF,0xFE, +0x00,0x00,0x00,0x03,0xFF,0xE0,0x00,0x00,0x1F,0xFF, +0xE0,0x00,0x00,0x00,0xFF,0xF8,0x00,0x00,0x03,0xFF, +0xFC,0x00,0x00,0x00,0x3F,0xFE,0x00,0x00,0x00,0x3F, +0xFF,0x80,0x00,0x00,0x0F,0xFF,0x80,0x00,0x00,0x07, +0xFF,0xF0,0x00,0x00,0x03,0xFF,0xE0,0x00,0x00,0x00, +0xFF,0xFE,0x00,0x00,0x00,0xFF,0xF8,0x00,0x00,0x00, +0x1F,0xFF,0xC0,0x00,0x00,0x3F,0xFE,0x00,0x00,0x00, +0x03,0xFF,0xF8,0x00,0x00,0x0F,0xFF,0x80,0x00,0x00, +0x00,0x7F,0xFF,0x00,0x00,0x03,0xFF,0xE0,0x00,0x00, +0x00,0x0F,0xFF,0xE0,0x00,0x00,0xFF,0xF8,0x00,0x00, +0x00,0x03,0xFF,0xFC,0x00,0x00,0x3F,0xFE,0x00,0x00, +0x00,0x00,0x7F,0xFF,0x00,0x00,0x0F,0xFF,0x80,0x00, +0x00,0x00,0x0F,0xFF,0xE0,0x00,0x03,0xFF,0xE0,0x00, +0x00,0x00,0x03,0xFF,0xFC,0x00,0x00,0xFF,0xF8,0x00, +0x00,0x00,0x00,0x7F,0xFF,0x00,0x00,0x3F,0xFE,0x00, +0x00,0x00,0x00,0x0F,0xFF,0xE0,0x00,0x0F,0xFF,0x80, +0x00,0x00,0x00,0x03,0xFF,0xFC,0x00,0x03,0xFF,0xE0, +0x00,0x00,0x00,0x00,0x7F,0xFF,0x00,0x00,0xFF,0xF8, +0x00,0x00,0x00,0x00,0x0F,0xFF,0xE0,0x00,0x3F,0xFE, +0x00,0x00,0x00,0x00,0x03,0xFF,0xFC,0x00,0x0F,0xFF, +0x80,0x00,0x00,0x00,0x00,0x7F,0xFF,0x00,0x04,0x7F, +0xFC,0x00,0x00,0x00,0x00,0x01,0xFF,0xFC,0x00,0x1F, +0xFF,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0x80,0x07, +0xFF,0xC0,0x00,0x00,0x00,0x00,0x0F,0xFF,0xF0,0x01, +0xFF,0xF0,0x00,0x00,0x00,0x00,0x01,0xFF,0xFC,0x00, +0x8F,0xFF,0x80,0x00,0x00,0x00,0x00,0x07,0xFF,0xF0, +0x03,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0xFF,0xFE, +0x01,0x1F,0xFF,0x00,0x00,0x00,0x00,0x00,0x03,0xFF, +0xF8,0x07,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x7F, +0xFF,0x01,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x1F, +0xFF,0xE0,0x7F,0xFC,0x00,0x00,0x00,0x00,0x00,0x03, +0xFF,0xF8,0x23,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00, +0x0F,0xFF,0xE0,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00, +0x01,0xFF,0xFC,0x3F,0xFE,0x00,0x00,0x00,0x00,0x00, +0x00,0x7F,0xFF,0x8F,0xFF,0x80,0x00,0x00,0x00,0x00, +0x00,0x0F,0xFF,0xE4,0x7F,0xFC,0x00,0x00,0x00,0x00, +0x00,0x00,0x3F,0xFF,0x9F,0xFF,0x00,0x00,0x00,0x00, +0x00,0x00,0x07,0xFF,0xF0,0x13,0x30,0x9B,0xFD,0x64, +0x00,0x00,0x00,0x03,0xFF,0xF8,0x00,0x00,0x00,0x00, +0x00,0x00,0x07,0xFF,0xFF,0xFE,0x00,0x00,0x00,0x00, +0x00,0x01,0xFF,0xFF,0xFF,0xFE,0x00,0x00,0x00,0x00, +0x00,0x7F,0xFF,0xFF,0xFF,0xFE,0x00,0x00,0x00,0x00, +0x0F,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x00,0x00, +0xFF,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x00,0x1F, +0xFF,0xFF,0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x01,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x1F,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x01,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x1F,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x01,0xFF,0xFF,0xFC, +0x00,0x1F,0xFF,0xFF,0xC0,0x00,0x1F,0xFF,0xFC,0x00, +0x00,0x0F,0xFF,0xFF,0x00,0x00,0xFF,0xFF,0x80,0x00, +0x00,0x0F,0xFF,0xF8,0x00,0x0F,0xFF,0xF0,0x00,0x00, +0x00,0x3F,0xFF,0xE0,0x00,0xFF,0xFF,0x00,0x00,0x00, +0x00,0x7F,0xFF,0x80,0x07,0xFF,0xF0,0x00,0x00,0x00, +0x01,0xFF,0xFC,0x00,0x3F,0xFF,0x00,0x00,0x00,0x00, +0x07,0xFF,0xF0,0x03,0xFF,0xF0,0x00,0x00,0x00,0x00, +0x1F,0xFF,0x80,0x1F,0xFF,0x00,0x00,0x00,0x00,0x00, +0xFF,0xFC,0x00,0xFF,0xF8,0x00,0x00,0x00,0x00,0x03, +0xFF,0xF0,0x0F,0xFF,0xC0,0x00,0x00,0x00,0x00,0x1F, +0xFF,0x88,0x0F,0xFF,0x80,0x00,0x00,0x00,0x00,0x0F, +0xFF,0x80,0x7F,0xFC,0x00,0x00,0x00,0x00,0x00,0x7F, +0xFE,0x48,0x7F,0xFC,0x00,0x00,0x00,0x00,0x00,0x3F, +0xFE,0x03,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x00, +0x02,0x03,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x0F,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x7F,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x03,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x0F,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x7F,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x01, +0xFF,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x0F, +0xFF,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x3F, +0xFF,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0xFF, +0xFF,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x03,0xFF, +0xFF,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF, +0xFF,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF, +0xFF,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF, +0xFF,0xFF,0xFE,0x00,0x00,0x00,0x00,0x01,0xFF,0xFF, +0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x07,0xFF,0xFF, +0xFF,0xFF,0xFE,0x00,0x00,0x00,0x00,0x0F,0xFF,0xFF, +0xFF,0xFF,0xFE,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF, +0xFF,0xFF,0xFC,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF, +0xFF,0xFF,0xF0,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF, +0xFF,0xFF,0xE0,0x00,0x00,0x00,0x00,0x0F,0xFF,0xFF, +0xFF,0xFF,0x80,0x00,0x00,0x00,0x00,0x0F,0xFF,0xFF, +0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xFF, +0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xFF, +0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xFF, +0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF, +0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF, +0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xFF, +0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xFF, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xF8, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xE0, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xF9,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xD1,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xF1,0xFF, +0xF8,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xF0,0xFF, +0xF8,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xF2,0xFF, +0xFC,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xE3,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0x1F,0xFF, +0x80,0x00,0x00,0x00,0x00,0x01,0xFF,0xF0,0xFF,0xFE, +0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0x83,0xFF,0xF8, +0x00,0x00,0x00,0x00,0x00,0xFF,0xFC,0x1F,0xFF,0xC0, +0x00,0x00,0x00,0x00,0x0F,0xFF,0xC0,0x7F,0xFF,0x00, +0x00,0x00,0x00,0x00,0x7F,0xFE,0x03,0xFF,0xFC,0x00, +0x00,0x00,0x00,0x07,0xFF,0xF0,0x0F,0xFF,0xF8,0x00, +0x00,0x00,0x00,0x7F,0xFF,0x00,0x7F,0xFF,0xE0,0x00, +0x00,0x00,0x07,0xFF,0xF8,0x01,0xFF,0xFF,0xC0,0x00, +0x00,0x00,0xFF,0xFF,0x80,0x07,0xFF,0xFF,0x80,0x00, +0x00,0x1F,0xFF,0xF8,0x00,0x1F,0xFF,0xFF,0x80,0x00, +0x07,0xFF,0xFF,0xC0,0x00,0x7F,0xFF,0xFF,0xC0,0x03, +0xFF,0xFF,0xFC,0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xC0,0x00,0x07,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFC,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xC0,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFC,0x00,0x00,0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0x80,0x00,0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xF8, +0x00,0x00,0x00,0x07,0xFF,0xFF,0xFF,0xFF,0xFF,0x00, +0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFF,0xFF,0xE0,0x00, +0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFF,0xF8,0x00,0x00, +0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFE,0x00,0x00,0x00, +0x00,0x00,0x00,0x01,0xFF,0xFE,0x00,0x00,0x00,0x00, +0x12,0xEF,0x8C,0x01,0x47,0x7F,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFD,0x7F,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFD,0x00,0x00,0x00,0x01,0xFF, +0xF0,0x00,0x00,0x00,0x1A,0x00,0x00,0x00,0x03,0xFF, +0xE0,0x00,0x00,0x00,0x34,0x00,0x00,0x00,0x07,0xFF, +0xC0,0x00,0x00,0x00,0x68,0x00,0x00,0x00,0x0F,0xFF, +0x80,0x00,0x00,0x00,0xD0,0x00,0x00,0x00,0x1F,0xFF, +0x00,0x00,0x00,0x01,0xA0,0x00,0x00,0x00,0x3F,0xFE, +0x00,0x00,0x00,0x03,0x40,0x00,0x00,0x00,0x7F,0xFC, +0x00,0x00,0x00,0x06,0x80,0x00,0x00,0x00,0xFF,0xF8, +0x00,0x00,0x00,0x0D,0x00,0x00,0x00,0x01,0xFF,0xF0, +0x00,0x00,0x00,0x1A,0x00,0x00,0x00,0x03,0xFF,0xE0, +0x00,0x00,0x00,0x34,0x00,0x00,0x00,0x07,0xFF,0xC0, +0x00,0x00,0x00,0x68,0x00,0x00,0x00,0x0F,0xFF,0x80, +0x00,0x00,0x00,0x12,0xB0,0x2F,0xFD,0x83,0x7F,0xFE, +0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xFD,0xFF,0xF8, +0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xF7,0xFF,0xE0, +0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xDF,0xFF,0x80, +0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0x7F,0xFE,0x00, +0x00,0x00,0x00,0x00,0x01,0xFF,0xFD,0xFF,0xF8,0x00, +0x00,0x00,0x00,0x00,0x07,0xFF,0xF7,0xFF,0xE0,0x00, +0x00,0x00,0x00,0x00,0x1F,0xFF,0xDF,0xFF,0x80,0x00, +0x00,0x00,0x00,0x00,0x7F,0xFF,0x7F,0xFE,0x00,0x00, +0x00,0x00,0x00,0x01,0xFF,0xF7,0xFF,0xC0,0x00,0x00, +0x00,0x00,0x00,0x7F,0xFE,0xFF,0xFC,0x00,0x00,0x00, +0x00,0x00,0x0F,0xFF,0xE9,0xFF,0xF0,0x00,0x00,0x00, +0x00,0x00,0x3F,0xFE,0x3F,0xFE,0x00,0x00,0x00,0x00, +0x00,0x0F,0xFF,0xC7,0xFF,0xE0,0x00,0x00,0x00,0x00, +0x01,0xFF,0xF8,0x7F,0xFC,0x00,0x00,0x00,0x00,0x00, +0x3F,0xFE,0x0F,0xFF,0x80,0x00,0x00,0x00,0x00,0x0F, +0xFF,0xC8,0x3F,0xFF,0x00,0x00,0x00,0x00,0x00,0x3F, +0xFF,0x03,0xFF,0xF0,0x00,0x00,0x00,0x00,0x0F,0xFF, +0xC0,0x7F,0xFF,0x00,0x00,0x00,0x00,0x03,0xFF,0xF8, +0x0F,0xFF,0xF0,0x00,0x00,0x00,0x00,0x7F,0xFF,0x00, +0xFF,0xFF,0x00,0x00,0x00,0x00,0x1F,0xFF,0xC0,0x1F, +0xFF,0xF0,0x00,0x00,0x00,0x0F,0xFF,0xF8,0x01,0xFF, +0xFF,0x00,0x00,0x00,0x03,0xFF,0xFE,0x00,0x3F,0xFF, +0xF8,0x00,0x00,0x01,0xFF,0xFF,0xC0,0x03,0xFF,0xFF, +0xC0,0x00,0x01,0xFF,0xFF,0xF0,0x00,0x7F,0xFF,0xFF, +0x80,0x03,0xFF,0xFF,0xFC,0x00,0x07,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x7F,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xE0,0x00,0x07,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xF8,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFE,0x00,0x00,0x07,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0x00,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF, +0xC0,0x00,0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0, +0x00,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xF8,0x00, +0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x00, +0x00,0x00,0x07,0xFF,0xFF,0xFF,0xFE,0x00,0x00,0x00, +0x00,0x00,0x0F,0xFF,0xFF,0xFC,0x00,0x00,0x00,0x00, +0x00,0x00,0x0F,0xFF,0xF0,0x00,0x00,0x00,0x00,0x16, +0xEF,0xFC,0x01,0x65,0xFF,0xF8,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x0F,0xFF,0xE1,0xFF,0xF8,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0x0F,0xFF,0x80, +0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xE0,0xFF, +0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFE, +0x07,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x07, +0xFF,0xE0,0x7F,0xFC,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0xFF,0xFC,0x07,0xFF,0xE0,0x00,0x00,0x00,0x00, +0x00,0x00,0x0F,0xFF,0xC0,0x3F,0xFE,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0xFF,0xF8,0x03,0xFF,0xF0,0x00, +0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0x80,0x1F,0xFF, +0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xF8,0x01, +0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF, +0x00,0x1F,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x03, +0xFF,0xF0,0x00,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00, +0x00,0x3F,0xFE,0x00,0x0F,0xFF,0xC0,0x00,0x00,0x00, +0x00,0x00,0x07,0xFF,0xE0,0x00,0x7F,0xFC,0x00,0x00, +0x00,0x00,0x00,0x00,0x7F,0xFE,0x00,0x07,0xFF,0xC0, +0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xC0,0x00,0x7F, +0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFC,0x00, +0x03,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF, +0x80,0x00,0x3F,0xFE,0x00,0x00,0x00,0x00,0x00,0x01, +0xFF,0xF8,0x00,0x01,0xFF,0xF0,0x00,0x00,0x00,0x00, +0x00,0x1F,0xFF,0x80,0x00,0x1F,0xFF,0x00,0x00,0x00, +0x00,0x00,0x01,0xFF,0xF0,0x00,0x01,0xFF,0xF8,0x00, +0x00,0x00,0x00,0x00,0x3F,0xFF,0x00,0x40,0x01,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x00,0x7F,0xFC,0x00,0x00, +0x0F,0xFF,0x80,0x00,0x00,0x00,0x00,0x0F,0xFF,0xC0, +0x00,0x00,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0xFF, +0xF8,0x00,0x00,0x07,0xFF,0xC0,0x00,0x00,0x00,0x00, +0x1F,0xFF,0x80,0x08,0x00,0x0F,0xFF,0x80,0x00,0x00, +0x00,0x00,0x3F,0xFE,0x00,0x00,0x00,0x7F,0xFC,0x00, +0x00,0x00,0x00,0x07,0xFF,0xE0,0x00,0x00,0x07,0xFF, +0xC0,0x00,0x00,0x00,0x00,0x7F,0xFC,0x00,0x00,0x00, +0x3F,0xFC,0x00,0x00,0x00,0x00,0x0F,0xFF,0xC0,0x01, +0x00,0x00,0x7F,0xFC,0x00,0x00,0x00,0x00,0x1F,0xFF, +0x00,0x00,0x00,0x03,0xFF,0xE0,0x00,0x00,0x00,0x03, +0xFF,0xF0,0x00,0x00,0x00,0x3F,0xFE,0x00,0x00,0x00, +0x00,0x3F,0xFE,0x00,0x00,0x00,0x01,0xFF,0xE0,0x00, +0x00,0x00,0x03,0xFF,0xE0,0x00,0x20,0x00,0x03,0xFF, +0xE0,0x00,0x00,0x00,0x0F,0xFF,0x80,0x00,0x00,0x00, +0x1F,0xFF,0x00,0x00,0x00,0x01,0xFF,0xF8,0x00,0x00, +0x00,0x01,0xFF,0xF0,0x00,0x00,0x00,0x1F,0xFF,0x00, +0x00,0x00,0x00,0x0F,0xFF,0x00,0x00,0x00,0x01,0xFF, +0xF0,0x00,0x00,0x00,0x00,0xFF,0xF8,0x00,0x00,0x00, +0x3F,0xFE,0x00,0x00,0x00,0x00,0x07,0xFF,0x80,0x00, +0x00,0x03,0xFF,0xE0,0x00,0x00,0x00,0x00,0x7F,0xF8, +0x00,0x00,0x00,0x7F,0xFE,0x00,0x00,0x00,0x00,0x07, +0xFF,0xC0,0x00,0x00,0x07,0xFF,0xC0,0x00,0x00,0x00, +0x00,0x3F,0xFC,0x00,0x00,0x00,0x7F,0xFC,0x00,0x00, +0x00,0x00,0x03,0xFF,0xE0,0x00,0x00,0x0F,0xFF,0x80, +0x00,0x04,0x00,0x00,0x03,0xFF,0xC0,0x00,0x00,0x1F, +0xFF,0x00,0x00,0x00,0x00,0x00,0x3F,0xFE,0x00,0x00, +0x03,0xFF,0xE0,0x00,0x00,0x00,0x00,0x01,0xFF,0xE0, +0x00,0x00,0x3F,0xFE,0x00,0x00,0x00,0x00,0x00,0x1F, +0xFF,0x00,0x00,0x07,0xFF,0xC0,0x00,0x00,0x80,0x00, +0x00,0x1F,0xFE,0x00,0x00,0x0F,0xFF,0x80,0x00,0x00, +0x00,0x00,0x01,0xFF,0xF0,0x00,0x01,0xFF,0xF0,0x00, +0x00,0x00,0x00,0x00,0x0F,0xFF,0x00,0x00,0x1F,0xFF, +0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xF0,0x00,0x03, +0xFF,0xE0,0x00,0x00,0x10,0x00,0x00,0x00,0xFF,0xF0, +0x00,0x07,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x0F, +0xFF,0x80,0x00,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00, +0x00,0x7F,0xF8,0x00,0x0F,0xFF,0x80,0x00,0x00,0x00, +0x00,0x00,0x07,0xFF,0x80,0x00,0xFF,0xF0,0x00,0x00, +0x02,0x00,0x00,0x00,0x07,0xFF,0x80,0x03,0xFF,0xE0, +0x00,0x00,0x04,0x00,0x00,0x00,0x07,0xFF,0x80,0x0F, +0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xF8, +0x00,0xFF,0xF0,0x00,0x00,0x00,0x80,0x00,0x00,0x00, +0x7F,0xF8,0x03,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00, +0x00,0x03,0xFF,0x80,0x7F,0xFC,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x3F,0xFC,0x07,0xFF,0xC0,0x00,0x00, +0x00,0x00,0x00,0x00,0x03,0xFF,0xC0,0x7F,0xF8,0x00, +0x00,0x00,0x10,0x00,0x00,0x00,0x03,0xFF,0xC1,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xFC, +0x1F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01, +0xFF,0xE3,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x1F,0xFE,0x3F,0xFC,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0xFF,0xE3,0xFF,0xC0,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x0F,0xFF,0x7F,0xFC,0x00,0x00, +0x00,0x02,0x00,0x00,0x00,0x00,0x0F,0xFE,0xFF,0xF0, +0x00,0x00,0x00,0x04,0x80,0x00,0x00,0x00,0x0F,0xFF, +0xFF,0xC0,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x00, +0x0F,0xFF,0xFF,0x00,0x00,0x00,0x00,0x12,0x00,0x00, +0x00,0x00,0x0F,0xFF,0xFC,0x00,0x00,0x00,0x00,0x20, +0x00,0x00,0x00,0x00,0x0F,0xFF,0xF0,0x00,0x00,0x00, +0x00,0x40,0x00,0x00,0x00,0x00,0x0F,0xFF,0xC0,0x00, +0x00,0x00,0x00,0x1F,0x2F,0x88,0x01,0xFE,0x3F,0xFF, +0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x80,0x00,0x00, +0x00,0x00,0xFF,0xFC,0xFF,0xF8,0x00,0x00,0x00,0x00, +0x07,0xFF,0xFC,0x00,0x00,0x00,0x00,0x07,0xFF,0xC7, +0xFF,0xC0,0x00,0x00,0x00,0x00,0x7F,0xFF,0xF0,0x00, +0x00,0x00,0x00,0x3F,0xFE,0x3F,0xFE,0x00,0x00,0x00, +0x00,0x03,0xFF,0xFF,0x80,0x00,0x00,0x00,0x03,0xFF, +0xF1,0xFF,0xF8,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFC, +0x00,0x00,0x00,0x00,0x1F,0xFF,0x87,0xFF,0xC0,0x00, +0x00,0x00,0x00,0xFF,0xFF,0xF0,0x00,0x00,0x00,0x00, +0xFF,0xF9,0x07,0xFF,0xC0,0x00,0x00,0x00,0x01,0xFF, +0xFF,0xF0,0x00,0x00,0x00,0x00,0xFF,0xF8,0x1F,0xFF, +0x00,0x00,0x00,0x00,0x0F,0xFF,0xFF,0x80,0x00,0x00, +0x00,0x0F,0xFF,0x88,0x1F,0xFF,0x00,0x00,0x00,0x00, +0x1F,0xFF,0xFF,0xC0,0x00,0x00,0x00,0x0F,0xFF,0x80, +0xFF,0xF8,0x00,0x00,0x00,0x00,0xFF,0xEF,0xFE,0x00, +0x00,0x00,0x00,0x7F,0xFC,0x03,0xFF,0xE0,0x00,0x00, +0x00,0x07,0xFF,0x7F,0xF0,0x00,0x00,0x00,0x07,0xFF, +0xC0,0x1F,0xFF,0x00,0x00,0x00,0x00,0x7F,0xFB,0xFF, +0xC0,0x00,0x00,0x00,0x3F,0xFE,0x10,0x1F,0xFF,0x00, +0x00,0x00,0x00,0x7F,0xF1,0xFF,0xC0,0x00,0x00,0x00, +0x3F,0xFE,0x00,0x7F,0xFC,0x00,0x00,0x00,0x03,0xFF, +0x8F,0xFF,0x00,0x00,0x00,0x03,0xFF,0xE0,0x03,0xFF, +0xE0,0x00,0x00,0x00,0x3F,0xFC,0x7F,0xF8,0x00,0x00, +0x00,0x1F,0xFF,0x04,0x03,0xFF,0xE0,0x00,0x00,0x00, +0x3F,0xF8,0x3F,0xF8,0x00,0x00,0x00,0x1F,0xFF,0x00, +0x0F,0xFF,0x00,0x00,0x00,0x01,0xFF,0xC1,0xFF,0xE0, +0x00,0x00,0x00,0xFF,0xF0,0x00,0x7F,0xFC,0x00,0x00, +0x00,0x1F,0xFE,0x0F,0xFF,0x00,0x00,0x00,0x0F,0xFF, +0x80,0x03,0xFF,0xE0,0x00,0x00,0x00,0xFF,0xE0,0x3F, +0xF8,0x00,0x00,0x00,0x7F,0xFC,0x00,0x0F,0xFF,0x00, +0x00,0x00,0x07,0xFF,0x01,0xFF,0xC0,0x00,0x00,0x03, +0xFF,0xC0,0x00,0x7F,0xF8,0x00,0x00,0x00,0x7F,0xF8, +0x0F,0xFF,0x00,0x00,0x00,0x1F,0xFE,0x00,0x03,0xFF, +0xE0,0x00,0x00,0x03,0xFF,0xC0,0x7F,0xF8,0x00,0x00, +0x01,0xFF,0xF0,0x00,0x1F,0xFF,0x00,0x00,0x00,0x1F, +0xFC,0x01,0xFF,0xC0,0x00,0x00,0x0F,0xFF,0x80,0x00, +0x7F,0xF8,0x00,0x00,0x00,0xFF,0xE0,0x0F,0xFF,0x00, +0x00,0x00,0x7F,0xF8,0x00,0x03,0xFF,0xC0,0x00,0x00, +0x0F,0xFF,0x00,0x7F,0xF8,0x00,0x00,0x03,0xFF,0xC0, +0x20,0x03,0xFF,0xE0,0x00,0x00,0x0F,0xFE,0x00,0x3F, +0xF8,0x00,0x00,0x07,0xFF,0xC0,0x00,0x0F,0xFF,0x00, +0x00,0x00,0x7F,0xF0,0x01,0xFF,0xE0,0x00,0x00,0x3F, +0xFC,0x00,0x00,0x7F,0xF8,0x00,0x00,0x07,0xFF,0x80, +0x0F,0xFF,0x00,0x00,0x01,0xFF,0xE0,0x00,0x03,0xFF, +0xC0,0x00,0x00,0x3F,0xF8,0x00,0x3F,0xF8,0x00,0x00, +0x1F,0xFF,0x00,0x00,0x1F,0xFF,0x00,0x00,0x01,0xFF, +0xC0,0x01,0xFF,0xE0,0x00,0x00,0xFF,0xF8,0x00,0x00, +0x7F,0xF8,0x00,0x00,0x0F,0xFE,0x00,0x0F,0xFF,0x00, +0x00,0x07,0xFF,0x80,0x00,0x03,0xFF,0xC0,0x00,0x00, +0xFF,0xF0,0x00,0x7F,0xF8,0x00,0x00,0x3F,0xFC,0x00, +0x00,0x1F,0xFE,0x00,0x00,0x07,0xFF,0x00,0x01,0xFF, +0xC0,0x00,0x01,0xFF,0xE0,0x00,0x00,0xFF,0xF8,0x00, +0x00,0x3F,0xF8,0x00,0x0F,0xFF,0x00,0x00,0x1F,0xFF, +0x00,0x20,0x00,0x7F,0xF8,0x00,0x00,0x7F,0xF8,0x00, +0x0F,0xFF,0x00,0x00,0x1F,0xFE,0x00,0x00,0x03,0xFF, +0xC0,0x00,0x03,0xFF,0x80,0x00,0x3F,0xF8,0x00,0x00, +0xFF,0xF0,0x00,0x00,0x0F,0xFF,0x00,0x00,0x1F,0xFC, +0x00,0x01,0xFF,0xE0,0x00,0x0F,0xFF,0x00,0x00,0x00, +0x7F,0xF8,0x00,0x01,0xFF,0xE0,0x00,0x0F,0xFF,0x00, +0x00,0x7F,0xF8,0x00,0x00,0x03,0xFF,0xC0,0x00,0x0F, +0xFE,0x00,0x00,0x3F,0xF8,0x00,0x03,0xFF,0xC0,0x00, +0x00,0x1F,0xFE,0x00,0x00,0x7F,0xF0,0x00,0x01,0xFF, +0xE0,0x00,0x1F,0xFE,0x00,0x00,0x00,0x7F,0xF8,0x00, +0x03,0xFF,0x80,0x00,0x0F,0xFF,0x00,0x01,0xFF,0xE0, +0x00,0x00,0x03,0xFF,0xC0,0x00,0x3F,0xFC,0x00,0x00, +0x7F,0xF8,0x00,0x0F,0xFF,0x00,0x00,0x00,0x1F,0xFE, +0x00,0x01,0xFF,0xC0,0x00,0x01,0xFF,0xC0,0x00,0x7F, +0xF8,0x00,0x00,0x00,0xFF,0xF0,0x00,0x0F,0xFE,0x00, +0x00,0x0F,0xFF,0x00,0x03,0xFF,0xC0,0x00,0x00,0x03, +0xFF,0x80,0x00,0x7F,0xF0,0x00,0x00,0x7F,0xF8,0x00, +0x1F,0xFC,0x00,0x00,0x00,0x1F,0xFE,0x00,0x07,0xFF, +0x80,0x00,0x03,0xFF,0xC0,0x01,0xFF,0xE0,0x00,0x00, +0x00,0xFF,0xF0,0x00,0x3F,0xF8,0x00,0x00,0x0F,0xFE, +0x00,0x0F,0xFF,0x00,0x00,0x00,0x07,0xFF,0x80,0x01, +0xFF,0xC0,0x00,0x00,0x7F,0xF8,0x00,0x7F,0xF8,0x00, +0x00,0x00,0x1F,0xFC,0x00,0x1F,0xFE,0x00,0x00,0x03, +0xFF,0xC0,0x03,0xFF,0x80,0x00,0x80,0x00,0x1F,0xFE, +0x00,0x1F,0xFC,0x00,0x00,0x01,0xFF,0xC0,0x07,0xFF, +0x80,0x00,0x00,0x00,0x7F,0xF0,0x00,0xFF,0xE0,0x00, +0x00,0x0F,0xFE,0x00,0x3F,0xF8,0x00,0x00,0x00,0x03, +0xFF,0x80,0x0F,0xFF,0x00,0x00,0x00,0x7F,0xF8,0x01, +0xFF,0xC0,0x00,0x20,0x00,0x03,0xFF,0xC0,0x0F,0xFE, +0x00,0x00,0x00,0x3F,0xF8,0x03,0xFF,0xC0,0x00,0x00, +0x00,0x0F,0xFE,0x00,0x7F,0xF0,0x00,0x00,0x01,0xFF, +0xC0,0x1F,0xFC,0x00,0x00,0x00,0x00,0x7F,0xF0,0x07, +0xFF,0x80,0x00,0x00,0x0F,0xFF,0x00,0xFF,0xE0,0x00, +0x00,0x00,0x03,0xFF,0x80,0x3F,0xF8,0x00,0x00,0x00, +0x3F,0xF8,0x0F,0xFF,0x00,0x00,0x00,0x00,0x1F,0xFE, +0x01,0xFF,0xC0,0x00,0x00,0x01,0xFF,0xC0,0x7F,0xF8, +0x00,0x00,0x00,0x00,0x7F,0xF0,0x0F,0xFE,0x00,0x00, +0x00,0x0F,0xFE,0x03,0xFF,0x80,0x00,0x00,0x00,0x03, +0xFF,0x80,0xFF,0xF0,0x00,0x00,0x00,0x7F,0xF8,0x1F, +0xFC,0x00,0x00,0x00,0x00,0x1F,0xFC,0x07,0xFF,0x00, +0x00,0x00,0x01,0xFF,0xC0,0xFF,0xE0,0x00,0x00,0x00, +0x00,0xFF,0xF0,0x3F,0xF8,0x00,0x00,0x00,0x0F,0xFE, +0x0F,0xFF,0x00,0x00,0x00,0x00,0x03,0xFF,0x83,0xFF, +0xC0,0x00,0x00,0x00,0x7F,0xF0,0x7F,0xF0,0x00,0x00, +0x00,0x00,0x1F,0xFC,0x1F,0xFC,0x00,0x00,0x00,0x01, +0xFF,0x83,0xFF,0x80,0x00,0x00,0x00,0x00,0xFF,0xE0, +0xFF,0xE0,0x00,0x00,0x00,0x0F,0xFE,0x1F,0xFC,0x00, +0x00,0x00,0x00,0x03,0xFF,0x87,0xFF,0x00,0x00,0x00, +0x00,0x7F,0xF1,0xFF,0xC0,0x00,0x00,0x00,0x00,0x1F, +0xFC,0x7F,0xF8,0x00,0x00,0x00,0x03,0xFF,0x8F,0xFE, +0x00,0x00,0x10,0x00,0x00,0x1F,0xFC,0x7F,0xF0,0x00, +0x00,0x00,0x01,0xFF,0x8F,0xFE,0x00,0x00,0x00,0x00, +0x00,0x7F,0xE3,0xFF,0x80,0x00,0x00,0x00,0x0F,0xFE, +0xFF,0xE0,0x00,0x00,0x00,0x00,0x03,0xFF,0xBF,0xFC, +0x00,0x00,0x00,0x00,0x7F,0xF7,0xFF,0x00,0x00,0x04, +0x00,0x00,0x03,0xFF,0xBF,0xF8,0x00,0x00,0x00,0x00, +0x3F,0xF7,0xFF,0x00,0x00,0x00,0x00,0x00,0x0F,0xFD, +0xFF,0xC0,0x00,0x00,0x00,0x01,0xFF,0xBF,0xF0,0x00, +0x00,0x00,0x00,0x00,0x7F,0xFF,0xFE,0x00,0x00,0x00, +0x00,0x0F,0xFF,0xFF,0x80,0x00,0x01,0x00,0x00,0x00, +0x7F,0xFF,0xFC,0x00,0x00,0x00,0x00,0x07,0xFF,0xFF, +0x80,0x00,0x00,0x00,0x00,0x01,0xFF,0xFF,0xE0,0x00, +0x00,0x00,0x00,0x3F,0xFF,0xF8,0x00,0x00,0x08,0x00, +0x00,0x01,0xFF,0xFF,0xC0,0x00,0x00,0x00,0x00,0x1F, +0xFF,0xF8,0x00,0x00,0x08,0x00,0x00,0x00,0xFF,0xFF, +0xC0,0x00,0x00,0x00,0x00,0x1F,0xFF,0xF0,0x00,0x00, +0x08,0x00,0x00,0x00,0xFF,0xFF,0x80,0x00,0x00,0x00, +0x00,0x0F,0xFF,0xF0,0x00,0x00,0x08,0x00,0x00,0x00, +0x7F,0xFF,0x80,0x00,0x00,0x00,0x00,0x0F,0xFF,0xE0, +0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xF8,0x00,0x00, +0x00,0x00,0x00,0x3F,0xFF,0x00,0x00,0x00,0x00,0x15, +0xAF,0x84,0x01,0x64,0x0F,0xFF,0xF0,0x00,0x00,0x00, +0x00,0x00,0x0F,0xFF,0xE0,0x0F,0xFF,0xE0,0x00,0x00, +0x00,0x00,0x00,0x1F,0xFF,0xC0,0x1F,0xFF,0xE0,0x00, +0x00,0x00,0x00,0x00,0x7F,0xFF,0x00,0x1F,0xFF,0xE0, +0x00,0x00,0x00,0x00,0x01,0xFF,0xFC,0x00,0x1F,0xFF, +0xC0,0x00,0x00,0x00,0x00,0x07,0xFF,0xF0,0x00,0x3F, +0xFF,0xC0,0x00,0x00,0x00,0x00,0x0F,0xFF,0xE0,0x00, +0x3F,0xFF,0xC0,0x00,0x00,0x00,0x00,0x3F,0xFF,0x80, +0x00,0x3F,0xFF,0xC0,0x00,0x00,0x00,0x00,0xFF,0xFE, +0x00,0x00,0x3F,0xFF,0x80,0x00,0x00,0x00,0x01,0xFF, +0xF8,0x00,0x00,0x7F,0xFF,0x80,0x00,0x00,0x00,0x07, +0xFF,0xF0,0x00,0x00,0x7F,0xFF,0x80,0x00,0x00,0x00, +0x1F,0xFF,0xC0,0x00,0x00,0x7F,0xFF,0x00,0x00,0x00, +0x00,0x7F,0xFF,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00, +0x00,0x00,0xFF,0xFE,0x00,0x00,0x00,0xFF,0xFF,0x00, +0x00,0x00,0x03,0xFF,0xF8,0x00,0x00,0x00,0xFF,0xFE, +0x00,0x00,0x00,0x0F,0xFF,0xE0,0x00,0x00,0x01,0xFF, +0xFE,0x00,0x00,0x00,0x3F,0xFF,0x80,0x00,0x00,0x01, +0xFF,0xFE,0x00,0x00,0x00,0x7F,0xFF,0x00,0x00,0x00, +0x01,0xFF,0xFC,0x00,0x00,0x01,0xFF,0xFC,0x00,0x00, +0x00,0x03,0xFF,0xFC,0x00,0x00,0x07,0xFF,0xF0,0x00, +0x00,0x00,0x03,0xFF,0xFC,0x00,0x00,0x1F,0xFF,0xC0, +0x00,0x00,0x00,0x03,0xFF,0xFC,0x00,0x00,0x3F,0xFF, +0x80,0x00,0x00,0x00,0x03,0xFF,0xF8,0x00,0x00,0xFF, +0xFE,0x00,0x00,0x00,0x00,0x07,0xFF,0xF8,0x00,0x03, +0xFF,0xF8,0x00,0x00,0x00,0x00,0x07,0xFF,0xF8,0x00, +0x0F,0xFF,0xF0,0x00,0x00,0x00,0x00,0x07,0xFF,0xF0, +0x00,0x1F,0xFF,0xC0,0x00,0x00,0x00,0x00,0x0F,0xFF, +0xF0,0x00,0x7F,0xFF,0x00,0x00,0x00,0x00,0x00,0x0F, +0xFF,0xF0,0x01,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00, +0x0F,0xFF,0xE0,0x07,0xFF,0xF8,0x00,0x00,0x00,0x00, +0x00,0x1F,0xFF,0xE0,0x0F,0xFF,0xE0,0x00,0x00,0x00, +0x00,0x00,0x1F,0xFF,0xE0,0x3F,0xFF,0x80,0x00,0x00, +0x00,0x00,0x00,0x1F,0xFF,0xC0,0xFF,0xFE,0x00,0x00, +0x00,0x00,0x00,0x00,0x1F,0xFF,0xC1,0xFF,0xFC,0x00, +0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xC7,0xFF,0xF0, +0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0x9F,0xFF, +0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xFF, +0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF, +0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F, +0xFF,0xFF,0xF8,0x00,0x00,0x00,0x40,0x00,0x00,0x00, +0x0F,0xFF,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x0F,0xFF,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x0F,0xFF,0xFF,0xC0,0x00,0x00,0x00,0x40, +0x00,0x00,0x00,0x01,0xFF,0xFF,0xE0,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x01,0xFF,0xFF,0x80,0x00,0x00, +0x00,0x20,0x00,0x00,0x00,0x00,0x3F,0xFF,0xC0,0x00, +0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x1F,0xFF,0xF8, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF, +0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xFF, +0xFF,0xF8,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x00, +0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x03,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x04,0x00,0x00, +0x00,0x01,0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x00,0x00, +0x00,0x00,0x07,0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x00, +0x00,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xE0,0x00,0x00, +0x00,0x00,0x00,0x00,0x7F,0xFF,0x9F,0xFF,0xC0,0x00, +0x00,0x00,0x00,0x00,0x00,0xFF,0xFE,0x3F,0xFF,0xC0, +0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xF8,0x3F,0xFF, +0xC0,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0xF0,0x3F, +0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xC0, +0x7F,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF, +0x00,0x7F,0xFF,0x80,0x00,0x00,0x00,0x00,0x01,0xFF, +0xFC,0x00,0x7F,0xFF,0x80,0x00,0x00,0x00,0x00,0x07, +0xFF,0xF8,0x00,0x7F,0xFF,0x00,0x00,0x00,0x00,0x00, +0x1F,0xFF,0xE0,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00, +0x00,0x3F,0xFF,0x80,0x00,0xFF,0xFF,0x00,0x00,0x00, +0x00,0x00,0xFF,0xFF,0x00,0x00,0xFF,0xFE,0x00,0x00, +0x00,0x00,0x03,0xFF,0xFC,0x00,0x01,0xFF,0xFE,0x00, +0x00,0x00,0x00,0x0F,0xFF,0xF0,0x00,0x01,0xFF,0xFE, +0x00,0x00,0x00,0x00,0x1F,0xFF,0xC0,0x00,0x01,0xFF, +0xFC,0x00,0x00,0x00,0x00,0x7F,0xFF,0x80,0x00,0x03, +0xFF,0xFC,0x00,0x00,0x00,0x01,0xFF,0xFE,0x00,0x00, +0x03,0xFF,0xFC,0x00,0x00,0x00,0x07,0xFF,0xF8,0x00, +0x00,0x03,0xFF,0xFC,0x00,0x00,0x00,0x0F,0xFF,0xE0, +0x00,0x00,0x03,0xFF,0xF8,0x00,0x00,0x00,0x3F,0xFF, +0xC0,0x00,0x00,0x07,0xFF,0xF8,0x00,0x00,0x00,0xFF, +0xFF,0x00,0x00,0x00,0x07,0xFF,0xF8,0x00,0x00,0x01, +0xFF,0xFC,0x00,0x00,0x00,0x07,0xFF,0xF0,0x00,0x00, +0x07,0xFF,0xF8,0x00,0x00,0x00,0x0F,0xFF,0xF0,0x00, +0x00,0x1F,0xFF,0xE0,0x00,0x00,0x00,0x0F,0xFF,0xF0, +0x00,0x00,0x7F,0xFF,0x80,0x00,0x00,0x00,0x0F,0xFF, +0xE0,0x00,0x00,0xFF,0xFE,0x00,0x00,0x00,0x00,0x1F, +0xFF,0xE0,0x00,0x03,0xFF,0xFC,0x00,0x00,0x00,0x00, +0x1F,0xFF,0xE0,0x00,0x0F,0xFF,0xF0,0x00,0x00,0x00, +0x00,0x1F,0xFF,0xE0,0x00,0x3F,0xFF,0xC0,0x00,0x00, +0x00,0x00,0x1F,0xFF,0xC0,0x00,0x7F,0xFF,0x00,0x00, +0x00,0x00,0x00,0x3F,0xFF,0xC0,0x01,0xFF,0xFE,0x00, +0x00,0x00,0x00,0x00,0x3F,0xFF,0xC0,0x07,0xFF,0xF8, +0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0x80,0x1F,0xFF, +0xE0,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0x80,0x3F, +0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0x80, +0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF, +0x03,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0xFF, +0xFF,0x0F,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x00, +0xFF,0xFF,0x1F,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00, +0x00,0xFF,0xFF,0x7F,0xFF,0x80,0x00,0x00,0x00,0x00, +0x00,0x00,0xFF,0xFE,0x15,0xEF,0x80,0x01,0x5D,0xFF, +0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xFC, +0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xFF, +0xF8,0x7F,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x07, +0xFF,0xF0,0x7F,0xFF,0x80,0x00,0x00,0x00,0x00,0x00, +0x0F,0xFF,0xF0,0x3F,0xFF,0x80,0x00,0x00,0x00,0x00, +0x00,0x0F,0xFF,0xE0,0x1F,0xFF,0xC0,0x00,0x00,0x00, +0x00,0x00,0x1F,0xFF,0xC0,0x1F,0xFF,0xE0,0x00,0x00, +0x00,0x00,0x00,0x3F,0xFF,0xC0,0x0F,0xFF,0xE0,0x00, +0x00,0x00,0x00,0x00,0x3F,0xFF,0x80,0x07,0xFF,0xF0, +0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0x00,0x03,0xFF, +0xF8,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x03, +0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0xFF,0xFE,0x00, +0x01,0xFF,0xFC,0x00,0x00,0x00,0x00,0x01,0xFF,0xFC, +0x00,0x00,0xFF,0xFE,0x00,0x00,0x00,0x00,0x03,0xFF, +0xFC,0x00,0x00,0xFF,0xFE,0x00,0x00,0x00,0x00,0x03, +0xFF,0xF8,0x00,0x00,0x7F,0xFF,0x00,0x00,0x00,0x00, +0x07,0xFF,0xF0,0x00,0x00,0x3F,0xFF,0x80,0x00,0x00, +0x00,0x07,0xFF,0xF0,0x00,0x00,0x3F,0xFF,0x80,0x00, +0x00,0x00,0x0F,0xFF,0xE0,0x00,0x00,0x1F,0xFF,0xC0, +0x00,0x00,0x00,0x1F,0xFF,0xC0,0x00,0x00,0x0F,0xFF, +0xE0,0x00,0x00,0x00,0x1F,0xFF,0xC0,0x00,0x00,0x0F, +0xFF,0xE0,0x00,0x00,0x00,0x3F,0xFF,0x80,0x00,0x00, +0x07,0xFF,0xF0,0x00,0x00,0x00,0x7F,0xFF,0x00,0x00, +0x00,0x03,0xFF,0xF8,0x00,0x00,0x00,0x7F,0xFF,0x00, +0x00,0x00,0x03,0xFF,0xF8,0x00,0x00,0x00,0xFF,0xFE, +0x00,0x00,0x00,0x01,0xFF,0xFC,0x00,0x00,0x01,0xFF, +0xFC,0x00,0x00,0x00,0x00,0xFF,0xFC,0x00,0x00,0x01, +0xFF,0xFC,0x00,0x00,0x00,0x00,0xFF,0xFE,0x00,0x00, +0x03,0xFF,0xF8,0x00,0x00,0x00,0x00,0x7F,0xFF,0x00, +0x00,0x07,0xFF,0xF0,0x00,0x00,0x00,0x00,0x3F,0xFF, +0x00,0x00,0x07,0xFF,0xF0,0x00,0x00,0x00,0x00,0x3F, +0xFF,0x80,0x00,0x0F,0xFF,0xE0,0x00,0x00,0x00,0x00, +0x1F,0xFF,0xC0,0x00,0x1F,0xFF,0xC0,0x00,0x00,0x00, +0x00,0x0F,0xFF,0xC0,0x00,0x1F,0xFF,0x80,0x00,0x00, +0x00,0x00,0x0F,0xFF,0xE0,0x00,0x3F,0xFF,0x80,0x00, +0x00,0x00,0x00,0x07,0xFF,0xF0,0x00,0x3F,0xFF,0x00, +0x00,0x00,0x00,0x00,0x03,0xFF,0xF0,0x00,0x7F,0xFE, +0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xF8,0x00,0xFF, +0xFE,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xFC,0x00, +0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFC, +0x01,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0xFF, +0xFE,0x03,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x00, +0x7F,0xFE,0x03,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00, +0x00,0x3F,0xFF,0x07,0xFF,0xE0,0x00,0x00,0x00,0x00, +0x00,0x00,0x3F,0xFF,0x8F,0xFF,0xE0,0x00,0x00,0x00, +0x00,0x00,0x00,0x1F,0xFF,0x8F,0xFF,0xC0,0x00,0x00, +0x00,0x00,0x00,0x00,0x0F,0xFF,0xDF,0xFF,0x80,0x00, +0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFF,0x80, +0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xFF,0xFF, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xFF, +0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xFF, +0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01, +0xFF,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0xFF,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x7F,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x7F,0xFF,0xF0,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x3F,0xFF,0xE0,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xE0,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xC0,0x00, +0x00,0x00,0x03,0x40,0x00,0x00,0x00,0x01,0xFF,0xF0, +0x00,0x00,0x00,0x00,0x68,0x00,0x00,0x00,0x00,0x3F, +0xFE,0x00,0x00,0x00,0x00,0x0D,0x00,0x00,0x00,0x00, +0x07,0xFF,0xC0,0x00,0x00,0x00,0x01,0xA0,0x00,0x00, +0x00,0x00,0xFF,0xF8,0x00,0x00,0x00,0x00,0x34,0x00, +0x00,0x00,0x00,0x1F,0xFF,0x00,0x00,0x00,0x00,0x06, +0x00,0x00,0x00,0x00,0x03,0xFF,0xE0,0x00,0x00,0x00, +0x00,0x12,0xEF,0x8C,0x01,0x47,0x40,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xE5,0x01,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x00,0x00, +0x00,0x00,0x07,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0xFF,0xFF,0x80,0x00,0x00,0x00,0x00,0x00, +0x00,0x0F,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x00, +0x01,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x3F,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x07, +0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF, +0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xFE, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xE0, +0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xFC,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0x80,0x00, +0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0xF0,0x00,0x00, +0x00,0x00,0x00,0x00,0x01,0xFF,0xFE,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x3F,0xFF,0xE0,0x00,0x00,0x00, +0x00,0x00,0x00,0x07,0xFF,0xFC,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x7F,0xFF,0x80,0x00,0x00,0x00,0x00, +0x00,0x00,0x0F,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00, +0x00,0x01,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x3F,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x00, +0x03,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x7F,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x0F, +0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xFF, +0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF, +0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xFC, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0x80, +0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0xF8,0x00, +0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xFF,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xE0,0x00,0x00, +0x00,0x00,0x00,0x00,0x03,0xFF,0xFC,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x7F,0xFF,0x80,0x00,0x00,0x00, +0x00,0x00,0x00,0x0F,0xFF,0xF8,0x00,0x00,0x00,0x00, +0x00,0x00,0x01,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x1F,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00, +0x00,0x03,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x7F,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x00, +0x0F,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F, +0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xFF, +0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF, +0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0xF8, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xE0,0x00, +0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xFE,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0xC0,0x00,0x00, +0x00,0x00,0x00,0x00,0x07,0xFF,0xF8,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x1F,0xFF,0xE0,0x00,0x00,0x00,0x00, +0x00,0x00,0x03,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x7F,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00, +0x00,0x07,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x1F,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x03, +0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F, +0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xFF, +0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xF0, +0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xFE,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xC0,0x00, +0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xF8,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x80,0x00,0x00, +0x00,0x00,0x00,0x00,0x1F,0xFF,0xF0,0x00,0x00,0x00, +0x00,0x00,0x00,0x03,0xFF,0xFE,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x3F,0xFF,0xC0,0x00,0x00,0x00,0x00, +0x00,0x00,0x07,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0xFF,0xFF,0x80,0x00,0x00,0x00,0x00,0x00, +0x00,0x1F,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x00, +0x01,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x3F,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x07, +0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xDF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x5F, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFC,0x06, +0x7C,0xA3,0x98,0x97,0x7F,0xFF,0xFF,0xF5,0xFF,0xFF, +0xFF,0xDF,0xFF,0x00,0x06,0xFF,0xF8,0x00,0x37,0xFF, +0xC0,0x01,0xBF,0xFE,0x00,0x0D,0xFF,0xF0,0x00,0x6F, +0xFF,0x80,0x03,0x7F,0xFC,0x00,0x1B,0xFF,0xE0,0x00, +0xDF,0xFF,0x00,0x06,0xFF,0xF8,0x00,0x37,0xFF,0xC0, +0x01,0xBF,0xFE,0x00,0x0D,0xFF,0xF0,0x00,0x6F,0xFF, +0x80,0x01,0xFF,0xE0,0x00,0xDF,0xFF,0xFF,0xFD,0x7F, +0xFF,0xFF,0xC0,0x09,0xAF,0x84,0x00,0x96,0x3F,0xF0, +0x00,0x00,0x00,0x7F,0xF0,0x00,0x00,0x01,0x0F,0xFC, +0x00,0x00,0x00,0x1F,0xFC,0x00,0x00,0x00,0x93,0xFF, +0x00,0x00,0x00,0x07,0xFF,0x00,0x00,0x00,0x40,0xFF, +0xC0,0x00,0x00,0x01,0xFF,0xC0,0x00,0x00,0x20,0x3F, +0xF0,0x00,0x00,0x08,0x0F,0xFE,0x00,0x00,0x02,0x01, +0xFF,0x80,0x00,0x00,0x03,0xFF,0x80,0x00,0x01,0x00, +0x7F,0xE0,0x00,0x00,0x00,0xFF,0xE0,0x00,0x00,0x80, +0x1F,0xF8,0x00,0x00,0x20,0x07,0xFF,0x00,0x00,0x08, +0x00,0xFF,0xC0,0x00,0x00,0x01,0xFF,0xC0,0x00,0x04, +0x00,0x3F,0xF0,0x00,0x00,0x00,0x7F,0xF0,0x00,0x02, +0x40,0x0F,0xFC,0x00,0x00,0x00,0x1F,0xFC,0x00,0x01, +0x00,0x03,0xFF,0x00,0x00,0x00,0x07,0xFF,0x00,0x00, +0x80,0x00,0xFF,0xC0,0x00,0x20,0x00,0x3F,0xF8,0x00, +0x08,0x00,0x07,0xFE,0x00,0x00,0x00,0x0F,0xFE,0x00, +0x04,0x00,0x01,0xFF,0x80,0x00,0x00,0x03,0xFF,0x80, +0x02,0x40,0x00,0x7F,0xE0,0x00,0x00,0x00,0xFF,0xE0, +0x01,0x00,0x00,0x1F,0xF8,0x00,0x00,0x00,0x3F,0xF8, +0x00,0x80,0x00,0x07,0xFE,0x00,0x20,0x00,0x01,0xFF, +0xC0,0x08,0x00,0x00,0x3F,0xF0,0x00,0x00,0x00,0x7F, +0xF0,0x04,0x00,0x00,0x0F,0xFC,0x00,0x00,0x00,0x1F, +0xFC,0x02,0x40,0x00,0x03,0xFF,0x00,0x00,0x00,0x07, +0xFF,0x01,0x00,0x00,0x00,0xFF,0xC0,0x00,0x00,0x01, +0xFF,0xC0,0x80,0x00,0x00,0x3F,0xF0,0x20,0x00,0x00, +0x0F,0xFE,0x08,0x00,0x00,0x01,0xFF,0x80,0x00,0x00, +0x03,0xFF,0x84,0x00,0x00,0x00,0x7F,0xE0,0x00,0x00, +0x00,0xFF,0xE2,0x40,0x00,0x00,0x1F,0xF8,0x00,0x00, +0x00,0x3F,0xF9,0x00,0x00,0x00,0x07,0xFE,0x00,0x00, +0x00,0x0F,0xFE,0x80,0x00,0x00,0x01,0xFF,0xA0,0x00, +0x00,0x00,0x7F,0xF0,0x06,0x7C,0x93,0x98,0x97,0x7F, +0xFF,0xFF,0xF5,0xFF,0xFF,0xFF,0xD0,0x00,0x7F,0xFE, +0x80,0x03,0xFF,0xF4,0x00,0x1F,0xFF,0xA0,0x00,0xFF, +0xFD,0x00,0x07,0xFF,0xE8,0x00,0x3F,0xFF,0x40,0x01, +0xFF,0xFA,0x00,0x0F,0xFF,0xD0,0x00,0x7F,0xFE,0x80, +0x03,0xFF,0xF4,0x00,0x1F,0xFF,0xA0,0x00,0xFF,0xFD, +0x00,0x07,0xFF,0xE8,0x00,0x3F,0xFC,0x00,0x0F,0xFF, +0xDF,0xFF,0xFF,0xFD,0x7F,0xFF,0xFF,0xC0,0x0D,0x59, +0x90,0xB8,0xF6,0x00,0x00,0x01,0xFF,0xC0,0x00,0x01, +0x20,0x00,0x01,0xFF,0xF0,0x00,0x00,0x80,0x00,0x01, +0xFF,0xFC,0x00,0x00,0x40,0x00,0x01,0xFF,0xFF,0x00, +0x00,0x24,0x00,0x01,0xFF,0xFF,0xC0,0x00,0x10,0x00, +0x01,0xFF,0xBF,0xF0,0x00,0x00,0x00,0x0F,0xFE,0xFF, +0xE0,0x00,0x00,0x00,0x3F,0xF1,0xFF,0x80,0x00,0x00, +0x01,0xFF,0xC7,0xFF,0x00,0x02,0x00,0x00,0xFF,0xC1, +0xFF,0x80,0x00,0x00,0x07,0xFF,0x07,0xFF,0x00,0x00, +0x00,0x1F,0xF8,0x0F,0xFC,0x00,0x00,0x00,0xFF,0xE0, +0x3F,0xF8,0x00,0x00,0x03,0xFF,0x00,0x7F,0xE0,0x01, +0x00,0x03,0xFF,0x80,0x3F,0xF8,0x00,0x00,0x0F,0xFC, +0x00,0x7F,0xF0,0x02,0x00,0x0F,0xFE,0x00,0x3F,0xF8, +0x01,0x00,0x0F,0xFE,0x00,0x0F,0xFE,0x00,0x80,0x0F, +0xFE,0x00,0x03,0xFF,0x80,0x00,0x7F,0xF8,0x00,0x0F, +0xFF,0x01,0x00,0x3F,0xF8,0x00,0x03,0xFF,0x80,0x80, +0x3F,0xF8,0x00,0x00,0xFF,0xE0,0x01,0xFF,0xE0,0x00, +0x03,0xFF,0xC0,0x07,0xFF,0x00,0x00,0x07,0xFF,0x04, +0x07,0xFF,0x80,0x00,0x03,0xFF,0xC0,0x1F,0xFC,0x00, +0x00,0x07,0xFF,0x00,0xFF,0xF0,0x00,0x00,0x1F,0xFE, +0x03,0xFF,0x80,0x00,0x00,0x3F,0xF8,0x83,0xFF,0xC0, +0x00,0x00,0x1F,0xFE,0x43,0xFF,0xC0,0x00,0x00,0x07, +0xFF,0x8F,0xFE,0x00,0x00,0x00,0x0F,0xFE,0x8F,0xFF, +0x00,0x00,0x00,0x07,0xFF,0x80,0x13,0x44,0x7B,0x99, +0x2B,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xF8,0x06,0x09,0x19,0x34,0xB1,0xFF,0xFC,0x00,0x7F, +0xFF,0x00,0x1F,0xFF,0x80,0x07,0xFF,0xE0,0x01,0xFF, +0xF0,0x10,0x0F,0xFF,0x80,0x03,0xFF,0xE0,0x00,0xFF, +0xF0,0x00,0x3F,0xFC,0x00,0x0F,0xFE,0x10,0x00,0x7F, +0xF0,0x00,0x1F,0xFC,0x00,0x07,0xFE,0x00,0x01,0xFF, +0x80,0x00,0x7F,0xC0,0x00,0x1F,0xF0,0x10,0x23,0x97, +0xFD,0x28,0x00,0x00,0x00,0x7F,0xFF,0x00,0x00,0x00, +0x00,0x00,0x0F,0xFF,0xFF,0xFC,0x00,0x00,0x00,0x00, +0x3F,0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x00,0x7F,0xFF, +0xFF,0xFF,0xF8,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF, +0xFE,0x00,0x00,0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xC0, +0x00,0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x01, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x01,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0x00,0x01,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0x80,0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xE0,0x00,0xFF,0xFF,0xE0,0x01,0xFF,0xFF,0xF0,0x00, +0xFF,0xFF,0x80,0x00,0x1F,0xFF,0xFC,0x00,0xFF,0xFF, +0x00,0x00,0x03,0xFF,0xFE,0x00,0x7F,0xFF,0x00,0x00, +0x00,0x7F,0xFF,0x00,0x3F,0xFF,0x00,0x00,0x00,0x1F, +0xFF,0x80,0x3F,0xFF,0x00,0x00,0x00,0x07,0xFF,0xE1, +0x03,0xFF,0xE0,0x00,0x00,0x00,0x7F,0xFE,0x10,0x7F, +0xFC,0x00,0x00,0x00,0x03,0xFF,0xE0,0x07,0xFC,0x00, +0x00,0x00,0x01,0xFF,0xF0,0x00,0x0E,0x00,0x00,0x00, +0x00,0xFF,0xF8,0x48,0x00,0x00,0x00,0x00,0x00,0x0F, +0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xC0, +0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0xE0,0x00,0x00, +0x00,0x00,0x07,0xFF,0xFF,0xF0,0x00,0x00,0x00,0x00, +0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x00,0x7F,0xFF,0xFF, +0xFF,0xFC,0x00,0x00,0x0F,0xFF,0xFF,0xFF,0xFF,0xFE, +0x00,0x00,0x3F,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00, +0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xC0,0x01,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xE0,0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xF0,0x01,0xFF,0xFF,0xFF,0xFF,0xFE,0xFF,0xF8,0x01, +0xFF,0xFF,0xFF,0xFF,0xF0,0x7F,0xFC,0x01,0xFF,0xFF, +0xFF,0xFF,0x00,0x3F,0xFE,0x01,0xFF,0xFF,0xFF,0xC0, +0x00,0x1F,0xFF,0x00,0xFF,0xFF,0xF0,0x00,0x00,0x0F, +0xFF,0x80,0xFF,0xFF,0x80,0x00,0x00,0x07,0xFF,0xC0, +0x7F,0xFF,0x00,0x00,0x00,0x03,0xFF,0xE0,0x7F,0xFE, +0x00,0x00,0x00,0x01,0xFF,0xF0,0x3F,0xFE,0x00,0x00, +0x00,0x00,0xFF,0xF8,0x1F,0xFE,0x00,0x00,0x00,0x00, +0xFF,0xFC,0x1F,0xFF,0x00,0x00,0x00,0x00,0x7F,0xFE, +0x0F,0xFF,0x00,0x00,0x00,0x00,0x3F,0xFF,0x08,0xFF, +0xF0,0x00,0x00,0x00,0x07,0xFF,0xF0,0x8F,0xFF,0x00, +0x00,0x00,0x00,0xFF,0xFF,0x07,0xFF,0x80,0x00,0x00, +0x00,0xFF,0xFF,0x83,0xFF,0xE0,0x00,0x00,0x00,0xFF, +0xFF,0xC1,0xFF,0xF8,0x00,0x00,0x01,0xFF,0xFF,0xE0, +0x7F,0xFC,0x00,0x00,0x01,0xFF,0xFF,0xF0,0x3F,0xFF, +0x80,0x00,0x03,0xFF,0xFF,0xF8,0x1F,0xFF,0xE0,0x00, +0x07,0xFF,0xFF,0xFE,0x07,0xFF,0xFE,0x00,0x3F,0xFF, +0xFF,0xFF,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0x80,0xFF,0xFF,0xFF,0xFF,0xFF,0xF7,0xFF,0xC0,0x7F, +0xFF,0xFF,0xFF,0xFF,0xF3,0xFF,0xE0,0x1F,0xFF,0xFF, +0xFF,0xFF,0xF0,0xFF,0xF0,0x07,0xFF,0xFF,0xFF,0xFF, +0xE0,0x7F,0xFC,0x01,0xFF,0xFF,0xFF,0xFF,0xE0,0x3F, +0xFE,0x00,0x7F,0xFF,0xFF,0xFF,0xC0,0x0F,0xFF,0x00, +0x0F,0xFF,0xFF,0xFF,0x80,0x07,0xFF,0xC0,0x03,0xFF, +0xFF,0xFF,0x00,0x01,0xFF,0xE0,0x00,0x3F,0xFF,0xFC, +0x00,0x00,0x7F,0xF8,0x00,0x01,0xFF,0xE0,0x00,0x00, +0x00,0x00,0x0F,0x30,0x27,0xFD,0x2B,0x7F,0xFC,0x00, +0x00,0x00,0x00,0x00,0x03,0x7F,0xFC,0x00,0x00,0x00, +0x00,0x00,0x03,0x7F,0xFC,0x00,0x00,0x00,0x00,0x00, +0x02,0xBF,0xFC,0x00,0x00,0x00,0x00,0x00,0x01,0xFF, +0xE0,0x00,0x7F,0xE0,0x00,0x00,0x0F,0xFF,0x00,0x1F, +0xFF,0xF0,0x00,0x00,0x7F,0xF8,0x03,0xFF,0xFF,0xF0, +0x00,0x03,0xFF,0xC0,0x7F,0xFF,0xFF,0xE0,0x00,0x1F, +0xFE,0x07,0xFF,0xFF,0xFF,0x80,0x00,0xFF,0xF0,0xFF, +0xFF,0xFF,0xFF,0x00,0x07,0xFF,0x8F,0xFF,0xFF,0xFF, +0xFC,0x00,0x3F,0xFC,0xFF,0xFF,0xFF,0xFF,0xF0,0x01, +0xFF,0xE7,0xFF,0xFF,0xFF,0xFF,0xC0,0x0F,0xFF,0x7F, +0xFF,0xFF,0xFF,0xFF,0x00,0x7F,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFC,0x03,0xFF,0xFF,0xFF,0x00,0xFF,0xFF,0xF0, +0x1F,0xFF,0xFF,0xC0,0x00,0xFF,0xFF,0x80,0xFF,0xFF, +0xFC,0x00,0x01,0xFF,0xFE,0x07,0xFF,0xFF,0x80,0x00, +0x07,0xFF,0xF0,0x3F,0xFF,0xF8,0x00,0x00,0x1F,0xFF, +0xC1,0xFF,0xFF,0x80,0x00,0x00,0x7F,0xFE,0x0F,0xFF, +0xF8,0x00,0x00,0x01,0xFF,0xF8,0x7F,0xFF,0x80,0x00, +0x00,0x07,0xFF,0xC3,0xFF,0xFC,0x00,0x00,0x00,0x1F, +0xFF,0x1F,0xFF,0xC0,0x00,0x00,0x00,0xFF,0xF8,0xFF, +0xFE,0x00,0x00,0x00,0x03,0xFF,0xC7,0xFF,0xE0,0x00, +0x00,0x00,0x1F,0xFE,0x3F,0xFF,0x00,0x00,0x00,0x00, +0xFF,0xFA,0xBF,0xFE,0x00,0x00,0x00,0x00,0x7F,0xF9, +0xFF,0xE0,0x00,0x00,0x00,0x03,0xFF,0xFB,0xFF,0xE0, +0x00,0x00,0x00,0x01,0xFF,0xF9,0xFF,0xE0,0x00,0x00, +0x00,0x01,0xFF,0xEF,0xFF,0x00,0x00,0x00,0x00,0x1F, +0xFE,0xAF,0xFF,0x80,0x00,0x00,0x00,0x1F,0xFE,0x7F, +0xFC,0x00,0x00,0x00,0x01,0xFF,0xF3,0xFF,0xF0,0x00, +0x00,0x00,0x0F,0xFF,0x1F,0xFF,0x80,0x00,0x00,0x00, +0xFF,0xF8,0xFF,0xFE,0x00,0x00,0x00,0x07,0xFF,0xC7, +0xFF,0xF0,0x00,0x00,0x00,0x7F,0xFC,0x3F,0xFF,0xC0, +0x00,0x00,0x03,0xFF,0xE1,0xFF,0xFF,0x00,0x00,0x00, +0x3F,0xFF,0x0F,0xFF,0xF8,0x00,0x00,0x03,0xFF,0xF0, +0x7F,0xFF,0xE0,0x00,0x00,0x3F,0xFF,0x83,0xFF,0xFF, +0x80,0x00,0x03,0xFF,0xF8,0x1F,0xFF,0xFF,0x00,0x00, +0x7F,0xFF,0x80,0xFF,0xFF,0xFE,0x00,0x07,0xFF,0xFC, +0x07,0xFF,0xFF,0xFE,0x01,0xFF,0xFF,0xC0,0x3F,0xFD, +0xFF,0xFF,0xFF,0xFF,0xFC,0x01,0xFF,0xEF,0xFF,0xFF, +0xFF,0xFF,0xC0,0x0F,0xFF,0x3F,0xFF,0xFF,0xFF,0xFC, +0x00,0x7F,0xF8,0xFF,0xFF,0xFF,0xFF,0xC0,0x03,0xFF, +0xC3,0xFF,0xFF,0xFF,0xFC,0x00,0x1F,0xFE,0x0F,0xFF, +0xFF,0xFF,0xC0,0x00,0xFF,0xF0,0x3F,0xFF,0xFF,0xFC, +0x00,0x07,0xFF,0x80,0xFF,0xFF,0xFF,0x80,0x00,0x3F, +0xFC,0x01,0xFF,0xFF,0xF0,0x00,0x01,0xFF,0xE0,0x03, +0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0x00, +0x00,0x00,0x0F,0x63,0x97,0xFD,0x0C,0x00,0x00,0x00, +0x7F,0xF8,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xFE, +0x00,0x00,0x00,0x00,0x07,0xFF,0xFF,0xFF,0x00,0x00, +0x00,0x00,0x7F,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x07, +0xFF,0xFF,0xFF,0xFE,0x00,0x00,0x00,0x3F,0xFF,0xFF, +0xFF,0xFE,0x00,0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xFC, +0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x00, +0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x07,0xFF,0xFF, +0xFF,0xFF,0xFF,0xE0,0x00,0x3F,0xFF,0xFF,0xFF,0xFF, +0xFF,0xC0,0x00,0xFF,0xFF,0xF0,0x07,0xFF,0xFF,0x00, +0x07,0xFF,0xFE,0x00,0x03,0xFF,0xFE,0x00,0x3F,0xFF, +0xE0,0x00,0x03,0xFF,0xF8,0x00,0xFF,0xFE,0x00,0x00, +0x07,0xFF,0xF0,0x07,0xFF,0xF0,0x00,0x00,0x0F,0xFF, +0xC0,0x1F,0xFF,0x80,0x00,0x00,0x1F,0xFF,0x80,0xFF, +0xFC,0x00,0x00,0x00,0x3F,0xFE,0x03,0xFF,0xE0,0x00, +0x00,0x00,0xFF,0xF8,0x83,0xFF,0xE0,0x00,0x00,0x00, +0x3F,0xFE,0x0F,0xFF,0x00,0x00,0x00,0x00,0x7F,0xC0, +0x3F,0xFC,0x00,0x00,0x00,0x01,0xC0,0x01,0xFF,0xF0, +0x00,0x00,0x00,0x00,0x00,0x14,0xFF,0xF0,0x00,0x00, +0x00,0x00,0x00,0x0D,0xFF,0xF0,0x00,0x00,0x00,0x00, +0x00,0x06,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x01, +0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x08,0x7F,0xF8, +0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xE0,0x00,0x00, +0x00,0x01,0xC0,0x07,0xFF,0x80,0x00,0x00,0x00,0x07, +0xFC,0x43,0xFF,0xE0,0x00,0x00,0x00,0x07,0xFF,0xC7, +0xFF,0x80,0x00,0x00,0x00,0x1F,0xFE,0x83,0xFF,0xE0, +0x00,0x00,0x00,0x1F,0xFF,0x07,0xFF,0xC0,0x00,0x00, +0x00,0xFF,0xFC,0x1F,0xFF,0x80,0x00,0x00,0x03,0xFF, +0xE0,0x3F,0xFF,0x00,0x00,0x00,0x1F,0xFF,0x80,0xFF, +0xFE,0x00,0x00,0x00,0xFF,0xFC,0x01,0xFF,0xFC,0x00, +0x00,0x07,0xFF,0xF0,0x07,0xFF,0xF8,0x00,0x00,0x7F, +0xFF,0x80,0x0F,0xFF,0xF8,0x00,0x07,0xFF,0xFE,0x00, +0x1F,0xFF,0xFE,0x00,0xFF,0xFF,0xF0,0x00,0x7F,0xFF, +0xFF,0xFF,0xFF,0xFF,0x80,0x00,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFC,0x00,0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0, +0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x03, +0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x07,0xFF,0xFF, +0xFF,0xFF,0xC0,0x00,0x00,0x0F,0xFF,0xFF,0xFF,0xFE, +0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFF,0xE0,0x00,0x00, +0x00,0x0F,0xFF,0xFF,0xFE,0x00,0x00,0x00,0x00,0x07, +0xFF,0xFF,0xC0,0x00,0x00,0x00,0x00,0x01,0xFF,0xF0, +0x00,0x00,0x00,0x0F,0x30,0x17,0xFD,0x2B,0x40,0x00, +0x00,0x00,0x00,0x00,0x3F,0xFF,0x40,0x00,0x00,0x00, +0x00,0x00,0x3F,0xFF,0x40,0x00,0x00,0x00,0x00,0x00, +0x3F,0xFE,0x80,0x00,0x00,0x00,0x00,0x00,0x3F,0xFC, +0x00,0x00,0x01,0xFF,0x80,0x01,0xFF,0xE0,0x00,0x00, +0xFF,0xFF,0x80,0x0F,0xFF,0x00,0x00,0x3F,0xFF,0xFF, +0x00,0x7F,0xF8,0x00,0x07,0xFF,0xFF,0xFE,0x03,0xFF, +0xC0,0x00,0x7F,0xFF,0xFF,0xF8,0x1F,0xFE,0x00,0x0F, +0xFF,0xFF,0xFF,0xE0,0xFF,0xF0,0x00,0xFF,0xFF,0xFF, +0xFF,0xC7,0xFF,0x80,0x0F,0xFF,0xFF,0xFF,0xFE,0x3F, +0xFC,0x00,0xFF,0xFF,0xFF,0xFF,0xF9,0xFF,0xE0,0x0F, +0xFF,0xFF,0xFF,0xFF,0xEF,0xFF,0x00,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xF8,0x0F,0xFF,0xFF,0x00,0xFF,0xFF, +0xFF,0xC0,0x7F,0xFF,0xC0,0x00,0xFF,0xFF,0xFE,0x07, +0xFF,0xF8,0x00,0x03,0xFF,0xFF,0xF0,0x3F,0xFF,0x80, +0x00,0x07,0xFF,0xFF,0x83,0xFF,0xF0,0x00,0x00,0x1F, +0xFF,0xFC,0x1F,0xFF,0x00,0x00,0x00,0x7F,0xFF,0xE1, +0xFF,0xF8,0x00,0x00,0x01,0xFF,0xFF,0x0F,0xFF,0x80, +0x00,0x00,0x07,0xFF,0xF8,0x7F,0xF8,0x00,0x00,0x00, +0x3F,0xFF,0xC7,0xFF,0xC0,0x00,0x00,0x00,0xFF,0xFE, +0x3F,0xFC,0x00,0x00,0x00,0x07,0xFF,0xF1,0xFF,0xE0, +0x00,0x00,0x00,0x1F,0xFF,0x9F,0xFF,0x00,0x00,0x00, +0x00,0xFF,0xFC,0xFF,0xF0,0x00,0x00,0x00,0x07,0xFF, +0xF2,0xFF,0xF0,0x00,0x00,0x00,0x03,0xFF,0xEF,0xFF, +0x00,0x00,0x00,0x00,0x1F,0xFF,0xDF,0xFF,0x00,0x00, +0x00,0x00,0x0F,0xFF,0xDF,0xFF,0x00,0x00,0x00,0x00, +0x0F,0xFF,0xA7,0xFF,0x80,0x00,0x00,0x00,0x1F,0xFF, +0x3F,0xFE,0x00,0x00,0x00,0x01,0xFF,0xF8,0xFF,0xF0, +0x00,0x00,0x00,0x0F,0xFF,0xC7,0xFF,0xC0,0x00,0x00, +0x00,0x7F,0xFE,0x3F,0xFE,0x00,0x00,0x00,0x07,0xFF, +0xF0,0xFF,0xF8,0x00,0x00,0x00,0x3F,0xFF,0x87,0xFF, +0xC0,0x00,0x00,0x03,0xFF,0xFC,0x3F,0xFF,0x00,0x00, +0x00,0x3F,0xFF,0xE0,0xFF,0xFC,0x00,0x00,0x03,0xFF, +0xFF,0x07,0xFF,0xF0,0x00,0x00,0x1F,0xFF,0xF8,0x1F, +0xFF,0xC0,0x00,0x03,0xFF,0xFF,0xC0,0x7F,0xFF,0x00, +0x00,0x3F,0xFF,0xFE,0x03,0xFF,0xFE,0x00,0x07,0xFF, +0xFF,0xF0,0x0F,0xFF,0xFE,0x01,0xFF,0xFF,0xFF,0xC0, +0x07,0xFF,0xFF,0xFF,0xFF,0xF7,0xFF,0x80,0x1F,0xFF, +0xFF,0xFF,0xFF,0x3F,0xFC,0x00,0x7F,0xFF,0xFF,0xFF, +0xF1,0xFF,0xE0,0x01,0xFF,0xFF,0xFF,0xFF,0x0F,0xFF, +0x00,0x03,0xFF,0xFF,0xFF,0xF0,0x7F,0xF8,0x00,0x0F, +0xFF,0xFF,0xFF,0x03,0xFF,0xC0,0x00,0x1F,0xFF,0xFF, +0xF0,0x1F,0xFE,0x00,0x00,0x3F,0xFF,0xFE,0x00,0xFF, +0xF0,0x00,0x00,0x7F,0xFF,0xC0,0x07,0xFF,0x80,0x00, +0x00,0x3F,0xF0,0x00,0x00,0x00,0x10,0x23,0x97,0xFD, +0x28,0x00,0x00,0x00,0x7F,0xF8,0x00,0x00,0x00,0x00, +0x00,0x03,0xFF,0xFF,0xE0,0x00,0x00,0x00,0x00,0x0F, +0xFF,0xFF,0xFE,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF, +0xFF,0xC0,0x00,0x00,0x00,0x3F,0xFF,0xFF,0xFF,0xF0, +0x00,0x00,0x00,0x3F,0xFF,0xFF,0xFF,0xFE,0x00,0x00, +0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x00,0x7F, +0xFF,0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x7F,0xFF,0xFF, +0xFF,0xFF,0xF8,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFF, +0xFE,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0x80, +0x00,0x7F,0xFF,0xF8,0x01,0xFF,0xFF,0xE0,0x00,0x7F, +0xFF,0xC0,0x00,0x0F,0xFF,0xF8,0x00,0x3F,0xFF,0x80, +0x00,0x01,0xFF,0xFE,0x00,0x3F,0xFF,0x80,0x00,0x00, +0x3F,0xFF,0x00,0x1F,0xFF,0x00,0x00,0x00,0x0F,0xFF, +0xC0,0x1F,0xFF,0x00,0x00,0x00,0x03,0xFF,0xE0,0x0F, +0xFF,0x00,0x00,0x00,0x00,0xFF,0xF8,0x0F,0xFF,0x00, +0x00,0x00,0x00,0x3F,0xFC,0x07,0xFF,0x00,0x00,0x00, +0x00,0x0F,0xFF,0x07,0xFF,0x80,0x00,0x00,0x00,0x07, +0xFF,0x90,0x7F,0xF0,0x00,0x00,0x00,0x00,0x3F,0xF8, +0x7F,0xF8,0x00,0x00,0x00,0x00,0x1F,0xFE,0x97,0xFF, +0x00,0x00,0x00,0x00,0x00,0xFF,0xE3,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xF6,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xCF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFD,0x7F,0xF8,0x00,0x00,0x00,0x00,0x00,0x00, +0x3F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x25,0xFF, +0xE0,0x00,0x00,0x00,0x00,0x00,0x02,0x1F,0xFF,0x00, +0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0x80,0x00,0x00, +0x00,0x01,0xC0,0x03,0xFF,0xE0,0x00,0x00,0x00,0x01, +0xFF,0x81,0xFF,0xF0,0x00,0x00,0x00,0x00,0xFF,0xF0, +0xFF,0xFC,0x00,0x00,0x00,0x00,0xFF,0xF8,0x3F,0xFF, +0x00,0x00,0x00,0x00,0xFF,0xFC,0x1F,0xFF,0xC0,0x00, +0x00,0x00,0x7F,0xFC,0x07,0xFF,0xF0,0x00,0x00,0x00, +0x7F,0xFE,0x03,0xFF,0xFC,0x00,0x00,0x00,0x7F,0xFE, +0x00,0xFF,0xFF,0x00,0x00,0x00,0xFF,0xFF,0x00,0x7F, +0xFF,0xE0,0x00,0x00,0xFF,0xFF,0x00,0x1F,0xFF,0xFC, +0x00,0x01,0xFF,0xFF,0x80,0x07,0xFF,0xFF,0xC0,0x0F, +0xFF,0xFF,0x80,0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0x80,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x00, +0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0xC0,0x00,0x07,0xFF, +0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x01,0xFF,0xFF,0xFF, +0xFF,0xFF,0x80,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFF, +0x80,0x00,0x00,0x0F,0xFF,0xFF,0xFF,0xFF,0x00,0x00, +0x00,0x01,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00, +0x3F,0xFF,0xFF,0xFC,0x00,0x00,0x00,0x00,0x03,0xFF, +0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0x80, +0x00,0x00,0x00,0x0A,0x30,0x08,0x00,0x94,0x00,0x00, +0x03,0xFF,0xE0,0x00,0x00,0x1F,0xFF,0xFF,0x00,0x00, +0x3F,0xFF,0xFF,0x80,0x00,0x3F,0xFF,0xFF,0xC0,0x00, +0x3F,0xFF,0xFF,0xC0,0x00,0x3F,0xFF,0xFF,0xE0,0x00, +0x3F,0xFF,0xFF,0xF0,0x00,0x3F,0xFF,0xFF,0xFA,0x00, +0x07,0xFF,0xFF,0xFF,0x80,0x03,0xFF,0xFF,0xFF,0x80, +0x03,0xFF,0xFE,0x00,0x40,0x01,0xFF,0xFC,0x00,0x04, +0x00,0x1F,0xFF,0x00,0x00,0x68,0x01,0xFF,0xE0,0x00, +0x05,0x80,0x1F,0xFE,0x00,0x00,0x6F,0xFF,0xFF,0xFF, +0xFF,0x05,0x7F,0xFF,0xFF,0xFF,0xF0,0x68,0x01,0xFF, +0xE0,0x00,0x06,0x80,0x1F,0xFE,0x00,0x00,0x68,0x01, +0xFF,0xE0,0x00,0x06,0x80,0x1F,0xFE,0x00,0x00,0x68, +0x01,0xFF,0xE0,0x00,0x06,0x80,0x1F,0xFE,0x00,0x00, +0x68,0x01,0xFF,0xE0,0x00,0x06,0x80,0x1F,0xFE,0x00, +0x00,0x40,0x01,0xFF,0xE0,0x00,0x00,0x0F,0x30,0x97, +0x95,0x28,0x00,0x00,0x03,0xFF,0x00,0x00,0x00,0x00, +0x00,0x01,0xFF,0xFF,0x80,0x0F,0xFF,0x00,0x00,0x7F, +0xFF,0xFF,0x00,0x7F,0xF8,0x00,0x07,0xFF,0xFF,0xFE, +0x03,0xFF,0xC0,0x00,0xFF,0xFF,0xFF,0xF8,0x1F,0xFE, +0x00,0x0F,0xFF,0xFF,0xFF,0xE0,0xFF,0xF0,0x01,0xFF, +0xFF,0xFF,0xFF,0x87,0xFF,0x80,0x1F,0xFF,0xFF,0xFF, +0xFE,0x3F,0xFC,0x01,0xFF,0xFF,0xFF,0xFF,0xF9,0xFF, +0xE0,0x0F,0xFF,0xFF,0xFF,0xFF,0xEF,0xFF,0x00,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xF8,0x0F,0xFF,0xFE,0x01, +0xFF,0xFF,0xFF,0xC0,0xFF,0xFF,0xC0,0x01,0xFF,0xFF, +0xFE,0x07,0xFF,0xF8,0x00,0x03,0xFF,0xFF,0xF0,0x7F, +0xFF,0x00,0x00,0x07,0xFF,0xFF,0x83,0xFF,0xF0,0x00, +0x00,0x1F,0xFF,0xFC,0x3F,0xFF,0x00,0x00,0x00,0x7F, +0xFF,0xF0,0x3F,0xFE,0x00,0x00,0x00,0x3F,0xFF,0xE3, +0xFF,0xE0,0x00,0x00,0x00,0xFF,0xFF,0x83,0xFF,0xC0, +0x00,0x00,0x00,0x7F,0xFF,0x3F,0xFE,0x00,0x00,0x00, +0x01,0xFF,0xFC,0x3F,0xFC,0x00,0x00,0x00,0x01,0xFF, +0xF9,0xFF,0xE0,0x00,0x00,0x00,0x07,0xFF,0xF3,0xFF, +0xC0,0x00,0x00,0x00,0x07,0xFF,0xF3,0xFF,0xC0,0x00, +0x00,0x00,0x03,0xFF,0xF3,0xFF,0xC0,0x00,0x00,0x00, +0x07,0xFF,0xDF,0xFF,0x00,0x00,0x00,0x00,0x3F,0xFF, +0x2F,0xFF,0x00,0x00,0x00,0x00,0x7F,0xFE,0x7F,0xFC, +0x00,0x00,0x00,0x07,0xFF,0xF1,0xFF,0xE0,0x00,0x00, +0x00,0x3F,0xFF,0x8F,0xFF,0x80,0x00,0x00,0x03,0xFF, +0xFC,0x3F,0xFC,0x00,0x00,0x00,0x1F,0xFF,0xE1,0xFF, +0xF0,0x00,0x00,0x01,0xFF,0xFF,0x0F,0xFF,0xC0,0x00, +0x00,0x1F,0xFF,0xF8,0x3F,0xFF,0x00,0x00,0x01,0xFF, +0xFF,0xC1,0xFF,0xFC,0x00,0x00,0x1F,0xFF,0xFE,0x07, +0xFF,0xF8,0x00,0x01,0xFF,0xFF,0xF0,0x1F,0xFF,0xE0, +0x00,0x3F,0xFF,0xFF,0x80,0xFF,0xFF,0xE0,0x0F,0xFF, +0xFF,0xFC,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xE0, +0x0F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x3F,0xFF, +0xFF,0xFF,0xFF,0x7F,0xF8,0x00,0xFF,0xFF,0xFF,0xFF, +0xF3,0xFF,0xC0,0x03,0xFF,0xFF,0xFF,0xFF,0x1F,0xFE, +0x00,0x0F,0xFF,0xFF,0xFF,0xF0,0xFF,0xF0,0x00,0x3F, +0xFF,0xFF,0xFF,0x07,0xFF,0x00,0x00,0x7F,0xFF,0xFF, +0xE0,0x3F,0xF8,0x00,0x00,0xFF,0xFF,0xFE,0x01,0xFF, +0xC0,0x00,0x01,0xFF,0xFF,0x80,0x1F,0xFE,0x00,0x00, +0x00,0xFF,0xE0,0x00,0xFF,0xF5,0x00,0x00,0x00,0x00, +0x00,0x00,0xFF,0xF0,0xE0,0x00,0x00,0x00,0x00,0x07, +0xFF,0x87,0xFC,0x00,0x00,0x00,0x00,0x3F,0xF9,0x07, +0xFF,0x80,0x00,0x00,0x00,0x7F,0xF8,0x3F,0xFC,0x00, +0x00,0x00,0x07,0xFF,0xC1,0xFF,0xF0,0x00,0x00,0x00, +0x3F,0xFE,0x0F,0xFF,0x80,0x00,0x00,0x03,0xFF,0xE0, +0x7F,0xFE,0x00,0x00,0x00,0x3F,0xFF,0x01,0xFF,0xF8, +0x00,0x00,0x03,0xFF,0xF0,0x0F,0xFF,0xE0,0x00,0x00, +0x7F,0xFF,0x80,0x7F,0xFF,0xC0,0x00,0x0F,0xFF,0xF8, +0x01,0xFF,0xFF,0xC0,0x03,0xFF,0xFF,0xC0,0x07,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x3F,0xFF,0xFF,0xFF, +0xFF,0xFF,0xC0,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFC, +0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xC0,0x00,0x0F, +0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x3F,0xFF,0xFF, +0xFF,0xFF,0xC0,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xF8, +0x00,0x00,0x01,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00, +0x01,0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x00,0x03,0xFF, +0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0xFF,0xFC,0x00, +0x00,0x00,0x0E,0x2F,0xA4,0x01,0x2B,0x7F,0xFC,0x00, +0x00,0x00,0x00,0x00,0x37,0xFF,0xC0,0x00,0x00,0x00, +0x00,0x03,0x7F,0xFC,0x00,0x00,0x00,0x00,0x00,0x2B, +0xFF,0xC0,0x00,0x00,0x00,0x00,0x01,0xFF,0xE0,0x00, +0x3F,0xF8,0x00,0x00,0xFF,0xF0,0x00,0xFF,0xFF,0xC0, +0x00,0x7F,0xF8,0x03,0xFF,0xFF,0xFC,0x00,0x3F,0xFC, +0x03,0xFF,0xFF,0xFF,0x00,0x1F,0xFE,0x07,0xFF,0xFF, +0xFF,0xE0,0x0F,0xFF,0x07,0xFF,0xFF,0xFF,0xF8,0x07, +0xFF,0x87,0xFF,0xFF,0xFF,0xFE,0x03,0xFF,0xC7,0xFF, +0xFF,0xFF,0xFF,0x81,0xFF,0xE7,0xFF,0xFF,0xFF,0xFF, +0xE0,0xFF,0xF7,0xFF,0xFF,0xFF,0xFF,0xF8,0x7F,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFC,0x3F,0xFF,0xFF,0xF0,0x0F, +0xFF,0xFF,0x1F,0xFF,0xFF,0xC0,0x00,0xFF,0xFF,0x8F, +0xFF,0xFF,0x80,0x00,0x1F,0xFF,0xC7,0xFF,0xFF,0x00, +0x00,0x07,0xFF,0xF3,0xFF,0xFF,0x00,0x00,0x01,0xFF, +0xF9,0xFF,0xFF,0x00,0x00,0x00,0xFF,0xFC,0xFF,0xFF, +0x00,0x00,0x00,0x3F,0xFE,0x7F,0xFF,0x00,0x00,0x00, +0x0F,0xFF,0x4F,0xFF,0xE0,0x00,0x00,0x00,0xFF,0xFD, +0x7F,0xFC,0x00,0x00,0x00,0x07,0xFF,0xEF,0xFF,0x80, +0x00,0x00,0x00,0x7F,0xFE,0xFF,0xF8,0x00,0x00,0x00, +0x07,0xFF,0xEF,0xFF,0x80,0x00,0x00,0x00,0x7F,0xFE, +0xFF,0xF8,0x00,0x00,0x00,0x07,0xFF,0xEF,0xFF,0x80, +0x00,0x00,0x00,0x7F,0xFE,0xFF,0xF8,0x00,0x00,0x00, +0x07,0xFF,0xC7,0xFF,0x80,0x00,0x00,0x00,0x7F,0xF8, +0x03,0x2F,0xA4,0x00,0x7B,0x7F,0xFE,0xFF,0xFF,0x40, +0x03,0x40,0x03,0x7F,0xFF,0x7F,0xFF,0x7F,0xFF,0x7F, +0xFF,0x7F,0xFF,0x7F,0xFF,0x7F,0xFF,0x7F,0xFF,0x7F, +0xFF,0x3F,0xFC,0x06,0xFD,0x6B,0x94,0x7B,0x40,0x00, +0x7F,0xFD,0x80,0x00,0xFF,0xFD,0x00,0x00,0x00,0x1A, +0x00,0x00,0x00,0x34,0x00,0x07,0xFF,0xE8,0x00,0x0F, +0xFF,0xD0,0x00,0x1F,0xFF,0xA0,0x00,0x3F,0xFF,0x40, +0x00,0x7F,0xFE,0x80,0x00,0xFF,0xFD,0x00,0x01,0xFF, +0xFA,0x00,0x03,0xFF,0xF4,0x00,0x07,0xFF,0xE8,0x00, +0x0F,0xFF,0xC0,0x00,0x1F,0xFF,0x00,0x00,0x7F,0xFE, +0x80,0x00,0xFF,0xF0,0x00,0x1F,0xFF,0x00,0x03,0xFF, +0xF0,0xC0,0x7F,0xFE,0x41,0xFF,0xFF,0xFC,0x87,0xFF, +0xFF,0xF1,0x0F,0xFF,0xFF,0xC0,0xFF,0xFF,0xF8,0x1F, +0xFF,0xFF,0x01,0xFF,0xFF,0xC0,0x1F,0xFF,0xF0,0x00, +0x3F,0xF8,0x00,0x00,0x0E,0x6F,0xA4,0x01,0x0F,0x7F, +0xFC,0x00,0x00,0x00,0x00,0x00,0x1B,0xFF,0xE0,0x00, +0x00,0x00,0x00,0x00,0xDF,0xFF,0x00,0x00,0x00,0x00, +0x00,0x05,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x1F, +0xFE,0x00,0x00,0x00,0x7F,0xFF,0x87,0xFF,0x80,0x00, +0x00,0x7F,0xFF,0xC1,0xFF,0xE0,0x00,0x00,0x3F,0xFF, +0xE0,0x7F,0xF8,0x00,0x00,0x1F,0xFF,0xF0,0x1F,0xFE, +0x00,0x00,0x0F,0xFF,0xF8,0x07,0xFF,0x80,0x00,0x07, +0xFF,0xFC,0x01,0xFF,0xE0,0x00,0x03,0xFF,0xFE,0x00, +0x7F,0xF8,0x00,0x01,0xFF,0xFF,0x00,0x1F,0xFE,0x00, +0x00,0xFF,0xFF,0x80,0x07,0xFF,0x80,0x00,0x7F,0xFF, +0xC0,0x01,0xFF,0xE0,0x00,0x3F,0xFF,0xE0,0x00,0x7F, +0xF8,0x00,0x1F,0xFF,0xF0,0x00,0x1F,0xFE,0x00,0x0F, +0xFF,0xF8,0x00,0x07,0xFF,0x80,0x07,0xFF,0xFC,0x00, +0x01,0xFF,0xE0,0x03,0xFF,0xFE,0x00,0x00,0x7F,0xF8, +0x01,0xFF,0xFF,0x00,0x00,0x1F,0xFE,0x00,0xFF,0xFF, +0x80,0x00,0x07,0xFF,0x80,0x7F,0xFF,0xC0,0x00,0x01, +0xFF,0xE0,0x3F,0xFF,0xE0,0x00,0x00,0x7F,0xF8,0x1F, +0xFF,0xF0,0x00,0x00,0x1F,0xFE,0x0F,0xFF,0xF8,0x00, +0x00,0x07,0xFF,0x87,0xFF,0xFC,0x00,0x00,0x01,0xFF, +0xE3,0xFF,0xFE,0x00,0x00,0x00,0x7F,0xFB,0xFF,0xFE, +0x00,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0x00,0x00,0x00, +0x07,0xFF,0xFF,0xFF,0x80,0x00,0x00,0x02,0x3F,0xFF, +0xFF,0xFE,0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFF,0xC0, +0x00,0x00,0x04,0x7F,0xFF,0xFF,0xFF,0x00,0x00,0x00, +0x1F,0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x08,0xFF,0xFF, +0xFF,0xFF,0x80,0x00,0x00,0x3F,0xFF,0xFB,0xFF,0xF0, +0x00,0x00,0x0F,0xFF,0xFC,0xFF,0xFE,0x00,0x00,0x03, +0xFF,0xFE,0x1F,0xFF,0x80,0x00,0x00,0xFF,0xFF,0x03, +0xFF,0xF0,0x00,0x00,0x3F,0xFF,0x80,0xFF,0xFE,0x00, +0x00,0x0F,0xFF,0xC0,0x1F,0xFF,0x80,0x00,0x03,0xFF, +0xE0,0x03,0xFF,0xF0,0x00,0x00,0xFF,0xF0,0x00,0xFF, +0xFE,0x00,0x00,0x3F,0xFC,0x00,0x1F,0xFF,0x80,0x00, +0x0F,0xFF,0x00,0x03,0xFF,0xF0,0x00,0x03,0xFF,0xC0, +0x00,0xFF,0xFE,0x00,0x00,0xFF,0xF0,0x00,0x1F,0xFF, +0x80,0x00,0x3F,0xFC,0x00,0x03,0xFF,0xF0,0x00,0x0F, +0xFF,0x00,0x00,0xFF,0xFE,0x00,0x03,0xFF,0xC0,0x00, +0x1F,0xFF,0x80,0x00,0xFF,0xF0,0x00,0x03,0xFF,0xF0, +0x00,0x3F,0xFC,0x00,0x00,0xFF,0xFE,0x00,0x0F,0xFF, +0x00,0x00,0x1F,0xFF,0x80,0x03,0xFF,0xC0,0x00,0x03, +0xFF,0xF0,0x00,0xFF,0xF0,0x00,0x00,0xFF,0xFE,0x00, +0x3F,0xFC,0x00,0x00,0x1F,0xFF,0x80,0x0F,0xFF,0x00, +0x00,0x03,0xFF,0xF0,0x03,0xFF,0xC0,0x00,0x00,0xFF, +0xFE,0x00,0xFF,0xF0,0x00,0x00,0x1F,0xFF,0x80,0x3F, +0xFC,0x00,0x00,0x03,0xFF,0xF0,0x0F,0xFF,0x00,0x00, +0x00,0xFF,0xFE,0x03,0xFF,0xC0,0x00,0x00,0x1F,0xFF, +0x80,0xFF,0xF0,0x00,0x00,0x03,0xFF,0xF0,0x3F,0xFC, +0x00,0x00,0x00,0xFF,0xFE,0x0F,0xFF,0x00,0x00,0x00, +0x1F,0xFF,0x83,0xFF,0xC0,0x00,0x00,0x03,0xFF,0xF0, +0xFF,0xF0,0x00,0x00,0x00,0xFF,0xFE,0x3F,0xFC,0x00, +0x00,0x00,0x1F,0xFF,0x8F,0xFF,0x00,0x00,0x00,0x03, +0xFF,0xF3,0xFF,0xC0,0x00,0x00,0x00,0xFF,0xFE,0x03, +0x2F,0xA4,0x00,0x7B,0x7F,0xFF,0x7F,0xFF,0x7F,0xFF, +0x7F,0xFF,0x7F,0xFF,0x7F,0xFF,0x7F,0xFF,0x7F,0xFF, +0x7F,0xFF,0x7F,0xFF,0x7F,0xFF,0x7F,0xFF,0x7F,0xFE, +0xBF,0xFC,0x17,0xA3,0x24,0x01,0xC0,0x00,0x00,0x00, +0x3F,0xF0,0x00,0x00,0x00,0x3F,0xF8,0x00,0x03,0xFF, +0xC0,0x03,0xFF,0xFE,0x00,0x00,0x03,0xFF,0xFF,0x00, +0x07,0xFF,0x80,0x1F,0xFF,0xFF,0x00,0x00,0x1F,0xFF, +0xFF,0x80,0x0F,0xFF,0x00,0xFF,0xFF,0xFF,0x00,0x00, +0xFF,0xFF,0xFF,0xC0,0x1F,0xFE,0x07,0xFF,0xFF,0xFF, +0x80,0x07,0xFF,0xFF,0xFF,0xC0,0x3F,0xFC,0x1F,0xFF, +0xFF,0xFF,0x80,0x1F,0xFF,0xFF,0xFF,0xC0,0x7F,0xF8, +0x7F,0xFF,0xFF,0xFF,0x00,0x7F,0xFF,0xFF,0xFF,0xC0, +0xFF,0xF1,0xFF,0xFF,0xFF,0xFF,0x01,0xFF,0xFF,0xFF, +0xFF,0xC1,0xFF,0xE7,0xFF,0xFF,0xFF,0xFF,0x07,0xFF, +0xFF,0xFF,0xFF,0x83,0xFF,0xDF,0xFF,0xFF,0xFF,0xFE, +0x1F,0xFF,0xFF,0xFF,0xFF,0x87,0xFF,0xBF,0xFF,0xFF, +0xFF,0xFE,0x3F,0xFF,0xFF,0xFF,0xFF,0x0F,0xFF,0xFF, +0xF8,0x07,0xFF,0xFC,0xFF,0xF8,0x07,0xFF,0xFF,0x1F, +0xFF,0xFF,0x80,0x03,0xFF,0xFF,0xFF,0x80,0x01,0xFF, +0xFE,0x3F,0xFF,0xFC,0x00,0x01,0xFF,0xFF,0xFC,0x00, +0x01,0xFF,0xFE,0x7F,0xFF,0xE0,0x00,0x01,0xFF,0xFF, +0xF0,0x00,0x00,0xFF,0xFC,0xFF,0xFF,0x80,0x00,0x03, +0xFF,0xFF,0xC0,0x00,0x01,0xFF,0xF9,0xFF,0xFE,0x00, +0x00,0x03,0xFF,0xFF,0x00,0x00,0x01,0xFF,0xF3,0xFF, +0xF8,0x00,0x00,0x07,0xFF,0xFC,0x00,0x00,0x01,0xFF, +0xE7,0xFF,0xF0,0x00,0x00,0x07,0xFF,0xF0,0x00,0x00, +0x03,0xFF,0xCF,0xFF,0xC0,0x00,0x00,0x0F,0xFF,0xE0, +0x00,0x00,0x07,0xFF,0xDF,0xFF,0x80,0x00,0x00,0x1F, +0xFF,0x80,0x00,0x00,0x0F,0xFF,0xBF,0xFE,0x00,0x00, +0x00,0x3F,0xFF,0x00,0x00,0x00,0x1F,0xFF,0x8F,0xFF, +0x80,0x00,0x00,0x07,0xFF,0xC0,0x00,0x00,0x03,0xFF, +0xDF,0xFF,0x00,0x00,0x00,0x0F,0xFF,0x00,0x00,0x00, +0x07,0xFF,0xEF,0xFF,0x80,0x00,0x00,0x03,0xFF,0xC0, +0x00,0x00,0x01,0xFF,0xFB,0xFF,0xE0,0x00,0x00,0x00, +0xFF,0xF0,0x00,0x00,0x00,0x7F,0xFE,0xFF,0xF8,0x00, +0x00,0x00,0x3F,0xFC,0x00,0x00,0x00,0x1F,0xFF,0xBF, +0xFE,0x00,0x00,0x00,0x0F,0xFF,0x00,0x00,0x00,0x07, +0xFF,0xEF,0xFF,0x80,0x00,0x00,0x03,0xFF,0xC0,0x00, +0x00,0x01,0xFF,0xFB,0xFF,0xE0,0x00,0x00,0x00,0xFF, +0xF0,0x00,0x00,0x00,0x7F,0xFC,0xFF,0xF8,0x00,0x00, +0x00,0x3F,0xFC,0x00,0x00,0x00,0x1F,0xFE,0x0E,0x23, +0x24,0x01,0x28,0x00,0x00,0x00,0x1F,0xFC,0x00,0x00, +0xFF,0xF0,0x00,0xFF,0xFF,0xC0,0x00,0x7F,0xF8,0x03, +0xFF,0xFF,0xFC,0x00,0x3F,0xFC,0x03,0xFF,0xFF,0xFF, +0x80,0x1F,0xFE,0x07,0xFF,0xFF,0xFF,0xE0,0x0F,0xFF, +0x07,0xFF,0xFF,0xFF,0xFC,0x07,0xFF,0x87,0xFF,0xFF, +0xFF,0xFF,0x03,0xFF,0xC7,0xFF,0xFF,0xFF,0xFF,0x81, +0xFF,0xE7,0xFF,0xFF,0xFF,0xFF,0xE0,0xFF,0xF7,0xFF, +0xFF,0xFF,0xFF,0xF8,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFC,0x3F,0xFF,0xFF,0xF0,0x0F,0xFF,0xFF,0x1F,0xFF, +0xFF,0x80,0x00,0xFF,0xFF,0x8F,0xFF,0xFF,0x00,0x00, +0x1F,0xFF,0xE7,0xFF,0xFF,0x00,0x00,0x07,0xFF,0xF3, +0xFF,0xFE,0x00,0x00,0x01,0xFF,0xF9,0xFF,0xFE,0x00, +0x00,0x00,0x7F,0xFC,0xFF,0xFF,0x00,0x00,0x00,0x3F, +0xFF,0x7F,0xFF,0x00,0x00,0x00,0x0F,0xFF,0xCF,0xFF, +0xE0,0x00,0x00,0x00,0xFF,0xFD,0x7F,0xFC,0x00,0x00, +0x00,0x07,0xFF,0xEF,0xFF,0x80,0x00,0x00,0x00,0x7F, +0xFE,0xFF,0xF8,0x00,0x00,0x00,0x07,0xFF,0xEF,0xFF, +0x80,0x00,0x00,0x00,0x7F,0xFE,0xFF,0xF8,0x00,0x00, +0x00,0x07,0xFF,0xEF,0xFF,0x80,0x00,0x00,0x00,0x7F, +0xFE,0xFF,0xF8,0x00,0x00,0x00,0x07,0xFF,0xC7,0xFF, +0x80,0x00,0x00,0x00,0x7F,0xF8,0x10,0x23,0x97,0xFD, +0x28,0x00,0x00,0x00,0x7F,0xF8,0x00,0x00,0x00,0x00, +0x00,0x07,0xFF,0xFF,0xC0,0x00,0x00,0x00,0x00,0x0F, +0xFF,0xFF,0xFC,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF, +0xFF,0x80,0x00,0x00,0x00,0x3F,0xFF,0xFF,0xFF,0xF0, +0x00,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFE,0x00,0x00, +0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x00,0x7F, +0xFF,0xFF,0xFF,0xFF,0xE0,0x00,0x00,0xFF,0xFF,0xFF, +0xFF,0xFF,0xF8,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFE,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0x80, +0x00,0x7F,0xFF,0xF8,0x01,0xFF,0xFF,0xE0,0x00,0x7F, +0xFF,0xE0,0x00,0x1F,0xFF,0xF8,0x00,0x7F,0xFF,0xC0, +0x00,0x03,0xFF,0xFC,0x00,0x3F,0xFF,0xC0,0x00,0x00, +0xFF,0xFF,0x00,0x3F,0xFF,0x80,0x00,0x00,0x1F,0xFF, +0xC0,0x1F,0xFF,0x80,0x00,0x00,0x07,0xFF,0xE1,0x03, +0xFF,0xF0,0x00,0x00,0x00,0x3F,0xFF,0x03,0xFF,0xF0, +0x00,0x00,0x00,0x0F,0xFF,0xC8,0x3F,0xFE,0x00,0x00, +0x00,0x00,0x7F,0xFC,0x1F,0xFE,0x00,0x00,0x00,0x00, +0x1F,0xFE,0x43,0xFF,0xE0,0x00,0x00,0x00,0x01,0xFF, +0xF4,0x3F,0xFC,0x00,0x00,0x00,0x00,0x0F,0xFF,0x1F, +0xFE,0x00,0x00,0x00,0x00,0x07,0xFF,0xDF,0xFF,0x00, +0x00,0x00,0x00,0x03,0xFF,0xFB,0xFF,0xE0,0x00,0x00, +0x00,0x00,0x1F,0xFF,0x9F,0xFE,0x00,0x00,0x00,0x00, +0x01,0xFF,0xEF,0xFF,0x80,0x00,0x00,0x00,0x01,0xFF, +0xF9,0x7F,0xF8,0x00,0x00,0x00,0x00,0x1F,0xFE,0x3F, +0xFC,0x00,0x00,0x00,0x00,0x1F,0xFF,0x1F,0xFF,0x00, +0x00,0x00,0x00,0x0F,0xFF,0x87,0xFF,0x80,0x00,0x00, +0x00,0x07,0xFF,0xD0,0x7F,0xFC,0x00,0x00,0x00,0x00, +0xFF,0xF8,0x3F,0xFF,0x00,0x00,0x00,0x00,0xFF,0xFC, +0x81,0xFF,0xF8,0x00,0x00,0x00,0x1F,0xFF,0x80,0x7F, +0xFE,0x00,0x00,0x00,0x1F,0xFF,0x80,0x3F,0xFF,0x80, +0x00,0x00,0x1F,0xFF,0xC0,0x0F,0xFF,0xF0,0x00,0x00, +0x3F,0xFF,0xC0,0x07,0xFF,0xFC,0x00,0x00,0x3F,0xFF, +0xE0,0x01,0xFF,0xFF,0x80,0x00,0x7F,0xFF,0xE0,0x00, +0x7F,0xFF,0xF8,0x01,0xFF,0xFF,0xE0,0x20,0x03,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFC,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xFF, +0xF8,0x00,0x00,0x07,0xFF,0xFF,0xFF,0xFF,0xF8,0x00, +0x00,0x01,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x00, +0x3F,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x00,0x0F,0xFF, +0xFF,0xFF,0xE0,0x00,0x00,0x00,0x01,0xFF,0xFF,0xFF, +0xC0,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF,0x00,0x00, +0x00,0x00,0x00,0x00,0x7F,0xF8,0x00,0x00,0x00,0x0F, +0x30,0x27,0x99,0x28,0x00,0x00,0x00,0x3F,0xF0,0x00, +0x00,0x0F,0xFF,0x00,0x1F,0xFF,0xF8,0x00,0x00,0x7F, +0xF8,0x03,0xFF,0xFF,0xF0,0x00,0x03,0xFF,0xC0,0x3F, +0xFF,0xFF,0xE0,0x00,0x1F,0xFE,0x07,0xFF,0xFF,0xFF, +0xC0,0x00,0xFF,0xF0,0x7F,0xFF,0xFF,0xFF,0x00,0x07, +0xFF,0x87,0xFF,0xFF,0xFF,0xFC,0x00,0x3F,0xFC,0x7F, +0xFF,0xFF,0xFF,0xF0,0x01,0xFF,0xE3,0xFF,0xFF,0xFF, +0xFF,0xC0,0x0F,0xFF,0x3F,0xFF,0xFF,0xFF,0xFF,0x00, +0x7F,0xFB,0xFF,0xFF,0xFF,0xFF,0xFC,0x03,0xFF,0xFF, +0xFF,0x00,0xFF,0xFF,0xF0,0x1F,0xFF,0xFF,0xE0,0x00, +0xFF,0xFF,0x80,0xFF,0xFF,0xFC,0x00,0x01,0xFF,0xFE, +0x07,0xFF,0xFF,0xC0,0x00,0x07,0xFF,0xF0,0x3F,0xFF, +0xF8,0x00,0x00,0x1F,0xFF,0xC1,0xFF,0xFF,0x80,0x00, +0x00,0x7F,0xFE,0x0F,0xFF,0xF8,0x00,0x00,0x01,0xFF, +0xF8,0x7F,0xFF,0xC0,0x00,0x00,0x07,0xFF,0xC3,0xFF, +0xFC,0x00,0x00,0x00,0x3F,0xFE,0x1F,0xFF,0xC0,0x00, +0x00,0x00,0xFF,0xF8,0xFF,0xFE,0x00,0x00,0x00,0x03, +0xFF,0xC7,0xFF,0xE0,0x00,0x00,0x00,0x1F,0xFE,0x3F, +0xFF,0x00,0x00,0x00,0x00,0xFF,0xF9,0xFF,0xF8,0x00, +0x00,0x00,0x03,0xFF,0xD3,0xFF,0xF0,0x00,0x00,0x00, +0x03,0xFF,0xCF,0xFF,0x80,0x00,0x00,0x00,0x1F,0xFF, +0xDF,0xFF,0x00,0x00,0x00,0x00,0x0F,0xFF,0xCF,0xFF, +0x00,0x00,0x00,0x00,0x0F,0xFF,0x7F,0xF8,0x00,0x00, +0x00,0x00,0xFF,0xF5,0x7F,0xFC,0x00,0x00,0x00,0x00, +0xFF,0xF4,0x7F,0xFE,0x00,0x00,0x00,0x01,0xFF,0xE3, +0xFF,0xF0,0x00,0x00,0x00,0x1F,0xFF,0x1F,0xFF,0xC0, +0x00,0x00,0x00,0xFF,0xF8,0xFF,0xFE,0x00,0x00,0x00, +0x0F,0xFF,0x87,0xFF,0xF8,0x00,0x00,0x00,0x7F,0xFC, +0x3F,0xFF,0xE0,0x00,0x00,0x07,0xFF,0xC1,0xFF,0xFF, +0x00,0x00,0x00,0x7F,0xFE,0x0F,0xFF,0xFC,0x00,0x00, +0x07,0xFF,0xE0,0x7F,0xFF,0xF8,0x00,0x00,0x7F,0xFF, +0x03,0xFF,0xFF,0xE0,0x00,0x07,0xFF,0xF0,0x1F,0xFF, +0xFF,0xC0,0x00,0xFF,0xFF,0x80,0xFF,0xFF,0xFF,0xC0, +0x3F,0xFF,0xF8,0x07,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0x80,0x3F,0xFF,0xFF,0xFF,0xFF,0xFF,0xF8,0x01,0xFF, +0xEF,0xFF,0xFF,0xFF,0xFF,0x80,0x0F,0xFF,0x3F,0xFF, +0xFF,0xFF,0xF8,0x00,0x7F,0xF8,0xFF,0xFF,0xFF,0xFF, +0x80,0x03,0xFF,0xC3,0xFF,0xFF,0xFF,0xF8,0x00,0x1F, +0xFE,0x0F,0xFF,0xFF,0xFF,0x00,0x00,0xFF,0xF0,0x3F, +0xFF,0xFF,0xF0,0x00,0x07,0xFF,0x80,0x7F,0xFF,0xFE, +0x00,0x00,0x3F,0xFC,0x00,0xFF,0xFF,0x80,0x00,0x01, +0xFF,0xE0,0x00,0xFF,0xC0,0x00,0x00,0x1B,0xFF,0xE0, +0x00,0x00,0x00,0x00,0x00,0x1B,0xFF,0xE0,0x00,0x00, +0x00,0x00,0x00,0x1B,0xFF,0xE0,0x00,0x00,0x00,0x00, +0x00,0x15,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x00, +0x0F,0x30,0x17,0x99,0x28,0x00,0x00,0x03,0xFF,0x00, +0x00,0x00,0x00,0x00,0x01,0xFF,0xFF,0x00,0x0F,0xFF, +0x00,0x00,0x3F,0xFF,0xFE,0x00,0x7F,0xF8,0x00,0x07, +0xFF,0xFF,0xFC,0x03,0xFF,0xC0,0x00,0xFF,0xFF,0xFF, +0xF0,0x1F,0xFE,0x00,0x0F,0xFF,0xFF,0xFF,0xC0,0xFF, +0xF0,0x01,0xFF,0xFF,0xFF,0xFF,0x07,0xFF,0x80,0x1F, +0xFF,0xFF,0xFF,0xFC,0x3F,0xFC,0x01,0xFF,0xFF,0xFF, +0xFF,0xF1,0xFF,0xF0,0x03,0xFF,0xFF,0xFF,0xFF,0xF9, +0xFF,0xE0,0x3F,0xFF,0xF8,0x07,0xFF,0xEF,0xFF,0x03, +0xFF,0xFF,0x00,0x07,0xFF,0xFF,0xF8,0x1F,0xFF,0xE0, +0x00,0x0F,0xFF,0xFF,0xC1,0xFF,0xFC,0x00,0x00,0x3F, +0xFF,0xFE,0x0F,0xFF,0xC0,0x00,0x00,0xFF,0xFF,0xF0, +0xFF,0xFC,0x00,0x00,0x03,0xFF,0xFF,0x87,0xFF,0xC0, +0x00,0x00,0x0F,0xFF,0xFC,0x7F,0xFE,0x00,0x00,0x00, +0x3F,0xFF,0xF0,0x7F,0xFC,0x00,0x00,0x00,0x1F,0xFF, +0xF0,0xFF,0xF8,0x00,0x00,0x00,0x0F,0xFF,0xF2,0xFF, +0xF0,0x00,0x00,0x00,0x07,0xFF,0xEF,0xFF,0x80,0x00, +0x00,0x00,0x1F,0xFF,0xBF,0xFF,0x00,0x00,0x00,0x00, +0x1F,0xFF,0xDF,0xFF,0x00,0x00,0x00,0x00,0x0F,0xFF, +0x8F,0xFF,0x00,0x00,0x00,0x00,0x0F,0xFF,0x9F,0xFF, +0x00,0x00,0x00,0x00,0x1F,0xFF,0x87,0xFF,0x80,0x00, +0x00,0x00,0x1F,0xFF,0x87,0xFF,0x80,0x00,0x00,0x00, +0x3F,0xFF,0x3F,0xFE,0x00,0x00,0x00,0x01,0xFF,0xF8, +0xFF,0xF0,0x00,0x00,0x00,0x1F,0xFF,0xC7,0xFF,0xC0, +0x00,0x00,0x00,0xFF,0xFE,0x3F,0xFE,0x00,0x00,0x00, +0x0F,0xFF,0xF0,0xFF,0xF8,0x00,0x00,0x00,0x7F,0xFF, +0x87,0xFF,0xE0,0x00,0x00,0x07,0xFF,0xFC,0x1F,0xFF, +0x80,0x00,0x00,0x7F,0xFF,0xE0,0xFF,0xFE,0x00,0x00, +0x07,0xFF,0xFF,0x03,0xFF,0xF8,0x00,0x00,0x7F,0xFF, +0xF8,0x0F,0xFF,0xE0,0x00,0x07,0xFF,0xFF,0xC0,0x7F, +0xFF,0xC0,0x00,0xFF,0xFF,0xFE,0x01,0xFF,0xFF,0xC0, +0x3F,0xFF,0xFF,0xF0,0x07,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0x80,0x1F,0xFF,0xFF,0xFF,0xFF,0xBF,0xFC,0x00, +0x7F,0xFF,0xFF,0xFF,0xFD,0xFF,0xE0,0x01,0xFF,0xFF, +0xFF,0xFF,0xCF,0xFF,0x00,0x07,0xFF,0xFF,0xFF,0xFC, +0x7F,0xF8,0x00,0x1F,0xFF,0xFF,0xFF,0xC3,0xFF,0xC0, +0x00,0x7F,0xFF,0xFF,0xFC,0x1F,0xFE,0x00,0x00,0xFF, +0xFF,0xFF,0x80,0xFF,0xF0,0x00,0x01,0xFF,0xFF,0xF0, +0x07,0xFF,0x80,0x00,0x01,0xFF,0xFE,0x00,0x3F,0xFC, +0x00,0x00,0x01,0xFF,0x80,0x01,0xFF,0xFA,0x00,0x00, +0x00,0x00,0x00,0x01,0xFF,0xFA,0x00,0x00,0x00,0x00, +0x00,0x01,0xFF,0xFA,0x00,0x00,0x00,0x00,0x00,0x01, +0xFF,0xF4,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xE0, +0x09,0x63,0x24,0x00,0xB0,0x00,0x00,0x0F,0xF8,0x07, +0xFE,0x00,0xFF,0xFC,0x1F,0xF8,0x0F,0xFF,0xFE,0x7F, +0xE0,0x7F,0xFF,0xFD,0xFF,0x83,0xFF,0xFF,0xE7,0xFE, +0x1F,0xFF,0xFF,0x9F,0xF8,0xFF,0xFF,0xFE,0x8F,0xFC, +0xFF,0xFF,0xFE,0x3F,0xF7,0xFF,0xFF,0xF8,0xFF,0xFF, +0xFF,0xFF,0xC3,0xFF,0xFF,0xF0,0x3F,0x0F,0xFF,0xFE, +0x00,0x18,0x3F,0xFF,0xF0,0x00,0x20,0xFF,0xFF,0x80, +0x00,0x03,0xFF,0xFC,0x00,0x00,0x11,0xFF,0xFC,0x00, +0x00,0x09,0xFF,0xFC,0x00,0x00,0x05,0xFF,0xFC,0x00, +0x00,0x03,0x7F,0xFC,0x00,0x00,0x01,0xBF,0xFE,0x00, +0x00,0x00,0xDF,0xFF,0x00,0x00,0x00,0x6F,0xFF,0x80, +0x00,0x00,0x37,0xFF,0xC0,0x00,0x00,0x1B,0xFF,0xE0, +0x00,0x00,0x08,0xFF,0xF0,0x00,0x00,0x00,0x0E,0x63, +0x97,0xFD,0x0C,0x00,0x00,0x0F,0xFF,0x00,0x00,0x00, +0x00,0x00,0x7F,0xFF,0xFE,0x00,0x00,0x00,0x00,0x7F, +0xFF,0xFF,0xF0,0x00,0x00,0x00,0x7F,0xFF,0xFF,0xFF, +0x00,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xE0,0x00,0x00, +0x3F,0xFF,0xFF,0xFF,0xFE,0x00,0x00,0x1F,0xFF,0xFF, +0xFF,0xFF,0xC0,0x00,0x0F,0xFF,0xFF,0xFF,0xFF,0xF8, +0x00,0x07,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x03,0xFF, +0xFF,0xFF,0xFF,0xFF,0xC0,0x01,0xFF,0xFF,0xFF,0xFF, +0xFF,0xF8,0x00,0x7F,0xFF,0xE0,0x07,0xFF,0xFF,0x00, +0x3F,0xFF,0xC0,0x00,0x3F,0xFF,0xC0,0x0F,0xFF,0xC0, +0x00,0x07,0xFF,0xF0,0x03,0xFF,0xE0,0x00,0x00,0x7F, +0xFE,0x01,0xFF,0xF0,0x00,0x00,0x1F,0xFF,0x80,0x7F, +0xF8,0x00,0x00,0x03,0xFF,0xE0,0x93,0xFF,0xC0,0x00, +0x00,0x0F,0xFF,0x80,0xFF,0xF0,0x00,0x00,0x01,0xFF, +0x00,0x3F,0xFE,0x00,0x00,0x00,0x70,0x00,0x0F,0xFF, +0x80,0x00,0x00,0x00,0x00,0x03,0xFF,0xF8,0x00,0x00, +0x00,0x00,0x00,0x7F,0xFF,0x00,0x00,0x00,0x00,0x00, +0x1F,0xFF,0xF8,0x00,0x00,0x00,0x00,0x07,0xFF,0xFF, +0xE0,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0x00,0x00, +0x00,0x00,0x3F,0xFF,0xFF,0xFC,0x00,0x00,0x00,0x07, +0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x01,0xFF,0xFF,0xFF, +0xFF,0x00,0x00,0x00,0x3F,0xFF,0xFF,0xFF,0xF8,0x00, +0x00,0x07,0xFF,0xFF,0xFF,0xFF,0xC0,0x00,0x00,0xFF, +0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x0F,0xFF,0xFF,0xFF, +0xFF,0xC0,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFC,0x00, +0x00,0x0F,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x00,0xFF, +0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x07,0xFF,0xFF,0xFF, +0xFE,0x00,0x00,0x00,0x3F,0xFF,0xFF,0xFF,0xC0,0x00, +0x00,0x00,0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x00,0x07, +0xFF,0xFF,0xFE,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF, +0xC0,0x00,0x00,0x00,0x00,0x7F,0xFF,0xF0,0x00,0x00, +0x00,0x00,0x03,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00, +0x3F,0xFF,0x80,0x00,0x00,0x00,0x00,0x07,0xFF,0xE0, +0x07,0x00,0x00,0x00,0x00,0xFF,0xF8,0x7F,0xC0,0x00, +0x00,0x00,0x1F,0xFF,0x1F,0xFF,0x00,0x00,0x00,0x00, +0xFF,0xF3,0xFF,0xC0,0x00,0x00,0x00,0x3F,0xFC,0xFF, +0xF8,0x00,0x00,0x00,0x0F,0xFF,0x3F,0xFE,0x00,0x00, +0x00,0x07,0xFF,0xCF,0xFF,0xC0,0x00,0x00,0x01,0xFF, +0xE1,0xFF,0xF8,0x00,0x00,0x00,0xFF,0xF8,0x7F,0xFF, +0x00,0x00,0x00,0x7F,0xFE,0x0F,0xFF,0xF0,0x00,0x00, +0x3F,0xFF,0x03,0xFF,0xFF,0x00,0x00,0x3F,0xFF,0xC0, +0x7F,0xFF,0xF8,0x00,0xFF,0xFF,0xE0,0x1F,0xFF,0xFF, +0xFF,0xFF,0xFF,0xF0,0x03,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFC,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xFE,0x00,0x0F, +0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x01,0xFF,0xFF,0xFF, +0xFF,0xFF,0x80,0x00,0x3F,0xFF,0xFF,0xFF,0xFF,0xC0, +0x00,0x07,0xFF,0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x7F, +0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x07,0xFF,0xFF,0xFF, +0xC0,0x00,0x00,0x00,0x3F,0xFF,0xFF,0x80,0x00,0x00, +0x00,0x00,0x7F,0xFE,0x00,0x00,0x00,0x08,0xAF,0x0B, +0xFC,0x94,0x00,0x00,0x10,0x00,0x00,0x00,0x0E,0x00, +0x00,0x00,0x03,0xC0,0x00,0x00,0x01,0xF8,0x00,0x00, +0x00,0xFF,0x00,0x00,0x00,0x7F,0xE0,0x00,0x00,0x1F, +0xFC,0x00,0x1A,0x00,0xFF,0xF0,0x00,0x68,0x03,0xFF, +0xC0,0x01,0x20,0x0F,0xFF,0x00,0x06,0xFF,0xFF,0xFF, +0xFF,0x95,0xFF,0xFF,0xFF,0xFE,0x68,0x03,0xFF,0xC0, +0x01,0xA0,0x0F,0xFF,0x00,0x06,0x80,0x3F,0xFC,0x00, +0x1A,0x00,0xFF,0xF0,0x00,0x68,0x03,0xFF,0xC0,0x01, +0xA0,0x0F,0xFF,0x00,0x04,0x80,0x3F,0xFC,0x00,0x00, +0x07,0xFF,0xC0,0x00,0x00,0xFF,0xFC,0x00,0x00,0x1F, +0xFF,0xC0,0x08,0x00,0x3F,0xFF,0xFF,0x20,0x00,0xFF, +0xFF,0xFE,0x80,0x01,0xFF,0xFF,0xF8,0x00,0x1F,0xFF, +0xFF,0x00,0x01,0xFF,0xFF,0xF0,0x00,0x1F,0xFF,0xFE, +0x00,0x00,0xFF,0xFF,0xC0,0x00,0x03,0xFF,0xC0,0x0E, +0x23,0x27,0xFD,0x2B,0x7F,0xFC,0x00,0x00,0x00,0x03, +0xFF,0xF7,0xFF,0xC0,0x00,0x00,0x00,0x3F,0xFF,0x7F, +0xFC,0x00,0x00,0x00,0x03,0xFF,0xF7,0xFF,0xC0,0x00, +0x00,0x00,0x3F,0xFF,0x7F,0xFC,0x00,0x00,0x00,0x03, +0xFF,0xF7,0xFF,0xC0,0x00,0x00,0x00,0x3F,0xFE,0x3F, +0xFC,0x00,0x00,0x00,0x03,0xFF,0xEB,0xFF,0xC0,0x00, +0x00,0x00,0x7F,0xFE,0x3F,0xFE,0x00,0x00,0x00,0x0F, +0xFF,0xE3,0xFF,0xE0,0x00,0x00,0x01,0xFF,0xFC,0xFF, +0xF8,0x00,0x00,0x01,0xFF,0xFE,0x7F,0xFC,0x00,0x00, +0x01,0xFF,0xFF,0x3F,0xFF,0x00,0x00,0x01,0xFF,0xFF, +0x9F,0xFF,0xC0,0x00,0x01,0xFF,0xFF,0xC7,0xFF,0xF0, +0x00,0x03,0xFF,0xFF,0xE3,0xFF,0xFE,0x00,0x07,0xFF, +0xFF,0xF1,0xFF,0xFF,0xE0,0x1F,0xFF,0x7F,0xF8,0x7F, +0xFF,0xFF,0xFF,0xFF,0xBF,0xFC,0x3F,0xFF,0xFF,0xFF, +0xFF,0x9F,0xFE,0x0F,0xFF,0xFF,0xFF,0xFF,0x8F,0xFF, +0x03,0xFF,0xFF,0xFF,0xFF,0x87,0xFF,0x80,0xFF,0xFF, +0xFF,0xFF,0x83,0xFF,0xC0,0x3F,0xFF,0xFF,0xFF,0x81, +0xFF,0xE0,0x0F,0xFF,0xFF,0xFF,0x80,0xFF,0xF0,0x03, +0xFF,0xFF,0xFF,0x00,0x7F,0xF8,0x00,0x7F,0xFF,0xFF, +0x00,0x3F,0xFC,0x00,0x07,0xFF,0xFC,0x00,0x1F,0xFE, +0x00,0x00,0x3F,0xF0,0x00,0x00,0x00,0x0F,0xE2,0x88, +0x01,0x0D,0xFF,0xF0,0x00,0x00,0x00,0x00,0x7F,0xFC, +0xFF,0xF0,0x00,0x00,0x00,0x00,0x7F,0xFE,0x1F,0xFF, +0x00,0x00,0x00,0x00,0x1F,0xFF,0x0F,0xFF,0x00,0x00, +0x00,0x00,0x1F,0xFE,0x41,0xFF,0xF0,0x00,0x00,0x00, +0x07,0xFF,0xC0,0xFF,0xF0,0x00,0x00,0x00,0x07,0xFF, +0x88,0x1F,0xFF,0x00,0x00,0x00,0x01,0xFF,0xF0,0x0F, +0xFF,0x00,0x00,0x00,0x01,0xFF,0xE0,0x0F,0xFF,0x80, +0x00,0x00,0x03,0xFF,0xE0,0x07,0xFF,0x80,0x00,0x00, +0x03,0xFF,0xE0,0x07,0xFF,0x80,0x00,0x00,0x03,0xFF, +0xC0,0x07,0xFF,0xC0,0x00,0x00,0x07,0xFF,0xC0,0x03, +0xFF,0xC0,0x00,0x00,0x07,0xFF,0xC0,0x03,0xFF,0xC0, +0x00,0x00,0x07,0xFF,0x80,0x03,0xFF,0xE0,0x00,0x00, +0x0F,0xFF,0x80,0x01,0xFF,0xE0,0x00,0x00,0x0F,0xFF, +0x80,0x01,0xFF,0xF0,0x00,0x00,0x0F,0xFF,0x00,0x01, +0xFF,0xF0,0x00,0x00,0x1F,0xFF,0x00,0x00,0xFF,0xF0, +0x00,0x00,0x1F,0xFF,0x00,0x00,0xFF,0xF8,0x00,0x00, +0x1F,0xFE,0x01,0x00,0x0F,0xFF,0x00,0x00,0x07,0xFF, +0xC0,0x00,0x0F,0xFF,0x80,0x00,0x07,0xFF,0x80,0x20, +0x00,0xFF,0xF0,0x00,0x01,0xFF,0xF0,0x00,0x00,0xFF, +0xF8,0x00,0x03,0xFF,0xE0,0x04,0x00,0x0F,0xFF,0x00, +0x00,0x7F,0xFC,0x00,0x00,0x0F,0xFF,0x80,0x00,0xFF, +0xF8,0x00,0x80,0x00,0xFF,0xF0,0x00,0x1F,0xFF,0x00, +0x12,0x00,0x0F,0xFF,0x00,0x07,0xFF,0xC0,0x02,0x00, +0x00,0xFF,0xF0,0x01,0xFF,0xF0,0x00,0x00,0x00,0xFF, +0xF0,0x01,0xFF,0xE0,0x00,0x40,0x00,0x0F,0xFF,0x00, +0x7F,0xFC,0x00,0x00,0x00,0x0F,0xFF,0x00,0x7F,0xF8, +0x00,0x08,0x00,0x00,0xFF,0xF0,0x1F,0xFF,0x00,0x00, +0x00,0x00,0xFF,0xF0,0x1F,0xFE,0x00,0x01,0x00,0x00, +0x0F,0xFF,0x07,0xFF,0xC0,0x00,0x00,0x00,0x07,0xFF, +0x07,0xFF,0x80,0x00,0x20,0x00,0x00,0xFF,0xF1,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x7F,0xF1,0xFF,0xE0,0x00, +0x04,0x00,0x00,0x0F,0xFF,0x7F,0xFC,0x00,0x00,0x00, +0x00,0x07,0xFF,0x7F,0xF8,0x00,0x00,0x80,0x00,0x00, +0xFF,0xFF,0xFF,0x00,0x00,0x10,0x00,0x00,0x0F,0xFF, +0xFF,0xC0,0x00,0x00,0x00,0x00,0x07,0xFF,0xFF,0xC0, +0x00,0x02,0x00,0x00,0x00,0xFF,0xFF,0xF0,0x00,0x00, +0x00,0x00,0x00,0x7F,0xFF,0xF0,0x00,0x00,0x40,0x00, +0x00,0x0F,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x07, +0xFF,0xFC,0x00,0x00,0x08,0x00,0x00,0x00,0xFF,0xFF, +0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0x00,0x00, +0x00,0x17,0xE2,0x80,0x01,0x7E,0x3F,0xFC,0x00,0x00, +0x00,0x1F,0xFF,0x00,0x00,0x00,0x07,0xFF,0xBF,0xFE, +0x00,0x00,0x00,0x1F,0xFF,0x80,0x00,0x00,0x0F,0xFF, +0xC3,0xFF,0xC0,0x00,0x00,0x07,0xFF,0xF0,0x00,0x00, +0x01,0xFF,0xE3,0xFF,0xE0,0x00,0x00,0x07,0xFF,0xF0, +0x00,0x00,0x03,0xFF,0xE8,0x3F,0xFC,0x00,0x00,0x01, +0xFF,0xFF,0x00,0x00,0x00,0x7F,0xF8,0x3F,0xFC,0x00, +0x00,0x01,0xFF,0xFF,0x00,0x00,0x00,0xFF,0xF8,0x3F, +0xFE,0x00,0x00,0x01,0xFF,0xFF,0x00,0x00,0x00,0xFF, +0xF9,0x03,0xFF,0xC0,0x00,0x00,0x7F,0xFF,0xF0,0x00, +0x00,0x1F,0xFE,0x03,0xFF,0xE0,0x00,0x00,0x7F,0xFF, +0xF0,0x00,0x00,0x3F,0xFE,0x01,0xFF,0xE0,0x00,0x00, +0x7F,0xFF,0xF0,0x00,0x00,0x3F,0xFC,0x01,0xFF,0xE0, +0x00,0x00,0xFF,0xFF,0xF8,0x00,0x00,0x3F,0xFC,0x01, +0xFF,0xF0,0x00,0x00,0xFF,0xFF,0xF8,0x00,0x00,0x7F, +0xFC,0x00,0xFF,0xF0,0x00,0x00,0xFF,0xDF,0xF8,0x00, +0x00,0x7F,0xF8,0x00,0xFF,0xF0,0x00,0x00,0xFF,0xDF, +0xFC,0x00,0x00,0x7F,0xF8,0x00,0xFF,0xF0,0x00,0x01, +0xFF,0xDF,0xFC,0x00,0x00,0x7F,0xF8,0x00,0x7F,0xF8, +0x00,0x01,0xFF,0xDF,0xFC,0x00,0x00,0xFF,0xF0,0x00, +0x7F,0xF8,0x00,0x01,0xFF,0x8F,0xFC,0x00,0x00,0xFF, +0xF0,0x00,0x7F,0xF8,0x00,0x01,0xFF,0x8F,0xFE,0x00, +0x00,0xFF,0xF0,0x20,0x07,0xFF,0x80,0x00,0x7F,0xF1, +0xFF,0xC0,0x00,0x3F,0xFC,0x00,0x07,0xFF,0x80,0x00, +0x7F,0xE0,0xFF,0xC0,0x00,0x3F,0xFC,0x00,0x07,0xFF, +0x80,0x00,0x7F,0xE0,0xFF,0xE0,0x00,0x7F,0xF8,0x04, +0x00,0x7F,0xF8,0x00,0x1F,0xFC,0x1F,0xFC,0x00,0x0F, +0xFF,0x00,0x00,0x7F,0xF8,0x00,0x1F,0xF8,0x0F,0xFC, +0x00,0x0F,0xFF,0x00,0x00,0x3F,0xFC,0x00,0x1F,0xF8, +0x0F,0xFE,0x00,0x1F,0xFE,0x00,0x80,0x07,0xFF,0x80, +0x07,0xFF,0x01,0xFF,0xC0,0x03,0xFF,0xC0,0x00,0x03, +0xFF,0xC0,0x07,0xFE,0x00,0xFF,0xC0,0x07,0xFF,0x80, +0x10,0x00,0x7F,0xF8,0x01,0xFF,0xC0,0x1F,0xFC,0x00, +0xFF,0xF0,0x00,0x00,0x3F,0xF8,0x01,0xFF,0xC0,0x1F, +0xFC,0x00,0xFF,0xE0,0x00,0x00,0x3F,0xFC,0x01,0xFF, +0x80,0x0F,0xFC,0x01,0xFF,0xE0,0x00,0x00,0x3F,0xFC, +0x03,0xFF,0x80,0x0F,0xFE,0x01,0xFF,0xE0,0x00,0x00, +0x1F,0xFC,0x03,0xFF,0x80,0x0F,0xFE,0x01,0xFF,0xC0, +0x00,0x00,0x1F,0xFE,0x03,0xFF,0x80,0x0F,0xFE,0x03, +0xFF,0xC0,0x00,0x00,0x1F,0xFE,0x03,0xFF,0x00,0x07, +0xFE,0x03,0xFF,0xC0,0x00,0x00,0x1F,0xFE,0x07,0xFF, +0x00,0x07,0xFF,0x03,0xFF,0x80,0x00,0x00,0x0F,0xFE, +0x07,0xFF,0x00,0x07,0xFF,0x07,0xFF,0x80,0x00,0x00, +0x0F,0xFF,0x07,0xFF,0x00,0x07,0xFF,0x07,0xFF,0x80, +0x00,0x00,0x0F,0xFF,0x07,0xFE,0x00,0x03,0xFF,0x07, +0xFF,0x80,0x00,0x00,0x07,0xFF,0x0F,0xFE,0x00,0x03, +0xFF,0x87,0xFF,0x00,0x00,0x00,0x07,0xFF,0x0F,0xFE, +0x00,0x03,0xFF,0x8F,0xFF,0x00,0x00,0x00,0x07,0xFF, +0x8F,0xFE,0x00,0x03,0xFF,0x8F,0xFF,0x00,0x00,0x00, +0x03,0xFF,0x8F,0xFC,0x00,0x01,0xFF,0x8F,0xFE,0x00, +0x00,0x00,0x03,0xFF,0x9F,0xFC,0x00,0x01,0xFF,0xCF, +0xFE,0x00,0x00,0x00,0x03,0xFF,0x9F,0xFC,0x00,0x01, +0xFF,0xDF,0xFE,0x00,0x00,0x00,0x01,0xFF,0x9F,0xFC, +0x00,0x01,0xFF,0xDF,0xFC,0x00,0x00,0x00,0x01,0xFF, +0xDF,0xF8,0x00,0x00,0xFF,0xDF,0xFC,0x00,0x00,0x00, +0x01,0xFF,0xFF,0xF8,0x00,0x00,0xFF,0xFF,0xFC,0x00, +0x02,0x00,0x00,0x1F,0xFF,0xFF,0x00,0x00,0x1F,0xFF, +0xFF,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFE,0x00,0x00, +0x0F,0xFF,0xFF,0x00,0x00,0x48,0x00,0x01,0xFF,0xFF, +0xC0,0x00,0x01,0xFF,0xFF,0xC0,0x00,0x00,0x00,0x01, +0xFF,0xFF,0x80,0x00,0x00,0xFF,0xFF,0x80,0x00,0x09, +0x00,0x00,0x1F,0xFF,0xF0,0x00,0x00,0x1F,0xFF,0xF0, +0x00,0x01,0x20,0x00,0x01,0xFF,0xFC,0x00,0x00,0x01, +0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0xFF,0xFC,0x00, +0x00,0x01,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0xFF, +0xF8,0x00,0x00,0x00,0xFF,0xF8,0x00,0x00,0x00,0x10, +0x22,0x84,0x01,0x08,0x7F,0xFF,0x00,0x00,0x00,0x00, +0x7F,0xFE,0x1F,0xFF,0x80,0x00,0x00,0x00,0x7F,0xFE, +0x07,0xFF,0xE0,0x00,0x00,0x00,0x7F,0xFF,0x03,0xFF, +0xF8,0x00,0x00,0x00,0x7F,0xFF,0x00,0xFF,0xFC,0x00, +0x00,0x00,0x3F,0xFF,0x00,0x3F,0xFF,0x00,0x00,0x00, +0x3F,0xFF,0x80,0x1F,0xFF,0xC0,0x00,0x00,0x3F,0xFF, +0x80,0x07,0xFF,0xE0,0x00,0x00,0x1F,0xFF,0x80,0x01, +0xFF,0xF8,0x00,0x00,0x1F,0xFF,0x80,0x00,0x7F,0xFE, +0x00,0x00,0x1F,0xFF,0xC0,0x00,0x3F,0xFF,0x80,0x00, +0x1F,0xFF,0xC0,0x00,0x0F,0xFF,0xC0,0x00,0x0F,0xFF, +0xC0,0x00,0x03,0xFF,0xF0,0x00,0x0F,0xFF,0xE0,0x00, +0x01,0xFF,0xFC,0x00,0x0F,0xFF,0xE0,0x00,0x00,0x7F, +0xFE,0x00,0x0F,0xFF,0xE0,0x00,0x00,0x1F,0xFF,0x80, +0x07,0xFF,0xE0,0x00,0x00,0x0F,0xFF,0xE0,0x07,0xFF, +0xF0,0x00,0x00,0x03,0xFF,0xF0,0x07,0xFF,0xF0,0x00, +0x00,0x00,0xFF,0xFC,0x03,0xFF,0xF0,0x00,0x00,0x00, +0x7F,0xFF,0x03,0xFF,0xF0,0x00,0x00,0x00,0x1F,0xFF, +0x83,0xFF,0xF8,0x00,0x00,0x00,0x07,0xFF,0xE3,0xFF, +0xF8,0x00,0x00,0x00,0x01,0xFF,0xF9,0xFF,0xF8,0x00, +0x00,0x00,0x00,0xFF,0xFD,0xFF,0xFC,0x00,0x00,0x00, +0x00,0x3F,0xFF,0xFF,0xFC,0x00,0x00,0x00,0x00,0x0F, +0xFF,0xFF,0xFC,0x00,0x00,0x00,0x00,0x07,0xFF,0xFF, +0xFC,0x00,0x00,0x00,0x00,0x01,0xFF,0xFF,0xFE,0x00, +0x00,0x00,0x00,0x00,0x7F,0xFF,0xFE,0x00,0x00,0x00, +0x00,0x00,0x3F,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00, +0x0F,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x03,0xFF, +0xFF,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xFF,0x00, +0x00,0x01,0x00,0x00,0x00,0x0F,0xFF,0xE0,0x00,0x00, +0x00,0x00,0x00,0x0F,0xFF,0xF8,0x00,0x00,0x00,0x00, +0x00,0x07,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x07, +0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xFF, +0xC0,0x00,0x01,0x00,0x00,0x00,0xFF,0xFF,0xFE,0x00, +0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0x80,0x00,0x00, +0x00,0x00,0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x00,0x00, +0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x00,0x00,0x7F,0xFE, +0xFF,0xFC,0x00,0x00,0x00,0x00,0x7F,0xFF,0x7F,0xFF, +0x00,0x00,0x00,0x00,0x7F,0xFF,0x1F,0xFF,0x80,0x00, +0x00,0x00,0x3F,0xFF,0x07,0xFF,0xE0,0x00,0x00,0x00, +0x3F,0xFF,0x01,0xFF,0xF8,0x00,0x00,0x00,0x3F,0xFF, +0x80,0xFF,0xFE,0x00,0x00,0x00,0x3F,0xFF,0x80,0x3F, +0xFF,0x00,0x00,0x00,0x1F,0xFF,0x80,0x0F,0xFF,0xC0, +0x00,0x00,0x1F,0xFF,0xC0,0x07,0xFF,0xF0,0x00,0x00, +0x1F,0xFF,0xC0,0x01,0xFF,0xF8,0x00,0x00,0x1F,0xFF, +0xC0,0x00,0x7F,0xFE,0x00,0x00,0x0F,0xFF,0xC0,0x00, +0x3F,0xFF,0x80,0x00,0x0F,0xFF,0xE0,0x00,0x0F,0xFF, +0xC0,0x00,0x0F,0xFF,0xE0,0x00,0x03,0xFF,0xF0,0x00, +0x07,0xFF,0xE0,0x00,0x01,0xFF,0xFC,0x00,0x07,0xFF, +0xE0,0x00,0x00,0x7F,0xFE,0x00,0x07,0xFF,0xF0,0x00, +0x00,0x1F,0xFF,0x80,0x07,0xFF,0xF0,0x00,0x00,0x07, +0xFF,0xE0,0x03,0xFF,0xF0,0x00,0x00,0x03,0xFF,0xF8, +0x03,0xFF,0xF8,0x00,0x00,0x00,0xFF,0xFC,0x03,0xFF, +0xF8,0x00,0x00,0x00,0x3F,0xFF,0x01,0xFF,0xF8,0x00, +0x00,0x00,0x1F,0xFF,0xC1,0xFF,0xF8,0x00,0x00,0x00, +0x07,0xFF,0xE1,0xFF,0xFC,0x00,0x00,0x00,0x01,0xFF, +0xF9,0xFF,0xFC,0x00,0x00,0x00,0x00,0xFF,0xFE,0x0F, +0x70,0x0B,0x95,0x05,0xFF,0xF0,0x00,0x00,0x00,0x00, +0xFF,0xF3,0xFF,0xC0,0x00,0x00,0x00,0x07,0xFF,0xCF, +0xFF,0x80,0x00,0x00,0x00,0x1F,0xFF,0x3F,0xFE,0x00, +0x00,0x00,0x00,0x7F,0xF8,0x7F,0xF8,0x00,0x00,0x00, +0x03,0xFF,0xE1,0xFF,0xF0,0x00,0x00,0x00,0x0F,0xFF, +0x87,0xFF,0xC0,0x00,0x00,0x00,0x3F,0xFC,0x0F,0xFF, +0x00,0x00,0x00,0x01,0xFF,0xF0,0x3F,0xFE,0x00,0x00, +0x00,0x07,0xFF,0xC0,0xFF,0xF8,0x00,0x00,0x00,0x1F, +0xFE,0x01,0xFF,0xE0,0x00,0x00,0x00,0xFF,0xF8,0x07, +0xFF,0xC0,0x00,0x00,0x03,0xFF,0xE0,0x0F,0xFF,0x00, +0x00,0x00,0x0F,0xFF,0x00,0x3F,0xFC,0x00,0x00,0x00, +0x7F,0xFC,0x00,0xFF,0xF8,0x00,0x00,0x01,0xFF,0xF0, +0x01,0xFF,0xE0,0x00,0x00,0x07,0xFF,0x82,0x00,0xFF, +0xF8,0x00,0x00,0x07,0xFF,0xC0,0x01,0xFF,0xE0,0x00, +0x00,0x1F,0xFE,0x04,0x00,0xFF,0xF8,0x00,0x00,0x1F, +0xFF,0x00,0x01,0xFF,0xE0,0x00,0x00,0x7F,0xF8,0x00, +0x07,0xFF,0xC0,0x00,0x03,0xFF,0xE0,0x00,0x0F,0xFF, +0x00,0x00,0x0F,0xFF,0x00,0x00,0x3F,0xFC,0x00,0x00, +0x7F,0xFC,0x00,0x00,0xFF,0xF8,0x00,0x01,0xFF,0xF0, +0x00,0x01,0xFF,0xE0,0x00,0x07,0xFF,0x80,0x00,0x07, +0xFF,0x80,0x00,0x3F,0xFE,0x00,0x00,0x1F,0xFF,0x00, +0x00,0xFF,0xF8,0x00,0x00,0x3F,0xFC,0x00,0x03,0xFF, +0xC0,0x08,0x00,0x1F,0xFF,0x00,0x03,0xFF,0xE0,0x00, +0x00,0x3F,0xFC,0x00,0x0F,0xFF,0x00,0x00,0x00,0xFF, +0xF8,0x00,0x7F,0xFC,0x00,0x00,0x01,0xFF,0xE0,0x01, +0xFF,0xF0,0x00,0x00,0x07,0xFF,0x80,0x07,0xFF,0x80, +0x00,0x00,0x1F,0xFF,0x00,0x3F,0xFE,0x00,0x00,0x00, +0x3F,0xFC,0x00,0xFF,0xF8,0x00,0x00,0x00,0xFF,0xF0, +0x03,0xFF,0xC0,0x00,0x00,0x03,0xFF,0xE0,0x1F,0xFF, +0x00,0x00,0x00,0x07,0xFF,0x80,0x7F,0xFC,0x00,0x00, +0x00,0x1F,0xFE,0x01,0xFF,0xE0,0x00,0x00,0x00,0x7F, +0xFC,0x0F,0xFF,0x80,0x00,0x00,0x00,0xFF,0xF0,0x3F, +0xFE,0x00,0x00,0x00,0x03,0xFF,0xC0,0xFF,0xF0,0x00, +0x00,0x00,0x07,0xFF,0x87,0xFF,0xC0,0x00,0x00,0x00, +0x1F,0xFE,0x1F,0xFE,0x00,0x00,0x00,0x00,0x7F,0xF8, +0xFF,0xF8,0x00,0x00,0x00,0x00,0xFF,0xF3,0xFF,0xE0, +0x00,0x00,0x00,0x03,0xFF,0xCF,0xFF,0x00,0x00,0x00, +0x00,0x0F,0xFF,0x7F,0xFC,0x00,0x00,0x00,0x00,0x1F, +0xFD,0xFF,0xF0,0x00,0x04,0x00,0x00,0x0F,0xFF,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF,0xC0,0x00, +0x00,0x00,0x00,0x7F,0xFF,0xFE,0x00,0x00,0x20,0x00, +0x00,0x1F,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x7F, +0xFF,0xF8,0x00,0x00,0x40,0x00,0x00,0x1F,0xFF,0xFC, +0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0xE0,0x00,0x00, +0x80,0x00,0x00,0x1F,0xFF,0xF0,0x00,0x00,0x00,0x00, +0x00,0x7F,0xFF,0x80,0x00,0x01,0x00,0x00,0x00,0x1F, +0xFF,0xC0,0x00,0x00,0x90,0x00,0x00,0x07,0xFF,0xC0, +0x00,0x00,0x40,0x00,0x00,0x07,0xFF,0xC0,0x00,0x00, +0x00,0x00,0x00,0x1F,0xFE,0x00,0x00,0x00,0x80,0x00, +0x00,0x1F,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x7F, +0xF8,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xE0,0x00, +0x00,0x00,0x00,0x00,0x0F,0xFF,0x00,0x00,0x00,0x10, +0x00,0x00,0x0F,0xFF,0x80,0x00,0x00,0x08,0x00,0x00, +0x0F,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x7F,0xFC, +0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xF0,0x00,0x00, +0x00,0x01,0x80,0x7F,0xFF,0x80,0x00,0x00,0x00,0x07, +0xFF,0xFF,0xFE,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF, +0xF0,0x00,0x00,0x00,0x10,0x07,0xFF,0xFF,0xF0,0x00, +0x00,0x00,0x00,0x1F,0xFF,0xFF,0x80,0x00,0x00,0x00, +0x00,0x7F,0xFF,0xFC,0x00,0x00,0x00,0x00,0x01,0xFF, +0xFF,0xE0,0x00,0x00,0x00,0x00,0x03,0xFF,0xFF,0x00, +0x00,0x00,0x00,0x00,0x0F,0xFF,0xF8,0x00,0x00,0x00, +0x00,0x00,0x3F,0xFF,0x80,0x00,0x00,0x00,0x00,0x00, +0x1F,0xF0,0x00,0x00,0x00,0x00,0x00,0x0F,0x22,0x94, +0x01,0x0F,0x43,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF2, +0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0x1F,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0xFF,0xFF,0xFF,0xFF, +0x8F,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF, +0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xF0,0x00,0x00, +0x00,0x00,0x00,0x7F,0xFF,0x00,0x00,0x00,0x00,0x00, +0x07,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF, +0x80,0x00,0x00,0x00,0x00,0x07,0xFF,0xF8,0x00,0x00, +0x00,0x00,0x00,0x7F,0xFF,0x80,0x00,0x00,0x00,0x00, +0x03,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF, +0x80,0x00,0x00,0x00,0x00,0x03,0xFF,0xF8,0x00,0x00, +0x00,0x00,0x00,0x3F,0xFF,0xC0,0x00,0x00,0x00,0x00, +0x03,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF, +0xC0,0x00,0x00,0x00,0x00,0x01,0xFF,0xFC,0x00,0x00, +0x00,0x00,0x00,0x1F,0xFF,0xC0,0x00,0x00,0x00,0x00, +0x01,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF, +0xE0,0x00,0x00,0x00,0x00,0x01,0xFF,0xFE,0x00,0x00, +0x00,0x00,0x00,0x1F,0xFF,0xE0,0x00,0x00,0x00,0x00, +0x01,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF, +0xE0,0x00,0x00,0x00,0x00,0x00,0xFF,0xFE,0x00,0x00, +0x00,0x00,0x00,0x0F,0xFF,0xE0,0x00,0x00,0x00,0x00, +0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00, +0x00,0x00,0x00,0x0F,0xFF,0xF0,0x00,0x00,0x00,0x00, +0x00,0x7F,0xFF,0x00,0x00,0x00,0x00,0x00,0x07,0xFF, +0xF0,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0x80,0x00, +0x00,0x00,0x00,0x07,0xFF,0xF8,0x00,0x00,0x00,0x00, +0x00,0x7F,0xFF,0x80,0x00,0x00,0x00,0x00,0x07,0xFF, +0xF8,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0x80,0x00, +0x00,0x00,0x00,0x03,0xFF,0xF8,0x00,0x00,0x00,0x00, +0x00,0x3F,0xFF,0x80,0x00,0x00,0x00,0x00,0x03,0xFF, +0xFC,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xC0,0x00, +0x00,0x00,0x00,0x03,0xFF,0xFC,0x00,0x00,0x00,0x00, +0x00,0x3F,0xFF,0xC0,0x00,0x00,0x00,0x00,0x01,0xFF, +0xFC,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xC0,0x00, +0x00,0x00,0x00,0x01,0xFF,0xFC,0x00,0x00,0x00,0x00, +0x00,0x1F,0xFF,0xE0,0x00,0x00,0x00,0x00,0x01,0xFF, +0xFE,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xE0,0x00, +0x00,0x00,0x00,0x00,0xFF,0xFE,0x00,0x00,0x00,0x00, +0x00,0x0F,0xFF,0xE1,0xFF,0xFF,0xFF,0xFF,0xFF,0xDF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x9F,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0x09,0xBD,0x8F,0x94,0xB0, +0x00,0x00,0x00,0x3F,0xF8,0x00,0x00,0x07,0xFF,0xF0, +0x00,0x00,0x3F,0xFF,0xE0,0x00,0x00,0xFF,0xFF,0xC0, +0x00,0x07,0xFF,0xFF,0xC0,0x00,0x03,0xFF,0xFF,0xE0, +0x00,0x0F,0xFF,0xFF,0xE4,0x00,0x07,0xFF,0xFF,0xF0, +0x00,0x1F,0xFF,0xFF,0xE0,0x00,0x3F,0xFF,0xE0,0x00, +0x00,0x7F,0xFE,0x00,0x00,0x01,0xFF,0xF8,0x00,0x90, +0x00,0x7F,0xFC,0x00,0x34,0x00,0x1F,0xFE,0x00,0x0D, +0x00,0x07,0xFF,0x80,0x03,0x40,0x01,0xFF,0xE0,0x00, +0xA0,0x00,0x7F,0xF8,0x00,0x2C,0x00,0x3F,0xFC,0x00, +0x08,0x00,0x1F,0xFE,0x00,0x00,0x00,0x7F,0xFC,0x00, +0x00,0x00,0xFF,0xF0,0x00,0x00,0x03,0xFF,0xE0,0x00, +0x00,0x0F,0xFF,0x80,0x00,0x00,0x7F,0xFF,0x00,0x00, +0x03,0xFF,0xFC,0x00,0x00,0x7F,0xFF,0xF0,0x00,0x00, +0xFF,0xFF,0xC0,0x00,0x01,0xFF,0xFE,0x00,0x00,0x03, +0xFF,0xF8,0x00,0x00,0x07,0xFF,0xC0,0x00,0x00,0x0F, +0xFE,0x00,0x00,0x00,0x1F,0xFF,0x00,0x00,0x00,0x3F, +0xFF,0x80,0x00,0x00,0x7F,0xFF,0x80,0x00,0x00,0xFF, +0xFF,0xC0,0x00,0x01,0xFF,0xFF,0xC0,0x00,0x00,0x3F, +0xFF,0xC0,0x00,0x00,0x1F,0xFF,0x80,0x00,0x00,0x0F, +0xFF,0x80,0x00,0x00,0x0F,0xFF,0x80,0x00,0x00,0x0F, +0xFF,0x00,0x00,0x00,0x1F,0xFF,0x00,0x01,0x00,0x03, +0xFF,0xC0,0x00,0x58,0x00,0x7F,0xF8,0x00,0x1A,0x00, +0x0F,0xFF,0x00,0x06,0x80,0x03,0xFF,0xC0,0x01,0xA0, +0x00,0xFF,0xF0,0x00,0x58,0x00,0x3F,0xFC,0x00,0x10, +0x00,0x07,0xFF,0x80,0x00,0x00,0x0F,0xFF,0x80,0x00, +0x00,0x1F,0xFF,0x80,0x00,0x00,0x3F,0xFF,0xC0,0x00, +0x00,0x7F,0xFF,0xFF,0xC0,0x00,0x0F,0xFF,0xFF,0xF0, +0x00,0x01,0xFF,0xFF,0xF8,0x00,0x01,0xFF,0xFF,0xF0, +0x00,0x01,0xFF,0xFF,0xE0,0x00,0x01,0xFF,0xFF,0xC0, +0x00,0x01,0xFF,0xFF,0x80,0x00,0x01,0xFF,0xFF,0x00, +0x00,0x00,0xFF,0xFE,0x00,0x00,0x00,0x1F,0xFC,0x02, +0xBE,0xB3,0x88,0x8B,0x7F,0xFD,0xFF,0xF7,0xFF,0xDF, +0xFF,0x7F,0xFD,0xFF,0xF7,0xFF,0xDF,0xFF,0x7F,0xFD, +0xFF,0xF7,0xFF,0xDF,0xFF,0x7F,0xFD,0xFF,0xF7,0xFF, +0xDF,0xFF,0x7F,0xFC,0xFF,0xC0,0x09,0xBD,0x8F,0x94, +0xB1,0xFF,0xC0,0x00,0x00,0x03,0xFF,0xF8,0x00,0x00, +0x07,0xFF,0xFC,0x00,0x00,0x0F,0xFF,0xFC,0x00,0x00, +0x1F,0xFF,0xFC,0x00,0x00,0x3F,0xFF,0xFC,0x00,0x00, +0x7F,0xFF,0xFC,0x00,0x01,0x1F,0xFF,0xFF,0x80,0x00, +0x47,0xFF,0xFF,0xF0,0x00,0x0F,0xFF,0xFF,0xF0,0x00, +0x00,0x1F,0xFF,0xE0,0x00,0x00,0x0F,0xFF,0xC0,0x00, +0x00,0x0F,0xFF,0x80,0x01,0x00,0x01,0xFF,0xE0,0x00, +0x68,0x00,0x3F,0xFC,0x00,0x1A,0x00,0x0F,0xFF,0x00, +0x06,0x80,0x03,0xFF,0xC0,0x01,0x60,0x00,0xFF,0xF0, +0x00,0x58,0x00,0x1F,0xFE,0x00,0x10,0x00,0x03,0xFF, +0xC0,0x00,0x00,0x07,0xFF,0xC0,0x00,0x00,0x07,0xFF, +0x80,0x00,0x00,0x0F,0xFF,0x80,0x00,0x00,0x0F,0xFF, +0x80,0x00,0x00,0x0F,0xFF,0xC0,0x00,0x00,0x1F,0xFF, +0xE0,0x00,0x00,0x1F,0xFF,0xFC,0x00,0x00,0x0F,0xFF, +0xF8,0x00,0x00,0x0F,0xFF,0xF0,0x00,0x00,0x0F,0xFF, +0xE0,0x00,0x00,0x07,0xFF,0xC0,0x00,0x00,0x03,0xFF, +0x80,0x00,0x00,0x1F,0xFF,0x00,0x00,0x00,0xFF,0xFE, +0x00,0x00,0x07,0xFF,0xFC,0x00,0x00,0x1F,0xFF,0xF8, +0x00,0x00,0x7F,0xFF,0xF0,0x00,0x01,0xFF,0xFE,0x00, +0x00,0x07,0xFF,0xF0,0x00,0x00,0x1F,0xFF,0x80,0x00, +0x00,0x3F,0xFE,0x00,0x80,0x00,0x1F,0xFF,0x00,0x20, +0x00,0x0F,0xFF,0x80,0x00,0x00,0x1F,0xFE,0x00,0x14, +0x00,0x0F,0xFF,0x80,0x06,0x80,0x03,0xFF,0xC0,0x01, +0xA0,0x00,0xFF,0xF0,0x00,0x68,0x00,0x3F,0xFC,0x00, +0x14,0x00,0x0F,0xFF,0x00,0x04,0x80,0x07,0xFF,0xC0, +0x00,0x00,0x1F,0xFF,0x80,0x00,0x00,0x7F,0xFE,0x00, +0x00,0x07,0xFF,0xFC,0x00,0x07,0xFF,0xFF,0xF8,0x00, +0x13,0xFF,0xFF,0xFC,0x00,0x03,0xFF,0xFF,0xF0,0x00, +0x07,0xFF,0xFF,0xC0,0x00,0x11,0xFF,0xFF,0xE0,0x00, +0x03,0xFF,0xFF,0x00,0x00,0x07,0xFF,0xFC,0x00,0x00, +0x0F,0xFF,0xE0,0x00,0x00,0x1F,0xFC,0x00,0x00,0x00, +0x00,0x10,0xCC,0x18,0x85,0x38,0x00,0x07,0xFC,0x00, +0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xFC,0x00,0x00, +0x00,0x00,0x04,0x01,0xFF,0xFF,0xF0,0x00,0x00,0x00, +0x00,0xC0,0x3F,0xFF,0xFF,0xC0,0x00,0x00,0x00,0x1C, +0x07,0xFF,0xFF,0xFF,0x80,0x00,0x00,0x03,0xC1,0xFF, +0xFF,0xFF,0xFE,0x00,0x00,0x00,0x7C,0x3F,0xFF,0xFF, +0xFF,0xF8,0x00,0x00,0x0F,0xC3,0xFF,0xFF,0xFF,0xFF, +0xC0,0x00,0x03,0xFC,0x7F,0xFF,0xFF,0xFF,0xFF,0x00, +0x00,0x7F,0xCF,0xFF,0xFF,0xFF,0xFF,0xFE,0x00,0x1F, +0xFD,0xFF,0xFF,0xFF,0xFF,0xFF,0xF8,0x07,0xFF,0xE3, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xBF,0xFE, +0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xFB,0xFF,0x80,0x03, +0xFF,0xFF,0xFF,0xFF,0xFF,0x3F,0xE0,0x00,0x0F,0xFF, +0xFF,0xFF,0xFF,0xE3,0xF8,0x00,0x00,0x3F,0xFF,0xFF, +0xFF,0xFC,0x3F,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF, +0x83,0xE0,0x00,0x00,0x03,0xFF,0xFF,0xFF,0xF0,0x3C, +0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFE,0x03,0x80,0x00, +0x00,0x00,0x3F,0xFF,0xFF,0xC0,0x30,0x00,0x00,0x00, +0x00,0xFF,0xFF,0xF0,0x02,0x00,0x00,0x00,0x00,0x03, +0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xFE, +0x00,0x00,}; +/* font data size: 40352 bytes */ + +static const unsigned char Arial_96_index[] = { +0x00,0x00,0x00,0x05,0x00,0x2D,0x00,0x5E, +0x02,0x38,0x05,0x0A,0x09,0x97,0x0D,0x36,0x0D,0x48, +0x0E,0x68,0x0F,0xA0,0x10,0x5A,0x10,0xB3,0x10,0xD3, +0x10,0xE2,0x10,0xEB,0x12,0x10,0x13,0xD3,0x14,0x99, +0x17,0x08,0x19,0xB5,0x1B,0x9D,0x1D,0x98,0x20,0x42, +0x21,0xE3,0x24,0x4A,0x26,0xC8,0x26,0xE3,0x27,0x15, +0x29,0x12,0x29,0x52,0x2B,0x4F,0x2D,0x49,0x34,0xA3, +0x37,0x86,0x3A,0x2A,0x3D,0x44,0x3F,0xBA,0x40,0x55, +0x40,0xE2,0x44,0x0A,0x44,0xA1,0x44,0xC4,0x45,0xB6, +0x49,0x5E,0x49,0xD1,0x4C,0xB4,0x4F,0xA4,0x52,0xE8, +0x54,0xB1,0x58,0x3A,0x5B,0x77,0x5E,0xCE,0x5F,0x5D, +0x60,0xCB,0x64,0x35,0x69,0x13,0x6C,0xE2,0x6F,0x7D, +0x72,0x5F,0x72,0xA9,0x73,0xCC,0x74,0x16,0x74,0xFA, +0x75,0x13,0x75,0x4B,0x77,0x62,0x79,0x24,0x7A,0xBF, +0x7C,0x7A,0x7E,0x39,0x7E,0xC9,0x80,0xFE,0x81,0xEC, +0x82,0x0D,0x82,0x7C,0x84,0x7F,0x84,0xA0,0x86,0x18, +0x86,0xE8,0x88,0x8F,0x8A,0x52,0x8C,0x00,0x8C,0x80, +0x8E,0x73,0x8F,0x01,0x8F,0xD1,0x91,0x65,0x93,0xF7, +0x96,0x1D,0x98,0x9B,0x9A,0x3D,0x9B,0x77,0x9B,0x9C, +0x9C,0xD7, +}; +/* font index size: 190 bytes */ + +const ILI9341_t3_font_t Arial_96 = { + Arial_96_index, + 0, + Arial_96_data, + 1, + 0, + 32, + 126, + 0, + 0, + 16, + 7, + 7, + 5, + 8, + 8, + 148, + 95 +}; + + + diff --git a/src/glcdfont.c b/src/glcdfont.c new file mode 100644 index 0000000..32885a5 --- /dev/null +++ b/src/glcdfont.c @@ -0,0 +1,286 @@ +#ifndef FONT5X7_H +#define FONT5X7_H + +#include "glcdfont.h" + +// Standard ASCII 5x7 font + +const unsigned char glcdfont[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, + 0x3E, 0x5B, 0x4F, 0x5B, 0x3E, + 0x3E, 0x6B, 0x4F, 0x6B, 0x3E, + 0x1C, 0x3E, 0x7C, 0x3E, 0x1C, + 0x18, 0x3C, 0x7E, 0x3C, 0x18, + 0x1C, 0x57, 0x7D, 0x57, 0x1C, + 0x1C, 0x5E, 0x7F, 0x5E, 0x1C, + 0x00, 0x18, 0x3C, 0x18, 0x00, + 0xFF, 0xE7, 0xC3, 0xE7, 0xFF, + 0x00, 0x18, 0x24, 0x18, 0x00, + 0xFF, 0xE7, 0xDB, 0xE7, 0xFF, + 0x30, 0x48, 0x3A, 0x06, 0x0E, + 0x26, 0x29, 0x79, 0x29, 0x26, + 0x40, 0x7F, 0x05, 0x05, 0x07, + 0x40, 0x7F, 0x05, 0x25, 0x3F, + 0x5A, 0x3C, 0xE7, 0x3C, 0x5A, + 0x7F, 0x3E, 0x1C, 0x1C, 0x08, + 0x08, 0x1C, 0x1C, 0x3E, 0x7F, + 0x14, 0x22, 0x7F, 0x22, 0x14, + 0x5F, 0x5F, 0x00, 0x5F, 0x5F, + 0x06, 0x09, 0x7F, 0x01, 0x7F, + 0x00, 0x66, 0x89, 0x95, 0x6A, + 0x60, 0x60, 0x60, 0x60, 0x60, + 0x94, 0xA2, 0xFF, 0xA2, 0x94, + 0x08, 0x04, 0x7E, 0x04, 0x08, + 0x10, 0x20, 0x7E, 0x20, 0x10, + 0x08, 0x08, 0x2A, 0x1C, 0x08, + 0x08, 0x1C, 0x2A, 0x08, 0x08, + 0x1E, 0x10, 0x10, 0x10, 0x10, + 0x0C, 0x1E, 0x0C, 0x1E, 0x0C, + 0x30, 0x38, 0x3E, 0x38, 0x30, + 0x06, 0x0E, 0x3E, 0x0E, 0x06, + 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x5F, 0x00, 0x00, + 0x00, 0x07, 0x00, 0x07, 0x00, + 0x14, 0x7F, 0x14, 0x7F, 0x14, + 0x24, 0x2A, 0x7F, 0x2A, 0x12, + 0x23, 0x13, 0x08, 0x64, 0x62, + 0x36, 0x49, 0x56, 0x20, 0x50, + 0x00, 0x08, 0x07, 0x03, 0x00, + 0x00, 0x1C, 0x22, 0x41, 0x00, + 0x00, 0x41, 0x22, 0x1C, 0x00, + 0x2A, 0x1C, 0x7F, 0x1C, 0x2A, + 0x08, 0x08, 0x3E, 0x08, 0x08, + 0x00, 0x80, 0x70, 0x30, 0x00, + 0x08, 0x08, 0x08, 0x08, 0x08, + 0x00, 0x00, 0x60, 0x60, 0x00, + 0x20, 0x10, 0x08, 0x04, 0x02, + 0x3E, 0x51, 0x49, 0x45, 0x3E, + 0x00, 0x42, 0x7F, 0x40, 0x00, + 0x72, 0x49, 0x49, 0x49, 0x46, + 0x21, 0x41, 0x49, 0x4D, 0x33, + 0x18, 0x14, 0x12, 0x7F, 0x10, + 0x27, 0x45, 0x45, 0x45, 0x39, + 0x3C, 0x4A, 0x49, 0x49, 0x31, + 0x41, 0x21, 0x11, 0x09, 0x07, + 0x36, 0x49, 0x49, 0x49, 0x36, + 0x46, 0x49, 0x49, 0x29, 0x1E, + 0x00, 0x00, 0x14, 0x00, 0x00, + 0x00, 0x40, 0x34, 0x00, 0x00, + 0x00, 0x08, 0x14, 0x22, 0x41, + 0x14, 0x14, 0x14, 0x14, 0x14, + 0x00, 0x41, 0x22, 0x14, 0x08, + 0x02, 0x01, 0x59, 0x09, 0x06, + 0x3E, 0x41, 0x5D, 0x59, 0x4E, + 0x7C, 0x12, 0x11, 0x12, 0x7C, + 0x7F, 0x49, 0x49, 0x49, 0x36, + 0x3E, 0x41, 0x41, 0x41, 0x22, + 0x7F, 0x41, 0x41, 0x41, 0x3E, + 0x7F, 0x49, 0x49, 0x49, 0x41, + 0x7F, 0x09, 0x09, 0x09, 0x01, + 0x3E, 0x41, 0x41, 0x51, 0x73, + 0x7F, 0x08, 0x08, 0x08, 0x7F, + 0x00, 0x41, 0x7F, 0x41, 0x00, + 0x20, 0x40, 0x41, 0x3F, 0x01, + 0x7F, 0x08, 0x14, 0x22, 0x41, + 0x7F, 0x40, 0x40, 0x40, 0x40, + 0x7F, 0x02, 0x1C, 0x02, 0x7F, + 0x7F, 0x04, 0x08, 0x10, 0x7F, + 0x3E, 0x41, 0x41, 0x41, 0x3E, + 0x7F, 0x09, 0x09, 0x09, 0x06, + 0x3E, 0x41, 0x51, 0x21, 0x5E, + 0x7F, 0x09, 0x19, 0x29, 0x46, + 0x26, 0x49, 0x49, 0x49, 0x32, + 0x03, 0x01, 0x7F, 0x01, 0x03, + 0x3F, 0x40, 0x40, 0x40, 0x3F, + 0x1F, 0x20, 0x40, 0x20, 0x1F, + 0x3F, 0x40, 0x38, 0x40, 0x3F, + 0x63, 0x14, 0x08, 0x14, 0x63, + 0x03, 0x04, 0x78, 0x04, 0x03, + 0x61, 0x59, 0x49, 0x4D, 0x43, + 0x00, 0x7F, 0x41, 0x41, 0x41, + 0x02, 0x04, 0x08, 0x10, 0x20, + 0x00, 0x41, 0x41, 0x41, 0x7F, + 0x04, 0x02, 0x01, 0x02, 0x04, + 0x40, 0x40, 0x40, 0x40, 0x40, + 0x00, 0x03, 0x07, 0x08, 0x00, + 0x20, 0x54, 0x54, 0x78, 0x40, + 0x7F, 0x28, 0x44, 0x44, 0x38, + 0x38, 0x44, 0x44, 0x44, 0x28, + 0x38, 0x44, 0x44, 0x28, 0x7F, + 0x38, 0x54, 0x54, 0x54, 0x18, + 0x00, 0x08, 0x7E, 0x09, 0x02, + 0x18, 0xA4, 0xA4, 0x9C, 0x78, + 0x7F, 0x08, 0x04, 0x04, 0x78, + 0x00, 0x44, 0x7D, 0x40, 0x00, + 0x20, 0x40, 0x40, 0x3D, 0x00, + 0x7F, 0x10, 0x28, 0x44, 0x00, + 0x00, 0x41, 0x7F, 0x40, 0x00, + 0x7C, 0x04, 0x78, 0x04, 0x78, + 0x7C, 0x08, 0x04, 0x04, 0x78, + 0x38, 0x44, 0x44, 0x44, 0x38, + 0xFC, 0x18, 0x24, 0x24, 0x18, + 0x18, 0x24, 0x24, 0x18, 0xFC, + 0x7C, 0x08, 0x04, 0x04, 0x08, + 0x48, 0x54, 0x54, 0x54, 0x24, + 0x04, 0x04, 0x3F, 0x44, 0x24, + 0x3C, 0x40, 0x40, 0x20, 0x7C, + 0x1C, 0x20, 0x40, 0x20, 0x1C, + 0x3C, 0x40, 0x30, 0x40, 0x3C, + 0x44, 0x28, 0x10, 0x28, 0x44, + 0x4C, 0x90, 0x90, 0x90, 0x7C, + 0x44, 0x64, 0x54, 0x4C, 0x44, + 0x00, 0x08, 0x36, 0x41, 0x00, + 0x00, 0x00, 0x77, 0x00, 0x00, + 0x00, 0x41, 0x36, 0x08, 0x00, + 0x02, 0x01, 0x02, 0x04, 0x02, + 0x3C, 0x26, 0x23, 0x26, 0x3C, + 0x1E, 0xA1, 0xA1, 0x61, 0x12, + 0x3A, 0x40, 0x40, 0x20, 0x7A, + 0x38, 0x54, 0x54, 0x55, 0x59, + 0x21, 0x55, 0x55, 0x79, 0x41, + 0x21, 0x54, 0x54, 0x78, 0x41, + 0x21, 0x55, 0x54, 0x78, 0x40, + 0x20, 0x54, 0x55, 0x79, 0x40, + 0x0C, 0x1E, 0x52, 0x72, 0x12, + 0x39, 0x55, 0x55, 0x55, 0x59, + 0x39, 0x54, 0x54, 0x54, 0x59, + 0x39, 0x55, 0x54, 0x54, 0x58, + 0x00, 0x00, 0x45, 0x7C, 0x41, + 0x00, 0x02, 0x45, 0x7D, 0x42, + 0x00, 0x01, 0x45, 0x7C, 0x40, + 0xF0, 0x29, 0x24, 0x29, 0xF0, + 0xF0, 0x28, 0x25, 0x28, 0xF0, + 0x7C, 0x54, 0x55, 0x45, 0x00, + 0x20, 0x54, 0x54, 0x7C, 0x54, + 0x7C, 0x0A, 0x09, 0x7F, 0x49, + 0x32, 0x49, 0x49, 0x49, 0x32, + 0x32, 0x48, 0x48, 0x48, 0x32, + 0x32, 0x4A, 0x48, 0x48, 0x30, + 0x3A, 0x41, 0x41, 0x21, 0x7A, + 0x3A, 0x42, 0x40, 0x20, 0x78, + 0x00, 0x9D, 0xA0, 0xA0, 0x7D, + 0x39, 0x44, 0x44, 0x44, 0x39, + 0x3D, 0x40, 0x40, 0x40, 0x3D, + 0x3C, 0x24, 0xFF, 0x24, 0x24, + 0x48, 0x7E, 0x49, 0x43, 0x66, + 0x2B, 0x2F, 0xFC, 0x2F, 0x2B, + 0xFF, 0x09, 0x29, 0xF6, 0x20, + 0xC0, 0x88, 0x7E, 0x09, 0x03, + 0x20, 0x54, 0x54, 0x79, 0x41, + 0x00, 0x00, 0x44, 0x7D, 0x41, + 0x30, 0x48, 0x48, 0x4A, 0x32, + 0x38, 0x40, 0x40, 0x22, 0x7A, + 0x00, 0x7A, 0x0A, 0x0A, 0x72, + 0x7D, 0x0D, 0x19, 0x31, 0x7D, + 0x26, 0x29, 0x29, 0x2F, 0x28, + 0x26, 0x29, 0x29, 0x29, 0x26, + 0x30, 0x48, 0x4D, 0x40, 0x20, + 0x38, 0x08, 0x08, 0x08, 0x08, + 0x08, 0x08, 0x08, 0x08, 0x38, + 0x2F, 0x10, 0xC8, 0xAC, 0xBA, + 0x2F, 0x10, 0x28, 0x34, 0xFA, + 0x00, 0x00, 0x7B, 0x00, 0x00, + 0x08, 0x14, 0x2A, 0x14, 0x22, + 0x22, 0x14, 0x2A, 0x14, 0x08, + 0xAA, 0x00, 0x55, 0x00, 0xAA, + 0xAA, 0x55, 0xAA, 0x55, 0xAA, + 0x00, 0x00, 0x00, 0xFF, 0x00, + 0x10, 0x10, 0x10, 0xFF, 0x00, + 0x14, 0x14, 0x14, 0xFF, 0x00, + 0x10, 0x10, 0xFF, 0x00, 0xFF, + 0x10, 0x10, 0xF0, 0x10, 0xF0, + 0x14, 0x14, 0x14, 0xFC, 0x00, + 0x14, 0x14, 0xF7, 0x00, 0xFF, + 0x00, 0x00, 0xFF, 0x00, 0xFF, + 0x14, 0x14, 0xF4, 0x04, 0xFC, + 0x14, 0x14, 0x17, 0x10, 0x1F, + 0x10, 0x10, 0x1F, 0x10, 0x1F, + 0x14, 0x14, 0x14, 0x1F, 0x00, + 0x10, 0x10, 0x10, 0xF0, 0x00, + 0x00, 0x00, 0x00, 0x1F, 0x10, + 0x10, 0x10, 0x10, 0x1F, 0x10, + 0x10, 0x10, 0x10, 0xF0, 0x10, + 0x00, 0x00, 0x00, 0xFF, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0xFF, 0x10, + 0x00, 0x00, 0x00, 0xFF, 0x14, + 0x00, 0x00, 0xFF, 0x00, 0xFF, + 0x00, 0x00, 0x1F, 0x10, 0x17, + 0x00, 0x00, 0xFC, 0x04, 0xF4, + 0x14, 0x14, 0x17, 0x10, 0x17, + 0x14, 0x14, 0xF4, 0x04, 0xF4, + 0x00, 0x00, 0xFF, 0x00, 0xF7, + 0x14, 0x14, 0x14, 0x14, 0x14, + 0x14, 0x14, 0xF7, 0x00, 0xF7, + 0x14, 0x14, 0x14, 0x17, 0x14, + 0x10, 0x10, 0x1F, 0x10, 0x1F, + 0x14, 0x14, 0x14, 0xF4, 0x14, + 0x10, 0x10, 0xF0, 0x10, 0xF0, + 0x00, 0x00, 0x1F, 0x10, 0x1F, + 0x00, 0x00, 0x00, 0x1F, 0x14, + 0x00, 0x00, 0x00, 0xFC, 0x14, + 0x00, 0x00, 0xF0, 0x10, 0xF0, + 0x10, 0x10, 0xFF, 0x10, 0xFF, + 0x14, 0x14, 0x14, 0xFF, 0x14, + 0x10, 0x10, 0x10, 0x1F, 0x00, + 0x00, 0x00, 0x00, 0xF0, 0x10, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, + 0xFF, 0xFF, 0xFF, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xFF, 0xFF, + 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, + 0x38, 0x44, 0x44, 0x38, 0x44, + 0x7C, 0x2A, 0x2A, 0x3E, 0x14, + 0x7E, 0x02, 0x02, 0x06, 0x06, + 0x02, 0x7E, 0x02, 0x7E, 0x02, + 0x63, 0x55, 0x49, 0x41, 0x63, + 0x38, 0x44, 0x44, 0x3C, 0x04, + 0x40, 0x7E, 0x20, 0x1E, 0x20, + 0x06, 0x02, 0x7E, 0x02, 0x02, + 0x99, 0xA5, 0xE7, 0xA5, 0x99, + 0x1C, 0x2A, 0x49, 0x2A, 0x1C, + 0x4C, 0x72, 0x01, 0x72, 0x4C, + 0x30, 0x4A, 0x4D, 0x4D, 0x30, + 0x30, 0x48, 0x78, 0x48, 0x30, + 0xBC, 0x62, 0x5A, 0x46, 0x3D, + 0x3E, 0x49, 0x49, 0x49, 0x00, + 0x7E, 0x01, 0x01, 0x01, 0x7E, + 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, + 0x44, 0x44, 0x5F, 0x44, 0x44, + 0x40, 0x51, 0x4A, 0x44, 0x40, + 0x40, 0x44, 0x4A, 0x51, 0x40, + 0x00, 0x00, 0xFF, 0x01, 0x03, + 0xE0, 0x80, 0xFF, 0x00, 0x00, + 0x08, 0x08, 0x6B, 0x6B, 0x08, + 0x36, 0x12, 0x36, 0x24, 0x36, + 0x06, 0x0F, 0x09, 0x0F, 0x06, + 0x00, 0x00, 0x18, 0x18, 0x00, + 0x00, 0x00, 0x10, 0x10, 0x00, + 0x30, 0x40, 0xFF, 0x01, 0x01, + 0x00, 0x1F, 0x01, 0x01, 0x1E, + 0x00, 0x19, 0x1D, 0x17, 0x12, + 0x00, 0x3C, 0x3C, 0x3C, 0x3C, + 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +const ILI9341_t3_font_t Font5x7 = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +#endif // FONT5X7_H diff --git a/src/i2c.c b/src/i2c.c new file mode 100644 index 0000000..1c25a2f --- /dev/null +++ b/src/i2c.c @@ -0,0 +1,152 @@ +/* + * i2c.c + * + * Created on: Sep 30, 2017 + * Author: pascal.spring + */ + + +#include + +#include "i2c.h" + + +void i2c_init(I2C_TypeDef * I2Cx) +{ + + //I2C1->TIMINGR = 0x901d23; + //I2C1->TIMINGR = 0x50330309; + //I2C1->CR1 |= I2C_CR1_ANFOFF; + //I2C1->CR2 |= I2C_CR2_AUTOEND; + if(I2Cx==I2C1) + { + RCC->APB1RSTR |= RCC_APB1RSTR_I2C1RST; + RCC->APB1RSTR &= ~RCC_APB1RSTR_I2C1RST; + RCC->CFGR3 |= RCC_CFGR3_I2C1SW; + + } + else + { + RCC->APB1RSTR |= RCC_APB1RSTR_I2C2RST; + RCC->APB1RSTR &= ~RCC_APB1RSTR_I2C2RST; + } + I2Cx->CR1 = 0x0; + I2Cx->CR2 = 0x0; + I2Cx->TIMINGR = 0x0; + + + I2Cx->TIMINGR |= (4<<28); // prescaler 1:4 == 12MHz + //I2C1->TIMINGR |= (176<<20); + I2Cx->TIMINGR |= (9<<8); // SCL high time == 15 cycles == 1,25uS 36==100kHz + I2Cx->TIMINGR |= (9<<0); + I2Cx->CR1 |= I2C_CR1_PE; + +} + + +uint8_t i2c_status(I2C_TypeDef * I2Cx, uint8_t stat) { + uint32_t flags1,flags2,last_ev; + uint32_t status[6] = { 0x8004, + 0x8001, + 0x8000, + 0x8009, + 0x8008, + }; + /* + uint32_t status[6] = { 0x30040, // 0 - master byte received - BUSY MSL RXNE + 0x70084, // 1 - master byte transmitted - BUSY MSL TXE TRA BTF + 0x30001, // 2 - master mode select - BUSY MSL SB + 0x70082, // 3 - master transmitter mode selected - BUSY MSL ADDR TXE TRA + 0x30002, // 4 - master receiver mode selected - BUSY MSL ADDR + }; + */ + flags1 = I2Cx->ISR; + //flags2 = I2C1->SR2; + //flags2<<=16; + + last_ev =(flags1) & 0xffff; + + if((last_ev & status[stat])!=status[stat]) { + return 0; + } + else { + return 1; + } +} + + +void i2c_start(I2C_TypeDef * I2Cx) { + //while(I2C1->ISR & I2C_ISR_BUSY); + + I2Cx->CR2 |= I2C_CR2_START; // set start condition + } + +/* +void i2c_restart(void) { + I2C1->CR2 |= 0x2000; + while(!(i2c_status(2))); + } +*/ +void i2c_stop(I2C_TypeDef * I2Cx) +{ + DMA1_Channel5->CCR &= ~(DMA_CCR_EN); + DMA1->IFCR |= DMA_IFCR_CTCIF5; + DMA1_Channel4->CCR &= ~DMA_CCR_EN; + DMA1->IFCR |= DMA_IFCR_CTCIF4; + I2Cx->CR2 |= I2C_CR2_STOP; +} + +void i2c_reset(I2C_TypeDef * I2Cx) +{ + while(!(I2Cx->ISR & I2C_ISR_STOPF)); + I2Cx->ICR &= ~(I2C_ICR_STOPCF); +} + +void i2c_autoend(I2C_TypeDef * I2Cx, uint8_t autoend) { + autoend = autoend & 0x1; + I2Cx->CR2 = ((uint32_t)(autoend) << 29); +} + +void i2c_set_nbytes(I2C_TypeDef * I2Cx, uint8_t nbytes) { + uint32_t tmp=0; + tmp |= I2C_CR2_NBYTES; + I2Cx->CR2 &= ~(tmp); + I2Cx->CR2 |= ((uint32_t)(nbytes)<<16); + DMA1_Channel4->CNDTR=nbytes; + DMA1_Channel5->CNDTR=nbytes; +} + +uint8_t i2c_read_ack(I2C_TypeDef * I2Cx) { + + while(!(I2Cx->ISR & I2C_ISR_RXNE)); + return I2Cx->RXDR; + +} + +uint8_t i2c_read_nack(I2C_TypeDef * I2Cx) { + uint8_t tmp=0; + + tmp = I2Cx->RXDR; + //I2C1->CR2 |= (I2C_CR2_NACK); // disable ACK flag + //I2C1->CR2 |= (I2C_CR2_START); + while(!(I2Cx->ISR & I2C_ISR_RXNE)); + //while(!(i2c_status(0))); + return tmp; +} + +void i2c_write_addr(I2C_TypeDef * I2Cx, uint8_t addr, uint8_t dir) { + //while(I2C1->ISR & I2C_ISR_BUSY); + uint32_t tmp=0; + dir = dir & 0x1; + tmp |= I2C_CR2_SADD | I2C_CR2_RD_WRN; + I2Cx->CR2 &= ~(tmp); + I2Cx->CR2 |= ((uint32_t)(addr)<<1); + I2Cx->CR2 |= ((uint32_t)(dir)<<10); + dir==0 ? DMA1_Channel4->CCR |= DMA_CCR_EN : (DMA1_Channel5->CCR |= DMA_CCR_EN); +} + + +void i2c_write(I2C_TypeDef * I2Cx, uint8_t data) { + while(!(I2Cx->ISR & I2C_ISR_TXE)); + I2Cx->TXDR = data; +} diff --git a/src/ili9341.c b/src/ili9341.c new file mode 100644 index 0000000..03c4ec2 --- /dev/null +++ b/src/ili9341.c @@ -0,0 +1,919 @@ +#ifndef __ILI9341_H +#include "ili9341.h" +#endif + +#ifndef __DELAY_H +#include "delay.h" +#endif + +volatile uint16_t TFT_WIDTH=ILI9341_TFTWIDTH; +volatile uint16_t TFT_HEIGHT=ILI9341_TFTHEIGHT; + +#define swap(a,b) do { __typeof__ (a) _a = (a); __typeof__(b) _b = (b); a = _b; b = _a; } while(0) +#define min(a,b) ({ __typeof__ (a) _a = (a); __typeof__ (b) _b = (b); _a < _b ? _a : _b; }) +#define max(a,b) ({ __typeof__ (a) _a = (a); __typeof__ (b) _b = (b); _a > _b ? _a : _b; }) + +int16_t width(void) { return TFT_WIDTH; } +int16_t height(void) { return TFT_HEIGHT; } + +void ili9341_updatedisplayclip() { + _displayclipx1 = max(0, min(_clipx1 + _originx, width())); + _displayclipx2 = max(0, min(_clipx2 + _originx, width())); + _displayclipy1 = max(0, min(_clipy1 + _originy, height())); + _displayclipy2 = max(0, min(_clipy2 + _originy, height())); + _invisible = (_displayclipx1 == _displayclipx2 || _displayclipy1 == _displayclipy2); + _standard = (_displayclipx1 == 0) && (_displayclipx2 == TFT_WIDTH) && (_displayclipy1 == 0) && (_displayclipy2 == TFT_HEIGHT); +} + +void ili9341_setorigin(void) { + _originx = 0; + _originy = 0; + ili9341_updatedisplayclip(); + } + +/* +void getOrigin(int16_t *x, int16_t *y) { + *x = _originx; + *y = _originy; + } +*/ + +void ili9341_setcliprect() { + _clipx1 = 0; + _clipy1 = 0; + _clipx2 = TFT_WIDTH; + _clipy2 = TFT_HEIGHT; + ili9341_updatedisplayclip(); +} + +void ili9341_hard_init(void)//init hardware +{ + //GPIOA->BSRR = RST; + GPIOA->BSRR = DC; + GPIOA->BRR = CS; + +} + +void ili9341_hard_reset(void)//hard reset display +{ + /* + GPIOA->BSRR = RST; + delay_ms(200); + GPIOA->BRR = RST; + delay_ms(200); + GPIOA->BSRR = RST; + delay_ms(200); + */ +} + +void ili9341_spi_init(void)//set spi speed and settings +{ + //GPIOA->CRL=0x03433330; // set port for sw spi + //GPIOA->CRL |= 0x6; // set port for hw spi + GPIOA->BSRR=CS; +} + +void ili9341_spi_send(SPI_TypeDef * SPIx, uint16_t spi_data)//send spi data to display +{ + //GPIOA->BRR |= CS; + spi_buf=spi_data; + SPIx->CR2 |= SPI_CR2_TXEIE; +} + + +void ili9341_writecommand8(uint8_t com)//command write +{ + + SPI1->CR2 &= ~SPI_CR2_DS_3; + GPIOA->BRR = DC; + ili9341_spi_send(SPI1, (uint16_t)com); +} + + +void ili9341_writedata8(uint8_t data)//data write +{ + SPI1->CR2 &= ~SPI_CR2_DS_3; + GPIOA->BSRR = DC; + ili9341_spi_send(SPI1, data); +} + + +void ili9341_writedata16(uint16_t data) +{ + SPI1->CR2 |= SPI_CR2_DS_3; + GPIOA->BSRR = DC; + + ili9341_spi_send(SPI1, data); + +} + + +void color565toRGB14(uint16_t color, int16_t *r, int16_t *g, int16_t *b) +{ + *r = (color>>2)&0x3E00; + *g = (color<<3)&0x3F00; + *b = (color<<9)&0x3E00; +} + +uint16_t RGB14tocolor565(int16_t r, int16_t g, int16_t b) +{ + return (((r & 0x3E00) << 2) | ((g & 0x3F00) >>3) | ((b & 0x3E00) >> 9)); +} + + +void ili9341_setaddress(uint16_t x1,uint16_t y1,uint16_t x2,uint16_t y2)//set coordinate for print or other function +{ + ili9341_writecommand8(0x2A); + + ili9341_writedata8(x1>>8); + ili9341_writedata8(x1); + ili9341_writedata8(x2>>8); + ili9341_writedata8(x2); + + ili9341_writecommand8(0x2B); + + ili9341_writedata8(y1>>8); + ili9341_writedata8(y1); + ili9341_writedata8(y2); + ili9341_writedata8(y2); + + ili9341_writecommand8(0x2C);//meory write +} + + +/*void ili9341_hard_reset(void)//hard reset display +{ + rstport |=(1<>8)); + ili9341_writedata8((uint8_t)color); +} + + +//clear lcd and fill with color +void ili9341_clear(uint16_t color) +{ + uint16_t i,j; + ili9341_setaddress(0,0,TFT_WIDTH-1,TFT_HEIGHT-1); + + for(i=0;i=TFT_WIDTH) || (y3 < 0) || (y3 >=TFT_HEIGHT)) return; + //if((x3 >= TFT_WIDTH) || (y3 >=TFT_HEIGHT)) return; + ili9341_setaddress(x3,y3,x3+1,y3+1); + + ili9341_pushcolor(color); +} + + +//draw vertical line +void ili9341_drawvline(uint16_t x,uint16_t y,uint16_t h,uint16_t color)//basically we will see this line horizental if we see the display 320*240 +{ + if((x >=TFT_WIDTH) || (y >=TFT_HEIGHT)) return; + if((y+h-1)>=TFT_HEIGHT) + { + h=TFT_HEIGHT-y; + } + ili9341_setaddress(x,y,x,y+h-1); + while(h--) + { + ili9341_pushcolor(color); + } +} + + +//draw horizental line + +void ili9341_drawhline(uint16_t x,uint16_t y,uint16_t w,uint16_t color) +{ + if((x >=TFT_WIDTH) || (y >=TFT_HEIGHT || y < 0)) return; + if(x < 0) + { + w += x; + x=0; + } + if((x+w-1)>=TFT_WIDTH) + { + w=((uint16_t)(TFT_WIDTH-x)); + } + ili9341_setaddress(x,y,((uint16_t)(x+w-1)),y); + while(w--) + { + ili9341_pushcolor(color); + } +} + +void ili9341_drawline(int16_t x0, int16_t y0, int16_t x1, int16_t y1, uint16_t color) +{ + if (y0 == y1) { + if (x1 > x0) + { + ili9341_drawhline(x0, y0, x1 - x0 + 1, color); + } + else if (x1 < x0) + { + ili9341_drawhline(x1, y0, x0 - x1 + 1, color); + } + else { + ili9341_setaddress(x0, y0, x0, y0); + ili9341_pushcolor(color); + } + return; + } + else if (x0 == x1) + { + if (y1 > y0) + { + ili9341_drawvline(x0, y0, y1 - y0 + 1, color); + } + else + { + ili9341_drawvline(x0, y1, y0 - y1 + 1, color); + } + return; + } + + uint8_t steep = abs(y1 - y0) > abs(x1 - x0); + if (steep) + { + swap(x0, y0); + swap(x1, y1); + } + if (x0 > x1) + { + swap(x0, x1); + swap(y0, y1); + } + + int16_t dx, dy; + dx = x1 - x0; + dy = abs(y1 - y0); + + int16_t err = dx / 2; + int16_t ystep; + + if (y0 < y1) { + ystep = 1; + } else { + ystep = -1; + } + + int16_t xbegin = x0; + if (steep) + { + for (; x0<=x1; x0++) + { + err -= dy; + if (err < 0) + { + int16_t len = x0 - xbegin; + if (len) + { + ili9341_drawvline(y0, xbegin, len + 1, color); + } + else + { + ili9341_setaddress(y0, x0, y0, x0); + ili9341_pushcolor(color); + } + xbegin = x0 + 1; + y0 += ystep; + err += dx; + } + } + if (x0 > xbegin + 1) + { + ili9341_drawvline(y0, xbegin, x0 - xbegin, color); + } + } + else + { + for (; x0<=x1; x0++) + { + err -= dy; + if (err < 0) + { + int16_t len = x0 - xbegin; + if (len) + { + ili9341_drawhline(xbegin, y0, len + 1, color); + } + else + { + ili9341_setaddress(x0, y0, x0, y0); + ili9341_pushcolor(color); + } + xbegin = x0 + 1; + y0 += ystep; + err += dx; + } + } + if (x0 > xbegin + 1) + { + ili9341_drawhline(xbegin, y0, x0 - xbegin, color); + } + } +} + +void ili9341_drawcirclehelper(int16_t x0, int16_t y0, int16_t r,uint8_t cornername, uint16_t color) +{ + int16_t f = 1 - r; + int16_t ddF_x = 1; + int16_t ddF_y = -2 * r; + int16_t x = 0; + int16_t y = r; + + while (x < y) + { + if (f >= 0) + { + y--; + ddF_y += 2; + f += ddF_y; + } + x++; + ddF_x += 2; + f += ddF_x; + if (cornername & 0x4) + { + ili9341_drawpixel(x0 + x, y0 + y, color); + ili9341_drawpixel(x0 + y, y0 + x, color); + } + if (cornername & 0x2) + { + ili9341_drawpixel(x0 + x, y0 - y, color); + ili9341_drawpixel(x0 + y, y0 - x, color); + } + if (cornername & 0x8) + { + ili9341_drawpixel(x0 - y, y0 + x, color); + ili9341_drawpixel(x0 - x, y0 + y, color); + } + if (cornername & 0x1) + { + ili9341_drawpixel(x0 - y, y0 - x, color); + ili9341_drawpixel(x0 - x, y0 - y, color); + } + } +} + +void ili9341_fillcirclehelper(int16_t x0, int16_t y0, int16_t r,uint8_t cornername, int16_t delta,uint16_t color) +{ + int16_t f = 1 - r; + int16_t ddF_x = 1; + int16_t ddF_y = -2 * r; + int16_t x = 0; + int16_t y = r; + + while (x < y) + { + if (f >= 0) + { + y--; + ddF_y += 2; + f += ddF_y; + } + x++; + ddF_x += 2; + f += ddF_x; + + if (cornername & 0x1) + { + ili9341_drawvline(x0 + x, y0 - y, 2 * y + 1 + delta, color); + ili9341_drawvline(x0 + y, y0 - x, 2 * x + 1 + delta, color); + } + if (cornername & 0x2) + { + ili9341_drawvline(x0 - x, y0 - y, 2 * y + 1 + delta, color); + ili9341_drawvline(x0 - y, y0 - x, 2 * x + 1 + delta, color); + } + } +} + +void ili9341_drawrect(uint16_t x, uint16_t y, uint16_t w, uint16_t h,uint16_t color) +{ + ili9341_drawhline(x,y,w,color); + ili9341_drawhline(x,y+h-1,w,color); + ili9341_drawvline(x,y,h,color); + ili9341_drawvline(x+w-1,y,h,color); + /* + HLine(x, y, w, color); + HLine(x, y + h - 1, w, color); + VLine(x, y, h, color); + VLine(x + w - 1, y, h, color); + writecommand_last(ILI9341_NOP); + endSPITransaction(); + */ +} + +void ili9341_fillrect(uint16_t x,uint16_t y,uint16_t w,uint16_t h,uint16_t color) +{ + if((x >=TFT_WIDTH) || (y >=TFT_HEIGHT)) + { + return; + } + if((x+w-1)>=TFT_WIDTH) + { + w=TFT_WIDTH-x; + } + if((y+h-1)>=TFT_HEIGHT) + { + h=TFT_HEIGHT-y; + } + + ili9341_setaddress(x, y, x+w-1, y+h-1); + + for(y=h; y>0; y--) + { + for(x=w; x>0; x--) + { + ili9341_pushcolor(color); + } + } +} + +void ili9341_drawroundrect(int16_t x, int16_t y, int16_t w, int16_t h,int16_t r, uint16_t color) +{ + // smarter version + ili9341_drawhline(x + r, y, w - 2 * r, color); // Top + ili9341_drawhline(x + r, y + h - 1, w - 2 * r, color); // Bottom + ili9341_drawvline(x, y + r, h - 2 * r, color); // Left + ili9341_drawvline(x + w - 1, y + r, h - 2 * r, color); // Right + // draw four corners + ili9341_drawcirclehelper(x + r, y + r, r, 1, color); + ili9341_drawcirclehelper(x + w - r - 1, y + r, r, 2, color); + ili9341_drawcirclehelper(x + w - r - 1, y + h - r - 1, r, 4, color); + ili9341_drawcirclehelper(x + r, y + h - r - 1, r, 8, color); +} + +// Fill a rounded rectangle +void ili9341_fillroundrect(int16_t x, int16_t y, int16_t w, int16_t h,int16_t r, uint16_t color) +{ + // smarter version + ili9341_fillrect(x + r, y, w - 2 * r, h, color); + + // draw four corners + ili9341_fillcirclehelper(x + w - r - 1, y + r, r, 1, h - 2 * r - 1, color); + ili9341_fillcirclehelper(x + r, y + r, r, 2, h - 2 * r - 1, color); +} + +void ili9341_drawhollowcircle(uint16_t X, uint16_t Y, uint16_t radius, uint16_t color) +{ + int16_t x = radius-1; + int16_t y = 0; + int16_t dx = 1; + int16_t dy = 1; + int16_t err = dx - (radius << 1); + + while (x >= y) + { + ili9341_drawpixel(X + x, Y + y, color); + ili9341_drawpixel(X + y, Y + x, color); + ili9341_drawpixel(X - y, Y + x, color); + ili9341_drawpixel(X - x, Y + y, color); + ili9341_drawpixel(X - x, Y - y, color); + ili9341_drawpixel(X - y, Y - x, color); + ili9341_drawpixel(X + y, Y - x, color); + ili9341_drawpixel(X + x, Y - y, color); + + if (err <= 0) + { + y++; + err += dy; + dy += 2; + } + + if (err > 0) + { + x--; + dx += 2; + err += (-radius << 1) + dx; + } + } +} + + +void ili9341_drawfilledcircle(uint16_t X, uint16_t Y, uint16_t radius, uint16_t color) +{ + + int16_t x = radius; + int16_t y = 0; + int16_t xChange = 1 - (radius << 1); + int16_t yChange = 0; + int16_t radiusError = 0; + + while (x >= y) + { + for (uint16_t i = X - x; i <= X + x; i++) + { + ili9341_drawpixel(i, Y + y,color); + ili9341_drawpixel(i, Y - y,color); + } + + for (int i = X - y; i <= X + y; i++) + { + ili9341_drawpixel(i, Y + x,color); + ili9341_drawpixel(i, Y - x,color); + } + + y++; + radiusError += yChange; + yChange += 2; + + if (((radiusError << 1) + xChange) > 0) + { + x--; + radiusError += xChange; + xChange += 2; + } + } +} + +void ili9341_drawtriangle(int16_t x0, int16_t y0, int16_t x1, int16_t y1, int16_t x2, int16_t y2, uint16_t color) +{ + ili9341_drawline(x0, y0, x1, y1, color); + ili9341_drawline(x1, y1, x2, y2, color); + ili9341_drawline(x2, y2, x0, y0, color); +} + +void ili9341_filltriangle(int16_t x0, int16_t y0,int16_t x1, int16_t y1,int16_t x2, int16_t y2, uint16_t color) +{ + int16_t a, b, y, last; + + // Sort coordinates by Y order (y2 >= y1 >= y0) + if (y0 > y1) { + swap(y0, y1); swap(x0, x1); + } + if (y1 > y2) { + swap(y2, y1); swap(x2, x1); + } + if (y0 > y1) { + swap(y0, y1); swap(x0, x1); + } + + if(y0 == y2) { // Handle awkward all-on-same-line case as its own thing + a = b = x0; + if(x1 < a) a = x1; + else if(x1 > b) b = x1; + if(x2 < a) a = x2; + else if(x2 > b) b = x2; + ili9341_drawhline(a, y0, b-a+1, color); + return; + } + + int32_t + dx01 = x1 - x0, + dy01 = y1 - y0, + dx02 = x2 - x0, + dy02 = y2 - y0, + dx12 = x2 - x1, + dy12 = y2 - y1, + sa = 0, + sb = 0; + + // For upper part of triangle, find scanline crossings for segments + // 0-1 and 0-2. If y1=y2 (flat-bottomed triangle), the scanline y1 + // is included here (and second loop will be skipped, avoiding a /0 + // error there), otherwise scanline y1 is skipped here and handled + // in the second loop...which also avoids a /0 error here if y0=y1 + // (flat-topped triangle). + if(y1 == y2) last = y1; // Include y1 scanline + else last = y1-1; // Skip it + + for(y=y0; y<=last; y++) + { + a = x0 + sa / dy01; + b = x0 + sb / dy02; + sa += dx01; + sb += dx02; + /* longhand: + a = x0 + (x1 - x0) * (y - y0) / (y1 - y0); + b = x0 + (x2 - x0) * (y - y0) / (y2 - y0); + */ + if(a > b) swap(a,b); + ili9341_drawhline(a, y, b-a+1, color); + } + + // For lower part of triangle, find scanline crossings for segments + // 0-2 and 1-2. This loop is skipped if y1=y2. + sa = dx12 * (y - y1); + sb = dx02 * (y - y0); + for(; y<=y2; y++) + { + a = x1 + sa / dy12; + b = x0 + sb / dy02; + sa += dx12; + sb += dx02; + /* longhand: + a = x1 + (x2 - x1) * (y - y1) / (y2 - y1); + b = x0 + (x2 - x0) * (y - y0) / (y2 - y0); + */ + if(a > b) swap(a,b); + ili9341_drawhline(a, y, b-a+1, color); + } +} + +void ili9341_fillrecthgradient(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color1, uint16_t color2) +{ + x += _originx; + y += _originy; + + // Rectangular clipping + if ((x >= _displayclipx2) || (y >= _displayclipy2)) + { + return; + } + if (x < _displayclipx1) + { + w -= (_displayclipx1 - x); + x = _displayclipx1; + } + if (y < _displayclipy1) + { + h -= (_displayclipy1 - y); + y = _displayclipy1; + } + if ((x + w - 1) >= _displayclipx2) + { + w = _displayclipx2 - x; + } + if ((y + h - 1) >= _displayclipy2) + { + h = _displayclipy2 - y; + } + + int16_t r1, g1, b1, r2, g2, b2, dr, dg, db, r, g, b; + uint16_t color; + color565toRGB14(color1, &r1, &g1, &b1); + color565toRGB14(color2, &r2, &g2, &b2); + dr = (r2 - r1) / w; + dg = (g2 - g1) / w; + db = (b2 - b1) / w; + r = r1; + g = g1; + b = b1; + ili9341_setaddress(x, y, x + w - 1, y + h - 1); + for (y = h; y > 0; y--) + { + for (x = w; x > 1; x--) + { + color = RGB14tocolor565(r, g, b); + ili9341_pushcolor(color); + r += dr; + g += dg; + b += db; + } + color = RGB14tocolor565(r, g, b); + ili9341_pushcolor(color); + r = r1; + g = g1; + b = b1; + } +} + + + +void ili9341_fillrectvgradient(int16_t x, int16_t y, int16_t w, int16_t h,uint16_t color1, uint16_t color2) +{ + x += _originx; + y += _originy; + + // Rectangular clipping + if ((x >= _displayclipx2) || (y >= _displayclipy2)) + { + return; + } + if (x < _displayclipx1) + { + w -= (_displayclipx1 - x); + x = _displayclipx1; + } + if (y < _displayclipy1) + { + h -= (_displayclipy1 - y); + y = _displayclipy1; + } + if ((x + w - 1) >= _displayclipx2) + { + w = _displayclipx2 - x; + } + if ((y + h - 1) >= _displayclipy2) + { + h = _displayclipy2 - y; + } + + int16_t r1, g1, b1, r2, g2, b2, dr, dg, db, r, g, b; + color565toRGB14(color1, &r1, &g1, &b1); + color565toRGB14(color2, &r2, &g2, &b2); + dr = (r2 - r1) / h; + dg = (g2 - g1) / h; + db = (b2 - b1) / h; + r = r1; + g = g1; + b = b1; + + ili9341_setaddress(x, y, x + w - 1, y + h - 1); + for (y = h; y > 0; y--) + { + uint16_t color = RGB14tocolor565(r, g, b); + + for (x = w; x > 1; x--) + { + ili9341_pushcolor(color); + } + ili9341_pushcolor(color); + r += dr; + g += dg; + b += db; + } +} + + +void ili9341_setrotation(uint8_t m) +{ + uint8_t rotation; + ili9341_writecommand8(0x36); + rotation=m%4; + switch (rotation) + { + case 0: + ili9341_writedata8(0x40|0x08); + TFT_WIDTH = 240; + TFT_HEIGHT = 320; + break; + case 1: + ili9341_writedata8(0x20|0x08); + TFT_WIDTH = 320; + TFT_HEIGHT = 240; + break; + case 2: + ili9341_writedata8(0x80|0x08); + TFT_WIDTH = 240; + TFT_HEIGHT = 320; + break; + case 3: + ili9341_writedata8(0x40|0x80|0x20|0x08); + TFT_WIDTH = 320; + TFT_HEIGHT = 240; + break; + } + ili9341_updatedisplayclip(); + ili9341_setorigin(); + ili9341_setcliprect(); +} + diff --git a/src/ili9341gfx.c b/src/ili9341gfx.c new file mode 100644 index 0000000..979f68c --- /dev/null +++ b/src/ili9341gfx.c @@ -0,0 +1,675 @@ +#ifndef __ILI9341_H +#include "ili9341.h" +#endif + +#ifndef __ILI9341_GFX_H +#include "ili9341gfx.h" +#endif + +#include "glcdfont.h" + +extern volatile uint16_t TFT_WIDTH; +extern volatile uint16_t TFT_HEIGHT; + +volatile uint16_t cursor_x; +volatile uint16_t cursor_y; +volatile uint16_t textcolor; +volatile uint16_t textbgcolor; +volatile uint8_t textsize; +uint16_t vsetx,vsety,vactualx,vactualy,isetx,isety,iactualx,iactualy; +uint8_t wrap=0; +ILI9341_t3_font_t font; + +void backuplocationvset(void)//backing up vset data start location to print next vset data in exact location +{ + vsetx=cursor_x; + vsety=cursor_y; +} + + +void backuplocationvactual(void)//backing up vactual data start location to print next vactual data in exact location +{ + vactualx=cursor_x; + vactualy=cursor_y; +} + +void backuplocationiset(void)//backing up iset data start location to print next iset data in exact location +{ + isetx=cursor_x; + isety=cursor_y; +} + + +void backuplocationiactual(void)//backing up iactual data start location to print next iactual data in exact location +{ + iactualx=cursor_x; + iactualy=cursor_y; +} + +static inline uint32_t fetchbit(const uint8_t *p, uint32_t index) +{ + return (p[index >> 3] & (0x80 >> (index & 7))); +} + +static uint32_t fetchbits_unsigned(const uint8_t *p, uint32_t index, uint32_t required) +{ + uint32_t val; + uint8_t *s = (uint8_t *)&p[index>>3]; + +#ifdef UNALIGNED_IS_SAFE + val = *(uint32_t *)s; // read 4 bytes - unaligned is ok + val = __builtin_bswap32(val); // change to big-endian order +#else + val = s[0] << 24; + val |= (s[1] << 16); + val |= (s[2] << 8); + val |= s[3]; +#endif + val <<= (index & 7); // shift out used bits + if (32 - (index & 7) < required) { // need to get more bits + val |= (s[4] >> (8 - (index & 7))); + } + val >>= (32-required); // right align the bits + return val; +} + +static uint32_t fetchbits_signed(const uint8_t *p, uint32_t index, uint32_t required) +{ + uint32_t val = fetchbits_unsigned(p, index, required); + if (val & (1 << (required - 1))) { + return (int32_t)val - (1 << required); + } + return (int32_t)val; +} + +void ili9341_setfont(const ILI9341_t3_font_t f) +{ + font = f; +} + + +void ili9341_setcursor(uint16_t x,uint16_t y)//set cursor at desired location to print data +{ + cursor_x=x; + cursor_y=y; +} + +void ili9341_settextcolor(uint16_t x,uint16_t y)//set text colour and text background colour +{ + textcolor=x; + textbgcolor=y; +} + +void ili9341_settextsize(uint8_t s) +{ + if(s>8) return; + textsize=(s>0) ? s: 1;//this operation means if s0 greater than 0,then s=s,else s=1 +} + + +void ili9341_drawcharbits(int16_t x, int16_t y, char c,uint16_t fgcolor, uint16_t bgcolor, uint8_t size_x,uint8_t size_y) +{ + if ((x >= TFT_WIDTH) || (y >= TFT_HEIGHT) || ((x + 6 * size_x - 1) < 0) || ((y + 8 * size_y - 1) < 0)) + { + return; + } + + if (fgcolor == bgcolor) + { + // This transparent approach is only about 20% faster + if ((size_x == 1) && (size_y == 1)) + { + uint8_t mask = 0x01; + int16_t xoff, yoff; + for (yoff = 0; yoff < 8; yoff++) + { + uint8_t line = 0; + for (xoff = 0; xoff < 5; xoff++) + { + if (glcdfont[c * 5 + xoff] & mask) + { + line |= 1; + } + line <<= 1; + } + line >>= 1; + xoff = 0; + while (line) + { + if (line == 0x1F) + { + ili9341_drawhline(x + xoff, y + yoff, 5, fgcolor); + break; + } + else if (line == 0x1E) + { + ili9341_drawhline(x + xoff, y + yoff, 4, fgcolor); + break; + } + else if ((line & 0x1C) == 0x1C) + { + ili9341_drawhline(x + xoff, y + yoff, 3, fgcolor); + line <<= 4; + xoff += 4; + } + else if ((line & 0x18) == 0x18) + { + ili9341_drawhline(x + xoff, y + yoff, 2, fgcolor); + line <<= 3; + xoff += 3; + } + else if ((line & 0x10) == 0x10) + { + ili9341_drawpixel(x + xoff, y + yoff, fgcolor); + line <<= 2; + xoff += 2; + } + else + { + line <<= 1; + xoff += 1; + } + } + mask = mask << 1; + } + } + else + { + uint8_t mask = 0x01; + int16_t xoff, yoff; + for (yoff = 0; yoff < 8; yoff++) + { + uint8_t line = 0; + for (xoff = 0; xoff < 5; xoff++) + { + if (glcdfont[c * 5 + xoff] & mask) + { + line |= 1; + } + line <<= 1; + } + line >>= 1; + xoff = 0; + while (line) + { + if (line == 0x1f) + { + ili9341_fillrect(x + xoff * size_x, y + yoff * size_y, 5 * size_x, size_y,fgcolor); + break; + } + else if (line == 0x1e) + { + ili9341_fillrect(x + xoff * size_x, y + yoff * size_y, 4 * size_x, size_y,fgcolor); + break; + } + else if ((line & 0x1c) == 0x1c) + { + ili9341_fillrect(x + xoff * size_x, y + yoff * size_y, 3 * size_x, size_y,fgcolor); + line <<= 4; + xoff += 4; + } + else if ((line & 0x18) == 0x18) + { + ili9341_fillrect(x + xoff * size_x, y + yoff * size_y, 2 * size_x, size_y,fgcolor); + line <<= 3; + xoff += 3; + } + else if ((line & 0x10) == 0x10) + { + ili9341_fillrect(x + xoff * size_x, y + yoff * size_y, size_x, size_y,fgcolor); + line <<= 2; + xoff += 2; + } + else + { + line <<= 1; + xoff += 1; + } + } + mask = mask << 1; + } + } + } + else + { + // This solid background approach is about 5 time faster + uint8_t xc, yc; + uint8_t xr, yr; + uint8_t mask = 0x01; + uint16_t color; + + // We need to offset by the origin. + x += _originx; + y += _originy; + int16_t x_char_start = x; // remember our X where we start outputting... + + if ((x >= _displayclipx2) || (y >= _displayclipy2) || ((x + 6 * size_x - 1) < _displayclipx1) || ((y + 8 * size_y - 1) <_displayclipy1)) + { + return; + } + // need to build actual pixel rectangle we will output into. + int16_t y_char_top = y; // remember the y + int16_t w = 6 * size_x; + int16_t h = 8 * size_y; + + if (x < _displayclipx1) + { + w -= (_displayclipx1 - x); + x = _displayclipx1; + } + if ((x + w - 1) >= _displayclipx2) + { + w = _displayclipx2 - x; + } + if (y < _displayclipy1) + { + h -= (_displayclipy1 - y); + y = _displayclipy1; + } + if ((y + h - 1) >= _displayclipy2) + { + h = _displayclipy2 - y; + } + ili9341_setaddress(x, y, x + w - 1, y + h - 1); + y = y_char_top; // restore the actual y. + for (yc = 0; (yc < 8) && (y < _displayclipy2); yc++) + { + for (yr = 0; (yr < size_y) && (y < _displayclipy2); yr++) + { + x = x_char_start; // get our first x position... + if (y >= _displayclipy1) + { + for (xc = 0; xc < 5; xc++) + { + if (glcdfont[c * 5 + xc] & mask) + { + color = fgcolor; + } + else + { + color = bgcolor; + } + for (xr = 0; xr < size_x; xr++) + { + if ((x >= _displayclipx1) && (x < _displayclipx2)) + { + ili9341_pushcolor(color); + } + x++; + } + } + for (xr = 0; xr < size_x; xr++) + { + if ((x >= _displayclipx1) && (x < _displayclipx2)) + { + ili9341_pushcolor(bgcolor); + } + x++; + } + } + y++; + } + mask = mask << 1; + } + } +} + + + + +void ili9341_drawfontbits(uint8_t opaque, uint32_t bits, uint32_t numbits, int32_t x, int32_t y, uint32_t repeat) { + if (bits == 0) { + if (opaque) { + ili9341_fillrect(x, y, numbits, repeat, textbgcolor); + } + } + else + { + int32_t x1 = x; + uint32_t n = numbits; + int16_t w; + int16_t bgw; + + w = 0; + bgw = 0; + + do { + n--; + if (bits & (1 << n)) { + if (bgw > 0) { + if (opaque) { + ili9341_fillrect(x1 - bgw, y, bgw, repeat, textbgcolor); + } + bgw = 0; + } + w++; + } + else + { + if (w > 0) { + ili9341_fillrect(x1 - w, y, w, repeat, textcolor); + w = 0; + } + bgw++; + } + x1++; + } + while (n > 0); + + if (w > 0) + { + ili9341_fillrect(x1 - w, y, w, repeat, textcolor); + } + + if (bgw > 0) + { + if (opaque) + { + ili9341_fillrect(x1 - bgw, y, bgw, repeat, textbgcolor); + } + } + } +} + +void ili9341_drawfontchar(char c) { + uint32_t bitoffset; + const uint8_t *data; + + if (c >= font.index1_first && c <= font.index1_last) { + bitoffset = c - font.index1_first; + bitoffset *= font.bits_index; + } + else if (c >= font.index2_first && c <= font.index2_last) + { + bitoffset = + c - font.index2_first + font.index1_last - font.index1_first + 1; + bitoffset *= font.bits_index; + } + else if (font.unicode) + { + return; // TODO: implement sparse unicode + } + else + { + return; + } + data = font.data + fetchbits_unsigned(font.index, bitoffset, font.bits_index); + + uint32_t encoding = fetchbits_unsigned(data, 0, 3); + if (encoding != 0) + { + return; + } + uint32_t width = fetchbits_unsigned(data, 3, font.bits_width); + bitoffset = font.bits_width + 3; + uint32_t height = fetchbits_unsigned(data, bitoffset, font.bits_height); + bitoffset += font.bits_height; + int32_t xoffset = fetchbits_signed(data, bitoffset, font.bits_xoffset); + bitoffset += font.bits_xoffset; + int32_t yoffset = fetchbits_signed(data, bitoffset, font.bits_yoffset); + bitoffset += font.bits_yoffset; + uint32_t delta = fetchbits_unsigned(data, bitoffset, font.bits_delta); + bitoffset += font.bits_delta; + if (cursor_x < 0) + { + cursor_x = 0; + } + int32_t origin_x = cursor_x + xoffset; + if (origin_x < 0) { + cursor_x -= xoffset; + origin_x = 0; + } + if (origin_x + (int)width >TFT_WIDTH) { + if (!wrap) + return; + origin_x = 0; + if (xoffset >= 0) { + cursor_x = 0; + } + else + { + cursor_x = -xoffset; + } + cursor_y += font.line_space; + } + if (cursor_y >= TFT_HEIGHT) + { + return; + } + // vertically, the top and/or bottom can be clipped + int32_t origin_y = cursor_y + font.cap_height - height - yoffset; + + // TODO: compute top skip and number of lines + int32_t linecount = height; + // uint32_t loopcount = 0; + int32_t y = origin_y; + uint8_t opaque; + textbgcolor != textcolor ? opaque=1 : (opaque=0); + + // Going to try a fast Opaque method which works similar to drawChar, which is + // near the speed of writerect + if (!opaque) { + while (linecount > 0) + { + uint32_t n = 1; + if (fetchbit(data, bitoffset++) != 0) + { + n = fetchbits_unsigned(data, bitoffset, 3) + 2; + bitoffset += 3; + } + uint32_t x = 0; + do + { + int32_t xsize = width - x; + if (xsize > 32) + { + xsize = 32; + } + + uint32_t bits = fetchbits_unsigned(data, bitoffset, xsize); + ili9341_drawfontbits(opaque, bits, xsize, origin_x + x, y, n); + bitoffset += xsize; + x += xsize; + } + while (x < width); + + y += n; + linecount -= n; + } + } // 1bpp + // opaque + else + { + // Now opaque mode... + // Now write out background color for the number of rows above the above the + // character + // figure out bounding rectangle... + // In this mode we need to update to use the offset and bounding rectangles + // as we are doing it it direct. + // also update the Origin + uint16_t cursor_x_origin = cursor_x + _originx; + uint16_t cursor_y_origin = cursor_y + _originy; + origin_x += _originx; + origin_y += _originy; + + uint16_t start_x = (origin_x < cursor_x_origin) ? origin_x : cursor_x_origin; + if (start_x < 0) + { + start_x = 0; + } + uint16_t start_y = (origin_y < cursor_y_origin) ? origin_y : cursor_y_origin; + if (start_y < 0) + { + start_y = 0; + } + uint16_t end_x = cursor_x_origin + delta; + if ((origin_x + (int)width) > end_x) + { + end_x = origin_x + (int)width; + } + if (end_x >= _displayclipx2) + { + end_x = _displayclipx2; + } + uint16_t end_y = cursor_y_origin + font.line_space; + if ((origin_y + (int)height) > end_y) + { + end_y = origin_y + (int)height; + } + if (end_y >= _displayclipy2) + { + end_y = _displayclipy2; + } + end_x--; // setup to last one we draw + end_y--; + uint16_t start_x_min = (start_x >= _displayclipx1) ? start_x : _displayclipx1; + uint16_t start_y_min = (start_y >= _displayclipy1) ? start_y : _displayclipy1; + + // See if anything is in the display area. + + if ((end_x < _displayclipx1) || (start_x >= _displayclipx2) || (end_y < _displayclipy1) || (start_y >= _displayclipy2)) + { + cursor_x += delta; // could use goto or another indent level... + return; + } + + //setAddr(start_x, start_y_min, end_x, end_y); + //writecommand_cont(ILI9341_RAMWR); + ili9341_setaddress(start_x, start_y, end_x, end_y); + uint16_t screen_y = start_y_min; + uint16_t screen_x; + + // Clear above character + while (screen_y < origin_y) + { + for (screen_x = start_x_min; screen_x <= end_x; screen_x++) { + ili9341_pushcolor(textbgcolor); + } + screen_y++; + } + + + // Now lets process each of the data lines. + screen_y = origin_y; + while (linecount > 0) + { + uint32_t b = fetchbit(data, bitoffset++); + uint32_t n; + if (b == 0) + { + n = 1; + } + else + { + n = fetchbits_unsigned(data, bitoffset, 3) + 2; + bitoffset += 3; + } + uint32_t bitoffset_row_start = bitoffset; + while (n--) + { + // do some clipping here. + bitoffset = bitoffset_row_start; // we will work through these bits + // maybe multiple times + // We need to handle case where some of the bits may not be visible, + // but we still need to + // read through them + // _displayclipx1, _displayclipx2); + if ((screen_y >= _displayclipy1) && (screen_y < _displayclipy2)) + { + for (screen_x = start_x; screen_x < origin_x; screen_x++) + { + if ((screen_x >= _displayclipx1) && (screen_x < _displayclipx2)) + { + ili9341_pushcolor(textbgcolor); + } + } + } + uint32_t x = 0; + screen_x = origin_x; + do + { + uint32_t xsize = width - x; + if (xsize > 32) + { + xsize = 32; + } + uint32_t bits = fetchbits_unsigned(data, bitoffset, xsize); + uint32_t bit_mask = 1 << (xsize - 1); + if ((screen_y >= _displayclipy1) && (screen_y < _displayclipy2)) + { + while (bit_mask) + { + if ((screen_x >= _displayclipx1) && (screen_x < _displayclipx2)) + { + ili9341_pushcolor((bits & bit_mask) ? textcolor : textbgcolor); + } + bit_mask = bit_mask >> 1; + screen_x++; // Current actual screen X + } + bitoffset += xsize; + } + x += xsize; + } + while (x < width); + if ((screen_y >= _displayclipy1) && (screen_y < _displayclipy2)) + { + // output bg color and right hand side + while (screen_x++ <= end_x) + { + ili9341_pushcolor(textbgcolor); + } + } + screen_y++; + linecount--; + } + } + + screen_x = (end_y + 1 - screen_y) * (end_x + 1 - start_x_min); // How many bytes we need to still output + while(screen_x-- >1) + { + ili9341_pushcolor(textbgcolor); + } + ili9341_pushcolor(textbgcolor); + } + // 1bpp + // Increment to setup for the next character. + cursor_x += delta; +} + +void ili9341_drawchar(char c) +{ + if (c == '\n') + { + cursor_y += textsize*8; + cursor_x = 0; + } + else if (c == '\r') + { + } + else { + ili9341_drawcharbits(cursor_x, cursor_y, c, textcolor, textbgcolor, textsize, textsize); + cursor_x += textsize*6; + if (wrap && (cursor_x > (TFT_WIDTH - textsize*6))) + { + cursor_y += textsize*8; + cursor_x = 0; + } + } +} + + +void ili9341_out(char *strn) { + register char c; + while((c= *strn++)) { + if(font.index!=0) + { + ili9341_drawfontchar(c); + } + else + { + ili9341_drawchar(c); + } + } +} + + diff --git a/src/main.c b/src/main.c new file mode 100644 index 0000000..5302428 --- /dev/null +++ b/src/main.c @@ -0,0 +1,1996 @@ +/* + * GPS disciplined OCXO with SI5351 frequency generator + * + */ + +// ---------------------------------------------------------------------------- + +#include +#include +#include +#include +#include +#include +#include +#include +#include "ili9341.h" +#include "ili9341gfx.h" +#include "font_Arial.h" +#include "glcdfont.h" +#include "delay.h" +#include "i2c.h" +#include "si5351a.h" +#include "24aaxx.h" + +#define LONGWEEKDAYS +#define LONGMONTHS + +#define IO_RX_BUFLEN ((rx_buf.in - rx_buf.out)) + +#define OCXO_LOCK (GPIOA->IDR & 0x800) +#define PHASE_B (GPIOA->IDR & 0x2) +#define PHASE_A (GPIOA->IDR & 0x8) +#define KEY (GPIOA->IDR & 0x1) + + +static volatile uint8_t tx_restart=1; +static volatile uint8_t rx_finished=0; +volatile uint8_t update_freq=0; +volatile uint16_t btn_hb=0; +volatile uint8_t ocxo_lock=0; +volatile uint8_t enc_event=0; +volatile int8_t enc_delta; + +/* +volatile int16_t encoderPosition; +const int8_t encoderStates[16] = {0,-1,1,0,1,0,0,-1,-1,0,0,1,0,1,-1,0}; +volatile uint8_t lastState=3; +volatile int32_t position; +*/ + +volatile uint8_t keyfunc=0xaa; +volatile uint8_t startup=1; +volatile uint16_t spi_buf; +volatile uint8_t i2c_rx_buf[10]; +volatile uint8_t i2c_tx_buf[10]; +volatile uint8_t i2c_index=0,i2c_count=0; +static int8_t enc_last; +uint32_t frequency_tmp[] = { 10,10,10,10 }; +uint8_t out_stat_tmp=0xf; +uint8_t usart_in_buf[513]; +#define Buffer_Size 64 + +char GGA_Buffer[Buffer_Size]; /* save GGA string */ +char RMC_Buffer[Buffer_Size]; +char GSA_Buffer[Buffer_Size]; +char GLL_Buffer[Buffer_Size]; +uint8_t GGA_Pointers[20]; /* to store instances of ',' */ +uint8_t RMC_Pointers[20]; +uint8_t GSA_Pointers[20]; +uint8_t GLL_Pointers[20]; +volatile char GGA_code[3]; + +volatile uint16_t GGA_Index, CommaCounter; + +uint8_t IsItGGAString = 0, + IsItRMCString=0, + IsItGSAString=0, + IsItGLLString=0, + flag1= 0, + flag2= 0; + + + +void RCC_Configuration(void); + +struct buf_str +{ + uint8_t in; + uint8_t out; + uint8_t buf[255]; +}; + +static struct buf_str rx_buf = { 0,0,{0} }; +static struct buf_str tx_buf = { 0,0,{0} }; + + + +struct ZoneInfo { + int8_t time; + char zone[4]; +}; + +struct rmc_data { + uint8_t sec; + uint8_t min; + uint8_t hour; + uint8_t day; + uint8_t month; + uint8_t wday; + uint16_t year; + //uint8_t gps_cs; + //uint8_t calc_cs; +}; + +struct gsa_data +{ + uint8_t fix; + uint8_t count; + uint16_t pdop; + uint16_t hdop; + uint16_t vdop; + uint8_t sats[13]; +}; + +struct gga_data +{ + uint32_t time; + uint8_t lat_deg; + uint8_t lat_min; + uint32_t lat_sec; + uint8_t long_deg; + uint8_t long_min; + uint32_t long_sec; + uint8_t lat_hemi; + uint8_t long_hemi; + uint16_t altitude; + uint32_t latitude; + uint32_t longitude; + uint8_t sat_num; +}; + +char * gpslock[] = { + " GPS NoLock", + " GPS Lock " +}; + +char * ocxolock[] = { + " OCXO NoLock", + " OCXO Lock " +}; + +char * lat_hemi[] = { + "N", + "S" +}; + +char * long_hemi[] = { + "E", + "W" +}; + +#ifdef LONGMONTHS +char * months[] = { + "January", + "February", + "March", + "April", + "May", + "June", + "July", + "August", + "September", + "October", + "November", + "December" +}; +#endif + +#ifdef SHORTMONTHS +char * months[] = { + "Jan", + "Feb", + "Mar", + "Apr", + "May", + "Jun", + "Jul", + "Aug", + "Sep", + "Oct", + "Nov", + "Dec" +}; +#endif + + +#ifdef LONGWEEKDAYS +char * weekdays[] = { + "Sunday", + "Monday", + "Tuesday", + "Wednesday", + "Thursday", + "Friday", + "Saturday" +}; +#endif + +#ifdef SHORTWEEKDAYS +char * weekdays[] = { + "Sun", + "Mon", + "Tue", + "Wed", + "Thu", + "Fri", + "Sat" +}; +#endif + +uint8_t _8mhz[] = { +0xb5, 0x62, // sync 1 & 2 +0x6, 0x31, // class & id for TP5 setting +0x20, 0x00, // payload length (32 bytes) +0x0, // TP selection +0x1, // reserved 0 +0x0, 0x0, // reserved 1 +0x32, 0x0, // antenna cable delay in ns (int16_t) +0x0, 0x0, // RF group delay in ns +0x1, 0x0, 0x0, 0x0, // frequency unlocked +0x0, 0x12, 0x7a, 0x0, // frequency locked +0x68, 0x9e, 0x9e, 0x7, // pulse width unlocked +0x0, 0x0, 0x0, 0x80, // pulse width locked +0x0, 0x0, 0x0, 0x0, // user config delay in ns +0xef, 0x0, 0x0, 0x0 // flags +}; + +uint8_t _4mhz[] = { // !!! byte-order little endian !!! +0xb5, 0x62, // sync 1 & 2 +0x6, 0x31, // class & id for TP5 setting +0x20, 0x00, // payload length (32 bytes) +0x0, // TP selection +0x1, // reserved 0 +0x0, 0x0, // reserved 1 +0x32, 0x0, // antenna cable delay in ns (int16_t) +0x0, 0x0, // RF group delay in ns +0x0, 0x0, 0x0, 0x0, // frequency unlocked +0x0, 0x9, 0x3d, 0x0, // frequency locked +0x68, 0x9e, 0x9e, 0x7, // pulse width unlocked +0x0, 0x0, 0x0, 0x80, // pulse width locked +0x0, 0x0, 0x0, 0x0, // user config delay in ns +0xef, 0x0, 0x0, 0x0 // flags +}; + +uint8_t _1mhz[] = { // !!! byte-order little endian !!! +0xb5, 0x62, // sync 1 & 2 +0x6, 0x31, // class & id for TP5 setting +0x20, 0x00, // payload length (32 bytes) +0x0, // TP selection +0x1, // reserved 0 +0x0, 0x0, // reserved 1 +0x32, 0x0, // antenna cable delay in ns (int16_t) +0x0, 0x0, // RF group delay in ns +0x1, 0x0, 0x0, 0x0, // frequency unlocked +0x40, 0x42, 0xf, 0x0, // frequency locked +0x0, 0x0, 0x0, 0x80, // pulse width unlocked +0x0, 0x0, 0x0, 0x80, // pulse width locked +0x0, 0x0, 0x0, 0x0, // user config delay in ns +0xef, 0x0, 0x0, 0x0 // flags +}; + + +void encode_init( void ) +{ + int8_t enc_new; + + enc_new = 0; + if( PHASE_A ) + enc_new = 3; + if( PHASE_B ) + enc_new ^= 1; // convert gray to binary + enc_last = enc_new; // power on state + enc_delta = 0; +} + +int8_t encode_read4( void ) // read four step encoders { +{ + int8_t enc_ret; + + enc_ret = enc_delta; + enc_delta = enc_ret & 3; + + return enc_ret >> 2; +} + + +/* +int16_t enc_old, enc_act; + +int16_t enc_read(void) +{ + + enc_old=enc_act; + enc_act=TIM1->CNT; + + enc_delta=enc_act-enc_old; + return enc_delta >> 2; + +} +*/ + +uint32_t powd(uint8_t exp) +{ + uint32_t dec=1; + while(exp--) + { + dec*=10; + } + + return dec; +} + +void i_to_a (char *a, uint32_t number, uint8_t count) +{ + a += count; + *a = '\0'; + + while (count--) + { + *--a = (number % 10) + '0'; + number /= 10; + } +} + +uint32_t a_to_i(char * buf, uint8_t count) +{ + register char n; + uint32_t num=0; + uint8_t i; + + for(i=0;i0x39) + { + n=0; + } + else + { + n=buf[i]-0x30; + } + num*=10; + num+=n; + } + return num; +} + +int h_to_i(char c){ + int first = c / 16 - 3; + int second = c % 16; + int result = first*10 + second; + if(result > 9) result--; + return result; +} + +int h_to_a(char c, char d){ + int high = h_to_i(c) * 16; + int low = h_to_i(d); + return high+low; +} + +void a_to_h(char a, char *s) +{ + char c; + c = (a >> 4) & 0x0f; + if (c <= 9) c+= '0'; else c += 'a' - 10; + *s++ = c; + c = a & 0x0f; + if (c <= 9) c+= '0'; else c += 'a' - 10; + *s++ = c; + *s = 0; +} + +/* +uint8_t nmea_checksum(char * nmea) +{ + +} +*/ + +uint8_t usart_in(void) +{ + struct buf_str *p = &rx_buf; + uint8_t tmp; + + if(((rx_buf.in)-(rx_buf.out))==0) + { + return 0; + } + GPIOB->ODR ^= GPIO_ODR_3; + + tmp=p->buf[p->out]; + p->out++; + return (tmp); + +} + +struct gga_data get_gga() +{ + /* + * $xxGGA,time,lat,NS,long,EW,quality,numSV,HDOP,alt,M,sep,M,diffAge,diffStation*cs + * $GPRMC,083559.00,A,4717.11437,N,00833.91522,E,0.004,77.52,091202,,,A* + */ + + char buf[16]; + uint16_t year=2000; + struct rmc_data rmc_tmp; + static int t[] = {0, 3, 2, 5, 0, 3, 5, 1, 4, 6, 2, 4}; + uint8_t rmc_index=0; + uint8_t i=0; + uint32_t tmp; + + for(uint8_t ind=0; RMC_Buffer[ind]!='\n';ind++) { + if(RMC_Buffer[ind]==',' || (RMC_Buffer[ind]=='*')) + { + + switch(rmc_index) + { + case 0: + tmp=a_to_i(buf,6); + rmc_tmp.sec=(uint8_t)(tmp%100); + tmp/=100; + rmc_tmp.min=(uint8_t)(tmp%100); + tmp/=100; + rmc_tmp.hour=(uint8_t)(tmp%100); + break; + case 8: + tmp=a_to_i(buf,6); + year+=tmp%100; + tmp/=100; + rmc_tmp.month=tmp%100; + tmp/=100; + rmc_tmp.day=tmp%100; + break; + } + rmc_index++; + i=0; + } + else if(rmc_index==0) + { + if(RMC_Buffer[ind]!='.') + { + buf[i]=RMC_Buffer[ind]; + i++; + } + } + else if(rmc_index==8) + { + buf[i]=RMC_Buffer[ind]; + i++; + } + } + rmc_tmp.year=year; + year -= rmc_tmp.month < 3; + rmc_tmp.wday=(year + year/4 - year/100 + year/400 + t[rmc_tmp.month-1] + rmc_tmp.day) % 7; + + if(rmc_tmp.wday>6) + { + rmc_tmp.wday=0; + + } + if(rmc_tmp.month>11) + { + rmc_tmp.month=0; + } + return rmc_tmp; +} + + +struct gsa_data get_gsa() { + + /* + * $xxGSA,opMode,navMode{,sv},PDOP,HDOP,VDOP*cs + * $GPGSA,A,3,23,29,07,08,09,18,26,28,,,,,1.94,1.18,1.54* + */ + + + struct gsa_data gsa_tmp; + uint8_t i=0; + uint8_t gsa_index=0; + char buf[4]; + + gsa_tmp.fix=0; + + + for(uint8_t ind=0; GSA_Buffer[ind]!='\0';ind++) { + if((GSA_Buffer[ind]==',') || (GSA_Buffer[ind]=='*')) + { + if(gsa_tmp.fix) + { + switch(gsa_index) + { + case 0: + break; + case 1: + break; + case 14: + gsa_tmp.pdop=a_to_i(buf,3); + break; + case 15: + gsa_tmp.hdop=a_to_i(buf,3); + break; + case 16: + gsa_tmp.vdop=a_to_i(buf,3); + break; + case 17: + break; + default: + gsa_tmp.sats[gsa_index-2]=a_to_i(buf,2); + break; + } + } + gsa_index++; + i=0; + } + else if(gsa_index==1) + { + if(GSA_Buffer[ind]!='3' ) + { + gsa_tmp.fix=0; + } + else + { + gsa_tmp.fix=1; + } + } + else if((gsa_index==14 || gsa_index==15 || gsa_index==16) && gsa_tmp.fix) + { + if(GSA_Buffer[ind]!='.') + { + buf[i]=GSA_Buffer[ind]; + i++; + } + + } + else if(gsa_index>1 && gsa_index<14) + { + buf[i]=GSA_Buffer[ind]; + i++; + + } + } + + return gsa_tmp; +} + +void set_active_dec(uint8_t i, uint8_t j, uint8_t factor, uint8_t output) +{ + if(factor==(i-2)) + { + if((output==j) && (output==0)) + { + ili9341_settextcolor(BLACK,YELLOW); + } + else if(output!=j && j==0) + { + ili9341_settextcolor(YELLOW,BLACK); + } + else if (output==j && output==1) + { + ili9341_settextcolor(BLACK,CYAN); + } + else if(output!=j && j==1) + { + ili9341_settextcolor(CYAN,BLACK); + } + else if(output==j && output==2) + { + ili9341_settextcolor(BLACK,MAGENTA); + } + else if(output!=j && j==2) + { + ili9341_settextcolor(MAGENTA,BLACK); + } + else if((output==j) && (output==3)) + { + ili9341_settextcolor(BLACK,MARINE); + } + else if(output!=j && j==3) + { + ili9341_settextcolor(MARINE,BLACK); + } + } +} + + +void show_frequency(uint32_t * frequency, uint8_t output, uint8_t factor, uint8_t output_status) +{ + uint8_t i=10,j; + uint32_t div=100000000; + uint32_t freq_tmp=0; + + output=output & 0x3; + output_status=output_status & 0xf; + + for(j=0;j<4;j++) + { + char text[4] = { 'C','h',' ' }; + + ili9341_setfont(Arial_12); + + if(j==0 && (output_status & 0x1)!=(out_stat_tmp & 0x1)) + { + if(output_status & 0x1) + { + ili9341_fillrect(0,58,46,28,YELLOW); + ili9341_settextcolor(BLACK, YELLOW); + ili9341_drawrect(0,57,238,30, YELLOW); + } + else + { + ili9341_fillrect(0,58,46,28,BLACK); //0x39C2); + ili9341_settextcolor(YELLOW,BLACK); //0x39C2); + ili9341_drawrect(0,57,238,30, BLACK); + } + ili9341_setcursor(0,59); + text[2]='1'; + ili9341_out(text); + out_stat_tmp = (out_stat_tmp & 0xe) + (output_status & 0x1); + } + else if(j==1 && (output_status & 0x2)!=(out_stat_tmp & 0x2)) + { + if(output_status & 0x2) + { + ili9341_fillrect(0,90,46,28,CYAN); + ili9341_settextcolor(BLACK, CYAN); + ili9341_drawrect(0,89,238,30,CYAN); + } + else + { + ili9341_fillrect(0,90,46,28,BLACK); //0x39C2); + ili9341_settextcolor(CYAN,BLACK); //0x11C6); + ili9341_drawrect(0,89,238,30,BLACK); + } + ili9341_setcursor(0,91); + text[2]='2'; + ili9341_out(text); + out_stat_tmp = (out_stat_tmp & 0xd) + (output_status & 0x2); + } + else if(j==2 && (output_status & 0x4)!=(out_stat_tmp & 0x4)) + { + if(output_status & 0x4) + { + ili9341_fillrect(0,122,46,28,MAGENTA); + ili9341_settextcolor(BLACK, MAGENTA); + ili9341_drawrect(0, 121,238,30, MAGENTA); + } + else + { + ili9341_fillrect(0,122,46,28,BLACK); //0x39C2); + ili9341_settextcolor(MAGENTA,BLACK); //0x11C6); + ili9341_drawrect(0, 121,238,30, BLACK); + } + ili9341_setcursor(0,123); + text[2]='3'; + ili9341_out(text); + out_stat_tmp = (out_stat_tmp & 0xb) + (output_status & 0x4); + } + else if(j==3 && (output_status & 0x8)!=(out_stat_tmp & 0x8)) + { + if(output_status & 0x8) + { + ili9341_fillrect(0,154,46,28,MARINE); + ili9341_settextcolor(BLACK, MARINE); + ili9341_drawrect(0,153,238,30,MARINE); + } + else + { + ili9341_fillrect(0,154,46,28,BLACK); //0x39C2); + ili9341_settextcolor(MARINE,BLACK); //0x11C6); + ili9341_drawrect(0,153,238,30,BLACK); + } + ili9341_setcursor(0,155); + text[2]='4'; + ili9341_out(text); + out_stat_tmp = (out_stat_tmp & 0x7) + (output_status & 0x8); + } + ili9341_setfont(Arial_18); + + switch(j) + { + case 0: + ili9341_setcursor(35,59); + ili9341_settextcolor(YELLOW,BLACK); + break; + case 1: + ili9341_setcursor(35,91); + ili9341_settextcolor(CYAN,BLACK); + break; + case 2: + ili9341_settextcolor(MAGENTA,BLACK); + ili9341_setcursor(35,123); + break; + case 3: + ili9341_settextcolor(MARINE,BLACK); + ili9341_setcursor(35,155); + break; + } + ili9341_out(" "); + ili9341_settextsize(2); + i=10; + if(frequency_tmp[j]!=frequency[j]) + { + div=100000000; + freq_tmp=frequency[j]; + } + else + { + div=0; + } + while(div) + { + set_active_dec(i,j,factor,output); + i_to_a(text,freq_tmp/div,1); + ili9341_out(text); + freq_tmp=freq_tmp%div; + div/=10; + i--; + + switch(j) + { + case 0: + ili9341_settextcolor(YELLOW,BLACK); + break; + case 1: + ili9341_settextcolor(CYAN,BLACK); + break; + case 2: + ili9341_settextcolor(MAGENTA,BLACK); + break; + case 3: + ili9341_settextcolor(MARINE,BLACK); + break; + } + + if(i==7 || i==4) + { + ili9341_out("."); + } + if(i==1) + { + ili9341_out(" Hz"); + } + } + } + ili9341_settextsize(1); +} + +void show_utctime(struct rmc_data rmc) +{ + char text[3]; + + ili9341_setcursor(224,14); + ili9341_settextcolor(WHITE,PURPLE); + i_to_a(text,rmc.hour,2); + ili9341_out(text); + ili9341_out(":"); + i_to_a(text,rmc.min,2); + ili9341_out(text); + ili9341_out(":"); + i_to_a(text,rmc.sec,2); + ili9341_out(text); + ili9341_out(" UTC"); + +} + +void show_dop(struct gsa_data gsa) +{ + char text[3]; + + ili9341_settextcolor(BLACK,WHITE); + ili9341_setcursor(242,34); + ili9341_out("PDOP: "); + i_to_a(text,(gsa.pdop/100),1); + ili9341_out(text); + ili9341_out("."); + i_to_a(text,(gsa.pdop%100),2); + ili9341_out(text); + ili9341_setcursor(242,48); + ili9341_out("HDOP: "); + i_to_a(text,(gsa.hdop/100),1); + ili9341_out(text); + ili9341_out("."); + i_to_a(text,(gsa.hdop%100),2); + ili9341_out(text); + ili9341_setcursor(242,62); + ili9341_out("VDOP: "); + i_to_a(text,(gsa.vdop/100),1); + ili9341_out(text); + ili9341_out("."); + i_to_a(text,(gsa.vdop%100),2); + ili9341_out(text); + +} + +void show_locator (struct gga_data gga) +{ + int32_t longitude; + int32_t latitude; + + char loc[] = { 'A','A','0','0','a','a','0','0','a','a',' ','\0' }; + + longitude=(int32_t)gga.longitude; + latitude=(int32_t)gga.latitude; + + if(gga.long_hemi) + { + longitude*=-1; + } + if(gga.lat_hemi) + { + latitude*=-1; + } + longitude+=1800000000; + latitude+=900000000; + + + loc[0]+=(char)(longitude/200000000); + loc[2]+=(char)((longitude%200000000)/20000000); + longitude=longitude%20000000; + loc[4]+=(char)((longitude*=12)/10000000); + longitude=longitude%10000000; + longitude/=12; + loc[6]+=(char)((longitude*=12)/1000000); + longitude=longitude%1000000; + longitude/=12; + loc[8]+=(char)((longitude*=288)/1000000); + + loc[1]+=(char)(latitude/100000000); + loc[3]+=(char)((latitude%100000000)/10000000); + latitude=latitude%10000000; + loc[5]+=(char)((latitude*=24)/10000000); + latitude=latitude%10000000; + latitude/=24; + loc[7]+=(char)((latitude*=24)/1000000); + latitude=latitude%1000000; + latitude/=24; + loc[9]+=(char)((latitude*=576)/1000000); + + ili9341_setcursor(3,206); + ili9341_settextcolor(WHITE,VIRIDIAN); + ili9341_out("Loc: "); + ili9341_out(loc); +} + + +void show_altitude(struct gga_data gga) +{ + char text[4]; + + ili9341_setcursor(163,206); + ili9341_settextcolor(WHITE,FAINTGREEN); + ili9341_out("Alt: "); + i_to_a(text,gga.altitude/10,3); + ili9341_out(text); + ili9341_out("."); + i_to_a(text,(gga.altitude%10),1); + ili9341_out(text); + ili9341_out("M\n"); +} + +void show_longitude(struct gga_data gga) +{ + char text[4]; + + ili9341_setcursor(163,222); + ili9341_settextcolor(WHITE,DARKGREEN); + ili9341_out("Lon: "); + i_to_a(text,gga.long_deg,3); + ili9341_out(text); + //ili9341_write(0x81); + i_to_a(text,gga.long_min,2); + ili9341_out(text); + ili9341_out("'"); + i_to_a(text,gga.long_sec/1000,2); + ili9341_out(text); + ili9341_out(","); + i_to_a(text,gga.long_sec%1000,3); + ili9341_out(text); + ili9341_out("\""); + ili9341_out(long_hemi[gga.long_hemi]); + ili9341_out("\n"); +} + +void show_latitude(struct gga_data gga) +{ + char text[4]; + + ili9341_setcursor(3,222); + ili9341_settextcolor(BLACK,EMERALD); + ili9341_out("Lat: "); + i_to_a(text,gga.lat_deg,2); + ili9341_out(text); + //ili9341_write(0x81); + i_to_a(text,gga.lat_min,2); + ili9341_out(text); + ili9341_out("'"); + i_to_a(text,gga.lat_sec/1000,2); + ili9341_out(text); + ili9341_out(","); + i_to_a(text,gga.lat_sec%1000,3); + ili9341_out(text); + ili9341_out("\""); + ili9341_out(lat_hemi[gga.lat_hemi]); +} + +void show_ocxo_lock(void) +{ + ili9341_setcursor(114,14); + ili9341_setfont(Arial_10); + ili9341_settextcolor(WHITE,DARKPURPLE); + OCXO_LOCK ? ili9341_out(ocxolock[1]) : ili9341_out(ocxolock[0]); + ili9341_settextcolor(WHITE,BLACK); +} + +void switch_i2c(uint8_t channel) +{ + if(!channel) + { + GPIOF->MODER &= ~(GPIO_MODER_MODER6 | GPIO_MODER_MODER7); + GPIOB->MODER |= (GPIO_MODER_MODER10_1 | GPIO_MODER_MODER11_1); + + } + else + { + GPIOB->MODER &= ~(GPIO_MODER_MODER10 | GPIO_MODER_MODER11); + GPIOF->MODER |= (GPIO_MODER_MODER6_1 | GPIO_MODER_MODER7_1); + } +} +void neo7m_out(uint8_t * s) +{ + struct buf_str *p = &tx_buf; + uint8_t ck_a=0,ck_b=0; + uint16_t n,i; + + n=s[4] + (s[5]<<8) + 0x6; + + for(i=0;i1) + { + ck_a = ck_a + s[i]; + ck_b = ck_b + ck_a; + } + p->buf[p->in]=(uint8_t)s[i]; + p->in++; + + } + + p->buf[p->in]=(uint8_t)ck_a; + p->in++; + p->buf[p->in]=(uint8_t)ck_b; + p->in++; + + if(tx_restart) + { + tx_restart=0; + USART2->CR1 |= USART_CR1_TXEIE; + } +} + + +int main(void) +{ + GGA_Index=0; + memset(GGA_Buffer, 0, Buffer_Size); + //uint32_t counter=0; + struct rmc_data rmc; + struct gsa_data gsa; + struct gga_data gga; + char text[36]; + uint32_t freq[]= { 10000,20000,40000,80000 }; + uint32_t freq_old[]= { 0,0,0,0 }; + //uint32_t freq2=2000000; + uint8_t spacing=0; + uint8_t set_mode=0; + register uint8_t tmp; + uint16_t ind=0; + uint8_t multiplier=0; + uint8_t sel_output=0; + uint8_t output_stat=0; + uint8_t menu=0; + uint8_t date_temp[] = { 0,0,0 }; + uint8_t init=0; + uint16_t counter=0; + RCC_Configuration(); + delay_init(); + + i2c_init(I2C2); + + GPIOA->MODER &= ~(GPIO_MODER_MODER0 | GPIO_MODER_MODER1 | GPIO_MODER_MODER2 | GPIO_MODER_MODER3 | GPIO_MODER_MODER4 | + GPIO_MODER_MODER6 | GPIO_MODER_MODER5 | GPIO_MODER_MODER7 | GPIO_MODER_MODER8 | GPIO_MODER_MODER9 | + GPIO_MODER_MODER10 | GPIO_MODER_MODER11); + GPIOA->OSPEEDR |= ( GPIO_OSPEEDER_OSPEEDR0 | GPIO_OSPEEDER_OSPEEDR1 | GPIO_OSPEEDER_OSPEEDR2 | + GPIO_OSPEEDER_OSPEEDR3 | GPIO_OSPEEDER_OSPEEDR4 | GPIO_OSPEEDER_OSPEEDR6 | + GPIO_OSPEEDER_OSPEEDR5 | GPIO_OSPEEDER_OSPEEDR7 | GPIO_OSPEEDER_OSPEEDR8 | + GPIO_OSPEEDER_OSPEEDR9 | GPIO_OSPEEDER_OSPEEDR10 | GPIO_OSPEEDR_OSPEEDR11); + GPIOA->MODER |= ( GPIO_MODER_MODER2_1 | GPIO_MODER_MODER4_1 | GPIO_MODER_MODER6_0 | + GPIO_MODER_MODER5_1 | GPIO_MODER_MODER7_1 | GPIO_MODER_MODER8_1 | GPIO_MODER_MODER10_1 | + GPIO_MODER_MODER11_1); // | GPIO_MODER_MODER8_1 | GPIO_MODER_MODER9_1; + GPIOA->PUPDR |= (GPIO_PUPDR_PUPDR0_0 | GPIO_PUPDR_PUPDR1_0 | GPIO_PUPDR_PUPDR3_0 | GPIO_PUPDR_PUPDR8_0 | GPIO_PUPDR_PUPDR9_0); + GPIOA->AFR[0] |= (1<<8) | (0<<16) | (0<<20) | (0<<28); // SPI1 + GPIOA->AFR[1] |= (1<<8) | (2<<0); // USART1 (2<<0) | (2<<4) | + + GPIOB->MODER &= ~(GPIO_MODER_MODER5 | GPIO_MODER_MODER6 | GPIO_MODER_MODER7 | GPIO_MODER_MODER8 | GPIO_MODER_MODER13 | GPIO_MODER_MODER10 | GPIO_MODER_MODER11 | + GPIO_MODER_MODER12); + GPIOB->OSPEEDR |= (GPIO_OSPEEDER_OSPEEDR5 | GPIO_OSPEEDER_OSPEEDR6 | GPIO_OSPEEDER_OSPEEDR7 | GPIO_OSPEEDER_OSPEEDR8 | GPIO_OSPEEDER_OSPEEDR12 | GPIO_OSPEEDER_OSPEEDR13 + | GPIO_OSPEEDER_OSPEEDR10 | GPIO_OSPEEDER_OSPEEDR11 ); + GPIOB->PUPDR |= (GPIO_PUPDR_PUPDR6_0 | GPIO_PUPDR_PUPDR7_0 | GPIO_PUPDR_PUPDR10_0 | GPIO_PUPDR_PUPDR11_0); + GPIOB->OTYPER |= (GPIO_OTYPER_OT_6 | GPIO_OTYPER_OT_7 | GPIO_OTYPER_OT_10 | GPIO_OTYPER_OT_11); + GPIOB->AFR[1] |= (1<<8) | (1<<12); + GPIOB->MODER |= (GPIO_MODER_MODER5_0 | GPIO_MODER_MODER6_1 | GPIO_MODER_MODER7_1 | GPIO_MODER_MODER8_0 | GPIO_MODER_MODER13_0 | GPIO_MODER_MODER12_1 //); + | GPIO_MODER_MODER10_1 | GPIO_MODER_MODER11_1 ); + GPIOB->AFR[0] |= (1<<24) | (1<<28); // I2C + //GPIOB->AFR[1] |= (1<<8) | (1<<12); + + GPIOF->MODER &= ~(GPIO_MODER_MODER6 | GPIO_MODER_MODER7); + GPIOF->OSPEEDR |= (GPIO_OSPEEDER_OSPEEDR6 | GPIO_OSPEEDER_OSPEEDR7); + //GPIOF->MODER |= (GPIO_MODER_MODER6_1 | GPIO_MODER_MODER7_1); + GPIOF->PUPDR |= (GPIO_PUPDR_PUPDR6_0 | GPIO_PUPDR_PUPDR7_0); + GPIOF->OTYPER |= (GPIO_OTYPER_OT_6 | GPIO_OTYPER_OT_7); + //GPIOF->AFR[0] |= (1<<24) | (1<<28); + + USART1->BRR = 400000 / 96; + USART1->CR1 |= USART_CR1_RE | USART_CR1_TE; + USART1->CR2 |= USART_CR2_RTOEN; + USART1->RTOR = 0xf00; + USART1->CR3 |= USART_CR3_DMAR; + USART1->CR1 |= USART_CR1_UE; + + USART2->BRR = 400000 / 96; + USART2->CR1 |= USART_CR1_TE; + USART2->CR1 |= USART_CR1_UE; + + DMA1_Channel3->CPAR = (uint32_t)(&(USART1->RDR)); + DMA1_Channel3->CMAR = (uint32_t)(usart_in_buf); + DMA1_Channel3->CNDTR = 512; + DMA1_Channel3->CCR |= DMA_CCR_MINC; + DMA1_Channel3->CCR |= DMA_CCR_EN; + + DMA1_Channel4->CPAR = (uint32_t)(&(I2C2->TXDR)); + DMA1_Channel4->CMAR = (uint32_t)(i2c_tx_buf); + DMA1_Channel4->CCR |= DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TCIE; + + DMA1_Channel5->CPAR = (uint32_t)(&(I2C2->RXDR)); + DMA1_Channel5->CMAR = (uint32_t)(i2c_rx_buf); + DMA1_Channel5->CCR |= DMA_CCR_MINC | DMA_CCR_TCIE; + + I2C2->CR1 |= I2C_CR1_TXDMAEN | I2C_CR1_RXDMAEN; + + + TIM1->PSC = 624; + TIM1->ARR = 63999; + TIM1->CCR1 = 1280; // Pulse_Output = ARR - CCR1 + TIM1->CCMR1 |= (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1FE); // | TIM_CCMR1_OC1PE) ; // // PWM Mode2 + //TIM1->CR1 |= TIM_CR1_OPM; // Select One-pulse mode + TIM1->CCER |= TIM_CCER_CC1E | TIM_CCER_CC1P; + TIM1->CR2 |= TIM_CR2_MMS_2; // MMS=100 Compare - OC1REF signal is used as trigger output (TRGO) + TIM1->EGR |= TIM_EGR_UG; + TIM1->BDTR |= TIM_BDTR_MOE; + TIM1->CR1 |= TIM_CR1_CEN; + + /* + TIM1->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0 | TIM_CCMR1_IC2F_3 | TIM_CCMR1_IC2F_2 | TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2; + //TIM_CCMR1_IC1PSC_1 | TIM_CCMR1_IC2PSC_1; + TIM1->CCER &= (uint16_t)(~(TIM_CCER_CC1P | TIM_CCER_CC2P)); + TIM1->SMCR |= TIM_SMCR_SMS_0 | TIM_SMCR_SMS_1 | TIM_SMCR_ETPS_1; + TIM1->CNT = 0x8000; + TIM1->DIER |= TIM_DIER_UIE; + //TIM1->EGR |= TIM_EGR_UG; + TIM1->CR1 |= TIM_CR1_CEN; + */ + + TIM15->PSC = 624; + TIM15->ARR = 63999; + TIM15->DIER = TIM_DIER_UIE; + TIM15->CR1 |= (TIM_CR1_CEN); + + TIM16->PSC = 0; // Timer3 500uS + TIM16->ARR = 19999; //18001; + TIM16->CR1 |= TIM_CR1_URS; + TIM16->DIER |= TIM_DIER_UIE; + TIM16->CR1 |= TIM_CR1_CEN; + + SPI1->CR1 |= SPI_CR1_MSTR; + SPI1->CR2 |= SPI_CR2_SSOE | SPI_CR2_FRXTH | SPI_CR2_DS_0 | SPI_CR2_DS_1 | SPI_CR2_DS_2; // FIFO threshold 8bit wide, Data size 8bit + SPI1->CR1 |= SPI_CR1_SPE; + NVIC->ISER[0] |= (1<<(SPI1_IRQn & 0x1f)); + + + SYSCFG->EXTICR[3] |= SYSCFG_EXTICR3_EXTI11_PA; // | SYSCFG_EXTICR3_EXTI8_PA; // | SYSCFG_EXTICR3_EXTI9_PA; + EXTI->IMR |= EXTI_IMR_MR11 | EXTI_IMR_MR8 | EXTI_IMR_MR9; + EXTI->EMR |= EXTI_EMR_MR11 | EXTI_EMR_MR8 | EXTI_EMR_MR9; + EXTI->FTSR |= EXTI_FTSR_TR11 | EXTI_FTSR_TR8 | EXTI_FTSR_TR9; + EXTI->RTSR |= EXTI_RTSR_TR11; + + delay_ms(100); + + encode_init(); + ili9341_init(); + ili9341_clear(BLACK); + ili9341_setrotation(3); + ili9341_setcursor(30,0); + ili9341_setfont(Arial_8); + ili9341_settextcolor(WHITE,BLACK); + ili9341_out("GPS Disciplined Frequency Reference by HB9EVI"); + ili9341_fillrect(0,10,106,18,ULTRAPURPLE); + ili9341_fillrect(107,10,107,18,DARKPURPLE); + ili9341_fillrect(214,10,106,18,PURPLE); + ili9341_drawhline(0,28,320,WHITE); + ili9341_fillrect(240,29,80,174,WHITE); + ili9341_drawhline(0,202,320,WHITE); + ili9341_fillrect(0,204,160,18,VIRIDIAN); + ili9341_fillrect(158,204,162,18,FAINTGREEN); + ili9341_fillrect(0,222,160,18,EMERALD); + ili9341_fillrect(158,222,162,18,DARKGREEN); + + delay_ms(100); + GPIOB->BSRR |= (GPIO_BSRR_BS_13); + //neo7m_out(_1mhz); + + NVIC->ISER[0] |= (1<<(TIM15_IRQn & 0x1f)); + NVIC->ISER[0] |= (1<<(TIM16_IRQn & 0x1f)); + //NVIC->ISER[0] |= (1<<(DMA1_Channel4_5_IRQn & 0x1f)); + //NVIC->ISER[0] |= (1<<(TIM1_BRK_UP_TRG_COM_IRQn & 0x1f)); + + //_24aa02_write_dword(I2C2,0x4,15600000); + + delay_ms(10); + + si5351aOutputOff(0x0); + + switch_i2c(0); + freq[0]=_24aa02_read_dword(I2C2,0x0); + freq[1]=_24aa02_read_dword(I2C2,0x4); + freq[2]=_24aa02_read_dword(I2C2,0x8); + freq[3]=_24aa02_read_dword(I2C2,0xc); + + si5351aSet(0, freq[0], 0,output_stat); + si5351aSet(0, freq[1], 1,output_stat); + si5351aSet(1, freq[2], 0,output_stat); + si5351aSet(1, freq[3], 1,output_stat); + si5351aOutputOff(output_stat); + + show_ocxo_lock(); + show_frequency(freq,0,0,0); + + GPIOB->BSRR |= GPIO_BSRR_BS_8; + + delay_ms(100); + + USART1->CR1 |= USART_CR1_RTOIE; + + NVIC->ISER[0] |= (1<<(USART1_IRQn & 0x1f)); + NVIC->ISER[0] |= (1<<(USART2_IRQn & 0x1f)); + neo7m_out(_1mhz); + /* + IWDG->KR = 0xcccc; + IWDG->KR = 0x5555; + IWDG->PR = IWDG_PR_PR_2; // IWDG_PR_PR_1 | IWDG_PR_PR_0 ; + IWDG->RLR = IWDG_RLR_RL; + */ + NVIC->ISER[0] |= (1<<(EXTI4_15_IRQn & 0x1f)); + delay_ms(100); + + + + while (1) + { + if(ocxo_lock) + { + show_ocxo_lock(); + ocxo_lock=0; + } + + if(rx_finished) + { + + IWDG->KR = 0xaaaa; + + ind=0; + while(usart_in_buf[ind]!='\0') + { + tmp=usart_in_buf[ind]; + usart_in_buf[ind]=0; + ind++; + if(tmp =='$'){ + GGA_Index = 0; + CommaCounter = 0; + IsItGGAString = 0; + IsItRMCString = 0; + IsItGSAString = 0; + IsItGLLString = 0; + } + else if(IsItGGAString == 1){ + if(tmp==',') GGA_Pointers[CommaCounter++] = GGA_Index; + GGA_Buffer[GGA_Index++] = tmp; + } + else if(IsItRMCString == 1) { + if(tmp==',') RMC_Pointers[CommaCounter++] = GGA_Index; + RMC_Buffer[GGA_Index++] = tmp; + } + else if(IsItGSAString == 1) { + if(tmp==',') GSA_Pointers[CommaCounter++] = GGA_Index; + GSA_Buffer[GGA_Index++] = tmp; + } + else if(IsItGLLString == 1) { + if(tmp==',') GLL_Pointers[CommaCounter++] = GGA_Index; + GLL_Buffer[GGA_Index++] = tmp; + } + else if(GGA_code[0] == 'G' && GGA_code[1] == 'G' && GGA_code[2] == 'A'){ + IsItGGAString = 1; + GGA_code[0] = 0; GGA_code[1] = 0; GGA_code[2] = 0; + } + else if(GGA_code[0] == 'R' && GGA_code[1] == 'M' && GGA_code[2] == 'C'){ + IsItRMCString = 1; + GGA_code[0] = 0; GGA_code[1] = 0; GGA_code[2] = 0; + } + else if(GGA_code[0] == 'G' && GGA_code[1] == 'S' && GGA_code[2] == 'A'){ + IsItGSAString = 1; + GGA_code[0] = 0; GGA_code[1] = 0; GGA_code[2] = 0; + } + else if(GGA_code[0] == 'G' && GGA_code[1] == 'L' && GGA_code[2] == 'L'){ + IsItGLLString = 1; + GGA_code[0] = 0; GGA_code[1] = 0; GGA_code[2] = 0; + } + else{ + GGA_code[0] = GGA_code[1]; GGA_code[1] = GGA_code[2]; GGA_code[2] = tmp; + } + DMA1_Channel3->CNDTR=512; + DMA1_Channel3->CCR |= DMA_CCR_EN; + rx_finished=0; + } + + gsa=get_gsa(); + + ili9341_setcursor(5,14); + ili9341_settextcolor(WHITE,ULTRAPURPLE); + ili9341_setfont(Arial_10); + ili9341_out(gpslock[gsa.fix]); + ili9341_settextcolor(WHITE,BLACK); + if(gsa.fix && init!=0) + { + ili9341_setcursor(0,34); + + + rmc=get_rmc(); + + if((date_temp[0]!=rmc.wday) || (date_temp[1]!=rmc.day) || (date_temp[2]!=rmc.month)) + { + ili9341_fillrect(0,34,238,18,BLACK); + } + ili9341_settextcolor(WHITE,BLACK); + ili9341_out(weekdays[rmc.wday]); + ili9341_out(", "); + i_to_a(text, rmc.day,2); + ili9341_out(text); + ili9341_out(". "); + ili9341_out(months[rmc.month-1]); + ili9341_out(" "); + i_to_a(text, rmc.year,4); + ili9341_out(text); + //ili9341_out(" \n"); + show_utctime(rmc); + date_temp[0]=rmc.wday; + date_temp[1]=rmc.day; + date_temp[2]=rmc.month; + + + show_dop(gsa); + + gga=get_gga(); + + + ili9341_settextcolor(BLACK,WHITE); + ili9341_setcursor(242,100); + ili9341_out("Sats: "); + i_to_a(text,gga.sat_num,2); + ili9341_out(text); + + + ili9341_setcursor(242,114); + spacing=128; + for(uint8_t i=0;i200000001) + { + freq[sel_output]=8192; + } + else if(freq[sel_output]<8192) + { + freq[sel_output]=8192; + } + + ili9341_setcursor(30,100); + show_frequency(freq,sel_output,multiplier,output_stat); + update_freq=1; + //set_mode=1; + break; + case 0xfd: + output_stat^=(1<CNT + (48000 - (uint32_t) TIM1->CCR1)) % 48000; + + /* + if(TIM1->CR1 & TIM_CR1_DIR) + { + test=-1; + } + else + { + test=1; + } + */ + /* + if(test<0) + { + test^=1; + test>>=2; + test^=1; + } + else + { + test>>=2; + } + */ + //TIM1->CNT=0; + //test-=test_old; + //freq[sel_output]+=(encoderPosition*powd(multiplier)); + //test_old=(int16_t)TIM1->CNT; + //ili9341_setcursor(30,100); + //show_frequency(freq,sel_output,multiplier,output_stat); + + //set_mode=1; + /* + ili9341_setcursor(270,185); + ili9341_settextsize(1); + ili9341_settextcolor(BLACK,LIGHTGREY); + i_to_a(text,TIM1->CNT>>2,5); + ili9341_out(text); + */ + break; + case 0xab: + //set_mode=1; + break; + } + keyfunc=0; + if(!menu) { + + ili9341_fillrect(0,180,240,24,BLACK); + } + btn_hb=0; + } + + if(set_mode) + { + switch(set_mode) + { + case 1: + switch(sel_output) + { + case 0: + if(freq[0]!=freq_old[0]) + { + si5351aSet(0, freq[0],0,output_stat); + freq_old[0]=freq[0]; + } + break; + case 1: + if(freq[1]!=freq_old[1]) + { + si5351aSet(0, freq[1],1,output_stat); + freq_old[1]=freq[1]; + } + break; + case 2: + if(freq[2]!=freq_old[2]) + { + si5351aSet(1, freq[2],0,output_stat); + freq_old[2]=freq[2]; + } + break; + case 3: + if(freq[3]!=freq_old[3]) + { + si5351aSet(1, freq[3],1,output_stat); + freq_old[3]=freq[3]; + } + break; + } + //set_mode=10; + break; + case 2: + si5351aOutputOff(output_stat); + set_mode=10; + break; + case 10: + ili9341_setcursor(30,100); + show_frequency(freq,sel_output,multiplier,output_stat); + set_mode=0; + break; + + } + } + } +} + +void RCC_Configuration(void) +{ + RCC->CR |= ((uint32_t)RCC_CR_HSEBYP); + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + while((RCC->CR & RCC_CR_HSERDY) == 0) {} + + FLASH->ACR |= FLASH_ACR_LATENCY | FLASH_ACR_PRFTBE; + + while((FLASH->ACR & FLASH_ACR_PRFTBS) == 0) {} + + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE_DIV1; + + if ((RCC->CFGR & RCC_CFGR_SWS) == RCC_CFGR_SWS_PLL) + { + RCC->CFGR &= (uint32_t) (~RCC_CFGR_SW); + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) + { + /* For robust implementation, add here time-out management */ + } + } + RCC->CR &= (uint32_t)(~RCC_CR_PLLON); + while((RCC->CR & RCC_CR_PLLRDY) != 0) + { + /* For robust implementation, add here time-out management */ + } + RCC->CFGR = (RCC->CFGR & (~RCC_CFGR_PLLMUL)) | (RCC_CFGR_PLLSRC_HSE_PREDIV) | (RCC_CFGR_PLLMUL4); + RCC->CR |= RCC_CR_PLLON; + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + /* For robust implementation, add here time-out management */ + } + RCC->CFGR |= (uint32_t) (RCC_CFGR_SW_PLL); + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) + { + /* For robust implementation, add here time-out management */ + } + + //RCC->CFGR |= RCC_CFGR_MCO_PLL; + + SystemCoreClockUpdate(); + + RCC->AHBENR |= RCC_AHBENR_GPIOAEN; + RCC->AHBENR |= RCC_AHBENR_GPIOBEN; + RCC->AHBENR |= RCC_AHBENR_GPIOCEN; + RCC->AHBENR |= RCC_AHBENR_GPIOFEN; + RCC->AHBENR |= RCC_AHBENR_DMA1EN; + RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; + //RCC->APB1ENR |= RCC_APB1ENR_I2C1EN; + RCC->APB1ENR |= RCC_APB1ENR_I2C2EN; + RCC->APB2ENR |= RCC_APB2ENR_USART1EN; + RCC->APB1ENR |= RCC_APB1ENR_USART2EN; + RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; + RCC->APB2ENR |= RCC_APB2ENR_TIM15EN; + RCC->APB2ENR |= RCC_APB2ENR_TIM16EN; + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; + RCC->APB2ENR |= RCC_APB2ENR_SYSCFGCOMPEN; + +} + +extern void SPI1_IRQHandler(void) +{ + if(SPI1->SR & SPI_SR_TXE) + { + *(uint8_t *)&(SPI1->DR)=spi_buf; + SPI1->CR2 &= ~SPI_CR2_TXEIE; + } +} + +/* +extern void DMA1_Channel4_5_IRQHandler() +{ + if(DMA1->ISR & DMA_ISR_TCIF4) + { + //I2C2->TXDR=i2c_tx_buf[i2c_index]; + //i2c_tx_buf[i2c_index]=0; + i2c_index++; + if(i2c_count==i2c_index) + { + + + //GPIOB->BSRR |= GPIO_BSRR_BS_5; + + i2c_stop(I2C2); + i2c_index=0; + i2c_count=0; + I2C2->CR1 &= ~I2C_CR1_PE; + DMA1_Channel4->CCR &= ~(DMA_CCR_EN); + + } + DMA1->IFCR |= DMA_IFCR_CTCIF4; + } + if(DMA1->ISR & DMA_ISR_TCIF5) + { + //i2c_rx_buf[i2c_index]=I2C2->RXDR; + i2c_index++; + //GPIOB->BSRR |= GPIO_BSRR_BS_5; + + if((i2c_count-i2c_index)==1) + { + //I2C2->CR2 |= (I2C_CR2_NACK); + } + if(i2c_count==i2c_index) + { + GPIOB->BSRR |= GPIO_BSRR_BS_5; + i2c_stop(I2C2); + //i2c_reset(I2C2); + i2c_index=0; + i2c_count=0; + I2C2->CR1 &= ~I2C_CR1_PE; + DMA1_Channel5->CCR &= ~(DMA_CCR_EN); + + + } + DMA1->IFCR |= DMA_IFCR_CTCIF5; + } +} +*/ + + +extern void USART2_IRQHandler(void) +{ + struct buf_str *p; + if((USART2->ISR & USART_ISR_TXE)) + { + p = &tx_buf; + if((p->in != p->out)) // && !(USART1->SR & USART_SR_CTS)) + { + USART2->TDR = (p->buf[p->out & 255]); + p->out++; + + } + else { + tx_restart=1; + USART2->CR1 &= ~(USART_CR1_TXEIE); + } + } +} +extern void USART1_IRQHandler(void) +{ + //register uint8_t tmp; + + + + if((USART1->ISR & USART_ISR_ORE)) + { + USART1->ICR |= USART_ICR_ORECF; + USART1->ISR &= ~USART_ISR_RXNE; + + (void)USART1->RDR; + } + + + if((USART1->ISR & USART_ISR_RTOF)) + { + USART1->ICR |= USART_ICR_RTOCF; + if(startup) + { + startup=0; + } + else + { + DMA1_Channel3->CCR &= ~(DMA_CCR_EN); + rx_finished=1; + } + } + + /* + if((USART1->ISR & USART_ISR_TXE)) + { + p = &tx_buf; + if((p->in != p->out)) // && !(USART1->SR & USART_SR_CTS)) + { + USART1->TDR = (p->buf[p->out & 255]); + p->out++; + + } + else { + tx_restart=1; + USART1->CR1 &= ~(USART_CR1_TXEIE); + } + } + */ +} +/* +extern void I2C1_IRQHandler(void) +{ + // + + ili9341_setcursor(55,184); + ili9341_settextcolor(WHITE,BLACK); + ili9341_setfont(Arial_14); + ili9341_out("I2C!"); + + uint32_t I2C_InterruptStatus = I2C1->ISR; + + if((I2C_InterruptStatus & I2C_ISR_ADDR) == I2C_ISR_ADDR) + { + I2C1->ICR |= I2C_ICR_ADDRCF; + if((I2C1->ISR & I2C_ISR_DIR) == I2C_ISR_DIR) + { + I2C1->CR1 |= I2C_CR1_TXIE; + } + else + { + I2C1->CR1 |= I2C_CR1_RXIE; + } + + } + else if((I2C_InterruptStatus & I2C_ISR_RXNE) == I2C_ISR_RXNE) + { + I2C1->CR1 &= ~I2C_CR1_RXIE; + i2c_rx_buf=I2C1->RXDR; + + //if(I2C1->RXDR == I2C_BYTE_TO_SEND) + //{ + // GPIOC->ODR ^= GPIO_ODR_9; + //} + } + else if((I2C_InterruptStatus & I2C_ISR_TXIS) == I2C_ISR_TXIS) + { + I2C1->CR1 &=~ I2C_CR1_TXIE; + I2C1->TXDR = i2c_tx_buf; + } + + else + { + //NVIC->ISER[0] &= ~(1<<(I2C1_IRQn & 0x1f)); + //GPIOC->BSRR = GPIO_BSRR_BS_8; + //NVIC_DisableIRQ(I2C1_IRQn); + } + +} +*/ + +extern void EXTI4_15_IRQHandler(void) +{ + if(EXTI->PR & EXTI_PR_PR11) + { + //keyfunc=0xaa; + ocxo_lock=1; + EXTI->PR |= EXTI_PR_PR11; + } + else if((EXTI->PR & EXTI_PR_PR8) || (EXTI->PR & EXTI_PR_PR9)) + { + + + /* + int8_t state = PHASE_A>>8 | PHASE_B>>8; + + if (state != lastState) { + position += encoderStates[state | (lastState << 2)]; + lastState = state; //remember previous state + if (state == 3) encoderPosition = position >> 2; + } + keyfunc=0xcc; + */ + EXTI->PR |= EXTI_PR_PR8; + EXTI->PR |= EXTI_PR_PR9; + } + +} + +/* +extern void TIM1_BRK_UP_TRG_COM_IRQHandler(void) +{ + if(TIM1->SR & TIM_SR_UIF) // if UIF flag is set + { + keyfunc=0xcc; + + TIM1->SR &= ~TIM_SR_UIF; // clear UIF flag + + } +} +*/ + +extern void TIM15_IRQHandler(void) +{ + + if(TIM15->SR & TIM_SR_UIF) // if UIF flag is set + { + + //keyfunc=0xab; + //update_freq=1; + + TIM15->SR &= ~TIM_SR_UIF; // clear UIF flag + } + +} +extern void TIM16_IRQHandler(void) +{ + + if(TIM16->SR & TIM_SR_UIF) // if UIF flag is set + { + + int8_t enc_new=0; + int8_t enc_diff=0; + int8_t enc_temp; + + enc_temp=enc_last; + + enc_new = 0; + if( !PHASE_A ) { + enc_new = 3; } + if( !PHASE_B ) { + enc_new ^= 1; } // convert gray to binary + enc_diff = enc_last - enc_new; // difference last - new + if( enc_diff & 1 ) { // bit 0 = value (1) + enc_last = enc_new; // store new as next last + enc_delta += (enc_diff & 2) - 1; } // bit 1 = direction (+/-) + if(enc_temp!=enc_last) { + keyfunc=0xfe; + } + + if(!KEY) { + btn_hb++; + } + else { + if(!btn_hb) {} // keyfunc==0xfe) { keypress=0; keyfunc=0; } + else if(btn_hb<1500) { + keyfunc=0xfd; + btn_hb=0xffff; + } + else if(btn_hb<3000) { + keyfunc=0xfc; + btn_hb=0xffff; + } + else if(btn_hb<4500) { + keyfunc=0xfb; + btn_hb=0xffff; + } + else if(btn_hb<6000) { + keyfunc=0xfa; + btn_hb=0xffff; + } + else if(btn_hb<7500) { + keyfunc=0xf9; + btn_hb=0xffff; + } + else if(btn_hb<0xffff) { + keyfunc=0xea; + btn_hb=0xffff; + } + + } + TIM16->SR &= ~TIM_SR_UIF; // clear UIF flag + } + +} +// ---------------------------------------------------------------------------- diff --git a/src/main.c.bak b/src/main.c.bak new file mode 100644 index 0000000..8f38e32 --- /dev/null +++ b/src/main.c.bak @@ -0,0 +1,1359 @@ +/* + * GPS disciplined OCXO with SI5351 frequency generator + * + */ + +// ---------------------------------------------------------------------------- + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ili9341.h" +#include "ili9341gfx.h" +#include "delay.h" +#include "i2c.h" +#include "si5351a.h" + + +#define IO_RX_BUFLEN ((rx_buf.in - rx_buf.out)) + +#define OCXO_LOCK (GPIOA->IDR & 0x800) +#define PHASE_A (GPIOA->IDR & 0x4) +#define PHASE_B (GPIOA->IDR & 0x2) +#define KEY (GPIOA->IDR & 0x1) + + +static volatile uint8_t tx_restart=1; +static volatile uint8_t rx_finished=0; +volatile uint16_t btn_hb=0; +volatile uint8_t enc_event=0; +volatile int8_t enc_delta; +volatile uint8_t keyfunc=0; +static int8_t enc_last; + +#define Buffer_Size 64 + +char GGA_Buffer[Buffer_Size]; /* save GGA string */ +char RMC_Buffer[Buffer_Size]; +char GSA_Buffer[Buffer_Size]; +char GLL_Buffer[Buffer_Size]; +uint8_t GGA_Pointers[20]; /* to store instances of ',' */ +uint8_t RMC_Pointers[20]; +uint8_t GSA_Pointers[20]; +uint8_t GLL_Pointers[20]; +volatile char GGA_code[3]; + +volatile uint16_t GGA_Index, CommaCounter; + +uint8_t IsItGGAString = 0, + IsItRMCString=0, + IsItGSAString=0, + IsItGLLString=0, + flag1= 0, + flag2= 0; + + + +void RCC_Configuration(void); + +struct buf_str +{ + uint8_t in; + uint8_t out; + uint8_t buf[255]; +}; + +static struct buf_str rx_buf = { 0,0,{0} }; +static struct buf_str tx_buf = { 0,0,{0} }; + + +struct date { + uint8_t sec; + uint8_t min; + uint8_t hour; + uint8_t day; + uint8_t month; + uint8_t wday; + uint16_t year; +}; + +struct ZoneInfo { + int8_t time; + char zone[4]; +}; + +struct gsa_data +{ + uint8_t fix; + uint8_t count; + uint16_t pdop; + uint16_t hdop; + uint16_t vdop; + uint8_t sats[13]; +}; + +struct gga_data +{ + uint32_t time; + uint8_t lat_deg; + uint8_t lat_min; + uint32_t lat_sec; + uint8_t long_deg; + uint8_t long_min; + uint32_t long_sec; + uint8_t lat_hemi; + uint8_t long_hemi; + uint16_t altitude; + uint32_t latitude; + uint32_t longitude; + uint8_t sat_num; +}; + +char * gpslock[] = { + "GPS NoLock", + " GPS Lock " +}; + +char * ocxolock[] = { + "OCXO NoLock", + " OCXO Lock " +}; + +char * lat_hemi[] = { + "N", + "S" +}; + +char * long_hemi[] = { + "E", + "W" +}; + +char * months[] = { + "January", + "February", + "March", + "April", + "May", + "June", + "July", + "August", + "September", + "October", + "November", + "December" + +}; + + +char * wday_long[] = { + "Sunday", + "Monday", + "Tuesday", + "Wednesday", + "Thursday", + "Friday", + "Saturday" + +}; + + +char * wday_short[] = { + "Sun", + "Mon", + "Tue", + "Wed", + "Thu", + "Fri", + "Sat" +}; + +uint8_t _8mhz[] = { +0xb5, 0x62, // sync 1 & 2 +0x6, 0x31, // class & id for TP5 setting +0x20, 0x00, // payload length (32 bytes) +0x0, // TP selection +0x1, // reserved 0 +0x0, 0x0, // reserved 1 +0x32, 0x0, // antenna cable delay in ns (int16_t) +0x0, 0x0, // RF group delay in ns +0x1, 0x0, 0x0, 0x0, // frequency unlocked +0x0, 0x12, 0x7a, 0x0, // frequency locked +0x68, 0x9e, 0x9e, 0x7, // pulse width unlocked +0x0, 0x0, 0x0, 0x80, // pulse width locked +0x0, 0x0, 0x0, 0x0, // user config delay in ns +0xef, 0x0, 0x0, 0x0 // flags +}; + +uint8_t _4mhz[] = { // !!! byte-order little endian !!! +0xb5, 0x62, // sync 1 & 2 +0x6, 0x31, // class & id for TP5 setting +0x20, 0x00, // payload length (32 bytes) +0x0, // TP selection +0x1, // reserved 0 +0x0, 0x0, // reserved 1 +0x32, 0x0, // antenna cable delay in ns (int16_t) +0x0, 0x0, // RF group delay in ns +0x0, 0x0, 0x0, 0x0, // frequency unlocked +0x0, 0x9, 0x3d, 0x0, // frequency locked +0x68, 0x9e, 0x9e, 0x7, // pulse width unlocked +0x0, 0x0, 0x0, 0x80, // pulse width locked +0x0, 0x0, 0x0, 0x0, // user config delay in ns +0xef, 0x0, 0x0, 0x0 // flags +}; + +uint8_t _1mhz[] = { // !!! byte-order little endian !!! +0xb5, 0x62, // sync 1 & 2 +0x6, 0x31, // class & id for TP5 setting +0x20, 0x00, // payload length (32 bytes) +0x0, // TP selection +0x1, // reserved 0 +0x0, 0x0, // reserved 1 +0x32, 0x0, // antenna cable delay in ns (int16_t) +0x0, 0x0, // RF group delay in ns +0x1, 0x0, 0x0, 0x0, // frequency unlocked +0x40, 0x42, 0xf, 0x0, // frequency locked +0x0, 0x0, 0x0, 0x80, // pulse width unlocked +0x0, 0x0, 0x0, 0x80, // pulse width locked +0x0, 0x0, 0x0, 0x0, // user config delay in ns +0xef, 0x0, 0x0, 0x0 // flags +}; + + +void encode_init( void ) +{ + int8_t enc_new; + + enc_new = 0; + if( PHASE_A ) + enc_new = 3; + if( PHASE_B ) + enc_new ^= 1; // convert gray to binary + enc_last = enc_new; // power on state + enc_delta = 0; +} + +int8_t encode_read4( void ) // read four step encoders { +{ + int8_t enc_ret; + + enc_ret = enc_delta; + enc_delta = enc_ret & 3; + + return enc_ret >> 2; +} + +uint32_t powd(uint8_t exp) +{ + uint32_t dec=1; + while(exp--) + { + dec*=10; + } + + return dec; +} + +void i_to_a (char *a, uint32_t number, uint8_t count) +{ + a += count; + *a = '\0'; + + while (count--) + { + *--a = (number % 10) + '0'; + number /= 10; + } +} + +uint32_t a_to_i(char * buf, uint8_t count) +{ + register char n; + uint32_t num=0; + uint8_t i; + + for(i=0;i0x39) + { + n=0; + } + else + { + n=buf[i]-0x30; + } + num*=10; + num+=n; + } + return num; +} + +uint8_t usart_in(void) +{ + struct buf_str *p = &rx_buf; + uint8_t tmp; + + if(((rx_buf.in)-(rx_buf.out))==0) + { + return 0; + } + GPIOB->ODR ^= GPIO_ODR_3; + + tmp=p->buf[p->out]; + p->out++; + return (tmp); + +} + +struct gga_data get_gga() +{ + /* + * $xxGGA,time,lat,NS,long,EW,quality,numSV,HDOP,alt,M,sep,M,diffAge,diffStation*cs0x5a) + { + loc[0]=0x41; + } + longitude=longitude%200000000; + loc[2]=(uint8_t)(longitude/20000000)+0x30; + if(loc[2]<0x30 || loc[2]>0x39) + { + loc[2]=0x30; + } + longitude=longitude%20000000; + loc[4]=(uint8_t)((longitude*=12)/10000000)+0x61; + if(loc[4]<0x61 || loc[4]>0x7a) + { + loc[4]=0x61; + } + longitude=longitude%10000000; + longitude/=12; + loc[6]=(uint8_t)((longitude*=12)/1000000)+0x30; + if(loc[6]<0x30 || loc[6]>0x39) + { + loc[6]=0x30; + } + longitude=longitude%1000000; + longitude/=12; + loc[8]=(uint8_t)((longitude*=288)/1000000)+0x61; + if(loc[8]<0x61 || loc[8]>0x7a) + { + loc[8]=0x61; + } + latitude=(int32_t)gga_tmp.latitude; + //latitude=(int32_t)lat; + if(gga_tmp.lat_hemi) + { + latitude*=-1; + } + latitude+=900000000; + loc[1]=(uint8_t)(latitude/100000000)+0x41; + if(loc[1]<0x41 || loc[1]>0x5a) + { + loc[1]=0x41; + } + latitude=latitude%100000000; + loc[3]=(uint8_t)(latitude/10000000)+0x30; + if(loc[3]<0x30 || loc[3]>0x39) + { + loc[3]=0x30; + } + latitude=latitude%10000000; + loc[5]=(uint8_t)((latitude*=24)/10000000)+0x61; + if(loc[5]<0x61 || loc[5]>0x7a) + { + loc[5]=0x61; + } + latitude=latitude%10000000; + latitude/=24; + loc[7]=(uint8_t)((latitude*=24)/1000000)+0x30; + if(loc[7]<0x30 || loc[7]>0x39) + { + loc[7]=0x30; + } + latitude=latitude%1000000; + latitude/=24; + loc[9]=(uint8_t)((latitude*=576)/1000000)+0x61; + if(loc[9]<0x61 || loc[9]>0x7a) + { + loc[9]=0x61; + } + loc[10]=' '; + loc[11]='\0'; + ili9341_setcursor(10,200); + ili9341_out(loc); +} + + +struct date get_rmc(){ + + /* + * $xxRMC,time,status,lat,NS,long,EW,spd,cog,date,mv,mvEW,posMode*cs + * $GPRMC,083559.00,A,4717.11437,N,00833.91522,E,0.004,77.52,091202,,,A* + */ + + char buf[16]; + uint16_t year=2000; + struct date date_tmp; + static int t[] = {0, 3, 2, 5, 0, 3, 5, 1, 4, 6, 2, 4}; + uint8_t rmc_index=0; + uint8_t i=0; + uint32_t tmp; + + __disable_irq(); + + for(uint8_t ind=0; RMC_Buffer[ind]!='\0';ind++) { + if(RMC_Buffer[ind]==',' || (RMC_Buffer[ind]=='*')) + { + + switch(rmc_index) + { + case 0: + tmp=a_to_i(buf,6); + date_tmp.sec=(uint8_t)(tmp%100); + tmp/=100; + date_tmp.min=(uint8_t)(tmp%100); + tmp/=100; + date_tmp.hour=(uint8_t)(tmp%100); + break; + case 8: + tmp=a_to_i(buf,6); + year+=tmp%100; + tmp/=100; + date_tmp.month=tmp%100; + tmp/=100; + date_tmp.day=tmp%100; + break; + } + rmc_index++; + i=0; + } + else if(rmc_index==0) + { + if(RMC_Buffer[ind]!='.') + { + buf[i]=RMC_Buffer[ind]; + i++; + } + } + else if(rmc_index==8) + { + buf[i]=RMC_Buffer[ind]; + i++; + } + } + date_tmp.year=year; + year -= date_tmp.month < 3; + date_tmp.wday=(year + year/4 - year/100 + year/400 + t[date_tmp.month-1] + date_tmp.day) % 7; + + if(date_tmp.wday>6) + { + date_tmp.wday=0; + + } + if(date_tmp.month>11) + { + date_tmp.month=0; + } + + __enable_irq(); + + return date_tmp; +} + + +struct gsa_data get_gsa() { + + /* + * $xxGSA,opMode,navMode{,sv},PDOP,HDOP,VDOP*cs + * $GPGSA,A,3,23,29,07,08,09,18,26,28,,,,,1.94,1.18,1.54* + */ + + + struct gsa_data gsa_tmp; + uint8_t i=0; + uint8_t gsa_index=0; + char buf[4]; + + gsa_tmp.fix=0; + + __disable_irq(); + + for(uint8_t ind=0; GSA_Buffer[ind]!='\0';ind++) { + if((GSA_Buffer[ind]==',') || (GSA_Buffer[ind]=='*')) + { + if(gsa_tmp.fix) + { + switch(gsa_index) + { + case 0: + break; + case 1: + break; + case 14: + gsa_tmp.pdop=a_to_i(buf,3); + break; + case 15: + gsa_tmp.hdop=a_to_i(buf,3); + break; + case 16: + gsa_tmp.vdop=a_to_i(buf,3); + break; + case 17: + break; + default: + gsa_tmp.sats[gsa_index-2]=a_to_i(buf,2); + break; + } + } + gsa_index++; + i=0; + } + else if(gsa_index==1) + { + if(GSA_Buffer[ind]!='3' ) + { + gsa_tmp.fix=0; + } + else + { + gsa_tmp.fix=1; + } + } + else if((gsa_index==14 || gsa_index==15 || gsa_index==16) && gsa_tmp.fix) + { + if(GSA_Buffer[ind]!='.') + { + buf[i]=GSA_Buffer[ind]; + i++; + } + + } + else if(gsa_index>1 && gsa_index<14) + { + buf[i]=GSA_Buffer[ind]; + i++; + + } + } + __enable_irq(); + + return gsa_tmp; +} + +void show_frequency(uint32_t frequency, uint8_t output, uint32_t pos) +{ + char text[4]; + uint16_t underscore=19; + int8_t add=0; + output=output & 0x1; + + ili9341_settextsize(2); + if(!output) + { + ili9341_setcursor(0,110); + ili9341_settextcolour(YELLOW,BLACK); + ili9341_out("Ch1: "); + + } + else + { + ili9341_setcursor(0,140); + ili9341_settextcolour(CYAN,BLACK); + ili9341_out("Ch2: "); + + } + i_to_a(text,(frequency/1000000),3); + ili9341_out(text); + ili9341_out("'"); + i_to_a(text,(frequency/1000)%1000,3); + ili9341_out(text); + ili9341_out("."); + i_to_a(text,(frequency%1000),3); + ili9341_out(text); + ili9341_out("Hz"); + /* + if(pos>=3) + { + underscore+=4; + } + else if(pos>=6) + { + underscore+=4; + } + */ + + switch(pos) + { + case 3: + underscore+=4; + break; + case 4: + underscore+=3; + break; + case 5: + underscore+=3; + add=1; + break; + case 6: + underscore+=4; + add=1; + break; + case 7: + underscore+=3; + add=-2; + break; + case 8: + underscore+=3; + add=-1; + break; + } + + if(!output) + { + ili9341_settextcolour(YELLOW,BLACK); + ili9341_drawhline(256-(underscore*pos)+add,132,12,YELLOW); + } + else + { + ili9341_settextcolour(CYAN,BLACK); + ili9341_drawhline(256-(underscore*pos),162,12,CYAN); + } + + ili9341_settextcolour(WHITE,BLACK); + ili9341_settextsize(1); + +} + + +void neo7m_out(uint8_t * s) +{ + struct buf_str *p = &tx_buf; + uint8_t ck_a=0,ck_b=0; + uint16_t n,i; + + n=s[4] + (s[5]<<8) + 0x6; + + for(i=0;i1) + { + ck_a = ck_a + s[i]; + ck_b = ck_b + ck_a; + } + p->buf[p->in]=(uint8_t)s[i]; + p->in++; + + } + + p->buf[p->in]=(uint8_t)ck_a; + p->in++; + p->buf[p->in]=(uint8_t)ck_b; + p->in++; + + if(tx_restart) + { + tx_restart=0; + USART1->CR1 |= USART_CR1_TXEIE; + } +} + + +int main(void) +{ + GGA_Index=0; + memset(GGA_Buffer, 0, Buffer_Size); + struct date rmc; + struct gsa_data gsa; + struct gga_data gga; + char text[16]; + uint32_t freq1=1000000; + uint32_t freq2=2000000; + + uint8_t multiplier=0; + + RCC_Configuration(); + delay_init(); + + i2c_init(); + + GPIOA->MODER &= ~(GPIO_MODER_MODER0 | GPIO_MODER_MODER1 | GPIO_MODER_MODER2 | GPIO_MODER_MODER3 | GPIO_MODER_MODER4 | + GPIO_MODER_MODER6 | GPIO_MODER_MODER5 | GPIO_MODER_MODER7 | GPIO_MODER_MODER8 | GPIO_MODER_MODER9 | + GPIO_MODER_MODER10 | GPIO_MODER_MODER11); + GPIOA->OSPEEDR |= ( GPIO_OSPEEDER_OSPEEDR0 | GPIO_OSPEEDER_OSPEEDR1 | GPIO_OSPEEDER_OSPEEDR2 | + GPIO_OSPEEDER_OSPEEDR3 | GPIO_OSPEEDER_OSPEEDR4 | GPIO_OSPEEDER_OSPEEDR6 | + GPIO_OSPEEDER_OSPEEDR5 | GPIO_OSPEEDER_OSPEEDR7 | GPIO_OSPEEDER_OSPEEDR8 | + GPIO_OSPEEDER_OSPEEDR9 | GPIO_OSPEEDER_OSPEEDR10 | GPIO_OSPEEDR_OSPEEDR11); + GPIOA->MODER |= (GPIO_MODER_MODER3_0 | GPIO_MODER_MODER4_0 | GPIO_MODER_MODER6_0 | + GPIO_MODER_MODER5_1 | GPIO_MODER_MODER7_1 | GPIO_MODER_MODER8_1 | GPIO_MODER_MODER9_1 | GPIO_MODER_MODER10_1); + GPIOA->PUPDR |= (GPIO_PUPDR_PUPDR0_0 | GPIO_PUPDR_PUPDR1_0 | GPIO_PUPDR_PUPDR2_0); + GPIOA->AFR[0] |= (0<<20) | (0<<28); // SPI1 + GPIOA->AFR[1] |= (1<<4) | (1<<8); // USART1 + + GPIOB->MODER &= ~(GPIO_MODER_MODER6 | GPIO_MODER_MODER7 | GPIO_MODER_MODER13 | GPIO_MODER_MODER10); + GPIOB->OSPEEDR |= (GPIO_OSPEEDER_OSPEEDR6 | GPIO_OSPEEDER_OSPEEDR7 | GPIO_OSPEEDER_OSPEEDR13 | GPIO_OSPEEDER_OSPEEDR10); + GPIOB->PUPDR |= (GPIO_PUPDR_PUPDR6_0 | GPIO_PUPDR_PUPDR7_0); + GPIOB->OTYPER |= (GPIO_OTYPER_OT_6 | GPIO_OTYPER_OT_7); + GPIOB->MODER |= (GPIO_MODER_MODER6_1 | GPIO_MODER_MODER7_1 | GPIO_MODER_MODER13_0 | GPIO_MODER_MODER10_1); + GPIOB->AFR[0] |= (1<<24) | (1<<28); // I2C + + USART1->BRR = 400000 / 96; + USART1->CR1 |= USART_CR1_RE | USART_CR1_TE; + //USART1->CR3 |= USART_CR3_OVRDIS; + USART1->CR2 |= USART_CR2_RTOEN; + USART1->RTOR=0x1000; + USART1->CR1 |= USART_CR1_UE; + + TIM15->PSC = 63; + TIM15->ARR = 62499; + TIM15->DIER = TIM_DIER_UIE; + TIM15->CR1 |= (TIM_CR1_CEN); + + TIM16->PSC = 0; // Timer3 500uS + TIM16->ARR = 23999; //18001; + //TIM3->CR1 |= TIM_CR1_URS; + TIM16->DIER |= TIM_DIER_UIE; + TIM16->CR1 |= (TIM_CR1_CEN); + + SPI1->CR1 |= SPI_CR1_SSI | SPI_CR1_SSM | SPI_CR1_MSTR; + SPI1->CR2 |= SPI_CR2_FRXTH | SPI_CR2_DS_0 | SPI_CR2_DS_1 | SPI_CR2_DS_2; // FIFO threshold 8bit wide, Data size 8bit + SPI1->CR1 |= SPI_CR1_SPE; + + delay_ms(100); + + encode_init(); + ili9341_init(); + ili9341_clear(BLACK); + ili9341_setRotation(3); + ili9341_setcursor(40,0); + ili9341_settextsize(0); + ili9341_settextcolour(WHITE,BLACK); + ili9341_fillrect(0,0,79,18,ULTRAPURPLE); + ili9341_fillrect(80,0,79,18,DARKPURPLE); + ili9341_fillrect(160,0,79,18,PURPLE); + ili9341_fillrect(240,0,79,18,RED); + + delay_ms(100); + GPIOB->BSRR |= (GPIO_BSRR_BS_13); + neo7m_out(_1mhz); + delay_ms(10); + NVIC->ISER[0] |= (1<<(TIM16_IRQn & 0x1f)); + NVIC->ISER[0] |= (1<<(TIM15_IRQn & 0x1f)); + + + //ili9341_settextcolour(ORANGE,BLACK); + //ili9341_out("GPS disciplined OCXO by HB9EVI"); + //ili9341_drawhline(0,18,320,WHITE); + si5351aSetFrequency(freq1, 1); + ili9341_setcursor(30,100); + show_frequency(freq1,0,0); + show_frequency(freq2,1,0); + + USART1->CR1 |= USART_CR1_RXNEIE; + USART1->CR1 |= USART_CR1_RTOIE; + NVIC->ISER[0] |= (1<<(USART1_IRQn & 0x1f)); + + IWDG->KR = 0xcccc; + IWDG->KR = 0x5555; + IWDG->PR = IWDG_PR_PR_0 | IWDG_PR_PR_1 | IWDG_PR_PR_2;/* (3) */ + IWDG->RLR = IWDG_RLR_RL; + + while (1) + { + + + + if(rx_finished) + { + + IWDG->KR = 0xaaaa; + + gsa=get_gsa(); + + ili9341_setcursor(0,0); + ili9341_settextcolour(WHITE,ULTRAPURPLE); + ili9341_out(gpslock[gsa.fix]); + ili9341_settextcolour(WHITE,BLACK); + if(gsa.fix) + { + ili9341_setcursor(0,22); + + rmc=get_rmc(); + i_to_a(text,rmc.hour,2); + ili9341_out(text); + ili9341_out(":"); + i_to_a(text,rmc.min,2); + ili9341_out(text); + ili9341_out(":"); + i_to_a(text,rmc.sec,2); + ili9341_out(text); + ili9341_out(" "); + ili9341_out(wday_long[rmc.wday]); + ili9341_out(", "); + i_to_a(text, rmc.day,2); + ili9341_out(text); + ili9341_out(". "); + ili9341_out(months[rmc.month-1]); + ili9341_out(" "); + i_to_a(text, rmc.year,4); + ili9341_out(text); + ili9341_out("\n"); + + + ili9341_out(" PDOP="); + i_to_a(text,(gsa.pdop/100),1); + ili9341_out(text); + ili9341_out("."); + i_to_a(text,(gsa.pdop%100),2); + ili9341_out(text); + ili9341_out(" HDOP="); + i_to_a(text,(gsa.hdop/100),1); + ili9341_out(text); + ili9341_out("."); + i_to_a(text,(gsa.hdop%100),2); + ili9341_out(text); + ili9341_out(" VDOP="); + i_to_a(text,(gsa.vdop/100),1); + ili9341_out(text); + ili9341_out("."); + i_to_a(text,(gsa.vdop%100),2); + ili9341_out(text); + ili9341_out("\n"); + + gga=get_gga(); + + ili9341_out("Lat: "); + i_to_a(text,gga.lat_deg,2); + ili9341_out(text); + ili9341_write(0x81); + i_to_a(text,gga.lat_min,2); + ili9341_out(text); + ili9341_out("'"); + + i_to_a(text,gga.lat_sec/1000,2); + ili9341_out(text); + ili9341_out(","); + i_to_a(text,gga.lat_sec%1000,3); + ili9341_out(text); + ili9341_out("\""); + + ili9341_out(lat_hemi[gga.lat_hemi]); + + ili9341_out(" Long: "); + i_to_a(text,gga.long_deg,3); + ili9341_out(text); + ili9341_write(0x81); + i_to_a(text,gga.long_min,2); + ili9341_out(text); + ili9341_out("'"); + i_to_a(text,gga.long_sec/1000,2); + ili9341_out(text); + ili9341_out(","); + i_to_a(text,gga.long_sec%1000,3); + ili9341_out(text); + ili9341_out("\""); + ili9341_out(long_hemi[gga.long_hemi]); + ili9341_out("\n"); + + ili9341_out("Altitude: "); + i_to_a(text,gga.altitude/10,3); + ili9341_out(text); + ili9341_out("."); + i_to_a(text,(gga.altitude%10),1); + ili9341_out(text); + ili9341_out("M\n"); + + + /* + i_to_a(text,gga.longitude,12); + ili9341_out(text); + ili9341_out("\n"); + i_to_a(text,gga.latitude,12); + ili9341_out(text); + ili9341_out("\n"); + */ + + /* + calc_locator(gga,text); + ili9341_out(text); + ili9341_out("\n"); + */ + + ili9341_out("Sats: "); + i_to_a(text,gga.sat_num,2); + ili9341_out(text); + ili9341_out(": "); + for(uint8_t i=0;i200000000) + { + freq1=0; + } + ili9341_setcursor(30,100); + show_frequency(freq1,0,multiplier); + /* + i_to_a(text,(frequency/1000000),3); + ili9341_out(text); + ili9341_out(" "); + i_to_a(text,(frequency/1000)%1000,3); + ili9341_out(text); + ili9341_out(" "); + i_to_a(text,(frequency%1000),3); + ili9341_out(text); + */ + si5351aSetFrequency(freq1,1); + break; + case 0xfd: + multiplier++; + if(multiplier==9) + { + multiplier=0; + } + show_frequency(freq1,0,multiplier); + break; + case 0xaa: + ili9341_setcursor(80,0); + ili9341_settextcolour(WHITE,DARKPURPLE); + OCXO_LOCK ? ili9341_out(ocxolock[1]) : ili9341_out(ocxolock[0]); + ili9341_settextcolour(WHITE,BLACK); + + } + keyfunc=0; + USART1->CR1 |= USART_CR1_RXNEIE; + } + } +} + +void RCC_Configuration(void) +{ + RCC->CR |= ((uint32_t)RCC_CR_HSEBYP); + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + while((RCC->CR & RCC_CR_HSERDY) == 0) {} + + FLASH->ACR |= FLASH_ACR_LATENCY | FLASH_ACR_PRFTBE; + + while((FLASH->ACR & FLASH_ACR_PRFTBS) == 0) {} + + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE_DIV1; + + if ((RCC->CFGR & RCC_CFGR_SWS) == RCC_CFGR_SWS_PLL) + { + RCC->CFGR &= (uint32_t) (~RCC_CFGR_SW); + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) + { + /* For robust implementation, add here time-out management */ + } + } + RCC->CR &= (uint32_t)(~RCC_CR_PLLON); + while((RCC->CR & RCC_CR_PLLRDY) != 0) + { + /* For robust implementation, add here time-out management */ + } + RCC->CFGR = (RCC->CFGR & (~RCC_CFGR_PLLMUL)) | (RCC_CFGR_PLLSRC_HSE_PREDIV) | (RCC_CFGR_PLLMUL4); + RCC->CR |= RCC_CR_PLLON; + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + /* For robust implementation, add here time-out management */ + } + RCC->CFGR |= (uint32_t) (RCC_CFGR_SW_PLL); + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) + { + /* For robust implementation, add here time-out management */ + } + + //RCC->CFGR |= RCC_CFGR_MCO_PLL; + + SystemCoreClockUpdate(); + + RCC->AHBENR |= RCC_AHBENR_GPIOAEN; + RCC->AHBENR |= RCC_AHBENR_GPIOBEN; + RCC->AHBENR |= RCC_AHBENR_GPIOCEN; + RCC->AHBENR |= RCC_AHBENR_GPIOFEN; + //RCC->AHBENR |= RCC_AHBENR_DMA1EN; + RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; + RCC->APB1ENR |= RCC_APB1ENR_I2C1EN; + RCC->APB2ENR |= RCC_APB2ENR_USART1EN; + RCC->APB1ENR |= RCC_APB1ENR_USART2EN; + RCC->APB2ENR |= RCC_APB2ENR_TIM15EN; + RCC->APB2ENR |= RCC_APB2ENR_TIM16EN; + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; + RCC->APB2ENR |= RCC_APB2ENR_SYSCFGCOMPEN; + +} + +extern void USART1_IRQHandler(void) +{ + struct buf_str *p; + register uint8_t tmp; + + if((USART1->ISR & USART_ISR_RTOF)) + { + USART1->ICR |= USART_ICR_RTOCF; + rx_finished=1; + } + + + if((USART1->ISR & USART_ISR_ORE)) + { + USART1->ICR |= USART_ICR_ORECF; + USART1->ISR &= ~USART_ISR_RXNE; + + + tmp=USART1->RDR; + + + } + + + if((USART1->ISR & USART_ISR_RXNE)) + { + tmp=USART1->RDR; + + if(tmp =='$'){ + GGA_Index = 0; + CommaCounter = 0; + IsItGGAString = 0; + IsItRMCString = 0; + IsItGSAString = 0; + IsItGLLString = 0; + } + else if(IsItGGAString == 1){ + if(tmp==',') GGA_Pointers[CommaCounter++] = GGA_Index; + GGA_Buffer[GGA_Index++] = tmp; + } + else if(IsItRMCString == 1) { + if(tmp==',') RMC_Pointers[CommaCounter++] = GGA_Index; + RMC_Buffer[GGA_Index++] = tmp; + } + else if(IsItGSAString == 1) { + if(tmp==',') GSA_Pointers[CommaCounter++] = GGA_Index; + GSA_Buffer[GGA_Index++] = tmp; + } + else if(IsItGLLString == 1) { + if(tmp==',') GLL_Pointers[CommaCounter++] = GGA_Index; + GLL_Buffer[GGA_Index++] = tmp; + /* + if(tmp==0xa) + { + rx_finished=1; + } + */ + } + else if(GGA_code[0] == 'G' && GGA_code[1] == 'G' && GGA_code[2] == 'A'){ + IsItGGAString = 1; + GGA_code[0] = 0; GGA_code[1] = 0; GGA_code[2] = 0; + } + else if(GGA_code[0] == 'R' && GGA_code[1] == 'M' && GGA_code[2] == 'C'){ + IsItRMCString = 1; + GGA_code[0] = 0; GGA_code[1] = 0; GGA_code[2] = 0; + } + else if(GGA_code[0] == 'G' && GGA_code[1] == 'S' && GGA_code[2] == 'A'){ + IsItGSAString = 1; + GGA_code[0] = 0; GGA_code[1] = 0; GGA_code[2] = 0; + } + else if(GGA_code[0] == 'G' && GGA_code[1] == 'L' && GGA_code[2] == 'L'){ + IsItGLLString = 1; + GGA_code[0] = 0; GGA_code[1] = 0; GGA_code[2] = 0; + } + else{ + GGA_code[0] = GGA_code[1]; GGA_code[1] = GGA_code[2]; GGA_code[2] = tmp; + } + + + } + + + + if((USART1->ISR & USART_ISR_TXE)) + { + p = &tx_buf; + if((p->in != p->out)) // && !(USART1->SR & USART_SR_CTS)) + { + USART1->TDR = (p->buf[p->out & 255]); + p->out++; + + } + else { + tx_restart=1; + USART1->CR1 &= ~(USART_CR1_TXEIE); + } + } +} + +extern void TIM15_IRQHandler(void) +{ + if(TIM15->SR & TIM_SR_UIF) // if UIF flag is set + { + keyfunc=0xaa; + + TIM15->SR &= ((uint16_t)~(0x1)); // clear UIF flag + } +} + +extern void TIM16_IRQHandler(void) +{ + if(TIM16->SR & TIM_SR_UIF) // if UIF flag is set + { + int8_t enc_new=0; + int8_t enc_diff=0; + int8_t enc_temp; + + enc_temp=enc_last; + + enc_new = 0; + if( !PHASE_A ) { + enc_new = 3; } + if( !PHASE_B ) { + enc_new ^= 1; } // convert gray to binary + enc_diff = enc_last - enc_new; // difference last - new + if( enc_diff & 1 ) { // bit 0 = value (1) + enc_last = enc_new; // store new as next last + enc_delta += (enc_diff & 2) - 1; } // bit 1 = direction (+/-) + if(enc_temp!=enc_last) { + keyfunc=0xfe; + } + + if(!KEY) { + btn_hb++; + } + else { + if(!btn_hb) {} // keyfunc==0xfe) { keypress=0; keyfunc=0; } + else if(btn_hb<1500) { + keyfunc=0xfd; + btn_hb=0xffff; + } + else if(btn_hb<3000) { + keyfunc=0xfc; + btn_hb=0xffff; + } + else if(btn_hb<4500) { + keyfunc=0xf9; + btn_hb=0xffff; + } + else if(btn_hb<6000) { + keyfunc=0xfb; + btn_hb=0xffff; + } + else if(btn_hb<7500) { + keyfunc=0xfa; + btn_hb=0xffff; + } + else if(btn_hb<0xffff) { + keyfunc=0xea; + btn_hb=0xffff; + } + + } + TIM16->SR &= ((uint16_t)~(0x1)); // clear UIF flag + } + +} +// ---------------------------------------------------------------------------- diff --git a/src/si5351a.c b/src/si5351a.c new file mode 100644 index 0000000..605889d --- /dev/null +++ b/src/si5351a.c @@ -0,0 +1,396 @@ +// +// Author: Hans Summers, 2015 +// Website: http://www.hanssummers.com +// +// A very very simple Si5351a demonstration +// using the Si5351a module kit http://www.hanssummers.com/synth +// Please also refer to SiLabs AN619 which describes all the registers to use +// + +#include "si5351a.h" + +void i2c_switch(uint8_t channel) +{ + if(!channel) + { + GPIOF->MODER &= ~(GPIO_MODER_MODER6 | GPIO_MODER_MODER7); + GPIOB->MODER |= (GPIO_MODER_MODER10_1 | GPIO_MODER_MODER11_1); + + } + else + { + GPIOB->MODER &= ~(GPIO_MODER_MODER10 | GPIO_MODER_MODER11); + GPIOF->MODER |= (GPIO_MODER_MODER6_1 | GPIO_MODER_MODER7_1); + } +} + +uint8_t i2cSendRegister(uint8_t i2c_chan, uint8_t reg, uint8_t reg_data) +{ + i2c_switch(i2c_chan); + + I2C2->CR1 &= ~I2C_CR1_PE; + i2c_autoend(I2C2,0); + i2c_set_nbytes(I2C2,4); + i2c_write_addr(I2C2,0x60,0); + i2c_tx_buf[0]=(reg); + i2c_tx_buf[1]=(reg_data); + I2C2->CR1 |= I2C_CR1_PE; + i2c_start(I2C2); + + while( ! (DMA1->ISR & DMA_ISR_TCIF4) ); + + i2c_stop(I2C2); + + return 0; +} + +uint8_t i2cReadRegister(uint8_t i2c_chan, uint8_t reg) //, uint8_t *read_data) +{ + uint8_t read_data; + + i2c_switch(i2c_chan); + i2c_autoend(I2C2,0); + i2c_set_nbytes(I2C2,1); + i2c_write_addr(I2C2,0x60,I2C_WRITE); + i2c_start(I2C2); + while(!(I2C2->ISR & I2C_ISR_TXIS)); + i2c_write(I2C2,reg); + while(!(I2C2->ISR & I2C_ISR_TC)); + i2c_stop(I2C2); + i2c_autoend(I2C2,1); + i2c_set_nbytes(I2C2,1); + i2c_write_addr(I2C2,0x60,I2C_READ); + i2c_start(I2C2); + read_data=(uint8_t)i2c_read_ack(I2C2); + i2c_reset(I2C2); + i2c_stop(I2C2); + + return read_data; +} + +// +// Set up specified PLL with mult, num and denom +// mult is 15..90 +// num is 0..1,048,575 (0xFFFFF) +// denom is 0..1,048,575 (0xFFFFF) +// + +void setupPLL(uint8_t i2c_chan, uint8_t pll, uint8_t mult, uint32_t num, uint32_t denom) +{ + uint32_t P1; // PLL config register P1 + uint32_t P2; // PLL config register P2 + uint32_t P3; // PLL config register P3 + + P1 = (uint32_t)(128 * ((float)num / (float)denom)); + P1 = (uint32_t)(128 * (uint32_t)(mult) + P1 - 512); + P2 = (uint32_t)(128 * ((float)num / (float)denom)); + P2 = (uint32_t)(128 * num - denom * P2); + P3 = denom; + i2cSendRegister(i2c_chan, SI_PLL_SRC, 0xc); + + i2cSendRegister(i2c_chan, pll + 0, (P3 & 0x0000FF00) >> 8); + i2cSendRegister(i2c_chan, pll + 1, (P3 & 0x000000FF)); + i2cSendRegister(i2c_chan, pll + 2, (P1 & 0x00030000) >> 16); + i2cSendRegister(i2c_chan, pll + 3, (P1 & 0x0000FF00) >> 8); + i2cSendRegister(i2c_chan, pll + 4, (P1 & 0x000000FF)); + i2cSendRegister(i2c_chan, pll + 5, ((P3 & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16)); + i2cSendRegister(i2c_chan, pll + 6, (P2 & 0x0000FF00) >> 8); + i2cSendRegister(i2c_chan, pll + 7, (P2 & 0x000000FF)); +} + +// +// Set up MultiSynth with integer div1 and R div1 +// R div1 is the bit value which is OR'ed onto the appropriate register, it is a #define in si5351a.h +// +void setupMultisynth(uint8_t i2c_chan, uint8_t synth, uint32_t div1, uint8_t rDiv) +{ + uint32_t P1; // Synth config register P1 + uint32_t P2; // Synth config register P2 + uint32_t P3; // Synth config register P3 + + P1 = 128 * div1 - 512; + P2 = 0; // P2 = 0, P3 = 1 forces an integer value for the div1 + P3 = 1; + + i2cSendRegister(i2c_chan, synth + 0, (P3 & 0x0000FF00) >> 8); + i2cSendRegister(i2c_chan, synth + 1, (P3 & 0x000000FF)); + i2cSendRegister(i2c_chan, synth + 2, ((P1 & 0x00030000) >> 16) | rDiv); + i2cSendRegister(i2c_chan, synth + 3, (P1 & 0x0000FF00) >> 8); + i2cSendRegister(i2c_chan, synth + 4, (P1 & 0x000000FF)); + i2cSendRegister(i2c_chan, synth + 5, ((P3 & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16)); + i2cSendRegister(i2c_chan, synth + 6, (P2 & 0x0000FF00) >> 8); + i2cSendRegister(i2c_chan, synth + 7, (P2 & 0x000000FF)); +} + +// +// Switches off Si5351a output +// Example: si5351aOutputOff(SI_CLK0_CONTROL); +// will switch off output CLK0 +// +void si5351aOutputOff(uint8_t output_status) +{ + uint8_t tmp; + + //tmp=(i2cReadRegister(I2C1, SI_CLK0_CONTROL) & 0x7f); + //tmp=tmp & 0x7f; + tmp=0x4f; + if(!(output_status & 0x1)) + { + tmp+=0x80; + } + i2cSendRegister(0, SI_CLK0_CONTROL, tmp); + + //tmp=(i2cReadRegister(I2C1, SI_CLK1_CONTROL) & 0x7f); + //tmp=tmp & 0x7f; + tmp=0x6f; + if(!(output_status & 0x2)) + { + tmp+=0x80; + } + i2cSendRegister(0, SI_CLK1_CONTROL, tmp); + + //tmp=(i2cReadRegister(I2C2, SI_CLK0_CONTROL) & 0x7f); + //tmp=tmp & 0x7f; + tmp=0x4f; + if(!(output_status & 0x4)) + { + tmp+=0x80; + } + i2cSendRegister(1, SI_CLK0_CONTROL, tmp); + + //tmp=(i2cReadRegister(I2C2, SI_CLK1_CONTROL) & 0x7f); + //tmp=tmp & 0x7f; + tmp=0x6f; + if(!(output_status & 0x8)) + { + tmp+=0x80; + } + i2cSendRegister(1, SI_CLK1_CONTROL, tmp); + +} + +// +// Set CLK0 output ON and to the specified frequency +// Frequency is in the range 1MHz to 150MHz +// Example: si5351aSetFrequency(10000000); +// will set output CLK0 to 10MHz +// +// This example sets up PLL A +// and MultiSynth 0 AND 1 +// and produces the output on CLK0 AND CLK1 +// + +/* +void si5351aSetFrequency(uint32_t frequency, uint8_t phase_off) +{ + uint32_t pllFreq; + uint32_t xtalFreq = XTAL_FREQ; + uint32_t l; + float f; + uint8_t multisynth_div=0; + uint16_t mult; + uint32_t num; + uint32_t denom; + uint32_t div1; + + denom = 1048575; // For simplicity we set the denominator to the maximum 1048575 + + if(frequency +#endif + +/*----------------------------------------------------------------------* + * Create a Timezone object from the given time change rules. * + *----------------------------------------------------------------------*/ +Timezone::Timezone(TimeChangeRule dstStart, TimeChangeRule stdStart) + : m_dst(dstStart), m_std(stdStart) +{ + initTimeChanges(); +} + +/*----------------------------------------------------------------------* + * Create a Timezone object for a zone that does not observe * + * daylight time. * + *----------------------------------------------------------------------*/ +Timezone::Timezone(TimeChangeRule stdTime) + : m_dst(stdTime), m_std(stdTime) +{ + initTimeChanges(); +} + +#ifdef __AVR__ +/*----------------------------------------------------------------------* + * Create a Timezone object from time change rules stored in EEPROM * + * at the given address. * + *----------------------------------------------------------------------*/ +Timezone::Timezone(int address) +{ + readRules(address); +} +#endif + +/*----------------------------------------------------------------------* + * Convert the given UTC time to local time, standard or * + * daylight time, as appropriate. * + *----------------------------------------------------------------------*/ +time_t Timezone::toLocal(time_t utc) +{ + // recalculate the time change points if needed + if (year(utc) != year(m_dstUTC)) calcTimeChanges(year(utc)); + + if (utcIsDST(utc)) + return utc + m_dst.offset * SECS_PER_MIN; + else + return utc + m_std.offset * SECS_PER_MIN; +} + +/*----------------------------------------------------------------------* + * Convert the given UTC time to local time, standard or * + * daylight time, as appropriate, and return a pointer to the time * + * change rule used to do the conversion. The caller must take care * + * not to alter this rule. * + *----------------------------------------------------------------------*/ +time_t Timezone::toLocal(time_t utc, TimeChangeRule **tcr) +{ + // recalculate the time change points if needed + if (year(utc) != year(m_dstUTC)) calcTimeChanges(year(utc)); + + if (utcIsDST(utc)) { + *tcr = &m_dst; + return utc + m_dst.offset * SECS_PER_MIN; + } + else { + *tcr = &m_std; + return utc + m_std.offset * SECS_PER_MIN; + } +} + +/*----------------------------------------------------------------------* + * Convert the given local time to UTC time. * + * * + * WARNING: * + * This function is provided for completeness, but should seldom be * + * needed and should be used sparingly and carefully. * + * * + * Ambiguous situations occur after the Standard-to-DST and the * + * DST-to-Standard time transitions. When changing to DST, there is * + * one hour of local time that does not exist, since the clock moves * + * forward one hour. Similarly, when changing to standard time, there * + * is one hour of local times that occur twice since the clock moves * + * back one hour. * + * * + * This function does not test whether it is passed an erroneous time * + * value during the Local -> DST transition that does not exist. * + * If passed such a time, an incorrect UTC time value will be returned. * + * * + * If passed a local time value during the DST -> Local transition * + * that occurs twice, it will be treated as the earlier time, i.e. * + * the time that occurs before the transistion. * + * * + * Calling this function with local times during a transition interval * + * should be avoided! * + *----------------------------------------------------------------------*/ +time_t Timezone::toUTC(time_t local) +{ + // recalculate the time change points if needed + if (year(local) != year(m_dstLoc)) calcTimeChanges(year(local)); + + if (locIsDST(local)) + return local - m_dst.offset * SECS_PER_MIN; + else + return local - m_std.offset * SECS_PER_MIN; +} + +/*----------------------------------------------------------------------* + * Determine whether the given UTC time_t is within the DST interval * + * or the Standard time interval. * + *----------------------------------------------------------------------*/ +bool Timezone::utcIsDST(time_t utc) +{ + // recalculate the time change points if needed + if (year(utc) != year(m_dstUTC)) calcTimeChanges(year(utc)); + + if (m_stdUTC == m_dstUTC) // daylight time not observed in this tz + return false; + else if (m_stdUTC > m_dstUTC) // northern hemisphere + return (utc >= m_dstUTC && utc < m_stdUTC); + else // southern hemisphere + return !(utc >= m_stdUTC && utc < m_dstUTC); +} + +/*----------------------------------------------------------------------* + * Determine whether the given Local time_t is within the DST interval * + * or the Standard time interval. * + *----------------------------------------------------------------------*/ +bool Timezone::locIsDST(time_t local) +{ + // recalculate the time change points if needed + if (year(local) != year(m_dstLoc)) calcTimeChanges(year(local)); + + if (m_stdUTC == m_dstUTC) // daylight time not observed in this tz + return false; + else if (m_stdLoc > m_dstLoc) // northern hemisphere + return (local >= m_dstLoc && local < m_stdLoc); + else // southern hemisphere + return !(local >= m_stdLoc && local < m_dstLoc); +} + +/*----------------------------------------------------------------------* + * Calculate the DST and standard time change points for the given * + * given year as local and UTC time_t values. * + *----------------------------------------------------------------------*/ +void Timezone::calcTimeChanges(int yr) +{ + m_dstLoc = toTime_t(m_dst, yr); + m_stdLoc = toTime_t(m_std, yr); + m_dstUTC = m_dstLoc - m_std.offset * SECS_PER_MIN; + m_stdUTC = m_stdLoc - m_dst.offset * SECS_PER_MIN; +} + +/*----------------------------------------------------------------------* + * Initialize the DST and standard time change points. * + *----------------------------------------------------------------------*/ +void Timezone::initTimeChanges() +{ + m_dstLoc = 0; + m_stdLoc = 0; + m_dstUTC = 0; + m_stdUTC = 0; +} + +/*----------------------------------------------------------------------* + * Convert the given time change rule to a time_t value * + * for the given year. * + *----------------------------------------------------------------------*/ +time_t Timezone::toTime_t(TimeChangeRule r, int yr) +{ + uint8_t m = r.month; // temp copies of r.month and r.week + uint8_t w = r.week; + if (w == 0) // is this a "Last week" rule? + { + if (++m > 12) // yes, for "Last", go to the next month + { + m = 1; + ++yr; + } + w = 1; // and treat as first week of next month, subtract 7 days later + } + + // calculate first day of the month, or for "Last" rules, first day of the next month + tmElements_t tm; + tm.Hour = r.hour; + tm.Minute = 0; + tm.Second = 0; + tm.Day = 1; + tm.Month = m; + tm.Year = yr - 1970; + time_t t = makeTime(tm); + + // add offset from the first of the month to r.dow, and offset for the given week + t += ( (r.dow - weekday(t) + 7) % 7 + (w - 1) * 7 ) * SECS_PER_DAY; + // back up a week if this is a "Last" rule + if (r.week == 0) t -= 7 * SECS_PER_DAY; + return t; +} + +/*----------------------------------------------------------------------* + * Read or update the daylight and standard time rules from RAM. * + *----------------------------------------------------------------------*/ +void Timezone::setRules(TimeChangeRule dstStart, TimeChangeRule stdStart) +{ + m_dst = dstStart; + m_std = stdStart; + initTimeChanges(); // force calcTimeChanges() at next conversion call +} + +#ifdef __AVR__ +/*----------------------------------------------------------------------* + * Read the daylight and standard time rules from EEPROM at * + * the given address. * + *----------------------------------------------------------------------*/ +void Timezone::readRules(int address) +{ + eeprom_read_block((void *) &m_dst, (void *) address, sizeof(m_dst)); + address += sizeof(m_dst); + eeprom_read_block((void *) &m_std, (void *) address, sizeof(m_std)); + initTimeChanges(); // force calcTimeChanges() at next conversion call +} + +/*----------------------------------------------------------------------* + * Write the daylight and standard time rules to EEPROM at * + * the given address. * + *----------------------------------------------------------------------*/ +void Timezone::writeRules(int address) +{ + eeprom_write_block((void *) &m_dst, (void *) address, sizeof(m_dst)); + address += sizeof(m_dst); + eeprom_write_block((void *) &m_std, (void *) address, sizeof(m_std)); +} + +#endif diff --git a/system/include/arm/semihosting.h b/system/include/arm/semihosting.h new file mode 100644 index 0000000..be713b2 --- /dev/null +++ b/system/include/arm/semihosting.h @@ -0,0 +1,142 @@ +/* + * This file is part of the ??OS++ distribution. + * (https://github.com/micro-os-plus) + * Copyright (c) 2014 Liviu Ionescu. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef ARM_SEMIHOSTING_H_ +#define ARM_SEMIHOSTING_H_ + +// ---------------------------------------------------------------------------- + +// Semihosting operations. +enum OperationNumber +{ + // Regular operations + SEMIHOSTING_EnterSVC = 0x17, + SEMIHOSTING_ReportException = 0x18, + SEMIHOSTING_SYS_CLOSE = 0x02, + SEMIHOSTING_SYS_CLOCK = 0x10, + SEMIHOSTING_SYS_ELAPSED = 0x30, + SEMIHOSTING_SYS_ERRNO = 0x13, + SEMIHOSTING_SYS_FLEN = 0x0C, + SEMIHOSTING_SYS_GET_CMDLINE = 0x15, + SEMIHOSTING_SYS_HEAPINFO = 0x16, + SEMIHOSTING_SYS_ISERROR = 0x08, + SEMIHOSTING_SYS_ISTTY = 0x09, + SEMIHOSTING_SYS_OPEN = 0x01, + SEMIHOSTING_SYS_READ = 0x06, + SEMIHOSTING_SYS_READC = 0x07, + SEMIHOSTING_SYS_REMOVE = 0x0E, + SEMIHOSTING_SYS_RENAME = 0x0F, + SEMIHOSTING_SYS_SEEK = 0x0A, + SEMIHOSTING_SYS_SYSTEM = 0x12, + SEMIHOSTING_SYS_TICKFREQ = 0x31, + SEMIHOSTING_SYS_TIME = 0x11, + SEMIHOSTING_SYS_TMPNAM = 0x0D, + SEMIHOSTING_SYS_WRITE = 0x05, + SEMIHOSTING_SYS_WRITEC = 0x03, + SEMIHOSTING_SYS_WRITE0 = 0x04, + + // Codes returned by SEMIHOSTING_ReportException + ADP_Stopped_ApplicationExit = ((2 << 16) + 38), + ADP_Stopped_RunTimeError = ((2 << 16) + 35), + +}; + +// ---------------------------------------------------------------------------- + +// SWI numbers and reason codes for RDI (Angel) monitors. +#define AngelSWI_ARM 0x123456 +#ifdef __thumb__ +#define AngelSWI 0xAB +#else +#define AngelSWI AngelSWI_ARM +#endif +// For thumb only architectures use the BKPT instruction instead of SWI. +#if defined(__ARM_ARCH_7M__) \ + || defined(__ARM_ARCH_7EM__) \ + || defined(__ARM_ARCH_6M__) +#define AngelSWIInsn "bkpt" +#define AngelSWIAsm bkpt +#else +#define AngelSWIInsn "swi" +#define AngelSWIAsm swi +#endif + +#if defined(OS_DEBUG_SEMIHOSTING_FAULTS) +// Testing the local semihosting handler cannot use another BKPT, since this +// configuration cannot trigger HaedFault exceptions while the debugger is +// connected, so we use an illegal op code, that will trigger an +// UsageFault exception. +#define AngelSWITestFault "setend be" +#define AngelSWITestFaultOpCode (0xB658) +#endif + +static inline int +__attribute__ ((always_inline)) +call_host (int reason, void* arg) +{ + int value; + asm volatile ( + + " mov r0, %[rsn] \n" + " mov r1, %[arg] \n" +#if defined(OS_DEBUG_SEMIHOSTING_FAULTS) + " " AngelSWITestFault " \n" +#else + " " AngelSWIInsn " %[swi] \n" +#endif + " mov %[val], r0" + + : [val] "=r" (value) /* Outputs */ + : [rsn] "r" (reason), [arg] "r" (arg), [swi] "i" (AngelSWI) /* Inputs */ + : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc" + // Clobbers r0 and r1, and lr if in supervisor mode + ); + + // Accordingly to page 13-77 of ARM DUI 0040D other registers + // can also be clobbered. Some memory positions may also be + // changed by a system call, so they should not be kept in + // registers. Note: we are assuming the manual is right and + // Angel is respecting the APCS. + return value; +} + +// ---------------------------------------------------------------------------- + +// Function used in _exit() to return the status code as Angel exception. +static inline void +__attribute__ ((always_inline,noreturn)) +report_exception (int reason) +{ + call_host (SEMIHOSTING_ReportException, (void*) reason); + + for (;;) + ; +} + +// ---------------------------------------------------------------------------- + +#endif // ARM_SEMIHOSTING_H_ diff --git a/system/include/cmsis/.stm32f0xx.h.swp b/system/include/cmsis/.stm32f0xx.h.swp new file mode 100644 index 0000000000000000000000000000000000000000..d87aaef9c292ebff2da8179704339b2fbf26442e GIT binary patch literal 16384 zcmeI2d2k!m9mkie(9m#%q%(Br@M4D~c5KPEa*+gxVmnwv>;&5hWF`}3y;|ElNV{Tp z72AaXZRre@o6-V>mU4y`8jch~pioLn8z^TFjzUXQC_MrxS4*3w(C^#*J!$omoC!1h z(?L7)wXOZU-|zk2Z{NArK+CFBx0oMm)o>lAX+7I6UU&6mp*>vCw7l*adN$_eUCSPl ze4Hz%kB*qx>^QV^JHB3b>vK2;(LR* z%3q%G9mE^S{w~Jk@4pl-}j*M_@85Z7URDmuJY5*_^+A$ z*^K{+@mm@HCF9RB{w#4des(eb46~p1>GJkH&3HHCPcgop@h2I-j`1gmtNCdg&R8el&5N@%vf*=PDuCf-5*6Ni-7e;0AJKO15EPU4MZzlrfXh^zd)!1yNO39{e+ z(DM4fPrRA+42V ze=Fm+5LfM6!}!h2|M`sHL_8K&t8HfdM&h%HZ)f}l;`515IXwJB#eY5Vxx~8}{|<50 zKfcWPb;OS&`}-OHHgT2z_Zj~dah0E=CzZ!{EpatJEMxo{;%a=kjDM4OisIYM_|?SK z{(U#&SF!r%A5k9PmBdy5Sj+e~h__Px=P~|u;wnE|8NY(rZ)f~##1rIy(&X~^E+-x* z-pTl7%)ih0rNq_zdo$yg5I=_eKf(CL#MStGoAHZ?tNa}`r9A!%i7z1kOBug_cqj35 z82>8qF5-_eem-$^zMA;i^7_f_6ZcEcXqp_8kI9JwbILl(z;4Wsw?UUfd1wuEJoFys z{TrdR&!fR2PFL-L&UD9&Od&`juHXeZ8=&q7G}H;nbM4bO z`(6cI2`z=*!CC!H=nZHSv;nf9Ug%`#FlaaO{~Gi-B%g(Pzd(;;FMidVcE%bM@kY_t z-<@b%+H&ft>17?FF|G+wpD_n5+Z6I5nrPMPtwG#ZH-h3C%$H{~W%op2Z26XBH;J5X z**;`u#GvDftU06`VGYw zVrU`^BuE2H*IS0^HHk5&APn86I)y)M5)+m!p(}jH$r{6GwJ@Aq-pZP;$h&6Vbztu~ zZcN4{`mOu|(eDU-y<=rW4&QJY9K-i!;Lq~JAdG~m8^gl4a%NDaZ6b%hBfJsI$Nd4* zA2Cf^R_~db7RD%lQex({j4qLxDSez9`Iu-KZI_L!NPeOvTBNcOXh;1X;lqT`}l@S_F#xMjAMwVj$dD5kFcd^Da6!p z6lH|!tn!&Oi0RX-lDXB1%vu8)Ud>%wb(7iS+&{K8D8EJy8rk~hEu^q zk5^*~wWx|3#o{wCgz!txWPE4Hbqaa0%o=cYcPwo<_MkOXaDyDr>My-u8==CpL$$Y%?l6lNrv{nF{;B$MuvC2cwVmERS(_83?3TV~oGi?w(6rTR)m z8b8iURxBm5R?hN+#CW2B#$cwxZ?dO9)!8SO_loxAJsqk3)bbvD zS}Kw~tHnvFo{lDATByUtlfg9Uc>)WCl|x@LGht8}%ky1ppx~oFRKzVXT}BI_^I>wX zOZJIWU!7QzL|&VMM9;W5OAbtEAAeV&w5@uj=}-^agKn- zAlX3&{G7EIe1t1Q$kHy_xg*ci)$CMM<5?A=@(?RhjJX9g+o3fOh% z$QJrRS6^p1q=L#yKkC%fxw5YllV`_@&fe6Du5?FlYE@@%U1bbHAV+fK`-nqiTnkf* zCz2~t4NbU(&h6xb)dYWGUPtH2X2Wq?&6VL~WS>WJ2C&fRa`C`ikik$leD#3wsKUC$L=z9xy~-dexCZm;*9PGC##k@%^jv;<}mR# z%Xu=aM~(owfm+oXn-gmZ@97197+p|ct`^BiFY7n;Tv#G_42Z6{+rW3)vBZ3=m)vq` z^89}!&d0~$Y%S0KOX#Gz{ZLKY2pQ1lq33bdzYJOht%Qz+1oQ^Z{F@*fia|T&nIAeA zItiKt9S-fl+5avm2hD)C(dZGtvJH$c}z*FaZ5mp~UoGAE0m z+EvRyEd#X-)G|=ZKrI823}6FM{Sq_V8zQI1$^&D#mFev1knatarj~U|KXGg+!dFjt z6|@0=%MD7|t>8v|@kMvps~c%aFNL%X)!qY@z1Z0h?0!nsRlb1g9L>v3VJ4lEr^=#h zyi8Xc;=1DQEO<*58?IB;Ry!_*EfKOkLF=kEuGBW#3Wu*zi?6U&_9c7!6Y1IMRPV`M zI8(}3(d?okb0bB#`TPiD)?!cQ{i*J`>5gRk9?XLxrQnJ+Cp+3()9uTVOo|~S>o$w;#dzlSmlx~B=1bmeWA`g4-r7fLMURu*_<9m_iN>vn- zK^3(|7=H}WSfb^MK6=~R)9t-|dvGCSkx1=$6Q9JJBoA*Rlq3T|x+R8dsbt~1eN=DJ_M!HngoEJeNE9@&fQ^~{L z*jIL=>h{!)D(Vk9M#-e?Aw}yC%M~9`r0a}hth$bkS+cUz*mA0^H?#P!LvXsr8xQp# zk?_A8#hS_Lib folder. + * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7l_math.lib (Little endian on Cortex-M7) + * - arm_cortexM7b_math.lib (Big endian on Cortex-M7) + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK-ARM version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * ------------ + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined __CC_ARM + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined __GNUC__ + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined __ICCARM__ + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED + +#elif defined __CSMC__ + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED + +#elif defined __TASKING__ + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED + +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + +/* + #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) + #define __CLZ __clz + #endif + */ +/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) + static __INLINE uint32_t __CLZ( + q31_t data); + + static __INLINE uint32_t __CLZ( + q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); + } +#endif + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + } +#endif /* end of ARM_MATH_CM0_FAMILY */ + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + static __INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + static __INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + static __INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + static __INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + static __INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + static __INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + static __INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + static __INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + static __INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + static __INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + static __INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + static __INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + static __INLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + static __INLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + static __INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + static __INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + static __INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + static __INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + static __INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + static __INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + static __INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + static __INLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0_FAMILY + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + */ + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + */ + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + static __INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + static __INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + static __INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if(in >= 0.0f) + { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + static __INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + static __INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + static __INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + static __INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + static __INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + static __INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) + #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__CSMC__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__TASKING__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/system/include/cmsis/cmsis_armcc.h b/system/include/cmsis/cmsis_armcc.h new file mode 100644 index 0000000..74c49c6 --- /dev/null +++ b/system/include/cmsis/cmsis_armcc.h @@ -0,0 +1,734 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return(result); +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/system/include/cmsis/cmsis_armcc_V6.h b/system/include/cmsis/cmsis_armcc_V6.h new file mode 100644 index 0000000..cd13240 --- /dev/null +++ b/system/include/cmsis/cmsis_armcc_V6.h @@ -0,0 +1,1800 @@ +/**************************************************************************//** + * @file cmsis_armcc_V6.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_V6_H +#define __CMSIS_ARMCC_V6_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get IPSR Register (non-secure) + \details Returns the content of the non-secure IPSR Register when in secure state. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get APSR Register (non-secure) + \details Returns the content of the non-secure APSR Register when in secure state. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get xPSR Register (non-secure) + \details Returns the content of the non-secure xPSR Register when in secure state. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp"); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp"); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Base Priority with condition (non_secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value) +{ + __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory"); +} +#endif + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + + +#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + +#if (__ARM_ARCH_8M__ == 1U) + +/** + \brief Get Process Stack Pointer Limit + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Get Process Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Get Main Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Set Main Stack Pointer Limit (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +} +#endif + +#endif /* (__ARM_ARCH_8M__ == 1U) */ + + +#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */ + +/** + \brief Get FPSCR + \details eturns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#define __get_FPSCR __builtin_arm_get_fpscr +#if 0 +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} +#endif + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get FPSCR (non-secure) + \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state. + \return Floating Point Status/Control register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} +#endif + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#define __set_FPSCR __builtin_arm_set_fpscr +#if 0 +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} +#endif + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set FPSCR (non-secure) + \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} +#endif + +#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __builtin_bswap32 + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ +#if 0 +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} +#endif + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ + /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ + /* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +/*#define __SSAT __builtin_arm_ssat*/ +#define __SSAT(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat +#if 0 +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) +#endif + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + +#if (__ARM_ARCH_8M__ == 1U) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* (__ARM_ARCH_8M__ == 1U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */ + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1U) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_V6_H */ diff --git a/system/include/cmsis/cmsis_device.h b/system/include/cmsis/cmsis_device.h new file mode 100644 index 0000000..9c74ee2 --- /dev/null +++ b/system/include/cmsis/cmsis_device.h @@ -0,0 +1,33 @@ +/* + * This file is part of the ??OS++ distribution. + * (https://github.com/micro-os-plus) + * Copyright (c) 2014 Liviu Ionescu. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef STM32F0_CMSIS_DEVICE_H_ +#define STM32F0_CMSIS_DEVICE_H_ + +#include "stm32f0xx.h" + +#endif // STM32F0_CMSIS_DEVICE_H_ diff --git a/system/include/cmsis/cmsis_gcc.h b/system/include/cmsis/cmsis_gcc.h new file mode 100644 index 0000000..bb89fbb --- /dev/null +++ b/system/include/cmsis/cmsis_gcc.h @@ -0,0 +1,1373 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* __CMSIS_GCC_H */ diff --git a/system/include/cmsis/core_cm0.h b/system/include/cmsis/core_cm0.h new file mode 100644 index 0000000..a881376 --- /dev/null +++ b/system/include/cmsis/core_cm0.h @@ -0,0 +1,811 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +// [ILG] +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +// [ILG] +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* __CMSIS_GENERIC */ diff --git a/system/include/cmsis/core_cm0plus.h b/system/include/cmsis/core_cm0plus.h new file mode 100644 index 0000000..dd2559a --- /dev/null +++ b/system/include/cmsis/core_cm0plus.h @@ -0,0 +1,927 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +// [ILG] +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +// [ILG] +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* __CMSIS_GENERIC */ diff --git a/system/include/cmsis/core_cm3.h b/system/include/cmsis/core_cm3.h new file mode 100644 index 0000000..c8a4d3d --- /dev/null +++ b/system/include/cmsis/core_cm3.h @@ -0,0 +1,1776 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +// [ILG] +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U)) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +// [ILG] +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* __CMSIS_GENERIC */ diff --git a/system/include/cmsis/core_cm4.h b/system/include/cmsis/core_cm4.h new file mode 100644 index 0000000..e62f7af --- /dev/null +++ b/system/include/cmsis/core_cm4.h @@ -0,0 +1,1950 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +// [ILG] +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ +#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1U) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +// [ILG] +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* __CMSIS_GENERIC */ diff --git a/system/include/cmsis/core_cm7.h b/system/include/cmsis/core_cm7.h new file mode 100644 index 0000000..b7d370b --- /dev/null +++ b/system/include/cmsis/core_cm7.h @@ -0,0 +1,2525 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +// [ILG] +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x07U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ +#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1U) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & 0x00000FF0UL) == 0x220UL) + { + return 2UL; /* Double + Single precision FPU */ + } + else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) + { + return 1UL; /* Single precision FPU */ + } + else + { + return 0UL; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +// [ILG] +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* __CMSIS_GENERIC */ diff --git a/system/include/cmsis/core_cmFunc.h b/system/include/cmsis/core_cmFunc.h new file mode 100644 index 0000000..652a48a --- /dev/null +++ b/system/include/cmsis/core_cmFunc.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/system/include/cmsis/core_cmInstr.h b/system/include/cmsis/core_cmInstr.h new file mode 100644 index 0000000..f474b0e --- /dev/null +++ b/system/include/cmsis/core_cmInstr.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/system/include/cmsis/core_cmSimd.h b/system/include/cmsis/core_cmSimd.h new file mode 100644 index 0000000..66bf5c2 --- /dev/null +++ b/system/include/cmsis/core_cmSimd.h @@ -0,0 +1,96 @@ +/**************************************************************************//** + * @file core_cmSimd.h + * @brief CMSIS Cortex-M SIMD Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMSIMD_H +#define __CORE_CMSIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CMSIMD_H */ diff --git a/system/include/cmsis/core_sc000.h b/system/include/cmsis/core_sc000.h new file mode 100644 index 0000000..514dbd8 --- /dev/null +++ b/system/include/cmsis/core_sc000.h @@ -0,0 +1,926 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of SC000 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/system/include/cmsis/core_sc300.h b/system/include/cmsis/core_sc300.h new file mode 100644 index 0000000..8bd18aa --- /dev/null +++ b/system/include/cmsis/core_sc300.h @@ -0,0 +1,1745 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/system/include/cmsis/stm32f030xc.h b/system/include/cmsis/stm32f030xc.h new file mode 100644 index 0000000..36dfa96 --- /dev/null +++ b/system/include/cmsis/stm32f030xc.h @@ -0,0 +1,2761 @@ +/** + ****************************************************************************** + * @file stm32f030xc.h + * @author MCD Application Team + * @version V2.3.0 + * @date 27-May-2016 + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F0xx devices. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral�s registers hardware + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f030xc + * @{ + */ + +#ifndef __STM32F030xC_H +#define __STM32F030xC_H + +#ifdef __cplusplus + extern C { +#endif /* __cplusplus */ + + /** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M0 Processor and Core Peripherals + */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F0xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + +typedef enum +{ +/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ + +/****** STM32F0 specific Interrupt Numbers ******************************************************************/ +} IRQn_Type; + +/** + * @} + */ + +#include core_cm0.h /* Cortex-M0 processor and core peripherals */ +#include system_stm32f0xx.h /* STM32F0xx System Header */ +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ +} ADC_TypeDef; + +typedef struct +{ +} ADC_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ +} CRC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ +} DMA_Channel_TypeDef; + +typedef struct +{ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ +} FLASH_TypeDef; + +/** + * @brief Option Bytes Registers + */ +typedef struct +{ +} OB_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ +} GPIO_TypeDef; + +/** + * @brief SysTem Configuration + */ + +typedef struct +{ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +typedef struct +{ +} RTC_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ +} SPI_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ +typedef struct +{ +} WWDG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + + +#define APBPERIPH_BASE PERIPH_BASE +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000) + +#define TIM3_BASE (APBPERIPH_BASE + 0x00000400) +#define TIM6_BASE (APBPERIPH_BASE + 0x00001000) +#define TIM7_BASE (APBPERIPH_BASE + 0x00001400) +#define TIM14_BASE (APBPERIPH_BASE + 0x00002000) +#define RTC_BASE (APBPERIPH_BASE + 0x00002800) +#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00) +#define IWDG_BASE (APBPERIPH_BASE + 0x00003000) +#define SPI2_BASE (APBPERIPH_BASE + 0x00003800) +#define USART2_BASE (APBPERIPH_BASE + 0x00004400) +#define USART3_BASE (APBPERIPH_BASE + 0x00004800) +#define USART4_BASE (APBPERIPH_BASE + 0x00004C00) +#define USART5_BASE (APBPERIPH_BASE + 0x00005000) +#define I2C1_BASE (APBPERIPH_BASE + 0x00005400) +#define I2C2_BASE (APBPERIPH_BASE + 0x00005800) +#define PWR_BASE (APBPERIPH_BASE + 0x00007000) +#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000) +#define EXTI_BASE (APBPERIPH_BASE + 0x00010400) +#define USART6_BASE (APBPERIPH_BASE + 0x00011400) +#define ADC1_BASE (APBPERIPH_BASE + 0x00012400) +#define ADC_BASE (APBPERIPH_BASE + 0x00012708) +#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00) +#define SPI1_BASE (APBPERIPH_BASE + 0x00013000) +#define USART1_BASE (APBPERIPH_BASE + 0x00013800) +#define TIM15_BASE (APBPERIPH_BASE + 0x00014000) +#define TIM16_BASE (APBPERIPH_BASE + 0x00014400) +#define TIM17_BASE (APBPERIPH_BASE + 0x00014800) +#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000) +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058) + +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000) + +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00) +#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400) + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define USART4 ((USART_TypeDef *) USART4_BASE) +#define USART5 ((USART_TypeDef *) USART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) /* Kept for legacy purpose */ +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define OB ((OB_TypeDef *) OB_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + */ +/* Note: No specific macro feature on this device */ + +/******************** Bits definition for ADC_ISR register ******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_AWD1_Pos (7U) + +/* Legacy defines */ +#define ADC_ISR_AWD (ADC_ISR_AWD1) +#define ADC_ISR_EOSEQ (ADC_ISR_EOS) + +/******************** Bits definition for ADC_IER register ******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_AWD1IE_Pos (7U) + +/* Legacy defines */ +#define ADC_IER_AWDIE (ADC_IER_AWD1IE) +#define ADC_IER_EOSEQIE (ADC_IER_EOSIE) + +/******************** Bits definition for ADC_CR register *******************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADCAL_Pos (31U) + +/******************* Bits definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_SCANDIR_Pos (2U) + +#define ADC_CFGR1_RES_Pos (3U) + +#define ADC_CFGR1_ALIGN_Pos (5U) + +#define ADC_CFGR1_EXTSEL_Pos (6U) + +#define ADC_CFGR1_EXTEN_Pos (10U) + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_AUTOFF_Pos (15U) +#define ADC_CFGR1_DISCEN_Pos (16U) + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1EN_Pos (23U) + +#define ADC_CFGR1_AWD1CH_Pos (26U) + +/* Legacy defines */ +#define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT) +#define ADC_CFGR1_AWDSGL (ADC_CFGR1_AWD1SGL) +#define ADC_CFGR1_AWDEN (ADC_CFGR1_AWD1EN) +#define ADC_CFGR1_AWDCH (ADC_CFGR1_AWD1CH) +#define ADC_CFGR1_AWDCH_0 (ADC_CFGR1_AWD1CH_0) +#define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1) +#define ADC_CFGR1_AWDCH_2 (ADC_CFGR1_AWD1CH_2) +#define ADC_CFGR1_AWDCH_3 (ADC_CFGR1_AWD1CH_3) +#define ADC_CFGR1_AWDCH_4 (ADC_CFGR1_AWD1CH_4) + +/******************* Bits definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_CKMODE_Pos (30U) + +/* Legacy defines */ + +/****************** Bit definition for ADC_SMPR register ********************/ +#define ADC_SMPR_SMP_Pos (0U) + +/* Legacy defines */ + +/******************* Bit definition for ADC_TR register ********************/ +#define ADC_TR1_LT1_Pos (0U) + +#define ADC_TR1_HT1_Pos (16U) + +/* Legacy defines */ +#define ADC_TR_HT (ADC_TR1_HT1) +#define ADC_TR_LT (ADC_TR1_LT1) +#define ADC_HTR_HT (ADC_TR1_HT1) +#define ADC_LTR_LT (ADC_TR1_LT1) + +/****************** Bit definition for ADC_CHSELR register ******************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL0_Pos (0U) + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0U) + +/************************* ADC Common registers *****************************/ +/******************* Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_TSEN_Pos (23U) + + +/******************************************************************************/ +/* */ +/* CRC calculation unit (CRC) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) + +/******************* Bit definition for CRC_IDR register ********************/ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_OUT_Pos (7U) + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) + +/******************************************************************************/ +/* */ +/* Debug MCU (DBGMCU) */ +/* */ +/******************************************************************************/ + +/**************** Bit definition for DBGMCU_IDCODE register *****************/ +#define DBGMCU_IDCODE_DEV_ID_Pos (0U) + +#define DBGMCU_IDCODE_REV_ID_Pos (16U) + +/****************** Bit definition for DBGMCU_CR register *******************/ +#define DBGMCU_CR_DBG_STOP_Pos (1U) +#define DBGMCU_CR_DBG_STANDBY_Pos (2U) + +/****************** Bit definition for DBGMCU_APB1_FZ register **************/ +#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U) +#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U) +#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U) +#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U) +#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) +#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) +#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) +#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U) + +/****************** Bit definition for DBGMCU_APB2_FZ register **************/ +#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (11U) +#define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos (16U) +#define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (17U) +#define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (18U) + +/******************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_TEIF5_Pos (19U) + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CTEIF5_Pos (19U) + +/******************* Bit definition for DMA_CCR register ********************/ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_MINC_Pos (7U) + +#define DMA_CCR_PSIZE_Pos (8U) + +#define DMA_CCR_MSIZE_Pos (10U) + +#define DMA_CCR_PL_Pos (12U) + +#define DMA_CCR_MEM2MEM_Pos (14U) + +/****************** Bit definition for DMA_CNDTR register *******************/ +#define DMA_CNDTR_NDT_Pos (0U) + +/****************** Bit definition for DMA_CPAR register ********************/ +#define DMA_CPAR_PA_Pos (0U) + +/****************** Bit definition for DMA_CMAR register ********************/ +#define DMA_CMAR_MA_Pos (0U) + +/****************** Bit definition for DMA1_CSELR register ********************/ +#define DMA_CSELR_C1S_Pos (0U) +#define DMA_CSELR_C2S_Pos (4U) +#define DMA_CSELR_C3S_Pos (8U) +#define DMA_CSELR_C4S_Pos (12U) +#define DMA_CSELR_C5S_Pos (16U) +#define DMA_CSELR_C6S_Pos (20U) +#define DMA_CSELR_C7S_Pos (24U) + +#define DMA1_CSELR_CH1_ADC_Pos (0U) +#define DMA1_CSELR_CH1_TIM17_CH1_Pos (0U) +#define DMA1_CSELR_CH1_TIM17_UP_Pos (0U) +#define DMA1_CSELR_CH1_USART1_RX_Pos (3U) +#define DMA1_CSELR_CH1_USART2_RX_Pos (0U) +#define DMA1_CSELR_CH1_USART3_RX_Pos (1U) +#define DMA1_CSELR_CH1_USART4_RX_Pos (0U) +#define DMA1_CSELR_CH1_USART5_RX_Pos (2U) +#define DMA1_CSELR_CH1_USART6_RX_Pos (0U) +#define DMA1_CSELR_CH2_ADC_Pos (4U) +#define DMA1_CSELR_CH2_I2C1_TX_Pos (5U) +#define DMA1_CSELR_CH2_SPI1_RX_Pos (4U) +#define DMA1_CSELR_CH2_TIM1_CH1_Pos (6U) +#define DMA1_CSELR_CH2_TIM17_CH1_Pos (4U) +#define DMA1_CSELR_CH2_TIM17_UP_Pos (4U) +#define DMA1_CSELR_CH2_USART1_TX_Pos (7U) +#define DMA1_CSELR_CH2_USART2_TX_Pos (4U) +#define DMA1_CSELR_CH2_USART3_TX_Pos (5U) +#define DMA1_CSELR_CH2_USART4_TX_Pos (4U) +#define DMA1_CSELR_CH2_USART5_TX_Pos (6U) +#define DMA1_CSELR_CH2_USART6_TX_Pos (4U) +#define DMA1_CSELR_CH3_TIM6_UP_Pos (8U) +#define DMA1_CSELR_CH3_I2C1_RX_Pos (9U) +#define DMA1_CSELR_CH3_SPI1_TX_Pos (8U) +#define DMA1_CSELR_CH3_TIM1_CH2_Pos (10U) +#define DMA1_CSELR_CH3_TIM16_CH1_Pos (8U) +#define DMA1_CSELR_CH3_TIM16_UP_Pos (8U) +#define DMA1_CSELR_CH3_USART1_RX_Pos (11U) +#define DMA1_CSELR_CH3_USART2_RX_Pos (8U) +#define DMA1_CSELR_CH3_USART3_RX_Pos (9U) +#define DMA1_CSELR_CH3_USART4_RX_Pos (8U) +#define DMA1_CSELR_CH3_USART5_RX_Pos (10U) +#define DMA1_CSELR_CH3_USART6_RX_Pos (8U) +#define DMA1_CSELR_CH4_TIM7_UP_Pos (12U) +#define DMA1_CSELR_CH4_I2C2_TX_Pos (13U) +#define DMA1_CSELR_CH4_SPI2_RX_Pos (12U) +#define DMA1_CSELR_CH4_TIM2_CH4_Pos (12U) +#define DMA1_CSELR_CH4_TIM3_CH1_Pos (13U) +#define DMA1_CSELR_CH4_TIM3_TRIG_Pos (13U) +#define DMA1_CSELR_CH4_TIM16_CH1_Pos (12U) +#define DMA1_CSELR_CH4_TIM16_UP_Pos (12U) +#define DMA1_CSELR_CH4_USART1_TX_Pos (15U) +#define DMA1_CSELR_CH4_USART2_TX_Pos (12U) +#define DMA1_CSELR_CH4_USART3_TX_Pos (13U) +#define DMA1_CSELR_CH4_USART4_TX_Pos (12U) +#define DMA1_CSELR_CH4_USART5_TX_Pos (14U) +#define DMA1_CSELR_CH4_USART6_TX_Pos (12U) +#define DMA1_CSELR_CH5_I2C2_RX_Pos (17U) +#define DMA1_CSELR_CH5_SPI2_TX_Pos (16U) +#define DMA1_CSELR_CH5_TIM1_CH3_Pos (18U) +#define DMA1_CSELR_CH5_USART1_RX_Pos (19U) +#define DMA1_CSELR_CH5_USART2_RX_Pos (16U) +#define DMA1_CSELR_CH5_USART3_RX_Pos (17U) +#define DMA1_CSELR_CH5_USART4_RX_Pos (16U) +#define DMA1_CSELR_CH5_USART5_RX_Pos (18U) +#define DMA1_CSELR_CH5_USART6_RX_Pos (16U) +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller (EXTI) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for EXTI_IMR register *******************/ +#define EXTI_IMR_MR0_Pos (0U) +#define EXTI_IMR_MR1_Pos (1U) +#define EXTI_IMR_MR2_Pos (2U) +#define EXTI_IMR_MR3_Pos (3U) +#define EXTI_IMR_MR4_Pos (4U) +#define EXTI_IMR_MR5_Pos (5U) +#define EXTI_IMR_MR6_Pos (6U) +#define EXTI_IMR_MR7_Pos (7U) +#define EXTI_IMR_MR8_Pos (8U) +#define EXTI_IMR_MR9_Pos (9U) +#define EXTI_IMR_MR10_Pos (10U) +#define EXTI_IMR_MR11_Pos (11U) +#define EXTI_IMR_MR12_Pos (12U) +#define EXTI_IMR_MR13_Pos (13U) +#define EXTI_IMR_MR14_Pos (14U) +#define EXTI_IMR_MR15_Pos (15U) +#define EXTI_IMR_MR17_Pos (17U) +#define EXTI_IMR_MR18_Pos (18U) +#define EXTI_IMR_MR19_Pos (19U) +#define EXTI_IMR_MR20_Pos (20U) +#define EXTI_IMR_MR23_Pos (23U) + +/* References Defines */ +#define EXTI_IMR_IM0 EXTI_IMR_MR0 +#define EXTI_IMR_IM1 EXTI_IMR_MR1 +#define EXTI_IMR_IM2 EXTI_IMR_MR2 +#define EXTI_IMR_IM3 EXTI_IMR_MR3 +#define EXTI_IMR_IM4 EXTI_IMR_MR4 +#define EXTI_IMR_IM5 EXTI_IMR_MR5 +#define EXTI_IMR_IM6 EXTI_IMR_MR6 +#define EXTI_IMR_IM7 EXTI_IMR_MR7 +#define EXTI_IMR_IM8 EXTI_IMR_MR8 +#define EXTI_IMR_IM9 EXTI_IMR_MR9 +#define EXTI_IMR_IM10 EXTI_IMR_MR10 +#define EXTI_IMR_IM11 EXTI_IMR_MR11 +#define EXTI_IMR_IM12 EXTI_IMR_MR12 +#define EXTI_IMR_IM13 EXTI_IMR_MR13 +#define EXTI_IMR_IM14 EXTI_IMR_MR14 +#define EXTI_IMR_IM15 EXTI_IMR_MR15 +#define EXTI_IMR_IM17 EXTI_IMR_MR17 +#define EXTI_IMR_IM18 EXTI_IMR_MR18 +#define EXTI_IMR_IM19 EXTI_IMR_MR19 +#define EXTI_IMR_IM20 EXTI_IMR_MR20 +#define EXTI_IMR_IM23 EXTI_IMR_MR23 + +#define EXTI_IMR_IM_Pos (0U) + + +/****************** Bit definition for EXTI_EMR register ********************/ +#define EXTI_EMR_MR0_Pos (0U) +#define EXTI_EMR_MR1_Pos (1U) +#define EXTI_EMR_MR2_Pos (2U) +#define EXTI_EMR_MR3_Pos (3U) +#define EXTI_EMR_MR4_Pos (4U) +#define EXTI_EMR_MR5_Pos (5U) +#define EXTI_EMR_MR6_Pos (6U) +#define EXTI_EMR_MR7_Pos (7U) +#define EXTI_EMR_MR8_Pos (8U) +#define EXTI_EMR_MR9_Pos (9U) +#define EXTI_EMR_MR10_Pos (10U) +#define EXTI_EMR_MR11_Pos (11U) +#define EXTI_EMR_MR12_Pos (12U) +#define EXTI_EMR_MR13_Pos (13U) +#define EXTI_EMR_MR14_Pos (14U) +#define EXTI_EMR_MR15_Pos (15U) +#define EXTI_EMR_MR17_Pos (17U) +#define EXTI_EMR_MR18_Pos (18U) +#define EXTI_EMR_MR19_Pos (19U) +#define EXTI_EMR_MR20_Pos (20U) +#define EXTI_EMR_MR23_Pos (23U) + +/* References Defines */ +#define EXTI_EMR_EM0 EXTI_EMR_MR0 +#define EXTI_EMR_EM1 EXTI_EMR_MR1 +#define EXTI_EMR_EM2 EXTI_EMR_MR2 +#define EXTI_EMR_EM3 EXTI_EMR_MR3 +#define EXTI_EMR_EM4 EXTI_EMR_MR4 +#define EXTI_EMR_EM5 EXTI_EMR_MR5 +#define EXTI_EMR_EM6 EXTI_EMR_MR6 +#define EXTI_EMR_EM7 EXTI_EMR_MR7 +#define EXTI_EMR_EM8 EXTI_EMR_MR8 +#define EXTI_EMR_EM9 EXTI_EMR_MR9 +#define EXTI_EMR_EM10 EXTI_EMR_MR10 +#define EXTI_EMR_EM11 EXTI_EMR_MR11 +#define EXTI_EMR_EM12 EXTI_EMR_MR12 +#define EXTI_EMR_EM13 EXTI_EMR_MR13 +#define EXTI_EMR_EM14 EXTI_EMR_MR14 +#define EXTI_EMR_EM15 EXTI_EMR_MR15 +#define EXTI_EMR_EM17 EXTI_EMR_MR17 +#define EXTI_EMR_EM18 EXTI_EMR_MR18 +#define EXTI_EMR_EM19 EXTI_EMR_MR19 +#define EXTI_EMR_EM20 EXTI_EMR_MR20 +#define EXTI_EMR_EM23 EXTI_EMR_MR23 + +/******************* Bit definition for EXTI_RTSR register ******************/ +#define EXTI_RTSR_TR0_Pos (0U) +#define EXTI_RTSR_TR1_Pos (1U) +#define EXTI_RTSR_TR2_Pos (2U) +#define EXTI_RTSR_TR3_Pos (3U) +#define EXTI_RTSR_TR4_Pos (4U) +#define EXTI_RTSR_TR5_Pos (5U) +#define EXTI_RTSR_TR6_Pos (6U) +#define EXTI_RTSR_TR7_Pos (7U) +#define EXTI_RTSR_TR8_Pos (8U) +#define EXTI_RTSR_TR9_Pos (9U) +#define EXTI_RTSR_TR10_Pos (10U) +#define EXTI_RTSR_TR11_Pos (11U) +#define EXTI_RTSR_TR12_Pos (12U) +#define EXTI_RTSR_TR13_Pos (13U) +#define EXTI_RTSR_TR14_Pos (14U) +#define EXTI_RTSR_TR15_Pos (15U) +#define EXTI_RTSR_TR16_Pos (16U) +#define EXTI_RTSR_TR17_Pos (17U) +#define EXTI_RTSR_TR19_Pos (19U) +#define EXTI_RTSR_TR20_Pos (20U) + +/* References Defines */ +#define EXTI_RTSR_RT0 EXTI_RTSR_TR0 +#define EXTI_RTSR_RT1 EXTI_RTSR_TR1 +#define EXTI_RTSR_RT2 EXTI_RTSR_TR2 +#define EXTI_RTSR_RT3 EXTI_RTSR_TR3 +#define EXTI_RTSR_RT4 EXTI_RTSR_TR4 +#define EXTI_RTSR_RT5 EXTI_RTSR_TR5 +#define EXTI_RTSR_RT6 EXTI_RTSR_TR6 +#define EXTI_RTSR_RT7 EXTI_RTSR_TR7 +#define EXTI_RTSR_RT8 EXTI_RTSR_TR8 +#define EXTI_RTSR_RT9 EXTI_RTSR_TR9 +#define EXTI_RTSR_RT10 EXTI_RTSR_TR10 +#define EXTI_RTSR_RT11 EXTI_RTSR_TR11 +#define EXTI_RTSR_RT12 EXTI_RTSR_TR12 +#define EXTI_RTSR_RT13 EXTI_RTSR_TR13 +#define EXTI_RTSR_RT14 EXTI_RTSR_TR14 +#define EXTI_RTSR_RT15 EXTI_RTSR_TR15 +#define EXTI_RTSR_RT16 EXTI_RTSR_TR16 +#define EXTI_RTSR_RT17 EXTI_RTSR_TR17 +#define EXTI_RTSR_RT19 EXTI_RTSR_TR19 +#define EXTI_RTSR_RT20 EXTI_RTSR_TR20 + +/******************* Bit definition for EXTI_FTSR register *******************/ +#define EXTI_FTSR_TR0_Pos (0U) +#define EXTI_FTSR_TR1_Pos (1U) +#define EXTI_FTSR_TR2_Pos (2U) +#define EXTI_FTSR_TR3_Pos (3U) +#define EXTI_FTSR_TR4_Pos (4U) +#define EXTI_FTSR_TR5_Pos (5U) +#define EXTI_FTSR_TR6_Pos (6U) +#define EXTI_FTSR_TR7_Pos (7U) +#define EXTI_FTSR_TR8_Pos (8U) +#define EXTI_FTSR_TR9_Pos (9U) +#define EXTI_FTSR_TR10_Pos (10U) +#define EXTI_FTSR_TR11_Pos (11U) +#define EXTI_FTSR_TR12_Pos (12U) +#define EXTI_FTSR_TR13_Pos (13U) +#define EXTI_FTSR_TR14_Pos (14U) +#define EXTI_FTSR_TR15_Pos (15U) +#define EXTI_FTSR_TR16_Pos (16U) +#define EXTI_FTSR_TR17_Pos (17U) +#define EXTI_FTSR_TR19_Pos (19U) +#define EXTI_FTSR_TR20_Pos (20U) + +/* References Defines */ +#define EXTI_FTSR_FT0 EXTI_FTSR_TR0 +#define EXTI_FTSR_FT1 EXTI_FTSR_TR1 +#define EXTI_FTSR_FT2 EXTI_FTSR_TR2 +#define EXTI_FTSR_FT3 EXTI_FTSR_TR3 +#define EXTI_FTSR_FT4 EXTI_FTSR_TR4 +#define EXTI_FTSR_FT5 EXTI_FTSR_TR5 +#define EXTI_FTSR_FT6 EXTI_FTSR_TR6 +#define EXTI_FTSR_FT7 EXTI_FTSR_TR7 +#define EXTI_FTSR_FT8 EXTI_FTSR_TR8 +#define EXTI_FTSR_FT9 EXTI_FTSR_TR9 +#define EXTI_FTSR_FT10 EXTI_FTSR_TR10 +#define EXTI_FTSR_FT11 EXTI_FTSR_TR11 +#define EXTI_FTSR_FT12 EXTI_FTSR_TR12 +#define EXTI_FTSR_FT13 EXTI_FTSR_TR13 +#define EXTI_FTSR_FT14 EXTI_FTSR_TR14 +#define EXTI_FTSR_FT15 EXTI_FTSR_TR15 +#define EXTI_FTSR_FT16 EXTI_FTSR_TR16 +#define EXTI_FTSR_FT17 EXTI_FTSR_TR17 +#define EXTI_FTSR_FT19 EXTI_FTSR_TR19 +#define EXTI_FTSR_FT20 EXTI_FTSR_TR20 + +/******************* Bit definition for EXTI_SWIER register *******************/ +#define EXTI_SWIER_SWIER0_Pos (0U) +#define EXTI_SWIER_SWIER1_Pos (1U) +#define EXTI_SWIER_SWIER2_Pos (2U) +#define EXTI_SWIER_SWIER3_Pos (3U) +#define EXTI_SWIER_SWIER4_Pos (4U) +#define EXTI_SWIER_SWIER5_Pos (5U) +#define EXTI_SWIER_SWIER6_Pos (6U) +#define EXTI_SWIER_SWIER7_Pos (7U) +#define EXTI_SWIER_SWIER8_Pos (8U) +#define EXTI_SWIER_SWIER9_Pos (9U) +#define EXTI_SWIER_SWIER10_Pos (10U) +#define EXTI_SWIER_SWIER11_Pos (11U) +#define EXTI_SWIER_SWIER12_Pos (12U) +#define EXTI_SWIER_SWIER13_Pos (13U) +#define EXTI_SWIER_SWIER14_Pos (14U) +#define EXTI_SWIER_SWIER15_Pos (15U) +#define EXTI_SWIER_SWIER16_Pos (16U) +#define EXTI_SWIER_SWIER17_Pos (17U) +#define EXTI_SWIER_SWIER19_Pos (19U) +#define EXTI_SWIER_SWIER20_Pos (20U) + +/* References Defines */ +#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 +#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 +#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 +#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 +#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 +#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 +#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 +#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 +#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 +#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 +#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 +#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 +#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 +#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 +#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 +#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 +#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 +#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 +#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19 +#define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20 + +/****************** Bit definition for EXTI_PR register *********************/ +#define EXTI_PR_PR0_Pos (0U) +#define EXTI_PR_PR1_Pos (1U) +#define EXTI_PR_PR2_Pos (2U) +#define EXTI_PR_PR3_Pos (3U) +#define EXTI_PR_PR4_Pos (4U) +#define EXTI_PR_PR5_Pos (5U) +#define EXTI_PR_PR6_Pos (6U) +#define EXTI_PR_PR7_Pos (7U) +#define EXTI_PR_PR8_Pos (8U) +#define EXTI_PR_PR9_Pos (9U) +#define EXTI_PR_PR10_Pos (10U) +#define EXTI_PR_PR11_Pos (11U) +#define EXTI_PR_PR12_Pos (12U) +#define EXTI_PR_PR13_Pos (13U) +#define EXTI_PR_PR14_Pos (14U) +#define EXTI_PR_PR15_Pos (15U) +#define EXTI_PR_PR16_Pos (16U) +#define EXTI_PR_PR17_Pos (17U) +#define EXTI_PR_PR19_Pos (19U) +#define EXTI_PR_PR20_Pos (20U) + +/* References Defines */ +#define EXTI_PR_PIF0 EXTI_PR_PR0 +#define EXTI_PR_PIF1 EXTI_PR_PR1 +#define EXTI_PR_PIF2 EXTI_PR_PR2 +#define EXTI_PR_PIF3 EXTI_PR_PR3 +#define EXTI_PR_PIF4 EXTI_PR_PR4 +#define EXTI_PR_PIF5 EXTI_PR_PR5 +#define EXTI_PR_PIF6 EXTI_PR_PR6 +#define EXTI_PR_PIF7 EXTI_PR_PR7 +#define EXTI_PR_PIF8 EXTI_PR_PR8 +#define EXTI_PR_PIF9 EXTI_PR_PR9 +#define EXTI_PR_PIF10 EXTI_PR_PR10 +#define EXTI_PR_PIF11 EXTI_PR_PR11 +#define EXTI_PR_PIF12 EXTI_PR_PR12 +#define EXTI_PR_PIF13 EXTI_PR_PR13 +#define EXTI_PR_PIF14 EXTI_PR_PR14 +#define EXTI_PR_PIF15 EXTI_PR_PR15 +#define EXTI_PR_PIF16 EXTI_PR_PR16 +#define EXTI_PR_PIF17 EXTI_PR_PR17 +#define EXTI_PR_PIF19 EXTI_PR_PR19 +#define EXTI_PR_PIF20 EXTI_PR_PR20 + +/******************************************************************************/ +/* */ +/* FLASH and Option Bytes Registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_ACR register ******************/ +#define FLASH_ACR_LATENCY_Pos (0U) + +#define FLASH_ACR_PRFTBE_Pos (4U) +#define FLASH_ACR_PRFTBS_Pos (5U) + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR_Pos (0U) + +/***************** Bit definition for FLASH_OPTKEYR register ****************/ +#define FLASH_OPTKEYR_OPTKEYR_Pos (0U) + +/****************** FLASH Keys **********************************************/ +#define FLASH_KEY1_Pos (0U) +#define FLASH_KEY2_Pos (0U) + to unlock the write access to the FPEC. */ + +#define FLASH_OPTKEY1_Pos (0U) +#define FLASH_OPTKEY2_Pos (0U) + unlock the write access to the option byte block */ + +/****************** Bit definition for FLASH_SR register *******************/ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_PGERR_Pos (2U) +#define FLASH_SR_WRPRTERR_Pos (4U) +#define FLASH_SR_EOP_Pos (5U) + +/******************* Bit definition for FLASH_CR register *******************/ +#define FLASH_CR_PG_Pos (0U) +#define FLASH_CR_PER_Pos (1U) +#define FLASH_CR_MER_Pos (2U) +#define FLASH_CR_OPTPG_Pos (4U) +#define FLASH_CR_OPTER_Pos (5U) +#define FLASH_CR_STRT_Pos (6U) +#define FLASH_CR_LOCK_Pos (7U) +#define FLASH_CR_OPTWRE_Pos (9U) +#define FLASH_CR_ERRIE_Pos (10U) +#define FLASH_CR_EOPIE_Pos (12U) +#define FLASH_CR_OBL_LAUNCH_Pos (13U) + +/******************* Bit definition for FLASH_AR register *******************/ +#define FLASH_AR_FAR_Pos (0U) + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR_Pos (0U) +#define FLASH_OBR_RDPRT1_Pos (1U) +#define FLASH_OBR_RDPRT2_Pos (2U) + +#define FLASH_OBR_USER_Pos (8U) +#define FLASH_OBR_IWDG_SW_Pos (8U) +#define FLASH_OBR_nRST_STOP_Pos (9U) +#define FLASH_OBR_nRST_STDBY_Pos (10U) +#define FLASH_OBR_nBOOT1_Pos (12U) +#define FLASH_OBR_VDDA_MONITOR_Pos (13U) +#define FLASH_OBR_RAM_PARITY_CHECK_Pos (14U) +#define FLASH_OBR_DATA0_Pos (16U) +#define FLASH_OBR_DATA1_Pos (24U) + +/* Old BOOT1 bit definition, maintained for legacy purpose */ +#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1 + +/* Old OBR_VDDA bit definition, maintained for legacy purpose */ +#define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR + +/****************** Bit definition for FLASH_WRPR register ******************/ +#define FLASH_WRPR_WRP_Pos (0U) + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for OB_RDP register **********************/ +#define OB_RDP_RDP_Pos (0U) +#define OB_RDP_nRDP_Pos (8U) + +/****************** Bit definition for OB_USER register *********************/ +#define OB_USER_USER_Pos (16U) +#define OB_USER_nUSER_Pos (24U) + +/****************** Bit definition for OB_WRP0 register *********************/ +#define OB_WRP0_WRP0_Pos (0U) +#define OB_WRP0_nWRP0_Pos (8U) + +/****************** Bit definition for OB_WRP1 register *********************/ +#define OB_WRP1_WRP1_Pos (16U) +#define OB_WRP1_nWRP1_Pos (24U) + +/****************** Bit definition for OB_WRP2 register *********************/ +#define OB_WRP2_WRP2_Pos (0U) +#define OB_WRP2_nWRP2_Pos (8U) + +/****************** Bit definition for OB_WRP3 register *********************/ +#define OB_WRP3_WRP3_Pos (16U) +#define OB_WRP3_nWRP3_Pos (24U) + +/******************************************************************************/ +/* */ +/* General Purpose IOs (GPIO) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODER0_Pos (0U) +#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODER1_Pos (2U) +#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODER2_Pos (4U) +#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODER3_Pos (6U) +#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODER4_Pos (8U) +#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODER5_Pos (10U) +#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODER6_Pos (12U) +#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODER7_Pos (14U) +#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODER8_Pos (16U) +#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODER9_Pos (18U) +#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODER10_Pos (20U) +#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk +#define GPIO_MODER_MODER11_Pos (22U) +#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk +#define GPIO_MODER_MODER12_Pos (24U) +#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk +#define GPIO_MODER_MODER13_Pos (26U) +#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk +#define GPIO_MODER_MODER14_Pos (28U) +#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk +#define GPIO_MODER_MODER15_Pos (30U) +#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk + +/****************** Bit definition for GPIO_OTYPER register *****************/ +#define GPIO_OTYPER_OT_0 (0x00000001U) +#define GPIO_OTYPER_OT_1 (0x00000002U) +#define GPIO_OTYPER_OT_2 (0x00000004U) +#define GPIO_OTYPER_OT_3 (0x00000008U) +#define GPIO_OTYPER_OT_4 (0x00000010U) +#define GPIO_OTYPER_OT_5 (0x00000020U) +#define GPIO_OTYPER_OT_6 (0x00000040U) +#define GPIO_OTYPER_OT_7 (0x00000080U) +#define GPIO_OTYPER_OT_8 (0x00000100U) +#define GPIO_OTYPER_OT_9 (0x00000200U) +#define GPIO_OTYPER_OT_10 (0x00000400U) +#define GPIO_OTYPER_OT_11 (0x00000800U) +#define GPIO_OTYPER_OT_12 (0x00001000U) +#define GPIO_OTYPER_OT_13 (0x00002000U) +#define GPIO_OTYPER_OT_14 (0x00004000U) +#define GPIO_OTYPER_OT_15 (0x00008000U) + +/**************** Bit definition for GPIO_OSPEEDR register ******************/ +#define GPIO_OSPEEDR_OSPEEDR0_Pos (0U) +#define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk +#define GPIO_OSPEEDR_OSPEEDR1_Pos (2U) +#define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk +#define GPIO_OSPEEDR_OSPEEDR2_Pos (4U) +#define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk +#define GPIO_OSPEEDR_OSPEEDR3_Pos (6U) +#define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk +#define GPIO_OSPEEDR_OSPEEDR4_Pos (8U) +#define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk +#define GPIO_OSPEEDR_OSPEEDR5_Pos (10U) +#define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk +#define GPIO_OSPEEDR_OSPEEDR6_Pos (12U) +#define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk +#define GPIO_OSPEEDR_OSPEEDR7_Pos (14U) +#define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk +#define GPIO_OSPEEDR_OSPEEDR8_Pos (16U) +#define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk +#define GPIO_OSPEEDR_OSPEEDR9_Pos (18U) +#define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk +#define GPIO_OSPEEDR_OSPEEDR10_Pos (20U) +#define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk +#define GPIO_OSPEEDR_OSPEEDR11_Pos (22U) +#define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk +#define GPIO_OSPEEDR_OSPEEDR12_Pos (24U) +#define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk +#define GPIO_OSPEEDR_OSPEEDR13_Pos (26U) +#define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk +#define GPIO_OSPEEDR_OSPEEDR14_Pos (28U) +#define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk +#define GPIO_OSPEEDR_OSPEEDR15_Pos (30U) +#define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk + +/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */ +#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0 +#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0 +#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1 +#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1 +#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0 +#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1 +#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2 +#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0 +#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1 +#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3 +#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0 +#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1 +#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4 +#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0 +#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1 +#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5 +#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0 +#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1 +#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6 +#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0 +#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1 +#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7 +#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0 +#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1 +#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8 +#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0 +#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1 +#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9 +#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0 +#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1 +#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10 +#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0 +#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1 +#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11 +#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0 +#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1 +#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12 +#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0 +#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1 +#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13 +#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0 +#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1 +#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14 +#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0 +#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1 +#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15 +#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0 +#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1 + +/******************* Bit definition for GPIO_PUPDR register ******************/ +#define GPIO_PUPDR_PUPDR0_Pos (0U) +#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk +#define GPIO_PUPDR_PUPDR1_Pos (2U) +#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk +#define GPIO_PUPDR_PUPDR2_Pos (4U) +#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk +#define GPIO_PUPDR_PUPDR3_Pos (6U) +#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk +#define GPIO_PUPDR_PUPDR4_Pos (8U) +#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk +#define GPIO_PUPDR_PUPDR5_Pos (10U) +#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk +#define GPIO_PUPDR_PUPDR6_Pos (12U) +#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk +#define GPIO_PUPDR_PUPDR7_Pos (14U) +#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk +#define GPIO_PUPDR_PUPDR8_Pos (16U) +#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk +#define GPIO_PUPDR_PUPDR9_Pos (18U) +#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk +#define GPIO_PUPDR_PUPDR10_Pos (20U) +#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk +#define GPIO_PUPDR_PUPDR11_Pos (22U) +#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk +#define GPIO_PUPDR_PUPDR12_Pos (24U) +#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk +#define GPIO_PUPDR_PUPDR13_Pos (26U) +#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk +#define GPIO_PUPDR_PUPDR14_Pos (28U) +#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk +#define GPIO_PUPDR_PUPDR15_Pos (30U) +#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk + +/******************* Bit definition for GPIO_IDR register *******************/ +#define GPIO_IDR_0 (0x00000001U) +#define GPIO_IDR_1 (0x00000002U) +#define GPIO_IDR_2 (0x00000004U) +#define GPIO_IDR_3 (0x00000008U) +#define GPIO_IDR_4 (0x00000010U) +#define GPIO_IDR_5 (0x00000020U) +#define GPIO_IDR_6 (0x00000040U) +#define GPIO_IDR_7 (0x00000080U) +#define GPIO_IDR_8 (0x00000100U) +#define GPIO_IDR_9 (0x00000200U) +#define GPIO_IDR_10 (0x00000400U) +#define GPIO_IDR_11 (0x00000800U) +#define GPIO_IDR_12 (0x00001000U) +#define GPIO_IDR_13 (0x00002000U) +#define GPIO_IDR_14 (0x00004000U) +#define GPIO_IDR_15 (0x00008000U) + +/****************** Bit definition for GPIO_ODR register ********************/ +#define GPIO_ODR_0 (0x00000001U) +#define GPIO_ODR_1 (0x00000002U) +#define GPIO_ODR_2 (0x00000004U) +#define GPIO_ODR_3 (0x00000008U) +#define GPIO_ODR_4 (0x00000010U) +#define GPIO_ODR_5 (0x00000020U) +#define GPIO_ODR_6 (0x00000040U) +#define GPIO_ODR_7 (0x00000080U) +#define GPIO_ODR_8 (0x00000100U) +#define GPIO_ODR_9 (0x00000200U) +#define GPIO_ODR_10 (0x00000400U) +#define GPIO_ODR_11 (0x00000800U) +#define GPIO_ODR_12 (0x00001000U) +#define GPIO_ODR_13 (0x00002000U) +#define GPIO_ODR_14 (0x00004000U) +#define GPIO_ODR_15 (0x00008000U) + +/****************** Bit definition for GPIO_BSRR register ********************/ +#define GPIO_BSRR_BS_0 (0x00000001U) +#define GPIO_BSRR_BS_1 (0x00000002U) +#define GPIO_BSRR_BS_2 (0x00000004U) +#define GPIO_BSRR_BS_3 (0x00000008U) +#define GPIO_BSRR_BS_4 (0x00000010U) +#define GPIO_BSRR_BS_5 (0x00000020U) +#define GPIO_BSRR_BS_6 (0x00000040U) +#define GPIO_BSRR_BS_7 (0x00000080U) +#define GPIO_BSRR_BS_8 (0x00000100U) +#define GPIO_BSRR_BS_9 (0x00000200U) +#define GPIO_BSRR_BS_10 (0x00000400U) +#define GPIO_BSRR_BS_11 (0x00000800U) +#define GPIO_BSRR_BS_12 (0x00001000U) +#define GPIO_BSRR_BS_13 (0x00002000U) +#define GPIO_BSRR_BS_14 (0x00004000U) +#define GPIO_BSRR_BS_15 (0x00008000U) +#define GPIO_BSRR_BR_0 (0x00010000U) +#define GPIO_BSRR_BR_1 (0x00020000U) +#define GPIO_BSRR_BR_2 (0x00040000U) +#define GPIO_BSRR_BR_3 (0x00080000U) +#define GPIO_BSRR_BR_4 (0x00100000U) +#define GPIO_BSRR_BR_5 (0x00200000U) +#define GPIO_BSRR_BR_6 (0x00400000U) +#define GPIO_BSRR_BR_7 (0x00800000U) +#define GPIO_BSRR_BR_8 (0x01000000U) +#define GPIO_BSRR_BR_9 (0x02000000U) +#define GPIO_BSRR_BR_10 (0x04000000U) +#define GPIO_BSRR_BR_11 (0x08000000U) +#define GPIO_BSRR_BR_12 (0x10000000U) +#define GPIO_BSRR_BR_13 (0x20000000U) +#define GPIO_BSRR_BR_14 (0x40000000U) +#define GPIO_BSRR_BR_15 (0x80000000U) + +/****************** Bit definition for GPIO_LCKR register ********************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk + +/****************** Bit definition for GPIO_AFRL register ********************/ +#define GPIO_AFRL_AFRL0_Pos (0U) +#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk +#define GPIO_AFRL_AFRL1_Pos (4U) +#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk +#define GPIO_AFRL_AFRL2_Pos (8U) +#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk +#define GPIO_AFRL_AFRL3_Pos (12U) +#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk +#define GPIO_AFRL_AFRL4_Pos (16U) +#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk +#define GPIO_AFRL_AFRL5_Pos (20U) +#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk +#define GPIO_AFRL_AFRL6_Pos (24U) +#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk +#define GPIO_AFRL_AFRL7_Pos (28U) +#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk + +/****************** Bit definition for GPIO_AFRH register ********************/ +#define GPIO_AFRH_AFRH0_Pos (0U) +#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk +#define GPIO_AFRH_AFRH1_Pos (4U) +#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk +#define GPIO_AFRH_AFRH2_Pos (8U) +#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk +#define GPIO_AFRH_AFRH3_Pos (12U) +#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk +#define GPIO_AFRH_AFRH4_Pos (16U) +#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk +#define GPIO_AFRH_AFRH5_Pos (20U) +#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk +#define GPIO_AFRH_AFRH6_Pos (24U) +#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk +#define GPIO_AFRH_AFRH7_Pos (28U) +#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk + +/****************** Bit definition for GPIO_BRR register *********************/ +#define GPIO_BRR_BR_0 (0x00000001U) +#define GPIO_BRR_BR_1 (0x00000002U) +#define GPIO_BRR_BR_2 (0x00000004U) +#define GPIO_BRR_BR_3 (0x00000008U) +#define GPIO_BRR_BR_4 (0x00000010U) +#define GPIO_BRR_BR_5 (0x00000020U) +#define GPIO_BRR_BR_6 (0x00000040U) +#define GPIO_BRR_BR_7 (0x00000080U) +#define GPIO_BRR_BR_8 (0x00000100U) +#define GPIO_BRR_BR_9 (0x00000200U) +#define GPIO_BRR_BR_10 (0x00000400U) +#define GPIO_BRR_BR_11 (0x00000800U) +#define GPIO_BRR_BR_12 (0x00001000U) +#define GPIO_BRR_BR_13 (0x00002000U) +#define GPIO_BRR_BR_14 (0x00004000U) +#define GPIO_BRR_BR_15 (0x00008000U) + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface (I2C) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CR1 register *******************/ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_SWRST_Pos (13U) +#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_PECEN_Pos (23U) + +/****************** Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_PECBYTE_Pos (26U) + +/******************* Bit definition for I2C_OAR1 register ******************/ +#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1EN_Pos (15U) + +/******************* Bit definition for I2C_OAR2 register ******************/ +#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2EN_Pos (15U) + +/******************* Bit definition for I2C_TIMINGR register ****************/ +#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_PRESC_Pos (28U) + +/******************* Bit definition for I2C_TIMEOUTR register ****************/ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TEXTEN_Pos (31U) + +/****************** Bit definition for I2C_ISR register ********************/ +#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_ADDCODE_Pos (17U) + +/****************** Bit definition for I2C_ICR register ********************/ +#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_ALERTCF_Pos (13U) + +/****************** Bit definition for I2C_PECR register *******************/ +#define I2C_PECR_PEC_Pos (0U) + +/****************** Bit definition for I2C_RXDR register *********************/ +#define I2C_RXDR_RXDATA_Pos (0U) + +/****************** Bit definition for I2C_TXDR register *******************/ +#define I2C_TXDR_TXDATA_Pos (0U) + +/*****************************************************************************/ +/* */ +/* Independent WATCHDOG (IWDG) */ +/* */ +/*****************************************************************************/ +/******************* Bit definition for IWDG_KR register *******************/ +#define IWDG_KR_KEY_Pos (0U) + +/******************* Bit definition for IWDG_PR register *******************/ +#define IWDG_PR_PR_Pos (0U) + +/******************* Bit definition for IWDG_RLR register ******************/ +#define IWDG_RLR_RL_Pos (0U) + +/******************* Bit definition for IWDG_SR register *******************/ +#define IWDG_SR_PVU_Pos (0U) +#define IWDG_SR_RVU_Pos (1U) +#define IWDG_SR_WVU_Pos (2U) + +/******************* Bit definition for IWDG_KR register *******************/ +#define IWDG_WINR_WIN_Pos (0U) + +/*****************************************************************************/ +/* */ +/* Power Control (PWR) */ +/* */ +/*****************************************************************************/ + +/* Note: No specific macro feature on this device */ + + +/******************** Bit definition for PWR_CR register *******************/ +#define PWR_CR_LPDS_Pos (0U) +#define PWR_CR_PDDS_Pos (1U) +#define PWR_CR_CWUF_Pos (2U) +#define PWR_CR_CSBF_Pos (3U) +#define PWR_CR_DBP_Pos (8U) + +/******************* Bit definition for PWR_CSR register *******************/ +#define PWR_CSR_WUF_Pos (0U) +#define PWR_CSR_SBF_Pos (1U) + +#define PWR_CSR_EWUP1_Pos (8U) +#define PWR_CSR_EWUP2_Pos (9U) +#define PWR_CSR_EWUP4_Pos (11U) +#define PWR_CSR_EWUP5_Pos (12U) +#define PWR_CSR_EWUP6_Pos (13U) +#define PWR_CSR_EWUP7_Pos (14U) + +/*****************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/*****************************************************************************/ +/* +* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +*/ + +/******************** Bit definition for RCC_CR register *******************/ +#define RCC_CR_HSION_Pos (0U) +#define RCC_CR_HSIRDY_Pos (1U) + +#define RCC_CR_HSITRIM_Pos (3U) + +#define RCC_CR_HSICAL_Pos (8U) + +#define RCC_CR_HSEON_Pos (16U) +#define RCC_CR_HSERDY_Pos (17U) +#define RCC_CR_HSEBYP_Pos (18U) +#define RCC_CR_CSSON_Pos (19U) +#define RCC_CR_PLLON_Pos (24U) +#define RCC_CR_PLLRDY_Pos (25U) + +/******************** Bit definition for RCC_CFGR register *****************/ +#define RCC_CFGR_SW_Pos (0U) + + +#define RCC_CFGR_SWS_Pos (2U) + + +#define RCC_CFGR_HPRE_Pos (4U) + + +#define RCC_CFGR_PPRE_Pos (8U) + +#define RCC_CFGR_PPRE_DIV2_Pos (10U) +#define RCC_CFGR_PPRE_DIV4_Pos (8U) +#define RCC_CFGR_PPRE_DIV8_Pos (9U) +#define RCC_CFGR_PPRE_DIV16_Pos (8U) + +#define RCC_CFGR_PLLSRC_Pos (15U) + +#define RCC_CFGR_PLLXTPRE_Pos (17U) + +#define RCC_CFGR_PLLMUL_Pos (18U) + + +#define RCC_CFGR_MCO_Pos (24U) + + +#define RCC_CFGR_MCOPRE_Pos (28U) + +#define RCC_CFGR_PLLNODIV_Pos (31U) + +/* Reference defines */ +#define RCC_CFGR_MCOSEL RCC_CFGR_MCO +#define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0 +#define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1 +#define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2 +#define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK +#define RCC_CFGR_MCOSEL_HSI14 RCC_CFGR_MCO_HSI14 +#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCO_LSI +#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCO_LSE +#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK +#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI +#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE +#define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL + +#define RCC_CIR_LSIRDYF_Pos (0U) +#define RCC_CIR_LSERDYF_Pos (1U) +#define RCC_CIR_HSIRDYF_Pos (2U) +#define RCC_CIR_HSERDYF_Pos (3U) +#define RCC_CIR_PLLRDYF_Pos (4U) +#define RCC_CIR_HSI14RDYF_Pos (5U) +#define RCC_CIR_CSSF_Pos (7U) +#define RCC_CIR_LSIRDYIE_Pos (8U) +#define RCC_CIR_LSERDYIE_Pos (9U) +#define RCC_CIR_HSIRDYIE_Pos (10U) +#define RCC_CIR_HSERDYIE_Pos (11U) +#define RCC_CIR_PLLRDYIE_Pos (12U) +#define RCC_CIR_HSI14RDYIE_Pos (13U) +#define RCC_CIR_LSIRDYC_Pos (16U) +#define RCC_CIR_LSERDYC_Pos (17U) +#define RCC_CIR_HSIRDYC_Pos (18U) +#define RCC_CIR_HSERDYC_Pos (19U) +#define RCC_CIR_PLLRDYC_Pos (20U) +#define RCC_CIR_HSI14RDYC_Pos (21U) +#define RCC_CIR_CSSC_Pos (23U) + +/***************** Bit definition for RCC_APB2RSTR register ****************/ +#define RCC_APB2RSTR_SYSCFGRST_Pos (0U) +#define RCC_APB2RSTR_USART6RST_Pos (5U) +#define RCC_APB2RSTR_ADCRST_Pos (9U) +#define RCC_APB2RSTR_TIM1RST_Pos (11U) +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_USART1RST_Pos (14U) +#define RCC_APB2RSTR_TIM15RST_Pos (16U) +#define RCC_APB2RSTR_TIM16RST_Pos (17U) +#define RCC_APB2RSTR_TIM17RST_Pos (18U) +#define RCC_APB2RSTR_DBGMCURST_Pos (22U) + +#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST + +/***************** Bit definition for RCC_APB1RSTR register ****************/ +#define RCC_APB1RSTR_TIM3RST_Pos (1U) +#define RCC_APB1RSTR_TIM6RST_Pos (4U) +#define RCC_APB1RSTR_TIM7RST_Pos (5U) +#define RCC_APB1RSTR_TIM14RST_Pos (8U) +#define RCC_APB1RSTR_WWDGRST_Pos (11U) +#define RCC_APB1RSTR_SPI2RST_Pos (14U) +#define RCC_APB1RSTR_USART2RST_Pos (17U) +#define RCC_APB1RSTR_USART3RST_Pos (18U) +#define RCC_APB1RSTR_USART4RST_Pos (19U) +#define RCC_APB1RSTR_USART5RST_Pos (20U) +#define RCC_APB1RSTR_I2C1RST_Pos (21U) +#define RCC_APB1RSTR_I2C2RST_Pos (22U) +#define RCC_APB1RSTR_PWRRST_Pos (28U) + +/****************** Bit definition for RCC_AHBENR register *****************/ +#define RCC_AHBENR_DMAEN_Pos (0U) +#define RCC_AHBENR_SRAMEN_Pos (2U) +#define RCC_AHBENR_FLITFEN_Pos (4U) +#define RCC_AHBENR_CRCEN_Pos (6U) +#define RCC_AHBENR_GPIOAEN_Pos (17U) +#define RCC_AHBENR_GPIOBEN_Pos (18U) +#define RCC_AHBENR_GPIOCEN_Pos (19U) +#define RCC_AHBENR_GPIODEN_Pos (20U) +#define RCC_AHBENR_GPIOFEN_Pos (22U) + +/* Old Bit definition maintained for legacy purpose */ + +/***************** Bit definition for RCC_APB2ENR register *****************/ +#define RCC_APB2ENR_SYSCFGCOMPEN_Pos (0U) +#define RCC_APB2ENR_USART6EN_Pos (5U) +#define RCC_APB2ENR_ADCEN_Pos (9U) +#define RCC_APB2ENR_TIM1EN_Pos (11U) +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_USART1EN_Pos (14U) +#define RCC_APB2ENR_TIM15EN_Pos (16U) +#define RCC_APB2ENR_TIM16EN_Pos (17U) +#define RCC_APB2ENR_TIM17EN_Pos (18U) +#define RCC_APB2ENR_DBGMCUEN_Pos (22U) + +/* Old Bit definition maintained for legacy purpose */ + +/***************** Bit definition for RCC_APB1ENR register *****************/ +#define RCC_APB1ENR_TIM3EN_Pos (1U) +#define RCC_APB1ENR_TIM6EN_Pos (4U) +#define RCC_APB1ENR_TIM7EN_Pos (5U) +#define RCC_APB1ENR_TIM14EN_Pos (8U) +#define RCC_APB1ENR_WWDGEN_Pos (11U) +#define RCC_APB1ENR_SPI2EN_Pos (14U) +#define RCC_APB1ENR_USART2EN_Pos (17U) +#define RCC_APB1ENR_USART3EN_Pos (18U) +#define RCC_APB1ENR_USART4EN_Pos (19U) +#define RCC_APB1ENR_USART5EN_Pos (20U) +#define RCC_APB1ENR_I2C1EN_Pos (21U) +#define RCC_APB1ENR_I2C2EN_Pos (22U) +#define RCC_APB1ENR_PWREN_Pos (28U) + +/******************* Bit definition for RCC_BDCR register ******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSERDY_Pos (1U) +#define RCC_BDCR_LSEBYP_Pos (2U) + +#define RCC_BDCR_LSEDRV_Pos (3U) + +#define RCC_BDCR_RTCSEL_Pos (8U) + + +#define RCC_BDCR_RTCEN_Pos (15U) +#define RCC_BDCR_BDRST_Pos (16U) + +/******************* Bit definition for RCC_CSR register *******************/ +#define RCC_CSR_LSION_Pos (0U) +#define RCC_CSR_LSIRDY_Pos (1U) +#define RCC_CSR_V18PWRRSTF_Pos (23U) +#define RCC_CSR_RMVF_Pos (24U) +#define RCC_CSR_OBLRSTF_Pos (25U) +#define RCC_CSR_PINRSTF_Pos (26U) +#define RCC_CSR_PORRSTF_Pos (27U) +#define RCC_CSR_SFTRSTF_Pos (28U) +#define RCC_CSR_IWDGRSTF_Pos (29U) +#define RCC_CSR_WWDGRSTF_Pos (30U) +#define RCC_CSR_LPWRRSTF_Pos (31U) + +/* Old Bit definition maintained for legacy purpose */ + +/******************* Bit definition for RCC_AHBRSTR register ***************/ +#define RCC_AHBRSTR_GPIOARST_Pos (17U) +#define RCC_AHBRSTR_GPIOBRST_Pos (18U) +#define RCC_AHBRSTR_GPIOCRST_Pos (19U) +#define RCC_AHBRSTR_GPIODRST_Pos (20U) +#define RCC_AHBRSTR_GPIOFRST_Pos (22U) + +/******************* Bit definition for RCC_CFGR2 register *****************/ +#define RCC_CFGR2_PREDIV_Pos (0U) + + +/******************* Bit definition for RCC_CFGR3 register *****************/ +#define RCC_CFGR3_USART1SW_Pos (0U) + + +#define RCC_CFGR3_I2C1SW_Pos (4U) + +#define RCC_CFGR3_I2C1SW_SYSCLK_Pos (4U) + +/******************* Bit definition for RCC_CR2 register *******************/ +#define RCC_CR2_HSI14ON_Pos (0U) +#define RCC_CR2_HSI14RDY_Pos (1U) +#define RCC_CR2_HSI14DIS_Pos (2U) +#define RCC_CR2_HSI14TRIM_Pos (3U) +#define RCC_CR2_HSI14CAL_Pos (8U) + +/*****************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/*****************************************************************************/ +/* +* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +*/ + +/******************** Bits definition for RTC_TR register ******************/ +#define RTC_TR_PM_Pos (22U) +#define RTC_TR_PM RTC_TR_PM_Msk +#define RTC_TR_HT_Pos (20U) +#define RTC_TR_HT RTC_TR_HT_Msk +#define RTC_TR_HU_Pos (16U) +#define RTC_TR_HU RTC_TR_HU_Msk +#define RTC_TR_MNT_Pos (12U) +#define RTC_TR_MNT RTC_TR_MNT_Msk +#define RTC_TR_MNU_Pos (8U) +#define RTC_TR_MNU RTC_TR_MNU_Msk +#define RTC_TR_ST_Pos (4U) +#define RTC_TR_ST RTC_TR_ST_Msk +#define RTC_TR_SU_Pos (0U) +#define RTC_TR_SU RTC_TR_SU_Msk + +/******************** Bits definition for RTC_DR register ******************/ +#define RTC_DR_YT_Pos (20U) +#define RTC_DR_YT RTC_DR_YT_Msk +#define RTC_DR_YU_Pos (16U) +#define RTC_DR_YU RTC_DR_YU_Msk +#define RTC_DR_WDU_Pos (13U) +#define RTC_DR_WDU RTC_DR_WDU_Msk +#define RTC_DR_MT_Pos (12U) +#define RTC_DR_MT RTC_DR_MT_Msk +#define RTC_DR_MU_Pos (8U) +#define RTC_DR_MU RTC_DR_MU_Msk +#define RTC_DR_DT_Pos (4U) +#define RTC_DR_DT RTC_DR_DT_Msk +#define RTC_DR_DU_Pos (0U) +#define RTC_DR_DU RTC_DR_DU_Msk + +/******************** Bits definition for RTC_CR register ******************/ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE RTC_CR_COE_Msk +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL RTC_CR_OSEL_Msk +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL RTC_CR_POL_Msk +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL RTC_CR_COSEL_Msk +#define RTC_CR_BCK_Pos (18U) +#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE RTC_CR_TSIE_Msk +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE RTC_CR_TSE_Msk +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE RTC_CR_WUTE_Msk +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk + +/******************** Bits definition for RTC_ISR register *****************/ +#define RTC_ISR_RECALPF_Pos (16U) +#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk +#define RTC_ISR_TAMP2F_Pos (14U) +#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk +#define RTC_ISR_TAMP1F_Pos (13U) +#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk +#define RTC_ISR_TSOVF_Pos (12U) +#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk +#define RTC_ISR_TSF_Pos (11U) +#define RTC_ISR_TSF RTC_ISR_TSF_Msk +#define RTC_ISR_WUTF_Pos (10U) +#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk +#define RTC_ISR_ALRAF_Pos (8U) +#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk +#define RTC_ISR_INIT_Pos (7U) +#define RTC_ISR_INIT RTC_ISR_INIT_Msk +#define RTC_ISR_INITF_Pos (6U) +#define RTC_ISR_INITF RTC_ISR_INITF_Msk +#define RTC_ISR_RSF_Pos (5U) +#define RTC_ISR_RSF RTC_ISR_RSF_Msk +#define RTC_ISR_INITS_Pos (4U) +#define RTC_ISR_INITS RTC_ISR_INITS_Msk +#define RTC_ISR_SHPF_Pos (3U) +#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk +#define RTC_ISR_WUTWF_Pos (2U) +#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk +#define RTC_ISR_ALRAWF_Pos (0U) +#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk + +/******************** Bits definition for RTC_PRER register ****************/ +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk + +/******************** Bits definition for RTC_WUTR register ****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk + +/******************** Bits definition for RTC_ALRMAR register **************/ +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk + +/******************** Bits definition for RTC_WPR register *****************/ +#define RTC_WPR_KEY_Pos (0U) +#define RTC_WPR_KEY RTC_WPR_KEY_Msk + +/******************** Bits definition for RTC_SSR register *****************/ +#define RTC_SSR_SS_Pos (0U) +#define RTC_SSR_SS RTC_SSR_SS_Msk + +/******************** Bits definition for RTC_SHIFTR register **************/ +#define RTC_SHIFTR_SUBFS_Pos (0U) +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk +#define RTC_SHIFTR_ADD1S_Pos (31U) +#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk + +/******************** Bits definition for RTC_TSTR register ****************/ +#define RTC_TSTR_PM_Pos (22U) +#define RTC_TSTR_PM RTC_TSTR_PM_Msk +#define RTC_TSTR_HT_Pos (20U) +#define RTC_TSTR_HT RTC_TSTR_HT_Msk +#define RTC_TSTR_HU_Pos (16U) +#define RTC_TSTR_HU RTC_TSTR_HU_Msk +#define RTC_TSTR_MNT_Pos (12U) +#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk +#define RTC_TSTR_MNU_Pos (8U) +#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk +#define RTC_TSTR_ST_Pos (4U) +#define RTC_TSTR_ST RTC_TSTR_ST_Msk +#define RTC_TSTR_SU_Pos (0U) +#define RTC_TSTR_SU RTC_TSTR_SU_Msk + +/******************** Bits definition for RTC_TSDR register ****************/ +#define RTC_TSDR_WDU_Pos (13U) +#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk +#define RTC_TSDR_MT_Pos (12U) +#define RTC_TSDR_MT RTC_TSDR_MT_Msk +#define RTC_TSDR_MU_Pos (8U) +#define RTC_TSDR_MU RTC_TSDR_MU_Msk +#define RTC_TSDR_DT_Pos (4U) +#define RTC_TSDR_DT RTC_TSDR_DT_Msk +#define RTC_TSDR_DU_Pos (0U) +#define RTC_TSDR_DU RTC_TSDR_DU_Msk + +/******************** Bits definition for RTC_TSSSR register ***************/ +#define RTC_TSSSR_SS_Pos (0U) +#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk + +/******************** Bits definition for RTC_CALR register ****************/ +#define RTC_CALR_CALP_Pos (15U) +#define RTC_CALR_CALP RTC_CALR_CALP_Msk +#define RTC_CALR_CALW8_Pos (14U) +#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk +#define RTC_CALR_CALW16_Pos (13U) +#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk +#define RTC_CALR_CALM_Pos (0U) +#define RTC_CALR_CALM RTC_CALR_CALM_Msk + +/******************** Bits definition for RTC_TAFCR register ***************/ +#define RTC_TAFCR_PC15MODE_Pos (23U) +#define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk +#define RTC_TAFCR_PC15VALUE_Pos (22U) +#define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk +#define RTC_TAFCR_PC14MODE_Pos (21U) +#define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk +#define RTC_TAFCR_PC14VALUE_Pos (20U) +#define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk +#define RTC_TAFCR_PC13MODE_Pos (19U) +#define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk +#define RTC_TAFCR_PC13VALUE_Pos (18U) +#define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk +#define RTC_TAFCR_TAMPPUDIS_Pos (15U) +#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk +#define RTC_TAFCR_TAMPPRCH_Pos (13U) +#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk +#define RTC_TAFCR_TAMPFLT_Pos (11U) +#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk +#define RTC_TAFCR_TAMPFREQ_Pos (8U) +#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk +#define RTC_TAFCR_TAMPTS_Pos (7U) +#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk +#define RTC_TAFCR_TAMP2TRG_Pos (4U) +#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk +#define RTC_TAFCR_TAMP2E_Pos (3U) +#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk +#define RTC_TAFCR_TAMPIE_Pos (2U) +#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk +#define RTC_TAFCR_TAMP1TRG_Pos (1U) +#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk +#define RTC_TAFCR_TAMP1E_Pos (0U) +#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk + +/* Reference defines */ +#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE + +/******************** Bits definition for RTC_ALRMASSR register ************/ +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk + +/*****************************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/*****************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + */ +/* Note: No specific macro feature on this device */ + +/******************* Bit definition for SPI_CR1 register *******************/ +#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPOL_Pos (1U) +#define SPI_CR1_MSTR_Pos (2U) +#define SPI_CR1_BR_Pos (3U) +#define SPI_CR1_SPE_Pos (6U) +#define SPI_CR1_LSBFIRST_Pos (7U) +#define SPI_CR1_SSI_Pos (8U) +#define SPI_CR1_SSM_Pos (9U) +#define SPI_CR1_RXONLY_Pos (10U) +#define SPI_CR1_CRCL_Pos (11U) +#define SPI_CR1_CRCNEXT_Pos (12U) +#define SPI_CR1_CRCEN_Pos (13U) +#define SPI_CR1_BIDIOE_Pos (14U) +#define SPI_CR1_BIDIMODE_Pos (15U) + +/******************* Bit definition for SPI_CR2 register *******************/ +#define SPI_CR2_RXDMAEN_Pos (0U) +#define SPI_CR2_TXDMAEN_Pos (1U) +#define SPI_CR2_SSOE_Pos (2U) +#define SPI_CR2_NSSP_Pos (3U) +#define SPI_CR2_FRF_Pos (4U) +#define SPI_CR2_ERRIE_Pos (5U) +#define SPI_CR2_RXNEIE_Pos (6U) +#define SPI_CR2_TXEIE_Pos (7U) +#define SPI_CR2_DS_Pos (8U) +#define SPI_CR2_FRXTH_Pos (12U) +#define SPI_CR2_LDMARX_Pos (13U) +#define SPI_CR2_LDMATX_Pos (14U) + +/******************** Bit definition for SPI_SR register *******************/ +#define SPI_SR_RXNE_Pos (0U) +#define SPI_SR_TXE_Pos (1U) +#define SPI_SR_CRCERR_Pos (4U) +#define SPI_SR_MODF_Pos (5U) +#define SPI_SR_OVR_Pos (6U) +#define SPI_SR_BSY_Pos (7U) +#define SPI_SR_FRE_Pos (8U) +#define SPI_SR_FRLVL_Pos (9U) +#define SPI_SR_FTLVL_Pos (11U) + +/******************** Bit definition for SPI_DR register *******************/ +#define SPI_DR_DR_Pos (0U) + +/******************* Bit definition for SPI_CRCPR register *****************/ +#define SPI_CRCPR_CRCPOLY_Pos (0U) + +/****************** Bit definition for SPI_RXCRCR register *****************/ +#define SPI_RXCRCR_RXCRC_Pos (0U) + +/****************** Bit definition for SPI_TXCRCR register *****************/ +#define SPI_TXCRCR_TXCRC_Pos (0U) + +/****************** Bit definition for SPI_I2SCFGR register ****************/ +#define SPI_I2SCFGR_I2SMOD_Pos (11U) + +/*****************************************************************************/ +/* */ +/* System Configuration (SYSCFG) */ +/* */ +/*****************************************************************************/ +/***************** Bit definition for SYSCFG_CFGR1 register ****************/ +#define SYSCFG_CFGR1_MEM_MODE_Pos (0U) + + +#define SYSCFG_CFGR1_I2C_FMP_PB6_Pos (16U) +#define SYSCFG_CFGR1_I2C_FMP_PB7_Pos (17U) +#define SYSCFG_CFGR1_I2C_FMP_PB8_Pos (18U) +#define SYSCFG_CFGR1_I2C_FMP_PB9_Pos (19U) +#define SYSCFG_CFGR1_I2C_FMP_I2C1_Pos (20U) +#define SYSCFG_CFGR1_I2C_FMP_PA9_Pos (22U) +#define SYSCFG_CFGR1_I2C_FMP_PA10_Pos (23U) + +/***************** Bit definition for SYSCFG_EXTICR1 register **************/ +#define SYSCFG_EXTICR1_EXTI0_Pos (0U) +#define SYSCFG_EXTICR1_EXTI1_Pos (4U) +#define SYSCFG_EXTICR1_EXTI2_Pos (8U) +#define SYSCFG_EXTICR1_EXTI3_Pos (12U) + +/** + * @brief EXTI0 configuration + */ + +/** + * @brief EXTI1 configuration + */ + +/** + * @brief EXTI2 configuration + */ + +/** + * @brief EXTI3 configuration + */ + +/***************** Bit definition for SYSCFG_EXTICR2 register **************/ +#define SYSCFG_EXTICR2_EXTI4_Pos (0U) +#define SYSCFG_EXTICR2_EXTI5_Pos (4U) +#define SYSCFG_EXTICR2_EXTI6_Pos (8U) +#define SYSCFG_EXTICR2_EXTI7_Pos (12U) + +/** + * @brief EXTI4 configuration + */ + +/** + * @brief EXTI5 configuration + */ + +/** + * @brief EXTI6 configuration + */ + +/** + * @brief EXTI7 configuration + */ + +/***************** Bit definition for SYSCFG_EXTICR3 register **************/ +#define SYSCFG_EXTICR3_EXTI8_Pos (0U) +#define SYSCFG_EXTICR3_EXTI9_Pos (4U) +#define SYSCFG_EXTICR3_EXTI10_Pos (8U) +#define SYSCFG_EXTICR3_EXTI11_Pos (12U) + +/** + * @brief EXTI8 configuration + */ + + +/** + * @brief EXTI9 configuration + */ + +/** + * @brief EXTI10 configuration + */ + +/** + * @brief EXTI11 configuration + */ + +/***************** Bit definition for SYSCFG_EXTICR4 register **************/ +#define SYSCFG_EXTICR4_EXTI12_Pos (0U) +#define SYSCFG_EXTICR4_EXTI13_Pos (4U) +#define SYSCFG_EXTICR4_EXTI14_Pos (8U) +#define SYSCFG_EXTICR4_EXTI15_Pos (12U) + +/** + * @brief EXTI12 configuration + */ + +/** + * @brief EXTI13 configuration + */ + +/** + * @brief EXTI14 configuration + */ + +/** + * @brief EXTI15 configuration + */ + +/***************** Bit definition for SYSCFG_CFGR2 register ****************/ +#define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U) +#define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos (1U) +#define SYSCFG_CFGR2_SRAM_PEF_Pos (8U) + +/*****************************************************************************/ +/* */ +/* Timers (TIM) */ +/* */ +/*****************************************************************************/ +/******************* Bit definition for TIM_CR1 register *******************/ +#define TIM_CR1_CEN_Pos (0U) +#define TIM_CR1_UDIS_Pos (1U) +#define TIM_CR1_URS_Pos (2U) +#define TIM_CR1_OPM_Pos (3U) +#define TIM_CR1_DIR_Pos (4U) + +#define TIM_CR1_CMS_Pos (5U) + +#define TIM_CR1_ARPE_Pos (7U) + +#define TIM_CR1_CKD_Pos (8U) + +/******************* Bit definition for TIM_CR2 register *******************/ +#define TIM_CR2_CCPC_Pos (0U) +#define TIM_CR2_CCUS_Pos (2U) +#define TIM_CR2_CCDS_Pos (3U) + +#define TIM_CR2_MMS_Pos (4U) + +#define TIM_CR2_TI1S_Pos (7U) +#define TIM_CR2_OIS1_Pos (8U) +#define TIM_CR2_OIS1N_Pos (9U) +#define TIM_CR2_OIS2_Pos (10U) +#define TIM_CR2_OIS2N_Pos (11U) +#define TIM_CR2_OIS3_Pos (12U) +#define TIM_CR2_OIS3N_Pos (13U) +#define TIM_CR2_OIS4_Pos (14U) + +/******************* Bit definition for TIM_SMCR register ******************/ +#define TIM_SMCR_SMS_Pos (0U) + +#define TIM_SMCR_OCCS_Pos (3U) + +#define TIM_SMCR_TS_Pos (4U) + +#define TIM_SMCR_MSM_Pos (7U) + +#define TIM_SMCR_ETF_Pos (8U) + +#define TIM_SMCR_ETPS_Pos (12U) + +#define TIM_SMCR_ECE_Pos (14U) +#define TIM_SMCR_ETP_Pos (15U) + +/******************* Bit definition for TIM_DIER register ******************/ +#define TIM_DIER_UIE_Pos (0U) +#define TIM_DIER_CC1IE_Pos (1U) +#define TIM_DIER_CC2IE_Pos (2U) +#define TIM_DIER_CC3IE_Pos (3U) +#define TIM_DIER_CC4IE_Pos (4U) +#define TIM_DIER_COMIE_Pos (5U) +#define TIM_DIER_TIE_Pos (6U) +#define TIM_DIER_BIE_Pos (7U) +#define TIM_DIER_UDE_Pos (8U) +#define TIM_DIER_CC1DE_Pos (9U) +#define TIM_DIER_CC2DE_Pos (10U) +#define TIM_DIER_CC3DE_Pos (11U) +#define TIM_DIER_CC4DE_Pos (12U) +#define TIM_DIER_COMDE_Pos (13U) +#define TIM_DIER_TDE_Pos (14U) + +/******************** Bit definition for TIM_SR register *******************/ +#define TIM_SR_UIF_Pos (0U) +#define TIM_SR_CC1IF_Pos (1U) +#define TIM_SR_CC2IF_Pos (2U) +#define TIM_SR_CC3IF_Pos (3U) +#define TIM_SR_CC4IF_Pos (4U) +#define TIM_SR_COMIF_Pos (5U) +#define TIM_SR_TIF_Pos (6U) +#define TIM_SR_BIF_Pos (7U) +#define TIM_SR_CC1OF_Pos (9U) +#define TIM_SR_CC2OF_Pos (10U) +#define TIM_SR_CC3OF_Pos (11U) +#define TIM_SR_CC4OF_Pos (12U) + +/******************* Bit definition for TIM_EGR register *******************/ +#define TIM_EGR_UG_Pos (0U) +#define TIM_EGR_CC1G_Pos (1U) +#define TIM_EGR_CC2G_Pos (2U) +#define TIM_EGR_CC3G_Pos (3U) +#define TIM_EGR_CC4G_Pos (4U) +#define TIM_EGR_COMG_Pos (5U) +#define TIM_EGR_TG_Pos (6U) +#define TIM_EGR_BG_Pos (7U) + +/****************** Bit definition for TIM_CCMR1 register ******************/ +#define TIM_CCMR1_CC1S_Pos (0U) + +#define TIM_CCMR1_OC1FE_Pos (2U) +#define TIM_CCMR1_OC1PE_Pos (3U) + +#define TIM_CCMR1_OC1M_Pos (4U) + +#define TIM_CCMR1_OC1CE_Pos (7U) + +#define TIM_CCMR1_CC2S_Pos (8U) + +#define TIM_CCMR1_OC2FE_Pos (10U) +#define TIM_CCMR1_OC2PE_Pos (11U) + +#define TIM_CCMR1_OC2M_Pos (12U) + +#define TIM_CCMR1_OC2CE_Pos (15U) + +/*---------------------------------------------------------------------------*/ + +#define TIM_CCMR1_IC1PSC_Pos (2U) + +#define TIM_CCMR1_IC1F_Pos (4U) + +#define TIM_CCMR1_IC2PSC_Pos (10U) + +#define TIM_CCMR1_IC2F_Pos (12U) + +/****************** Bit definition for TIM_CCMR2 register ******************/ +#define TIM_CCMR2_CC3S_Pos (0U) + +#define TIM_CCMR2_OC3FE_Pos (2U) +#define TIM_CCMR2_OC3PE_Pos (3U) + +#define TIM_CCMR2_OC3M_Pos (4U) + +#define TIM_CCMR2_OC3CE_Pos (7U) + +#define TIM_CCMR2_CC4S_Pos (8U) + +#define TIM_CCMR2_OC4FE_Pos (10U) +#define TIM_CCMR2_OC4PE_Pos (11U) + +#define TIM_CCMR2_OC4M_Pos (12U) + +#define TIM_CCMR2_OC4CE_Pos (15U) + +/*---------------------------------------------------------------------------*/ + +#define TIM_CCMR2_IC3PSC_Pos (2U) + +#define TIM_CCMR2_IC3F_Pos (4U) + +#define TIM_CCMR2_IC4PSC_Pos (10U) + +#define TIM_CCMR2_IC4F_Pos (12U) + +/******************* Bit definition for TIM_CCER register ******************/ +#define TIM_CCER_CC1E_Pos (0U) +#define TIM_CCER_CC1P_Pos (1U) +#define TIM_CCER_CC1NE_Pos (2U) +#define TIM_CCER_CC1NP_Pos (3U) +#define TIM_CCER_CC2E_Pos (4U) +#define TIM_CCER_CC2P_Pos (5U) +#define TIM_CCER_CC2NE_Pos (6U) +#define TIM_CCER_CC2NP_Pos (7U) +#define TIM_CCER_CC3E_Pos (8U) +#define TIM_CCER_CC3P_Pos (9U) +#define TIM_CCER_CC3NE_Pos (10U) +#define TIM_CCER_CC3NP_Pos (11U) +#define TIM_CCER_CC4E_Pos (12U) +#define TIM_CCER_CC4P_Pos (13U) +#define TIM_CCER_CC4NP_Pos (15U) + +/******************* Bit definition for TIM_CNT register *******************/ +#define TIM_CNT_CNT_Pos (0U) + +/******************* Bit definition for TIM_PSC register *******************/ +#define TIM_PSC_PSC_Pos (0U) + +/******************* Bit definition for TIM_ARR register *******************/ +#define TIM_ARR_ARR_Pos (0U) + +/******************* Bit definition for TIM_RCR register *******************/ +#define TIM_RCR_REP_Pos (0U) + +/******************* Bit definition for TIM_CCR1 register ******************/ +#define TIM_CCR1_CCR1_Pos (0U) + +/******************* Bit definition for TIM_CCR2 register ******************/ +#define TIM_CCR2_CCR2_Pos (0U) + +/******************* Bit definition for TIM_CCR3 register ******************/ +#define TIM_CCR3_CCR3_Pos (0U) + +/******************* Bit definition for TIM_CCR4 register ******************/ +#define TIM_CCR4_CCR4_Pos (0U) + +/******************* Bit definition for TIM_BDTR register ******************/ +#define TIM_BDTR_DTG_Pos (0U) + +#define TIM_BDTR_LOCK_Pos (8U) + +#define TIM_BDTR_OSSI_Pos (10U) +#define TIM_BDTR_OSSR_Pos (11U) +#define TIM_BDTR_BKE_Pos (12U) +#define TIM_BDTR_BKP_Pos (13U) +#define TIM_BDTR_AOE_Pos (14U) +#define TIM_BDTR_MOE_Pos (15U) + +/******************* Bit definition for TIM_DCR register *******************/ +#define TIM_DCR_DBA_Pos (0U) + +#define TIM_DCR_DBL_Pos (8U) + +/******************* Bit definition for TIM_DMAR register ******************/ +#define TIM_DMAR_DMAB_Pos (0U) + +/******************* Bit definition for TIM14_OR register ********************/ +#define TIM14_OR_TI1_RMP_Pos (0U) + +/******************************************************************************/ +/* */ +/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ +/* */ +/******************************************************************************/ + +/* +* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +*/ + +/* Support of 7 bits data length feature */ +#define USART_7BITS_SUPPORT + +/* Support of Full Auto Baud rate feature (4 modes) activation */ +#define USART_FABR_SUPPORT + +/****************** Bit definition for USART_CR1 register *******************/ +#define USART_CR1_UE_Pos (0U) +#define USART_CR1_RE_Pos (2U) +#define USART_CR1_TE_Pos (3U) +#define USART_CR1_IDLEIE_Pos (4U) +#define USART_CR1_RXNEIE_Pos (5U) +#define USART_CR1_TCIE_Pos (6U) +#define USART_CR1_TXEIE_Pos (7U) +#define USART_CR1_PEIE_Pos (8U) +#define USART_CR1_PS_Pos (9U) +#define USART_CR1_PCE_Pos (10U) +#define USART_CR1_WAKE_Pos (11U) +#define USART_CR1_M0_Pos (12U) +#define USART_CR1_MME_Pos (13U) +#define USART_CR1_CMIE_Pos (14U) +#define USART_CR1_OVER8_Pos (15U) +#define USART_CR1_DEDT_Pos (16U) +#define USART_CR1_DEAT_Pos (21U) +#define USART_CR1_RTOIE_Pos (26U) +#define USART_CR1_EOBIE_Pos (27U) +#define USART_CR1_M1_Pos (28U) +#define USART_CR1_M_Pos (12U) + +/****************** Bit definition for USART_CR2 register *******************/ +#define USART_CR2_ADDM7_Pos (4U) +#define USART_CR2_LBCL_Pos (8U) +#define USART_CR2_CPHA_Pos (9U) +#define USART_CR2_CPOL_Pos (10U) +#define USART_CR2_CLKEN_Pos (11U) +#define USART_CR2_STOP_Pos (12U) +#define USART_CR2_SWAP_Pos (15U) +#define USART_CR2_RXINV_Pos (16U) +#define USART_CR2_TXINV_Pos (17U) +#define USART_CR2_DATAINV_Pos (18U) +#define USART_CR2_MSBFIRST_Pos (19U) +#define USART_CR2_ABREN_Pos (20U) +#define USART_CR2_ABRMODE_Pos (21U) +#define USART_CR2_RTOEN_Pos (23U) +#define USART_CR2_ADD_Pos (24U) + +/****************** Bit definition for USART_CR3 register *******************/ +#define USART_CR3_EIE_Pos (0U) +#define USART_CR3_HDSEL_Pos (3U) +#define USART_CR3_DMAR_Pos (6U) +#define USART_CR3_DMAT_Pos (7U) +#define USART_CR3_RTSE_Pos (8U) +#define USART_CR3_CTSE_Pos (9U) +#define USART_CR3_CTSIE_Pos (10U) +#define USART_CR3_ONEBIT_Pos (11U) +#define USART_CR3_OVRDIS_Pos (12U) +#define USART_CR3_DDRE_Pos (13U) +#define USART_CR3_DEM_Pos (14U) +#define USART_CR3_DEP_Pos (15U) + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_FRACTION_Pos (0U) +#define USART_BRR_DIV_MANTISSA_Pos (4U) + +/****************** Bit definition for USART_GTPR register ******************/ +#define USART_GTPR_PSC_Pos (0U) +#define USART_GTPR_GT_Pos (8U) + + +/******************* Bit definition for USART_RTOR register *****************/ +#define USART_RTOR_RTO_Pos (0U) +#define USART_RTOR_BLEN_Pos (24U) + +/******************* Bit definition for USART_RQR register ******************/ +#define USART_RQR_ABRRQ_Pos (0U) +#define USART_RQR_SBKRQ_Pos (1U) +#define USART_RQR_MMRQ_Pos (2U) +#define USART_RQR_RXFRQ_Pos (3U) + +/******************* Bit definition for USART_ISR register ******************/ +#define USART_ISR_PE_Pos (0U) +#define USART_ISR_FE_Pos (1U) +#define USART_ISR_NE_Pos (2U) +#define USART_ISR_ORE_Pos (3U) +#define USART_ISR_IDLE_Pos (4U) +#define USART_ISR_RXNE_Pos (5U) +#define USART_ISR_TC_Pos (6U) +#define USART_ISR_TXE_Pos (7U) +#define USART_ISR_CTSIF_Pos (9U) +#define USART_ISR_CTS_Pos (10U) +#define USART_ISR_RTOF_Pos (11U) +#define USART_ISR_ABRE_Pos (14U) +#define USART_ISR_ABRF_Pos (15U) +#define USART_ISR_BUSY_Pos (16U) +#define USART_ISR_CMF_Pos (17U) +#define USART_ISR_SBKF_Pos (18U) +#define USART_ISR_RWU_Pos (19U) +#define USART_ISR_TEACK_Pos (21U) +#define USART_ISR_REACK_Pos (22U) + +/******************* Bit definition for USART_ICR register ******************/ +#define USART_ICR_PECF_Pos (0U) +#define USART_ICR_FECF_Pos (1U) +#define USART_ICR_NCF_Pos (2U) +#define USART_ICR_ORECF_Pos (3U) +#define USART_ICR_IDLECF_Pos (4U) +#define USART_ICR_TCCF_Pos (6U) +#define USART_ICR_CTSCF_Pos (9U) +#define USART_ICR_RTOCF_Pos (11U) +#define USART_ICR_CMCF_Pos (17U) + +/******************* Bit definition for USART_RDR register ******************/ + +/******************* Bit definition for USART_TDR register ******************/ + +/******************************************************************************/ +/* */ +/* Window WATCHDOG (WWDG) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CR register ********************/ +#define WWDG_CR_T_Pos (0U) + +/* Legacy defines */ +#define WWDG_CR_T0 WWDG_CR_T_0 +#define WWDG_CR_T1 WWDG_CR_T_1 +#define WWDG_CR_T2 WWDG_CR_T_2 +#define WWDG_CR_T3 WWDG_CR_T_3 +#define WWDG_CR_T4 WWDG_CR_T_4 +#define WWDG_CR_T5 WWDG_CR_T_5 +#define WWDG_CR_T6 WWDG_CR_T_6 + +#define WWDG_CR_WDGA_Pos (7U) + +/******************* Bit definition for WWDG_CFR register *******************/ +#define WWDG_CFR_W_Pos (0U) + +/* Legacy defines */ +#define WWDG_CFR_W0 WWDG_CFR_W_0 +#define WWDG_CFR_W1 WWDG_CFR_W_1 +#define WWDG_CFR_W2 WWDG_CFR_W_2 +#define WWDG_CFR_W3 WWDG_CFR_W_3 +#define WWDG_CFR_W4 WWDG_CFR_W_4 +#define WWDG_CFR_W5 WWDG_CFR_W_5 +#define WWDG_CFR_W6 WWDG_CFR_W_6 + +#define WWDG_CFR_WDGTB_Pos (7U) + +/* Legacy defines */ +#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 +#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 + +#define WWDG_CFR_EWI_Pos (9U) + +/******************* Bit definition for WWDG_SR register ********************/ +#define WWDG_SR_EWIF_Pos (0U) + +/** + * @} + */ + + /** + * @} + */ + + +/** @addtogroup Exported_macro + * @{ + */ + +/****************************** ADC Instances *********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) + +#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC) + +/****************************** CRC Instances *********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) + +/******************************* DMA Instances ********************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || ((INSTANCE) == DMA1_Channel2) || ((INSTANCE) == DMA1_Channel3) || ((INSTANCE) == DMA1_Channel4) || ((INSTANCE) == DMA1_Channel5)) + +/****************************** GPIO Instances ********************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || ((INSTANCE) == GPIOB) || ((INSTANCE) == GPIOC) || ((INSTANCE) == GPIOD) || ((INSTANCE) == GPIOF)) + +/**************************** GPIO Alternate Function Instances ***************/ +#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || ((INSTANCE) == GPIOB)) + +/****************************** GPIO Lock Instances ***************************/ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || ((INSTANCE) == GPIOB)) + +/****************************** I2C Instances *********************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || ((INSTANCE) == I2C2)) + + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) + +/****************************** SMBUS Instances *********************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1) + +/****************************** SPI Instances *********************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || ((INSTANCE) == SPI2)) + +/****************************** TIM Instances *********************************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM6) || ((INSTANCE) == TIM7) || ((INSTANCE) == TIM14) || ((INSTANCE) == TIM15) || ((INSTANCE) == TIM16) || ((INSTANCE) == TIM17)) + +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM14) || ((INSTANCE) == TIM15) || ((INSTANCE) == TIM16) || ((INSTANCE) == TIM17)) + +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM15)) + +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM3)) + +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM3)) + +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM3)) + +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM3)) + +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM15)) + +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM15)) + +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM3)) + +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM3)) + +#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)) + +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)) + +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM3)) + +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM6) || ((INSTANCE) == TIM7) || ((INSTANCE) == TIM15)) + +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM15)) + +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(0) + +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM15) || ((INSTANCE) == TIM16) || ((INSTANCE) == TIM17)) + +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM15) || ((INSTANCE) == TIM16) || ((INSTANCE) == TIM17)) + +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == TIM1) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4))) || (((INSTANCE) == TIM3) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4))) || (((INSTANCE) == TIM14) && (((CHANNEL) == TIM_CHANNEL_1))) || (((INSTANCE) == TIM15) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2))) || (((INSTANCE) == TIM16) && (((CHANNEL) == TIM_CHANNEL_1))) || (((INSTANCE) == TIM17) && (((CHANNEL) == TIM_CHANNEL_1)))) + +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == TIM1) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3))) || (((INSTANCE) == TIM15) && ((CHANNEL) == TIM_CHANNEL_1)) || (((INSTANCE) == TIM16) && ((CHANNEL) == TIM_CHANNEL_1)) || (((INSTANCE) == TIM17) && ((CHANNEL) == TIM_CHANNEL_1))) + +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM3)) + +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM15) || ((INSTANCE) == TIM16) || ((INSTANCE) == TIM17)) + +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM14) || ((INSTANCE) == TIM15) || ((INSTANCE) == TIM16) || ((INSTANCE) == TIM17)) + +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM6) || ((INSTANCE) == TIM7) || ((INSTANCE) == TIM15) || ((INSTANCE) == TIM16) || ((INSTANCE) == TIM17)) + +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM15) || ((INSTANCE) == TIM16) || ((INSTANCE) == TIM17)) + +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM15) || ((INSTANCE) == TIM16) || ((INSTANCE) == TIM17)) + +#define IS_TIM_REMAP_INSTANCE(INSTANCE) ((INSTANCE) == TIM14) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3) || ((INSTANCE) == USART4) || ((INSTANCE) == USART5)) + +/******************** USART Instances : auto Baud rate detection **************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3) || ((INSTANCE) == USART4) || ((INSTANCE) == USART5) || ((INSTANCE) == USART6)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3) || ((INSTANCE) == USART4) || ((INSTANCE) == USART5) || ((INSTANCE) == USART6)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3) || ((INSTANCE) == USART4)) + +/****************** UART Instances : Driver enable detection ********************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3) || ((INSTANCE) == USART4) || ((INSTANCE) == USART5) || ((INSTANCE) == USART6)) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) + +/** + * @} + */ + + +/******************************************************************************/ +/* For a painless codes migration between the STM32F0xx device product */ +/* lines, the aliases defined below are put in place to overcome the */ +/* differences in the interrupt handlers and IRQn definitions. */ +/* No need to update developed interrupt code when moving across */ +/* product lines within the same STM32F0 Family */ +/******************************************************************************/ + +/* Aliases for __IRQn */ +#define ADC1_COMP_IRQn ADC1_IRQn +#define DMA1_Ch1_IRQn DMA1_Channel1_IRQn +#define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn +#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn +#define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn +#define RCC_CRS_IRQn RCC_IRQn +#define TIM6_DAC_IRQn TIM6_IRQn +#define USART3_4_IRQn USART3_6_IRQn +#define USART3_8_IRQn USART3_6_IRQn + + +/* Aliases for __IRQHandler */ +#define ADC1_COMP_IRQHandler ADC1_IRQHandler +#define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler +#define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler +#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler +#define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler +#define RCC_CRS_IRQHandler RCC_IRQHandler +#define TIM6_DAC_IRQHandler TIM6_IRQHandler +#define USART3_4_IRQHandler USART3_6_IRQHandler +#define USART3_8_IRQHandler USART3_6_IRQHandler + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F030xC_H */ + +/** + * @} + */ + + /** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/system/include/cmsis/stm32f0xx.h b/system/include/cmsis/stm32f0xx.h new file mode 100644 index 0000000..53c6bc6 --- /dev/null +++ b/system/include/cmsis/stm32f0xx.h @@ -0,0 +1,5710 @@ +/** + ****************************************************************************** + * @file stm32f0xx.h + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F0xx devices. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The device used in the target application + * - To use or not the peripheral???s drivers in application code(i.e. + * code will be based on direct access to peripheral???s registers + * rather than drivers API), this option is controlled by + * "#define USE_STDPERIPH_DRIVER" + * - To change few application-specific parameters such as the HSE + * crystal frequency + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral???s registers hardware + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx + * @{ + */ + +#ifndef __STM32F0XX_H +#define __STM32F0XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32F0 device used in your + application + */ + +#if !defined (STM32F030) && !defined (STM32F031) && !defined (STM32F051) && \ + !defined (STM32F072) && !defined (STM32F042) && !defined (STM32F091) && \ + !defined (STM32F070xB) && !defined (STM32F070x6) && !defined (STM32F030xC) + /* #define STM32F030 */ + /* #define STM32F031 */ + /* #define STM32F051 */ + /* #define STM32F072 */ + /* #define STM32F070xB */ + /* #define STM32F042 */ + /* #define STM32F070x6 */ + /* #define STM32F091 */ + /* #define STM32F030xC */ +#endif /* STM32F030 || STM32F031 || STM32F051 || STM32F072 || STM32F042 || STM32F091 || + STM32F070xB || STM32F070x6 || STM32F030xC */ + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +/* Old STM32F0XX definition, maintained for legacy purpose */ +#if defined(STM32F0XX) || defined(STM32F0XX_MD) + #define STM32F051 +#endif /* STM32F0XX */ + +/* Old STM32F0XX_LD definition, maintained for legacy purpose */ +#ifdef STM32F0XX_LD + #define STM32F031 +#endif /* STM32F0XX_LD */ + +/* Old STM32F0XX_HD definition, maintained for legacy purpose */ +#ifdef STM32F0XX_HD + #define STM32F072 +#endif /* STM32F0XX_HD */ + +/* Old STM32F030X6/X8 definition, maintained for legacy purpose */ +#if defined (STM32F030X8) || defined (STM32F030X6) + #define STM32F030 +#endif /* STM32F030X8 or STM32F030X6 */ + + +#if !defined (STM32F030) && !defined (STM32F031) && !defined (STM32F051) && \ + !defined (STM32F072) && !defined (STM32F042) && !defined (STM32F091) && \ + !defined (STM32F070xB) && !defined (STM32F070x6) && !defined (STM32F030xC) + #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)" +#endif /* STM32F030 || STM32F031 || STM32F051 || STM32F072 || STM32F042 || STM32F091 || + STM32F070xB || STM32F070x6 || STM32F030xC */ + +#if !defined USE_STDPERIPH_DRIVER +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif /* USE_STDPERIPH_DRIVER */ + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/ +#endif /* HSE_VALUE */ + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSE start up */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup + Timeout value + */ +#if !defined (HSI_STARTUP_TIMEOUT) +#define HSI_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSI start up */ +#endif /* HSI_STARTUP_TIMEOUT */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal High Speed oscillator in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* HSI_VALUE */ + +#if !defined (HSI14_VALUE) +#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* HSI14_VALUE */ + +#if !defined (HSI48_VALUE) +#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* HSI48_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE ((uint32_t)40000) /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* LSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +/** + * @brief STM32F0xx Standard Peripheral Library version number V1.4.0 + */ +#define __STM32F0XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F0XX_STDPERIPH_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */ +#define __STM32F0XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F0XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F0XX_STDPERIPH_VERSION ((__STM32F0XX_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32F0XX_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32F0XX_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32F0XX_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief STM32F0xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +#define __CM0_REV 0 /*!< Core Revision r0p0 */ +#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */ +#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/*!< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + +#if defined (STM32F051) +/****** STM32F051 specific Interrupt Numbers *************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ + RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ + FLASH_IRQn = 3, /*!< FLASH Interrupt */ + RCC_IRQn = 4, /*!< RCC Interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + TS_IRQn = 8, /*!< Touch sense controller Interrupt */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */ + ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 Interrupt */ + TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */ + TIM14_IRQn = 19, /*!< TIM14 Interrupt */ + TIM15_IRQn = 20, /*!< TIM15 Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt */ + I2C2_IRQn = 24, /*!< I2C2 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28, /*!< USART2 Interrupt */ + CEC_IRQn = 30 /*!< CEC Interrupt */ +#elif defined (STM32F031) +/****** STM32F031 specific Interrupt Numbers *************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ + RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ + FLASH_IRQn = 3, /*!< FLASH Interrupt */ + RCC_IRQn = 4, /*!< RCC Interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */ + ADC1_IRQn = 12, /*!< ADC1 Interrupt */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + USART1_IRQn = 27 /*!< USART1 Interrupt */ +#elif defined (STM32F030) +/****** STM32F030 specific Interrupt Numbers *************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ + FLASH_IRQn = 3, /*!< FLASH Interrupt */ + RCC_IRQn = 4, /*!< RCC Interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */ + ADC1_IRQn = 12, /*!< ADC1 Interrupt */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 Interrupt */ + TIM15_IRQn = 20, /*!< TIM15 Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt */ + I2C2_IRQn = 24, /*!< I2C2 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28 /*!< USART2 Interrupt */ +#elif defined (STM32F072) + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_VDDIO2_IRQn = 1, /*!< PVD and VDDIO2 supply comparator through EXTI Line detect Interrupt */ + RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ + FLASH_IRQn = 3, /*!< FLASH Interrupt */ + RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */ + EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + TSC_IRQn = 8, /*!< TSC Interrupt */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ + ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 Interrupt */ + TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */ + TIM7_IRQn = 18, /*!< TIM7 Interrupts */ + TIM14_IRQn = 19, /*!< TIM14 Interrupt */ + TIM15_IRQn = 20, /*!< TIM15 Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt */ + I2C2_IRQn = 24, /*!< I2C2 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28, /*!< USART2 Interrupt */ + USART3_4_IRQn = 29, /*!< USART3 and USART4 Interrupts */ + CEC_CAN_IRQn = 30, /*!< CEC and CAN Interrupts */ + USB_IRQn = 31 /*!< USB Low Priority global Interrupt */ +#elif defined (STM32F042) + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_VDDIO2_IRQn = 1, /*!< PVD and VDDIO2 supply comparator through EXTI Line detect Interrupt */ + RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ + FLASH_IRQn = 3, /*!< FLASH Interrupt */ + RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */ + EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + TSC_IRQn = 8, /*!< TSC Interrupt */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4, Channel 5 Interrupts */ + ADC1_IRQn = 12, /*!< ADC1 Interrupts */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28, /*!< USART2 Interrupt */ + CEC_CAN_IRQn = 30, /*!< CEC and CAN Interrupts */ + USB_IRQn = 31 /*!< USB Low Priority global Interrupt */ +#elif defined (STM32F091) + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_VDDIO2_IRQn = 1, /*!< PVD & VDDIO2 Interrupts through EXTI Lines 16 and 31 */ + RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCC_CRS_IRQn = 4, /*!< RCC & CRS Global Interrupts */ + EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + TSC_IRQn = 8, /*!< Touch Sensing Controller Interrupts */ + DMA1_Ch1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Ch2_3_DMA2_Ch1_2_IRQn = 10, /*!< DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2 Interrupts */ + DMA1_Ch4_7_DMA2_Ch3_5_IRQn = 11, /*!< DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5 Interrupts */ + ADC1_COMP_IRQn = 12, /*!< ADC, COMP1 and COMP2 Interrupts (EXTI Lines 21 and 22) */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ + TIM6_DAC_IRQn = 17, /*!< TIM6 global and DAC channel underrun error Interrupts */ + TIM7_IRQn = 18, /*!< TIM7 global Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ + TIM15_IRQn = 20, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ + I2C2_IRQn = 24, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */ + SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 global Interrupt */ + USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ + USART2_IRQn = 28, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ + USART3_8_IRQn = 29, /*!< USART3 to USART8 global Interrupts */ + CEC_CAN_IRQn = 30 /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt */ +#elif defined (STM32F070xB) + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCC_IRQn = 4, /*!< RCC Global Interrupts */ + EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */ + ADC1_IRQn = 12, /*!< ADC1 interrupts (ADC interrupt combined with EXTI Lines 21 and 22 */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ + TIM6_IRQn = 17, /*!< TIM6 global Interrupts */ + TIM7_IRQn = 18, /*!< TIM7 global Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ + TIM15_IRQn = 20, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ + I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 global Interrupt */ + USART1_IRQn = 27, /*!< USART1 global Interrupt */ + USART2_IRQn = 28, /*!< USART2 global Interrupt */ + USART3_4_IRQn = 29, /*!< USART3 and USART4 global Interrupts */ + USB_IRQn = 31 /*!< USB global Interrupts & EXTI Line18 Interrupt */ +#elif defined (STM32F070x6) + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCC_IRQn = 4, /*!< RCC Global Interrupts */ + EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */ + ADC1_IRQn = 12, /*!< ADC1 Interrupt */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ + SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ + USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ + USART2_IRQn = 28, /*!< USART2 global Interrupt */ + USB_IRQn = 31 /*!< USB global Interrupts & EXTI Line18 Interrupt */ +#elif defined (STM32F030xC) + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCC_IRQn = 4, /*!< RCC Global Interrupts */ + EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */ + ADC1_IRQn = 12, /*!< ADC Interrupts */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ + TIM6_IRQn = 17, /*!< TIM6 global Interrupts */ + TIM7_IRQn = 18, /*!< TIM7 global Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ + TIM15_IRQn = 20, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ + I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 global Interrupt */ + USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ + USART2_IRQn = 28, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ + USART3_6_IRQn = 29, /*!< USART3 to USART6 global Interrupts */ +#endif /* STM32F051 */ +}IRQn_Type; + +/** + * @} + */ + +#include "core_cm0.h" +#include "system_stm32f0xx.h" +#include + +/** @addtogroup Exported_types + * @{ + */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ + __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ + __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ + __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ + uint32_t RESERVED3; /*!< Reserved, 0x24 */ + __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ + uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ + __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief HDMI-CEC + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x1C */ +} COMP_TypeDef; + + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ + __IO uint32_t CSELR; /*!< DMA channel x selection address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ + uint32_t RESERVED0[40];/*!< Reserved as declared by channel typedef 0x08 - 0xA4*/ + __IO uint32_t RMPCR; /*!< Remap control register, Address offset: 0xA8 */ +}DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*! exti[31] Interrupt */ +#define SYSCFG_ITLINE1_SR_VDDIO2 ((uint32_t)0x00000002) /*!< VDDIO2 -> exti[16] Interrupt */ +#define SYSCFG_ITLINE2_SR_RTC_WAKEUP ((uint32_t)0x00000001) /*!< RTC WAKEUP -> exti[20] Interrupt */ +#define SYSCFG_ITLINE2_SR_RTC_TSTAMP ((uint32_t)0x00000002) /*!< RTC Time Stamp -> exti[19] interrupt */ +#define SYSCFG_ITLINE2_SR_RTC_ALRA ((uint32_t)0x00000003) /*!< RTC Alarm -> exti[17] interrupt .... */ +#define SYSCFG_ITLINE3_SR_FLASH_ITF ((uint32_t)0x00000001) /*!< Flash ITF Interrupt */ +#define SYSCFG_ITLINE4_SR_CRS ((uint32_t)0x00000001) /*!< CRS interrupt */ +#define SYSCFG_ITLINE4_SR_CLK_CTRL ((uint32_t)0x00000002) /*!< CLK CTRL interrupt */ +#define SYSCFG_ITLINE5_SR_EXTI0 ((uint32_t)0x00000001) /*!< External Interrupt 0 */ +#define SYSCFG_ITLINE5_SR_EXTI1 ((uint32_t)0x00000002) /*!< External Interrupt 1 */ +#define SYSCFG_ITLINE6_SR_EXTI2 ((uint32_t)0x00000001) /*!< External Interrupt 2 */ +#define SYSCFG_ITLINE6_SR_EXTI3 ((uint32_t)0x00000002) /*!< External Interrupt 3 */ +#define SYSCFG_ITLINE7_SR_EXTI4 ((uint32_t)0x00000001) /*!< External Interrupt 15 to 4 */ +#define SYSCFG_ITLINE7_SR_EXTI5 ((uint32_t)0x00000002) /*!< External Interrupt 15 to 4 */ +#define SYSCFG_ITLINE7_SR_EXTI6 ((uint32_t)0x00000004) /*!< External Interrupt 15 to 4 */ +#define SYSCFG_ITLINE7_SR_EXTI7 ((uint32_t)0x00000008) /*!< External Interrupt 15 to 4 */ +#define SYSCFG_ITLINE7_SR_EXTI8 ((uint32_t)0x00000010) /*!< External Interrupt 15 to 4 */ +#define SYSCFG_ITLINE7_SR_EXTI9 ((uint32_t)0x00000020) /*!< External Interrupt 15 to 4 */ +#define SYSCFG_ITLINE7_SR_EXTI10 ((uint32_t)0x00000040) /*!< External Interrupt 15 to 4 */ +#define SYSCFG_ITLINE7_SR_EXTI11 ((uint32_t)0x00000080) /*!< External Interrupt 15 to 4 */ +#define SYSCFG_ITLINE7_SR_EXTI12 ((uint32_t)0x00000100) /*!< External Interrupt 15 to 4 */ +#define SYSCFG_ITLINE7_SR_EXTI13 ((uint32_t)0x00000200) /*!< External Interrupt 15 to 4 */ +#define SYSCFG_ITLINE7_SR_EXTI14 ((uint32_t)0x00000400) /*!< External Interrupt 15 to 4 */ +#define SYSCFG_ITLINE7_SR_EXTI15 ((uint32_t)0x00000800) /*!< External Interrupt 15 to 4 */ +#define SYSCFG_ITLINE8_SR_TSC_EOA ((uint32_t)0x00000001) /*!< Touch control EOA Interrupt */ +#define SYSCFG_ITLINE8_SR_TSC_MCE ((uint32_t)0x00000002) /*!< Touch control MCE Interrupt */ +#define SYSCFG_ITLINE9_SR_DMA1_CH1 ((uint32_t)0x00000001) /*!< DMA1 Channel 1 Interrupt */ +#define SYSCFG_ITLINE10_SR_DMA1_CH2 ((uint32_t)0x00000001) /*!< DMA1 Channel 2 Interrupt */ +#define SYSCFG_ITLINE10_SR_DMA1_CH3 ((uint32_t)0x00000002) /*!< DMA2 Channel 3 Interrupt */ +#define SYSCFG_ITLINE10_SR_DMA2_CH1 ((uint32_t)0x00000004) /*!< DMA2 Channel 1 Interrupt */ +#define SYSCFG_ITLINE10_SR_DMA2_CH2 ((uint32_t)0x00000008) /*!< DMA2 Channel 2 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH4 ((uint32_t)0x00000001) /*!< DMA1 Channel 4 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH5 ((uint32_t)0x00000002) /*!< DMA1 Channel 5 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH6 ((uint32_t)0x00000004) /*!< DMA1 Channel 6 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH7 ((uint32_t)0x00000008) /*!< DMA1 Channel 7 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA2_CH3 ((uint32_t)0x00000010) /*!< DMA2 Channel 3 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA2_CH4 ((uint32_t)0x00000020) /*!< DMA2 Channel 4 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA2_CH5 ((uint32_t)0x00000040) /*!< DMA2 Channel 5 Interrupt */ +#define SYSCFG_ITLINE12_SR_ADC ((uint32_t)0x00000001) /*!< ADC Interrupt */ +#define SYSCFG_ITLINE12_SR_COMP1 ((uint32_t)0x00000002) /*!< COMP1 Interrupt -> exti[21] */ +#define SYSCFG_ITLINE12_SR_COMP2 ((uint32_t)0x00000004) /*!< COMP2 Interrupt -> exti[22] */ +#define SYSCFG_ITLINE13_SR_TIM1_BRK ((uint32_t)0x00000001) /*!< TIM1 BRK Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_UPD ((uint32_t)0x00000002) /*!< TIM1 UPD Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_TRG ((uint32_t)0x00000004) /*!< TIM1 TRG Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_CCU ((uint32_t)0x00000008) /*!< TIM1 CCU Interrupt */ +#define SYSCFG_ITLINE14_SR_TIM1_CC ((uint32_t)0x00000001) /*!< TIM1 CC Interrupt */ +#define SYSCFG_ITLINE15_SR_TIM2_GLB ((uint32_t)0x00000001) /*!< TIM2 GLB Interrupt */ +#define SYSCFG_ITLINE16_SR_TIM3_GLB ((uint32_t)0x00000001) /*!< TIM3 GLB Interrupt */ +#define SYSCFG_ITLINE17_SR_DAC ((uint32_t)0x00000001) /*!< DAC Interrupt */ +#define SYSCFG_ITLINE17_SR_TIM6_GLB ((uint32_t)0x00000002) /*!< TIM6 GLB Interrupt */ +#define SYSCFG_ITLINE18_SR_TIM7_GLB ((uint32_t)0x00000001) /*!< TIM7 GLB Interrupt */ +#define SYSCFG_ITLINE19_SR_TIM14_GLB ((uint32_t)0x00000001) /*!< TIM14 GLB Interrupt */ +#define SYSCFG_ITLINE20_SR_TIM15_GLB ((uint32_t)0x00000001) /*!< TIM15 GLB Interrupt */ +#define SYSCFG_ITLINE21_SR_TIM16_GLB ((uint32_t)0x00000001) /*!< TIM16 GLB Interrupt */ +#define SYSCFG_ITLINE22_SR_TIM17_GLB ((uint32_t)0x00000001) /*!< TIM17 GLB Interrupt */ +#define SYSCFG_ITLINE23_SR_I2C1_GLB ((uint32_t)0x00000001) /*!< I2C1 GLB Interrupt -> exti[23] */ +#define SYSCFG_ITLINE24_SR_I2C2_GLB ((uint32_t)0x00000001) /*!< I2C2 GLB Interrupt */ +#define SYSCFG_ITLINE25_SR_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Interrupt */ +#define SYSCFG_ITLINE26_SR_SPI2 ((uint32_t)0x00000001) /*!< SPI2 Interrupt */ +#define SYSCFG_ITLINE27_SR_USART1_GLB ((uint32_t)0x00000001) /*!< USART1 GLB Interrupt -> exti[25] */ +#define SYSCFG_ITLINE28_SR_USART2_GLB ((uint32_t)0x00000001) /*!< USART2 GLB Interrupt -> exti[26] */ +#define SYSCFG_ITLINE29_SR_USART3_GLB ((uint32_t)0x00000001) /*!< USART3 GLB Interrupt -> exti[28] */ +#define SYSCFG_ITLINE29_SR_USART4_GLB ((uint32_t)0x00000002) /*!< USART4 GLB Interrupt */ +#define SYSCFG_ITLINE29_SR_USART5_GLB ((uint32_t)0x00000004) /*!< USART5 GLB Interrupt */ +#define SYSCFG_ITLINE29_SR_USART6_GLB ((uint32_t)0x00000008) /*!< USART6 GLB Interrupt */ +#define SYSCFG_ITLINE29_SR_USART7_GLB ((uint32_t)0x00000010) /*!< USART7 GLB Interrupt */ +#define SYSCFG_ITLINE29_SR_USART8_GLB ((uint32_t)0x00000020) /*!< USART8 GLB Interrupt */ +#define SYSCFG_ITLINE30_SR_CAN ((uint32_t)0x00000001) /*!< CAN Interrupt */ +#define SYSCFG_ITLINE30_SR_CEC ((uint32_t)0x00000002) /*!< CEC Interrupt */ + +/******************************************************************************/ +/* */ +/* Timers (TIM) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TIM_CR1 register ********************/ +#define TIM_CR1_CEN ((uint16_t)0x0001) /*!
© COPYRIGHT 2014 STMicroelectronics
+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F0XX_H +#define __SYSTEM_STM32F0XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F0xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F0xx_System_Exported_types + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F0XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/include/cortexm/ExceptionHandlers.h b/system/include/cortexm/ExceptionHandlers.h new file mode 100644 index 0000000..4ab9dfe --- /dev/null +++ b/system/include/cortexm/ExceptionHandlers.h @@ -0,0 +1,116 @@ +/* + * This file is part of the ??OS++ distribution. + * (https://github.com/micro-os-plus) + * Copyright (c) 2014 Liviu Ionescu. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef CORTEXM_EXCEPTION_HANDLERS_H_ +#define CORTEXM_EXCEPTION_HANDLERS_H_ + +#include + +#if defined(DEBUG) +#define __DEBUG_BKPT() asm volatile ("bkpt 0") +#endif + +// ---------------------------------------------------------------------------- + +#if defined(__cplusplus) +extern "C" +{ +#endif + +// External references to cortexm_handlers.c + + extern void + Reset_Handler (void); + extern void + NMI_Handler (void); + extern void + HardFault_Handler (void); + +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) + extern void + MemManage_Handler (void); + extern void + BusFault_Handler (void); + extern void + UsageFault_Handler (void); + extern void + DebugMon_Handler (void); +#endif + + extern void + SVC_Handler (void); + + extern void + PendSV_Handler (void); + extern void + SysTick_Handler (void); + + // Exception Stack Frame of the Cortex-M3 or Cortex-M4 processor. + typedef struct + { + uint32_t r0; + uint32_t r1; + uint32_t r2; + uint32_t r3; + uint32_t r12; + uint32_t lr; + uint32_t pc; + uint32_t psr; +#if defined(__ARM_ARCH_7EM__) + uint32_t s[16]; +#endif + } ExceptionStackFrame; + +#if defined(TRACE) +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) + void + dumpExceptionStack (ExceptionStackFrame* frame, uint32_t cfsr, uint32_t mmfar, + uint32_t bfar, uint32_t lr); +#endif // defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) +#if defined(__ARM_ARCH_6M__) + void + dumpExceptionStack (ExceptionStackFrame* frame, uint32_t lr); +#endif // defined(__ARM_ARCH_6M__) +#endif // defined(TRACE) + + void + HardFault_Handler_C (ExceptionStackFrame* frame, uint32_t lr); + +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) + void + UsageFault_Handler_C (ExceptionStackFrame* frame, uint32_t lr); + void + BusFault_Handler_C (ExceptionStackFrame* frame, uint32_t lr); +#endif // defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) + +#if defined(__cplusplus) +} +#endif + +// ---------------------------------------------------------------------------- + +#endif // CORTEXM_EXCEPTION_HANDLERS_H_ diff --git a/system/include/diag/Trace.h b/system/include/diag/Trace.h new file mode 100644 index 0000000..b90005e --- /dev/null +++ b/system/include/diag/Trace.h @@ -0,0 +1,168 @@ +/* + * This file is part of the ??OS++ distribution. + * (https://github.com/micro-os-plus) + * Copyright (c) 2014 Liviu Ionescu. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef DIAG_TRACE_H_ +#define DIAG_TRACE_H_ + +// ---------------------------------------------------------------------------- + +#include + +// ---------------------------------------------------------------------------- + +// The trace device is an independent output channel, intended for debug +// purposes. +// +// The API is simple, and mimics the standard output calls: +// - trace_printf() +// - trace_puts() +// - trace_putchar(); +// +// The implementation is done in +// - trace_write() +// +// Trace support is enabled by adding the TRACE definition. +// By default the trace messages are forwarded to the ITM output, +// but can be rerouted via any device or completely suppressed by +// changing the definitions required in system/src/diag/trace_impl.c +// (currently OS_USE_TRACE_ITM, OS_USE_TRACE_SEMIHOSTING_DEBUG/_STDOUT). +// +// When TRACE is not defined, all functions are inlined to empty bodies. +// This has the advantage that the trace call do not need to be conditionally +// compiled with #ifdef TRACE/#endif + + +#if defined(TRACE) + +#if defined(__cplusplus) +extern "C" +{ +#endif + + void + trace_initialize(void); + + // Implementation dependent + ssize_t + trace_write(const char* buf, size_t nbyte); + + // ----- Portable ----- + + int + trace_printf(const char* format, ...); + + int + trace_puts(const char *s); + + int + trace_putchar(int c); + + void + trace_dump_args(int argc, char* argv[]); + +#if defined(__cplusplus) +} +#endif + +#else // !defined(TRACE) + +#if defined(__cplusplus) +extern "C" +{ +#endif + + inline void + trace_initialize(void); + + // Implementation dependent + inline ssize_t + trace_write(const char* buf, size_t nbyte); + + inline int + trace_printf(const char* format, ...); + + inline int + trace_puts(const char *s); + + inline int + trace_putchar(int c); + + inline void + trace_dump_args(int argc, char* argv[]); + +#if defined(__cplusplus) +} +#endif + +inline void +__attribute__((always_inline)) +trace_initialize(void) +{ +} + +// Empty definitions when trace is not defined +inline ssize_t +__attribute__((always_inline)) +trace_write(const char* buf __attribute__((unused)), + size_t nbyte __attribute__((unused))) +{ + return 0; +} + +inline int +__attribute__((always_inline)) +trace_printf(const char* format __attribute__((unused)), ...) + { + return 0; + } + +inline int +__attribute__((always_inline)) +trace_puts(const char *s __attribute__((unused))) +{ + return 0; +} + +inline int +__attribute__((always_inline)) +trace_putchar(int c) +{ + return c; +} + +inline void +__attribute__((always_inline)) +trace_dump_args(int argc __attribute__((unused)), + char* argv[] __attribute__((unused))) +{ +} + +#endif // defined(TRACE) + +// ---------------------------------------------------------------------------- + +#endif // DIAG_TRACE_H_ diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_adc.h b/system/include/stm32f0-stdperiph/stm32f0xx_adc.h new file mode 100644 index 0000000..f364d9c --- /dev/null +++ b/system/include/stm32f0-stdperiph/stm32f0xx_adc.h @@ -0,0 +1,450 @@ +/** + ****************************************************************************** + * @file stm32f0xx_adc.h + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file contains all the functions prototypes for the ADC firmware + * library + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_ADC_H +#define __STM32F0XX_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief ADC Init structure definition + */ + +typedef struct +{ + uint32_t ADC_Resolution; /*!< Selects the resolution of the conversion. + This parameter can be a value of @ref ADC_Resolution */ + + FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in + Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ADC_ExternalTrigConvEdge; /*!< Selects the external trigger Edge and enables the + trigger of a regular group. This parameter can be a value + of @ref ADC_external_trigger_edge_conversion */ + + uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog + to digital conversion of regular channels. This parameter + can be a value of @ref ADC_external_trigger_sources_for_channels_conversion */ + + uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_data_align */ + + uint32_t ADC_ScanDirection; /*!< Specifies in which direction the channels will be scanned + in the sequence. + This parameter can be a value of @ref ADC_Scan_Direction */ +}ADC_InitTypeDef; + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Constants + * @{ + */ +#define IS_ADC_ALL_PERIPH(PERIPH) ((PERIPH) == ADC1) + +/** @defgroup ADC_JitterOff + * @{ + */ +/* These defines are obsolete and maintained for legacy purpose only. They are replaced by the ADC_ClockMode */ +#define ADC_JitterOff_PCLKDiv2 ADC_CFGR2_JITOFFDIV2 +#define ADC_JitterOff_PCLKDiv4 ADC_CFGR2_JITOFFDIV4 + +#define IS_ADC_JITTEROFF(JITTEROFF) (((JITTEROFF) & 0x3FFFFFFF) == (uint32_t)RESET) + +/** + * @} + */ + +/** @defgroup ADC_ClockMode + * @{ + */ +#define ADC_ClockMode_AsynClk ((uint32_t)0x00000000) /*!< ADC Asynchronous clock mode */ +#define ADC_ClockMode_SynClkDiv2 ADC_CFGR2_CKMODE_0 /*!< Synchronous clock mode divided by 2 */ +#define ADC_ClockMode_SynClkDiv4 ADC_CFGR2_CKMODE_1 /*!< Synchronous clock mode divided by 4 */ +#define IS_ADC_CLOCKMODE(CLOCK) (((CLOCK) == ADC_ClockMode_AsynClk) ||\ + ((CLOCK) == ADC_ClockMode_SynClkDiv2) ||\ + ((CLOCK) == ADC_ClockMode_SynClkDiv4)) + +/** + * @} + */ + +/** @defgroup ADC_Resolution + * @{ + */ +#define ADC_Resolution_12b ((uint32_t)0x00000000) +#define ADC_Resolution_10b ADC_CFGR1_RES_0 +#define ADC_Resolution_8b ADC_CFGR1_RES_1 +#define ADC_Resolution_6b ADC_CFGR1_RES + +#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \ + ((RESOLUTION) == ADC_Resolution_10b) || \ + ((RESOLUTION) == ADC_Resolution_8b) || \ + ((RESOLUTION) == ADC_Resolution_6b)) + +/** + * @} + */ + +/** @defgroup ADC_external_trigger_edge_conversion + * @{ + */ +#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000) +#define ADC_ExternalTrigConvEdge_Rising ADC_CFGR1_EXTEN_0 +#define ADC_ExternalTrigConvEdge_Falling ADC_CFGR1_EXTEN_1 +#define ADC_ExternalTrigConvEdge_RisingFalling ADC_CFGR1_EXTEN + +#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \ + ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \ + ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \ + ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling)) +/** + * @} + */ + +/** @defgroup ADC_external_trigger_sources_for_channels_conversion + * @{ + */ + +/* TIM1 */ +#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC4 ADC_CFGR1_EXTSEL_0 + +/* TIM2 */ +#define ADC_ExternalTrigConv_T2_TRGO ADC_CFGR1_EXTSEL_1 + +/* TIM3 */ +#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_0 | ADC_CFGR1_EXTSEL_1)) + +/* TIM15 */ +#define ADC_ExternalTrigConv_T15_TRGO ADC_CFGR1_EXTSEL_2 + +#define IS_ADC_EXTERNAL_TRIG_CONV(CONV) (((CONV) == ADC_ExternalTrigConv_T1_TRGO) || \ + ((CONV) == ADC_ExternalTrigConv_T1_CC4) || \ + ((CONV) == ADC_ExternalTrigConv_T2_TRGO) || \ + ((CONV) == ADC_ExternalTrigConv_T3_TRGO) || \ + ((CONV) == ADC_ExternalTrigConv_T15_TRGO)) +/** + * @} + */ + +/** @defgroup ADC_data_align + * @{ + */ + +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ADC_CFGR1_ALIGN + +#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ + ((ALIGN) == ADC_DataAlign_Left)) +/** + * @} + */ + +/** @defgroup ADC_Scan_Direction + * @{ + */ + +#define ADC_ScanDirection_Upward ((uint32_t)0x00000000) +#define ADC_ScanDirection_Backward ADC_CFGR1_SCANDIR + +#define IS_ADC_SCAN_DIRECTION(DIRECTION) (((DIRECTION) == ADC_ScanDirection_Upward) || \ + ((DIRECTION) == ADC_ScanDirection_Backward)) +/** + * @} + */ + +/** @defgroup ADC_DMA_Mode + * @{ + */ + +#define ADC_DMAMode_OneShot ((uint32_t)0x00000000) +#define ADC_DMAMode_Circular ADC_CFGR1_DMACFG + +#define IS_ADC_DMA_MODE(MODE) (((MODE) == ADC_DMAMode_OneShot) || \ + ((MODE) == ADC_DMAMode_Circular)) +/** + * @} + */ + +/** @defgroup ADC_analog_watchdog_selection + * @{ + */ + +#define ADC_AnalogWatchdog_Channel_0 ((uint32_t)0x00000000) +#define ADC_AnalogWatchdog_Channel_1 ((uint32_t)0x04000000) +#define ADC_AnalogWatchdog_Channel_2 ((uint32_t)0x08000000) +#define ADC_AnalogWatchdog_Channel_3 ((uint32_t)0x0C000000) +#define ADC_AnalogWatchdog_Channel_4 ((uint32_t)0x10000000) +#define ADC_AnalogWatchdog_Channel_5 ((uint32_t)0x14000000) +#define ADC_AnalogWatchdog_Channel_6 ((uint32_t)0x18000000) +#define ADC_AnalogWatchdog_Channel_7 ((uint32_t)0x1C000000) +#define ADC_AnalogWatchdog_Channel_8 ((uint32_t)0x20000000) +#define ADC_AnalogWatchdog_Channel_9 ((uint32_t)0x24000000) +#define ADC_AnalogWatchdog_Channel_10 ((uint32_t)0x28000000) /*!< Not available for STM32F031 devices */ +#define ADC_AnalogWatchdog_Channel_11 ((uint32_t)0x2C000000) /*!< Not available for STM32F031 devices */ +#define ADC_AnalogWatchdog_Channel_12 ((uint32_t)0x30000000) /*!< Not available for STM32F031 devices */ +#define ADC_AnalogWatchdog_Channel_13 ((uint32_t)0x34000000) /*!< Not available for STM32F031 devices */ +#define ADC_AnalogWatchdog_Channel_14 ((uint32_t)0x38000000) /*!< Not available for STM32F031 devices */ +#define ADC_AnalogWatchdog_Channel_15 ((uint32_t)0x3C000000) /*!< Not available for STM32F031 devices */ +#define ADC_AnalogWatchdog_Channel_16 ((uint32_t)0x40000000) +#define ADC_AnalogWatchdog_Channel_17 ((uint32_t)0x44000000) +#define ADC_AnalogWatchdog_Channel_18 ((uint32_t)0x48000000) + + +#define IS_ADC_ANALOG_WATCHDOG_CHANNEL(CHANNEL) (((CHANNEL) == ADC_AnalogWatchdog_Channel_0) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_1) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_2) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_3) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_4) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_5) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_6) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_7) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_8) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_9) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_10) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_11) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_12) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_13) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_14) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_15) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_16) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_17) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_18)) +/** + * @} + */ + +/** @defgroup ADC_sampling_times + * @{ + */ + +#define ADC_SampleTime_1_5Cycles ((uint32_t)0x00000000) +#define ADC_SampleTime_7_5Cycles ((uint32_t)0x00000001) +#define ADC_SampleTime_13_5Cycles ((uint32_t)0x00000002) +#define ADC_SampleTime_28_5Cycles ((uint32_t)0x00000003) +#define ADC_SampleTime_41_5Cycles ((uint32_t)0x00000004) +#define ADC_SampleTime_55_5Cycles ((uint32_t)0x00000005) +#define ADC_SampleTime_71_5Cycles ((uint32_t)0x00000006) +#define ADC_SampleTime_239_5Cycles ((uint32_t)0x00000007) + +#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1_5Cycles) || \ + ((TIME) == ADC_SampleTime_7_5Cycles) || \ + ((TIME) == ADC_SampleTime_13_5Cycles) || \ + ((TIME) == ADC_SampleTime_28_5Cycles) || \ + ((TIME) == ADC_SampleTime_41_5Cycles) || \ + ((TIME) == ADC_SampleTime_55_5Cycles) || \ + ((TIME) == ADC_SampleTime_71_5Cycles) || \ + ((TIME) == ADC_SampleTime_239_5Cycles)) +/** + * @} + */ + +/** @defgroup ADC_thresholds + * @{ + */ + +#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) + +/** + * @} + */ + +/** @defgroup ADC_channels + * @{ + */ + +#define ADC_Channel_0 ADC_CHSELR_CHSEL0 +#define ADC_Channel_1 ADC_CHSELR_CHSEL1 +#define ADC_Channel_2 ADC_CHSELR_CHSEL2 +#define ADC_Channel_3 ADC_CHSELR_CHSEL3 +#define ADC_Channel_4 ADC_CHSELR_CHSEL4 +#define ADC_Channel_5 ADC_CHSELR_CHSEL5 +#define ADC_Channel_6 ADC_CHSELR_CHSEL6 +#define ADC_Channel_7 ADC_CHSELR_CHSEL7 +#define ADC_Channel_8 ADC_CHSELR_CHSEL8 +#define ADC_Channel_9 ADC_CHSELR_CHSEL9 +#define ADC_Channel_10 ADC_CHSELR_CHSEL10 /*!< Not available for STM32F031 devices */ +#define ADC_Channel_11 ADC_CHSELR_CHSEL11 /*!< Not available for STM32F031 devices */ +#define ADC_Channel_12 ADC_CHSELR_CHSEL12 /*!< Not available for STM32F031 devices */ +#define ADC_Channel_13 ADC_CHSELR_CHSEL13 /*!< Not available for STM32F031 devices */ +#define ADC_Channel_14 ADC_CHSELR_CHSEL14 /*!< Not available for STM32F031 devices */ +#define ADC_Channel_15 ADC_CHSELR_CHSEL15 /*!< Not available for STM32F031 devices */ +#define ADC_Channel_16 ADC_CHSELR_CHSEL16 +#define ADC_Channel_17 ADC_CHSELR_CHSEL17 +#define ADC_Channel_18 ADC_CHSELR_CHSEL18 /*!< Not available for STM32F030 devices */ + +#define ADC_Channel_TempSensor ((uint32_t)ADC_Channel_16) +#define ADC_Channel_Vrefint ((uint32_t)ADC_Channel_17) +#define ADC_Channel_Vbat ((uint32_t)ADC_Channel_18) /*!< Not available for STM32F030 devices */ + +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) != (uint32_t)RESET) && (((CHANNEL) & 0xFFF80000) == (uint32_t)RESET)) + +/** + * @} + */ + +/** @defgroup ADC_interrupts_definition + * @{ + */ + +#define ADC_IT_ADRDY ADC_IER_ADRDYIE +#define ADC_IT_EOSMP ADC_IER_EOSMPIE +#define ADC_IT_EOC ADC_IER_EOCIE +#define ADC_IT_EOSEQ ADC_IER_EOSEQIE +#define ADC_IT_OVR ADC_IER_OVRIE +#define ADC_IT_AWD ADC_IER_AWDIE + +#define IS_ADC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFF60) == (uint32_t)RESET)) + +#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_ADRDY) || ((IT) == ADC_IT_EOSMP) || \ + ((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_EOSEQ) || \ + ((IT) == ADC_IT_OVR) || ((IT) == ADC_IT_AWD)) + +#define IS_ADC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFF60) == (uint32_t)RESET)) + +/** + * @} + */ + +/** @defgroup ADC_flags_definition + * @{ + */ + +#define ADC_FLAG_ADRDY ADC_ISR_ADRDY +#define ADC_FLAG_EOSMP ADC_ISR_EOSMP +#define ADC_FLAG_EOC ADC_ISR_EOC +#define ADC_FLAG_EOSEQ ADC_ISR_EOSEQ +#define ADC_FLAG_OVR ADC_ISR_OVR +#define ADC_FLAG_AWD ADC_ISR_AWD + +#define ADC_FLAG_ADEN ((uint32_t)0x01000001) +#define ADC_FLAG_ADDIS ((uint32_t)0x01000002) +#define ADC_FLAG_ADSTART ((uint32_t)0x01000004) +#define ADC_FLAG_ADSTP ((uint32_t)0x01000010) +#define ADC_FLAG_ADCAL ((uint32_t)0x81000000) + +#define IS_ADC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFFFF60) == (uint32_t)RESET)) + +#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_ADRDY) || ((FLAG) == ADC_FLAG_EOSMP) || \ + ((FLAG) == ADC_FLAG_EOC) || ((FLAG) == ADC_FLAG_EOSEQ) || \ + ((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_OVR) || \ + ((FLAG) == ADC_FLAG_ADEN) || ((FLAG) == ADC_FLAG_ADDIS) || \ + ((FLAG) == ADC_FLAG_ADSTART) || ((FLAG) == ADC_FLAG_ADSTP) || \ + ((FLAG) == ADC_FLAG_ADCAL)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Function used to set the ADC configuration to the default reset state *****/ +void ADC_DeInit(ADC_TypeDef* ADCx); + +/* Initialization and Configuration functions *********************************/ +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); +void ADC_ClockModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ClockMode); +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); +/* This Function is obsolete and maintained for legacy purpose only. + ADC_ClockModeConfig() function should be used instead */ +void ADC_JitterCmd(ADC_TypeDef* ADCx, uint32_t ADC_JitterOff, FunctionalState NewState); + +/* Power saving functions *****************************************************/ +void ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); + +/* Analog Watchdog configuration functions ************************************/ +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog_Channel); +void ADC_AnalogWatchdogSingleChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState); + +/* Temperature Sensor , Vrefint and Vbat management function ******************/ +void ADC_TempSensorCmd(FunctionalState NewState); +void ADC_VrefintCmd(FunctionalState NewState); +void ADC_VbatCmd(FunctionalState NewState); /*!< Not applicable for STM32F030 devices */ + +/* Channels Configuration functions *******************************************/ +void ADC_ChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_Channel, uint32_t ADC_SampleTime); +void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_OverrunModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +uint32_t ADC_GetCalibrationFactor(ADC_TypeDef* ADCx); +void ADC_StopOfConversion(ADC_TypeDef* ADCx); +void ADC_StartOfConversion(ADC_TypeDef* ADCx); +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); + +/* Regular Channels DMA Configuration functions *******************************/ +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_DMARequestModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMARequestMode); + +/* Interrupts and flags management functions **********************************/ +void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F0XX_ADC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_can.h b/system/include/stm32f0-stdperiph/stm32f0xx_can.h new file mode 100644 index 0000000..7e4ca37 --- /dev/null +++ b/system/include/stm32f0-stdperiph/stm32f0xx_can.h @@ -0,0 +1,643 @@ +/** + ****************************************************************************** + * @file stm32f0xx_can.h + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file contains all the functions prototypes for the CAN firmware + * library, applicable only for STM32F072 devices. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_CAN_H +#define __STM32F0xx_CAN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CAN + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN)) + +/** + * @brief CAN init structure definition + */ +typedef struct +{ + uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. + It ranges from 1 to 1024. */ + + uint8_t CAN_Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of @ref CAN_operating_mode */ + + uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of @ref CAN_synchronisation_jump_width */ + + uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit + Segment 1. This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_1 */ + + uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ + + FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_NART; /*!< Enable or disable the non-automatic retransmission mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_InitTypeDef; + +/** + * @brief CAN filter init structure definition + */ +typedef struct +{ + uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ + + uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint8_t CAN_FilterScale; /*!< Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_FilterInitTypeDef; + +/** + * @brief CAN Tx message structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /*!< Specifies the type of identifier for the message that + will be transmitted. This parameter can be a value + of @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the message that will + be transmitted. This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be + transmitted. This parameter can be a value between + 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 + to 0xFF. */ +} CanTxMsg; + +/** + * @brief CAN Rx message structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /*!< Specifies the type of identifier for the message that + will be received. This parameter can be a value of + @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the received message. + This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be received. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to + 0xFF. */ + + uint8_t FMI; /*!< Specifies the index of the filter the message stored in + the mailbox passes through. This parameter can be a + value between 0 to 0xFF */ +} CanRxMsg; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CAN_Exported_Constants + * @{ + */ + +/** @defgroup CAN_InitStatus + * @{ + */ + +#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */ +#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */ + + +/* Legacy defines */ +#define CANINITFAILED CAN_InitStatus_Failed +#define CANINITOK CAN_InitStatus_Success +/** + * @} + */ + +/** @defgroup CAN_operating_mode + * @{ + */ + +#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */ +#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */ +#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */ +#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */ + +#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \ + ((MODE) == CAN_Mode_LoopBack)|| \ + ((MODE) == CAN_Mode_Silent) || \ + ((MODE) == CAN_Mode_Silent_LoopBack)) +/** + * @} + */ + + + /** + * @defgroup CAN_operating_mode + * @{ + */ +#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */ +#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */ +#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */ + + +#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\ + ((MODE) == CAN_OperatingMode_Normal)|| \ + ((MODE) == CAN_OperatingMode_Sleep)) +/** + * @} + */ + +/** + * @defgroup CAN_operating_mode_status + * @{ + */ + +#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */ +#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */ +/** + * @} + */ + +/** @defgroup CAN_synchronisation_jump_width + * @{ + */ +#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ + +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ + ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_1 + * @{ + */ +#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ +#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ +#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ +#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ +#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ +#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ +#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ +#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ +#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ + +#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq) +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_2 + * @{ + */ +#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ + +#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq) +/** + * @} + */ + +/** @defgroup CAN_clock_prescaler + * @{ + */ +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) +/** + * @} + */ + +/** @defgroup CAN_filter_number + * @{ + */ +#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) +/** + * @} + */ + +/** @defgroup CAN_filter_mode + * @{ + */ +#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */ +#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */ + +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ + ((MODE) == CAN_FilterMode_IdList)) +/** + * @} + */ + +/** @defgroup CAN_filter_scale + * @{ + */ +#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */ +#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */ + +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \ + ((SCALE) == CAN_FilterScale_32bit)) +/** + * @} + */ + +/** @defgroup CAN_filter_FIFO + * @{ + */ +#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ +#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ + ((FIFO) == CAN_FilterFIFO1)) + +/* Legacy defines */ +#define CAN_FilterFIFO0 CAN_Filter_FIFO0 +#define CAN_FilterFIFO1 CAN_Filter_FIFO1 +/** + * @} + */ + +/** @defgroup CAN_Start_bank_filter_for_slave_CAN + * @{ + */ +#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27)) +/** + * @} + */ + +/** @defgroup CAN_Tx + * @{ + */ +#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) +#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) +#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) +/** + * @} + */ + +/** @defgroup CAN_identifier_type + * @{ + */ +#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */ +#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */ +#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \ + ((IDTYPE) == CAN_Id_Extended)) + +/* Legacy defines */ +#define CAN_ID_STD CAN_Id_Standard +#define CAN_ID_EXT CAN_Id_Extended +/** + * @} + */ + +/** @defgroup CAN_remote_transmission_request + * @{ + */ +#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */ +#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */ +#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote)) + +/* Legacy defines */ +#define CAN_RTR_DATA CAN_RTR_Data +#define CAN_RTR_REMOTE CAN_RTR_Remote +/** + * @} + */ + +/** @defgroup CAN_transmit_constants + * @{ + */ +#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */ +#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */ +#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */ +#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide + an empty mailbox */ +/* Legacy defines */ +#define CANTXFAILED CAN_TxStatus_Failed +#define CANTXOK CAN_TxStatus_Ok +#define CANTXPENDING CAN_TxStatus_Pending +#define CAN_NO_MB CAN_TxStatus_NoMailBox +/** + * @} + */ + +/** @defgroup CAN_receive_FIFO_number_constants + * @{ + */ +#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ + +#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) +/** + * @} + */ + +/** @defgroup CAN_sleep_constants + * @{ + */ +#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ +#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */ + +/* Legacy defines */ +#define CANSLEEPFAILED CAN_Sleep_Failed +#define CANSLEEPOK CAN_Sleep_Ok +/** + * @} + */ + +/** @defgroup CAN_wake_up_constants + * @{ + */ +#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ +#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ + +/* Legacy defines */ +#define CANWAKEUPFAILED CAN_WakeUp_Failed +#define CANWAKEUPOK CAN_WakeUp_Ok +/** + * @} + */ + +/** + * @defgroup CAN_Error_Code_constants + * @{ + */ +#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */ +#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */ +#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */ +#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */ +#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ +#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */ +#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */ +#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */ +/** + * @} + */ + +/** @defgroup CAN_flags + * @{ + */ +/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() + and CAN_ClearFlag() functions. */ +/* If the flag is 0x1XXXXXXX, it means that it can only be used with + CAN_GetFlagStatus() function. */ + +/* Transmit Flags */ +#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */ +#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */ +#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */ + +/* Receive Flags */ +#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */ +#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */ +#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */ +#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */ +#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */ +#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */ +#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */ +/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. + In this case the SLAK bit can be polled.*/ + +/* Error Flags */ +#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */ +#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */ +#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */ +#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */ + +#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \ + ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \ + ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \ + ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \ + ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \ + ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \ + ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \ + ((FLAG) == CAN_FLAG_SLAK )) + +#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \ + ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \ + ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\ + ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \ + ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK)) +/** + * @} + */ + + +/** @defgroup CAN_interrupts + * @{ + */ +#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/ + +/* Receive Interrupts */ +#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/ +#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/ +#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/ +#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/ +#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/ +#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/ + +/* Operating Mode Interrupts */ +#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/ +#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/ + +/* Error Interrupts */ +#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/ +#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/ +#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/ +#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/ +#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/ + +/* Flags named as Interrupts : kept only for FW compatibility */ +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME + + +#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ + ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ + ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) + +#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ + ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the CAN configuration to the default reset state *****/ +void CAN_DeInit(CAN_TypeDef* CANx); + +/* Initialization and Configuration functions *********************************/ +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); +void CAN_SlaveStartBank(uint8_t CAN_BankNumber); +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); +void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState); + +/* CAN Frames Transmission functions ******************************************/ +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); +uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); +void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); + +/* CAN Frames Reception functions *********************************************/ +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); +void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); +uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); + +/* Operation modes functions **************************************************/ +uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode); +uint8_t CAN_Sleep(CAN_TypeDef* CANx); +uint8_t CAN_WakeUp(CAN_TypeDef* CANx); + +/* CAN Bus Error management functions *****************************************/ +uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx); +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx); +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx); + +/* Interrupts and flags management functions **********************************/ +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); +void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_CAN_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_cec.h b/system/include/stm32f0-stdperiph/stm32f0xx_cec.h new file mode 100644 index 0000000..f02fec0 --- /dev/null +++ b/system/include/stm32f0-stdperiph/stm32f0xx_cec.h @@ -0,0 +1,300 @@ +/** + ****************************************************************************** + * @file stm32f0xx_cec.h + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file contains all the functions prototypes for the CEC firmware + * library, applicable only for STM32F051, STM32F042 and STM32F072 devices. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_CEC_H +#define __STM32F0XX_CEC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CEC + * @{ + */ +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief CEC Init structure definition + */ +typedef struct +{ + uint32_t CEC_SignalFreeTime; /*!< Specifies the CEC Signal Free Time configuration. + This parameter can be a value of @ref CEC_Signal_Free_Time */ + uint32_t CEC_RxTolerance; /*!< Specifies the CEC Reception Tolerance. + This parameter can be a value of @ref CEC_RxTolerance */ + uint32_t CEC_StopReception; /*!< Specifies the CEC Stop Reception. + This parameter can be a value of @ref CEC_Stop_Reception */ + uint32_t CEC_BitRisingError; /*!< Specifies the CEC Bit Rising Error generation. + This parameter can be a value of @ref CEC_Bit_Rising_Error_Generation */ + uint32_t CEC_LongBitPeriodError; /*!< Specifies the CEC Long Bit Error generation. + This parameter can be a value of @ref CEC_Long_Bit_Error_Generation */ + uint32_t CEC_BRDNoGen; /*!< Specifies the CEC Broadcast Error generation. + This parameter can be a value of @ref CEC_BDR_No_Gen */ + uint32_t CEC_SFTOption; /*!< Specifies the CEC Signal Free Time option. + This parameter can be a value of @ref CEC_SFT_Option */ + +}CEC_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CEC_Exported_Constants + * @{ + */ + +/** @defgroup CEC_Signal_Free_Time + * @{ + */ +#define CEC_SignalFreeTime_Standard ((uint32_t)0x00000000) /*!< CEC Signal Free Time Standard */ +#define CEC_SignalFreeTime_1T ((uint32_t)0x00000001) /*!< CEC 1.5 nominal data bit periods */ +#define CEC_SignalFreeTime_2T ((uint32_t)0x00000002) /*!< CEC 2.5 nominal data bit periods */ +#define CEC_SignalFreeTime_3T ((uint32_t)0x00000003) /*!< CEC 3.5 nominal data bit periods */ +#define CEC_SignalFreeTime_4T ((uint32_t)0x00000004) /*!< CEC 4.5 nominal data bit periods */ +#define CEC_SignalFreeTime_5T ((uint32_t)0x00000005) /*!< CEC 5.5 nominal data bit periods */ +#define CEC_SignalFreeTime_6T ((uint32_t)0x00000006) /*!< CEC 6.5 nominal data bit periods */ +#define CEC_SignalFreeTime_7T ((uint32_t)0x00000007) /*!< CEC 7.5 nominal data bit periods */ + +#define IS_CEC_SIGNAL_FREE_TIME(TIME) (((TIME) == CEC_SignalFreeTime_Standard) || \ + ((TIME) == CEC_SignalFreeTime_1T)|| \ + ((TIME) == CEC_SignalFreeTime_2T)|| \ + ((TIME) == CEC_SignalFreeTime_3T)|| \ + ((TIME) == CEC_SignalFreeTime_4T)|| \ + ((TIME) == CEC_SignalFreeTime_5T)|| \ + ((TIME) == CEC_SignalFreeTime_6T)|| \ + ((TIME) == CEC_SignalFreeTime_7T)) +/** + * @} + */ + +/** @defgroup CEC_RxTolerance + * @{ + */ +#define CEC_RxTolerance_Standard ((uint32_t)0x00000000) /*!< Standard Tolerance Margin */ +#define CEC_RxTolerance_Extended CEC_CFGR_RXTOL /*!< Extended Tolerance Margin */ + +#define IS_CEC_RX_TOLERANCE(TOLERANCE) (((TOLERANCE) == CEC_RxTolerance_Standard) || \ + ((TOLERANCE) == CEC_RxTolerance_Extended)) +/** + * @} + */ + +/** @defgroup CEC_Stop_Reception + * @{ + */ +#define CEC_StopReception_Off ((uint32_t)0x00000000) /*!< No RX Stop on bit Rising Error (BRE) */ +#define CEC_StopReception_On CEC_CFGR_BRESTP /*!< RX Stop on bit Rising Error (BRE) */ + +#define IS_CEC_STOP_RECEPTION(RECEPTION) (((RECEPTION) == CEC_StopReception_On) || \ + ((RECEPTION) == CEC_StopReception_Off)) +/** + * @} + */ + +/** @defgroup CEC_Bit_Rising_Error_Generation + * @{ + */ +#define CEC_BitRisingError_Off ((uint32_t)0x00000000) /*!< Bit Rising Error generation turned Off */ +#define CEC_BitRisingError_On CEC_CFGR_BREGEN /*!< Bit Rising Error generation turned On */ + +#define IS_CEC_BIT_RISING_ERROR(ERROR) (((ERROR) == CEC_BitRisingError_Off) || \ + ((ERROR) == CEC_BitRisingError_On)) +/** + * @} + */ + +/** @defgroup CEC_Long_Bit_Error_Generation + * @{ + */ +#define CEC_LongBitPeriodError_Off ((uint32_t)0x00000000) /*!< Long Bit Period Error generation turned Off */ +#define CEC_LongBitPeriodError_On CEC_CFGR_LREGEN /*!< Long Bit Period Error generation turned On */ + +#define IS_CEC_LONG_BIT_PERIOD_ERROR(ERROR) (((ERROR) == CEC_LongBitPeriodError_Off) || \ + ((ERROR) == CEC_LongBitPeriodError_On)) +/** + * @} + */ + +/** @defgroup CEC_BDR_No_Gen + * @{ + */ + +#define CEC_BRDNoGen_Off ((uint32_t)0x00000000) /*!< Broadcast Bit Rising Error generation turned Off */ +#define CEC_BRDNoGen_On CEC_CFGR_BRDNOGEN /*!< Broadcast Bit Rising Error generation turned On */ + +#define IS_CEC_BDR_NO_GEN_ERROR(ERROR) (((ERROR) == CEC_BRDNoGen_Off) || \ + ((ERROR) == CEC_BRDNoGen_On)) +/** + * @} + */ + +/** @defgroup CEC_SFT_Option + * @{ + */ +#define CEC_SFTOption_Off ((uint32_t)0x00000000) /*!< SFT option turned Off */ +#define CEC_SFTOption_On CEC_CFGR_SFTOPT /*!< SFT option turned On */ + +#define IS_CEC_SFT_OPTION(OPTION) (((OPTION) == CEC_SFTOption_Off) || \ + ((OPTION) == CEC_SFTOption_On)) +/** + * @} + */ + +/** @defgroup CEC_Own_Address + * @{ + */ +#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10) + +/** + * @} + */ + +/** @defgroup CEC_Interrupt_Configuration_definition + * @{ + */ +#define CEC_IT_TXACKE CEC_IER_TXACKEIE +#define CEC_IT_TXERR CEC_IER_TXERRIE +#define CEC_IT_TXUDR CEC_IER_TXUDRIE +#define CEC_IT_TXEND CEC_IER_TXENDIE +#define CEC_IT_TXBR CEC_IER_TXBRIE +#define CEC_IT_ARBLST CEC_IER_ARBLSTIE +#define CEC_IT_RXACKE CEC_IER_RXACKEIE +#define CEC_IT_LBPE CEC_IER_LBPEIE +#define CEC_IT_SBPE CEC_IER_SBPEIE +#define CEC_IT_BRE CEC_IER_BREIEIE +#define CEC_IT_RXOVR CEC_IER_RXOVRIE +#define CEC_IT_RXEND CEC_IER_RXENDIE +#define CEC_IT_RXBR CEC_IER_RXBRIE + +#define IS_CEC_IT(IT) ((((IT) & (uint32_t)0xFFFFE000) == 0x00) && ((IT) != 0x00)) + +#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TXACKE) || \ + ((IT) == CEC_IT_TXERR)|| \ + ((IT) == CEC_IT_TXUDR)|| \ + ((IT) == CEC_IT_TXEND)|| \ + ((IT) == CEC_IT_TXBR)|| \ + ((IT) == CEC_IT_ARBLST)|| \ + ((IT) == CEC_IT_RXACKE)|| \ + ((IT) == CEC_IT_LBPE)|| \ + ((IT) == CEC_IT_SBPE)|| \ + ((IT) == CEC_IT_BRE)|| \ + ((IT) == CEC_IT_RXOVR)|| \ + ((IT) == CEC_IT_RXEND)|| \ + ((IT) == CEC_IT_RXBR)) +/** + * @} + */ + +/** @defgroup CEC_ISR_register_flags_definition + * @{ + */ +#define CEC_FLAG_TXACKE CEC_ISR_TXACKE +#define CEC_FLAG_TXERR CEC_ISR_TXERR +#define CEC_FLAG_TXUDR CEC_ISR_TXUDR +#define CEC_FLAG_TXEND CEC_ISR_TXEND +#define CEC_FLAG_TXBR CEC_ISR_TXBR +#define CEC_FLAG_ARBLST CEC_ISR_ARBLST +#define CEC_FLAG_RXACKE CEC_ISR_RXACKE +#define CEC_FLAG_LBPE CEC_ISR_LBPE +#define CEC_FLAG_SBPE CEC_ISR_SBPE +#define CEC_FLAG_BRE CEC_ISR_BRE +#define CEC_FLAG_RXOVR CEC_ISR_RXOVR +#define CEC_FLAG_RXEND CEC_ISR_RXEND +#define CEC_FLAG_RXBR CEC_ISR_RXBR + +#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFE000) == 0x00) && ((FLAG) != 0x00)) + +#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_TXACKE) || \ + ((FLAG) == CEC_FLAG_TXERR)|| \ + ((FLAG) == CEC_FLAG_TXUDR)|| \ + ((FLAG) == CEC_FLAG_TXEND)|| \ + ((FLAG) == CEC_FLAG_TXBR)|| \ + ((FLAG) == CEC_FLAG_ARBLST)|| \ + ((FLAG) == CEC_FLAG_RXACKE)|| \ + ((FLAG) == CEC_FLAG_LBPE)|| \ + ((FLAG) == CEC_FLAG_SBPE)|| \ + ((FLAG) == CEC_FLAG_BRE)|| \ + ((FLAG) == CEC_FLAG_RXOVR)|| \ + ((FLAG) == CEC_FLAG_RXEND)|| \ + ((FLAG) == CEC_FLAG_RXBR)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Function used to set the CEC configuration to the default reset state *****/ +void CEC_DeInit(void); + +/* CEC_Initialization and Configuration functions *****************************/ +void CEC_Init(CEC_InitTypeDef* CEC_InitStruct); +void CEC_StructInit(CEC_InitTypeDef* CEC_InitStruct); +void CEC_Cmd(FunctionalState NewState); +void CEC_ListenModeCmd(FunctionalState NewState); +void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress); +void CEC_OwnAddressClear(void); + +/* CEC_Data transfers functions ***********************************************/ +void CEC_SendData(uint8_t Data); +uint8_t CEC_ReceiveData(void); +void CEC_StartOfMessage(void); +void CEC_EndOfMessage(void); + +/* CEC_Interrupts and flags management functions ******************************/ +void CEC_ITConfig(uint16_t CEC_IT, FunctionalState NewState); +FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG); +void CEC_ClearFlag(uint32_t CEC_FLAG); +ITStatus CEC_GetITStatus(uint16_t CEC_IT); +void CEC_ClearITPendingBit(uint16_t CEC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0XX_CEC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_comp.h b/system/include/stm32f0-stdperiph/stm32f0xx_comp.h new file mode 100644 index 0000000..6854d55 --- /dev/null +++ b/system/include/stm32f0-stdperiph/stm32f0xx_comp.h @@ -0,0 +1,245 @@ +/** + ****************************************************************************** + * @file stm32f0xx_comp.h + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file contains all the functions prototypes for the COMP firmware + * library, applicable only for STM32F051 and STM32F072 devices. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_COMP_H +#define __STM32F0XX_COMP_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup COMP + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief COMP Init structure definition + */ + +typedef struct +{ + + uint32_t COMP_InvertingInput; /*!< Selects the inverting input of the comparator. + This parameter can be a value of @ref COMP_InvertingInput */ + + uint32_t COMP_Output; /*!< Selects the output redirection of the comparator. + This parameter can be a value of @ref COMP_Output */ + + uint32_t COMP_OutputPol; /*!< Selects the output polarity of the comparator. + This parameter can be a value of @ref COMP_OutputPolarity */ + + uint32_t COMP_Hysteresis; /*!< Selects the hysteresis voltage of the comparator. + This parameter can be a value of @ref COMP_Hysteresis */ + + uint32_t COMP_Mode; /*!< Selects the operating mode of the comparator + and allows to adjust the speed/consumption. + This parameter can be a value of @ref COMP_Mode */ + +}COMP_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup COMP_Exported_Constants + * @{ + */ + +/** @defgroup COMP_Selection + * @{ + */ + +#define COMP_Selection_COMP1 ((uint32_t)0x00000000) /*!< COMP1 Selection */ +#define COMP_Selection_COMP2 ((uint32_t)0x00000010) /*!< COMP2 Selection */ + +#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \ + ((PERIPH) == COMP_Selection_COMP2)) + +/** + * @} + */ + +/** @defgroup COMP_InvertingInput + * @{ + */ + +#define COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */ +#define COMP_InvertingInput_1_2VREFINT COMP_CSR_COMP1INSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */ +#define COMP_InvertingInput_3_4VREFINT COMP_CSR_COMP1INSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */ +#define COMP_InvertingInput_VREFINT ((uint32_t)0x00000030) /*!< VREFINT connected to comparator inverting input */ +#define COMP_InvertingInput_DAC1 COMP_CSR_COMP1INSEL_2 /*!< DAC1_OUT (PA4) connected to comparator inverting input */ +#define COMP_InvertingInput_DAC2 ((uint32_t)0x00000050) /*!< DAC2_OUT (PA5) connected to comparator inverting input, applicable only for STM32F072 devices */ +#define COMP_InvertingInput_IO ((uint32_t)0x00000060) /*!< I/O (PA0 for COMP1 and PA2 for COMP2) connected to comparator inverting input */ + +#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_1_4VREFINT) || \ + ((INPUT) == COMP_InvertingInput_1_2VREFINT) || \ + ((INPUT) == COMP_InvertingInput_3_4VREFINT) || \ + ((INPUT) == COMP_InvertingInput_VREFINT) || \ + ((INPUT) == COMP_InvertingInput_DAC1) || \ + ((INPUT) == COMP_InvertingInput_DAC2) || \ + ((INPUT) == COMP_InvertingInput_1_4VREFINT) || \ + ((INPUT) == COMP_InvertingInput_IO)) +/** + * @} + */ + +/** @defgroup COMP_Output + * @{ + */ + +#define COMP_Output_None ((uint32_t)0x00000000) /*!< COMP output isn't connected to other peripherals */ +#define COMP_Output_TIM1BKIN COMP_CSR_COMP1OUTSEL_0 /*!< COMP output connected to TIM1 Break Input (BKIN) */ +#define COMP_Output_TIM1IC1 COMP_CSR_COMP1OUTSEL_1 /*!< COMP output connected to TIM1 Input Capture 1 */ +#define COMP_Output_TIM1OCREFCLR ((uint32_t)0x00000300) /*!< COMP output connected to TIM1 OCREF Clear */ +#define COMP_Output_TIM2IC4 COMP_CSR_COMP1OUTSEL_2 /*!< COMP output connected to TIM2 Input Capture 4 */ +#define COMP_Output_TIM2OCREFCLR ((uint32_t)0x00000500) /*!< COMP output connected to TIM2 OCREF Clear */ +#define COMP_Output_TIM3IC1 ((uint32_t)0x00000600) /*!< COMP output connected to TIM3 Input Capture 1 */ +#define COMP_Output_TIM3OCREFCLR COMP_CSR_COMP1OUTSEL /*!< COMP output connected to TIM3 OCREF Clear */ + + +#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_Output_None) || \ + ((OUTPUT) == COMP_Output_TIM1BKIN) || \ + ((OUTPUT) == COMP_Output_TIM1IC1) || \ + ((OUTPUT) == COMP_Output_TIM1OCREFCLR) || \ + ((OUTPUT) == COMP_Output_TIM2IC4) || \ + ((OUTPUT) == COMP_Output_TIM2OCREFCLR) || \ + ((OUTPUT) == COMP_Output_TIM3IC1) || \ + ((OUTPUT) == COMP_Output_TIM3OCREFCLR)) +/** + * @} + */ + +/** @defgroup COMP_OutputPolarity + * @{ + */ +#define COMP_OutputPol_NonInverted ((uint32_t)0x00000000) /*!< COMP output on GPIO isn't inverted */ +#define COMP_OutputPol_Inverted COMP_CSR_COMP1POL /*!< COMP output on GPIO is inverted */ + +#define IS_COMP_OUTPUT_POL(POL) (((POL) == COMP_OutputPol_NonInverted) || \ + ((POL) == COMP_OutputPol_Inverted)) + +/** + * @} + */ + +/** @defgroup COMP_Hysteresis + * @{ + */ +/* Please refer to the electrical characteristics in the device datasheet for + the hysteresis level */ +#define COMP_Hysteresis_No 0x00000000 /*!< No hysteresis */ +#define COMP_Hysteresis_Low COMP_CSR_COMP1HYST_0 /*!< Hysteresis level low */ +#define COMP_Hysteresis_Medium COMP_CSR_COMP1HYST_1 /*!< Hysteresis level medium */ +#define COMP_Hysteresis_High COMP_CSR_COMP1HYST /*!< Hysteresis level high */ + +#define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_Hysteresis_No) || \ + ((HYSTERESIS) == COMP_Hysteresis_Low) || \ + ((HYSTERESIS) == COMP_Hysteresis_Medium) || \ + ((HYSTERESIS) == COMP_Hysteresis_High)) +/** + * @} + */ + +/** @defgroup COMP_Mode + * @{ + */ +/* Please refer to the electrical characteristics in the device datasheet for + the power consumption values */ +#define COMP_Mode_HighSpeed 0x00000000 /*!< High Speed */ +#define COMP_Mode_MediumSpeed COMP_CSR_COMP1MODE_0 /*!< Medium Speed */ +#define COMP_Mode_LowPower COMP_CSR_COMP1MODE_1 /*!< Low power mode */ +#define COMP_Mode_UltraLowPower COMP_CSR_COMP1MODE /*!< Ultra-low power mode */ + +#define IS_COMP_MODE(MODE) (((MODE) == COMP_Mode_UltraLowPower) || \ + ((MODE) == COMP_Mode_LowPower) || \ + ((MODE) == COMP_Mode_MediumSpeed) || \ + ((MODE) == COMP_Mode_HighSpeed)) +/** + * @} + */ + +/** @defgroup COMP_OutputLevel + * @{ + */ +/* When output polarity is not inverted, comparator output is high when + the non-inverting input is at a higher voltage than the inverting input */ +#define COMP_OutputLevel_High COMP_CSR_COMP1OUT +/* When output polarity is not inverted, comparator output is low when + the non-inverting input is at a lower voltage than the inverting input*/ +#define COMP_OutputLevel_Low ((uint32_t)0x00000000) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Function used to set the COMP configuration to the default reset state ****/ +void COMP_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct); +void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct); +void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState); +void COMP_SwitchCmd(FunctionalState NewState); +uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection); + +/* Window mode control function ***********************************************/ +void COMP_WindowCmd(FunctionalState NewState); + +/* COMP configuration locking function ****************************************/ +void COMP_LockConfig(uint32_t COMP_Selection); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F0XX_COMP_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_crc.h b/system/include/stm32f0-stdperiph/stm32f0xx_crc.h new file mode 100644 index 0000000..3b235e6 --- /dev/null +++ b/system/include/stm32f0-stdperiph/stm32f0xx_crc.h @@ -0,0 +1,122 @@ +/** + ****************************************************************************** + * @file stm32f0xx_crc.h + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file contains all the functions prototypes for the CRC firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_CRC_H +#define __STM32F0XX_CRC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/*!< Includes ----------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CRC_ReverseInputData + * @{ + */ +#define CRC_ReverseInputData_No ((uint32_t)0x00000000) /*!< No reverse operation of Input Data */ +#define CRC_ReverseInputData_8bits CRC_CR_REV_IN_0 /*!< Reverse operation of Input Data on 8 bits */ +#define CRC_ReverseInputData_16bits CRC_CR_REV_IN_1 /*!< Reverse operation of Input Data on 16 bits */ +#define CRC_ReverseInputData_32bits CRC_CR_REV_IN /*!< Reverse operation of Input Data on 32 bits */ + +#define IS_CRC_REVERSE_INPUT_DATA(DATA) (((DATA) == CRC_ReverseInputData_No) || \ + ((DATA) == CRC_ReverseInputData_8bits) || \ + ((DATA) == CRC_ReverseInputData_16bits) || \ + ((DATA) == CRC_ReverseInputData_32bits)) + +/** + * @} + */ + +/** @defgroup CRC_PolynomialSize + * @brief Only applicable for STM32F042 and STM32F072 devices + * @{ + */ +#define CRC_PolSize_7 CRC_CR_POLSIZE /*!< 7-bit polynomial for CRC calculation */ +#define CRC_PolSize_8 CRC_CR_POLSIZE_1 /*!< 8-bit polynomial for CRC calculation */ +#define CRC_PolSize_16 CRC_CR_POLSIZE_0 /*!< 16-bit polynomial for CRC calculation */ +#define CRC_PolSize_32 ((uint32_t)0x00000000)/*!< 32-bit polynomial for CRC calculation */ + +#define IS_CRC_POL_SIZE(SIZE) (((SIZE) == CRC_PolSize_7) || \ + ((SIZE) == CRC_PolSize_8) || \ + ((SIZE) == CRC_PolSize_16) || \ + ((SIZE) == CRC_PolSize_32)) + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +/* Configuration of the CRC computation unit **********************************/ +void CRC_DeInit(void); +void CRC_ResetDR(void); +void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize); /*!< Only applicable for STM32F042 and STM32F072 devices */ +void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData); +void CRC_ReverseOutputDataCmd(FunctionalState NewState); +void CRC_SetInitRegister(uint32_t CRC_InitValue); +void CRC_SetPolynomial(uint32_t CRC_Pol); /*!< Only applicable for STM32F042 and STM32F072 devices */ + +/* CRC computation ************************************************************/ +uint32_t CRC_CalcCRC(uint32_t CRC_Data); +uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data); /*!< Only applicable for STM32F042 and STM32F072 devices */ +uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data); /*!< Only applicable for STM32F042 and STM32F072 devices */ +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); +uint32_t CRC_GetCRC(void); + +/* Independent register (IDR) access (write/read) *****************************/ +void CRC_SetIDRegister(uint8_t CRC_IDValue); +uint8_t CRC_GetIDRegister(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0XX_CRC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_crs.h b/system/include/stm32f0-stdperiph/stm32f0xx_crs.h new file mode 100644 index 0000000..d47e865 --- /dev/null +++ b/system/include/stm32f0-stdperiph/stm32f0xx_crs.h @@ -0,0 +1,183 @@ +/** + ****************************************************************************** + * @file stm32f0xx_crs.h + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file contains all the functions prototypes for the CRS firmware + * library, applicable only for STM32F042 and STM32F072 devices. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_CRS_H +#define __STM32F0XX_CRS_H + +#ifdef __cplusplus + extern "C" { +#endif + +/*!< Includes ----------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CRS + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CRS_Interrupt_Sources + * @{ + */ +#define CRS_IT_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */ +#define CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */ +#define CRS_IT_ERR CRS_ISR_ERRF /*!< error */ +#define CRS_IT_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */ +#define CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ +#define CRS_IT_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ +#define CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ + +#define IS_CRS_IT(IT) (((IT) == CRS_IT_SYNCOK) || ((IT) == CRS_IT_SYNCWARN) || \ + ((IT) == CRS_IT_ERR) || ((IT) == CRS_IT_ESYNC)) + +#define IS_CRS_GET_IT(IT) (((IT) == CRS_IT_SYNCOK) || ((IT) == CRS_IT_SYNCWARN) || \ + ((IT) == CRS_IT_ERR) || ((IT) == CRS_IT_ESYNC) || \ + ((IT) == CRS_IT_TRIMOVF) || ((IT) == CRS_IT_SYNCERR) || \ + ((IT) == CRS_IT_SYNCMISS)) + +#define IS_CRS_CLEAR_IT(IT) ((IT) != 0x00) + +/** + * @} + */ + +/** @defgroup CRS_Flags + * @{ + */ +#define CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */ +#define CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */ +#define CRS_FLAG_ERR CRS_ISR_ERRF /*!< error */ +#define CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */ +#define CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ +#define CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ +#define CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ + +#define IS_CRS_FLAG(FLAG) (((FLAG) == CRS_FLAG_SYNCOK) || ((FLAG) == CRS_FLAG_SYNCWARN) || \ + ((FLAG) == CRS_FLAG_ERR) || ((FLAG) == CRS_FLAG_ESYNC) || \ + ((FLAG) == CRS_FLAG_TRIMOVF) || ((FLAG) == CRS_FLAG_SYNCERR) || \ + ((FLAG) == CRS_FLAG_SYNCMISS)) + +/** + * @} + */ + +/** @defgroup CRS_Synchro_Source + * @{ + */ +#define CRS_SYNCSource_GPIO ((uint32_t)0x00) /*!< Synchro Signal soucre GPIO */ +#define CRS_SYNCSource_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ +#define CRS_SYNCSource_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF */ + +#define IS_CRS_SYNC_SOURCE(SOURCE) (((SOURCE) == CRS_SYNCSource_GPIO) || \ + ((SOURCE) == CRS_SYNCSource_LSE) ||\ + ((SOURCE) == CRS_SYNCSource_USB)) +/** + * @} + */ + +/** @defgroup CRS_SynchroDivider + * @{ + */ +#define CRS_SYNC_Div1 ((uint32_t)0x00) /*!< Synchro Signal not divided */ +#define CRS_SYNC_Div2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ +#define CRS_SYNC_Div4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ +#define CRS_SYNC_Div8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ +#define CRS_SYNC_Div16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ +#define CRS_SYNC_Div32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ +#define CRS_SYNC_Div64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ +#define CRS_SYNC_Div128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ + +#define IS_CRS_SYNC_DIV(DIV) (((DIV) == CRS_SYNC_Div1) || ((DIV) == CRS_SYNC_Div2) ||\ + ((DIV) == CRS_SYNC_Div4) || ((DIV) == CRS_SYNC_Div8) || \ + ((DIV) == CRS_SYNC_Div16) || ((DIV) == CRS_SYNC_Div32) || \ + ((DIV) == CRS_SYNC_Div64) || ((DIV) == CRS_SYNC_Div128)) +/** + * @} + */ + +/** @defgroup CRS_SynchroPolarity + * @{ + */ +#define CRS_SYNCPolarity_Rising ((uint32_t)0x00) /*!< Synchro Active on rising edge */ +#define CRS_SYNCPolarity_Falling CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ + +#define IS_CRS_SYNC_POLARITY(POLARITY) (((POLARITY) == CRS_SYNCPolarity_Rising) || \ + ((POLARITY) == CRS_SYNCPolarity_Falling)) +/** + * @} + */ + + + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +/* Configuration of the CRS **********************************/ +void CRS_DeInit(void); +void CRS_AdjustHSI48CalibrationValue(uint8_t CRS_HSI48CalibrationValue); +void CRS_FrequencyErrorCounterCmd(FunctionalState NewState); +void CRS_AutomaticCalibrationCmd(FunctionalState NewState); +void CRS_SoftwareSynchronizationGenerate(void); +void CRS_FrequencyErrorCounterReload(uint32_t CRS_ReloadValue); +void CRS_FrequencyErrorLimitConfig(uint8_t CRS_ErrorLimitValue); +void CRS_SynchronizationPrescalerConfig(uint32_t CRS_Prescaler); +void CRS_SynchronizationSourceConfig(uint32_t CRS_Source); +void CRS_SynchronizationPolarityConfig(uint32_t CRS_Polarity); +uint32_t CRS_GetReloadValue(void); +uint32_t CRS_GetHSI48CalibrationValue(void); +uint32_t CRS_GetFrequencyErrorValue(void); +uint32_t CRS_GetFrequencyErrorDirection(void); + +/* Interrupts and flags management functions **********************************/ +void CRS_ITConfig(uint32_t CRS_IT, FunctionalState NewState); +FlagStatus CRS_GetFlagStatus(uint32_t CRS_FLAG); +void CRS_ClearFlag(uint32_t CRS_FLAG); +ITStatus CRS_GetITStatus(uint32_t CRS_IT); +void CRS_ClearITPendingBit(uint32_t CRS_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0XX_CRS_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_dac.h b/system/include/stm32f0-stdperiph/stm32f0xx_dac.h new file mode 100644 index 0000000..30ec216 --- /dev/null +++ b/system/include/stm32f0-stdperiph/stm32f0xx_dac.h @@ -0,0 +1,312 @@ +/** + ****************************************************************************** + * @file stm32f0xx_dac.h + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file contains all the functions prototypes for the DAC firmware + * library, applicable only for STM32F051 and STM32F072 devices. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_DAC_H +#define __STM32F0XX_DAC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief DAC Init structure definition + */ + +typedef struct +{ + uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. + This parameter can be a value of @ref DAC_trigger_selection */ + + uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves + are generated, or whether no wave is generated. + This parameter can be a value of @ref DAC_wave_generation + This parameter is only applicable for STM32F072 devices */ + + uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or + the maximum amplitude triangle generation for the DAC channel. + This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude + This parameter is only applicable for STM32F072 devices */ + + uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. + This parameter can be a value of @ref DAC_output_buffer */ +}DAC_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DAC_Exported_Constants + * @{ + */ + +/** @defgroup DAC_Trigger + * @{ + */ + +#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel1 */ +#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel1 */ +#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel1, + applicable only for STM32F072 devices */ +#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel1 */ +#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel1 */ +#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channels */ +#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channels */ + +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ + ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T3_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T15_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ + ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ + ((TRIGGER) == DAC_Trigger_Software)) + +/** + * @} + */ + +/** @defgroup DAC_wave_generation + * @brief This parameters are only applicable for STM32F072 devices. + * @{ + */ + +#define DAC_WaveGeneration_None ((uint32_t)0x00000000) +#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) +#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) +#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ + ((WAVE) == DAC_WaveGeneration_Noise) || \ + ((WAVE) == DAC_WaveGeneration_Triangle)) +/** + * @} + */ + +/** @defgroup DAC_lfsrunmask_triangleamplitude + * @brief These parameters are only applicable for STM32F072 devices. + * @{ + */ + +#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ +#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ +#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ +#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ +#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ +#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ +#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ +#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ +#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ +#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ +#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ +#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ + +#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ + ((VALUE) == DAC_TriangleAmplitude_1) || \ + ((VALUE) == DAC_TriangleAmplitude_3) || \ + ((VALUE) == DAC_TriangleAmplitude_7) || \ + ((VALUE) == DAC_TriangleAmplitude_15) || \ + ((VALUE) == DAC_TriangleAmplitude_31) || \ + ((VALUE) == DAC_TriangleAmplitude_63) || \ + ((VALUE) == DAC_TriangleAmplitude_127) || \ + ((VALUE) == DAC_TriangleAmplitude_255) || \ + ((VALUE) == DAC_TriangleAmplitude_511) || \ + ((VALUE) == DAC_TriangleAmplitude_1023) || \ + ((VALUE) == DAC_TriangleAmplitude_2047) || \ + ((VALUE) == DAC_TriangleAmplitude_4095)) +/** + * @} + */ + +/** @defgroup DAC_OutputBuffer + * @{ + */ + +#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) +#define DAC_OutputBuffer_Disable DAC_CR_BOFF1 +#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ + ((STATE) == DAC_OutputBuffer_Disable)) +/** + * @} + */ + +/** @defgroup DAC_Channel_selection + * @{ + */ + +#define DAC_Channel_1 ((uint32_t)0x00000000) +#define DAC_Channel_2 ((uint32_t)0x00000010) /*!< Only applicable for STM32F072 devices */ +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ + ((CHANNEL) == DAC_Channel_2)) + +/** + * @} + */ + +/** @defgroup DAC_data_alignment + * @{ + */ + +#define DAC_Align_12b_R ((uint32_t)0x00000000) +#define DAC_Align_12b_L ((uint32_t)0x00000004) +#define DAC_Align_8b_R ((uint32_t)0x00000008) +#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ + ((ALIGN) == DAC_Align_12b_L) || \ + ((ALIGN) == DAC_Align_8b_R)) +/** + * @} + */ + +/** @defgroup DAC_wave_generation + * @brief These parameters are only applicable for STM32F072 devices. + * @{ + */ + +#define DAC_Wave_Noise ((uint32_t)0x00000040) +#define DAC_Wave_Triangle ((uint32_t)0x00000080) +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ + ((WAVE) == DAC_Wave_Triangle)) +/** + * @} + */ + +/** @defgroup DAC_data + * @{ + */ + +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) + +/** + * @} + */ + +/** @defgroup DAC_interrupts_definition + * @{ + */ + +#define DAC_IT_DMAUDR DAC_SR_DMAUDR1 +#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) + +/** + * @} + */ + + +/** @defgroup DAC_flags_definition + * @{ + */ + +#define DAC_FLAG_DMAUDR DAC_SR_DMAUDR1 + +#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Function used to set the DAC configuration to the default reset state *****/ +void DAC_DeInit(void); + +/* DAC channels configuration: trigger, output buffer, data format functions */ +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); /*!< Only applicable for STM32F072 devices */ +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); /*!< Only applicable for STM32F072 devices */ +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); /*!< Only applicable for STM32F072 devices */ +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); /*!< Only applicable for STM32F072 devices */ +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); + +/* DMA management functions ***************************************************/ +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); +FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); +void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); +ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); +void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F0XX_DAC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h b/system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h new file mode 100644 index 0000000..6efeac8 --- /dev/null +++ b/system/include/stm32f0-stdperiph/stm32f0xx_dbgmcu.h @@ -0,0 +1,107 @@ +/** + ****************************************************************************** + * @file stm32f0xx_dbgmcu.h + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file contains all the functions prototypes for the DBGMCU firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_DBGMCU_H +#define __STM32F0XX_DBGMCU_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DBGMCU + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + + +/** @defgroup DBGMCU_Exported_Constants + * @{ + */ + +#define DBGMCU_STOP DBGMCU_CR_DBG_STOP +#define DBGMCU_STANDBY DBGMCU_CR_DBG_STANDBY +#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF9) == 0x00) && ((PERIPH) != 0x00)) + +#define DBGMCU_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< Not applicable for STM32F030 devices */ +#define DBGMCU_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP +#define DBGMCU_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP +#define DBGMCU_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< Only applicable for STM32F072 devices */ +#define DBGMCU_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP +#define DBGMCU_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP +#define DBGMCU_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP +#define DBGMCU_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP +#define DBGMCU_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT +#define DBGMCU_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP /*!< Only applicable for STM32F042 and STM32F072 devices */ +#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFDDFE2CC) == 0x00) && ((PERIPH) != 0x00)) + +#define DBGMCU_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP +#define DBGMCU_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP +#define DBGMCU_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP +#define DBGMCU_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP +#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8F7FF) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Device and Revision ID management functions ********************************/ +uint32_t DBGMCU_GetREVID(void); +uint32_t DBGMCU_GetDEVID(void); + +/* Peripherals Configuration functions ****************************************/ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); +void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); +void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0XX_DBGMCU_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_dma.h b/system/include/stm32f0-stdperiph/stm32f0xx_dma.h new file mode 100644 index 0000000..08c93ea --- /dev/null +++ b/system/include/stm32f0-stdperiph/stm32f0xx_dma.h @@ -0,0 +1,804 @@ +/** + ****************************************************************************** + * @file stm32f0xx_dma.h + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file contains all the functions prototypes for the DMA firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_DMA_H +#define __STM32F0XX_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief DMA Init structures definition + */ +typedef struct +{ + uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ + + uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */ + + uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. + The data unit is equal to the configuration set in DMA_PeripheralDataSize + or DMA_MemoryDataSize members depending in the transfer direction */ + + uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_circular_normal_mode + @note: The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. + This parameter can be a value of @ref DMA_memory_to_memory */ +}DMA_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants + * @{ + */ + +#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \ + ((PERIPH) == DMA1_Channel2) || \ + ((PERIPH) == DMA1_Channel3) || \ + ((PERIPH) == DMA1_Channel4) || \ + ((PERIPH) == DMA1_Channel5) || \ + ((PERIPH) == DMA1_Channel6) || \ + ((PERIPH) == DMA1_Channel7) || \ + ((PERIPH) == DMA2_Channel1) || \ + ((PERIPH) == DMA2_Channel2) || \ + ((PERIPH) == DMA2_Channel3) || \ + ((PERIPH) == DMA2_Channel4) || \ + ((PERIPH) == DMA2_Channel5)) + +/** @defgroup DMA_data_transfer_direction + * @{ + */ + +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) +#define DMA_DIR_PeripheralDST DMA_CCR_DIR + +#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \ + ((DIR) == DMA_DIR_PeripheralDST)) +/** + * @} + */ + +/** @defgroup DMA_peripheral_incremented_mode + * @{ + */ + +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) +#define DMA_PeripheralInc_Enable DMA_CCR_PINC + +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \ + ((STATE) == DMA_PeripheralInc_Enable)) +/** + * @} + */ + +/** @defgroup DMA_memory_incremented_mode + * @{ + */ + +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) +#define DMA_MemoryInc_Enable DMA_CCR_MINC + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \ + ((STATE) == DMA_MemoryInc_Enable)) +/** + * @} + */ + +/** @defgroup DMA_peripheral_data_size + * @{ + */ + +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord DMA_CCR_PSIZE_0 +#define DMA_PeripheralDataSize_Word DMA_CCR_PSIZE_1 + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ + ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ + ((SIZE) == DMA_PeripheralDataSize_Word)) +/** + * @} + */ + +/** @defgroup DMA_memory_data_size + * @{ + */ + +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord DMA_CCR_MSIZE_0 +#define DMA_MemoryDataSize_Word DMA_CCR_MSIZE_1 + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ + ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ + ((SIZE) == DMA_MemoryDataSize_Word)) +/** + * @} + */ + +/** @defgroup DMA_circular_normal_mode + * @{ + */ + +#define DMA_Mode_Normal ((uint32_t)0x00000000) +#define DMA_Mode_Circular DMA_CCR_CIRC + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular)) +/** + * @} + */ + +/** @defgroup DMA_priority_level + * @{ + */ + +#define DMA_Priority_VeryHigh DMA_CCR_PL +#define DMA_Priority_High DMA_CCR_PL_1 +#define DMA_Priority_Medium DMA_CCR_PL_0 +#define DMA_Priority_Low ((uint32_t)0x00000000) + +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ + ((PRIORITY) == DMA_Priority_High) || \ + ((PRIORITY) == DMA_Priority_Medium) || \ + ((PRIORITY) == DMA_Priority_Low)) +/** + * @} + */ + +/** @defgroup DMA_memory_to_memory + * @{ + */ + +#define DMA_M2M_Disable ((uint32_t)0x00000000) +#define DMA_M2M_Enable DMA_CCR_MEM2MEM + +#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable)) + +/** + * @} + */ + +/** @defgroup DMA_Remap_Config + * @{ + */ +#define DMAx_CHANNEL1_RMP 0x00000000 +#define DMAx_CHANNEL2_RMP 0x10000000 +#define DMAx_CHANNEL3_RMP 0x20000000 +#define DMAx_CHANNEL4_RMP 0x30000000 +#define DMAx_CHANNEL5_RMP 0x40000000 +#define DMAx_CHANNEL6_RMP 0x50000000 +#define DMAx_CHANNEL7_RMP 0x60000000 + + +#define IS_DMA_ALL_LIST(LIST) (((LIST) == DMA1) || \ + ((LIST) == DMA2)) + +/****************** DMA1 remap bit field definition********************/ +/* DMA1 - Channel 1 */ +#define DMA1_CH1_DEFAULT (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ +#define DMA1_CH1_ADC (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_ADC) /*!< Remap ADC on DMA1 Channel 1*/ +#define DMA1_CH1_TIM17_CH1 (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */ +#define DMA1_CH1_TIM17_UP (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 1 */ +#define DMA1_CH1_USART1_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 1 */ +#define DMA1_CH1_USART2_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 1 */ +#define DMA1_CH1_USART3_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 1 */ +#define DMA1_CH1_USART4_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 1 */ +#define DMA1_CH1_USART5_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 1 */ +#define DMA1_CH1_USART6_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 1 */ +#define DMA1_CH1_USART7_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 1 */ +#define DMA1_CH1_USART8_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 1 */ +/* DMA1 - Channel 2 */ +#define DMA1_CH2_DEFAULT (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ +#define DMA1_CH2_ADC (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_ADC) /*!< Remap ADC on DMA1 channel 2 */ +#define DMA1_CH2_I2C1_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 2 */ +#define DMA1_CH2_SPI1_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_SPI_1RX) /*!< Remap SPI1 Rx on DMA1 channel 2 */ +#define DMA1_CH2_TIM1_CH1 (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */ +#define DMA1_CH2_TIM17_CH1 (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */ +#define DMA1_CH2_TIM17_UP (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 2 */ +#define DMA1_CH2_USART1_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 2 */ +#define DMA1_CH2_USART2_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 2 */ +#define DMA1_CH2_USART3_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 2 */ +#define DMA1_CH2_USART4_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 2 */ +#define DMA1_CH2_USART5_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 2 */ +#define DMA1_CH2_USART6_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 2 */ +#define DMA1_CH2_USART7_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 2 */ +#define DMA1_CH2_USART8_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 2 */ +/* DMA1 - Channel 3 */ +#define DMA1_CH3_DEFAULT (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMAx */ +#define DMA1_CH3_TIM6_UP (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA1 channel 3 */ +#define DMA1_CH3_DAC_CH1 (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_DAC_CH1) /*!< Remap DAC Channel 1on DMA1 channel 3 */ +#define DMA1_CH3_I2C1_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 3 */ +#define DMA1_CH3_SPI1_TX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_SPI1_TX) /*!< Remap SPI1 Tx on DMA1 channel 3 */ +#define DMA1_CH3_TIM1_CH2 (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */ +#define DMA1_CH3_TIM2_CH2 (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */ +#define DMA1_CH3_TIM16_CH1 (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */ +#define DMA1_CH3_TIM16_UP (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 3 */ +#define DMA1_CH3_USART1_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 3 */ +#define DMA1_CH3_USART2_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 3 */ +#define DMA1_CH3_USART3_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 3 */ +#define DMA1_CH3_USART4_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 3 */ +#define DMA1_CH3_USART5_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 3 */ +#define DMA1_CH3_USART6_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 3 */ +#define DMA1_CH3_USART7_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 3 */ +#define DMA1_CH3_USART8_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 3 */ +/* DMA1 - Channel 4 */ +#define DMA1_CH4_DEFAULT (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ +#define DMA1_CH4_TIM7_UP (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA1 channel 4 */ +#define DMA1_CH4_DAC_CH2 (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_DAC_CH2) /*!< Remap DAC Channel 2 on DMA1 channel 4 */ +#define DMA1_CH4_I2C2_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_I2C2_TX) /*!< Remap I2C2 Tx on DMA1 channel 4 */ +#define DMA1_CH4_SPI2_RX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 4 */ +#define DMA1_CH4_TIM2_CH4 (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */ +#define DMA1_CH4_TIM3_CH1 (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */ +#define DMA1_CH4_TIM3_TRIG (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 4 */ +#define DMA1_CH4_TIM16_CH1 (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */ +#define DMA1_CH4_TIM16_UP (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 4 */ +#define DMA1_CH4_USART1_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 4 */ +#define DMA1_CH4_USART2_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 4 */ +#define DMA1_CH4_USART3_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 4 */ +#define DMA1_CH4_USART4_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 4 */ +#define DMA1_CH4_USART5_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 4 */ +#define DMA1_CH4_USART6_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 4 */ +#define DMA1_CH4_USART7_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 4 */ +#define DMA1_CH4_USART8_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 4 */ +/* DMA1 - Channel 5 */ +#define DMA1_CH5_DEFAULT (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ +#define DMA1_CH5_I2C2_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_I2C2_RX) /*!< Remap I2C2 Rx on DMA1 channel 5 */ +#define DMA1_CH5_SPI2_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_SPI2_TX) /*!< Remap SPI1 Tx on DMA1 channel 5 */ +#define DMA1_CH5_TIM1_CH3 (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */ +#define DMA1_CH5_USART1_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 5 */ +#define DMA1_CH5_USART2_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 5 */ +#define DMA1_CH5_USART3_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 5 */ +#define DMA1_CH5_USART4_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 5 */ +#define DMA1_CH5_USART5_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 5 */ +#define DMA1_CH5_USART6_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 5 */ +#define DMA1_CH5_USART7_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 5 */ +#define DMA1_CH5_USART8_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 5 */ +/* DMA1 - Channel 6 */ +#define DMA1_CH6_DEFAULT (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ +#define DMA1_CH6_I2C1_TX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 6 */ +#define DMA1_CH6_SPI2_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 6 */ +#define DMA1_CH6_TIM1_CH1 (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */ +#define DMA1_CH6_TIM1_CH2 (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */ +#define DMA1_CH6_TIM1_CH3 (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */ +#define DMA1_CH6_TIM3_CH1 (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */ +#define DMA1_CH6_TIM3_TRIG (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 6 */ +#define DMA1_CH6_TIM16_CH1 (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */ +#define DMA1_CH6_TIM16_UP (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 6 */ +#define DMA1_CH6_USART1_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 6 */ +#define DMA1_CH6_USART2_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 6 */ +#define DMA1_CH6_USART3_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 6 */ +#define DMA1_CH6_USART4_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 6 */ +#define DMA1_CH6_USART5_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 6 */ +#define DMA1_CH6_USART6_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 6 */ +#define DMA1_CH6_USART7_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 6 */ +#define DMA1_CH6_USART8_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 6 */ +/* DMA1 - Channel 7 */ +#define DMA1_CH7_DEFAULT (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ +#define DMA1_CH7_I2C1_RX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 7 */ +#define DMA1_CH7_SPI2_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_SPI2_TX) /*!< Remap SPI2 Tx on DMA1 channel 7 */ +#define DMA1_CH7_TIM2_CH2 (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */ +#define DMA1_CH7_TIM2_CH4 (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */ +#define DMA1_CH7_TIM17_CH1 (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */ +#define DMA1_CH7_TIM17_UP (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 7 */ +#define DMA1_CH7_USART1_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 7 */ +#define DMA1_CH7_USART2_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 7 */ +#define DMA1_CH7_USART3_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 7 */ +#define DMA1_CH7_USART4_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 7 */ +#define DMA1_CH7_USART5_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 7 */ +#define DMA1_CH7_USART6_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 7 */ +#define DMA1_CH7_USART7_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 7 */ +#define DMA1_CH7_USART8_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 7 */ + +#define IS_DMA1_REMAP(REMAP) ((REMAP == DMA1_CH1_DEFAULT) ||\ + (REMAP == DMA1_CH1_ADC) ||\ + (REMAP == DMA1_CH1_TIM17_CH1) ||\ + (REMAP == DMA1_CH1_TIM17_UP) ||\ + (REMAP == DMA1_CH1_USART1_RX) ||\ + (REMAP == DMA1_CH1_USART2_RX) ||\ + (REMAP == DMA1_CH1_USART3_RX) ||\ + (REMAP == DMA1_CH1_USART4_RX) ||\ + (REMAP == DMA1_CH1_USART5_RX) ||\ + (REMAP == DMA1_CH1_USART6_RX) ||\ + (REMAP == DMA1_CH1_USART7_RX) ||\ + (REMAP == DMA1_CH1_USART8_RX) ||\ + (REMAP == DMA1_CH2_DEFAULT) ||\ + (REMAP == DMA1_CH2_ADC) ||\ + (REMAP == DMA1_CH2_I2C1_TX) ||\ + (REMAP == DMA1_CH2_SPI1_RX) ||\ + (REMAP == DMA1_CH2_TIM1_CH1) ||\ + (REMAP == DMA1_CH2_I2C1_TX) ||\ + (REMAP == DMA1_CH2_TIM17_CH1) ||\ + (REMAP == DMA1_CH2_TIM17_UP) ||\ + (REMAP == DMA1_CH2_USART1_TX) ||\ + (REMAP == DMA1_CH2_USART2_TX) ||\ + (REMAP == DMA1_CH2_USART3_TX) ||\ + (REMAP == DMA1_CH2_USART4_TX) ||\ + (REMAP == DMA1_CH2_USART5_TX) ||\ + (REMAP == DMA1_CH2_USART6_TX) ||\ + (REMAP == DMA1_CH2_USART7_TX) ||\ + (REMAP == DMA1_CH2_USART8_TX) ||\ + (REMAP == DMA1_CH3_DEFAULT) ||\ + (REMAP == DMA1_CH3_TIM6_UP) ||\ + (REMAP == DMA1_CH3_DAC_CH1) ||\ + (REMAP == DMA1_CH3_I2C1_RX) ||\ + (REMAP == DMA1_CH3_SPI1_TX) ||\ + (REMAP == DMA1_CH3_TIM1_CH2) ||\ + (REMAP == DMA1_CH3_TIM2_CH2) ||\ + (REMAP == DMA1_CH3_TIM16_CH1) ||\ + (REMAP == DMA1_CH3_TIM16_UP) ||\ + (REMAP == DMA1_CH3_USART1_RX) ||\ + (REMAP == DMA1_CH3_USART2_RX) ||\ + (REMAP == DMA1_CH3_USART3_RX) ||\ + (REMAP == DMA1_CH3_USART4_RX) ||\ + (REMAP == DMA1_CH3_USART5_RX) ||\ + (REMAP == DMA1_CH3_USART6_RX) ||\ + (REMAP == DMA1_CH3_USART7_RX) ||\ + (REMAP == DMA1_CH3_USART8_RX) ||\ + (REMAP == DMA1_CH4_DEFAULT) ||\ + (REMAP == DMA1_CH4_TIM7_UP) ||\ + (REMAP == DMA1_CH4_DAC_CH2) ||\ + (REMAP == DMA1_CH4_I2C2_TX) ||\ + (REMAP == DMA1_CH4_SPI2_RX) ||\ + (REMAP == DMA1_CH4_TIM2_CH4) ||\ + (REMAP == DMA1_CH4_TIM3_CH1) ||\ + (REMAP == DMA1_CH4_TIM3_TRIG) ||\ + (REMAP == DMA1_CH4_TIM16_CH1) ||\ + (REMAP == DMA1_CH4_TIM16_UP) ||\ + (REMAP == DMA1_CH4_USART1_TX) ||\ + (REMAP == DMA1_CH4_USART2_TX) ||\ + (REMAP == DMA1_CH4_USART3_TX) ||\ + (REMAP == DMA1_CH4_USART4_TX) ||\ + (REMAP == DMA1_CH4_USART5_TX) ||\ + (REMAP == DMA1_CH4_USART6_TX) ||\ + (REMAP == DMA1_CH4_USART7_TX) ||\ + (REMAP == DMA1_CH4_USART8_TX) ||\ + (REMAP == DMA1_CH5_DEFAULT) ||\ + (REMAP == DMA1_CH5_I2C2_RX) ||\ + (REMAP == DMA1_CH5_SPI2_TX) ||\ + (REMAP == DMA1_CH5_TIM1_CH3) ||\ + (REMAP == DMA1_CH5_USART1_RX) ||\ + (REMAP == DMA1_CH5_USART2_RX) ||\ + (REMAP == DMA1_CH5_USART3_RX) ||\ + (REMAP == DMA1_CH5_USART4_RX) ||\ + (REMAP == DMA1_CH5_USART5_RX) ||\ + (REMAP == DMA1_CH5_USART6_RX) ||\ + (REMAP == DMA1_CH5_USART7_RX) ||\ + (REMAP == DMA1_CH5_USART8_RX) ||\ + (REMAP == DMA1_CH6_DEFAULT) ||\ + (REMAP == DMA1_CH6_I2C1_TX) ||\ + (REMAP == DMA1_CH6_SPI2_RX) ||\ + (REMAP == DMA1_CH6_TIM1_CH1) ||\ + (REMAP == DMA1_CH6_TIM1_CH2) ||\ + (REMAP == DMA1_CH6_TIM1_CH3) ||\ + (REMAP == DMA1_CH6_TIM3_CH1) ||\ + (REMAP == DMA1_CH6_TIM3_TRIG) ||\ + (REMAP == DMA1_CH6_TIM16_CH1) ||\ + (REMAP == DMA1_CH6_TIM16_UP) ||\ + (REMAP == DMA1_CH6_USART1_RX) ||\ + (REMAP == DMA1_CH6_USART2_RX) ||\ + (REMAP == DMA1_CH6_USART3_RX) ||\ + (REMAP == DMA1_CH6_USART4_RX) ||\ + (REMAP == DMA1_CH6_USART5_RX) ||\ + (REMAP == DMA1_CH6_USART6_RX) ||\ + (REMAP == DMA1_CH6_USART7_RX) ||\ + (REMAP == DMA1_CH6_USART8_RX) ||\ + (REMAP == DMA1_CH7_DEFAULT) ||\ + (REMAP == DMA1_CH7_I2C1_RX) ||\ + (REMAP == DMA1_CH7_SPI2_TX) ||\ + (REMAP == DMA1_CH7_TIM2_CH2) ||\ + (REMAP == DMA1_CH7_TIM2_CH4) ||\ + (REMAP == DMA1_CH7_TIM17_CH1) ||\ + (REMAP == DMA1_CH7_TIM17_UP) ||\ + (REMAP == DMA1_CH7_USART1_TX) ||\ + (REMAP == DMA1_CH7_USART2_TX) ||\ + (REMAP == DMA1_CH7_USART3_TX) ||\ + (REMAP == DMA1_CH7_USART4_TX) ||\ + (REMAP == DMA1_CH7_USART5_TX) ||\ + (REMAP == DMA1_CH7_USART6_TX) ||\ + (REMAP == DMA1_CH7_USART7_TX) ||\ + (REMAP == DMA1_CH7_USART8_TX)) + +/****************** DMA2 remap bit field definition********************/ +/* DMA2 - Channel 1 */ +#define DMA2_CH1_DEFAULT (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ +#define DMA2_CH1_I2C2_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_I2C2_TX) /*!< Remap I2C2 TX on DMA2 channel 1 */ +#define DMA2_CH1_USART1_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 1 */ +#define DMA2_CH1_USART2_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 1 */ +#define DMA2_CH1_USART3_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 1 */ +#define DMA2_CH1_USART4_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 1 */ +#define DMA2_CH1_USART5_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 1 */ +#define DMA2_CH1_USART6_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 1 */ +#define DMA2_CH1_USART7_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 1 */ +#define DMA2_CH1_USART8_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 1 */ +/* DMA2 - Channel 2 */ +#define DMA2_CH2_DEFAULT (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ +#define DMA2_CH2_I2C2_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_I2C2_RX) /*!< Remap I2C2 Rx on DMA2 channel 2 */ +#define DMA2_CH2_USART1_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 2 */ +#define DMA2_CH2_USART2_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 2 */ +#define DMA2_CH2_USART3_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 2 */ +#define DMA2_CH2_USART4_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 2 */ +#define DMA2_CH2_USART5_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 2 */ +#define DMA2_CH2_USART6_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 2 */ +#define DMA2_CH2_USART7_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 2 */ +#define DMA2_CH2_USART8_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 2 */ +/* DMA2 - Channel 3 */ +#define DMA2_CH3_DEFAULT (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ +#define DMA2_CH3_TIM6_UP (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA2 channel 3 */ +#define DMA2_CH3_DAC_CH1 (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_DAC_CH1) /*!< Remap DAC channel 1 on DMA2 channel 3 */ +#define DMA2_CH3_SPI1_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_SPI1_RX) /*!< Remap SPI1 Rx on DMA2 channel 3 */ +#define DMA2_CH3_USART1_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 3 */ +#define DMA2_CH3_USART2_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 3 */ +#define DMA2_CH3_USART3_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 3 */ +#define DMA2_CH3_USART4_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 3 */ +#define DMA2_CH3_USART5_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 3 */ +#define DMA2_CH3_USART6_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 3 */ +#define DMA2_CH3_USART7_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 3 */ +#define DMA2_CH3_USART8_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 3 */ +/* DMA2 - Channel 4 */ +#define DMA2_CH4_DEFAULT (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ +#define DMA2_CH4_TIM7_UP (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA2 channel 4 */ +#define DMA2_CH4_DAC_CH2 (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_DAC_CH2) /*!< Remap DAC channel 2 on DMA2 channel 4 */ +#define DMA2_CH4_SPI1_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_SPI1_TX) /*!< Remap SPI1 Tx on DMA2 channel 4 */ +#define DMA2_CH4_USART1_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 4 */ +#define DMA2_CH4_USART2_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 4 */ +#define DMA2_CH4_USART3_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 4 */ +#define DMA2_CH4_USART4_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 4 */ +#define DMA2_CH4_USART5_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 4 */ +#define DMA2_CH4_USART6_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 4 */ +#define DMA2_CH4_USART7_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 4 */ +#define DMA2_CH4_USART8_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 4 */ +/* DMA2 - Channel 5 */ +#define DMA2_CH5_DEFAULT (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ +#define DMA2_CH5_ADC (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_ADC) /*!< Remap ADC on DMA2 channel 5 */ +#define DMA2_CH5_USART1_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 5 */ +#define DMA2_CH5_USART2_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 5 */ +#define DMA2_CH5_USART3_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 5 */ +#define DMA2_CH5_USART4_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 5 */ +#define DMA2_CH5_USART5_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 5 */ +#define DMA2_CH5_USART6_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 5 */ +#define DMA2_CH5_USART7_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 5 */ +#define DMA2_CH5_USART8_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 5 */ + +#define IS_DMA2_REMAP(REMAP) ((REMAP == DMA2_CH1_DEFAULT) ||\ + (REMAP == DMA2_CH1_I2C2_TX) ||\ + (REMAP == DMA2_CH1_USART1_TX) ||\ + (REMAP == DMA2_CH1_USART2_TX) ||\ + (REMAP == DMA2_CH1_USART3_TX) ||\ + (REMAP == DMA2_CH1_USART4_TX) ||\ + (REMAP == DMA2_CH1_USART5_TX) ||\ + (REMAP == DMA2_CH1_USART6_TX) ||\ + (REMAP == DMA2_CH1_USART7_TX) ||\ + (REMAP == DMA2_CH1_USART8_TX) ||\ + (REMAP == DMA2_CH2_DEFAULT) ||\ + (REMAP == DMA2_CH2_I2C2_RX) ||\ + (REMAP == DMA2_CH2_USART1_RX) ||\ + (REMAP == DMA2_CH2_USART2_RX) ||\ + (REMAP == DMA2_CH2_USART3_RX) ||\ + (REMAP == DMA2_CH2_USART4_RX) ||\ + (REMAP == DMA2_CH2_USART5_RX) ||\ + (REMAP == DMA2_CH2_USART6_RX) ||\ + (REMAP == DMA2_CH2_USART7_RX) ||\ + (REMAP == DMA2_CH2_USART8_RX) ||\ + (REMAP == DMA2_CH3_DEFAULT) ||\ + (REMAP == DMA2_CH3_TIM6_UP) ||\ + (REMAP == DMA2_CH3_DAC_CH1) ||\ + (REMAP == DMA2_CH3_SPI1_RX) ||\ + (REMAP == DMA2_CH3_USART1_RX) ||\ + (REMAP == DMA2_CH3_USART2_RX) ||\ + (REMAP == DMA2_CH3_USART3_RX) ||\ + (REMAP == DMA2_CH3_USART4_RX) ||\ + (REMAP == DMA2_CH3_USART5_RX) ||\ + (REMAP == DMA2_CH3_USART6_RX) ||\ + (REMAP == DMA2_CH3_USART7_RX) ||\ + (REMAP == DMA2_CH3_USART8_RX) ||\ + (REMAP == DMA2_CH4_DEFAULT) ||\ + (REMAP == DMA2_CH4_TIM7_UP) ||\ + (REMAP == DMA2_CH4_DAC_CH2) ||\ + (REMAP == DMA2_CH4_SPI1_TX) ||\ + (REMAP == DMA2_CH4_USART1_TX) ||\ + (REMAP == DMA2_CH4_USART2_TX) ||\ + (REMAP == DMA2_CH4_USART3_TX) ||\ + (REMAP == DMA2_CH4_USART4_TX) ||\ + (REMAP == DMA2_CH4_USART5_TX) ||\ + (REMAP == DMA2_CH4_USART6_TX) ||\ + (REMAP == DMA2_CH4_USART7_TX) ||\ + (REMAP == DMA2_CH4_USART8_TX) ||\ + (REMAP == DMA2_CH5_DEFAULT) ||\ + (REMAP == DMA2_CH5_ADC) ||\ + (REMAP == DMA2_CH5_USART1_TX) ||\ + (REMAP == DMA2_CH5_USART2_TX) ||\ + (REMAP == DMA2_CH5_USART3_TX) ||\ + (REMAP == DMA2_CH5_USART4_TX) ||\ + (REMAP == DMA2_CH5_USART5_TX) ||\ + (REMAP == DMA2_CH5_USART6_TX) ||\ + (REMAP == DMA2_CH5_USART7_TX) ||\ + (REMAP == DMA2_CH5_USART8_TX )) + +/** + * @} + */ + +/** @defgroup DMA_interrupts_definition + * @{ + */ + +#define DMA_IT_TC DMA_CCR_TCIE +#define DMA_IT_HT DMA_CCR_HTIE +#define DMA_IT_TE DMA_CCR_TEIE + +#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) + +#define DMA1_IT_GL1 DMA_ISR_GIF1 +#define DMA1_IT_TC1 DMA_ISR_TCIF1 +#define DMA1_IT_HT1 DMA_ISR_HTIF1 +#define DMA1_IT_TE1 DMA_ISR_TEIF1 +#define DMA1_IT_GL2 DMA_ISR_GIF2 +#define DMA1_IT_TC2 DMA_ISR_TCIF2 +#define DMA1_IT_HT2 DMA_ISR_HTIF2 +#define DMA1_IT_TE2 DMA_ISR_TEIF2 +#define DMA1_IT_GL3 DMA_ISR_GIF3 +#define DMA1_IT_TC3 DMA_ISR_TCIF3 +#define DMA1_IT_HT3 DMA_ISR_HTIF3 +#define DMA1_IT_TE3 DMA_ISR_TEIF3 +#define DMA1_IT_GL4 DMA_ISR_GIF4 +#define DMA1_IT_TC4 DMA_ISR_TCIF4 +#define DMA1_IT_HT4 DMA_ISR_HTIF4 +#define DMA1_IT_TE4 DMA_ISR_TEIF4 +#define DMA1_IT_GL5 DMA_ISR_GIF5 +#define DMA1_IT_TC5 DMA_ISR_TCIF5 +#define DMA1_IT_HT5 DMA_ISR_HTIF5 +#define DMA1_IT_TE5 DMA_ISR_TEIF5 +#define DMA1_IT_GL6 DMA_ISR_GIF6 /*!< Only applicable for STM32F072 and STM32F091 devices */ +#define DMA1_IT_TC6 DMA_ISR_TCIF6 /*!< Only applicable for STM32F072 and STM32F091 devices */ +#define DMA1_IT_HT6 DMA_ISR_HTIF6 /*!< Only applicable for STM32F072 and STM32F091 devices */ +#define DMA1_IT_TE6 DMA_ISR_TEIF6 /*!< Only applicable for STM32F072 and STM32F091 devices */ +#define DMA1_IT_GL7 DMA_ISR_GIF7 /*!< Only applicable for STM32F072 and STM32F091 devices */ +#define DMA1_IT_TC7 DMA_ISR_TCIF7 /*!< Only applicable for STM32F072 and STM32F091 devices */ +#define DMA1_IT_HT7 DMA_ISR_HTIF7 /*!< Only applicable for STM32F072 and STM32F091 devices */ +#define DMA1_IT_TE7 DMA_ISR_TEIF7 /*!< Only applicable for STM32F072 and STM32F091 devices */ + +#define DMA2_IT_GL1 ((uint32_t)0x10000001) /*!< Only applicable for STM32F091 devices */ +#define DMA2_IT_TC1 ((uint32_t)0x10000002) /*!< Only applicable for STM32F091 devices */ +#define DMA2_IT_HT1 ((uint32_t)0x10000004) /*!< Only applicable for STM32F091 devices */ +#define DMA2_IT_TE1 ((uint32_t)0x10000008) /*!< Only applicable for STM32F091 devices */ +#define DMA2_IT_GL2 ((uint32_t)0x10000010) /*!< Only applicable for STM32F091 devices */ +#define DMA2_IT_TC2 ((uint32_t)0x10000020) /*!< Only applicable for STM32F091 devices */ +#define DMA2_IT_HT2 ((uint32_t)0x10000040) /*!< Only applicable for STM32F091 devices */ +#define DMA2_IT_TE2 ((uint32_t)0x10000080) /*!< Only applicable for STM32F091 devices */ +#define DMA2_IT_GL3 ((uint32_t)0x10000100) /*!< Only applicable for STM32F091 devices */ +#define DMA2_IT_TC3 ((uint32_t)0x10000200) /*!< Only applicable for STM32F091 devices */ +#define DMA2_IT_HT3 ((uint32_t)0x10000400) /*!< Only applicable for STM32F091 devices */ +#define DMA2_IT_TE3 ((uint32_t)0x10000800) /*!< Only applicable for STM32F091 devices */ +#define DMA2_IT_GL4 ((uint32_t)0x10001000) /*!< Only applicable for STM32F091 devices */ +#define DMA2_IT_TC4 ((uint32_t)0x10002000) /*!< Only applicable for STM32F091 devices */ +#define DMA2_IT_HT4 ((uint32_t)0x10004000) /*!< Only applicable for STM32F091 devices */ +#define DMA2_IT_TE4 ((uint32_t)0x10008000) /*!< Only applicable for STM32F091 devices */ +#define DMA2_IT_GL5 ((uint32_t)0x10010000) /*!< Only applicable for STM32F091 devices */ +#define DMA2_IT_TC5 ((uint32_t)0x10020000) /*!< Only applicable for STM32F091 devices */ +#define DMA2_IT_HT5 ((uint32_t)0x10040000) /*!< Only applicable for STM32F091 devices */ +#define DMA2_IT_TE5 ((uint32_t)0x10080000) /*!< Only applicable for STM32F091 devices */ + +#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00)) + +#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ + ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ + ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ + ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ + ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ + ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ + ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ + ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ + ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ + ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ + ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ + ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ + ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ + ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \ + ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \ + ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \ + ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \ + ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \ + ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \ + ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \ + ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \ + ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \ + ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \ + ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5)) + +/** + * @} + */ + +/** @defgroup DMA_flags_definition + * @{ + */ +#define DMA1_FLAG_GL1 DMA_ISR_GIF1 +#define DMA1_FLAG_TC1 DMA_ISR_TCIF1 +#define DMA1_FLAG_HT1 DMA_ISR_HTIF1 +#define DMA1_FLAG_TE1 DMA_ISR_TEIF1 +#define DMA1_FLAG_GL2 DMA_ISR_GIF2 +#define DMA1_FLAG_TC2 DMA_ISR_TCIF2 +#define DMA1_FLAG_HT2 DMA_ISR_HTIF2 +#define DMA1_FLAG_TE2 DMA_ISR_TEIF2 +#define DMA1_FLAG_GL3 DMA_ISR_GIF3 +#define DMA1_FLAG_TC3 DMA_ISR_TCIF3 +#define DMA1_FLAG_HT3 DMA_ISR_HTIF3 +#define DMA1_FLAG_TE3 DMA_ISR_TEIF3 +#define DMA1_FLAG_GL4 DMA_ISR_GIF4 +#define DMA1_FLAG_TC4 DMA_ISR_TCIF4 +#define DMA1_FLAG_HT4 DMA_ISR_HTIF4 +#define DMA1_FLAG_TE4 DMA_ISR_TEIF4 +#define DMA1_FLAG_GL5 DMA_ISR_GIF5 +#define DMA1_FLAG_TC5 DMA_ISR_TCIF5 +#define DMA1_FLAG_HT5 DMA_ISR_HTIF5 +#define DMA1_FLAG_TE5 DMA_ISR_TEIF5 +#define DMA1_FLAG_GL6 DMA_ISR_GIF6 /*!< Only applicable for STM32F072 and STM32F091 devices */ +#define DMA1_FLAG_TC6 DMA_ISR_TCIF6 /*!< Only applicable for STM32F072 and STM32F091 devices */ +#define DMA1_FLAG_HT6 DMA_ISR_HTIF6 /*!< Only applicable for STM32F072 and STM32F091 devices */ +#define DMA1_FLAG_TE6 DMA_ISR_TEIF6 /*!< Only applicable for STM32F072 and STM32F091 devices */ +#define DMA1_FLAG_GL7 DMA_ISR_GIF7 /*!< Only applicable for STM32F072 and STM32F091 devices */ +#define DMA1_FLAG_TC7 DMA_ISR_TCIF7 /*!< Only applicable for STM32F072 and STM32F091 devices */ +#define DMA1_FLAG_HT7 DMA_ISR_HTIF7 /*!< Only applicable for STM32F072 and STM32F091 devices */ +#define DMA1_FLAG_TE7 DMA_ISR_TEIF7 /*!< Only applicable for STM32F072 and STM32F091 devices */ + +#define DMA2_FLAG_GL1 ((uint32_t)0x10000001) +#define DMA2_FLAG_TC1 ((uint32_t)0x10000002) +#define DMA2_FLAG_HT1 ((uint32_t)0x10000004) +#define DMA2_FLAG_TE1 ((uint32_t)0x10000008) +#define DMA2_FLAG_GL2 ((uint32_t)0x10000010) +#define DMA2_FLAG_TC2 ((uint32_t)0x10000020) +#define DMA2_FLAG_HT2 ((uint32_t)0x10000040) +#define DMA2_FLAG_TE2 ((uint32_t)0x10000080) +#define DMA2_FLAG_GL3 ((uint32_t)0x10000100) +#define DMA2_FLAG_TC3 ((uint32_t)0x10000200) +#define DMA2_FLAG_HT3 ((uint32_t)0x10000400) +#define DMA2_FLAG_TE3 ((uint32_t)0x10000800) +#define DMA2_FLAG_GL4 ((uint32_t)0x10001000) +#define DMA2_FLAG_TC4 ((uint32_t)0x10002000) +#define DMA2_FLAG_HT4 ((uint32_t)0x10004000) +#define DMA2_FLAG_TE4 ((uint32_t)0x10008000) +#define DMA2_FLAG_GL5 ((uint32_t)0x10010000) +#define DMA2_FLAG_TC5 ((uint32_t)0x10020000) +#define DMA2_FLAG_HT5 ((uint32_t)0x10040000) +#define DMA2_FLAG_TE5 ((uint32_t)0x10080000) + +#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) + +#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ + ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ + ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ + ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ + ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ + ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ + ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ + ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ + ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ + ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ + ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ + ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ + ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ + ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \ + ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \ + ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \ + ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \ + ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \ + ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \ + ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \ + ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \ + ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \ + ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \ + ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5)) +/** + * @} + */ + +/** @defgroup DMA_Buffer_Size + * @{ + */ + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Function used to set the DMA configuration to the default reset state ******/ +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); + +/* Initialization and Configuration functions *********************************/ +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); +void DMA_RemapConfig(DMA_TypeDef* DMAy, uint32_t DMAx_CHy_RemapRequest); + +/* Data Counter functions******************************************************/ +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); + +/* Interrupts and flags management functions **********************************/ +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); +void DMA_ClearFlag(uint32_t DMAy_FLAG); +ITStatus DMA_GetITStatus(uint32_t DMAy_IT); +void DMA_ClearITPendingBit(uint32_t DMAy_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F0XX_DMA_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_exti.h b/system/include/stm32f0-stdperiph/stm32f0xx_exti.h new file mode 100644 index 0000000..beeac72 --- /dev/null +++ b/system/include/stm32f0-stdperiph/stm32f0xx_exti.h @@ -0,0 +1,216 @@ +/** + ****************************************************************************** + * @file stm32f0xx_exti.h + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file contains all the functions prototypes for the EXTI + * firmware library + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_EXTI_H +#define __STM32F0XX_EXTI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief EXTI mode enumeration + */ + +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +}EXTIMode_TypeDef; + +#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) + +/** + * @brief EXTI Trigger enumeration + */ + +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +}EXTITrigger_TypeDef; + +#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ + ((TRIGGER) == EXTI_Trigger_Falling) || \ + ((TRIGGER) == EXTI_Trigger_Rising_Falling)) +/** + * @brief EXTI Init Structure definition + */ + +typedef struct +{ + uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination of @ref EXTI_Lines */ + + EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +}EXTI_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Constants + * @{ + */ +/** @defgroup EXTI_Lines + * @{ + */ + +#define EXTI_Line0 ((uint32_t)0x00000001) /*!< External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00000002) /*!< External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00000004) /*!< External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00000008) /*!< External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00000010) /*!< External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00000020) /*!< External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00000040) /*!< External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00000080) /*!< External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00000100) /*!< External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00000200) /*!< External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00000400) /*!< External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00000800) /*!< External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x00001000) /*!< External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x00002000) /*!< External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x00004000) /*!< External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x00008000) /*!< External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x00010000) /*!< External interrupt line 16 + Connected to the PVD Output, + not applicable for STM32F030 devices */ +#define EXTI_Line17 ((uint32_t)0x00020000) /*!< Internal interrupt line 17 + Connected to the RTC Alarm + event */ +#define EXTI_Line18 ((uint32_t)0x00040000) /*!< Internal interrupt line 18 + Connected to the USB + event, only applicable for + STM32F072 devices */ +#define EXTI_Line19 ((uint32_t)0x00080000) /*!< Internal interrupt line 19 + Connected to the RTC Tamper + and Time Stamp events */ +#define EXTI_Line20 ((uint32_t)0x00100000) /*!< Internal interrupt line 20 + Connected to the RTC wakeup + event, only applicable for + STM32F072 devices */ +#define EXTI_Line21 ((uint32_t)0x00200000) /*!< Internal interrupt line 21 + Connected to the Comparator 1 + event, only applicable for STM32F051 + ans STM32F072 devices */ +#define EXTI_Line22 ((uint32_t)0x00400000) /*!< Internal interrupt line 22 + Connected to the Comparator 2 + event, only applicable for STM32F051 + and STM32F072 devices */ +#define EXTI_Line23 ((uint32_t)0x00800000) /*!< Internal interrupt line 23 + Connected to the I2C1 wakeup + event, not applicable for STM32F030 devices */ +#define EXTI_Line25 ((uint32_t)0x02000000) /*!< Internal interrupt line 25 + Connected to the USART1 wakeup + event, not applicable for STM32F030 devices */ +#define EXTI_Line26 ((uint32_t)0x04000000) /*!< Internal interrupt line 26 + Connected to the USART2 wakeup + event, applicable only for + STM32F072 devices */ +#define EXTI_Line27 ((uint32_t)0x08000000) /*!< Internal interrupt line 27 + Connected to the CEC wakeup + event, applicable only for STM32F051 + and STM32F072 devices */ +#define EXTI_Line31 ((uint32_t)0x80000000) /*!< Internal interrupt line 31 + Connected to the VDD USB monitor + event, applicable only for + STM32F072 devices */ +#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0x71000000) == 0x00) && ((LINE) != (uint16_t)0x00)) + +#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ + ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ + ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ + ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ + ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ + ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ + ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ + ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ + ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ + ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \ + ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \ + ((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line23) || \ + ((LINE) == EXTI_Line25) || ((LINE) == EXTI_Line26) || \ + ((LINE) == EXTI_Line27) || ((LINE) == EXTI_Line31)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +/* Function used to set the EXTI configuration to the default reset state *****/ +void EXTI_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); + +/* Interrupts and flags management functions **********************************/ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); +void EXTI_ClearFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClearITPendingBit(uint32_t EXTI_Line); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0XX_EXTI_H */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_flash.h b/system/include/stm32f0-stdperiph/stm32f0xx_flash.h new file mode 100644 index 0000000..236cdde --- /dev/null +++ b/system/include/stm32f0-stdperiph/stm32f0xx_flash.h @@ -0,0 +1,435 @@ +/** + ****************************************************************************** + * @file stm32f0xx_flash.h + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file contains all the functions prototypes for the FLASH + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_FLASH_H +#define __STM32F0XX_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief FLASH Status + */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_WRP, + FLASH_ERROR_PROGRAM, + FLASH_COMPLETE, + FLASH_TIMEOUT +}FLASH_Status; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup FLASH_Exported_Constants + * @{ + */ + +/** @defgroup FLASH_Latency + * @{ + */ +#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */ +#define FLASH_Latency_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */ + +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ + ((LATENCY) == FLASH_Latency_1)) +/** + * @} + */ + +/** @defgroup FLASH_Interrupts + * @{ + */ + +#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of programming interrupt source */ +#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error interrupt source */ +#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) +/** + * @} + */ + +/** @defgroup FLASH_Address + * @{ + */ +#if defined(STM32F042) || defined(STM32F031) || defined(STM32F070x6) /*32K devices */ + #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x08007FFF)) +#elif defined(STM32F030) || defined(STM32F051) /*64K devices */ + #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0800FFFF)) +#elif defined(STM32F072) || defined(STM32F070xB) /*128K devices */ + #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0801FFFF)) +#else /* STM32F091 || STM32F030 || STM32F030xC */ /*256K Flash devices */ + #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0800FFFF)) +#endif /* STM32F042 || STM32F031 || STM32F070x6 */ +/** + * @} + */ + +/** @defgroup FLASH_OB_DATA_ADDRESS + * @{ + */ +#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) + +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_Write_Protection + * @{ + */ + +#if !defined (STM32F072) && !defined (STM32F070xB) && !defined (STM32F091) && !defined (STM32F030) && !defined (STM32F030xC) /* 32K and 64K Flash devices */ +#define OB_WRP_Pages0to3 ((uint32_t)0x00000001) /* Write protection of page 0 to 3 */ +#define OB_WRP_Pages4to7 ((uint32_t)0x00000002) /* Write protection of page 4 to 7 */ +#define OB_WRP_Pages8to11 ((uint32_t)0x00000004) /* Write protection of page 8 to 11 */ +#define OB_WRP_Pages12to15 ((uint32_t)0x00000008) /* Write protection of page 12 to 15 */ +#define OB_WRP_Pages16to19 ((uint32_t)0x00000010) /* Write protection of page 16 to 19 */ +#define OB_WRP_Pages20to23 ((uint32_t)0x00000020) /* Write protection of page 20 to 23 */ +#define OB_WRP_Pages24to27 ((uint32_t)0x00000040) /* Write protection of page 24 to 27 */ +#define OB_WRP_Pages28to31 ((uint32_t)0x00000080) /* Write protection of page 28 to 31 */ +#define OB_WRP_Pages32to35 ((uint32_t)0x00000100) /* Write protection of page 32 to 35 */ +#define OB_WRP_Pages36to39 ((uint32_t)0x00000200) /* Write protection of page 36 to 39 */ +#define OB_WRP_Pages40to43 ((uint32_t)0x00000400) /* Write protection of page 40 to 43 */ +#define OB_WRP_Pages44to47 ((uint32_t)0x00000800) /* Write protection of page 44 to 47 */ +#define OB_WRP_Pages48to51 ((uint32_t)0x00001000) /* Write protection of page 48 to 51 */ +#define OB_WRP_Pages52to55 ((uint32_t)0x00002000) /* Write protection of page 52 to 55 */ +#define OB_WRP_Pages56to59 ((uint32_t)0x00004000) /* Write protection of page 56 to 59 */ +#define OB_WRP_Pages60to63 ((uint32_t)0x00008000) /* Write protection of page 60 to 63 */ + +#define OB_WRP_AllPages ((uint32_t)0x0000FFFF) /*!< Write protection of all Sectors */ + +#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000)) + +#else /* 128K and 256K Flash devices */ + +#define OB_WRP_Pages0to1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */ +#define OB_WRP_Pages2to3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */ +#define OB_WRP_Pages4to5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */ +#define OB_WRP_Pages6to7 ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */ +#define OB_WRP_Pages8to9 ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */ +#define OB_WRP_Pages10to11 ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */ +#define OB_WRP_Pages12to13 ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */ +#define OB_WRP_Pages14to15 ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */ +#define OB_WRP_Pages16to17 ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */ +#define OB_WRP_Pages18to19 ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */ +#define OB_WRP_Pages20to21 ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */ +#define OB_WRP_Pages22to23 ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */ +#define OB_WRP_Pages24to25 ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */ +#define OB_WRP_Pages26to27 ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */ +#define OB_WRP_Pages28to29 ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */ +#define OB_WRP_Pages30to31 ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */ +#define OB_WRP_Pages32to33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */ +#define OB_WRP_Pages34to35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */ +#define OB_WRP_Pages36to37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */ +#define OB_WRP_Pages38to39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */ +#define OB_WRP_Pages40to41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */ +#define OB_WRP_Pages42to43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */ +#define OB_WRP_Pages44to45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */ +#define OB_WRP_Pages46to47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */ +#define OB_WRP_Pages48to49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */ +#define OB_WRP_Pages50to51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */ +#define OB_WRP_Pages52to53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */ +#define OB_WRP_Pages54to55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */ +#define OB_WRP_Pages56to57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */ +#define OB_WRP_Pages58to59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */ +#define OB_WRP_Pages60to61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */ + +#if defined(STM32F091) || defined(STM32F030xC) /* 256K Flash devices */ +#define OB_WRP_Pages62to127 ((uint32_t)0x80000000) /* Write protection of page 62 to 127 */ +#else /* 128K Flash devices */ +#define OB_WRP_Pages62to63 ((uint32_t)0x80000000) /* Write protection of page 62 to 63 */ +#endif /* STM32F091 || STM32F030xC */ +#define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */ +#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000)) + +#endif /* STM32F072 || STM32F070xB || STM32F091 || STM32F030 || STM32F030xC */ +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_Read_Protection + * @{ + */ + +/** + * @brief FLASH_Read Protection Level + */ +#define OB_RDP_Level_0 ((uint8_t)0xAA) +#define OB_RDP_Level_1 ((uint8_t)0xBB) +/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2 + it's no more possible to go back to level 1 or 0 */ + +#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\ + ((LEVEL) == OB_RDP_Level_1))/*||\ + ((LEVEL) == OB_RDP_Level_2))*/ +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_IWatchdog + * @{ + */ + +#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */ +#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_nRST_STOP + * @{ + */ + +#define OB_STOP_NoRST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) + +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_nRST_STDBY + * @{ + */ + +#define OB_STDBY_NoRST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) + +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_BOOT1 + * @{ + */ + +#define OB_BOOT1_RESET ((uint8_t)0x00) /*!< BOOT1 Reset */ +#define OB_BOOT1_SET ((uint8_t)0x10) /*!< BOOT1 Set */ +#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET)) + +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_BOOT0 + * @{ + */ + +#define OB_BOOT0_RESET ((uint8_t)0x00) /*!< BOOT0 Reset */ +#define OB_BOOT0_SET ((uint8_t)0x08) /*!< BOOT0 Set */ +#define IS_OB_BOOT0(BOOT0) (((BOOT0) == OB_BOOT0_RESET) || ((BOOT0) == OB_BOOT0_SET)) + +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_BOOT0SW + * @{ + */ + +#define OB_BOOT0_SW ((uint8_t)0x00) /*!< BOOT0 pin disabled */ +#define OB_BOOT0_HW ((uint8_t)0x80) /*!< BOOT0 pin bonded with GPIO */ +#define IS_OB_BOOT0SW(BOOT0) (((BOOT0) == OB_BOOT0_SW) || ((BOOT0) == OB_BOOT0_HW)) + +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_VDDA_Analog_Monitoring + * @{ + */ + +#define OB_VDDA_ANALOG_ON ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source ON */ +#define OB_VDDA_ANALOG_OFF ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source OFF */ + +#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF)) + +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_SRAM_Parity_Enable + * @{ + */ + +#define OB_SRAM_PARITY_SET ((uint8_t)0x00) /*!< SRAM parity enable Set */ +#define OB_SRAM_PARITY_RESET ((uint8_t)0x40) /*!< SRAM parity enable reset */ + +#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET)) + +/** + * @} + */ + +/** @defgroup FLASH_Flags + * @{ + */ + +#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ +#define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */ +#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */ + +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCB) == 0x00000000) && ((FLAG) != 0x00000000)) + +#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PGERR) || \ + ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP)) +/** + * @} + */ + +/** @defgroup FLASH_Timeout_definition + * @{ + */ +#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x000B0000) + +/** + * @} + */ + +/** @defgroup FLASH_Legacy + * @{ + */ +#define FLASH_WRProt_Pages0to3 OB_WRP_Pages0to3 +#define FLASH_WRProt_Pages4to7 OB_WRP_Pages4to7 +#define FLASH_WRProt_Pages8to11 OB_WRP_Pages8to11 +#define FLASH_WRProt_Pages12to15 OB_WRP_Pages12to15 +#define FLASH_WRProt_Pages16to19 OB_WRP_Pages16to19 +#define FLASH_WRProt_Pages20to23 OB_WRP_Pages20to23 +#define FLASH_WRProt_Pages24to27 OB_WRP_Pages24to27 +#define FLASH_WRProt_Pages28to31 OB_WRP_Pages28to31 +#define FLASH_WRProt_Pages32to35 OB_WRP_Pages32to35 +#define FLASH_WRProt_Pages36to39 OB_WRP_Pages36to39 +#define FLASH_WRProt_Pages40to43 OB_WRP_Pages40to21 +#define FLASH_WRProt_Pages44to47 OB_WRP_Pages44to23 +#define FLASH_WRProt_Pages48to51 OB_WRP_Pages48to51 +#define FLASH_WRProt_Pages52to55 OB_WRP_Pages52to55 +#define FLASH_WRProt_Pages56to59 OB_WRP_Pages56to59 +#define FLASH_WRProt_Pages60to63 OB_WRP_Pages60to63 + + +#define FLASH_WRProt_AllPages OB_WRP_AllPages +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/** + * @brief FLASH memory functions that can be executed from FLASH. + */ +/* FLASH Interface configuration functions ************************************/ +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_PrefetchBufferCmd(FunctionalState NewState); +FlagStatus FLASH_GetPrefetchBufferStatus(void); + +/* FLASH Memory Programming functions *****************************************/ +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_ErasePage(uint32_t Page_Address); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); + +/* FLASH Option Bytes Programming functions *****************************************/ +void FLASH_OB_Unlock(void); +void FLASH_OB_Lock(void); +void FLASH_OB_Launch(void); +FLASH_Status FLASH_OB_Erase(void); +FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP); +FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP); +FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); +FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1); +FLASH_Status FLASH_OB_BOOT0Config(uint8_t OB_BOOT0); +FLASH_Status FLASH_OB_BOOT0SWConfig(uint8_t OB_BOOT0SW); +FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG); +FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity); +FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER); +FLASH_Status FLASH_OB_ProgramData(uint32_t Address, uint8_t Data); +uint8_t FLASH_OB_GetUser(void); +uint32_t FLASH_OB_GetWRP(void); +FlagStatus FLASH_OB_GetRDP(void); + +/* FLASH Interrupts and flags management functions **********************************/ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); + +/** @defgroup FLASH_Legacy + * @{ + */ +#define FLASH_EraseOptionBytes FLASH_OB_Erase +#define FLASH_EnableWriteProtection FLASH_OB_EnableWRP +#define FLASH_UserOptionByteConfig FLASH_OB_UserConfig +#define FLASH_ProgramOptionByteData FLASH_OB_ProgramData +#define FLASH_GetUserOptionByte FLASH_OB_GetUser +#define FLASH_GetWriteProtectionOptionByte FLASH_OB_GetWRP + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0XX_FLASH_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_gpio.h b/system/include/stm32f0-stdperiph/stm32f0xx_gpio.h new file mode 100644 index 0000000..867e4d8 --- /dev/null +++ b/system/include/stm32f0-stdperiph/stm32f0xx_gpio.h @@ -0,0 +1,358 @@ +/** + ****************************************************************************** + * @file stm32f0xx_gpio.h + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file contains all the functions prototypes for the GPIO + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_GPIO_H +#define __STM32F0XX_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ +/* Exported types ------------------------------------------------------------*/ + +#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ + ((PERIPH) == GPIOB) || \ + ((PERIPH) == GPIOC) || \ + ((PERIPH) == GPIOD) || \ + ((PERIPH) == GPIOE) || \ + ((PERIPH) == GPIOF)) + +#define IS_GPIO_LIST_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ + ((PERIPH) == GPIOB)) + +/** @defgroup Configuration_Mode_enumeration + * @{ + */ +typedef enum +{ + GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */ + GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */ + GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */ + GPIO_Mode_AN = 0x03 /*!< GPIO Analog In/Out Mode */ +}GPIOMode_TypeDef; + +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)|| ((MODE) == GPIO_Mode_OUT) || \ + ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN)) +/** + * @} + */ + +/** @defgroup Output_type_enumeration + * @{ + */ +typedef enum +{ + GPIO_OType_PP = 0x00, + GPIO_OType_OD = 0x01 +}GPIOOType_TypeDef; + +#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD)) + +/** + * @} + */ + +/** @defgroup Output_Maximum_frequency_enumeration + * @{ + */ +typedef enum +{ + GPIO_Speed_Level_1 = 0x00, /*!< I/O output speed: Low 2 MHz */ + GPIO_Speed_Level_2 = 0x01, /*!< I/O output speed: Medium 10 MHz */ + GPIO_Speed_Level_3 = 0x03 /*!< I/O output speed: High 50 MHz */ +}GPIOSpeed_TypeDef; + +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_Level_1) || ((SPEED) == GPIO_Speed_Level_2) || \ + ((SPEED) == GPIO_Speed_Level_3)) +/** + * @} + */ + +/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration + * @{ + */ +typedef enum +{ + GPIO_PuPd_NOPULL = 0x00, + GPIO_PuPd_UP = 0x01, + GPIO_PuPd_DOWN = 0x02 +}GPIOPuPd_TypeDef; + +#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \ + ((PUPD) == GPIO_PuPd_DOWN)) +/** + * @} + */ + +/** @defgroup Bit_SET_and_Bit_RESET_enumeration + * @{ + */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +}BitAction; + +#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) +/** + * @} + */ + +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ + + GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIOOType_TypeDef */ + + GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIOPuPd_TypeDef */ +}GPIO_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Constants + * @{ + */ + +/** @defgroup GPIO_pins_define + * @{ + */ +#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ + +#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00) + +#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ + ((PIN) == GPIO_Pin_1) || \ + ((PIN) == GPIO_Pin_2) || \ + ((PIN) == GPIO_Pin_3) || \ + ((PIN) == GPIO_Pin_4) || \ + ((PIN) == GPIO_Pin_5) || \ + ((PIN) == GPIO_Pin_6) || \ + ((PIN) == GPIO_Pin_7) || \ + ((PIN) == GPIO_Pin_8) || \ + ((PIN) == GPIO_Pin_9) || \ + ((PIN) == GPIO_Pin_10) || \ + ((PIN) == GPIO_Pin_11) || \ + ((PIN) == GPIO_Pin_12) || \ + ((PIN) == GPIO_Pin_13) || \ + ((PIN) == GPIO_Pin_14) || \ + ((PIN) == GPIO_Pin_15)) + +/** + * @} + */ + +/** @defgroup GPIO_Pin_sources + * @{ + */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + +#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ + ((PINSOURCE) == GPIO_PinSource1) || \ + ((PINSOURCE) == GPIO_PinSource2) || \ + ((PINSOURCE) == GPIO_PinSource3) || \ + ((PINSOURCE) == GPIO_PinSource4) || \ + ((PINSOURCE) == GPIO_PinSource5) || \ + ((PINSOURCE) == GPIO_PinSource6) || \ + ((PINSOURCE) == GPIO_PinSource7) || \ + ((PINSOURCE) == GPIO_PinSource8) || \ + ((PINSOURCE) == GPIO_PinSource9) || \ + ((PINSOURCE) == GPIO_PinSource10) || \ + ((PINSOURCE) == GPIO_PinSource11) || \ + ((PINSOURCE) == GPIO_PinSource12) || \ + ((PINSOURCE) == GPIO_PinSource13) || \ + ((PINSOURCE) == GPIO_PinSource14) || \ + ((PINSOURCE) == GPIO_PinSource15)) +/** + * @} + */ + +/** @defgroup GPIO_Alternate_function_selection_define + * @{ + */ + +/** + * @brief AF 0 selection + */ +#define GPIO_AF_0 ((uint8_t)0x00) /* WKUP, EVENTOUT, TIM15, SPI1, TIM17, + MCO, SWDAT, SWCLK, TIM14, BOOT, + USART1, CEC, IR_OUT, SPI2, TS, TIM3, + USART4, CAN, TIM3, USART2, USART3, + CRS, TIM16, TIM1 */ +/** + * @brief AF 1 selection + */ +#define GPIO_AF_1 ((uint8_t)0x01) /* USART2, CEC, TIM3, USART1, IR, + EVENTOUT, I2C1, I2C2, TIM15, SPI2, + USART3, TS, SPI1 */ +/** + * @brief AF 2 selection + */ +#define GPIO_AF_2 ((uint8_t)0x02) /* TIM2, TIM1, EVENTOUT, TIM16, TIM17, + USB */ +/** + * @brief AF 3 selection + */ +#define GPIO_AF_3 ((uint8_t)0x03) /* TS, I2C1, TIM15, EVENTOUT */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF_4 ((uint8_t)0x04) /* TIM14, USART4, USART3, CRS, CAN, + I2C1 */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF_5 ((uint8_t)0x05) /* TIM16, TIM17, TIM15, SPI2, I2C2, + MCO, I2C1, USB */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF_6 ((uint8_t)0x06) /* EVENTOUT */ +/** + * @brief AF 7 selection + */ +#define GPIO_AF_7 ((uint8_t)0x07) /* COMP1 OUT and COMP2 OUT */ + +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_0) || ((AF) == GPIO_AF_1) || \ + ((AF) == GPIO_AF_2) || ((AF) == GPIO_AF_3) || \ + ((AF) == GPIO_AF_4) || ((AF) == GPIO_AF_5) || \ + ((AF) == GPIO_AF_6) || ((AF) == GPIO_AF_7)) + +/** + * @} + */ + +/** @defgroup GPIO_Speed_Legacy + * @{ + */ + +#define GPIO_Speed_2MHz GPIO_Speed_Level_1 /*!< I/O output speed: Low 2 MHz */ +#define GPIO_Speed_10MHz GPIO_Speed_Level_2 /*!< I/O output speed: Medium 10 MHz */ +#define GPIO_Speed_50MHz GPIO_Speed_Level_3 /*!< I/O output speed: High 50 MHz */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +/* Function used to set the GPIO configuration to the default reset state *****/ +void GPIO_DeInit(GPIO_TypeDef* GPIOx); + +/* Initialization and Configuration functions *********************************/ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); + +/* GPIO Read and Write functions **********************************************/ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); + +/* GPIO Alternate functions configuration functions ***************************/ +void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0XX_GPIO_H */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_i2c.h b/system/include/stm32f0-stdperiph/stm32f0xx_i2c.h new file mode 100644 index 0000000..0e29f5d --- /dev/null +++ b/system/include/stm32f0-stdperiph/stm32f0xx_i2c.h @@ -0,0 +1,478 @@ +/** + ****************************************************************************** + * @file stm32f0xx_i2c.h + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file contains all the functions prototypes for the I2C firmware + * library + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_I2C_H +#define __STM32F0XX_I2C_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief I2C Init structure definition + */ + +typedef struct +{ + uint32_t I2C_Timing; /*!< Specifies the I2C_TIMINGR_register value. + This parameter must be set by referring to I2C_Timing_Config_Tool*/ + + uint32_t I2C_AnalogFilter; /*!< Enables or disables analog noise filter. + This parameter can be a value of @ref I2C_Analog_Filter*/ + + uint32_t I2C_DigitalFilter; /*!< Configures the digital noise filter. + This parameter can be a number between 0x00 and 0x0F*/ + + uint32_t I2C_Mode; /*!< Specifies the I2C mode. + This parameter can be a value of @ref I2C_mode*/ + + uint32_t I2C_OwnAddress1; /*!< Specifies the device own address 1. + This parameter can be a 7-bit or 10-bit address*/ + + uint32_t I2C_Ack; /*!< Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement*/ + + uint32_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address*/ +}I2C_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + + +/** @defgroup I2C_Exported_Constants + * @{ + */ + +#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ + ((PERIPH) == I2C2)) + +#define IS_I2C_1_PERIPH(PERIPH) ((PERIPH) == I2C1) + +/** @defgroup I2C_Analog_Filter + * @{ + */ + +#define I2C_AnalogFilter_Enable ((uint32_t)0x00000000) +#define I2C_AnalogFilter_Disable I2C_CR1_ANFOFF + +#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_AnalogFilter_Enable) || \ + ((FILTER) == I2C_AnalogFilter_Disable)) +/** + * @} + */ + +/** @defgroup I2C_Digital_Filter + * @{ + */ + +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F) +/** + * @} + */ + +/** @defgroup I2C_mode + * @{ + */ + +#define I2C_Mode_I2C ((uint32_t)0x00000000) +#define I2C_Mode_SMBusDevice I2C_CR1_SMBDEN +#define I2C_Mode_SMBusHost I2C_CR1_SMBHEN + +#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ + ((MODE) == I2C_Mode_SMBusDevice) || \ + ((MODE) == I2C_Mode_SMBusHost)) +/** + * @} + */ + +/** @defgroup I2C_acknowledgement + * @{ + */ + +#define I2C_Ack_Enable ((uint32_t)0x00000000) +#define I2C_Ack_Disable I2C_CR2_NACK + +#define IS_I2C_ACK(ACK) (((ACK) == I2C_Ack_Enable) || \ + ((ACK) == I2C_Ack_Disable)) +/** + * @} + */ + +/** @defgroup I2C_acknowledged_address + * @{ + */ + +#define I2C_AcknowledgedAddress_7bit ((uint32_t)0x00000000) +#define I2C_AcknowledgedAddress_10bit I2C_OAR1_OA1MODE + +#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ + ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) +/** + * @} + */ + +/** @defgroup I2C_own_address1 + * @{ + */ + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF) +/** + * @} + */ + +/** @defgroup I2C_transfer_direction + * @{ + */ + +#define I2C_Direction_Transmitter ((uint16_t)0x0000) +#define I2C_Direction_Receiver ((uint16_t)0x0400) + +#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ + ((DIRECTION) == I2C_Direction_Receiver)) +/** + * @} + */ + +/** @defgroup I2C_DMA_transfer_requests + * @{ + */ + +#define I2C_DMAReq_Tx I2C_CR1_TXDMAEN +#define I2C_DMAReq_Rx I2C_CR1_RXDMAEN + +#define IS_I2C_DMA_REQ(REQ) ((((REQ) & (uint32_t)0xFFFF3FFF) == 0x00) && ((REQ) != 0x00)) +/** + * @} + */ + +/** @defgroup I2C_slave_address + * @{ + */ + +#define IS_I2C_SLAVE_ADDRESS(ADDRESS) ((ADDRESS) <= (uint16_t)0x03FF) +/** + * @} + */ + + +/** @defgroup I2C_own_address2 + * @{ + */ + +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF) + +/** + * @} + */ + +/** @defgroup I2C_own_address2_mask + * @{ + */ + +#define I2C_OA2_NoMask ((uint8_t)0x00) +#define I2C_OA2_Mask01 ((uint8_t)0x01) +#define I2C_OA2_Mask02 ((uint8_t)0x02) +#define I2C_OA2_Mask03 ((uint8_t)0x03) +#define I2C_OA2_Mask04 ((uint8_t)0x04) +#define I2C_OA2_Mask05 ((uint8_t)0x05) +#define I2C_OA2_Mask06 ((uint8_t)0x06) +#define I2C_OA2_Mask07 ((uint8_t)0x07) + +#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NoMask) || \ + ((MASK) == I2C_OA2_Mask01) || \ + ((MASK) == I2C_OA2_Mask02) || \ + ((MASK) == I2C_OA2_Mask03) || \ + ((MASK) == I2C_OA2_Mask04) || \ + ((MASK) == I2C_OA2_Mask05) || \ + ((MASK) == I2C_OA2_Mask06) || \ + ((MASK) == I2C_OA2_Mask07)) + +/** + * @} + */ + +/** @defgroup I2C_timeout + * @{ + */ + +#define IS_I2C_TIMEOUT(TIMEOUT) ((TIMEOUT) <= (uint16_t)0x0FFF) + +/** + * @} + */ + +/** @defgroup I2C_registers + * @{ + */ + +#define I2C_Register_CR1 ((uint8_t)0x00) +#define I2C_Register_CR2 ((uint8_t)0x04) +#define I2C_Register_OAR1 ((uint8_t)0x08) +#define I2C_Register_OAR2 ((uint8_t)0x0C) +#define I2C_Register_TIMINGR ((uint8_t)0x10) +#define I2C_Register_TIMEOUTR ((uint8_t)0x14) +#define I2C_Register_ISR ((uint8_t)0x18) +#define I2C_Register_ICR ((uint8_t)0x1C) +#define I2C_Register_PECR ((uint8_t)0x20) +#define I2C_Register_RXDR ((uint8_t)0x24) +#define I2C_Register_TXDR ((uint8_t)0x28) + +#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ + ((REGISTER) == I2C_Register_CR2) || \ + ((REGISTER) == I2C_Register_OAR1) || \ + ((REGISTER) == I2C_Register_OAR2) || \ + ((REGISTER) == I2C_Register_TIMINGR) || \ + ((REGISTER) == I2C_Register_TIMEOUTR) || \ + ((REGISTER) == I2C_Register_ISR) || \ + ((REGISTER) == I2C_Register_ICR) || \ + ((REGISTER) == I2C_Register_PECR) || \ + ((REGISTER) == I2C_Register_RXDR) || \ + ((REGISTER) == I2C_Register_TXDR)) +/** + * @} + */ + +/** @defgroup I2C_interrupts_definition + * @{ + */ + +#define I2C_IT_ERRI I2C_CR1_ERRIE +#define I2C_IT_TCI I2C_CR1_TCIE +#define I2C_IT_STOPI I2C_CR1_STOPIE +#define I2C_IT_NACKI I2C_CR1_NACKIE +#define I2C_IT_ADDRI I2C_CR1_ADDRIE +#define I2C_IT_RXI I2C_CR1_RXIE +#define I2C_IT_TXI I2C_CR1_TXIE + +#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint32_t)0xFFFFFF01) == 0x00) && ((IT) != 0x00)) + +/** + * @} + */ + +/** @defgroup I2C_flags_definition + * @{ + */ + +#define I2C_FLAG_TXE I2C_ISR_TXE +#define I2C_FLAG_TXIS I2C_ISR_TXIS +#define I2C_FLAG_RXNE I2C_ISR_RXNE +#define I2C_FLAG_ADDR I2C_ISR_ADDR +#define I2C_FLAG_NACKF I2C_ISR_NACKF +#define I2C_FLAG_STOPF I2C_ISR_STOPF +#define I2C_FLAG_TC I2C_ISR_TC +#define I2C_FLAG_TCR I2C_ISR_TCR +#define I2C_FLAG_BERR I2C_ISR_BERR +#define I2C_FLAG_ARLO I2C_ISR_ARLO +#define I2C_FLAG_OVR I2C_ISR_OVR +#define I2C_FLAG_PECERR I2C_ISR_PECERR +#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT +#define I2C_FLAG_ALERT I2C_ISR_ALERT +#define I2C_FLAG_BUSY I2C_ISR_BUSY + +#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFF4000) == 0x00) && ((FLAG) != 0x00)) + +#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_TXIS) || \ + ((FLAG) == I2C_FLAG_RXNE) || ((FLAG) == I2C_FLAG_ADDR) || \ + ((FLAG) == I2C_FLAG_NACKF) || ((FLAG) == I2C_FLAG_STOPF) || \ + ((FLAG) == I2C_FLAG_TC) || ((FLAG) == I2C_FLAG_TCR) || \ + ((FLAG) == I2C_FLAG_BERR) || ((FLAG) == I2C_FLAG_ARLO) || \ + ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_PECERR) || \ + ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_ALERT) || \ + ((FLAG) == I2C_FLAG_BUSY)) + +/** + * @} + */ + + +/** @defgroup I2C_interrupts_definition + * @{ + */ + +#define I2C_IT_TXIS I2C_ISR_TXIS +#define I2C_IT_RXNE I2C_ISR_RXNE +#define I2C_IT_ADDR I2C_ISR_ADDR +#define I2C_IT_NACKF I2C_ISR_NACKF +#define I2C_IT_STOPF I2C_ISR_STOPF +#define I2C_IT_TC I2C_ISR_TC +#define I2C_IT_TCR I2C_ISR_TCR +#define I2C_IT_BERR I2C_ISR_BERR +#define I2C_IT_ARLO I2C_ISR_ARLO +#define I2C_IT_OVR I2C_ISR_OVR +#define I2C_IT_PECERR I2C_ISR_PECERR +#define I2C_IT_TIMEOUT I2C_ISR_TIMEOUT +#define I2C_IT_ALERT I2C_ISR_ALERT + +#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFFFFC001) == 0x00) && ((IT) != 0x00)) + +#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_TXIS) || ((IT) == I2C_IT_RXNE) || \ + ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_NACKF) || \ + ((IT) == I2C_IT_STOPF) || ((IT) == I2C_IT_TC) || \ + ((IT) == I2C_IT_TCR) || ((IT) == I2C_IT_BERR) || \ + ((IT) == I2C_IT_ARLO) || ((IT) == I2C_IT_OVR) || \ + ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_TIMEOUT) || \ + ((IT) == I2C_IT_ALERT)) + + +/** + * @} + */ + +/** @defgroup I2C_ReloadEndMode_definition + * @{ + */ + +#define I2C_Reload_Mode I2C_CR2_RELOAD +#define I2C_AutoEnd_Mode I2C_CR2_AUTOEND +#define I2C_SoftEnd_Mode ((uint32_t)0x00000000) + + +#define IS_RELOAD_END_MODE(MODE) (((MODE) == I2C_Reload_Mode) || \ + ((MODE) == I2C_AutoEnd_Mode) || \ + ((MODE) == I2C_SoftEnd_Mode)) + + +/** + * @} + */ + +/** @defgroup I2C_StartStopMode_definition + * @{ + */ + +#define I2C_No_StartStop ((uint32_t)0x00000000) +#define I2C_Generate_Stop I2C_CR2_STOP +#define I2C_Generate_Start_Read (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) +#define I2C_Generate_Start_Write I2C_CR2_START + + +#define IS_START_STOP_MODE(MODE) (((MODE) == I2C_Generate_Stop) || \ + ((MODE) == I2C_Generate_Start_Read) || \ + ((MODE) == I2C_Generate_Start_Write) || \ + ((MODE) == I2C_No_StartStop)) + + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + + +/* Initialization and Configuration functions *********************************/ +void I2C_DeInit(I2C_TypeDef* I2Cx); +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx); +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); /*!< not applicable for STM32F030 devices */ +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask); +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address); +void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); + +/* Communications handling functions ******************************************/ +void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes); +void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction); +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); +uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx); +uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx); +void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode); + +/* SMBUS management functions ************************************************/ +void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout); +void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout); +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); + +/* I2C registers management functions *****************************************/ +uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); + +/* Data transfers management functions ****************************************/ +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); + +/* DMA transfers management functions *****************************************/ +void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); + + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F0XX_I2C_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h b/system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h new file mode 100644 index 0000000..1f2eece --- /dev/null +++ b/system/include/stm32f0-stdperiph/stm32f0xx_iwdg.h @@ -0,0 +1,140 @@ +/** + ****************************************************************************** + * @file stm32f0xx_iwdg.h + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file contains all the functions prototypes for the IWDG + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_IWDG_H +#define __STM32F0XX_IWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup IWDG + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup IWDG_Exported_Constants + * @{ + */ + +/** @defgroup IWDG_WriteAccess + * @{ + */ + +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) +#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ + ((ACCESS) == IWDG_WriteAccess_Disable)) +/** + * @} + */ + +/** @defgroup IWDG_prescaler + * @{ + */ + +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) +#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ + ((PRESCALER) == IWDG_Prescaler_8) || \ + ((PRESCALER) == IWDG_Prescaler_16) || \ + ((PRESCALER) == IWDG_Prescaler_32) || \ + ((PRESCALER) == IWDG_Prescaler_64) || \ + ((PRESCALER) == IWDG_Prescaler_128)|| \ + ((PRESCALER) == IWDG_Prescaler_256)) +/** + * @} + */ + +/** @defgroup IWDG_Flag + * @{ + */ + +#define IWDG_FLAG_PVU IWDG_SR_PVU +#define IWDG_FLAG_RVU IWDG_SR_RVU +#define IWDG_FLAG_WVU IWDG_SR_WVU +#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU) || \ + ((FLAG) == IWDG_FLAG_WVU)) + +#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) + +#define IS_IWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0xFFF) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Prescaler and Counter configuration functions ******************************/ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); +void IWDG_SetReload(uint16_t Reload); +void IWDG_ReloadCounter(void); +void IWDG_SetWindowValue(uint16_t WindowValue); + +/* IWDG activation function ***************************************************/ +void IWDG_Enable(void); + +/* Flag management function ***************************************************/ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0XX_IWDG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_misc.h b/system/include/stm32f0-stdperiph/stm32f0xx_misc.h new file mode 100644 index 0000000..3811f0f --- /dev/null +++ b/system/include/stm32f0-stdperiph/stm32f0xx_misc.h @@ -0,0 +1,143 @@ +/** + ****************************************************************************** + * @file stm32f0xx_misc.h + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file contains all the functions prototypes for the miscellaneous + * firmware library functions (add-on to CMSIS functions). + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_MISC_H +#define __STM32F0XX_MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup MISC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief NVIC Init Structure definition + */ + +typedef struct +{ + uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. + This parameter can be a value of @ref IRQn_Type + (For the complete STM32 Devices IRQ Channels list, + please refer to stm32f0xx.h file) */ + + uint8_t NVIC_IRQChannelPriority; /*!< Specifies the priority level for the IRQ channel specified + in NVIC_IRQChannel. This parameter can be a value + between 0 and 3. */ + + FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel + will be enabled or disabled. + This parameter can be set either to ENABLE or DISABLE */ +} NVIC_InitTypeDef; + +/** + * +@verbatim + +@endverbatim +*/ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup MISC_Exported_Constants + * @{ + */ + +/** @defgroup MISC_System_Low_Power + * @{ + */ + +#define NVIC_LP_SEVONPEND ((uint8_t)0x10) +#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) +#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) +#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ + ((LP) == NVIC_LP_SLEEPDEEP) || \ + ((LP) == NVIC_LP_SLEEPONEXIT)) +/** + * @} + */ + +/** @defgroup MISC_Preemption_Priority_Group + * @{ + */ +#define IS_NVIC_PRIORITY(PRIORITY) ((PRIORITY) < 0x04) + +/** + * @} + */ + +/** @defgroup MISC_SysTick_clock_source + * @{ + */ + +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ + ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0XX_MISC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_pwr.h b/system/include/stm32f0-stdperiph/stm32f0xx_pwr.h new file mode 100644 index 0000000..378e07e --- /dev/null +++ b/system/include/stm32f0-stdperiph/stm32f0xx_pwr.h @@ -0,0 +1,197 @@ +/** + ****************************************************************************** + * @file stm32f0xx_pwr.h + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file contains all the functions prototypes for the PWR firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_PWR_H +#define __STM32F0XX_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Constants + * @{ + */ + +/** @defgroup PWR_PVD_detection_level + * @brief This parameters are only applicable for STM32F051 and STM32F072 devices + * @{ + */ + +#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0 +#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1 +#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2 +#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3 +#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4 +#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5 +#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6 +#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 + +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \ + ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \ + ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \ + ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7)) +/** + * @} + */ + +/** @defgroup PWR_WakeUp_Pins + * @{ + */ + +#define PWR_WakeUpPin_1 PWR_CSR_EWUP1 +#define PWR_WakeUpPin_2 PWR_CSR_EWUP2 +#define PWR_WakeUpPin_3 PWR_CSR_EWUP3 /*!< only applicable for STM32F072 devices */ +#define PWR_WakeUpPin_4 PWR_CSR_EWUP4 /*!< only applicable for STM32F072 devices */ +#define PWR_WakeUpPin_5 PWR_CSR_EWUP5 /*!< only applicable for STM32F072 devices */ +#define PWR_WakeUpPin_6 PWR_CSR_EWUP6 /*!< only applicable for STM32F072 devices */ +#define PWR_WakeUpPin_7 PWR_CSR_EWUP7 /*!< only applicable for STM32F072 devices */ +#define PWR_WakeUpPin_8 PWR_CSR_EWUP8 /*!< only applicable for STM32F072 devices */ +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || ((PIN) == PWR_WakeUpPin_2) || \ + ((PIN) == PWR_WakeUpPin_3) || ((PIN) == PWR_WakeUpPin_4) || \ + ((PIN) == PWR_WakeUpPin_5) || ((PIN) == PWR_WakeUpPin_6) || \ + ((PIN) == PWR_WakeUpPin_7) || ((PIN) == PWR_WakeUpPin_8)) +/** + * @} + */ + + +/** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode + * @{ + */ + +#define PWR_Regulator_ON ((uint32_t)0x00000000) +#define PWR_Regulator_LowPower PWR_CR_LPSDSR +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ + ((REGULATOR) == PWR_Regulator_LowPower)) +/** + * @} + */ + +/** @defgroup PWR_SLEEP_mode_entry + * @{ + */ + +#define PWR_SLEEPEntry_WFI ((uint8_t)0x01) +#define PWR_SLEEPEntry_WFE ((uint8_t)0x02) +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE)) + +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry + * @{ + */ + +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) +#define PWR_STOPEntry_SLEEPONEXIT ((uint8_t)0x03) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE) ||\ + ((ENTRY) == PWR_STOPEntry_SLEEPONEXIT)) + +/** + * @} + */ + +/** @defgroup PWR_Flag + * @{ + */ + +#define PWR_FLAG_WU PWR_CSR_WUF +#define PWR_FLAG_SB PWR_CSR_SBF +#define PWR_FLAG_PVDO PWR_CSR_PVDO /*!< Not applicable for STM32F030 devices */ +#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF + +#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ + ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY)) + +#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Function used to set the PWR configuration to the default reset state ******/ +void PWR_DeInit(void); + +/* Backup Domain Access function **********************************************/ +void PWR_BackupAccessCmd(FunctionalState NewState); + +/* PVD configuration functions ************************************************/ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); /*!< only applicable for STM32F051 and STM32F072 devices */ +void PWR_PVDCmd(FunctionalState NewState); /*!< only applicable for STM32F051 and STM32F072 devices */ + +/* WakeUp pins configuration functions ****************************************/ +void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState); + +/* Low Power modes configuration functions ************************************/ +void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry); +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_EnterSTANDBYMode(void); + +/* Flags management functions *************************************************/ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +void PWR_ClearFlag(uint32_t PWR_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0XX_PWR_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_rcc.h b/system/include/stm32f0-stdperiph/stm32f0xx_rcc.h new file mode 100644 index 0000000..380f98d --- /dev/null +++ b/system/include/stm32f0-stdperiph/stm32f0xx_rcc.h @@ -0,0 +1,624 @@ +/** + ****************************************************************************** + * @file stm32f0xx_rcc.h + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file contains all the functions prototypes for the RCC + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_RCC_H +#define __STM32F0XX_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +typedef struct +{ + uint32_t SYSCLK_Frequency; + uint32_t HCLK_Frequency; + uint32_t PCLK_Frequency; + uint32_t ADCCLK_Frequency; + uint32_t CECCLK_Frequency; + uint32_t I2C1CLK_Frequency; + uint32_t USART1CLK_Frequency; + uint32_t USART2CLK_Frequency; /*!< Only applicable for STM32F072 and STM32F091 devices */ + uint32_t USART3CLK_Frequency; /*!< Only applicable for STM32F091 devices */ + uint32_t USBCLK_Frequency; /*!< Only applicable for STM32F072 devices */ +}RCC_ClocksTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Constants + * @{ + */ + +/** @defgroup RCC_HSE_configuration + * @{ + */ + +#define RCC_HSE_OFF ((uint8_t)0x00) +#define RCC_HSE_ON ((uint8_t)0x01) +#define RCC_HSE_Bypass ((uint8_t)0x05) +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_Bypass)) + +/** + * @} + */ + +/** @defgroup RCC_PLL_Clock_Source + * @{ + */ + +#define RCC_PLLSource_HSI_Div2 RCC_CFGR_PLLSRC_HSI_Div2 +#define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_HSE_PREDIV /* Old HSEPREDIV1 bit definition, maintained for legacy purpose */ +#define RCC_PLLSource_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< Only applicable for STM32F072 devices */ +#define RCC_PLLSource_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV /*!< Only applicable for STM32F072 devices */ +#define RCC_PLLSource_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< Only applicable for STM32F072 devices */ + +#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ + ((SOURCE) == RCC_PLLSource_HSI48) || \ + ((SOURCE) == RCC_PLLSource_HSI) || \ + ((SOURCE) == RCC_PLLSource_HSE) || \ + ((SOURCE) == RCC_PLLSource_PREDIV1)) +/** + * @} + */ + +/** @defgroup RCC_PLL_Multiplication_Factor + * @{ + */ + +#define RCC_PLLMul_2 RCC_CFGR_PLLMULL2 +#define RCC_PLLMul_3 RCC_CFGR_PLLMULL3 +#define RCC_PLLMul_4 RCC_CFGR_PLLMULL4 +#define RCC_PLLMul_5 RCC_CFGR_PLLMULL5 +#define RCC_PLLMul_6 RCC_CFGR_PLLMULL6 +#define RCC_PLLMul_7 RCC_CFGR_PLLMULL7 +#define RCC_PLLMul_8 RCC_CFGR_PLLMULL8 +#define RCC_PLLMul_9 RCC_CFGR_PLLMULL9 +#define RCC_PLLMul_10 RCC_CFGR_PLLMULL10 +#define RCC_PLLMul_11 RCC_CFGR_PLLMULL11 +#define RCC_PLLMul_12 RCC_CFGR_PLLMULL12 +#define RCC_PLLMul_13 RCC_CFGR_PLLMULL13 +#define RCC_PLLMul_14 RCC_CFGR_PLLMULL14 +#define RCC_PLLMul_15 RCC_CFGR_PLLMULL15 +#define RCC_PLLMul_16 RCC_CFGR_PLLMULL16 +#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ + ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ + ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ + ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ + ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ + ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ + ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ + ((MUL) == RCC_PLLMul_16)) +/** + * @} + */ + +/** @defgroup RCC_PREDIV1_division_factor + * @{ + */ +#define RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1 +#define RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2 +#define RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3 +#define RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4 +#define RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5 +#define RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6 +#define RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7 +#define RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8 +#define RCC_PREDIV1_Div9 RCC_CFGR2_PREDIV1_DIV9 +#define RCC_PREDIV1_Div10 RCC_CFGR2_PREDIV1_DIV10 +#define RCC_PREDIV1_Div11 RCC_CFGR2_PREDIV1_DIV11 +#define RCC_PREDIV1_Div12 RCC_CFGR2_PREDIV1_DIV12 +#define RCC_PREDIV1_Div13 RCC_CFGR2_PREDIV1_DIV13 +#define RCC_PREDIV1_Div14 RCC_CFGR2_PREDIV1_DIV14 +#define RCC_PREDIV1_Div15 RCC_CFGR2_PREDIV1_DIV15 +#define RCC_PREDIV1_Div16 RCC_CFGR2_PREDIV1_DIV16 + +#define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ + ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ + ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ + ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ + ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ + ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ + ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ + ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source + * @{ + */ + +#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI +#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE +#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL +#define RCC_SYSCLKSource_HSI48 RCC_CFGR_SW_HSI48 /*!< Only applicable for STM32F072 devices */ + +#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ + ((SOURCE) == RCC_SYSCLKSource_HSE) || \ + ((SOURCE) == RCC_SYSCLKSource_HSI48) || \ + ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source + * @{ + */ + +#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1 +#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2 +#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4 +#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8 +#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16 +#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64 +#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128 +#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256 +#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512 +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ + ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ + ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ + ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ + ((HCLK) == RCC_SYSCLK_Div512)) +/** + * @} + */ + +/** @defgroup RCC_APB_Clock_Source + * @{ + */ + +#define RCC_HCLK_Div1 RCC_CFGR_PPRE_DIV1 +#define RCC_HCLK_Div2 RCC_CFGR_PPRE_DIV2 +#define RCC_HCLK_Div4 RCC_CFGR_PPRE_DIV4 +#define RCC_HCLK_Div8 RCC_CFGR_PPRE_DIV8 +#define RCC_HCLK_Div16 RCC_CFGR_PPRE_DIV16 +#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ + ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ + ((PCLK) == RCC_HCLK_Div16)) +/** + * @} + */ + +/** @defgroup RCC_ADC_clock_source + * @{ + */ +/* These defines are obsolete and kept for legacy purpose only. +Proper ADC clock selection is done within ADC driver by mean of the ADC_ClockModeConfig() function */ +#define RCC_ADCCLK_HSI14 ((uint32_t)0x00000000) +#define RCC_ADCCLK_PCLK_Div2 ((uint32_t)0x01000000) +#define RCC_ADCCLK_PCLK_Div4 ((uint32_t)0x01004000) + +#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADCCLK_HSI14) || ((ADCCLK) == RCC_ADCCLK_PCLK_Div2) || \ + ((ADCCLK) == RCC_ADCCLK_PCLK_Div4)) + +/** + * @} + */ + +/** @defgroup RCC_CEC_clock_source + * @{ + */ + +#define RCC_CECCLK_HSI_Div244 ((uint32_t)0x00000000) +#define RCC_CECCLK_LSE RCC_CFGR3_CECSW + +#define IS_RCC_CECCLK(CECCLK) (((CECCLK) == RCC_CECCLK_HSI_Div244) || ((CECCLK) == RCC_CECCLK_LSE)) + +/** + * @} + */ + +/** @defgroup RCC_I2C_clock_source + * @{ + */ + +#define RCC_I2C1CLK_HSI ((uint32_t)0x00000000) +#define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW + +#define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK)) + +/** + * @} + */ + +/** @defgroup RCC_USB_clock_source + * @brief Applicable only for STM32F072 devices + * @{ + */ + +#define RCC_USBCLK_HSI48 ((uint32_t)0x00000000) +#define RCC_USBCLK_PLLCLK RCC_CFGR3_USBSW + +#define IS_RCC_USBCLK(USBCLK) (((USBCLK) == RCC_USBCLK_HSI48) || ((USBCLK) == RCC_USBCLK_PLLCLK)) + +/** + * @} + */ + +/** @defgroup RCC_USART_clock_source + * @{ + */ + +#define RCC_USART1CLK_PCLK ((uint32_t)0x10000000) +#define RCC_USART1CLK_SYSCLK ((uint32_t)0x10000001) +#define RCC_USART1CLK_LSE ((uint32_t)0x10000002) +#define RCC_USART1CLK_HSI ((uint32_t)0x10000003) + +#define RCC_USART2CLK_PCLK ((uint32_t)0x20000000) /*!< Only applicable for STM32F072 and STM32F091 devices */ +#define RCC_USART2CLK_SYSCLK ((uint32_t)0x20010000) /*!< Only applicable for STM32F072 and STM32F091 devices */ +#define RCC_USART2CLK_LSE ((uint32_t)0x20020000) /*!< Only applicable for STM32F072 and STM32F091 devices */ +#define RCC_USART2CLK_HSI ((uint32_t)0x20030000) /*!< Only applicable for STM32F072 and STM32F091 devices */ + +#define RCC_USART3CLK_PCLK ((uint32_t)0x30000000) /*!< Only applicable for STM32F091 devices */ +#define RCC_USART3CLK_SYSCLK ((uint32_t)0x30040000) /*!< Only applicable for STM32F091 devices */ +#define RCC_USART3CLK_LSE ((uint32_t)0x30080000) /*!< Only applicable for STM32F091 devices */ +#define RCC_USART3CLK_HSI ((uint32_t)0x300C0000) /*!< Only applicable for STM32F091 devices */ + + +#define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || \ + ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \ + ((USARTCLK) == RCC_USART1CLK_LSE) || \ + ((USARTCLK) == RCC_USART1CLK_HSI) || \ + ((USARTCLK) == RCC_USART2CLK_PCLK) || \ + ((USARTCLK) == RCC_USART2CLK_SYSCLK) || \ + ((USARTCLK) == RCC_USART2CLK_LSE) || \ + ((USARTCLK) == RCC_USART2CLK_HSI)|| \ + ((USARTCLK) == RCC_USART3CLK_PCLK) || \ + ((USARTCLK) == RCC_USART3CLK_SYSCLK) || \ + ((USARTCLK) == RCC_USART3CLK_LSE) || \ + ((USARTCLK) == RCC_USART3CLK_HSI)) + +/** + * @} + */ + +/** @defgroup RCC_Interrupt_Source + * @{ + */ + +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_HSI14RDY ((uint8_t)0x20) +#define RCC_IT_HSI48RDY ((uint8_t)0x40) /*!< Only applicable for STM32F072 devices */ +#define RCC_IT_CSS ((uint8_t)0x80) + +#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) + +#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ + ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ + ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_HSI14RDY) || \ + ((IT) == RCC_IT_CSS) || ((IT) == RCC_IT_HSI48RDY)) + +#define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00) + +/** + * @} + */ + +/** @defgroup RCC_LSE_Configuration + * @{ + */ + +#define RCC_LSE_OFF ((uint32_t)0x00000000) +#define RCC_LSE_ON RCC_BDCR_LSEON +#define RCC_LSE_Bypass ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP)) +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_Bypass)) +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source + * @{ + */ + +#define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE +#define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI +#define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSE + +#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ + ((SOURCE) == RCC_RTCCLKSource_LSI) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div32)) +/** + * @} + */ + +/** @defgroup RCC_LSE_Drive_Configuration + * @{ + */ + +#define RCC_LSEDrive_Low ((uint32_t)0x00000000) +#define RCC_LSEDrive_MediumLow RCC_BDCR_LSEDRV_0 +#define RCC_LSEDrive_MediumHigh RCC_BDCR_LSEDRV_1 +#define RCC_LSEDrive_High RCC_BDCR_LSEDRV +#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \ + ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High)) +/** + * @} + */ + +/** @defgroup RCC_AHB_Peripherals + * @{ + */ + +#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN +#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN +#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN +#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN +#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN /*!< Only applicable for STM32F072 and STM32F091 devices */ +#define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN +#define RCC_AHBPeriph_TS RCC_AHBENR_TSEN +#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN +#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN +#define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN +#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN +#define RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN + +#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFE81FFA8) == 0x00) && ((PERIPH) != 0x00)) +#define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xFE81FFA8) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Peripherals + * @{ + */ + +#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN +#define RCC_APB2Periph_USART6 RCC_APB2ENR_USART6EN +#define RCC_APB2Periph_USART7 RCC_APB2ENR_USART7EN +#define RCC_APB2Periph_USART8 RCC_APB2ENR_USART8EN +#define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN +#define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1EN +#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN +#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN +#define RCC_APB2Periph_TIM15 RCC_APB2ENR_TIM15EN +#define RCC_APB2Periph_TIM16 RCC_APB2ENR_TIM16EN +#define RCC_APB2Periph_TIM17 RCC_APB2ENR_TIM17EN +#define RCC_APB2Periph_DBGMCU RCC_APB2ENR_DBGMCUEN + +#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFB8A51E) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Peripherals + * @{ + */ + +#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN /*!< Only applicable for STM32F051, STM32F072 and STM32F091 devices */ +#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN +#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN +#define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN /*!< Only applicable for STM32F072 devices */ +#define RCC_APB1Periph_TIM14 RCC_APB1ENR_TIM14EN +#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN +#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN +#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN +#define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN /*!< Only applicable for STM32F072 and STM32F091 devices */ +#define RCC_APB1Periph_USART4 RCC_APB1ENR_USART4EN /*!< Only applicable for STM32F072 and STM32F091 devices */ +#define RCC_APB1Periph_USART5 RCC_APB1ENR_USART5EN /*!< Only applicable for STM32F091 devices */ +#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN +#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN +#define RCC_APB1Periph_USB RCC_APB1ENR_USBEN /*!< Only applicable for STM32F072 and STM32F042 devices */ +#define RCC_APB1Periph_CAN RCC_APB1ENR_CANEN /*!< Only applicable for STM32F072, STM32F042 and STM32F091 devices */ +#define RCC_APB1Periph_CRS RCC_APB1ENR_CRSEN /*!< Only applicable for STM32F072, STM32F042 and STM32F091 devices */ +#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN +#define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN /*!< Only applicable for STM32F051, STM32F072 and STM32F091 devices */ +#define RCC_APB1Periph_CEC RCC_APB1ENR_CECEN /*!< Only applicable for STM32F051, STM32F042, STM32F072 and STM32F091 devices */ + +#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x8581B6CC) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup RCC_MCO_Clock_Source + * @{ + */ + +#define RCC_MCOSource_NoClock ((uint8_t)0x00) +#define RCC_MCOSource_HSI14 ((uint8_t)0x01) +#define RCC_MCOSource_LSI ((uint8_t)0x02) +#define RCC_MCOSource_LSE ((uint8_t)0x03) +#define RCC_MCOSource_SYSCLK ((uint8_t)0x04) +#define RCC_MCOSource_HSI ((uint8_t)0x05) +#define RCC_MCOSource_HSE ((uint8_t)0x06) +#define RCC_MCOSource_PLLCLK_Div2 ((uint8_t)0x07) +#define RCC_MCOSource_HSI48 ((uint8_t)0x08) /*!< Only applicable for STM32F072 devices */ +#define RCC_MCOSource_PLLCLK ((uint8_t)0x87) + +#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_HSI14) || \ + ((SOURCE) == RCC_MCOSource_SYSCLK) || ((SOURCE) == RCC_MCOSource_HSI) || \ + ((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK_Div2)|| \ + ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_HSI48) || \ + ((SOURCE) == RCC_MCOSource_PLLCLK) || ((SOURCE) == RCC_MCOSource_LSE)) +/** + * @} + */ + +/** @defgroup RCC_MCOPrescaler + * @{ + */ +#if !defined (STM32F051) +#define RCC_MCOPrescaler_1 RCC_CFGR_MCO_PRE_1 +#define RCC_MCOPrescaler_2 RCC_CFGR_MCO_PRE_2 +#define RCC_MCOPrescaler_4 RCC_CFGR_MCO_PRE_4 +#define RCC_MCOPrescaler_8 RCC_CFGR_MCO_PRE_8 +#define RCC_MCOPrescaler_16 RCC_CFGR_MCO_PRE_16 +#define RCC_MCOPrescaler_32 RCC_CFGR_MCO_PRE_32 +#define RCC_MCOPrescaler_64 RCC_CFGR_MCO_PRE_64 +#define RCC_MCOPrescaler_128 RCC_CFGR_MCO_PRE_128 + +#define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1) || \ + ((PRESCALER) == RCC_MCOPrescaler_2) || \ + ((PRESCALER) == RCC_MCOPrescaler_4) || \ + ((PRESCALER) == RCC_MCOPrescaler_8) || \ + ((PRESCALER) == RCC_MCOPrescaler_16) || \ + ((PRESCALER) == RCC_MCOPrescaler_32) || \ + ((PRESCALER) == RCC_MCOPrescaler_64) || \ + ((PRESCALER) == RCC_MCOPrescaler_128)) +#endif /* STM32F051 */ +/** + * @} + */ + +/** @defgroup RCC_Flag + * @{ + */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x01) +#define RCC_FLAG_HSERDY ((uint8_t)0x11) +#define RCC_FLAG_PLLRDY ((uint8_t)0x19) +#define RCC_FLAG_LSERDY ((uint8_t)0x21) +#define RCC_FLAG_LSIRDY ((uint8_t)0x41) +#define RCC_FLAG_V18PWRRSTF ((uint8_t)0x57) +#define RCC_FLAG_OBLRST ((uint8_t)0x59) +#define RCC_FLAG_PINRST ((uint8_t)0x5A) +#define RCC_FLAG_PORRST ((uint8_t)0x5B) +#define RCC_FLAG_SFTRST ((uint8_t)0x5C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x5D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x5E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x5F) +#define RCC_FLAG_HSI14RDY ((uint8_t)0x61) +#define RCC_FLAG_HSI48RDY ((uint8_t)0x71) /*!< Only applicable for STM32F072 devices */ + +#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \ + ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ + ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST) || \ + ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST) || \ + ((FLAG) == RCC_FLAG_HSI14RDY)|| ((FLAG) == RCC_FLAG_HSI48RDY)|| \ + ((FLAG) == RCC_FLAG_V18PWRRSTF)) + +#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) +#define IS_RCC_HSI14_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Function used to set the RCC clock configuration to the default reset state */ +void RCC_DeInit(void); + +/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ +void RCC_HSEConfig(uint8_t RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue); +void RCC_HSI14Cmd(FunctionalState NewState); +void RCC_HSI14ADCRequestCmd(FunctionalState NewState); +void RCC_LSEConfig(uint32_t RCC_LSE); +void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive); +void RCC_LSICmd(FunctionalState NewState); +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); +void RCC_PLLCmd(FunctionalState NewState); +void RCC_HSI48Cmd(FunctionalState NewState); /*!< Only applicable for STM32F072 devices */ +uint32_t RCC_GetHSI48CalibrationValue(void); /*!< Only applicable for STM32F072 devices */ +void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +#ifdef STM32F051 +void RCC_MCOConfig(uint8_t RCC_MCOSource); +#else +void RCC_MCOConfig(uint8_t RCC_MCOSource,uint32_t RCC_MCOPrescaler); +#endif /* STM32F051 */ + +/* System, AHB and APB busses clocks configuration functions ******************/ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_PCLKConfig(uint32_t RCC_HCLK); +void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK); /* This function is obsolete. + For proper ADC clock selection, refer to + ADC_ClockModeConfig() in the ADC driver */ +void RCC_CECCLKConfig(uint32_t RCC_CECCLK); +void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK); +void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK); +void RCC_USBCLKConfig(uint32_t RCC_USBCLK); /*!< Only applicable for STM32F042 and STM32F072 devices */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); + +/* Peripheral clocks configuration functions **********************************/ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); + +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); + +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0XX_RCC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_rtc.h b/system/include/stm32f0-stdperiph/stm32f0xx_rtc.h new file mode 100644 index 0000000..60aa00c --- /dev/null +++ b/system/include/stm32f0-stdperiph/stm32f0xx_rtc.h @@ -0,0 +1,807 @@ +/** + ****************************************************************************** + * @file stm32f0xx_rtc.h + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file contains all the functions prototypes for the RTC firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_RTC_H +#define __STM32F0XX_RTC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief RTC Init structures definition + */ +typedef struct +{ + uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format. + This parameter can be a value of @ref RTC_Hour_Formats */ + + uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. + This parameter must be set to a value lower than 0x7F */ + + uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. + This parameter must be set to a value lower than 0x1FFF */ +}RTC_InitTypeDef; + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour. + This parameter must be set to a value in the 0-12 range + if the RTC_HourFormat_12 is selected or 0-23 range if + the RTC_HourFormat_24 is selected. */ + + uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes. + This parameter must be set to a value in the 0-59 range. */ + + uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds. + This parameter must be set to a value in the 0-59 range. */ + + uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time. + This parameter can be a value of @ref RTC_AM_PM_Definitions */ +}RTC_TimeTypeDef; + +/** + * @brief RTC Date structure definition + */ +typedef struct +{ + uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay. + This parameter can be a value of @ref RTC_WeekDay_Definitions */ + + uint8_t RTC_Month; /*!< Specifies the RTC Date Month. + This parameter can be a value of @ref RTC_Month_Date_Definitions */ + + uint8_t RTC_Date; /*!< Specifies the RTC Date. + This parameter must be set to a value in the 1-31 range. */ + + uint8_t RTC_Year; /*!< Specifies the RTC Date Year. + This parameter must be set to a value in the 0-99 range. */ +}RTC_DateTypeDef; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct +{ + RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */ + + uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks. + This parameter can be a value of @ref RTC_AlarmMask_Definitions */ + + uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. + This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ + + uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. + This parameter must be set to a value in the 1-31 range + if the Alarm Date is selected. + This parameter can be a value of @ref RTC_WeekDay_Definitions + if the Alarm WeekDay is selected. */ +}RTC_AlarmTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RTC_Exported_Constants + * @{ + */ + + +/** @defgroup RTC_Hour_Formats + * @{ + */ +#define RTC_HourFormat_24 ((uint32_t)0x00000000) +#define RTC_HourFormat_12 ((uint32_t)0x00000040) +#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \ + ((FORMAT) == RTC_HourFormat_24)) +/** + * @} + */ + +/** @defgroup RTC_Asynchronous_Predivider + * @{ + */ +#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F) + +/** + * @} + */ + + +/** @defgroup RTC_Synchronous_Predivider + * @{ + */ +#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF) + +/** + * @} + */ + +/** @defgroup RTC_Time_Definitions + * @{ + */ +#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12)) +#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23) +#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59) +#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59) + +/** + * @} + */ + +/** @defgroup RTC_AM_PM_Definitions + * @{ + */ +#define RTC_H12_AM ((uint8_t)0x00) +#define RTC_H12_PM ((uint8_t)0x40) +#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM)) + +/** + * @} + */ + +/** @defgroup RTC_Year_Date_Definitions + * @{ + */ +#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99) + +/** + * @} + */ + +/** @defgroup RTC_Month_Date_Definitions + * @{ + */ +#define RTC_Month_January ((uint8_t)0x01) +#define RTC_Month_February ((uint8_t)0x02) +#define RTC_Month_March ((uint8_t)0x03) +#define RTC_Month_April ((uint8_t)0x04) +#define RTC_Month_May ((uint8_t)0x05) +#define RTC_Month_June ((uint8_t)0x06) +#define RTC_Month_July ((uint8_t)0x07) +#define RTC_Month_August ((uint8_t)0x08) +#define RTC_Month_September ((uint8_t)0x09) +#define RTC_Month_October ((uint8_t)0x10) +#define RTC_Month_November ((uint8_t)0x11) +#define RTC_Month_December ((uint8_t)0x12) +#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12)) +#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31)) + +/** + * @} + */ + +/** @defgroup RTC_WeekDay_Definitions + * @{ + */ + +#define RTC_Weekday_Monday ((uint8_t)0x01) +#define RTC_Weekday_Tuesday ((uint8_t)0x02) +#define RTC_Weekday_Wednesday ((uint8_t)0x03) +#define RTC_Weekday_Thursday ((uint8_t)0x04) +#define RTC_Weekday_Friday ((uint8_t)0x05) +#define RTC_Weekday_Saturday ((uint8_t)0x6) +#define RTC_Weekday_Sunday ((uint8_t)0x07) +#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ + ((WEEKDAY) == RTC_Weekday_Tuesday) || \ + ((WEEKDAY) == RTC_Weekday_Wednesday) || \ + ((WEEKDAY) == RTC_Weekday_Thursday) || \ + ((WEEKDAY) == RTC_Weekday_Friday) || \ + ((WEEKDAY) == RTC_Weekday_Saturday) || \ + ((WEEKDAY) == RTC_Weekday_Sunday)) +/** + * @} + */ + + +/** @defgroup RTC_Alarm_Definitions + * @{ + */ +#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31)) +#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ + ((WEEKDAY) == RTC_Weekday_Tuesday) || \ + ((WEEKDAY) == RTC_Weekday_Wednesday) || \ + ((WEEKDAY) == RTC_Weekday_Thursday) || \ + ((WEEKDAY) == RTC_Weekday_Friday) || \ + ((WEEKDAY) == RTC_Weekday_Saturday) || \ + ((WEEKDAY) == RTC_Weekday_Sunday)) + +/** + * @} + */ + + +/** @defgroup RTC_AlarmDateWeekDay_Definitions + * @{ + */ +#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000) +#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000) + +#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \ + ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay)) + +/** + * @} + */ + + +/** @defgroup RTC_AlarmMask_Definitions + * @{ + */ +#define RTC_AlarmMask_None ((uint32_t)0x00000000) +#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000) +#define RTC_AlarmMask_Hours ((uint32_t)0x00800000) +#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000) +#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080) +#define RTC_AlarmMask_All ((uint32_t)0x80808080) +#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) + +/** + * @} + */ + +/** @defgroup RTC_Alarms_Definitions + * @{ + */ +#define RTC_Alarm_A ((uint32_t)0x00000100) +#define IS_RTC_ALARM(ALARM) ((ALARM) == RTC_Alarm_A) +#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A)) != (uint32_t)RESET) + +/** + * @} + */ + +/** @defgroup RTC_Alarm_Sub_Seconds_Masks Definitions. + * @{ + */ +#define RTC_AlarmSubSecondMask_All ((uint8_t)0x00) /*!< All Alarm SS fields are masked. + There is no comparison on sub seconds + for Alarm */ +#define RTC_AlarmSubSecondMask_SS14_1 ((uint8_t)0x01) /*!< SS[14:1] are don't care in Alarm + comparison. Only SS[0] is compared. */ +#define RTC_AlarmSubSecondMask_SS14_2 ((uint8_t)0x02) /*!< SS[14:2] are don't care in Alarm + comparison. Only SS[1:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_3 ((uint8_t)0x03) /*!< SS[14:3] are don't care in Alarm + comparison. Only SS[2:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_4 ((uint8_t)0x04) /*!< SS[14:4] are don't care in Alarm + comparison. Only SS[3:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_5 ((uint8_t)0x05) /*!< SS[14:5] are don't care in Alarm + comparison. Only SS[4:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_6 ((uint8_t)0x06) /*!< SS[14:6] are don't care in Alarm + comparison. Only SS[5:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_7 ((uint8_t)0x07) /*!< SS[14:7] are don't care in Alarm + comparison. Only SS[6:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_8 ((uint8_t)0x08) /*!< SS[14:8] are don't care in Alarm + comparison. Only SS[7:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_9 ((uint8_t)0x09) /*!< SS[14:9] are don't care in Alarm + comparison. Only SS[8:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_10 ((uint8_t)0x0A) /*!< SS[14:10] are don't care in Alarm + comparison. Only SS[9:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_11 ((uint8_t)0x0B) /*!< SS[14:11] are don't care in Alarm + comparison. Only SS[10:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_12 ((uint8_t)0x0C) /*!< SS[14:12] are don't care in Alarm + comparison.Only SS[11:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_13 ((uint8_t)0x0D) /*!< SS[14:13] are don't care in Alarm + comparison. Only SS[12:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14 ((uint8_t)0x0E) /*!< SS[14] is don't care in Alarm + comparison.Only SS[13:0] are compared */ +#define RTC_AlarmSubSecondMask_None ((uint8_t)0x0F) /*!< SS[14:0] are compared and must match + to activate alarm. */ +#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14) || \ + ((MASK) == RTC_AlarmSubSecondMask_None)) +/** + * @} + */ + +/** @defgroup RTC_Alarm_Sub_Seconds_Value + * @{ + */ + +#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF) + +/** + * @} + */ + +/** @defgroup RTC_Wakeup_Timer_Definitions + * @brief These parameters are only available for STM32F072 devices + * @{ + */ +#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000) +#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001) +#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002) +#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003) +#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004) +#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006) +#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \ + ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \ + ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \ + ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \ + ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \ + ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits)) +#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) +/** + * @} + */ + +/** @defgroup RTC_Time_Stamp_Edges_definitions + * @{ + */ +#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000) +#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008) +#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \ + ((EDGE) == RTC_TimeStampEdge_Falling)) +/** + * @} + */ + +/** @defgroup RTC_Output_selection_Definitions + * @{ + */ +#define RTC_Output_Disable ((uint32_t)0x00000000) +#define RTC_Output_AlarmA ((uint32_t)0x00200000) +#define RTC_Output_WakeUp ((uint32_t)0x00600000) /*!< available only for STM32F072 devices */ + +#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \ + ((OUTPUT) == RTC_Output_AlarmA) || \ + ((OUTPUT) == RTC_Output_WakeUp)) + +/** + * @} + */ + +/** @defgroup RTC_Output_Polarity_Definitions + * @{ + */ +#define RTC_OutputPolarity_High ((uint32_t)0x00000000) +#define RTC_OutputPolarity_Low ((uint32_t)0x00100000) +#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \ + ((POL) == RTC_OutputPolarity_Low)) +/** + * @} + */ + + +/** @defgroup RTC_Calib_Output_selection_Definitions + * @{ + */ +#define RTC_CalibOutput_512Hz ((uint32_t)0x00000000) +#define RTC_CalibOutput_1Hz ((uint32_t)0x00080000) +#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \ + ((OUTPUT) == RTC_CalibOutput_1Hz)) +/** + * @} + */ + +/** @defgroup RTC_Smooth_calib_period_Definitions + * @{ + */ +#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation + period is 32s, else 2exp20 RTCCLK seconds */ +#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation + period is 16s, else 2exp19 RTCCLK seconds */ +#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation + period is 8s, else 2exp18 RTCCLK seconds */ +#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \ + ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \ + ((PERIOD) == RTC_SmoothCalibPeriod_8sec)) + +/** + * @} + */ + +/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions + * @{ + */ +#define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added + during a X -second window = Y - CALM[8:0]. + with Y = 512, 256, 128 when X = 32, 16, 8 */ +#define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited + during a 32-second window = CALM[8:0]. */ +#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \ + ((PLUS) == RTC_SmoothCalibPlusPulses_Reset)) + +/** + * @} + */ + +/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions + * @{ + */ +#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF) + +/** + * @} + */ + +/** @defgroup RTC_DayLightSaving_Definitions + * @{ + */ +#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000) +#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000) +#define IS_RTC_DAYLIGHT_SAVING(SAVING) (((SAVING) == RTC_DayLightSaving_SUB1H) || \ + ((SAVING) == RTC_DayLightSaving_ADD1H)) + +#define RTC_StoreOperation_Reset ((uint32_t)0x00000000) +#define RTC_StoreOperation_Set ((uint32_t)0x00040000) +#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \ + ((OPERATION) == RTC_StoreOperation_Set)) +/** + * @} + */ + +/** @defgroup RTC_Tamper_Trigger_Definitions + * @{ + */ +#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000) +#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001) +#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000) +#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001) +#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \ + ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \ + ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \ + ((TRIGGER) == RTC_TamperTrigger_HighLevel)) + +/** + * @} + */ + +/** @defgroup RTC_Tamper_Filter_Definitions + * @{ + */ +#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */ + +#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2 + consecutive samples at the active level */ +#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4 + consecutive samples at the active level */ +#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8 + consecutive samples at the active leve. */ +#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \ + ((FILTER) == RTC_TamperFilter_2Sample) || \ + ((FILTER) == RTC_TamperFilter_4Sample) || \ + ((FILTER) == RTC_TamperFilter_8Sample)) +/** + * @} + */ + +/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions + * @{ + */ +#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 32768 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x00000100) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 16384 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 8192 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 4096 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 2048 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 1024 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 512 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 256 */ +#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256)) + +/** + * @} + */ + + /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions + * @{ + */ +#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before + sampling during 1 RTCCLK cycle */ +#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before + sampling during 2 RTCCLK cycles */ +#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before + sampling during 4 RTCCLK cycles */ +#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before + sampling during 8 RTCCLK cycles */ + +#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \ + ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \ + ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \ + ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK)) +/** + * @} + */ + +/** @defgroup RTC_Tamper_Pins_Definitions + * @{ + */ +#define RTC_Tamper_1 RTC_TAFCR_TAMP1E /*!< Tamper detection enable for + input tamper 1 */ +#define RTC_Tamper_2 RTC_TAFCR_TAMP2E /*!< Tamper detection enable for + input tamper 2 */ +#define RTC_Tamper_3 RTC_TAFCR_TAMP3E /*!< Tamper detection enable for + input tamper 3, available only + for STM32F072 devices */ +#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET)) + +/** + * @} + */ + +/** @defgroup RTC_Output_Type_ALARM_OUT + * @{ + */ +#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000) +#define RTC_OutputType_PushPull ((uint32_t)0x00040000) +#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \ + ((TYPE) == RTC_OutputType_PushPull)) + +/** + * @} + */ + +/** @defgroup RTC_Add_1_Second_Parameter_Definitions + * @{ + */ +#define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000) +#define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000) +#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \ + ((SEL) == RTC_ShiftAdd1S_Set)) +/** + * @} + */ + +/** @defgroup RTC_Substract_Fraction_Of_Second_Value + * @{ + */ +#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF) + +/** + * @} + */ + +/** @defgroup RTC_Backup_Registers_Definitions + * @{ + */ + +#define RTC_BKP_DR0 ((uint32_t)0x00000000) +#define RTC_BKP_DR1 ((uint32_t)0x00000001) +#define RTC_BKP_DR2 ((uint32_t)0x00000002) +#define RTC_BKP_DR3 ((uint32_t)0x00000003) +#define RTC_BKP_DR4 ((uint32_t)0x00000004) +#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \ + ((BKP) == RTC_BKP_DR1) || \ + ((BKP) == RTC_BKP_DR2) || \ + ((BKP) == RTC_BKP_DR3) || \ + ((BKP) == RTC_BKP_DR4)) +/** + * @} + */ + +/** @defgroup RTC_Input_parameter_format_definitions + * @{ + */ +#define RTC_Format_BIN ((uint32_t)0x000000000) +#define RTC_Format_BCD ((uint32_t)0x000000001) +#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD)) + +/** + * @} + */ + +/** @defgroup RTC_Flags_Definitions + * @{ + */ +#define RTC_FLAG_RECALPF RTC_ISR_RECALPF +#define RTC_FLAG_TAMP3F RTC_ISR_TAMP3F /*!< Only available for STM32F072 devices */ +#define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F +#define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F +#define RTC_FLAG_TSOVF RTC_ISR_TSOVF +#define RTC_FLAG_TSF RTC_ISR_TSF +#define RTC_FLAG_WUTF RTC_ISR_WUTF /*!< Only available for STM32F072 devices */ +#define RTC_FLAG_ALRAF RTC_ISR_ALRAF +#define RTC_FLAG_INITF RTC_ISR_INITF +#define RTC_FLAG_RSF RTC_ISR_RSF +#define RTC_FLAG_INITS RTC_ISR_INITS +#define RTC_FLAG_SHPF RTC_ISR_SHPF +#define RTC_FLAG_WUTWF RTC_ISR_WUTWF /*!< Only available for STM32F072 devices */ +#define RTC_FLAG_ALRAWF RTC_ISR_ALRAWF + +#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \ + ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRAWF) || \ + ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \ + ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \ + ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_TAMP2F) || \ + ((FLAG) == RTC_FLAG_TAMP3F) || ((FLAG) == RTC_FLAG_RECALPF) || \ + ((FLAG) == RTC_FLAG_SHPF)) +#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF02DF) == (uint32_t)RESET)) + +/** + * @} + */ + +/** @defgroup RTC_Interrupts_Definitions + * @{ + */ +#define RTC_IT_TS ((uint32_t)0x00008000) +#define RTC_IT_WUT ((uint32_t)0x00004000) /* Available only for STM32F072 devices */ +#define RTC_IT_ALRA ((uint32_t)0x00001000) +#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */ +#define RTC_IT_TAMP1 ((uint32_t)0x00020000) +#define RTC_IT_TAMP2 ((uint32_t)0x00040000) +#define RTC_IT_TAMP3 ((uint32_t)0x00080000) /* Available only for STM32F072 devices */ + +#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF2FFB) == (uint32_t)RESET)) +#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_ALRA) || \ + ((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_WUT) || \ + ((IT) == RTC_IT_TAMP2) || ((IT) == RTC_IT_TAMP3)) + +#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF12FFF) == (uint32_t)RESET)) + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +/* Function used to set the RTC configuration to the default reset state *****/ +ErrorStatus RTC_DeInit(void); + + +/* Initialization and Configuration functions *********************************/ +ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct); +void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct); +void RTC_WriteProtectionCmd(FunctionalState NewState); +ErrorStatus RTC_EnterInitMode(void); +void RTC_ExitInitMode(void); +ErrorStatus RTC_WaitForSynchro(void); +ErrorStatus RTC_RefClockCmd(FunctionalState NewState); +void RTC_BypassShadowCmd(FunctionalState NewState); + +/* Time and Date configuration functions **************************************/ +ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); +void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct); +void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); +uint32_t RTC_GetSubSecond(void); +ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); +void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct); +void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); + +/* Alarms (Alarm A) configuration functions **********************************/ +void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); +void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct); +void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); +ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState); +void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint8_t RTC_AlarmSubSecondMask); +uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm); + +/* WakeUp Timer configuration functions ***************************************/ +void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock); /*!< available only for STM32F072 devices */ +void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter); /*!< available only for STM32F072 devices */ +uint32_t RTC_GetWakeUpCounter(void); /*!< available only for STM32F072 devices */ +ErrorStatus RTC_WakeUpCmd(FunctionalState NewState); /*!< available only for STM32F072 devices */ + +/* Daylight Saving configuration functions ************************************/ +void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation); +uint32_t RTC_GetStoreOperation(void); + +/* Output pin Configuration function ******************************************/ +void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity); + +/* Digital Calibration configuration functions ********************************/ +void RTC_CalibOutputCmd(FunctionalState NewState); +void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput); +ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, + uint32_t RTC_SmoothCalibPlusPulses, + uint32_t RTC_SmouthCalibMinusPulsesValue); + +/* TimeStamp configuration functions ******************************************/ +void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState); +void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, RTC_DateTypeDef* RTC_StampDateStruct); +uint32_t RTC_GetTimeStampSubSecond(void); + +/* Tampers configuration functions ********************************************/ +void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger); +void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState); +void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter); +void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq); +void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration); +void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState); +void RTC_TamperPullUpCmd(FunctionalState NewState); + +/* Backup Data Registers configuration functions ******************************/ +void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data); +uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR); + +/* Output Type Config configuration functions *********************************/ +void RTC_OutputTypeConfig(uint32_t RTC_OutputType); + +/* RTC_Shift_control_synchonisation_functions *********************************/ +ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS); + +/* Interrupts and flags management functions **********************************/ +void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState); +FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG); +void RTC_ClearFlag(uint32_t RTC_FLAG); +ITStatus RTC_GetITStatus(uint32_t RTC_IT); +void RTC_ClearITPendingBit(uint32_t RTC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F0XX_RTC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_spi.h b/system/include/stm32f0-stdperiph/stm32f0xx_spi.h new file mode 100644 index 0000000..edaea32 --- /dev/null +++ b/system/include/stm32f0-stdperiph/stm32f0xx_spi.h @@ -0,0 +1,588 @@ +/** + ****************************************************************************** + * @file stm32f0xx_spi.h + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file contains all the functions prototypes for the SPI + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_SPI_H +#define __STM32F0XX_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief SPI Init structure definition + */ + +typedef struct +{ + uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SPI_Mode; /*!< Specifies the SPI mode (Master/Slave). + This parameter can be a value of @ref SPI_mode */ + + uint16_t SPI_DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ +}SPI_InitTypeDef; + + +/** + * @brief I2S Init structure definition + * @note These parameters are not available for STM32F030 devices. + */ + +typedef struct +{ + uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref SPI_I2S_Mode */ + + uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref SPI_I2S_Standard */ + + uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref SPI_I2S_Data_Format */ + + uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref SPI_I2S_MCLK_Output */ + + uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref SPI_I2S_Audio_Frequency */ + + uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref SPI_I2S_Clock_Polarity */ +}I2S_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SPI_Exported_Constants + * @{ + */ + +#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ + ((PERIPH) == SPI2)) + +#define IS_SPI_1_PERIPH(PERIPH) (((PERIPH) == SPI1)) + +/** @defgroup SPI_data_direction + * @{ + */ + +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) +#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ + ((MODE) == SPI_Direction_2Lines_RxOnly) || \ + ((MODE) == SPI_Direction_1Line_Rx) || \ + ((MODE) == SPI_Direction_1Line_Tx)) +/** + * @} + */ + +/** @defgroup SPI_mode + * @{ + */ + +#define SPI_Mode_Master ((uint16_t)0x0104) +#define SPI_Mode_Slave ((uint16_t)0x0000) +#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ + ((MODE) == SPI_Mode_Slave)) +/** + * @} + */ + +/** @defgroup SPI_data_size + * @{ + */ + +#define SPI_DataSize_4b ((uint16_t)0x0300) +#define SPI_DataSize_5b ((uint16_t)0x0400) +#define SPI_DataSize_6b ((uint16_t)0x0500) +#define SPI_DataSize_7b ((uint16_t)0x0600) +#define SPI_DataSize_8b ((uint16_t)0x0700) +#define SPI_DataSize_9b ((uint16_t)0x0800) +#define SPI_DataSize_10b ((uint16_t)0x0900) +#define SPI_DataSize_11b ((uint16_t)0x0A00) +#define SPI_DataSize_12b ((uint16_t)0x0B00) +#define SPI_DataSize_13b ((uint16_t)0x0C00) +#define SPI_DataSize_14b ((uint16_t)0x0D00) +#define SPI_DataSize_15b ((uint16_t)0x0E00) +#define SPI_DataSize_16b ((uint16_t)0x0F00) +#define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \ + ((SIZE) == SPI_DataSize_5b) || \ + ((SIZE) == SPI_DataSize_6b) || \ + ((SIZE) == SPI_DataSize_7b) || \ + ((SIZE) == SPI_DataSize_8b) || \ + ((SIZE) == SPI_DataSize_9b) || \ + ((SIZE) == SPI_DataSize_10b) || \ + ((SIZE) == SPI_DataSize_11b) || \ + ((SIZE) == SPI_DataSize_12b) || \ + ((SIZE) == SPI_DataSize_13b) || \ + ((SIZE) == SPI_DataSize_14b) || \ + ((SIZE) == SPI_DataSize_15b) || \ + ((SIZE) == SPI_DataSize_16b)) +/** + * @} + */ + +/** @defgroup SPI_CRC_length + * @{ + */ + +#define SPI_CRCLength_8b ((uint16_t)0x0000) +#define SPI_CRCLength_16b SPI_CR1_CRCL +#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \ + ((LENGTH) == SPI_CRCLength_16b)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity + * @{ + */ + +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High SPI_CR1_CPOL +#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ + ((CPOL) == SPI_CPOL_High)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase + * @{ + */ + +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge SPI_CR1_CPHA +#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ + ((CPHA) == SPI_CPHA_2Edge)) +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_management + * @{ + */ + +#define SPI_NSS_Soft SPI_CR1_SSM +#define SPI_NSS_Hard ((uint16_t)0x0000) +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ + ((NSS) == SPI_NSS_Hard)) +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler + * @{ + */ + +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_256)) +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_transmission + * @{ + */ + +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB SPI_CR1_LSBFIRST +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ + ((BIT) == SPI_FirstBit_LSB)) +/** + * @} + */ + +/** @defgroup SPI_I2S_Mode + * @{ + */ + +#define I2S_Mode_SlaveTx ((uint16_t)0x0000) +#define I2S_Mode_SlaveRx ((uint16_t)0x0100) +#define I2S_Mode_MasterTx ((uint16_t)0x0200) +#define I2S_Mode_MasterRx ((uint16_t)0x0300) +#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ + ((MODE) == I2S_Mode_SlaveRx) || \ + ((MODE) == I2S_Mode_MasterTx)|| \ + ((MODE) == I2S_Mode_MasterRx)) +/** + * @} + */ + +/** @defgroup SPI_I2S_Standard + * @{ + */ + +#define I2S_Standard_Phillips ((uint16_t)0x0000) +#define I2S_Standard_MSB ((uint16_t)0x0010) +#define I2S_Standard_LSB ((uint16_t)0x0020) +#define I2S_Standard_PCMShort ((uint16_t)0x0030) +#define I2S_Standard_PCMLong ((uint16_t)0x00B0) +#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ + ((STANDARD) == I2S_Standard_MSB) || \ + ((STANDARD) == I2S_Standard_LSB) || \ + ((STANDARD) == I2S_Standard_PCMShort) || \ + ((STANDARD) == I2S_Standard_PCMLong)) +/** + * @} + */ + +/** @defgroup SPI_I2S_Data_Format + * @{ + */ + +#define I2S_DataFormat_16b ((uint16_t)0x0000) +#define I2S_DataFormat_16bextended ((uint16_t)0x0001) +#define I2S_DataFormat_24b ((uint16_t)0x0003) +#define I2S_DataFormat_32b ((uint16_t)0x0005) +#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ + ((FORMAT) == I2S_DataFormat_16bextended) || \ + ((FORMAT) == I2S_DataFormat_24b) || \ + ((FORMAT) == I2S_DataFormat_32b)) +/** + * @} + */ + +/** @defgroup SPI_I2S_MCLK_Output + * @{ + */ + +#define I2S_MCLKOutput_Enable SPI_I2SPR_MCKOE +#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) +#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ + ((OUTPUT) == I2S_MCLKOutput_Disable)) +/** + * @} + */ + +/** @defgroup SPI_I2S_Audio_Frequency + * @{ + */ + +#define I2S_AudioFreq_192k ((uint32_t)192000) +#define I2S_AudioFreq_96k ((uint32_t)96000) +#define I2S_AudioFreq_48k ((uint32_t)48000) +#define I2S_AudioFreq_44k ((uint32_t)44100) +#define I2S_AudioFreq_32k ((uint32_t)32000) +#define I2S_AudioFreq_22k ((uint32_t)22050) +#define I2S_AudioFreq_16k ((uint32_t)16000) +#define I2S_AudioFreq_11k ((uint32_t)11025) +#define I2S_AudioFreq_8k ((uint32_t)8000) +#define I2S_AudioFreq_Default ((uint32_t)2) + +#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ + ((FREQ) <= I2S_AudioFreq_192k)) || \ + ((FREQ) == I2S_AudioFreq_Default)) +/** + * @} + */ + +/** @defgroup SPI_I2S_Clock_Polarity + * @{ + */ + +#define I2S_CPOL_Low ((uint16_t)0x0000) +#define I2S_CPOL_High SPI_I2SCFGR_CKPOL +#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ + ((CPOL) == I2S_CPOL_High)) +/** + * @} + */ + +/** @defgroup SPI_FIFO_reception_threshold + * @{ + */ + +#define SPI_RxFIFOThreshold_HF ((uint16_t)0x0000) +#define SPI_RxFIFOThreshold_QF SPI_CR2_FRXTH +#define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \ + ((THRESHOLD) == SPI_RxFIFOThreshold_QF)) +/** + * @} + */ + +/** @defgroup SPI_I2S_DMA_transfer_requests + * @{ + */ + +#define SPI_I2S_DMAReq_Tx SPI_CR2_TXDMAEN +#define SPI_I2S_DMAReq_Rx SPI_CR2_RXDMAEN +#define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00)) +/** + * @} + */ + +/** @defgroup SPI_last_DMA_transfers + * @{ + */ + +#define SPI_LastDMATransfer_TxEvenRxEven ((uint16_t)0x0000) +#define SPI_LastDMATransfer_TxOddRxEven ((uint16_t)0x4000) +#define SPI_LastDMATransfer_TxEvenRxOdd ((uint16_t)0x2000) +#define SPI_LastDMATransfer_TxOddRxOdd ((uint16_t)0x6000) +#define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \ + ((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \ + ((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \ + ((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd)) +/** + * @} + */ +/** @defgroup SPI_NSS_internal_software_management + * @{ + */ + +#define SPI_NSSInternalSoft_Set SPI_CR1_SSI +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) +#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ + ((INTERNAL) == SPI_NSSInternalSoft_Reset)) +/** + * @} + */ + +/** @defgroup SPI_CRC_Transmit_Receive + * @{ + */ + +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) +#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) +/** + * @} + */ + +/** @defgroup SPI_direction_transmit_receive + * @{ + */ + +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) +#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ + ((DIRECTION) == SPI_Direction_Tx)) +/** + * @} + */ + +/** @defgroup SPI_I2S_interrupts_definition + * @{ + */ + +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) + +#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ + ((IT) == SPI_I2S_IT_RXNE) || \ + ((IT) == SPI_I2S_IT_ERR)) + +#define I2S_IT_UDR ((uint8_t)0x53) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_I2S_IT_FRE ((uint8_t)0x58) + +#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ + ((IT) == SPI_I2S_IT_OVR) || ((IT) == SPI_IT_MODF) || \ + ((IT) == SPI_I2S_IT_FRE)|| ((IT) == I2S_IT_UDR)) +/** + * @} + */ + + +/** @defgroup SPI_transmission_fifo_status_level + * @{ + */ + +#define SPI_TransmissionFIFOStatus_Empty ((uint16_t)0x0000) +#define SPI_TransmissionFIFOStatus_1QuarterFull ((uint16_t)0x0800) +#define SPI_TransmissionFIFOStatus_HalfFull ((uint16_t)0x1000) +#define SPI_TransmissionFIFOStatus_Full ((uint16_t)0x1800) + +/** + * @} + */ + +/** @defgroup SPI_reception_fifo_status_level + * @{ + */ +#define SPI_ReceptionFIFOStatus_Empty ((uint16_t)0x0000) +#define SPI_ReceptionFIFOStatus_1QuarterFull ((uint16_t)0x0200) +#define SPI_ReceptionFIFOStatus_HalfFull ((uint16_t)0x0400) +#define SPI_ReceptionFIFOStatus_Full ((uint16_t)0x0600) + +/** + * @} + */ + + +/** @defgroup SPI_I2S_flags_definition + * @{ + */ + +#define SPI_I2S_FLAG_RXNE SPI_SR_RXNE +#define SPI_I2S_FLAG_TXE SPI_SR_TXE +#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE +#define I2S_FLAG_UDR SPI_SR_UDR +#define SPI_FLAG_CRCERR SPI_SR_CRCERR +#define SPI_FLAG_MODF SPI_SR_MODF +#define SPI_I2S_FLAG_OVR SPI_SR_OVR +#define SPI_I2S_FLAG_BSY SPI_SR_BSY +#define SPI_I2S_FLAG_FRE SPI_SR_FRE + + + +#define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) +#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ + ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ + ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \ + ((FLAG) == SPI_I2S_FLAG_FRE)|| ((FLAG) == I2S_FLAG_CHSIDE)|| \ + ((FLAG) == I2S_FLAG_UDR)) +/** + * @} + */ + +/** @defgroup SPI_CRC_polynomial + * @{ + */ + +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Initialization and Configuration functions *********************************/ +void SPI_I2S_DeInit(SPI_TypeDef* SPIx); +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); /*!< Not applicable for STM32F030 devices */ +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); /*!< Not applicable for STM32F030 devices */ +void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); /*!< Not applicable for STM32F030 devices */ +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); +void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold); +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); + +/* Data transfers functions ***************************************************/ +void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data); +void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data); +uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx); +uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx); + +/* Hardware CRC Calculation functions *****************************************/ +void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength); +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_TransmitCRC(SPI_TypeDef* SPIx); +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); + +/* DMA transfers management functions *****************************************/ +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); +void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer); + +/* Interrupts and flags management functions **********************************/ +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); +uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx); +uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx); +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F0XX_SPI_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h b/system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h new file mode 100644 index 0000000..8c96414 --- /dev/null +++ b/system/include/stm32f0-stdperiph/stm32f0xx_syscfg.h @@ -0,0 +1,459 @@ +/** + ****************************************************************************** + * @file stm32f0xx_syscfg.h + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file contains all the functions prototypes for the SYSCFG firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/*!< Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_SYSCFG_H +#define __STM32F0XX_SYSCFG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/*!< Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SYSCFG + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SYSCFG_Exported_Constants + * @{ + */ + +/** @defgroup SYSCFG_EXTI_Port_Sources + * @{ + */ +#define EXTI_PortSourceGPIOA ((uint8_t)0x00) +#define EXTI_PortSourceGPIOB ((uint8_t)0x01) +#define EXTI_PortSourceGPIOC ((uint8_t)0x02) +#define EXTI_PortSourceGPIOD ((uint8_t)0x03) /*!< not available for STM32F031 devices */ +#define EXTI_PortSourceGPIOE ((uint8_t)0x04) /*!< only available for STM32F072 devices */ +#define EXTI_PortSourceGPIOF ((uint8_t)0x05) + +#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOF)) +/** + * @} + */ + +/** @defgroup SYSCFG_EXTI_Pin_sources + * @{ + */ +#define EXTI_PinSource0 ((uint8_t)0x00) +#define EXTI_PinSource1 ((uint8_t)0x01) +#define EXTI_PinSource2 ((uint8_t)0x02) +#define EXTI_PinSource3 ((uint8_t)0x03) +#define EXTI_PinSource4 ((uint8_t)0x04) +#define EXTI_PinSource5 ((uint8_t)0x05) +#define EXTI_PinSource6 ((uint8_t)0x06) +#define EXTI_PinSource7 ((uint8_t)0x07) +#define EXTI_PinSource8 ((uint8_t)0x08) +#define EXTI_PinSource9 ((uint8_t)0x09) +#define EXTI_PinSource10 ((uint8_t)0x0A) +#define EXTI_PinSource11 ((uint8_t)0x0B) +#define EXTI_PinSource12 ((uint8_t)0x0C) +#define EXTI_PinSource13 ((uint8_t)0x0D) +#define EXTI_PinSource14 ((uint8_t)0x0E) +#define EXTI_PinSource15 ((uint8_t)0x0F) + +#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \ + ((PINSOURCE) == EXTI_PinSource1) || \ + ((PINSOURCE) == EXTI_PinSource2) || \ + ((PINSOURCE) == EXTI_PinSource3) || \ + ((PINSOURCE) == EXTI_PinSource4) || \ + ((PINSOURCE) == EXTI_PinSource5) || \ + ((PINSOURCE) == EXTI_PinSource6) || \ + ((PINSOURCE) == EXTI_PinSource7) || \ + ((PINSOURCE) == EXTI_PinSource8) || \ + ((PINSOURCE) == EXTI_PinSource9) || \ + ((PINSOURCE) == EXTI_PinSource10) || \ + ((PINSOURCE) == EXTI_PinSource11) || \ + ((PINSOURCE) == EXTI_PinSource12) || \ + ((PINSOURCE) == EXTI_PinSource13) || \ + ((PINSOURCE) == EXTI_PinSource14) || \ + ((PINSOURCE) == EXTI_PinSource15)) +/** + * @} + */ + +/** @defgroup SYSCFG_Memory_Remap_Config + * @{ + */ +#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00) +#define SYSCFG_MemoryRemap_SystemMemory ((uint8_t)0x01) +#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03) + + +#define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ + ((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \ + ((REMAP) == SYSCFG_MemoryRemap_SRAM)) + +/** + * @} + */ + +/** @defgroup SYSCFG_DMA_Remap_Config + * @{ + */ +#define SYSCFG_DMARemap_TIM3 SYSCFG_CFGR1_TIM3_DMA_RMP /* Remap TIM3 DMA requests from channel4 to channel6, + available only for STM32F072 devices */ +#define SYSCFG_DMARemap_TIM2 SYSCFG_CFGR1_TIM2_DMA_RMP /* Remap TIM2 DMA requests from channel3/4 to channel7, + available only for STM32F072 devices */ +#define SYSCFG_DMARemap_TIM1 SYSCFG_CFGR1_TIM1_DMA_RMP /* Remap TIM1 DMA requests from channel2/3/4 to channel6, + available only for STM32F072 devices */ +#define SYSCFG_DMARemap_I2C1 SYSCFG_CFGR1_I2C1_DMA_RMP /* Remap I2C1 DMA requests from channel3/2 to channel7/6, + available only for STM32F072 devices */ +#define SYSCFG_DMARemap_USART3 SYSCFG_CFGR1_USART3_DMA_RMP /* Remap USART3 DMA requests from channel6/7 to channel3/2, + available only for STM32F072 devices */ +#define SYSCFG_DMARemap_USART2 SYSCFG_CFGR1_USART2_DMA_RMP /* Remap USART2 DMA requests from channel4/5 to channel6/7, + available only for STM32F072 devices */ +#define SYSCFG_DMARemap_SPI2 SYSCFG_CFGR1_SPI2_DMA_RMP /* Remap SPI2 DMA requests from channel4/5 to channel6/7, + available only for STM32F072 devices */ +#define SYSCFG_DMARemap_TIM17_2 SYSCFG_CFGR1_TIM17_DMA_RMP2 /* Remap TIM17 DMA requests from channel1/2 to channel7, + available only for STM32F072 devices */ +#define SYSCFG_DMARemap_TIM16_2 SYSCFG_CFGR1_TIM16_DMA_RMP2 /* Remap TIM16 DMA requests from channel3/4 to channel6, + available only for STM32F072 devices */ +#define SYSCFG_DMARemap_TIM17 SYSCFG_CFGR1_TIM17_DMA_RMP /* Remap TIM17 DMA requests from channel1 to channel2 */ +#define SYSCFG_DMARemap_TIM16 SYSCFG_CFGR1_TIM16_DMA_RMP /* Remap TIM16 DMA requests from channel3 to channel4 */ +#define SYSCFG_DMARemap_USART1Rx SYSCFG_CFGR1_USART1RX_DMA_RMP /* Remap USART1 Rx DMA requests from channel3 to channel5 */ +#define SYSCFG_DMARemap_USART1Tx SYSCFG_CFGR1_USART1TX_DMA_RMP /* Remap USART1 Tx DMA requests from channel2 to channel4 */ +#define SYSCFG_DMARemap_ADC1 SYSCFG_CFGR1_ADC_DMA_RMP /* Remap ADC1 DMA requests from channel1 to channel2 */ + +#define IS_SYSCFG_DMA_REMAP(REMAP) (((REMAP) == SYSCFG_DMARemap_TIM17) || \ + ((REMAP) == SYSCFG_DMARemap_TIM16) || \ + ((REMAP) == SYSCFG_DMARemap_USART1Rx) || \ + ((REMAP) == SYSCFG_DMARemap_USART1Tx) || \ + ((REMAP) == SYSCFG_CFGR1_TIM3_DMA_RMP) || \ + ((REMAP) == SYSCFG_CFGR1_TIM2_DMA_RMP) || \ + ((REMAP) == SYSCFG_CFGR1_TIM1_DMA_RMP) || \ + ((REMAP) == SYSCFG_CFGR1_I2C1_DMA_RMP) || \ + ((REMAP) == SYSCFG_CFGR1_USART3_DMA_RMP) || \ + ((REMAP) == SYSCFG_CFGR1_USART2_DMA_RMP) || \ + ((REMAP) == SYSCFG_CFGR1_SPI2_DMA_RMP) || \ + ((REMAP) == SYSCFG_CFGR1_TIM17_DMA_RMP2) || \ + ((REMAP) == SYSCFG_CFGR1_TIM16_DMA_RMP2) || \ + ((REMAP) == SYSCFG_DMARemap_ADC1)) + +/** + * @} + */ + +/** @defgroup SYSCFG_I2C_FastModePlus_Config + * @{ + */ +#define SYSCFG_I2CFastModePlus_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /* Enable Fast Mode Plus on PB6 */ +#define SYSCFG_I2CFastModePlus_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /* Enable Fast Mode Plus on PB7 */ +#define SYSCFG_I2CFastModePlus_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /* Enable Fast Mode Plus on PB8 */ +#define SYSCFG_I2CFastModePlus_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /* Enable Fast Mode Plus on PB9 */ +#define SYSCFG_I2CFastModePlus_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /* Enable Fast Mode Plus on PB10, PB11, PF6 and PF7(only for STM32F0031 and STM32F030 devices) */ +#define SYSCFG_I2CFastModePlus_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /* Enable Fast Mode Plus on I2C2 pins, available only for STM32F072 devices */ +#define SYSCFG_I2CFastModePlus_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /* Enable Fast Mode Plus on PA9 (only for STM32F031 and STM32F030 devices) */ +#define SYSCFG_I2CFastModePlus_PA10 SYSCFG_CFGR1_I2C_FMP_PA10/* Enable Fast Mode Plus on PA10(only for STM32F031 and STM32F030 devices) */ + +#define IS_SYSCFG_I2C_FMP(PIN) (((PIN) == SYSCFG_I2CFastModePlus_PB6) || \ + ((PIN) == SYSCFG_I2CFastModePlus_PB7) || \ + ((PIN) == SYSCFG_I2CFastModePlus_PB8) || \ + ((PIN) == SYSCFG_I2CFastModePlus_PB9) || \ + ((PIN) == SYSCFG_I2CFastModePlus_I2C1) || \ + ((PIN) == SYSCFG_I2CFastModePlus_I2C2) || \ + ((PIN) == SYSCFG_I2CFastModePlus_PA9) || \ + ((PIN) == SYSCFG_I2CFastModePlus_PA10)) + + +/** + * @} + */ + +/** @defgroup SYSCFG_Lock_Config + * @{ + */ +#define SYSCFG_Break_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Connects the PVD event to the Break Input of TIM1, not available for STM32F030 devices */ +#define SYSCFG_Break_SRAMParity SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Connects the SRAM_PARITY error signal to the Break Input of TIM1 */ +#define SYSCFG_Break_Lockup SYSCFG_CFGR2_LOCKUP_LOCK /*!< Connects Lockup output of CortexM0 to the break input of TIM1 */ + +#define IS_SYSCFG_LOCK_CONFIG(CONFIG) (((CONFIG) == SYSCFG_Break_PVD) || \ + ((CONFIG) == SYSCFG_Break_SRAMParity) || \ + ((CONFIG) == SYSCFG_Break_Lockup)) + +/** + * @} + */ + +/** @defgroup SYSCFG_flags_definition + * @{ + */ + +#define SYSCFG_FLAG_PE SYSCFG_CFGR2_SRAM_PE + +#define IS_SYSCFG_FLAG(FLAG) (((FLAG) == SYSCFG_FLAG_PE)) + +/** + * @} + */ + +/** @defgroup SYSCFG_ISR_WRAPPER + * @{ + */ +#define SYSCFG_ITLINE0 ((uint32_t) 0x00000000) +#define SYSCFG_ITLINE1 ((uint32_t) 0x00000001) +#define SYSCFG_ITLINE2 ((uint32_t) 0x00000002) +#define SYSCFG_ITLINE3 ((uint32_t) 0x00000003) +#define SYSCFG_ITLINE4 ((uint32_t) 0x00000004) +#define SYSCFG_ITLINE5 ((uint32_t) 0x00000005) +#define SYSCFG_ITLINE6 ((uint32_t) 0x00000006) +#define SYSCFG_ITLINE7 ((uint32_t) 0x00000007) +#define SYSCFG_ITLINE8 ((uint32_t) 0x00000008) +#define SYSCFG_ITLINE9 ((uint32_t) 0x00000009) +#define SYSCFG_ITLINE10 ((uint32_t) 0x0000000A) +#define SYSCFG_ITLINE11 ((uint32_t) 0x0000000B) +#define SYSCFG_ITLINE12 ((uint32_t) 0x0000000C) +#define SYSCFG_ITLINE13 ((uint32_t) 0x0000000D) +#define SYSCFG_ITLINE14 ((uint32_t) 0x0000000E) +#define SYSCFG_ITLINE15 ((uint32_t) 0x0000000F) +#define SYSCFG_ITLINE16 ((uint32_t) 0x00000010) +#define SYSCFG_ITLINE17 ((uint32_t) 0x00000011) +#define SYSCFG_ITLINE18 ((uint32_t) 0x00000012) +#define SYSCFG_ITLINE19 ((uint32_t) 0x00000013) +#define SYSCFG_ITLINE20 ((uint32_t) 0x00000014) +#define SYSCFG_ITLINE21 ((uint32_t) 0x00000015) +#define SYSCFG_ITLINE22 ((uint32_t) 0x00000016) +#define SYSCFG_ITLINE23 ((uint32_t) 0x00000017) +#define SYSCFG_ITLINE24 ((uint32_t) 0x00000018) +#define SYSCFG_ITLINE25 ((uint32_t) 0x00000019) +#define SYSCFG_ITLINE26 ((uint32_t) 0x0000001A) +#define SYSCFG_ITLINE27 ((uint32_t) 0x0000001B) +#define SYSCFG_ITLINE28 ((uint32_t) 0x0000001C) +#define SYSCFG_ITLINE29 ((uint32_t) 0x0000001D) +#define SYSCFG_ITLINE30 ((uint32_t) 0x0000001E) +#define SYSCFG_ITLINE31 ((uint32_t) 0x0000001F) + +#define ITLINE_EWDG ((uint32_t) ((SYSCFG_ITLINE0 << 0x18) | SYSCFG_ITLINE0_SR_EWDG)) /* EWDG Interrupt */ +#define ITLINE_PVDOUT ((uint32_t) ((SYSCFG_ITLINE1 << 0x18) | SYSCFG_ITLINE1_SR_PVDOUT)) /* Power voltage detection Interrupt */ +#define ITLINE_VDDIO2 ((uint32_t) ((SYSCFG_ITLINE1 << 0x18) | SYSCFG_ITLINE1_SR_VDDIO2)) /* VDDIO2 Interrupt */ +#define ITLINE_RTC_WAKEUP ((uint32_t) ((SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_WAKEUP)) /* RTC WAKEUP -> exti[20] Interrupt */ +#define ITLINE_RTC_TSTAMP ((uint32_t) ((SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_TSTAMP)) /* RTC Time Stamp -> exti[19] interrupt */ +#define ITLINE_RTC_ALRA ((uint32_t) ((SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_ALRA)) /* RTC Alarm -> exti[17] interrupt */ +#define ITLINE_FLASH_ITF ((uint32_t) ((SYSCFG_ITLINE3 << 0x18) | SYSCFG_ITLINE3_SR_FLASH_ITF)) /* Flash ITF Interrupt */ +#define ITLINE_CRS ((uint32_t) ((SYSCFG_ITLINE4 << 0x18) | SYSCFG_ITLINE4_SR_CRS)) /* CRS Interrupt */ +#define ITLINE_CLK_CTRL ((uint32_t) ((SYSCFG_ITLINE4 << 0x18) | SYSCFG_ITLINE4_SR_CLK_CTRL)) /* CLK Control Interrupt */ +#define ITLINE_EXTI0 ((uint32_t) ((SYSCFG_ITLINE5 << 0x18) | SYSCFG_ITLINE5_SR_EXTI0)) /* External Interrupt 0 */ +#define ITLINE_EXTI1 ((uint32_t) ((SYSCFG_ITLINE5 << 0x18) | SYSCFG_ITLINE5_SR_EXTI1)) /* External Interrupt 1 */ +#define ITLINE_EXTI2 ((uint32_t) ((SYSCFG_ITLINE6 << 0x18) | SYSCFG_ITLINE6_SR_EXTI2)) /* External Interrupt 2 */ +#define ITLINE_EXTI3 ((uint32_t) ((SYSCFG_ITLINE6 << 0x18) | SYSCFG_ITLINE6_SR_EXTI3)) /* External Interrupt 3 */ +#define ITLINE_EXTI4 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI4)) /* EXTI4 Interrupt */ +#define ITLINE_EXTI5 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI5)) /* EXTI5 Interrupt */ +#define ITLINE_EXTI6 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI6)) /* EXTI6 Interrupt */ +#define ITLINE_EXTI7 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI7)) /* EXTI7 Interrupt */ +#define ITLINE_EXTI8 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI8)) /* EXTI8 Interrupt */ +#define ITLINE_EXTI9 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI9)) /* EXTI9 Interrupt */ +#define ITLINE_EXTI10 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI10)) /* EXTI10 Interrupt */ +#define ITLINE_EXTI11 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI11)) /* EXTI11 Interrupt */ +#define ITLINE_EXTI12 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI12)) /* EXTI12 Interrupt */ +#define ITLINE_EXTI13 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI13)) /* EXTI13 Interrupt */ +#define ITLINE_EXTI14 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI14)) /* EXTI14 Interrupt */ +#define ITLINE_EXTI15 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI15)) /* EXTI15 Interrupt */ +#define ITLINE_TSC_EOA ((uint32_t) ((SYSCFG_ITLINE8 << 0x18) | SYSCFG_ITLINE8_SR_TSC_EOA)) /* Touch control EOA Interrupt */ +#define ITLINE_TSC_MCE ((uint32_t) ((SYSCFG_ITLINE8 << 0x18) | SYSCFG_ITLINE8_SR_TSC_MCE)) /* Touch control MCE Interrupt */ +#define ITLINE_DMA1_CH1 ((uint32_t) ((SYSCFG_ITLINE9 << 0x18) | SYSCFG_ITLINE9_SR_DMA1_CH1)) /* DMA1 Channel 1 Interrupt */ +#define ITLINE_DMA1_CH2 ((uint32_t) ((SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA1_CH2)) /* DMA1 Channel 2 Interrupt */ +#define ITLINE_DMA1_CH3 ((uint32_t) ((SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA1_CH3)) /* DMA1 Channel 3 Interrupt */ +#define ITLINE_DMA2_CH1 ((uint32_t) ((SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA2_CH1)) /* DMA2 Channel 1 Interrupt */ +#define ITLINE_DMA2_CH2 ((uint32_t) ((SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA2_CH2)) /* DMA2 Channel 2 Interrupt */ +#define ITLINE_DMA1_CH4 ((uint32_t) ((SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH4)) /* DMA1 Channel 4 Interrupt */ +#define ITLINE_DMA1_CH5 ((uint32_t) ((SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH5)) /* DMA1 Channel 5 Interrupt */ +#define ITLINE_DMA1_CH6 ((uint32_t) ((SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH6)) /* DMA1 Channel 6 Interrupt */ +#define ITLINE_DMA1_CH7 ((uint32_t) ((SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH7)) /* DMA1 Channel 7 Interrupt */ +#define ITLINE_DMA2_CH3 ((uint32_t) ((SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH3)) /* DMA2 Channel 3 Interrupt */ +#define ITLINE_DMA2_CH4 ((uint32_t) ((SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH4)) /* DMA2 Channel 4 Interrupt */ +#define ITLINE_DMA2_CH5 ((uint32_t) ((SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH5)) /* DMA2 Channel 5 Interrupt */ +#define ITLINE_ADC ((uint32_t) ((SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_ADC)) /* ADC Interrupt */ +#define ITLINE_COMP1 ((uint32_t) ((SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_COMP1)) /* COMP1 Interrupt -> exti[21] */ +#define ITLINE_COMP2 ((uint32_t) ((SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_COMP2)) /* COMP2 Interrupt -> exti[21] */ +#define ITLINE_TIM1_BRK ((uint32_t) ((SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_BRK)) /* TIM1 BRK Interrupt */ +#define ITLINE_TIM1_UPD ((uint32_t) ((SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_UPD)) /* TIM1 UPD Interrupt */ +#define ITLINE_TIM1_TRG ((uint32_t) ((SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_TRG)) /* TIM1 TRG Interrupt */ +#define ITLINE_TIM1_CCU ((uint32_t) ((SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_CCU)) /* TIM1 CCU Interrupt */ +#define ITLINE_TIM1_CC ((uint32_t) ((SYSCFG_ITLINE14 << 0x18) | SYSCFG_ITLINE14_SR_TIM1_CC)) /* TIM1 CC Interrupt */ +#define ITLINE_TIM2 ((uint32_t) ((SYSCFG_ITLINE15 << 0x18) | SYSCFG_ITLINE15_SR_TIM2_GLB)) /* TIM2 Interrupt */ +#define ITLINE_TIM3 ((uint32_t) ((SYSCFG_ITLINE16 << 0x18) | SYSCFG_ITLINE16_SR_TIM3_GLB)) /* TIM3 Interrupt */ +#define ITLINE_DAC ((uint32_t) ((SYSCFG_ITLINE17 << 0x18) | SYSCFG_ITLINE17_SR_DAC)) /* DAC Interrupt */ +#define ITLINE_TIM6 ((uint32_t) ((SYSCFG_ITLINE17 << 0x18) | SYSCFG_ITLINE17_SR_TIM6_GLB)) /* TIM6 Interrupt */ +#define ITLINE_TIM7 ((uint32_t) ((SYSCFG_ITLINE18 << 0x18) | SYSCFG_ITLINE18_SR_TIM7_GLB)) /* TIM7 Interrupt */ +#define ITLINE_TIM14 ((uint32_t) ((SYSCFG_ITLINE19 << 0x18) | SYSCFG_ITLINE19_SR_TIM14_GLB)) /* TIM14 Interrupt */ +#define ITLINE_TIM15 ((uint32_t) ((SYSCFG_ITLINE20 << 0x18) | SYSCFG_ITLINE20_SR_TIM15_GLB)) /* TIM15 Interrupt */ +#define ITLINE_TIM16 ((uint32_t) ((SYSCFG_ITLINE21 << 0x18) | SYSCFG_ITLINE21_SR_TIM16_GLB)) /* TIM16 Interrupt */ +#define ITLINE_TIM17 ((uint32_t) ((SYSCFG_ITLINE22 << 0x18) | SYSCFG_ITLINE22_SR_TIM17_GLB)) /* TIM17 Interrupt */ +#define ITLINE_I2C1 ((uint32_t) ((SYSCFG_ITLINE23 << 0x18) | SYSCFG_ITLINE23_SR_I2C1_GLB)) /* I2C1 Interrupt -> exti[23] */ +#define ITLINE_I2C2 ((uint32_t) ((SYSCFG_ITLINE24 << 0x18) | SYSCFG_ITLINE24_SR_I2C2_GLB)) /* I2C2 Interrupt */ +#define ITLINE_SPI1 ((uint32_t) ((SYSCFG_ITLINE25 << 0x18) | SYSCFG_ITLINE25_SR_SPI1)) /* I2C1 Interrupt -> exti[23] */ +#define ITLINE_SPI2 ((uint32_t) ((SYSCFG_ITLINE26 << 0x18) | SYSCFG_ITLINE26_SR_SPI2)) /* SPI1 Interrupt */ +#define ITLINE_USART1 ((uint32_t) ((SYSCFG_ITLINE27 << 0x18) | SYSCFG_ITLINE27_SR_USART1_GLB)) /*!< USART1 GLB Interrupt -> exti[25] */ +#define ITLINE_USART2 ((uint32_t) ((SYSCFG_ITLINE28 << 0x18) | SYSCFG_ITLINE28_SR_USART2_GLB)) /*!< USART2 GLB Interrupt -> exti[26] */ +#define ITLINE_USART3 ((uint32_t) ((SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART3_GLB)) /* USART3 Interrupt */ +#define ITLINE_USART4 ((uint32_t) ((SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART4_GLB)) /* USART4 Interrupt */ +#define ITLINE_USART5 ((uint32_t) ((SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART5_GLB)) /* USART5 Interrupt */ +#define ITLINE_USART6 ((uint32_t) ((SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART6_GLB)) /* USART6 Interrupt */ +#define ITLINE_USART7 ((uint32_t) ((SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART7_GLB)) /* USART7 Interrupt */ +#define ITLINE_USART8 ((uint32_t) ((SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART8_GLB)) /* USART8 Interrupt */ +#define ITLINE_CAN ((uint32_t) ((SYSCFG_ITLINE30 << 0x18) | SYSCFG_ITLINE30_SR_CAN)) /* CAN Interrupt */ +#define ITLINE_CEC ((uint32_t) ((SYSCFG_ITLINE30 << 0x18) | SYSCFG_ITLINE30_SR_CEC)) /* CEC Interrupt -> exti[27] */ + +#define IS_SYSCFG_ITLINE(LINE) (((LINE) == ITLINE_EWDG) || \ + ((LINE) == ITLINE_PVDOUT) || \ + ((LINE) == ITLINE_VDDIO2) || \ + ((LINE) == ITLINE_RTC_WAKEUP) || \ + ((LINE) == ITLINE_RTC_TSTAMP) || \ + ((LINE) == ITLINE_RTC_ALRA) || \ + ((LINE) == ITLINE_FLASH_ITF) || \ + ((LINE) == ITLINE_CRS) || \ + ((LINE) == ITLINE_CLK_CTRL) || \ + ((LINE) == ITLINE_EXTI0) || \ + ((LINE) == ITLINE_EXTI1) || \ + ((LINE) == ITLINE_EXTI2) || \ + ((LINE) == ITLINE_EXTI3) || \ + ((LINE) == ITLINE_EXTI4) || \ + ((LINE) == ITLINE_EXTI5) || \ + ((LINE) == ITLINE_EXTI6) || \ + ((LINE) == ITLINE_EXTI7) || \ + ((LINE) == ITLINE_EXTI8) || \ + ((LINE) == ITLINE_EXTI9) || \ + ((LINE) == ITLINE_EXTI10) || \ + ((LINE) == ITLINE_EXTI11) || \ + ((LINE) == ITLINE_EXTI12) || \ + ((LINE) == ITLINE_EXTI13) || \ + ((LINE) == ITLINE_EXTI14) || \ + ((LINE) == ITLINE_EXTI15) || \ + ((LINE) == ITLINE_TSC_EOA) || \ + ((LINE) == ITLINE_TSC_MCE) || \ + ((LINE) == ITLINE_DMA1_CH1) || \ + ((LINE) == ITLINE_DMA1_CH2) || \ + ((LINE) == ITLINE_DMA1_CH3) || \ + ((LINE) == ITLINE_DMA1_CH4) || \ + ((LINE) == ITLINE_DMA1_CH5) || \ + ((LINE) == ITLINE_DMA1_CH6) || \ + ((LINE) == ITLINE_DMA1_CH7) || \ + ((LINE) == ITLINE_DMA2_CH1) || \ + ((LINE) == ITLINE_DMA2_CH2) || \ + ((LINE) == ITLINE_DMA2_CH3) || \ + ((LINE) == ITLINE_DMA2_CH4) || \ + ((LINE) == ITLINE_DMA2_CH5) || \ + ((LINE) == ITLINE_ADC) || \ + ((LINE) == ITLINE_COMP1) || \ + ((LINE) == ITLINE_COMP2) || \ + ((LINE) == ITLINE_TIM1_BRK) || \ + ((LINE) == ITLINE_TIM1_UPD) || \ + ((LINE) == ITLINE_TIM1_TRG) || \ + ((LINE) == ITLINE_TIM1_CCU) || \ + ((LINE) == ITLINE_TIM1_CC) || \ + ((LINE) == ITLINE_TIM2) || \ + ((LINE) == ITLINE_TIM3) || \ + ((LINE) == ITLINE_DAC) || \ + ((LINE) == ITLINE_TIM6) || \ + ((LINE) == ITLINE_TIM7) || \ + ((LINE) == ITLINE_TIM14) || \ + ((LINE) == ITLINE_TIM15) || \ + ((LINE) == ITLINE_TIM16) || \ + ((LINE) == ITLINE_TIM17) || \ + ((LINE) == ITLINE_I2C1) || \ + ((LINE) == ITLINE_I2C2) || \ + ((LINE) == ITLINE_SPI1) || \ + ((LINE) == ITLINE_SPI2) || \ + ((LINE) == ITLINE_USART1) || \ + ((LINE) == ITLINE_USART2) || \ + ((LINE) == ITLINE_USART3) || \ + ((LINE) == ITLINE_USART4) || \ + ((LINE) == ITLINE_USART5) || \ + ((LINE) == ITLINE_USART6) || \ + ((LINE) == ITLINE_USART7) || \ + ((LINE) == ITLINE_USART8) || \ + ((LINE) == ITLINE_CAN) || \ + ((LINE) == ITLINE_CEC)) + +/** + * @} + */ +/** @defgroup IRDA_ENV_SEL + * @{ + */ +#define SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IRDA_ENV_SEL_0&SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* Timer16 is selected as IRDA Modulation envelope source */ +#define SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IRDA_ENV_SEL_0) /* USART1 is selected as IRDA Modulation envelope source.*/ +#define SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* USART4 is selected as IRDA Modulation envelope source.*/ + +#define IS_SYSCFG_IRDA_ENV(ENV) (((ENV) == SYSCFG_IRDA_ENV_SEL_TIM16) || \ + ((ENV) == SYSCFG_IRDA_ENV_SEL_USART1) || \ + ((ENV) == SYSCFG_IRDA_ENV_SEL_USART4)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Function used to set the SYSCFG configuration to the default reset state **/ +void SYSCFG_DeInit(void); + +/* SYSCFG configuration functions *********************************************/ +void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap); +void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState); +void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState); +void SYSCFG_IRDAEnvSelection(uint32_t SYSCFG_IRDAEnv); +void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex); +uint32_t SYSCFG_GetPendingIT(uint32_t ITSourceLine); +void SYSCFG_BreakConfig(uint32_t SYSCFG_Break); +FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag); +void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F0XX_SYSCFG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_tim.h b/system/include/stm32f0-stdperiph/stm32f0xx_tim.h new file mode 100644 index 0000000..47a509d --- /dev/null +++ b/system/include/stm32f0-stdperiph/stm32f0xx_tim.h @@ -0,0 +1,1186 @@ +/** + ****************************************************************************** + * @file stm32f0xx_tim.h + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file contains all the functions prototypes for the TIM + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_TIM_H +#define __STM32F0XX_TIM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief TIM Time Base Init structure definition + * @note This sturcture is used with all TIMx. + */ + +typedef struct +{ + uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint16_t TIM_ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1. */ +} TIM_TimeBaseInitTypeDef; + +/** + * @brief TIM Output Compare Init structure definition + */ + +typedef struct +{ + uint16_t TIM_OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_state */ + + uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_state + @note This parameter is valid only for TIM1. */ + + uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF ( or 0xFFFFFFFF + for TIM2) */ + + uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1. */ + + uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1. */ + + uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1. */ +} TIM_OCInitTypeDef; + +/** + * @brief TIM Input Capture Init structure definition + */ + +typedef struct +{ + + uint16_t TIM_Channel; /*!< Specifies the TIM channel. + This parameter can be a value of @ref TIM_Channel */ + + uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t TIM_ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitTypeDef; + +/** + * @brief TIM_BDTR structure definition + * @note This sturcture is used only with TIM1. + */ + +typedef struct +{ + + uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref TIM_Lock_level */ + + uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + + uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref TIM_Break_Polarity */ + + uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BDTRInitTypeDef; + +/** + * @brief TIM Input Capture Init structure definition + */ + +/* Exported constants --------------------------------------------------------*/ + + +/** @defgroup TIM_Exported_constants + * @{ + */ + +#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM14)|| \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST1: TIM 1 */ +#define IS_TIM_LIST1_PERIPH(PERIPH) ((PERIPH) == TIM1) + +/* LIST2: TIM 1, 15, 16 and 17 */ +#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST3: TIM 1, 2 and 3 */ +#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3)) + +/* LIST4: TIM 1, 2, 3, 14, 15, 16 and 17 */ +#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM14) || \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST5: TIM 1, 2, 3, 15, 16 and 17 */ +#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST6: TIM 1, 2, 3 and 15 */ +#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM15)) + +/* LIST7: TIM 1, 2, 3, 6, 7 and 14 */ +#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM14)) + +/* LIST8: TIM 1, 2, 3 and 14 */ +#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM14)) + +/* LIST9: TIM 1, 2, 3, 6, 7 and 15 */ +#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM15)) + +/* LIST10: TIM 1, 2, 3, 6, 7, 15, 16 and 17 */ +#define IS_TIM_LIST10_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST1: TIM 11 */ +#define IS_TIM_LIST11_PERIPH(PERIPH) ((PERIPH) == TIM14) + + +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes + * @{ + */ + +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) +#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ + ((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2)) +#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ + ((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2) || \ + ((MODE) == TIM_ForcedAction_Active) || \ + ((MODE) == TIM_ForcedAction_InActive)) +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode + * @{ + */ + +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) +#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ + ((MODE) == TIM_OPMode_Repetitive)) +/** + * @} + */ + +/** @defgroup TIM_Channel + * @{ + */ + +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) + +#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3) || \ + ((CHANNEL) == TIM_Channel_4)) +#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3)) +#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2)) + +/** + * @} + */ + +/** @defgroup TIM_Clock_Division_CKD + * @{ + */ + +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) +#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ + ((DIV) == TIM_CKD_DIV2) || \ + ((DIV) == TIM_CKD_DIV4)) +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode + * @{ + */ + +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) +#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ + ((MODE) == TIM_CounterMode_Down) || \ + ((MODE) == TIM_CounterMode_CenterAligned1) || \ + ((MODE) == TIM_CounterMode_CenterAligned2) || \ + ((MODE) == TIM_CounterMode_CenterAligned3)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity + * @{ + */ + +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) +#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ + ((POLARITY) == TIM_OCPolarity_Low)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity + * @{ + */ + +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) +#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ + ((POLARITY) == TIM_OCNPolarity_Low)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_state + * @{ + */ + +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) +#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ + ((STATE) == TIM_OutputState_Enable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_state + * @{ + */ + +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) +#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ + ((STATE) == TIM_OutputNState_Enable)) +/** + * @} + */ + +/** @defgroup TIM_Capture_Compare_state + * @{ + */ + +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) +#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ + ((CCX) == TIM_CCx_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Capture_Compare_N_state + * @{ + */ + +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) +#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ + ((CCXN) == TIM_CCxN_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Break_Input_enable_disable + * @{ + */ + +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) +#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ + ((STATE) == TIM_Break_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Break_Polarity + * @{ + */ + +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) +#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ + ((POLARITY) == TIM_BreakPolarity_High)) +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset + * @{ + */ + +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ + ((STATE) == TIM_AutomaticOutput_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Lock_level + * @{ + */ + +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) +#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ + ((LEVEL) == TIM_LOCKLevel_1) || \ + ((LEVEL) == TIM_LOCKLevel_2) || \ + ((LEVEL) == TIM_LOCKLevel_3)) +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state + * @{ + */ + +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) +#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ + ((STATE) == TIM_OSSIState_Disable)) +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state + * @{ + */ + +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) +#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ + ((STATE) == TIM_OSSRState_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State + * @{ + */ + +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) +#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ + ((STATE) == TIM_OCIdleState_Reset)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State + * @{ + */ + +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) +#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ + ((STATE) == TIM_OCNIdleState_Reset)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity + * @{ + */ + +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) +#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ + ((POLARITY) == TIM_ICPolarity_Falling)|| \ + ((POLARITY) == TIM_ICPolarity_BothEdge)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection + * @{ + */ + +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ +#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ + ((SELECTION) == TIM_ICSelection_IndirectTI) || \ + ((SELECTION) == TIM_ICSelection_TRC)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler + * @{ + */ + +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ +#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ + ((PRESCALER) == TIM_ICPSC_DIV2) || \ + ((PRESCALER) == TIM_ICPSC_DIV4) || \ + ((PRESCALER) == TIM_ICPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_interrupt_sources + * @{ + */ + +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) +#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) + +#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ + ((IT) == TIM_IT_CC1) || \ + ((IT) == TIM_IT_CC2) || \ + ((IT) == TIM_IT_CC3) || \ + ((IT) == TIM_IT_CC4) || \ + ((IT) == TIM_IT_COM) || \ + ((IT) == TIM_IT_Trigger) || \ + ((IT) == TIM_IT_Break)) +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address + * @{ + */ + +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) +#define TIM_DMABase_OR ((uint16_t)0x0013) +#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ + ((BASE) == TIM_DMABase_CR2) || \ + ((BASE) == TIM_DMABase_SMCR) || \ + ((BASE) == TIM_DMABase_DIER) || \ + ((BASE) == TIM_DMABase_SR) || \ + ((BASE) == TIM_DMABase_EGR) || \ + ((BASE) == TIM_DMABase_CCMR1) || \ + ((BASE) == TIM_DMABase_CCMR2) || \ + ((BASE) == TIM_DMABase_CCER) || \ + ((BASE) == TIM_DMABase_CNT) || \ + ((BASE) == TIM_DMABase_PSC) || \ + ((BASE) == TIM_DMABase_ARR) || \ + ((BASE) == TIM_DMABase_RCR) || \ + ((BASE) == TIM_DMABase_CCR1) || \ + ((BASE) == TIM_DMABase_CCR2) || \ + ((BASE) == TIM_DMABase_CCR3) || \ + ((BASE) == TIM_DMABase_CCR4) || \ + ((BASE) == TIM_DMABase_BDTR) || \ + ((BASE) == TIM_DMABase_DCR) || \ + ((BASE) == TIM_DMABase_OR)) +/** + * @} + */ + + +/** @defgroup TIM_DMA_Burst_Length + * @{ + */ + +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) +#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ + ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_18Transfers)) +/** + * @} + */ + +/** @defgroup TIM_DMA_sources + * @{ + */ + +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) +#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Prescaler + * @{ + */ + +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) +#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_Internal_Trigger_Selection + * @{ + */ + +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) +#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3) || \ + ((SELECTION) == TIM_TS_TI1F_ED) || \ + ((SELECTION) == TIM_TS_TI1FP1) || \ + ((SELECTION) == TIM_TS_TI2FP2) || \ + ((SELECTION) == TIM_TS_ETRF)) +#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3)) +/** + * @} + */ + +/** @defgroup TIM_TIx_External_Clock_Source + * @{ + */ + +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) + +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Polarity + * @{ + */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) +#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ + ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) +/** + * @} + */ + +/** @defgroup TIM_Prescaler_Reload_Mode + * @{ + */ + +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) +#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ + ((RELOAD) == TIM_PSCReloadMode_Immediate)) +/** + * @} + */ + +/** @defgroup TIM_Forced_Action + * @{ + */ + +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) +#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ + ((ACTION) == TIM_ForcedAction_InActive)) +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode + * @{ + */ + +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) +#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ + ((MODE) == TIM_EncoderMode_TI2) || \ + ((MODE) == TIM_EncoderMode_TI12)) +/** + * @} + */ + + +/** @defgroup TIM_Event_Source + * @{ + */ + +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) +#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @defgroup TIM_Update_Source + * @{ + */ + +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ +#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ + ((SOURCE) == TIM_UpdateSource_Regular)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Preload_State + * @{ + */ + +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) +#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ + ((STATE) == TIM_OCPreload_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Fast_State + * @{ + */ + +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) +#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ + ((STATE) == TIM_OCFast_Disable)) + +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Clear_State + * @{ + */ + +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) +#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ + ((STATE) == TIM_OCClear_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Trigger_Output_Source + * @{ + */ + +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) +#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ + ((SOURCE) == TIM_TRGOSource_Enable) || \ + ((SOURCE) == TIM_TRGOSource_Update) || \ + ((SOURCE) == TIM_TRGOSource_OC1) || \ + ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC4Ref)) +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode + * @{ + */ + +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) +#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ + ((MODE) == TIM_SlaveMode_Gated) || \ + ((MODE) == TIM_SlaveMode_Trigger) || \ + ((MODE) == TIM_SlaveMode_External1)) +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode + * @{ + */ + +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) +#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ + ((STATE) == TIM_MasterSlaveMode_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Flags + * @{ + */ + +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) +#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ + ((FLAG) == TIM_FLAG_CC1) || \ + ((FLAG) == TIM_FLAG_CC2) || \ + ((FLAG) == TIM_FLAG_CC3) || \ + ((FLAG) == TIM_FLAG_CC4) || \ + ((FLAG) == TIM_FLAG_COM) || \ + ((FLAG) == TIM_FLAG_Trigger) || \ + ((FLAG) == TIM_FLAG_Break) || \ + ((FLAG) == TIM_FLAG_CC1OF) || \ + ((FLAG) == TIM_FLAG_CC2OF) || \ + ((FLAG) == TIM_FLAG_CC3OF) || \ + ((FLAG) == TIM_FLAG_CC4OF)) + + +#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) +/** + * @} + */ + + +/** @defgroup TIM_Input_Capture_Filer_Value + * @{ + */ + +#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Filter + * @{ + */ + +#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_OCReferenceClear + * @{ + */ +#define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008) +#define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000) +#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \ + ((SOURCE) == TIM_OCReferenceClear_OCREFCLR)) + +/** + * @} + */ +/** @defgroup TIM_Remap + * @{ + */ +#define TIM14_GPIO ((uint16_t)0x0000) +#define TIM14_RTC_CLK ((uint16_t)0x0001) +#define TIM14_HSEDiv32 ((uint16_t)0x0002) +#define TIM14_MCO ((uint16_t)0x0003) + +#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM14_GPIO)|| \ + ((TIM_REMAP) == TIM14_RTC_CLK) || \ + ((TIM_REMAP) == TIM14_HSEDiv32) || \ + ((TIM_REMAP) == TIM14_MCO)) +/** + * @} + */ + +/** @defgroup TIM_Legacy + * @{ + */ + +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* TimeBase management ********************************************************/ +void TIM_DeInit(TIM_TypeDef* TIMx); +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); +void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter); +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload); +uint32_t TIM_GetCounter(TIM_TypeDef* TIMx); +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Advanced-control timers (TIM1) specific features*******************/ +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Output Compare management **************************************************/ +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1); +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2); +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3); +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4); +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear); +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Input Capture management ***************************************************/ +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx); +uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx); +uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx); +uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx); +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); + +/* Interrupts, DMA and flags management ***************************************/ +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Clocks management **********************************************************/ +void TIM_InternalClockConfig(TIM_TypeDef* TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); + + +/* Synchronization management *************************************************/ +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); + +/* Specific interface management **********************************************/ +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Specific remapping management **********************************************/ +void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap); + + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F0XX_TIM_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_usart.h b/system/include/stm32f0-stdperiph/stm32f0xx_usart.h new file mode 100644 index 0000000..2e73252 --- /dev/null +++ b/system/include/stm32f0-stdperiph/stm32f0xx_usart.h @@ -0,0 +1,604 @@ +/** + ****************************************************************************** + * @file stm32f0xx_usart.h + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file contains all the functions prototypes for the USART + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_USART_H +#define __STM32F0XX_USART_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup USART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + + + +/** + * @brief USART Init Structure definition + */ + +typedef struct +{ + uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) + - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */ + + uint32_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint32_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint32_t USART_Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint32_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control*/ +} USART_InitTypeDef; + +/** + * @brief USART Clock Init Structure definition + */ + +typedef struct +{ + uint32_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_Clock */ + + uint32_t USART_CPOL; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint32_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint32_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup USART_Exported_Constants + * @{ + */ + +#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3) || \ + ((PERIPH) == USART4) || \ + ((PERIPH) == USART5) || \ + ((PERIPH) == USART6) || \ + ((PERIPH) == USART7) || \ + ((PERIPH) == USART8)) + +#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3)) + +/** @defgroup USART_Word_Length + * @{ + */ + +#define USART_WordLength_8b ((uint32_t)0x00000000) +#define USART_WordLength_9b USART_CR1_M /* should be ((uint32_t)0x00001000) */ +#define USART_WordLength_7b ((uint32_t)0x10001000) /*!< only available for STM32F072 and STM32F030 devices */ +#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ + ((LENGTH) == USART_WordLength_9b) || \ + ((LENGTH) == USART_WordLength_7b)) +/** + * @} + */ + +/** @defgroup USART_Stop_Bits + * @{ + */ + +#define USART_StopBits_1 ((uint32_t)0x00000000) +#define USART_StopBits_2 USART_CR2_STOP_1 +#define USART_StopBits_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) +#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ + ((STOPBITS) == USART_StopBits_2) || \ + ((STOPBITS) == USART_StopBits_1_5)) +/** + * @} + */ + +/** @defgroup USART_Parity + * @{ + */ + +#define USART_Parity_No ((uint32_t)0x00000000) +#define USART_Parity_Even USART_CR1_PCE +#define USART_Parity_Odd (USART_CR1_PCE | USART_CR1_PS) +#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ + ((PARITY) == USART_Parity_Even) || \ + ((PARITY) == USART_Parity_Odd)) +/** + * @} + */ + +/** @defgroup USART_Mode + * @{ + */ + +#define USART_Mode_Rx USART_CR1_RE +#define USART_Mode_Tx USART_CR1_TE +#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFFFFFF3) == 0x00) && \ + ((MODE) != (uint32_t)0x00)) +/** + * @} + */ + +/** @defgroup USART_Hardware_Flow_Control + * @{ + */ + +#define USART_HardwareFlowControl_None ((uint32_t)0x00000000) +#define USART_HardwareFlowControl_RTS USART_CR3_RTSE +#define USART_HardwareFlowControl_CTS USART_CR3_CTSE +#define USART_HardwareFlowControl_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) +#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ + (((CONTROL) == USART_HardwareFlowControl_None) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS) || \ + ((CONTROL) == USART_HardwareFlowControl_CTS) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) +/** + * @} + */ + +/** @defgroup USART_Clock + * @{ + */ + +#define USART_Clock_Disable ((uint32_t)0x00000000) +#define USART_Clock_Enable USART_CR2_CLKEN +#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ + ((CLOCK) == USART_Clock_Enable)) +/** + * @} + */ + +/** @defgroup USART_Clock_Polarity + * @{ + */ + +#define USART_CPOL_Low ((uint32_t)0x00000000) +#define USART_CPOL_High USART_CR2_CPOL +#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) + +/** + * @} + */ + +/** @defgroup USART_Clock_Phase + * @{ + */ + +#define USART_CPHA_1Edge ((uint32_t)0x00000000) +#define USART_CPHA_2Edge USART_CR2_CPHA +#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) + +/** + * @} + */ + +/** @defgroup USART_Last_Bit + * @{ + */ + +#define USART_LastBit_Disable ((uint32_t)0x00000000) +#define USART_LastBit_Enable USART_CR2_LBCL +#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ + ((LASTBIT) == USART_LastBit_Enable)) +/** + * @} + */ + +/** @defgroup USART_DMA_Requests + * @{ + */ + +#define USART_DMAReq_Tx USART_CR3_DMAT +#define USART_DMAReq_Rx USART_CR3_DMAR +#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint32_t)0xFFFFFF3F) == 0x00) && \ + ((DMAREQ) != (uint32_t)0x00)) + +/** + * @} + */ + +/** @defgroup USART_DMA_Recception_Error + * @{ + */ + +#define USART_DMAOnError_Enable ((uint32_t)0x00000000) +#define USART_DMAOnError_Disable USART_CR3_DDRE +#define IS_USART_DMAONERROR(DMAERROR) (((DMAERROR) == USART_DMAOnError_Disable)|| \ + ((DMAERROR) == USART_DMAOnError_Enable)) +/** + * @} + */ + +/** @defgroup USART_MuteMode_WakeUp_methods + * @{ + */ + +#define USART_WakeUp_IdleLine ((uint32_t)0x00000000) +#define USART_WakeUp_AddressMark USART_CR1_WAKE +#define IS_USART_MUTEMODE_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ + ((WAKEUP) == USART_WakeUp_AddressMark)) +/** + * @} + */ + +/** @defgroup USART_Address_Detection + * @{ + */ + +#define USART_AddressLength_4b ((uint32_t)0x00000000) +#define USART_AddressLength_7b USART_CR2_ADDM7 +#define IS_USART_ADDRESS_DETECTION(ADDRESS) (((ADDRESS) == USART_AddressLength_4b) || \ + ((ADDRESS) == USART_AddressLength_7b)) +/** + * @} + */ + +/** @defgroup USART_StopMode_WakeUp_methods + * @note These parameters are only available for STM32F051 and STM32F072 devices + * @{ + */ + +#define USART_WakeUpSource_AddressMatch ((uint32_t)0x00000000) +#define USART_WakeUpSource_StartBit USART_CR3_WUS_1 +#define USART_WakeUpSource_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) +#define IS_USART_STOPMODE_WAKEUPSOURCE(SOURCE) (((SOURCE) == USART_WakeUpSource_AddressMatch) || \ + ((SOURCE) == USART_WakeUpSource_StartBit) || \ + ((SOURCE) == USART_WakeUpSource_RXNE)) +/** + * @} + */ + +/** @defgroup USART_LIN_Break_Detection_Length + * @{ + */ + +#define USART_LINBreakDetectLength_10b ((uint32_t)0x00000000) +#define USART_LINBreakDetectLength_11b USART_CR2_LBDL +#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ + (((LENGTH) == USART_LINBreakDetectLength_10b) || \ + ((LENGTH) == USART_LINBreakDetectLength_11b)) +/** + * @} + */ + +/** @defgroup USART_IrDA_Low_Power + * @{ + */ + +#define USART_IrDAMode_LowPower USART_CR3_IRLP +#define USART_IrDAMode_Normal ((uint32_t)0x00000000) +#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ + ((MODE) == USART_IrDAMode_Normal)) +/** + * @} + */ + +/** @defgroup USART_DE_Polarity + * @{ + */ + +#define USART_DEPolarity_High ((uint32_t)0x00000000) +#define USART_DEPolarity_Low USART_CR3_DEP +#define IS_USART_DE_POLARITY(POLARITY) (((POLARITY) == USART_DEPolarity_Low) || \ + ((POLARITY) == USART_DEPolarity_High)) +/** + * @} + */ + +/** @defgroup USART_Inversion_Pins + * @{ + */ + +#define USART_InvPin_Tx USART_CR2_TXINV +#define USART_InvPin_Rx USART_CR2_RXINV +#define IS_USART_INVERSTION_PIN(PIN) ((((PIN) & (uint32_t)0xFFFCFFFF) == 0x00) && \ + ((PIN) != (uint32_t)0x00)) + +/** + * @} + */ + +/** @defgroup USART_AutoBaudRate_Mode + * @{ + */ + +#define USART_AutoBaudRate_StartBit ((uint32_t)0x00000000) +#define USART_AutoBaudRate_FallingEdge USART_CR2_ABRMODE_0 +#define IS_USART_AUTOBAUDRATE_MODE(MODE) (((MODE) == USART_AutoBaudRate_StartBit) || \ + ((MODE) == USART_AutoBaudRate_FallingEdge)) +/** + * @} + */ + +/** @defgroup USART_OVR_DETECTION + * @{ + */ + +#define USART_OVRDetection_Enable ((uint32_t)0x00000000) +#define USART_OVRDetection_Disable USART_CR3_OVRDIS +#define IS_USART_OVRDETECTION(OVR) (((OVR) == USART_OVRDetection_Enable)|| \ + ((OVR) == USART_OVRDetection_Disable)) +/** + * @} + */ +/** @defgroup USART_Request + * @{ + */ + +#define USART_Request_ABRRQ USART_RQR_ABRRQ +#define USART_Request_SBKRQ USART_RQR_SBKRQ +#define USART_Request_MMRQ USART_RQR_MMRQ +#define USART_Request_RXFRQ USART_RQR_RXFRQ +#define USART_Request_TXFRQ USART_RQR_TXFRQ + +#define IS_USART_REQUEST(REQUEST) (((REQUEST) == USART_Request_TXFRQ) || \ + ((REQUEST) == USART_Request_RXFRQ) || \ + ((REQUEST) == USART_Request_MMRQ) || \ + ((REQUEST) == USART_Request_SBKRQ) || \ + ((REQUEST) == USART_Request_ABRRQ)) +/** + * @} + */ + +/** @defgroup USART_Flags + * @{ + */ +#define USART_FLAG_REACK USART_ISR_REACK +#define USART_FLAG_TEACK USART_ISR_TEACK +#define USART_FLAG_WU USART_ISR_WUF /*!< Not available for STM32F030 devices */ +#define USART_FLAG_RWU USART_ISR_RWU /*!< Not available for STM32F030 devices */ +#define USART_FLAG_SBK USART_ISR_SBKF +#define USART_FLAG_CM USART_ISR_CMF +#define USART_FLAG_BUSY USART_ISR_BUSY +#define USART_FLAG_ABRF USART_ISR_ABRF +#define USART_FLAG_ABRE USART_ISR_ABRE +#define USART_FLAG_EOB USART_ISR_EOBF /*!< Not available for STM32F030 devices */ +#define USART_FLAG_RTO USART_ISR_RTOF +#define USART_FLAG_nCTSS USART_ISR_CTS +#define USART_FLAG_CTS USART_ISR_CTSIF +#define USART_FLAG_LBD USART_ISR_LBD /*!< Not available for STM32F030 devices */ +#define USART_FLAG_TXE USART_ISR_TXE +#define USART_FLAG_TC USART_ISR_TC +#define USART_FLAG_RXNE USART_ISR_RXNE +#define USART_FLAG_IDLE USART_ISR_IDLE +#define USART_FLAG_ORE USART_ISR_ORE +#define USART_FLAG_NE USART_ISR_NE +#define USART_FLAG_FE USART_ISR_FE +#define USART_FLAG_PE USART_ISR_PE +#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ + ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ + ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ + ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ + ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \ + ((FLAG) == USART_FLAG_nCTSS) || ((FLAG) == USART_FLAG_RTO) || \ + ((FLAG) == USART_FLAG_EOB) || ((FLAG) == USART_FLAG_ABRE) || \ + ((FLAG) == USART_FLAG_ABRF) || ((FLAG) == USART_FLAG_BUSY) || \ + ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_SBK) || \ + ((FLAG) == USART_FLAG_RWU) || ((FLAG) == USART_FLAG_WU) || \ + ((FLAG) == USART_FLAG_TEACK)|| ((FLAG) == USART_FLAG_REACK)) + +#define IS_USART_CLEAR_FLAG(FLAG) (((FLAG) == USART_FLAG_WU) || ((FLAG) == USART_FLAG_TC) || \ + ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_ORE) || \ + ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \ + ((FLAG) == USART_FLAG_LBD) || ((FLAG) == USART_FLAG_CTS) || \ + ((FLAG) == USART_FLAG_RTO) || ((FLAG) == USART_FLAG_EOB) || \ + ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_PE)) +/** + * @} + */ + +/** @defgroup USART_Interrupt_definition + * @brief USART Interrupt definition + * USART_IT possible values + * Elements values convention: 0xZZZZYYXX + * XX: Position of the corresponding Interrupt + * YY: Register index + * ZZZZ: Flag position + * @{ + */ + +#define USART_IT_WU ((uint32_t)0x00140316) /*!< Not available for STM32F030 devices */ +#define USART_IT_CM ((uint32_t)0x0011010E) +#define USART_IT_EOB ((uint32_t)0x000C011B) /*!< Not available for STM32F030 devices */ +#define USART_IT_RTO ((uint32_t)0x000B011A) +#define USART_IT_PE ((uint32_t)0x00000108) +#define USART_IT_TXE ((uint32_t)0x00070107) +#define USART_IT_TC ((uint32_t)0x00060106) +#define USART_IT_RXNE ((uint32_t)0x00050105) +#define USART_IT_IDLE ((uint32_t)0x00040104) +#define USART_IT_LBD ((uint32_t)0x00080206) /*!< Not available for STM32F030 devices */ +#define USART_IT_CTS ((uint32_t)0x0009030A) +#define USART_IT_ERR ((uint32_t)0x00000300) +#define USART_IT_ORE ((uint32_t)0x00030300) +#define USART_IT_NE ((uint32_t)0x00020300) +#define USART_IT_FE ((uint32_t)0x00010300) + +#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ + ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ + ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR) || \ + ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \ + ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU)) + +#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ + ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ + ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ + ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE) || \ + ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \ + ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU)) + +#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_PE) || \ + ((IT) == USART_IT_FE) || ((IT) == USART_IT_NE) || \ + ((IT) == USART_IT_ORE) || ((IT) == USART_IT_IDLE) || \ + ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || \ + ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \ + ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU)) +/** + * @} + */ + +/** @defgroup USART_Global_definition + * @{ + */ + +#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x005B8D81)) +#define IS_USART_DE_ASSERTION_DEASSERTION_TIME(TIME) ((TIME) <= 0x1F) +#define IS_USART_AUTO_RETRY_COUNTER(COUNTER) ((COUNTER) <= 0x7) +#define IS_USART_TIMEOUT(TIMEOUT) ((TIMEOUT) <= 0x00FFFFFF) +#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Initialization and Configuration functions *********************************/ +void USART_DeInit(USART_TypeDef* USARTx); +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); +void USART_StructInit(USART_InitTypeDef* USART_InitStruct); +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState); +void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); /* Not available for STM32F030 devices */ +void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState); +void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut); + +/* STOP Mode functions ********************************************************/ +void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource); /* Not available for STM32F030 devices */ + +/* AutoBaudRate functions *****************************************************/ +void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate); + +/* Data transfers functions ***************************************************/ +void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_TypeDef* USARTx); + +/* Multi-Processor Communication functions ************************************/ +void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); +void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp); +void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength); + +/* LIN mode functions *********************************************************/ +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength); /* Not available for STM32F030 devices */ +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); /* Not available for STM32F030 devices */ + +/* Half-duplex mode function **************************************************/ +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); + +/* Smartcard mode functions ***************************************************/ +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); /* Not available for STM32F030 devices */ +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); /* Not available for STM32F030 devices */ +void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); /* Not available for STM32F030 devices */ +void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount); /* Not available for STM32F030 devices */ +void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength); /* Not available for STM32F030 devices */ + +/* IrDA mode functions ********************************************************/ +void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode); /* Not available for STM32F030 devices */ +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); /* Not available for STM32F030 devices */ + +/* RS485 mode functions *******************************************************/ +void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity); +void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime); +void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime); + +/* DMA transfers management functions *****************************************/ +void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState); +void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError); + +/* Interrupts and flags management functions **********************************/ +void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState); +void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState); +void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection); +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG); +void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT); +void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0XX_USART_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h b/system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h new file mode 100644 index 0000000..d32d006 --- /dev/null +++ b/system/include/stm32f0-stdperiph/stm32f0xx_wwdg.h @@ -0,0 +1,109 @@ +/** + ****************************************************************************** + * @file stm32f0xx_wwdg.h + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file contains all the functions prototypes for the WWDG + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_WWDG_H +#define __STM32F0XX_WWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup WWDG + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup WWDG_Exported_Constants + * @{ + */ + +/** @defgroup WWDG_Prescaler + * @{ + */ + +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) +#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ + ((PRESCALER) == WWDG_Prescaler_2) || \ + ((PRESCALER) == WWDG_Prescaler_4) || \ + ((PRESCALER) == WWDG_Prescaler_8)) +#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) +#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +/* Function used to set the WWDG configuration to the default reset state ****/ +void WWDG_DeInit(void); + +/* Prescaler, Refresh window and Counter configuration functions **************/ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); +void WWDG_SetWindowValue(uint8_t WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(uint8_t Counter); + +/* WWDG activation functions **************************************************/ +void WWDG_Enable(uint8_t Counter); + +/* Interrupts and flags management functions **********************************/ +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0XX_WWDG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/src/cmsis/README_DEVICE.txt b/system/src/cmsis/README_DEVICE.txt new file mode 100644 index 0000000..061dbe6 --- /dev/null +++ b/system/src/cmsis/README_DEVICE.txt @@ -0,0 +1,7 @@ +The system_stm32f0xx.c file is from +STM32F0xx_StdPeriph_Lib_V1.5.0.zip, the folder: + + STM32F0xx_StdPeriph_Lib_V1.5.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates + +The vectors_stm32f0xx.c file was created to conform with +the assembly files gcc_ride7/startup_stm32f0??.s. \ No newline at end of file diff --git a/system/src/cmsis/system_stm32f0xx.c b/system/src/cmsis/system_stm32f0xx.c new file mode 100644 index 0000000..9dd7b3d --- /dev/null +++ b/system/src/cmsis/system_stm32f0xx.c @@ -0,0 +1,358 @@ +/** + ****************************************************************************** + * @file system_stm32f0xx.c + * @author MCD Application Team + * @version V1.4.0 + * @date 05-December-2014 + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F0xx devices, + * and is generated by the clock configuration tool + * STM32F0xx_Clock_Configuration_V1.0.0.xls + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f0xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz Range) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define + * in "stm32f0xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + * System Clock Configuration + *============================================================================= + * System Clock source | PLL(HSE) + *----------------------------------------------------------------------------- + * SYSCLK | 48000000 Hz + *----------------------------------------------------------------------------- + * HCLK | 48000000 Hz + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * HSE Frequency | 8000000 Hz + *----------------------------------------------------------------------------- + * PLL MUL | 6 + *----------------------------------------------------------------------------- + * VDD | 3.3 V + *----------------------------------------------------------------------------- + * Flash Latency | 1 WS + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx_system + * @{ + */ + +/** @addtogroup STM32F0xx_System_Private_Includes + * @{ + */ + +#include "stm32f0xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Defines + * @{ + */ +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Variables + * @{ + */ +uint32_t SystemCoreClock = 48000000; +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + +#if defined(STM32F051) + /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */ + RCC->CFGR &= (uint32_t)0xF8FFB80C; +#else + /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */ + RCC->CFGR &= (uint32_t)0x08FFB80C; +#endif /* STM32F051 */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ + RCC->CFGR &= (uint32_t)0xFFC0FFFF; + + /* Reset PREDIV1[3:0] bits */ + RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; + + /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFFEAC; + + /* Reset HSI14 bit */ + RCC->CR2 &= (uint32_t)0xFFFFFFFE; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + + /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */ + SetSysClock(); +} + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + break; + default: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash + * settings. + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer and set Flash Latency */ + FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1; + + /* PLL configuration = HSE * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6); + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/src/cmsis/vectors_stm32f0xx.c b/system/src/cmsis/vectors_stm32f0xx.c new file mode 100644 index 0000000..0eb5b5f --- /dev/null +++ b/system/src/cmsis/vectors_stm32f0xx.c @@ -0,0 +1,525 @@ +/* + * This file is part of the ??OS++ distribution. + * (https://github.com/micro-os-plus) + * Copyright (c) 2014 Liviu Ionescu. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +// ---------------------------------------------------------------------------- + +#include "cortexm/ExceptionHandlers.h" + +// ---------------------------------------------------------------------------- + +void __attribute__((weak)) +Default_Handler(void); + +// Forward declaration of the specific IRQ handlers. These are aliased +// to the Default_Handler, which is a 'forever' loop. When the application +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions + +void __attribute__ ((weak, alias ("Default_Handler"))) +WWDG_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +PVD_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +RTC_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +FLASH_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +RCC_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +EXTI0_1_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +EXTI2_3_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +EXTI4_15_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +TS_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +DMA1_Channel1_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +DMA1_Channel2_3_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +DMA1_Channel4_5_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +ADC1_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +TIM1_BRK_UP_TRG_COM_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +TIM1_CC_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +TIM2_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +TIM3_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +TIM6_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +TIM6_DAC_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +TIM14_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +TIM15_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +TIM16_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +TIM17_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +I2C1_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +I2C2_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +SPI1_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +SPI2_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +USART1_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +USART2_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +CEC_IRQHandler(void); + +void __attribute__ ((weak, alias ("Default_Handler"))) +ADC1_COMP_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +PVD_VDDIO2_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +VDDIO2_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +RCC_CRS_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +TSC_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +TIM7_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +USART3_4_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +USART3_6_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +USART3_8_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +CEC_CAN_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +USB_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +DMA1_Channel4_5_6_7_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler(void); +void __attribute__ ((weak, alias ("Default_Handler"))) +DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler(void); + +// ---------------------------------------------------------------------------- + +extern unsigned int _estack; + +typedef void +(* const pHandler)(void); + +// ---------------------------------------------------------------------------- + +// The vector table. +// This relies on the linker script to place at correct location in memory. + +__attribute__ ((section(".isr_vector"),used)) +pHandler g_pfnVectors[] = + { + // Core Level - CM0 + (pHandler) &_estack, // The initial stack pointer + Reset_Handler, // The reset handler + + NMI_Handler, // The NMI handler + HardFault_Handler, // The hard fault handler +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) + MemManage_Handler, // The MPU fault handler + BusFault_Handler, // The bus fault handler + UsageFault_Handler, // The usage fault handler +#else + 0, 0, 0, // Reserved +#endif + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall handler +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) + DebugMon_Handler, // Debug monitor handler +#else + 0, // Reserved +#endif + 0, // Reserved + PendSV_Handler, // The PendSV handler + SysTick_Handler, // The SysTick handler + + // ---------------------------------------------------------------------- + +#if defined(STM32F030) + + // Chip Level - STM32F030 + WWDG_IRQHandler, // + 0, // + RTC_IRQHandler, // + FLASH_IRQHandler, // + RCC_IRQHandler, // + EXTI0_1_IRQHandler, // + EXTI2_3_IRQHandler, // + EXTI4_15_IRQHandler, // + 0, // + DMA1_Channel1_IRQHandler, // + DMA1_Channel2_3_IRQHandler, // + DMA1_Channel4_5_IRQHandler, // + ADC1_IRQHandler, // + TIM1_BRK_UP_TRG_COM_IRQHandler, // + TIM1_CC_IRQHandler, // + 0, // + TIM3_IRQHandler, // + 0, // + 0, // + TIM14_IRQHandler, // + TIM15_IRQHandler, // + TIM16_IRQHandler, // + TIM17_IRQHandler, // + I2C1_IRQHandler, // + I2C2_IRQHandler, // + SPI1_IRQHandler, // + SPI2_IRQHandler, // + USART1_IRQHandler, // + USART2_IRQHandler, // + 0, // + 0, // + 0, // + +#elif defined(STM32F030xC) + + // Chip Level - STM32F030 + WWDG_IRQHandler, // + 0, // + RTC_IRQHandler, // + FLASH_IRQHandler, // + RCC_IRQHandler, // + EXTI0_1_IRQHandler, // + EXTI2_3_IRQHandler, // + EXTI4_15_IRQHandler, // + 0, // + DMA1_Channel1_IRQHandler, // + DMA1_Channel2_3_IRQHandler, // + DMA1_Channel4_5_IRQHandler, // + ADC1_IRQHandler, // + TIM1_BRK_UP_TRG_COM_IRQHandler, // + TIM1_CC_IRQHandler, // + 0, // + TIM3_IRQHandler, // + TIM6_IRQHandler, // + TIM7_IRQHandler, // + TIM14_IRQHandler, // + TIM15_IRQHandler, // + TIM16_IRQHandler, // + TIM17_IRQHandler, // + I2C1_IRQHandler, // + I2C2_IRQHandler, // + SPI1_IRQHandler, // + SPI2_IRQHandler, // + USART1_IRQHandler, // + USART2_IRQHandler, // + USART3_6_IRQHandler, // + 0, // + 0, // + +#elif defined(STM32F031) + + // Chip Level - STM32F031 (was STM32F0xx LD) + WWDG_IRQHandler, // + PVD_IRQHandler, // + RTC_IRQHandler, // + FLASH_IRQHandler, // + RCC_IRQHandler, // + EXTI0_1_IRQHandler, // + EXTI2_3_IRQHandler, // + EXTI4_15_IRQHandler, // + 0, // + DMA1_Channel1_IRQHandler, // + DMA1_Channel2_3_IRQHandler, // + DMA1_Channel4_5_IRQHandler, // + ADC1_IRQHandler, // + TIM1_BRK_UP_TRG_COM_IRQHandler, // + TIM1_CC_IRQHandler, // + TIM2_IRQHandler, // + TIM3_IRQHandler, // + 0, // + 0, // + TIM14_IRQHandler, // + 0, // + TIM16_IRQHandler, // + TIM17_IRQHandler, // + I2C1_IRQHandler, // + 0, // + SPI1_IRQHandler, // + 0, // + USART1_IRQHandler, // + 0, // + 0, // + 0, // + 0, // + +#elif defined(STM32F042) + + // Chip Level - STM32F042 (was STM32F0xx MD) + WWDG_IRQHandler, // + PVD_VDDIO2_IRQHandler, // + RTC_IRQHandler, // + FLASH_IRQHandler, // + RCC_CRS_IRQHandler, // + EXTI0_1_IRQHandler, // + EXTI2_3_IRQHandler, // + EXTI4_15_IRQHandler, // + TSC_IRQHandler, // + DMA1_Channel1_IRQHandler, // + DMA1_Channel2_3_IRQHandler, // + DMA1_Channel4_5_IRQHandler, // + ADC1_IRQHandler, // + TIM1_BRK_UP_TRG_COM_IRQHandler, // + TIM1_CC_IRQHandler, // + TIM2_IRQHandler, // + TIM3_IRQHandler, // + 0, // + 0, // + TIM14_IRQHandler, // + 0, // + TIM16_IRQHandler, // + TIM17_IRQHandler, // + I2C1_IRQHandler, // + 0, // + SPI1_IRQHandler, // + SPI2_IRQHandler, // + USART1_IRQHandler, // + USART2_IRQHandler, // + 0, // + CEC_CAN_IRQHandler, // + USB_IRQHandler, // + +#elif defined(STM32F051) + + // Chip Level - STM32F051 (was STM32F0xx MD) + WWDG_IRQHandler, // + PVD_IRQHandler, // + RTC_IRQHandler, // + FLASH_IRQHandler, // + RCC_IRQHandler, // + EXTI0_1_IRQHandler, // + EXTI2_3_IRQHandler, // + EXTI4_15_IRQHandler, // + TS_IRQHandler, // + DMA1_Channel1_IRQHandler, // + DMA1_Channel2_3_IRQHandler, // + DMA1_Channel4_5_IRQHandler, // + ADC1_COMP_IRQHandler, // + TIM1_BRK_UP_TRG_COM_IRQHandler, // + TIM1_CC_IRQHandler, // + TIM2_IRQHandler, // + TIM3_IRQHandler, // + TIM6_DAC_IRQHandler, // + 0, // + TIM14_IRQHandler, // + TIM15_IRQHandler, // + TIM16_IRQHandler, // + TIM17_IRQHandler, // + I2C1_IRQHandler, // + I2C2_IRQHandler, // + SPI1_IRQHandler, // + SPI2_IRQHandler, // + USART1_IRQHandler, // + USART2_IRQHandler, // + 0, // + CEC_IRQHandler, // + 0, // + +#elif defined (STM32F070x6) + + // Chip Level - STM32F070 + WWDG_IRQHandler, // + 0, // + RTC_IRQHandler, // + FLASH_IRQHandler, // + RCC_IRQHandler, // + EXTI0_1_IRQHandler, // + EXTI2_3_IRQHandler, // + EXTI4_15_IRQHandler, // + 0, // + DMA1_Channel1_IRQHandler, // + DMA1_Channel2_3_IRQHandler, // + DMA1_Channel4_5_IRQHandler, // + ADC1_IRQHandler, // + TIM1_BRK_UP_TRG_COM_IRQHandler, // + TIM1_CC_IRQHandler, // + 0, // + TIM3_IRQHandler, // + 0, // + 0, // + TIM14_IRQHandler, // + 0, // + TIM16_IRQHandler, // + TIM17_IRQHandler, // + I2C1_IRQHandler, // + 0, // + SPI1_IRQHandler, // + 0, // + USART1_IRQHandler, // + USART2_IRQHandler, // + 0, // + 0, // + USB_IRQHandler, // + +#elif defined (STM32F070xB) + + // Chip Level - STM32F070 + WWDG_IRQHandler, // + 0, // + RTC_IRQHandler, // + FLASH_IRQHandler, // + RCC_IRQHandler, // + EXTI0_1_IRQHandler, // + EXTI2_3_IRQHandler, // + EXTI4_15_IRQHandler, // + 0, // + DMA1_Channel1_IRQHandler, // + DMA1_Channel2_3_IRQHandler, // + DMA1_Channel4_5_IRQHandler, // + ADC1_IRQHandler, // + TIM1_BRK_UP_TRG_COM_IRQHandler, // + TIM1_CC_IRQHandler, // + 0, // + TIM3_IRQHandler, // + TIM6_DAC_IRQHandler, // + TIM7_IRQHandler, // + TIM14_IRQHandler, // + TIM15_IRQHandler, // + TIM16_IRQHandler, // + TIM17_IRQHandler, // + I2C1_IRQHandler, // + I2C2_IRQHandler, // + SPI1_IRQHandler, // + SPI2_IRQHandler, // + USART1_IRQHandler, // + USART2_IRQHandler, // + USART3_4_IRQHandler, // + 0, // + USB_IRQHandler, // + +#elif defined (STM32F072) + + // Chip Level - STM32F051 (was STM32F0xx MD) + WWDG_IRQHandler, // + PVD_VDDIO2_IRQHandler, // + RTC_IRQHandler, // + FLASH_IRQHandler, // + RCC_CRS_IRQHandler, // + EXTI0_1_IRQHandler, // + EXTI2_3_IRQHandler, // + EXTI4_15_IRQHandler, // + TSC_IRQHandler, // + DMA1_Channel1_IRQHandler, // + DMA1_Channel2_3_IRQHandler, // + DMA1_Channel4_5_6_7_IRQHandler, // + ADC1_COMP_IRQHandler, // + TIM1_BRK_UP_TRG_COM_IRQHandler, // + TIM1_CC_IRQHandler, // + TIM2_IRQHandler, // + TIM3_IRQHandler, // + TIM6_DAC_IRQHandler, // + TIM7_IRQHandler, // + TIM14_IRQHandler, // + TIM15_IRQHandler, // + TIM16_IRQHandler, // + TIM17_IRQHandler, // + I2C1_IRQHandler, // + I2C2_IRQHandler, // + SPI1_IRQHandler, // + SPI2_IRQHandler, // + USART1_IRQHandler, // + USART2_IRQHandler, // + USART3_4_IRQHandler, // + CEC_CAN_IRQHandler, // + USB_IRQHandler, // + +#elif defined (STM32F091) + + // Chip Level - STM32F091 + WWDG_IRQHandler, // + PVD_VDDIO2_IRQHandler, // + RTC_IRQHandler, // + FLASH_IRQHandler, // + RCC_CRS_IRQHandler, // + EXTI0_1_IRQHandler, // + EXTI2_3_IRQHandler, // + EXTI4_15_IRQHandler, // + TSC_IRQHandler, // + DMA1_Channel1_IRQHandler, // + DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler, // + DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler, // + ADC1_COMP_IRQHandler, // + TIM1_BRK_UP_TRG_COM_IRQHandler, // + TIM1_CC_IRQHandler, // + TIM2_IRQHandler, // + TIM3_IRQHandler, // + TIM6_DAC_IRQHandler, // + TIM7_IRQHandler, // + TIM14_IRQHandler, // + TIM15_IRQHandler, // + TIM16_IRQHandler, // + TIM17_IRQHandler, // + I2C1_IRQHandler, // + I2C2_IRQHandler, // + SPI1_IRQHandler, // + SPI2_IRQHandler, // + USART1_IRQHandler, // + USART2_IRQHandler, // + USART3_8_IRQHandler, // + CEC_CAN_IRQHandler, // + 0, // + +#else +#error "missing vectors" +#endif + + // @0x108. This is for boot in RAM mode for STM32F0xx devices. + (pHandler) 0xF108F85F + + }; + +// ---------------------------------------------------------------------------- + +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. + +void __attribute__ ((section(".after_vectors"))) +Default_Handler(void) +{ +#if defined(DEBUG) + __DEBUG_BKPT(); +#endif + while (1) + { + } +} + +// ---------------------------------------------------------------------------- diff --git a/system/src/cortexm/_initialize_hardware.c b/system/src/cortexm/_initialize_hardware.c new file mode 100644 index 0000000..90a7772 --- /dev/null +++ b/system/src/cortexm/_initialize_hardware.c @@ -0,0 +1,109 @@ +/* + * This file is part of the ??OS++ distribution. + * (https://github.com/micro-os-plus) + * Copyright (c) 2014 Liviu Ionescu. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +// ---------------------------------------------------------------------------- + +#include "cmsis_device.h" + +// ---------------------------------------------------------------------------- + +extern unsigned int __vectors_start; + +// Forward declarations. + +void +__initialize_hardware_early(void); + +void +__initialize_hardware(void); + +// ---------------------------------------------------------------------------- + +// This is the early hardware initialisation routine, it can be +// redefined in the application for more complex cases that +// require early inits (before BSS init). +// +// Called early from _start(), right before data & bss init. +// +// After Reset the Cortex-M processor is in Thread mode, +// priority is Privileged, and the Stack is set to Main. + +void +__attribute__((weak)) +__initialize_hardware_early(void) +{ + // Call the CSMSIS system initialisation routine. + SystemInit(); + +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) + // Set VTOR to the actual address, provided by the linker script. + // Override the manual, possibly wrong, SystemInit() setting. + SCB->VTOR = (uint32_t)(&__vectors_start); +#endif + + // The current version of SystemInit() leaves the value of the clock + // in a RAM variable (SystemCoreClock), which will be cleared shortly, + // so it needs to be recomputed after the RAM initialisations + // are completed. + +#if defined(OS_INCLUDE_STARTUP_INIT_FP) || (defined (__VFP_FP__) && !defined (__SOFTFP__)) + + // Normally FP init is done by SystemInit(). In case this is not done + // there, it is possible to force its inclusion by defining + // OS_INCLUDE_STARTUP_INIT_FP. + + // Enable the Cortex-M4 FPU only when -mfloat-abi=hard. + // Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C) + + // Set bits 20-23 to enable CP10 and CP11 coprocessor + SCB->CPACR |= (0xF << 20); + +#endif // (__VFP_FP__) && !(__SOFTFP__) + +#if defined(OS_DEBUG_SEMIHOSTING_FAULTS) + SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk; +#endif +} + +// This is the second hardware initialisation routine, it can be +// redefined in the application for more complex cases that +// require custom inits (before constructors), otherwise these can +// be done in main(). +// +// Called from _start(), right after data & bss init, before +// constructors. + +void +__attribute__((weak)) +__initialize_hardware(void) +{ + // Call the CSMSIS system clock routine to store the clock frequency + // in the SystemCoreClock global RAM location. + SystemCoreClockUpdate(); +} + +// ---------------------------------------------------------------------------- diff --git a/system/src/cortexm/_reset_hardware.c b/system/src/cortexm/_reset_hardware.c new file mode 100644 index 0000000..52f2e64 --- /dev/null +++ b/system/src/cortexm/_reset_hardware.c @@ -0,0 +1,59 @@ +/* + * This file is part of the ??OS++ distribution. + * (https://github.com/micro-os-plus) + * Copyright (c) 2014 Liviu Ionescu. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +// ---------------------------------------------------------------------------- + +#include "cmsis_device.h" + +// ---------------------------------------------------------------------------- + +extern void +__attribute__((noreturn)) +NVIC_SystemReset(void); + +// ---------------------------------------------------------------------------- + +// Forward declarations + +void +__reset_hardware(void); + +// ---------------------------------------------------------------------------- + +// This is the default hardware reset routine; it can be +// redefined in the application for more complex applications. +// +// Called from _exit(). + +void +__attribute__((weak,noreturn)) +__reset_hardware() +{ + NVIC_SystemReset(); +} + +// ---------------------------------------------------------------------------- diff --git a/system/src/cortexm/exception_handlers.c b/system/src/cortexm/exception_handlers.c new file mode 100644 index 0000000..e6bcf9c --- /dev/null +++ b/system/src/cortexm/exception_handlers.c @@ -0,0 +1,621 @@ +/* + * This file is part of the ??OS++ distribution. + * (https://github.com/micro-os-plus) + * Copyright (c) 2014 Liviu Ionescu. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +// ---------------------------------------------------------------------------- + +#include "cortexm/ExceptionHandlers.h" +#include "cmsis_device.h" +#include "arm/semihosting.h" +#include "diag/Trace.h" +#include + +// ---------------------------------------------------------------------------- + +extern void +__attribute__((noreturn,weak)) +_start (void); + +// ---------------------------------------------------------------------------- +// Default exception handlers. Override the ones here by defining your own +// handler routines in your application code. +// ---------------------------------------------------------------------------- + +#if defined(DEBUG) + +// The DEBUG version is not naked, but has a proper stack frame, +// to allow setting breakpoints at Reset_Handler. +void __attribute__ ((section(".after_vectors"),noreturn)) +Reset_Handler (void) +{ + _start (); +} + +#else + +// The Release version is optimised to a quick branch to _start. +void __attribute__ ((section(".after_vectors"),naked)) +Reset_Handler(void) + { + asm volatile + ( + " ldr r0,=_start \n" + " bx r0" + : + : + : + ); + } + +#endif + +void __attribute__ ((section(".after_vectors"),weak)) +NMI_Handler (void) +{ +#if defined(DEBUG) + __DEBUG_BKPT(); +#endif + while (1) + { + } +} + +// ---------------------------------------------------------------------------- + +#if defined(TRACE) + +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) + +// The values of BFAR and MMFAR stay unchanged if the BFARVALID or +// MMARVALID is set. However, if a new fault occurs during the +// execution of this fault handler, the value of the BFAR and MMFAR +// could potentially be erased. In order to ensure the fault addresses +// accessed are valid, the following procedure should be used: +// 1. Read BFAR/MMFAR. +// 2. Read CFSR to get BFARVALID or MMARVALID. If the value is 0, the +// value of BFAR or MMFAR accessed can be invalid and can be discarded. +// 3. Optionally clear BFARVALID or MMARVALID. +// (See Joseph Yiu's book). + +void +dumpExceptionStack (ExceptionStackFrame* frame, + uint32_t cfsr, uint32_t mmfar, uint32_t bfar, + uint32_t lr) +{ + trace_printf ("Stack frame:\n"); + trace_printf (" R0 = %08X\n", frame->r0); + trace_printf (" R1 = %08X\n", frame->r1); + trace_printf (" R2 = %08X\n", frame->r2); + trace_printf (" R3 = %08X\n", frame->r3); + trace_printf (" R12 = %08X\n", frame->r12); + trace_printf (" LR = %08X\n", frame->lr); + trace_printf (" PC = %08X\n", frame->pc); + trace_printf (" PSR = %08X\n", frame->psr); + trace_printf ("FSR/FAR:\n"); + trace_printf (" CFSR = %08X\n", cfsr); + trace_printf (" HFSR = %08X\n", SCB->HFSR); + trace_printf (" DFSR = %08X\n", SCB->DFSR); + trace_printf (" AFSR = %08X\n", SCB->AFSR); + + if (cfsr & (1UL << 7)) + { + trace_printf (" MMFAR = %08X\n", mmfar); + } + if (cfsr & (1UL << 15)) + { + trace_printf (" BFAR = %08X\n", bfar); + } + trace_printf ("Misc\n"); + trace_printf (" LR/EXC_RETURN= %08X\n", lr); +} + +#endif // defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) + +#if defined(__ARM_ARCH_6M__) + +void +dumpExceptionStack (ExceptionStackFrame* frame, uint32_t lr) +{ + trace_printf ("Stack frame:\n"); + trace_printf (" R0 = %08X\n", frame->r0); + trace_printf (" R1 = %08X\n", frame->r1); + trace_printf (" R2 = %08X\n", frame->r2); + trace_printf (" R3 = %08X\n", frame->r3); + trace_printf (" R12 = %08X\n", frame->r12); + trace_printf (" LR = %08X\n", frame->lr); + trace_printf (" PC = %08X\n", frame->pc); + trace_printf (" PSR = %08X\n", frame->psr); + trace_printf ("Misc\n"); + trace_printf (" LR/EXC_RETURN= %08X\n", lr); +} + +#endif // defined(__ARM_ARCH_6M__) + +#endif // defined(TRACE) + +// ---------------------------------------------------------------------------- + +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) + +#if defined(OS_USE_SEMIHOSTING) || defined(OS_USE_TRACE_SEMIHOSTING_STDOUT) || defined(OS_USE_TRACE_SEMIHOSTING_DEBUG) + +int +isSemihosting (ExceptionStackFrame* frame, uint16_t opCode); + +/** + * This function provides the minimum functionality to make a semihosting program execute even without the debugger present. + * @param frame pointer to an exception stack frame. + * @param opCode the 16-bin word of the BKPT instruction. + * @return 1 if the instruction was a valid semihosting call; 0 otherwise. + */ +int +isSemihosting (ExceptionStackFrame* frame, uint16_t opCode) +{ + uint16_t* pw = (uint16_t*) frame->pc; + if (*pw == opCode) + { + uint32_t r0 = frame->r0; +#if defined(OS_DEBUG_SEMIHOSTING_FAULTS) || defined(OS_USE_SEMIHOSTING) || defined(OS_USE_TRACE_SEMIHOSTING_STDOUT) + uint32_t r1 = frame->r1; +#endif +#if defined(OS_USE_SEMIHOSTING) || defined(OS_USE_TRACE_SEMIHOSTING_STDOUT) + uint32_t* blk = (uint32_t*) r1; +#endif + +#if defined(OS_DEBUG_SEMIHOSTING_FAULTS) + // trace_printf ("sh r0=%d\n", r0); +#endif + + switch (r0) + { + +#if defined(OS_USE_SEMIHOSTING) + + case SEMIHOSTING_SYS_CLOCK: + case SEMIHOSTING_SYS_ELAPSED: + case SEMIHOSTING_SYS_FLEN: + case SEMIHOSTING_SYS_GET_CMDLINE: + case SEMIHOSTING_SYS_REMOVE: + case SEMIHOSTING_SYS_RENAME: + case SEMIHOSTING_SYS_SEEK: + case SEMIHOSTING_SYS_SYSTEM: + case SEMIHOSTING_SYS_TICKFREQ: + case SEMIHOSTING_SYS_TMPNAM: + case SEMIHOSTING_SYS_ISTTY: + frame->r0 = (uint32_t)-1; // the call is not successful or not supported + break; + + case SEMIHOSTING_SYS_CLOSE: + frame->r0 = 0; // call is successful + break; + + case SEMIHOSTING_SYS_ERRNO: + frame->r0 = 0; // the value of the C library errno variable. + break; + + case SEMIHOSTING_SYS_HEAPINFO: + blk[0] = 0; // heap_base + blk[1] = 0; // heap_limit + blk[2] = 0; // stack_base + blk[3] = 0; // stack_limit + break; + + case SEMIHOSTING_SYS_ISERROR: + frame->r0 = 0; // 0 if the status word is not an error indication + break; + + case SEMIHOSTING_SYS_READ: + // If R0 contains the same value as word 3, the call has + // failed and EOF is assumed. + frame->r0 = blk[2]; + break; + + case SEMIHOSTING_SYS_READC: + frame->r0 = '\0'; // the byte read from the console. + break; + + case SEMIHOSTING_SYS_TIME: + frame->r0 = 0; // the number of seconds since 00:00 January 1, 1970. + break; + + case SEMIHOSTING_ReportException: + + NVIC_SystemReset (); + // Should not reach here + return 0; + +#endif // defined(OS_USE_SEMIHOSTING) + +#if defined(OS_USE_SEMIHOSTING) || defined(OS_USE_TRACE_SEMIHOSTING_STDOUT) + +#define HANDLER_STDIN (1) +#define HANDLER_STDOUT (2) +#define HANDLER_STDERR (3) + + case SEMIHOSTING_SYS_OPEN: + // Process only standard io/out/err and return 1/2/3 + if (strcmp ((char*) blk[0], ":tt") == 0) + { + if ((blk[1] == 0)) + { + frame->r0 = HANDLER_STDIN; + break; + } + else if (blk[1] == 4) + { + frame->r0 = HANDLER_STDOUT; + break; + } + else if (blk[1] == 8) + { + frame->r0 = HANDLER_STDERR; + break; + } + } + frame->r0 = (uint32_t)-1; // the call is not successful or not supported + break; + + case SEMIHOSTING_SYS_WRITE: + // Silently ignore writes to stdout/stderr, fail on all other handler. + if ((blk[0] == HANDLER_STDOUT) || (blk[0] == HANDLER_STDERR)) + { +#if defined(OS_DEBUG_SEMIHOSTING_FAULTS) + frame->r0 = (uint32_t) blk[2] + - trace_write ((char*) blk[1], blk[2]); +#else + frame->r0 = 0; // all sent, no more. +#endif // defined(OS_DEBUG_SEMIHOSTING_FAULTS) + } + else + { + // If other handler, return the total number of bytes + // as the number of bytes that are not written. + frame->r0 = blk[2]; + } + break; + +#endif // defined(OS_USE_SEMIHOSTING) || defined(OS_USE_TRACE_SEMIHOSTING_STDOUT) + +#if defined(OS_USE_SEMIHOSTING) || defined(OS_USE_TRACE_SEMIHOSTING_STDOUT) || defined(OS_USE_TRACE_SEMIHOSTING_DEBUG) + + case SEMIHOSTING_SYS_WRITEC: +#if defined(OS_DEBUG_SEMIHOSTING_FAULTS) + { + char ch = *((char*) r1); + trace_write (&ch, 1); + } +#endif + // Register R0 is corrupted. + break; + + case SEMIHOSTING_SYS_WRITE0: +#if defined(OS_DEBUG_SEMIHOSTING_FAULTS) + { + char* p = ((char*) r1); + trace_write (p, strlen (p)); + } +#endif + // Register R0 is corrupted. + break; + +#endif + + default: + return 0; + } + + // Alter the PC to make the exception returns to + // the instruction after the faulty BKPT. + frame->pc += 2; + return 1; + } + return 0; +} + +#endif + +// Hard Fault handler wrapper in assembly. +// It extracts the location of stack frame and passes it to handler +// in C as a pointer. We also pass the LR value as second +// parameter. +// (Based on Joseph Yiu's, The Definitive Guide to ARM Cortex-M3 and +// Cortex-M4 Processors, Third Edition, Chap. 12.8, page 402). + +void __attribute__ ((section(".after_vectors"),weak,naked)) +HardFault_Handler (void) +{ + asm volatile( + " tst lr,#4 \n" + " ite eq \n" + " mrseq r0,msp \n" + " mrsne r0,psp \n" + " mov r1,lr \n" + " ldr r2,=HardFault_Handler_C \n" + " bx r2" + + : /* Outputs */ + : /* Inputs */ + : /* Clobbers */ + ); +} + +void __attribute__ ((section(".after_vectors"),weak,used)) +HardFault_Handler_C (ExceptionStackFrame* frame __attribute__((unused)), + uint32_t lr __attribute__((unused))) +{ +#if defined(TRACE) + uint32_t mmfar = SCB->MMFAR; // MemManage Fault Address + uint32_t bfar = SCB->BFAR; // Bus Fault Address + uint32_t cfsr = SCB->CFSR; // Configurable Fault Status Registers +#endif + +#if defined(OS_USE_SEMIHOSTING) || defined(OS_USE_TRACE_SEMIHOSTING_STDOUT) || defined(OS_USE_TRACE_SEMIHOSTING_DEBUG) + + // If the BKPT instruction is executed with C_DEBUGEN == 0 and MON_EN == 0, + // it will cause the processor to enter a HardFault exception, with DEBUGEVT + // in the Hard Fault Status register (HFSR) set to 1, and BKPT in the + // Debug Fault Status register (DFSR) also set to 1. + + if (((SCB->DFSR & SCB_DFSR_BKPT_Msk) != 0) + && ((SCB->HFSR & SCB_HFSR_DEBUGEVT_Msk) != 0)) + { + if (isSemihosting (frame, 0xBE00 + (AngelSWI & 0xFF))) + { + // Clear the exception cause in exception status. + SCB->HFSR = SCB_HFSR_DEBUGEVT_Msk; + + // Continue after the BKPT + return; + } + } + +#endif + +#if defined(TRACE) + trace_printf ("[HardFault]\n"); + dumpExceptionStack (frame, cfsr, mmfar, bfar, lr); +#endif // defined(TRACE) + +#if defined(DEBUG) + __DEBUG_BKPT(); +#endif + while (1) + { + } +} + +#endif // defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) + + +#if defined(__ARM_ARCH_6M__) + +// Hard Fault handler wrapper in assembly. +// It extracts the location of stack frame and passes it to handler +// in C as a pointer. We also pass the LR value as second +// parameter. +// (Based on Joseph Yiu's, The Definitive Guide to ARM Cortex-M0 +// First Edition, Chap. 12.8, page 402). + +void __attribute__ ((section(".after_vectors"),weak,naked)) +HardFault_Handler (void) +{ + asm volatile( + " movs r0,#4 \n" + " mov r1,lr \n" + " tst r0,r1 \n" + " beq 1f \n" + " mrs r0,psp \n" + " b 2f \n" + "1: \n" + " mrs r0,msp \n" + "2:" + " mov r1,lr \n" + " ldr r2,=HardFault_Handler_C \n" + " bx r2" + + : /* Outputs */ + : /* Inputs */ + : /* Clobbers */ + ); +} + +void __attribute__ ((section(".after_vectors"),weak,used)) +HardFault_Handler_C (ExceptionStackFrame* frame __attribute__((unused)), + uint32_t lr __attribute__((unused))) +{ + // There is no semihosting support for Cortex-M0, since on ARMv6-M + // faults are fatal and it is not possible to return from the handler. + +#if defined(TRACE) + trace_printf ("[HardFault]\n"); + dumpExceptionStack (frame, lr); +#endif // defined(TRACE) + +#if defined(DEBUG) + __DEBUG_BKPT(); +#endif + while (1) + { + } +} + +#endif // defined(__ARM_ARCH_6M__) + + +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) + +void __attribute__ ((section(".after_vectors"),weak)) +MemManage_Handler (void) +{ +#if defined(DEBUG) + __DEBUG_BKPT(); +#endif + while (1) + { + } +} + +void __attribute__ ((section(".after_vectors"),weak,naked)) +BusFault_Handler (void) +{ + asm volatile( + " tst lr,#4 \n" + " ite eq \n" + " mrseq r0,msp \n" + " mrsne r0,psp \n" + " mov r1,lr \n" + " ldr r2,=BusFault_Handler_C \n" + " bx r2" + + : /* Outputs */ + : /* Inputs */ + : /* Clobbers */ + ); +} + +void __attribute__ ((section(".after_vectors"),weak,used)) +BusFault_Handler_C (ExceptionStackFrame* frame __attribute__((unused)), + uint32_t lr __attribute__((unused))) +{ +#if defined(TRACE) + uint32_t mmfar = SCB->MMFAR; // MemManage Fault Address + uint32_t bfar = SCB->BFAR; // Bus Fault Address + uint32_t cfsr = SCB->CFSR; // Configurable Fault Status Registers + + trace_printf ("[BusFault]\n"); + dumpExceptionStack (frame, cfsr, mmfar, bfar, lr); +#endif // defined(TRACE) + +#if defined(DEBUG) + __DEBUG_BKPT(); +#endif + while (1) + { + } +} + +void __attribute__ ((section(".after_vectors"),weak,naked)) +UsageFault_Handler (void) +{ + asm volatile( + " tst lr,#4 \n" + " ite eq \n" + " mrseq r0,msp \n" + " mrsne r0,psp \n" + " mov r1,lr \n" + " ldr r2,=UsageFault_Handler_C \n" + " bx r2" + + : /* Outputs */ + : /* Inputs */ + : /* Clobbers */ + ); +} + +void __attribute__ ((section(".after_vectors"),weak,used)) +UsageFault_Handler_C (ExceptionStackFrame* frame __attribute__((unused)), + uint32_t lr __attribute__((unused))) +{ +#if defined(TRACE) + uint32_t mmfar = SCB->MMFAR; // MemManage Fault Address + uint32_t bfar = SCB->BFAR; // Bus Fault Address + uint32_t cfsr = SCB->CFSR; // Configurable Fault Status Registers +#endif + +#if defined(OS_DEBUG_SEMIHOSTING_FAULTS) + + if ((cfsr & (1UL << 16)) != 0) // UNDEFINSTR + { + // For testing purposes, instead of BKPT use 'setend be'. + if (isSemihosting (frame, AngelSWITestFaultOpCode)) + { + return; + } + } + +#endif + +#if defined(TRACE) + trace_printf ("[UsageFault]\n"); + dumpExceptionStack (frame, cfsr, mmfar, bfar, lr); +#endif // defined(TRACE) + +#if defined(DEBUG) + __DEBUG_BKPT(); +#endif + while (1) + { + } +} + +#endif + +void __attribute__ ((section(".after_vectors"),weak)) +SVC_Handler (void) +{ +#if defined(DEBUG) + __DEBUG_BKPT(); +#endif + while (1) + { + } +} + +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) + +void __attribute__ ((section(".after_vectors"),weak)) +DebugMon_Handler (void) +{ +#if defined(DEBUG) + __DEBUG_BKPT(); +#endif + while (1) + { + } +} + +#endif + +void __attribute__ ((section(".after_vectors"),weak)) +PendSV_Handler (void) +{ +#if defined(DEBUG) + __DEBUG_BKPT(); +#endif + while (1) + { + } +} + +void __attribute__ ((section(".after_vectors"),weak)) +SysTick_Handler (void) +{ + // DO NOT loop, just return. + // Useful in case someone (like STM HAL) inadvertently enables SysTick. + ; +} + +// ---------------------------------------------------------------------------- diff --git a/system/src/diag/Trace.c b/system/src/diag/Trace.c new file mode 100644 index 0000000..2ed60da --- /dev/null +++ b/system/src/diag/Trace.c @@ -0,0 +1,98 @@ +/* + * This file is part of the ??OS++ distribution. + * (https://github.com/micro-os-plus) + * Copyright (c) 2014 Liviu Ionescu. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +// ---------------------------------------------------------------------------- + +#if defined(TRACE) + +#include +#include +#include "diag/Trace.h" +#include "string.h" + +#ifndef OS_INTEGER_TRACE_PRINTF_TMP_ARRAY_SIZE +#define OS_INTEGER_TRACE_PRINTF_TMP_ARRAY_SIZE (128) +#endif + +// ---------------------------------------------------------------------------- + +int +trace_printf(const char* format, ...) +{ + int ret; + va_list ap; + + va_start (ap, format); + + // TODO: rewrite it to no longer use newlib, it is way too heavy + + static char buf[OS_INTEGER_TRACE_PRINTF_TMP_ARRAY_SIZE]; + + // Print to the local buffer + ret = vsnprintf (buf, sizeof(buf), format, ap); + if (ret > 0) + { + // Transfer the buffer to the device + ret = trace_write (buf, (size_t)ret); + } + + va_end (ap); + return ret; +} + +int +trace_puts(const char *s) +{ + trace_write(s, strlen(s)); + return trace_write("\n", 1); +} + +int +trace_putchar(int c) +{ + trace_write((const char*)&c, 1); + return c; +} + +void +trace_dump_args(int argc, char* argv[]) +{ + trace_printf("main(argc=%d, argv=[", argc); + for (int i = 0; i < argc; ++i) + { + if (i != 0) + { + trace_printf(", "); + } + trace_printf("\"%s\"", argv[i]); + } + trace_printf("]);\n"); +} + +// ---------------------------------------------------------------------------- + +#endif // TRACE diff --git a/system/src/diag/trace_impl.c b/system/src/diag/trace_impl.c new file mode 100644 index 0000000..e89ee28 --- /dev/null +++ b/system/src/diag/trace_impl.c @@ -0,0 +1,274 @@ +/* + * This file is part of the ??OS++ distribution. + * (https://github.com/micro-os-plus) + * Copyright (c) 2014 Liviu Ionescu. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +// ---------------------------------------------------------------------------- + +#if defined(TRACE) + +#include "cmsis_device.h" +#include "diag/Trace.h" + +// ---------------------------------------------------------------------------- + +// One of these definitions must be passed via the compiler command line +// Note: small Cortex-M0/M0+ might implement a simplified debug interface. + +//#define OS_USE_TRACE_ITM +//#define OS_USE_TRACE_SEMIHOSTING_DEBUG +//#define OS_USE_TRACE_SEMIHOSTING_STDOUT + +#if !(defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)) +#if defined(OS_USE_TRACE_ITM) +#undef OS_USE_TRACE_ITM +#warning "ITM unavailable" +#endif // defined(OS_USE_TRACE_ITM) +#endif // !(defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)) + +#if defined(OS_DEBUG_SEMIHOSTING_FAULTS) +#if defined(OS_USE_TRACE_SEMIHOSTING_STDOUT) || defined(OS_USE_TRACE_SEMIHOSTING_DEBUG) +#error "Cannot debug semihosting using semihosting trace; use OS_USE_TRACE_ITM" +#endif +#endif + +// ---------------------------------------------------------------------------- + +// Forward definitions. + +#if defined(OS_USE_TRACE_ITM) +static ssize_t +_trace_write_itm (const char* buf, size_t nbyte); +#endif + +#if defined(OS_USE_TRACE_SEMIHOSTING_STDOUT) +static ssize_t +_trace_write_semihosting_stdout(const char* buf, size_t nbyte); +#endif + +#if defined(OS_USE_TRACE_SEMIHOSTING_DEBUG) +static ssize_t +_trace_write_semihosting_debug(const char* buf, size_t nbyte); +#endif + +// ---------------------------------------------------------------------------- + +void +trace_initialize(void) +{ + // For regular ITM / semihosting, no inits required. +} + +// ---------------------------------------------------------------------------- + +// This function is called from _write() for fd==1 or fd==2 and from some +// of the trace_* functions. + +ssize_t +trace_write (const char* buf __attribute__((unused)), + size_t nbyte __attribute__((unused))) +{ +#if defined(OS_USE_TRACE_ITM) + return _trace_write_itm (buf, nbyte); +#elif defined(OS_USE_TRACE_SEMIHOSTING_STDOUT) + return _trace_write_semihosting_stdout(buf, nbyte); +#elif defined(OS_USE_TRACE_SEMIHOSTING_DEBUG) + return _trace_write_semihosting_debug(buf, nbyte); +#endif + + return -1; +} + +// ---------------------------------------------------------------------------- + +#if defined(OS_USE_TRACE_ITM) + +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) + +// ITM is the ARM standard mechanism, running over SWD/SWO on Cortex-M3/M4 +// devices, and is the recommended setting, if available. +// +// The JLink probe and the GDB server fully support SWD/SWO +// and the JLink Debugging plug-in enables it by default. +// The current OpenOCD does not include support to parse the SWO stream, +// so this configuration will not work on OpenOCD (will not crash, but +// nothing will be displayed in the output console). + +#if !defined(OS_INTEGER_TRACE_ITM_STIMULUS_PORT) +#define OS_INTEGER_TRACE_ITM_STIMULUS_PORT (0) +#endif + +static ssize_t +_trace_write_itm (const char* buf, size_t nbyte) +{ + for (size_t i = 0; i < nbyte; i++) + { + // Check if ITM or the stimulus port are not enabled + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) == 0) + || ((ITM->TER & (1UL << OS_INTEGER_TRACE_ITM_STIMULUS_PORT)) == 0)) + { + return (ssize_t)i; // return the number of sent characters (may be 0) + } + + // Wait until STIMx is ready... + while (ITM->PORT[OS_INTEGER_TRACE_ITM_STIMULUS_PORT].u32 == 0) + ; + // then send data, one byte at a time + ITM->PORT[OS_INTEGER_TRACE_ITM_STIMULUS_PORT].u8 = (uint8_t) (*buf++); + } + + return (ssize_t)nbyte; // all characters successfully sent +} + +#endif // defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) + +#endif // OS_USE_TRACE_ITM + +// ---------------------------------------------------------------------------- + +#if defined(OS_USE_TRACE_SEMIHOSTING_DEBUG) || defined(OS_USE_TRACE_SEMIHOSTING_STDOUT) + +#include "arm/semihosting.h" + +// Semihosting is the other output channel that can be used for the trace +// messages. It comes in two flavours: STDOUT and DEBUG. The STDOUT channel +// is the equivalent of the stdout in POSIX and in most cases it is forwarded +// to the GDB server stdout stream. The debug channel is a separate +// channel. STDOUT is buffered, so nothing is displayed until a \n; +// DEBUG is not buffered, but can be slow. +// +// Choosing between semihosting stdout and debug depends on the capabilities +// of your GDB server, and also on specific needs. It is recommended to test +// DEBUG first, and if too slow, try STDOUT. +// +// The JLink GDB server fully support semihosting, and both configurations +// are available; to activate it, use "monitor semihosting enable" or check +// the corresponding button in the JLink Debugging plug-in. +// In OpenOCD, support for semihosting can be enabled using +// "monitor arm semihosting enable". +// +// Note: Applications built with semihosting output active normally cannot +// be executed without the debugger connected and active, since they use +// BKPT to communicate with the host. However, with a carefully written +// HardFault_Handler, the semihosting BKPT calls can be processed, making +// possible to run semihosting applications as standalone, without being +// terminated with hardware faults. + +#endif // OS_USE_TRACE_SEMIHOSTING_DEBUG_* + +// ---------------------------------------------------------------------------- + +#if defined(OS_USE_TRACE_SEMIHOSTING_STDOUT) + +static ssize_t +_trace_write_semihosting_stdout (const char* buf, size_t nbyte) +{ + static int handle; + void* block[3]; + int ret; + + if (handle == 0) + { + // On the first call get the file handle from the host + block[0] = ":tt"; // special filename to be used for stdin/out/err + block[1] = (void*) 4; // mode "w" + // length of ":tt", except null terminator + block[2] = (void*) (sizeof(":tt") - 1); + + ret = call_host (SEMIHOSTING_SYS_OPEN, (void*) block); + if (ret == -1) + return -1; + + handle = ret; + } + + block[0] = (void*) handle; + block[1] = (void*) buf; + block[2] = (void*) nbyte; + // send character array to host file/device + ret = call_host (SEMIHOSTING_SYS_WRITE, (void*) block); + // this call returns the number of bytes NOT written (0 if all ok) + + // -1 is not a legal value, but SEGGER seems to return it + if (ret == -1) + return -1; + + // The compliant way of returning errors + if (ret == (int) nbyte) + return -1; + + // Return the number of bytes written + return (ssize_t) (nbyte) - (ssize_t) ret; +} + +#endif // OS_USE_TRACE_SEMIHOSTING_STDOUT + +// ---------------------------------------------------------------------------- + +#if defined(OS_USE_TRACE_SEMIHOSTING_DEBUG) + +#define OS_INTEGER_TRACE_TMP_ARRAY_SIZE (16) + +static ssize_t +_trace_write_semihosting_debug (const char* buf, size_t nbyte) +{ + // Since the single character debug channel is quite slow, try to + // optimise and send a null terminated string, if possible. + if (buf[nbyte] == '\0') + { + // send string + call_host (SEMIHOSTING_SYS_WRITE0, (void*) buf); + } + else + { + // If not, use a local buffer to speed things up + char tmp[OS_INTEGER_TRACE_TMP_ARRAY_SIZE]; + size_t togo = nbyte; + while (togo > 0) + { + unsigned int n = ((togo < sizeof(tmp)) ? togo : sizeof(tmp)); + unsigned int i = 0; + for (; i < n; ++i, ++buf) + { + tmp[i] = *buf; + } + tmp[i] = '\0'; + + call_host (SEMIHOSTING_SYS_WRITE0, (void*) tmp); + + togo -= n; + } + } + + // All bytes written + return (ssize_t) nbyte; +} + +#endif // OS_USE_TRACE_SEMIHOSTING_DEBUG + +#endif // TRACE + +// ---------------------------------------------------------------------------- + diff --git a/system/src/newlib/README.txt b/system/src/newlib/README.txt new file mode 100644 index 0000000..26256d8 --- /dev/null +++ b/system/src/newlib/README.txt @@ -0,0 +1,16 @@ + +The following files extend or replace some of the the newlib functionality: + +_startup.c: a customised startup sequence, written in C + +_exit.c: a customised exit() implementation + +_syscalls.c: local versions of the libnosys/librdimon code + +_sbrk.c: a custom _sbrk() to match the actual linker scripts + +assert.c: implementation for the asserion macros + +_cxx.cpp: local versions of some C++ support, to avoid references to + large functions. + diff --git a/system/src/newlib/_cxx.cpp b/system/src/newlib/_cxx.cpp new file mode 100644 index 0000000..b296411 --- /dev/null +++ b/system/src/newlib/_cxx.cpp @@ -0,0 +1,72 @@ +/* + * This file is part of the ??OS++ distribution. + * (https://github.com/micro-os-plus) + * Copyright (c) 2014 Liviu Ionescu. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +// ---------------------------------------------------------------------------- + +// These functions are redefined locally, to avoid references to some +// heavy implementations in the standard C++ library. + +// ---------------------------------------------------------------------------- + +#include +#include +#include "diag/Trace.h" + +// ---------------------------------------------------------------------------- + +namespace __gnu_cxx +{ + void + __attribute__((noreturn)) + __verbose_terminate_handler(); + + void + __verbose_terminate_handler() + { + trace_puts(__func__); + abort(); + } +} + +// ---------------------------------------------------------------------------- + +extern "C" +{ + void + __attribute__((noreturn)) + __cxa_pure_virtual(); + + void + __cxa_pure_virtual() + { + trace_puts(__func__); + abort(); + } +} + +// ---------------------------------------------------------------------------- + diff --git a/system/src/newlib/_exit.c b/system/src/newlib/_exit.c new file mode 100644 index 0000000..551384f --- /dev/null +++ b/system/src/newlib/_exit.c @@ -0,0 +1,81 @@ +/* + * This file is part of the ??OS++ distribution. + * (https://github.com/micro-os-plus) + * Copyright (c) 2014 Liviu Ionescu. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +// ---------------------------------------------------------------------------- + +#include +#include "diag/Trace.h" + +// ---------------------------------------------------------------------------- + +#if !defined(DEBUG) +extern void +__attribute__((noreturn)) +__reset_hardware(void); +#endif + +// ---------------------------------------------------------------------------- + +// Forward declaration + +void +_exit(int code); + +// ---------------------------------------------------------------------------- + +// On Release, call the hardware reset procedure. +// On Debug we just enter an infinite loop, to be used as landmark when halting +// the debugger. +// +// It can be redefined in the application, if more functionality +// is required. + +void +__attribute__((weak)) +_exit(int code __attribute__((unused))) +{ +#if !defined(DEBUG) + __reset_hardware(); +#endif + + // TODO: write on trace + while (1) + ; +} + +// ---------------------------------------------------------------------------- + +void +__attribute__((weak,noreturn)) +abort(void) +{ + trace_puts("abort(), exiting..."); + + _exit(1); +} + +// ---------------------------------------------------------------------------- diff --git a/system/src/newlib/_sbrk.c b/system/src/newlib/_sbrk.c new file mode 100644 index 0000000..7445213 --- /dev/null +++ b/system/src/newlib/_sbrk.c @@ -0,0 +1,87 @@ +/* + * This file is part of the ??OS++ distribution. + * (https://github.com/micro-os-plus) + * Copyright (c) 2014 Liviu Ionescu. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +// ---------------------------------------------------------------------------- + +#include +#include + +// ---------------------------------------------------------------------------- + +caddr_t +_sbrk(int incr); + +// ---------------------------------------------------------------------------- + +// The definitions used here should be kept in sync with the +// stack definitions in the linker script. + +caddr_t +_sbrk(int incr) +{ + extern char _Heap_Begin; // Defined by the linker. + extern char _Heap_Limit; // Defined by the linker. + + static char* current_heap_end; + char* current_block_address; + + if (current_heap_end == 0) + { + current_heap_end = &_Heap_Begin; + } + + current_block_address = current_heap_end; + + // Need to align heap to word boundary, else will get + // hard faults on Cortex-M0. So we assume that heap starts on + // word boundary, hence make sure we always add a multiple of + // 4 to it. + incr = (incr + 3) & (~3); // align value to 4 + if (current_heap_end + incr > &_Heap_Limit) + { + // Some of the libstdc++-v3 tests rely upon detecting + // out of memory errors, so do not abort here. +#if 0 + extern void abort (void); + + _write (1, "_sbrk: Heap and stack collision\n", 32); + + abort (); +#else + // Heap has overflowed + errno = ENOMEM; + return (caddr_t) - 1; +#endif + } + + current_heap_end += incr; + + return (caddr_t) current_block_address; +} + +// ---------------------------------------------------------------------------- + diff --git a/system/src/newlib/_startup.c b/system/src/newlib/_startup.c new file mode 100644 index 0000000..14038e6 --- /dev/null +++ b/system/src/newlib/_startup.c @@ -0,0 +1,349 @@ +/* + * This file is part of the ??OS++ distribution. + * (https://github.com/micro-os-plus) + * Copyright (c) 2014 Liviu Ionescu. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +// ---------------------------------------------------------------------------- + +// This module contains the startup code for a portable embedded +// C/C++ application, built with newlib. +// +// Control reaches here from the reset handler via jump or call. +// +// The actual steps performed by _start are: +// - copy the initialised data region(s) +// - clear the BSS region(s) +// - initialise the system +// - run the preinit/init array (for the C++ static constructors) +// - initialise the arc/argv +// - branch to main() +// - run the fini array (for the C++ static destructors) +// - call _exit(), directly or via exit() +// +// If OS_INCLUDE_STARTUP_INIT_MULTIPLE_RAM_SECTIONS is defined, the +// code is capable of initialising multiple regions. +// +// The normal configuration is standalone, with all support +// functions implemented locally. +// +// For this to be called, the project linker must be configured without +// the startup sequence (-nostartfiles). + +// ---------------------------------------------------------------------------- + +#include +#include + +// ---------------------------------------------------------------------------- + +#if !defined(OS_INCLUDE_STARTUP_GUARD_CHECKS) +#define OS_INCLUDE_STARTUP_GUARD_CHECKS (1) +#endif + +// ---------------------------------------------------------------------------- + +#if !defined(OS_INCLUDE_STARTUP_INIT_MULTIPLE_RAM_SECTIONS) +// Begin address for the initialisation values of the .data section. +// defined in linker script +extern unsigned int _sidata; +// Begin address for the .data section; defined in linker script +extern unsigned int _sdata; +// End address for the .data section; defined in linker script +extern unsigned int _edata; + +// Begin address for the .bss section; defined in linker script +extern unsigned int __bss_start__; +// End address for the .bss section; defined in linker script +extern unsigned int __bss_end__; +#else +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Memory regions initialisation arrays". +// These arrays are created by the linker via the managed linker script +// of each RW data mechanism. It contains the load address, execution address +// and length section and the execution and length of each BSS (zero +// initialised) section. +extern unsigned int __data_regions_array_start; +extern unsigned int __data_regions_array_end; +extern unsigned int __bss_regions_array_start; +extern unsigned int __bss_regions_array_end; +#endif + +extern void +__initialize_args (int*, char***); + +// main() is the entry point for newlib based applications. +// By default, there are no arguments, but this can be customised +// by redefining __initialize_args(), which is done when the +// semihosting configurations are used. +extern int +main (int argc, char* argv[]); + +// The implementation for the exit routine; for embedded +// applications, a system reset will be performed. +extern void +__attribute__((noreturn)) +_exit (int); + +// ---------------------------------------------------------------------------- + +// Forward declarations + +void +_start (void); + +void +__initialize_data (unsigned int* from, unsigned int* region_begin, + unsigned int* region_end); + +void +__initialize_bss (unsigned int* region_begin, unsigned int* region_end); + +void +__run_init_array (void); + +void +__run_fini_array (void); + +void +__initialize_hardware_early (void); + +void +__initialize_hardware (void); + +// ---------------------------------------------------------------------------- + +inline void +__attribute__((always_inline)) +__initialize_data (unsigned int* from, unsigned int* region_begin, + unsigned int* region_end) +{ + // Iterate and copy word by word. + // It is assumed that the pointers are word aligned. + unsigned int *p = region_begin; + while (p < region_end) + *p++ = *from++; +} + +inline void +__attribute__((always_inline)) +__initialize_bss (unsigned int* region_begin, unsigned int* region_end) +{ + // Iterate and clear word by word. + // It is assumed that the pointers are word aligned. + unsigned int *p = region_begin; + while (p < region_end) + *p++ = 0; +} + +// These magic symbols are provided by the linker. +extern void +(*__preinit_array_start[]) (void) __attribute__((weak)); +extern void +(*__preinit_array_end[]) (void) __attribute__((weak)); +extern void +(*__init_array_start[]) (void) __attribute__((weak)); +extern void +(*__init_array_end[]) (void) __attribute__((weak)); +extern void +(*__fini_array_start[]) (void) __attribute__((weak)); +extern void +(*__fini_array_end[]) (void) __attribute__((weak)); + +// Iterate over all the preinit/init routines (mainly static constructors). +inline void +__attribute__((always_inline)) +__run_init_array (void) +{ + int count; + int i; + + count = __preinit_array_end - __preinit_array_start; + for (i = 0; i < count; i++) + __preinit_array_start[i] (); + + // If you need to run the code in the .init section, please use + // the startup files, since this requires the code in crti.o and crtn.o + // to add the function prologue/epilogue. + //_init(); // DO NOT ENABE THIS! + + count = __init_array_end - __init_array_start; + for (i = 0; i < count; i++) + __init_array_start[i] (); +} + +// Run all the cleanup routines (mainly static destructors). +inline void +__attribute__((always_inline)) +__run_fini_array (void) +{ + int count; + int i; + + count = __fini_array_end - __fini_array_start; + for (i = count; i > 0; i--) + __fini_array_start[i - 1] (); + + // If you need to run the code in the .fini section, please use + // the startup files, since this requires the code in crti.o and crtn.o + // to add the function prologue/epilogue. + //_fini(); // DO NOT ENABE THIS! +} + +#if defined(DEBUG) && (OS_INCLUDE_STARTUP_GUARD_CHECKS) + +// These definitions are used to check if the routines used to +// clear the BSS and to copy the initialised DATA perform correctly. + +#define BSS_GUARD_BAD_VALUE (0xCADEBABA) + +static uint32_t volatile __attribute__ ((section(".bss_begin"))) +__bss_begin_guard; +static uint32_t volatile __attribute__ ((section(".bss_end"))) +__bss_end_guard; + +#define DATA_GUARD_BAD_VALUE (0xCADEBABA) +#define DATA_BEGIN_GUARD_VALUE (0x12345678) +#define DATA_END_GUARD_VALUE (0x98765432) + +static uint32_t volatile __attribute__ ((section(".data_begin"))) +__data_begin_guard = DATA_BEGIN_GUARD_VALUE; + +static uint32_t volatile __attribute__ ((section(".data_end"))) +__data_end_guard = DATA_END_GUARD_VALUE; + +#endif // defined(DEBUG) && (OS_INCLUDE_STARTUP_GUARD_CHECKS) + +// This is the place where Cortex-M core will go immediately after reset, +// via a call or jump from the Reset_Handler. +// +// For the call to work, and for the call to __initialize_hardware_early() +// to work, the reset stack must point to a valid internal RAM area. + +void __attribute__ ((section(".after_vectors"),noreturn,weak)) +_start (void) +{ + + // Initialise hardware right after reset, to switch clock to higher + // frequency and have the rest of the initialisations run faster. + // + // Mandatory on platforms like Kinetis, which start with the watch dog + // enabled and require an early sequence to disable it. + // + // Also useful on platform with external RAM, that need to be + // initialised before filling the BSS section. + + __initialize_hardware_early (); + + // Use Old Style DATA and BSS section initialisation, + // that will manage a single BSS sections. + +#if defined(DEBUG) && (OS_INCLUDE_STARTUP_GUARD_CHECKS) + __data_begin_guard = DATA_GUARD_BAD_VALUE; + __data_end_guard = DATA_GUARD_BAD_VALUE; +#endif + +#if !defined(OS_INCLUDE_STARTUP_INIT_MULTIPLE_RAM_SECTIONS) + // Copy the DATA segment from Flash to RAM (inlined). + __initialize_data(&_sidata, &_sdata, &_edata); +#else + + // Copy the data sections from flash to SRAM. + for (unsigned int* p = &__data_regions_array_start; + p < &__data_regions_array_end;) + { + unsigned int* from = (unsigned int *) (*p++); + unsigned int* region_begin = (unsigned int *) (*p++); + unsigned int* region_end = (unsigned int *) (*p++); + + __initialize_data (from, region_begin, region_end); + } + +#endif + +#if defined(DEBUG) && (OS_INCLUDE_STARTUP_GUARD_CHECKS) + if ((__data_begin_guard != DATA_BEGIN_GUARD_VALUE) + || (__data_end_guard != DATA_END_GUARD_VALUE)) + { + for (;;) + ; + } +#endif + +#if defined(DEBUG) && (OS_INCLUDE_STARTUP_GUARD_CHECKS) + __bss_begin_guard = BSS_GUARD_BAD_VALUE; + __bss_end_guard = BSS_GUARD_BAD_VALUE; +#endif + +#if !defined(OS_INCLUDE_STARTUP_INIT_MULTIPLE_RAM_SECTIONS) + // Zero fill the BSS section (inlined). + __initialize_bss(&__bss_start__, &__bss_end__); +#else + + // Zero fill all bss segments + for (unsigned int *p = &__bss_regions_array_start; + p < &__bss_regions_array_end;) + { + unsigned int* region_begin = (unsigned int*) (*p++); + unsigned int* region_end = (unsigned int*) (*p++); + __initialize_bss (region_begin, region_end); + } +#endif + +#if defined(DEBUG) && (OS_INCLUDE_STARTUP_GUARD_CHECKS) + if ((__bss_begin_guard != 0) || (__bss_end_guard != 0)) + { + for (;;) + ; + } +#endif + + // Hook to continue the initialisations. Usually compute and store the + // clock frequency in the global CMSIS variable, cleared above. + __initialize_hardware (); + + // Get the argc/argv (useful in semihosting configurations). + int argc; + char** argv; + __initialize_args (&argc, &argv); + + // Call the standard library initialisation (mandatory for C++ to + // execute the constructors for the static objects). + __run_init_array (); + + // Call the main entry point, and save the exit code. + int code = main (argc, argv); + + // Run the C++ static destructors. + __run_fini_array (); + + _exit (code); + + // Should never reach this, _exit() should have already + // performed a reset. + for (;;) + ; +} + +// ---------------------------------------------------------------------------- diff --git a/system/src/newlib/_syscalls.c b/system/src/newlib/_syscalls.c new file mode 100644 index 0000000..973fa79 --- /dev/null +++ b/system/src/newlib/_syscalls.c @@ -0,0 +1,1240 @@ +/* + * This file is part of the ??OS++ distribution. + * (https://github.com/micro-os-plus) + * Copyright (c) 2014 Liviu Ionescu. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +// ---------------------------------------------------------------------------- + +int errno; +void *__dso_handle __attribute__ ((weak)); + +// ---------------------------------------------------------------------------- + +#if !defined(OS_USE_SEMIHOSTING) + +#include <_ansi.h> +#include <_syslist.h> +#include +//#include +#include +#include +#include +#include +#include + +void +__initialize_args(int* p_argc, char*** p_argv); + +// This is the standard default implementation for the routine to +// process args. It returns a single empty arg. +// For semihosting applications, this is redefined to get the real +// args from the debugger. You can also use it if you decide to keep +// some args in a non-volatile memory. + +void __attribute__((weak)) +__initialize_args(int* p_argc, char*** p_argv) +{ + // By the time we reach this, the data and bss should have been initialised. + + // The strings pointed to by the argv array shall be modifiable by the + // program, and retain their last-stored values between program startup + // and program termination. (static, no const) + static char name[] = ""; + + // The string pointed to by argv[0] represents the program name; + // argv[0][0] shall be the null character if the program name is not + // available from the host environment. argv[argc] shall be a null pointer. + // (static, no const) + static char* argv[2] = + { name, NULL }; + + *p_argc = 1; + *p_argv = &argv[0]; + return; +} + +// These functions are defined here to avoid linker errors in freestanding +// applications. They might be called in some error cases from library +// code. +// +// If you detect other functions to be needed, just let us know +// and we'll add them. + +__attribute__((weak)) int +raise(int sig __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int +kill(pid_t pid, int sig); + +__attribute__((weak)) int +kill(pid_t pid __attribute__((unused)), int sig __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +#endif // !defined(OS_USE_SEMIHOSTING) + +// ---------------------------------------------------------------------------- + +// If you need the empty definitions, remove the -ffreestanding option. + +#if __STDC_HOSTED__ == 1 + +char* __env[1] = + { 0 }; +char** environ = __env; + +#if !defined(OS_USE_SEMIHOSTING) + +// Forward declarations + +int +_chown(const char* path, uid_t owner, gid_t group); + +int +_close(int fildes); + +int +_execve(char* name, char** argv, char** env); + +int +_fork(void); + +int +_fstat(int fildes, struct stat* st); + +int +_getpid(void); + +int +_gettimeofday(struct timeval* ptimeval, void* ptimezone); + +int +_isatty(int file); + +int +_kill(int pid, int sig); + +int +_link(char* existing, char* _new); + +int +_lseek(int file, int ptr, int dir); + +int +_open(char* file, int flags, int mode); + +int +_read(int file, char* ptr, int len); + +int +_readlink(const char* path, char* buf, size_t bufsize); + +int +_stat(const char* file, struct stat* st); + +int +_symlink(const char* path1, const char* path2); + +clock_t +_times(struct tms* buf); + +int +_unlink(char* name); + +int +_wait(int* status); + +int +_write(int file, char* ptr, int len); + +// Definitions + +int __attribute__((weak)) +_chown(const char* path __attribute__((unused)), + uid_t owner __attribute__((unused)), gid_t group __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_close(int fildes __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_execve(char* name __attribute__((unused)), char** argv __attribute__((unused)), + char** env __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_fork(void) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_fstat(int fildes __attribute__((unused)), + struct stat* st __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_getpid(void) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_gettimeofday(struct timeval* ptimeval __attribute__((unused)), + void* ptimezone __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_isatty(int file __attribute__((unused))) +{ + errno = ENOSYS; + return 0; +} + +int __attribute__((weak)) +_kill(int pid __attribute__((unused)), int sig __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_link(char* existing __attribute__((unused)), + char* _new __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_lseek(int file __attribute__((unused)), int ptr __attribute__((unused)), + int dir __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_open(char* file __attribute__((unused)), int flags __attribute__((unused)), + int mode __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_read(int file __attribute__((unused)), char* ptr __attribute__((unused)), + int len __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_readlink(const char* path __attribute__((unused)), + char* buf __attribute__((unused)), size_t bufsize __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_stat(const char* file __attribute__((unused)), + struct stat* st __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_symlink(const char* path1 __attribute__((unused)), + const char* path2 __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +clock_t __attribute__((weak)) +_times(struct tms* buf __attribute__((unused))) +{ + errno = ENOSYS; + return ((clock_t) -1); +} + +int __attribute__((weak)) +_unlink(char* name __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_wait(int* status __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_write(int file __attribute__((unused)), char* ptr __attribute__((unused)), + int len __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +// ---------------------------------------------------------------------------- + +#else // defined(OS_USE_SEMIHOSTING) + +// ---------------------------------------------------------------------------- + +/* Support files for GNU libc. Files in the system namespace go here. + Files in the C namespace (ie those that do not start with an + underscore) go in .c. */ + +#include <_ansi.h> +#include +//#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "arm/semihosting.h" + +int +_kill (int pid, int sig); + +void +__attribute__((noreturn)) +_exit (int status); + +// Forward declarations. +int +_system (const char*); +int +_rename (const char*, const char*); +int +_isatty (int); +clock_t +_times (struct tms*); +int +_gettimeofday (struct timeval *, void*); +int +_unlink (const char*); +int +_link (void); + +int +_stat (const char*, struct stat*); + +int +_fstat (int, struct stat*); +int +_swistat (int fd, struct stat* st); +int +_getpid (int); +int +_close (int); +clock_t +_clock (void); +int +_swiclose (int); +int +_open (const char*, int, ...); +int +_swiopen (const char*, int); +int +_write (int, char*, int); +int +_swiwrite (int, char*, int); +int +_lseek (int, int, int); +int +_swilseek (int, int, int); +int +_read (int, char*, int); +int +_swiread (int, char*, int); + +void +initialise_monitor_handles (void); + +void +__initialize_args (int* p_argc, char*** p_argv); + +static int +checkerror (int); +static int +error (int); +static int +get_errno (void); + +// ---------------------------------------------------------------------------- + +#define ARGS_BUF_ARRAY_SIZE 80 +#define ARGV_BUF_ARRAY_SIZE 10 + +typedef struct +{ + char* pCommandLine; + int size; +} CommandLineBlock; + +void +__initialize_args (int* p_argc, char*** p_argv) +{ + + // Array of chars to receive the command line from the host + static char args_buf[ARGS_BUF_ARRAY_SIZE]; + + // Array of pointers to store the final argv pointers (pointing + // in the above array). + static char* argv_buf[ARGV_BUF_ARRAY_SIZE]; + + int argc = 0; + int isInArgument = 0; + + CommandLineBlock cmdBlock; + cmdBlock.pCommandLine = args_buf; + cmdBlock.size = sizeof(args_buf) - 1; + + int ret = call_host (SEMIHOSTING_SYS_GET_CMDLINE, &cmdBlock); + if (ret == 0) + { + + // In case the host send more than we can chew, limit the + // string to our buffer. + args_buf[ARGS_BUF_ARRAY_SIZE - 1] = '\0'; + + // The command line is a null terminated string + char* p = cmdBlock.pCommandLine; + + int delim = '\0'; + int ch; + + while ((ch = *p) != '\0') + { + if (isInArgument == 0) + { + if (!isblank(ch)) + { + if (argc + >= (int) ((sizeof(argv_buf) / sizeof(argv_buf[0])) - 1)) + break; + + if (ch == '"' || ch == '\'') + { + // Remember the delimiter to search for the + // corresponding terminator + delim = ch; + ++p; // skip the delimiter + ch = *p; + } + // Remember the arg beginning address + argv_buf[argc++] = p; + isInArgument = 1; + } + } + else if (delim != '\0') + { + if ((ch == delim)) + { + delim = '\0'; + *p = '\0'; + isInArgument = 0; + } + } + else if (isblank(ch)) + { + delim = '\0'; + *p = '\0'; + isInArgument = 0; + } + ++p; + } + } + + if (argc == 0) + { + // No args found in string, return a single empty name. + args_buf[0] = '\0'; + argv_buf[0] = &args_buf[0]; + ++argc; + } + + // Must end the array with a null pointer. + argv_buf[argc] = NULL; + + *p_argc = argc; + *p_argv = &argv_buf[0]; + + // temporary here + initialise_monitor_handles (); + + return; +} + +// ---------------------------------------------------------------------------- + +void +_exit (int status) +{ + /* There is only one SWI for both _exit and _kill. For _exit, call + the SWI with the second argument set to -1, an invalid value for + signum, so that the SWI handler can distinguish the two calls. + Note: The RDI implementation of _kill throws away both its + arguments. */ + report_exception ( + status == 0 ? ADP_Stopped_ApplicationExit : ADP_Stopped_RunTimeError); +} + +// ---------------------------------------------------------------------------- + +int __attribute__((weak)) +_kill (int pid __attribute__((unused)), int sig __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +// ---------------------------------------------------------------------------- + +/* Struct used to keep track of the file position, just so we + can implement fseek(fh,x,SEEK_CUR). */ +struct fdent +{ + int handle; + int pos; +}; + +#define MAX_OPEN_FILES 20 + +/* User file descriptors (fd) are integer indexes into + the openfiles[] array. Error checking is done by using + findslot(). + + This openfiles array is manipulated directly by only + these 5 functions: + + findslot() - Translate entry. + newslot() - Find empty entry. + initilise_monitor_handles() - Initialize entries. + _swiopen() - Initialize entry. + _close() - Handle stdout == stderr case. + + Every other function must use findslot(). */ + +static struct fdent openfiles[MAX_OPEN_FILES]; + +static struct fdent* +findslot (int); +static int +newslot (void); + +/* Register name faking - works in collusion with the linker. */ +register char* stack_ptr asm ("sp"); + +/* following is copied from libc/stdio/local.h to check std streams */ +extern void __sinit(struct _reent*); +#define CHECK_INIT(ptr) \ + do \ + { \ + if ((ptr) && !(ptr)->__sdidinit) \ + __sinit (ptr); \ + } \ + while (0) + +static int monitor_stdin; +static int monitor_stdout; +static int monitor_stderr; + +/* Return a pointer to the structure associated with + the user file descriptor fd. */ +static struct fdent* +findslot (int fd) +{ + CHECK_INIT(_REENT); + + /* User file descriptor is out of range. */ + if ((unsigned int) fd >= MAX_OPEN_FILES) + { + return NULL; + } + + /* User file descriptor is open? */ + if (openfiles[fd].handle == -1) + { + return NULL; + } + + /* Valid. */ + return &openfiles[fd]; +} + +/* Return the next lowest numbered free file + structure, or -1 if we can't find one. */ +static int +newslot (void) +{ + int i; + + for (i = 0; i < MAX_OPEN_FILES; i++) + { + if (openfiles[i].handle == -1) + { + break; + } + } + + if (i == MAX_OPEN_FILES) + { + return -1; + } + + return i; +} + +void +initialise_monitor_handles (void) +{ + int i; + + /* Open the standard file descriptors by opening the special + * teletype device, ":tt", read-only to obtain a descriptor for + * standard input and write-only to obtain a descriptor for standard + * output. Finally, open ":tt" in append mode to obtain a descriptor + * for standard error. Since this is a write mode, most kernels will + * probably return the same value as for standard output, but the + * kernel can differentiate the two using the mode flag and return a + * different descriptor for standard error. + */ + + int volatile block[3]; + + block[0] = (int) ":tt"; + block[2] = 3; /* length of filename */ + block[1] = 0; /* mode "r" */ + monitor_stdin = call_host (SEMIHOSTING_SYS_OPEN, (void*) block); + + block[0] = (int) ":tt"; + block[2] = 3; /* length of filename */ + block[1] = 4; /* mode "w" */ + monitor_stdout = call_host (SEMIHOSTING_SYS_OPEN, (void*) block); + + block[0] = (int) ":tt"; + block[2] = 3; /* length of filename */ + block[1] = 8; /* mode "a" */ + monitor_stderr = call_host (SEMIHOSTING_SYS_OPEN, (void*) block); + + /* If we failed to open stderr, redirect to stdout. */ + if (monitor_stderr == -1) + { + monitor_stderr = monitor_stdout; + } + + for (i = 0; i < MAX_OPEN_FILES; i++) + { + openfiles[i].handle = -1; + } + + openfiles[0].handle = monitor_stdin; + openfiles[0].pos = 0; + openfiles[1].handle = monitor_stdout; + openfiles[1].pos = 0; + openfiles[2].handle = monitor_stderr; + openfiles[2].pos = 0; +} + +static int +get_errno (void) +{ + return call_host (SEMIHOSTING_SYS_ERRNO, NULL); +} + +/* Set errno and return result. */ +static int +error (int result) +{ + errno = get_errno (); + return result; +} + +/* Check the return and set errno appropriately. */ +static int +checkerror (int result) +{ + if (result == -1) + { + return error (-1); + } + + return result; +} + +/* fh, is a valid internal file handle. + ptr, is a null terminated string. + len, is the length in bytes to read. + Returns the number of bytes *not* written. */ +int +_swiread (int fh, char* ptr, int len) +{ + int block[3]; + + block[0] = fh; + block[1] = (int) ptr; + block[2] = len; + + return checkerror (call_host (SEMIHOSTING_SYS_READ, block)); +} + +/* fd, is a valid user file handle. + Translates the return of _swiread into + bytes read. */ +int +_read (int fd, char* ptr, int len) +{ + int res; + struct fdent *pfd; + + pfd = findslot (fd); + if (pfd == NULL) + { + errno = EBADF; + return -1; + } + + res = _swiread (pfd->handle, ptr, len); + + if (res == -1) + { + return res; + } + + pfd->pos += len - res; + + /* res == len is not an error, + at least if we want feof() to work. */ + return len - res; +} + +/* fd, is a user file descriptor. */ +int +_swilseek (int fd, int ptr, int dir) +{ + int res; + struct fdent *pfd; + + /* Valid file descriptor? */ + pfd = findslot (fd); + if (pfd == NULL) + { + errno = EBADF; + return -1; + } + + /* Valid whence? */ + if ((dir != SEEK_CUR) && (dir != SEEK_SET) && (dir != SEEK_END)) + { + errno = EINVAL; + return -1; + } + + /* Convert SEEK_CUR to SEEK_SET */ + if (dir == SEEK_CUR) + { + ptr = pfd->pos + ptr; + /* The resulting file offset would be negative. */ + if (ptr < 0) + { + errno = EINVAL; + if ((pfd->pos > 0) && (ptr > 0)) + { + errno = EOVERFLOW; + } + return -1; + } + dir = SEEK_SET; + } + + int block[2]; + if (dir == SEEK_END) + { + block[0] = pfd->handle; + res = checkerror (call_host (SEMIHOSTING_SYS_FLEN, block)); + if (res == -1) + { + return -1; + } + ptr += res; + } + + /* This code only does absolute seeks. */ + block[0] = pfd->handle; + block[1] = ptr; + res = checkerror (call_host (SEMIHOSTING_SYS_SEEK, block)); + + /* At this point ptr is the current file position. */ + if (res >= 0) + { + pfd->pos = ptr; + return ptr; + } + else + { + return -1; + } +} + +int +_lseek (int fd, int ptr, int dir) +{ + return _swilseek (fd, ptr, dir); +} + +/* fh, is a valid internal file handle. + Returns the number of bytes *not* written. */ +int +_swiwrite (int fh, char* ptr, int len) +{ + int block[3]; + + block[0] = fh; + block[1] = (int) ptr; + block[2] = len; + + return checkerror (call_host (SEMIHOSTING_SYS_WRITE, block)); +} + +/* fd, is a user file descriptor. */ +int +_write (int fd, char* ptr, int len) +{ + int res; + struct fdent *pfd; + + pfd = findslot (fd); + if (pfd == NULL) + { + errno = EBADF; + return -1; + } + + res = _swiwrite (pfd->handle, ptr, len); + + /* Clearly an error. */ + if (res < 0) + { + return -1; + } + + pfd->pos += len - res; + + /* We wrote 0 bytes? + Retrieve errno just in case. */ + if ((len - res) == 0) + { + return error (0); + } + + return (len - res); +} + +int +_swiopen (const char* path, int flags) +{ + int aflags = 0, fh; + uint32_t block[3]; + + int fd = newslot (); + + if (fd == -1) + { + errno = EMFILE; + return -1; + } + + /* It is an error to open a file that already exists. */ + if ((flags & O_CREAT) && (flags & O_EXCL)) + { + struct stat st; + int res; + res = _stat (path, &st); + if (res != -1) + { + errno = EEXIST; + return -1; + } + } + + /* The flags are Unix-style, so we need to convert them. */ +#ifdef O_BINARY + if (flags & O_BINARY) + { + aflags |= 1; + } +#endif + + /* In O_RDONLY we expect aflags == 0. */ + + if (flags & O_RDWR) + { + aflags |= 2; + } + + if ((flags & O_CREAT) || (flags & O_TRUNC) || (flags & O_WRONLY)) + { + aflags |= 4; + } + + if (flags & O_APPEND) + { + /* Can't ask for w AND a; means just 'a'. */ + aflags &= ~4; + aflags |= 8; + } + + block[0] = (uint32_t) path; + block[2] = strlen (path); + block[1] = (uint32_t) aflags; + + fh = call_host (SEMIHOSTING_SYS_OPEN, block); + + /* Return a user file descriptor or an error. */ + if (fh >= 0) + { + openfiles[fd].handle = fh; + openfiles[fd].pos = 0; + return fd; + } + else + { + return error (fh); + } +} + +int +_open (const char* path, int flags, ...) +{ + return _swiopen (path, flags); +} + +/* fh, is a valid internal file handle. */ +int +_swiclose (int fh) +{ + return checkerror (call_host (SEMIHOSTING_SYS_CLOSE, &fh)); +} + +/* fd, is a user file descriptor. */ +int +_close (int fd) +{ + int res; + struct fdent *pfd; + + pfd = findslot (fd); + if (pfd == NULL) + { + errno = EBADF; + return -1; + } + + /* Handle stderr == stdout. */ + if ((fd == 1 || fd == 2) && (openfiles[1].handle == openfiles[2].handle)) + { + pfd->handle = -1; + return 0; + } + + /* Attempt to close the handle. */ + res = _swiclose (pfd->handle); + + /* Reclaim handle? */ + if (res == 0) + { + pfd->handle = -1; + } + + return res; +} + +int __attribute__((weak)) +_getpid (int n __attribute__ ((unused))) +{ + return 1; +} + +int +_swistat (int fd, struct stat* st) +{ + struct fdent *pfd; + int res; + + pfd = findslot (fd); + if (pfd == NULL) + { + errno = EBADF; + return -1; + } + + /* Always assume a character device, + with 1024 byte blocks. */ + st->st_mode |= S_IFCHR; + st->st_blksize = 1024; + res = checkerror (call_host (SEMIHOSTING_SYS_FLEN, &pfd->handle)); + if (res == -1) + { + return -1; + } + + /* Return the file size. */ + st->st_size = res; + return 0; +} + +int __attribute__((weak)) +_fstat (int fd, struct stat* st) +{ + memset (st, 0, sizeof(*st)); + return _swistat (fd, st); +} + +int __attribute__((weak)) +_stat (const char*fname, struct stat *st) +{ + int fd, res; + memset (st, 0, sizeof(*st)); + /* The best we can do is try to open the file readonly. + If it exists, then we can guess a few things about it. */ + if ((fd = _open (fname, O_RDONLY)) == -1) + { + return -1; + } + st->st_mode |= S_IFREG | S_IREAD; + res = _swistat (fd, st); + /* Not interested in the error. */ + _close (fd); + return res; +} + +int __attribute__((weak)) +_link (void) +{ + errno = ENOSYS; + return -1; +} + +int +_unlink (const char* path) +{ + int res; + uint32_t block[2]; + block[0] = (uint32_t) path; + block[1] = strlen (path); + res = call_host (SEMIHOSTING_SYS_REMOVE, block); + + if (res == -1) + { + return error (res); + } + return 0; +} + +int +_gettimeofday (struct timeval* tp, void* tzvp) +{ + struct timezone* tzp = tzvp; + if (tp) + { + /* Ask the host for the seconds since the Unix epoch. */ + tp->tv_sec = call_host (SEMIHOSTING_SYS_TIME, NULL); + tp->tv_usec = 0; + } + + /* Return fixed data for the timezone. */ + if (tzp) + { + tzp->tz_minuteswest = 0; + tzp->tz_dsttime = 0; + } + + return 0; +} + +/* Return a clock that ticks at 100Hz. */ +clock_t +_clock (void) +{ + clock_t timeval; + + timeval = (clock_t) call_host (SEMIHOSTING_SYS_CLOCK, NULL); + return timeval; +} + +/* Return a clock that ticks at 100Hz. */ +clock_t +_times (struct tms* tp) +{ + clock_t timeval = _clock (); + + if (tp) + { + tp->tms_utime = timeval; /* user time */ + tp->tms_stime = 0; /* system time */ + tp->tms_cutime = 0; /* user time, children */ + tp->tms_cstime = 0; /* system time, children */ + } + + return timeval; +} + +int +_isatty (int fd) +{ + struct fdent *pfd; + int tty; + + pfd = findslot (fd); + if (pfd == NULL) + { + errno = EBADF; + return 0; + } + + tty = call_host (SEMIHOSTING_SYS_ISTTY, &pfd->handle); + + if (tty == 1) + { + return 1; + } + + errno = get_errno (); + return 0; +} + +int +_system (const char* s) +{ + uint32_t block[2]; + int e; + + /* Hmmm. The ARM debug interface specification doesn't say whether + SYS_SYSTEM does the right thing with a null argument, or assign any + meaning to its return value. Try to do something reasonable.... */ + if (!s) + { + return 1; /* maybe there is a shell available? we can hope. :-P */ + } + block[0] = (uint32_t) s; + block[1] = strlen (s); + e = checkerror (call_host (SEMIHOSTING_SYS_SYSTEM, block)); + if ((e >= 0) && (e < 256)) + { + /* We have to convert e, an exit status to the encoded status of + the command. To avoid hard coding the exit status, we simply + loop until we find the right position. */ + int exit_code; + + for (exit_code = e; e && WEXITSTATUS (e) != exit_code; e <<= 1) + { + continue; + } + } + return e; +} + +int +_rename (const char* oldpath, const char* newpath) +{ + uint32_t block[4]; + block[0] = (uint32_t) oldpath; + block[1] = strlen (oldpath); + block[2] = (uint32_t) newpath; + block[3] = strlen (newpath); + return checkerror (call_host (SEMIHOSTING_SYS_RENAME, block)) ? -1 : 0; +} + +// ---------------------------------------------------------------------------- +// Required by Google Tests + +int +mkdir (const char *path __attribute__((unused)), + mode_t mode __attribute__((unused))) +{ +#if 0 + // always return true + return 0; +#else + errno = ENOSYS; + return -1; +#endif +} + +char * +getcwd (char *buf, size_t size) +{ + // no cwd available via semihosting, so we use the temporary folder + strncpy (buf, "/tmp", size); + return buf; +} + +#endif // defined OS_USE_SEMIHOSTING + +#endif // __STDC_HOSTED__ == 1 diff --git a/system/src/newlib/assert.c b/system/src/newlib/assert.c new file mode 100644 index 0000000..5bffcdc --- /dev/null +++ b/system/src/newlib/assert.c @@ -0,0 +1,77 @@ +/* + * This file is part of the ??OS++ distribution. + * (https://github.com/micro-os-plus) + * Copyright (c) 2014 Liviu Ionescu. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include "diag/Trace.h" + +// ---------------------------------------------------------------------------- + +void +__attribute__((noreturn)) +__assert_func (const char *file, int line, const char *func, + const char *failedexpr) +{ + trace_printf ("assertion \"%s\" failed: file \"%s\", line %d%s%s\n", + failedexpr, file, line, func ? ", function: " : "", + func ? func : ""); + abort (); + /* NOTREACHED */ +} + +// ---------------------------------------------------------------------------- + +// This is STM32 specific, but can be used on other platforms too. +// If you need it, add the following to your application header: + +//#ifdef USE_FULL_ASSERT +//#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +//void assert_failed(uint8_t* file, uint32_t line); +//#else +//#define assert_param(expr) ((void)0) +//#endif // USE_FULL_ASSERT + +#if defined(USE_FULL_ASSERT) + +void +assert_failed (uint8_t* file, uint32_t line); + +// Called from the assert_param() macro, usually defined in the stm32f*_conf.h +void +__attribute__((noreturn, weak)) +assert_failed (uint8_t* file, uint32_t line) +{ + trace_printf ("assert_param() failed: file \"%s\", line %d\n", file, line); + abort (); + /* NOTREACHED */ +} + +#endif // defined(USE_FULL_ASSERT) + +// ---------------------------------------------------------------------------- diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_adc.c b/system/src/stm32f0-stdperiph/stm32f0xx_adc.c new file mode 100644 index 0000000..59b88fe --- /dev/null +++ b/system/src/stm32f0-stdperiph/stm32f0xx_adc.c @@ -0,0 +1,1240 @@ +/** + ****************************************************************************** + * @file stm32f0xx_adc.c + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Convertor (ADC) peripheral: + * + Initialization and Configuration + * + Power saving + * + Analog Watchdog configuration + * + Temperature Sensor, Vrefint (Internal Reference Voltage) and + * Vbat (Voltage battery) management + * + ADC Channels Configuration + * + ADC Channels DMA Configuration + * + Interrupts and flags management + * + * @verbatim +================================================================================ + ##### How to use this driver ##### +================================================================================ + [..] + (#) Enable the ADC interface clock using + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE); + (#) ADC pins configuration + (++) Enable the clock for the ADC GPIOs using the following function: + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE); + (++) Configure these ADC pins in analog mode using GPIO_Init(); + (#) Configure the ADC conversion resolution, data alignment, external + trigger and edge, scan direction and Enable/Disable the continuous mode + using the ADC_Init() function. + (#) Activate the ADC peripheral using ADC_Cmd() function. + + *** ADC channels group configuration *** + ============================================ + [..] + (+) To configure the ADC channels features, use ADC_Init() and + ADC_ChannelConfig() functions. + (+) To activate the continuous mode, use the ADC_ContinuousModeCmd() + function. + (+) To activate the Discontinuous mode, use the ADC_DiscModeCmd() functions. + (+) To activate the overrun mode, use the ADC_OverrunModeCmd() functions. + (+) To activate the calibration mode, use the ADC_GetCalibrationFactor() functions. + (+) To read the ADC converted values, use the ADC_GetConversionValue() + function. + + *** DMA for ADC channels features configuration *** + ============================================================= + [..] + (+) To enable the DMA mode for ADC channels group, use the ADC_DMACmd() function. + (+) To configure the DMA transfer request, use ADC_DMARequestModeConfig() function. + + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_adc.h" +#include "stm32f0xx_rcc.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup ADC + * @brief ADC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ADC CFGR mask */ +#define CFGR1_CLEAR_MASK ((uint32_t)0xFFFFD203) + +/* Calibration time out */ +#define CALIBRATION_TIMEOUT ((uint32_t)0x0000F000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup ADC_Private_Functions + * @{ + */ + +/** @defgroup ADC_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the ADC Prescaler + (+) ADC Conversion Resolution (12bit..6bit) + (+) ADC Continuous Conversion Mode (Continuous or Single conversion) + (+) External trigger Edge and source + (+) Converted data alignment (left or right) + (+) The direction in which the channels will be scanned in the sequence + (+) Enable or disable the ADC peripheral + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes ADC1 peripheral registers to their default reset values. + * @param ADCx: where x can be 1 to select the ADC peripheral. + * @retval None + */ +void ADC_DeInit(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + if(ADCx == ADC1) + { + /* Enable ADC1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); + + /* Release ADC1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); + } +} + +/** + * @brief Initializes the ADCx peripheral according to the specified parameters + * in the ADC_InitStruct. + * @note This function is used to configure the global features of the ADC ( + * Resolution, Data Alignment, continuous mode activation, External + * trigger source and edge, Sequence Scan Direction). + * @param ADCx: where x can be 1 to select the ADC peripheral. + * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains + * the configuration information for the specified ADC peripheral. + * @retval None + */ +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge)); + assert_param(IS_ADC_EXTERNAL_TRIG_CONV(ADC_InitStruct->ADC_ExternalTrigConv)); + assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); + assert_param(IS_ADC_SCAN_DIRECTION(ADC_InitStruct->ADC_ScanDirection)); + + /* Get the ADCx CFGR value */ + tmpreg = ADCx->CFGR1; + + /* Clear SCANDIR, RES[1:0], ALIGN, EXTSEL[2:0], EXTEN[1:0] and CONT bits */ + tmpreg &= CFGR1_CLEAR_MASK; + + /*---------------------------- ADCx CFGR Configuration ---------------------*/ + + /* Set RES[1:0] bits according to ADC_Resolution value */ + /* Set CONT bit according to ADC_ContinuousConvMode value */ + /* Set EXTEN[1:0] bits according to ADC_ExternalTrigConvEdge value */ + /* Set EXTSEL[2:0] bits according to ADC_ExternalTrigConv value */ + /* Set ALIGN bit according to ADC_DataAlign value */ + /* Set SCANDIR bit according to ADC_ScanDirection value */ + + tmpreg |= (uint32_t)(ADC_InitStruct->ADC_Resolution | ((uint32_t)(ADC_InitStruct->ADC_ContinuousConvMode) << 13) | + ADC_InitStruct->ADC_ExternalTrigConvEdge | ADC_InitStruct->ADC_ExternalTrigConv | + ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ScanDirection); + + /* Write to ADCx CFGR */ + ADCx->CFGR1 = tmpreg; +} + +/** + * @brief Fills each ADC_InitStruct member with its default value. + * @note This function is used to initialize the global features of the ADC ( + * Resolution, Data Alignment, continuous mode activation, External + * trigger source and edge, Sequence Scan Direction). + * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) +{ + /* Reset ADC init structure parameters values */ + /* Initialize the ADC_Resolution member */ + ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b; + + /* Initialize the ADC_ContinuousConvMode member */ + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + + /* Initialize the ADC_ExternalTrigConvEdge member */ + ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; + + /* Initialize the ADC_ExternalTrigConv member */ + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_TRGO; + + /* Initialize the ADC_DataAlign member */ + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + + /* Initialize the ADC_ScanDirection member */ + ADC_InitStruct->ADC_ScanDirection = ADC_ScanDirection_Upward; +} + +/** + * @brief Enables or disables the specified ADC peripheral. + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param NewState: new state of the ADCx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the ADEN bit to Enable the ADC peripheral */ + ADCx->CR |= (uint32_t)ADC_CR_ADEN; + } + else + { + /* Set the ADDIS to Disable the ADC peripheral */ + ADCx->CR |= (uint32_t)ADC_CR_ADDIS; + } +} + +/** + * @brief Configure the ADC to either be clocked by the asynchronous clock(which is + * independent, the dedicated 14MHz clock) or the synchronous clock derived from + * the APB clock of the ADC bus interface divided by 2 or 4 + * @note This function can be called only when ADC is disabled. + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param ADC_ClockMode: This parameter can be : + * @arg ADC_ClockMode_AsynClk: ADC clocked by the dedicated 14MHz clock + * @arg ADC_ClockMode_SynClkDiv2: ADC clocked by PCLK/2 + * @arg ADC_ClockMode_SynClkDiv4: ADC clocked by PCLK/4 + * @retval None + */ +void ADC_ClockModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ClockMode) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CLOCKMODE(ADC_ClockMode)); + + /* Configure the ADC Clock mode according to ADC_ClockMode */ + ADCx->CFGR2 = (uint32_t)ADC_ClockMode; + +} + +/** + * @brief Enables or disables the jitter when the ADC is clocked by PCLK div2 + * or div4 + * @note This function is obsolete and maintained for legacy purpose only. ADC_ClockModeConfig() + * function should be used instead. + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param ADC_JitterOff: This parameter can be : + * @arg ADC_JitterOff_PCLKDiv2: Remove jitter when ADC is clocked by PLCK divided by 2 + * @arg ADC_JitterOff_PCLKDiv4: Remove jitter when ADC is clocked by PLCK divided by 4 + * @param NewState: new state of the ADCx jitter. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_JitterCmd(ADC_TypeDef* ADCx, uint32_t ADC_JitterOff, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_JITTEROFF(ADC_JitterOff)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Disable Jitter */ + ADCx->CFGR2 |= (uint32_t)ADC_JitterOff; + } + else + { + /* Enable Jitter */ + ADCx->CFGR2 &= (uint32_t)(~ADC_JitterOff); + } +} + +/** + * @} + */ + +/** @defgroup ADC_Group2 Power saving functions + * @brief Power saving functions + * +@verbatim + =============================================================================== + ##### Power saving functions ##### + =============================================================================== + [..] This section provides functions allowing to reduce power consumption. + [..] The two function must be combined to get the maximal benefits: + When the ADC frequency is higher than the CPU one, it is recommended to + (#) Enable the Auto Delayed Conversion mode : + ==> using ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); + (#) Enable the power off in Delay phases : + ==> using ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState); + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the ADC Power Off. + * @note ADC power-on and power-off can be managed by hardware to cut the + * consumption when the ADC is not converting. + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @note The ADC can be powered down: + * - During the Auto delay phase: The ADC is powered on again at the end + * of the delay (until the previous data is read from the ADC data register). + * - During the ADC is waiting for a trigger event: The ADC is powered up + * at the next trigger event (when the conversion is started). + * @param NewState: new state of the ADCx power Off. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the ADC Automatic Power-Off */ + ADCx->CFGR1 |= ADC_CFGR1_AUTOFF; + } + else + { + /* Disable the ADC Automatic Power-Off */ + ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AUTOFF; + } +} + +/** + * @brief Enables or disables the Wait conversion mode. + * @note When the CPU clock is not fast enough to manage the data rate, a + * Hardware delay can be introduced between ADC conversions to reduce + * this data rate. + * @note The Hardware delay is inserted after each conversions and until the + * previous data is read from the ADC data register + * @note This is a way to automatically adapt the speed of the ADC to the speed + * of the system which will read the data. + * @note Any hardware triggers wich occur while a conversion is on going or + * while the automatic Delay is applied are ignored + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param NewState: new state of the ADCx Auto-Delay. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the ADC Automatic Delayed conversion */ + ADCx->CFGR1 |= ADC_CFGR1_WAIT; + } + else + { + /* Disable the ADC Automatic Delayed conversion */ + ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_WAIT; + } +} + +/** + * @} + */ + +/** @defgroup ADC_Group3 Analog Watchdog configuration functions + * @brief Analog Watchdog configuration functions + * +@verbatim + =============================================================================== + ##### Analog Watchdog configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to configure the Analog Watchdog + (AWD) feature in the ADC. + [..] A typical configuration Analog Watchdog is done following these steps : + (#) the ADC guarded channel(s) is (are) selected using the + ADC_AnalogWatchdogSingleChannelConfig() function. + (#) The Analog watchdog lower and higher threshold are configured using the + ADC_AnalogWatchdogThresholdsConfig() function. + (#) The Analog watchdog is enabled and configured to enable the check, on one + or more channels, using the ADC_AnalogWatchdogCmd() function. + (#) Enable the analog watchdog on the selected channel using + ADC_AnalogWatchdogSingleChannelCmd() function + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the analog watchdog + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param NewState: new state of the ADCx Analog Watchdog. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the ADC Analog Watchdog */ + ADCx->CFGR1 |= ADC_CFGR1_AWDEN; + } + else + { + /* Disable the ADC Analog Watchdog */ + ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AWDEN; + } +} + +/** + * @brief Configures the high and low thresholds of the analog watchdog. + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param HighThreshold: the ADC analog watchdog High threshold value. + * This parameter must be a 12bit value. + * @param LowThreshold: the ADC analog watchdog Low threshold value. + * This parameter must be a 12bit value. + * @retval None + */ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_THRESHOLD(HighThreshold)); + assert_param(IS_ADC_THRESHOLD(LowThreshold)); + + /* Set the ADCx high and low threshold */ + ADCx->TR = LowThreshold | ((uint32_t)HighThreshold << 16); + +} + +/** + * @brief Configures the analog watchdog guarded single channel + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param ADC_AnalogWatchdog_Channel: the ADC channel to configure for the analog watchdog. + * This parameter can be one of the following values: + * @arg ADC_AnalogWatchdog_Channel_0: ADC Channel0 selected + * @arg ADC_AnalogWatchdog_Channel_1: ADC Channel1 selected + * @arg ADC_AnalogWatchdog_Channel_2: ADC Channel2 selected + * @arg ADC_AnalogWatchdog_Channel_3: ADC Channel3 selected + * @arg ADC_AnalogWatchdog_Channel_4: ADC Channel4 selected + * @arg ADC_AnalogWatchdog_Channel_5: ADC Channel5 selected + * @arg ADC_AnalogWatchdog_Channel_6: ADC Channel6 selected + * @arg ADC_AnalogWatchdog_Channel_7: ADC Channel7 selected + * @arg ADC_AnalogWatchdog_Channel_8: ADC Channel8 selected + * @arg ADC_AnalogWatchdog_Channel_9: ADC Channel9 selected + * @arg ADC_AnalogWatchdog_Channel_10: ADC Channel10 selected, not available for STM32F031 devices + * @arg ADC_AnalogWatchdog_Channel_11: ADC Channel11 selected, not available for STM32F031 devices + * @arg ADC_AnalogWatchdog_Channel_12: ADC Channel12 selected, not available for STM32F031 devices + * @arg ADC_AnalogWatchdog_Channel_13: ADC Channel13 selected, not available for STM32F031 devices + * @arg ADC_AnalogWatchdog_Channel_14: ADC Channel14 selected, not available for STM32F031 devices + * @arg ADC_AnalogWatchdog_Channel_15: ADC Channel15 selected, not available for STM32F031 devices + * @arg ADC_AnalogWatchdog_Channel_16: ADC Channel16 selected + * @arg ADC_AnalogWatchdog_Channel_17: ADC Channel17 selected + * @arg ADC_AnalogWatchdog_Channel_18: ADC Channel18 selected, not available for STM32F030 devices + * @note The channel selected on the AWDCH must be also set into the CHSELR + * register + * @retval None + */ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog_Channel) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_ANALOG_WATCHDOG_CHANNEL(ADC_AnalogWatchdog_Channel)); + + /* Get the old register value */ + tmpreg = ADCx->CFGR1; + + /* Clear the Analog watchdog channel select bits */ + tmpreg &= ~ADC_CFGR1_AWDCH; + + /* Set the Analog watchdog channel */ + tmpreg |= ADC_AnalogWatchdog_Channel; + + /* Store the new register value */ + ADCx->CFGR1 = tmpreg; +} + +/** + * @brief Enables or disables the ADC Analog Watchdog Single Channel. + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param NewState: new state of the ADCx ADC Analog Watchdog Single Channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_AnalogWatchdogSingleChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the ADC Analog Watchdog Single Channel */ + ADCx->CFGR1 |= ADC_CFGR1_AWDSGL; + } + else + { + /* Disable the ADC Analog Watchdog Single Channel */ + ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AWDSGL; + } +} + +/** + * @} + */ + +/** @defgroup ADC_Group4 Temperature Sensor, Vrefint and Vbat management functions + * @brief Temperature Sensor, Vrefint and Vbat management functions + * +@verbatim + =============================================================================== + ##### Temperature Sensor, Vrefint and Vbat management function ##### + =============================================================================== + [..] This section provides a function allowing to enable/disable the internal + connections between the ADC and the Temperature Sensor, the Vrefint and + Vbat source. + + [..] A typical configuration to get the Temperature sensor, Vrefint and Vbat channels + voltages is done following these steps : + (#) Enable the internal connection of Temperature sensor, Vrefint or Vbat sources + with the ADC channels using ADC_TempSensorCmd(), ADC_VrefintCmd() or ADC_VbatCmd() + functions. + (#) select the ADC_Channel_16(Temperature sensor), ADC_Channel_17(Vrefint) + or ADC_Channel_18(Voltage battery) using ADC_ChannelConfig() function + (#) Get the voltage values, using ADC_GetConversionValue() function + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the temperature sensor channel. + * @param NewState: new state of the temperature sensor input channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_TempSensorCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the temperature sensor channel*/ + ADC->CCR |= (uint32_t)ADC_CCR_TSEN; + } + else + { + /* Disable the temperature sensor channel*/ + ADC->CCR &= (uint32_t)(~ADC_CCR_TSEN); + } +} + +/** + * @brief Enables or disables the Vrefint channel. + * @param NewState: new state of the Vref input channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_VrefintCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Vrefint channel*/ + ADC->CCR |= (uint32_t)ADC_CCR_VREFEN; + } + else + { + /* Disable the Vrefint channel*/ + ADC->CCR &= (uint32_t)(~ADC_CCR_VREFEN); + } +} + +/** + * @brief Enables or disables the Vbat channel. + * @note This feature is not applicable for STM32F030 devices. + * @param NewState: new state of the Vbat input channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_VbatCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Vbat channel*/ + ADC->CCR |= (uint32_t)ADC_CCR_VBATEN; + } + else + { + /* Disable the Vbat channel*/ + ADC->CCR &= (uint32_t)(~ADC_CCR_VBATEN); + } +} + +/** + * @} + */ + +/** @defgroup ADC_Group5 Channels Configuration functions + * @brief Channels Configuration functions + * +@verbatim + =============================================================================== + ##### Channels Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to manage the ADC channels, + it is composed of 3 sub sections : + (#) Configuration and management functions for ADC channels: This subsection + provides functions allowing to configure the ADC channels : + (++) Select the ADC channels + (++) Activate ADC Calibration + (++) Activate the Overrun Mode. + (++) Activate the Discontinuous Mode + (++) Activate the Continuous Mode. + (++) Configure the sampling time for each channel + (++) Select the conversion Trigger and Edge for ADC channels + (++) Select the scan direction. + -@@- Please Note that the following features for ADC channels are configurated + using the ADC_Init() function : + (+@@) Activate the Continuous Mode (can be also activated by ADC_OverrunModeCmd(). + (+@@) Select the conversion Trigger and Edge for ADC channels + (+@@) Select the scan direction. + (#) Control the ADC peripheral : This subsection permits to command the ADC: + (++) Stop or discard an on-going conversion (ADSTP command) + (++) Start the ADC conversion . + (#) Get the conversion data: This subsection provides an important function in + the ADC peripheral since it returns the converted data of the current + ADC channel. When the Conversion value is read, the EOC Flag is + automatically cleared. + +@endverbatim + * @{ + */ + +/** + * @brief Configures for the selected ADC and its sampling time. + * @param ADCx: where x can be 1 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure. + * This parameter can be any combination of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected, not available for STM32F031 devices + * @arg ADC_Channel_11: ADC Channel11 selected, not available for STM32F031 devices + * @arg ADC_Channel_12: ADC Channel12 selected, not available for STM32F031 devices + * @arg ADC_Channel_13: ADC Channel13 selected, not available for STM32F031 devices + * @arg ADC_Channel_14: ADC Channel14 selected, not available for STM32F031 devices + * @arg ADC_Channel_15: ADC Channel15 selected, not available for STM32F031 devices + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @arg ADC_Channel_18: ADC Channel18 selected, not available for STM32F030 devices + * @param ADC_SampleTime: The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SampleTime_1_5Cycles: Sample time equal to 1.5 cycles + * @arg ADC_SampleTime_7_5Cycles: Sample time equal to 7.5 cycles + * @arg ADC_SampleTime_13_5Cycles: Sample time equal to 13.5 cycles + * @arg ADC_SampleTime_28_5Cycles: Sample time equal to 28.5 cycles + * @arg ADC_SampleTime_41_5Cycles: Sample time equal to 41.5 cycles + * @arg ADC_SampleTime_55_5Cycles: Sample time equal to 55.5 cycles + * @arg ADC_SampleTime_71_5Cycles: Sample time equal to 71.5 cycles + * @arg ADC_SampleTime_239_5Cycles: Sample time equal to 239.5 cycles + * @retval None + */ +void ADC_ChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_Channel, uint32_t ADC_SampleTime) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + + /* Configure the ADC Channel */ + ADCx->CHSELR |= (uint32_t)ADC_Channel; + + /* Clear the Sampling time Selection bits */ + tmpreg &= ~ADC_SMPR1_SMPR; + + /* Set the ADC Sampling Time register */ + tmpreg |= (uint32_t)ADC_SampleTime; + + /* Configure the ADC Sample time register */ + ADCx->SMPR = tmpreg ; +} + +/** + * @brief Enable the Continuous mode for the selected ADCx channels. + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param NewState: new state of the Continuous mode. + * This parameter can be: ENABLE or DISABLE. + * @note It is not possible to have both discontinuous mode and continuous mode + * enabled. In this case (If DISCEN and CONT are Set), the ADC behaves + * as if continuous mode was disabled + * @retval None + */ +void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Continuous mode*/ + ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_CONT; + } + else + { + /* Disable the Continuous mode */ + ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_CONT); + } +} + +/** + * @brief Enable the discontinuous mode for the selected ADC channels. + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param NewState: new state of the discontinuous mode. + * This parameter can be: ENABLE or DISABLE. + * @note It is not possible to have both discontinuous mode and continuous mode + * enabled. In this case (If DISCEN and CONT are Set), the ADC behaves + * as if continuous mode was disabled + * @retval None + */ +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Discontinuous mode */ + ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_DISCEN; + } + else + { + /* Disable the Discontinuous mode */ + ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_DISCEN); + } +} + +/** + * @brief Enable the Overrun mode for the selected ADC channels. + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param NewState: new state of the Overrun mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_OverrunModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Overrun mode */ + ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_OVRMOD; + } + else + { + /* Disable the Overrun mode */ + ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_OVRMOD); + } +} + +/** + * @brief Active the Calibration operation for the selected ADC. + * @note The Calibration can be initiated only when ADC is still in the + * reset configuration (ADEN must be equal to 0). + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @retval ADC Calibration factor + */ +uint32_t ADC_GetCalibrationFactor(ADC_TypeDef* ADCx) +{ + uint32_t tmpreg = 0, calibrationcounter = 0, calibrationstatus = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Set the ADC calibartion */ + ADCx->CR |= (uint32_t)ADC_CR_ADCAL; + + /* Wait until no ADC calibration is completed */ + do + { + calibrationstatus = ADCx->CR & ADC_CR_ADCAL; + calibrationcounter++; + } while((calibrationcounter != CALIBRATION_TIMEOUT) && (calibrationstatus != 0x00)); + + if((uint32_t)(ADCx->CR & ADC_CR_ADCAL) == RESET) + { + /*Get the calibration factor from the ADC data register */ + tmpreg = ADCx->DR; + } + else + { + /* Error factor */ + tmpreg = 0x00000000; + } + return tmpreg; +} + +/** + * @brief Stop the on going conversions for the selected ADC. + * @note When ADSTP is set, any on going conversion is aborted, and the ADC + * data register is not updated with current conversion. + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @retval None + */ +void ADC_StopOfConversion(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + ADCx->CR |= (uint32_t)ADC_CR_ADSTP; +} + +/** + * @brief Start Conversion for the selected ADC channels. + * @note In continuous mode, ADSTART is not cleared by hardware with the + * assertion of EOSEQ because the sequence is automatic relaunched + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @retval None + */ +void ADC_StartOfConversion(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + ADCx->CR |= (uint32_t)ADC_CR_ADSTART; +} + +/** + * @brief Returns the last ADCx conversion result data for ADC channel. + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @retval The Data conversion value. + */ +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Return the selected ADC conversion value */ + return (uint16_t) ADCx->DR; +} + +/** + * @} + */ + +/** @defgroup ADC_Group6 DMA Configuration functions + * @brief Regular Channels DMA Configuration functions + * +@verbatim + =============================================================================== + ##### DMA Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to configure the DMA for ADC hannels. + Since converted channel values are stored into a unique data register, + it is useful to use DMA for conversion of more than one channel. This + avoids the loss of the data already stored in the ADC Data register. + When the DMA mode is enabled (using the ADC_DMACmd() function), after each + conversion of a channel, a DMA request is generated. + + [..] Depending on the "DMA disable selection" configuration (using the + ADC_DMARequestModeConfig() function), at the end of the last DMA + transfer, two possibilities are allowed: + (+) No new DMA request is issued to the DMA controller (One Shot Mode) + (+) Requests can continue to be generated (Circular Mode). + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified ADC DMA request. + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param NewState: new state of the selected ADC DMA transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC DMA request */ + ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_DMAEN; + } + else + { + /* Disable the selected ADC DMA request */ + ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_DMAEN); + } +} + +/** + * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode) + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param ADC_DMARequestMode: the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_DMAMode_OneShot: DMA One Shot Mode + * @arg ADC_DMAMode_Circular: DMA Circular Mode + * @retval None + */ +void ADC_DMARequestModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMARequestMode) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_DMACFG; + ADCx->CFGR1 |= (uint32_t)ADC_DMARequestMode; +} + +/** + * @} + */ + +/** @defgroup ADC_Group7 Interrupts and flags management functions + * @brief Interrupts and flags management functions. + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + [..] This section provides functions allowing to configure the ADC Interrupts + and get the status and clear flags and Interrupts pending bits. + + [..] The ADC provide 6 Interrupts sources and 11 Flags which can be divided into + 3 groups: + + *** Flags for ADC status *** + ====================================================== + [..] + (+)Flags : + (##) ADC_FLAG_ADRDY : This flag is set after the ADC has been enabled (bit ADEN=1) + and when the ADC reaches a state where it is ready to accept conversion requests + (##) ADC_FLAG_ADEN : This flag is set by software to enable the ADC. + The ADC will be effectively ready to operate once the ADRDY flag has been set. + (##) ADC_FLAG_ADDIS : This flag is cleared once the ADC is effectively + disabled. + (##) ADC_FLAG_ADSTART : This flag is cleared after the execution of + ADC_StopOfConversion() function, at the same time as the ADSTP bit is + cleared by hardware + (##) ADC_FLAG_ADSTP : This flag is cleared by hardware when the conversion + is effectively discarded and the ADC is ready to accept a new start conversion + (##) ADC_FLAG_ADCAL : This flag is set once the calibration is complete. + + (+)Interrupts + (##) ADC_IT_ADRDY : specifies the interrupt source for ADC ready event. + + *** Flags and Interrupts for ADC channel conversion *** + ===================================================== + [..] + (+)Flags : + (##) ADC_FLAG_EOC : This flag is set by hardware at the end of each conversion + of a channel when a new data result is available in the data register + (##) ADC_FLAG_EOSEQ : This bit is set by hardware at the end of the conversion + of a sequence of channels selected by ADC_ChannelConfig() function. + (##) ADC_FLAG_EOSMP : This bit is set by hardware at the end of the sampling phase. + (##) ADC_FLAG_OVR : This flag is set by hardware when an overrun occurs, + meaning that a new conversion has complete while the EOC flag was already set. + + (+)Interrupts : + (##) ADC_IT_EOC : specifies the interrupt source for end of conversion event. + (##) ADC_IT_EOSEQ : specifies the interrupt source for end of sequence event. + (##) ADC_IT_EOSMP : specifies the interrupt source for end of sampling event. + (##) ADC_IT_OVR : specifies the interrupt source for Overrun detection + event. + + *** Flags and Interrupts for the Analog Watchdog *** + ================================================ + [..] + (+)Flags : + (##) ADC_FLAG_AWD: This flag is set by hardware when the converted + voltage crosses the values programmed thrsholds + + (+)Interrupts : + (##) ADC_IT_AWD : specifies the interrupt source for Analog watchdog + event. + + [..] The user should identify which mode will be used in his application to + manage the ADC controller events: Polling mode or Interrupt mode. + + [..] In the Polling Mode it is advised to use the following functions: + (+) ADC_GetFlagStatus() : to check if flags events occur. + (+) ADC_ClearFlag() : to clear the flags events. + + [..] In the Interrupt Mode it is advised to use the following functions: + (+) ADC_ITConfig() : to enable or disable the interrupt source. + (+) ADC_GetITStatus() : to check if Interrupt occurs. + (+) ADC_ClearITPendingBit() : to clear the Interrupt pending Bit + (corresponding Flag). + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified ADC interrupts. + * @param ADCx: where x can be 1 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg ADC_IT_ADRDY: ADC ready interrupt + * @arg ADC_IT_EOSMP: End of sampling interrupt + * @arg ADC_IT_EOC: End of conversion interrupt + * @arg ADC_IT_EOSEQ: End of sequence of conversion interrupt + * @arg ADC_IT_OVR: overrun interrupt + * @arg ADC_IT_AWD: Analog watchdog interrupt + * @param NewState: new state of the specified ADC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_ADC_CONFIG_IT(ADC_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC interrupts */ + ADCx->IER |= ADC_IT; + } + else + { + /* Disable the selected ADC interrupts */ + ADCx->IER &= (~(uint32_t)ADC_IT); + } +} + +/** + * @brief Checks whether the specified ADC flag is set or not. + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param ADC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ADC_FLAG_AWD: Analog watchdog flag + * @arg ADC_FLAG_OVR: Overrun flag + * @arg ADC_FLAG_EOSEQ: End of Sequence flag + * @arg ADC_FLAG_EOC: End of conversion flag + * @arg ADC_FLAG_EOSMP: End of sampling flag + * @arg ADC_FLAG_ADRDY: ADC Ready flag + * @arg ADC_FLAG_ADEN: ADC enable flag + * @arg ADC_FLAG_ADDIS: ADC disable flag + * @arg ADC_FLAG_ADSTART: ADC start flag + * @arg ADC_FLAG_ADSTP: ADC stop flag + * @arg ADC_FLAG_ADCAL: ADC Calibration flag + * @retval The new state of ADC_FLAG (SET or RESET). + */ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); + + if((uint32_t)(ADC_FLAG & 0x01000000)) + { + tmpreg = ADCx->CR & 0xFEFFFFFF; + } + else + { + tmpreg = ADCx->ISR; + } + + /* Check the status of the specified ADC flag */ + if ((tmpreg & ADC_FLAG) != (uint32_t)RESET) + { + /* ADC_FLAG is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the ADC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx's pending flags. + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param ADC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_AWD: Analog watchdog flag + * @arg ADC_FLAG_EOC: End of conversion flag + * @arg ADC_FLAG_ADRDY: ADC Ready flag + * @arg ADC_FLAG_EOSMP: End of sampling flag + * @arg ADC_FLAG_EOSEQ: End of Sequence flag + * @arg ADC_FLAG_OVR: Overrun flag + * @retval None + */ +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); + + /* Clear the selected ADC flags */ + ADCx->ISR = (uint32_t)ADC_FLAG; +} + +/** + * @brief Checks whether the specified ADC interrupt has occurred or not. + * @param ADCx: where x can be 1 to select the ADC1 peripheral + * @param ADC_IT: specifies the ADC interrupt source to check. + * This parameter can be one of the following values: + * @arg ADC_IT_ADRDY: ADC ready interrupt + * @arg ADC_IT_EOSMP: End of sampling interrupt + * @arg ADC_IT_EOC: End of conversion interrupt + * @arg ADC_IT_EOSEQ: End of sequence of conversion interrupt + * @arg ADC_IT_OVR: overrun interrupt + * @arg ADC_IT_AWD: Analog watchdog interrupt + * @retval The new state of ADC_IT (SET or RESET). + */ +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_GET_IT(ADC_IT)); + + /* Get the ADC_IT enable bit status */ + enablestatus = (uint32_t)(ADCx->IER & ADC_IT); + + /* Check the status of the specified ADC interrupt */ + if (((uint32_t)(ADCx->ISR & ADC_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + /* ADC_IT is set */ + bitstatus = SET; + } + else + { + /* ADC_IT is reset */ + bitstatus = RESET; + } + /* Return the ADC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx's interrupt pending bits. + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param ADC_IT: specifies the ADC interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg ADC_IT_ADRDY: ADC ready interrupt + * @arg ADC_IT_EOSMP: End of sampling interrupt + * @arg ADC_IT_EOC: End of conversion interrupt + * @arg ADC_IT_EOSEQ: End of sequence of conversion interrupt + * @arg ADC_IT_OVR: overrun interrupt + * @arg ADC_IT_AWD: Analog watchdog interrupt + * @retval None + */ +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CLEAR_IT(ADC_IT)); + + /* Clear the selected ADC interrupt pending bits */ + ADCx->ISR = (uint32_t)ADC_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_can.c b/system/src/stm32f0-stdperiph/stm32f0xx_can.c new file mode 100644 index 0000000..e401e74 --- /dev/null +++ b/system/src/stm32f0-stdperiph/stm32f0xx_can.c @@ -0,0 +1,1631 @@ +/** + ****************************************************************************** + * @file stm32f0xx_can.c + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Controller area network (CAN) peripheral and + * applicable only for STM32F072 devices : + * + Initialization and Configuration + * + CAN Frames Transmission + * + CAN Frames Reception + * + Operation modes switch + * + Error management + * + Interrupts and flags + * + @verbatim + + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (#) Enable the CAN controller interface clock using + RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN, ENABLE); + (#) CAN pins configuration: + (++) Enable the clock for the CAN GPIOs using the following function: + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE); + (++) Connect the involved CAN pins to AF0 using the following function + GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx); + (++) Configure these CAN pins in alternate function mode by calling + the function GPIO_Init(); + (#) Initialise and configure the CAN using CAN_Init() and + CAN_FilterInit() functions. + (#) Transmit the desired CAN frame using CAN_Transmit() function. + (#) Check the transmission of a CAN frame using CAN_TransmitStatus() function. + (#) Cancel the transmission of a CAN frame using CAN_CancelTransmit() function. + (#) Receive a CAN frame using CAN_Recieve() function. + (#) Release the receive FIFOs using CAN_FIFORelease() function. + (#) Return the number of pending received frames using CAN_MessagePending() function. + (#) To control CAN events you can use one of the following two methods: + (++) Check on CAN flags using the CAN_GetFlagStatus() function. + (++) Use CAN interrupts through the function CAN_ITConfig() at initialization + phase and CAN_GetITStatus() function into interrupt routines to check + if the event has occurred or not. + After checking on a flag you should clear it using CAN_ClearFlag() + function. And after checking on an interrupt event you should clear it + using CAN_ClearITPendingBit() function. + + @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_can.h" +#include "stm32f0xx_rcc.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup CAN + * @brief CAN driver modules + * @{ + */ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* CAN Master Control Register bits */ +#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */ + +/* CAN Mailbox Transmit Request */ +#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ + +/* CAN Filter Master Register bits */ +#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */ + +/* Time out for INAK bit */ +#define INAK_TIMEOUT ((uint32_t)0x00FFFFFF) +/* Time out for SLAK bit */ +#define SLAK_TIMEOUT ((uint32_t)0x00FFFFFF) + +/* Flags in TSR register */ +#define CAN_FLAGS_TSR ((uint32_t)0x08000000) +/* Flags in RF1R register */ +#define CAN_FLAGS_RF1R ((uint32_t)0x04000000) +/* Flags in RF0R register */ +#define CAN_FLAGS_RF0R ((uint32_t)0x02000000) +/* Flags in MSR register */ +#define CAN_FLAGS_MSR ((uint32_t)0x01000000) +/* Flags in ESR register */ +#define CAN_FLAGS_ESR ((uint32_t)0x00F00000) + +/* Mailboxes definition */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02) + +#define CAN_MODE_MASK ((uint32_t) 0x00000003) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); + +/** @defgroup CAN_Private_Functions + * @{ + */ + +/** @defgroup CAN_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the CAN peripherals : Prescaler, operating mode, the maximum + number of time quanta to perform resynchronization, the number of time + quanta in Bit Segment 1 and 2 and many other modes. + (+) Configure the CAN reception filter. + (+) Select the start bank filter for slave CAN. + (+) Enable or disable the Debug Freeze mode for CAN. + (+) Enable or disable the CAN Time Trigger Operation communication mode. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the CAN peripheral registers to their default reset values. + * @param CANx: where x can be 1 to select the CAN peripheral. + * @retval None. + */ +void CAN_DeInit(CAN_TypeDef* CANx) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Enable CAN reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, ENABLE); + /* Release CAN from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, DISABLE); +} + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * @param CANx: where x can be 1 to select the CAN peripheral. + * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that contains + * the configuration information for the CAN peripheral. + * @retval Constant indicates initialization succeed which will be + * CAN_InitStatus_Failed or CAN_InitStatus_Success. + */ +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) +{ + uint8_t InitStatus = CAN_InitStatus_Failed; + uint32_t wait_ack = 0x00000000; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); + assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); + assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); + assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); + assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); + assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); + + /* Exit from sleep mode */ + CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP); + + /* Request initialisation */ + CANx->MCR |= CAN_MCR_INRQ ; + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + /* Check acknowledge */ + if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + /* Set the time triggered communication mode */ + if (CAN_InitStruct->CAN_TTCM == ENABLE) + { + CANx->MCR |= CAN_MCR_TTCM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM; + } + + /* Set the automatic bus-off management */ + if (CAN_InitStruct->CAN_ABOM == ENABLE) + { + CANx->MCR |= CAN_MCR_ABOM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM; + } + + /* Set the automatic wake-up mode */ + if (CAN_InitStruct->CAN_AWUM == ENABLE) + { + CANx->MCR |= CAN_MCR_AWUM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM; + } + + /* Set the no automatic retransmission */ + if (CAN_InitStruct->CAN_NART == ENABLE) + { + CANx->MCR |= CAN_MCR_NART; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_NART; + } + + /* Set the receive FIFO locked mode */ + if (CAN_InitStruct->CAN_RFLM == ENABLE) + { + CANx->MCR |= CAN_MCR_RFLM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM; + } + + /* Set the transmit FIFO priority */ + if (CAN_InitStruct->CAN_TXFP == ENABLE) + { + CANx->MCR |= CAN_MCR_TXFP; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP; + } + + /* Set the bit timing register */ + CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \ + ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \ + ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \ + ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \ + ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); + + /* Request leave initialisation */ + CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ; + + /* Wait the acknowledge */ + wait_ack = 0; + + while (((CANx->MSR & CAN_MSR_INAK) == (uint16_t)CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + /* ...and check acknowledged */ + if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + InitStatus = CAN_InitStatus_Success ; + } + } + + /* At this step, return the status of initialization */ + return InitStatus; +} + +/** + * @brief Configures the CAN reception filter according to the specified + * parameters in the CAN_FilterInitStruct. + * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef structure that + * contains the configuration information. + * @retval None + */ +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) +{ + uint32_t filter_number_bit_pos = 0; + /* Check the parameters */ + assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); + assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); + + filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; + + /* Initialisation mode for the filter */ + CAN->FMR |= FMR_FINIT; + + /* Filter Deactivation */ + CAN->FA1R &= ~(uint32_t)filter_number_bit_pos; + + /* Filter Scale */ + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) + { + /* 16-bit scale for the filter */ + CAN->FS1R &= ~(uint32_t)filter_number_bit_pos; + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); + } + + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) + { + /* 32-bit scale for the filter */ + CAN->FS1R |= filter_number_bit_pos; + /* 32-bit identifier or First 32-bit identifier */ + CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + /* 32-bit mask or Second 32-bit identifier */ + CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); + } + + /* Filter Mode */ + if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) + { + /*Id/Mask mode for the filter*/ + CAN->FM1R &= ~(uint32_t)filter_number_bit_pos; + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /*Identifier list mode for the filter*/ + CAN->FM1R |= (uint32_t)filter_number_bit_pos; + } + + /* Filter FIFO assignment */ + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) + { + /* FIFO 0 assignation for the filter */ + CAN->FFA1R &= ~(uint32_t)filter_number_bit_pos; + } + + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) + { + /* FIFO 1 assignation for the filter */ + CAN->FFA1R |= (uint32_t)filter_number_bit_pos; + } + + /* Filter activation */ + if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) + { + CAN->FA1R |= filter_number_bit_pos; + } + + /* Leave the initialisation mode for the filter */ + CAN->FMR &= ~FMR_FINIT; +} + +/** + * @brief Fills each CAN_InitStruct member with its default value. + * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which ill be initialized. + * @retval None + */ +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) +{ + /* Reset CAN init structure parameters values */ + + /* Initialize the time triggered communication mode */ + CAN_InitStruct->CAN_TTCM = DISABLE; + + /* Initialize the automatic bus-off management */ + CAN_InitStruct->CAN_ABOM = DISABLE; + + /* Initialize the automatic wake-up mode */ + CAN_InitStruct->CAN_AWUM = DISABLE; + + /* Initialize the no automatic retransmission */ + CAN_InitStruct->CAN_NART = DISABLE; + + /* Initialize the receive FIFO locked mode */ + CAN_InitStruct->CAN_RFLM = DISABLE; + + /* Initialize the transmit FIFO priority */ + CAN_InitStruct->CAN_TXFP = DISABLE; + + /* Initialize the CAN_Mode member */ + CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; + + /* Initialize the CAN_SJW member */ + CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; + + /* Initialize the CAN_BS1 member */ + CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; + + /* Initialize the CAN_BS2 member */ + CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; + + /* Initialize the CAN_Prescaler member */ + CAN_InitStruct->CAN_Prescaler = 1; +} + +/** + * @brief Select the start bank filter for slave CAN. + * @param CAN_BankNumber: Select the start slave bank filter from 1..27. + * @retval None + */ +void CAN_SlaveStartBank(uint8_t CAN_BankNumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber)); + + /* Enter Initialisation mode for the filter */ + CAN->FMR |= FMR_FINIT; + + /* Select the start slave bank */ + CAN->FMR &= (uint32_t)0xFFFFC0F1 ; + CAN->FMR |= (uint32_t)(CAN_BankNumber)<<8; + + /* Leave Initialisation mode for the filter */ + CAN->FMR &= ~FMR_FINIT; +} + +/** + * @brief Enables or disables the DBG Freeze for CAN. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param NewState: new state of the CAN peripheral. + * This parameter can be: ENABLE (CAN reception/transmission is frozen + * during debug. Reception FIFOs can still be accessed/controlled normally) + * or DISABLE (CAN is working during debug). + * @retval None + */ +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Debug Freeze */ + CANx->MCR |= MCR_DBF; + } + else + { + /* Disable Debug Freeze */ + CANx->MCR &= ~MCR_DBF; + } +} + +/** + * @brief Enables or disables the CAN Time TriggerOperation communication mode. + * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be + * sent over the CAN bus. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param NewState: Mode new state. This parameter can be: ENABLE or DISABLE. + * When enabled, Time stamp (TIME[15:0]) value is sent in the last two + * data bytes of the 8-byte message: TIME[7:0] in data byte 6 and TIME[15:8] + * in data byte 7. + * @retval None + */ +void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the TTCM mode */ + CANx->MCR |= CAN_MCR_TTCM; + + /* Set TGT bits */ + CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT); + CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT); + CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT); + } + else + { + /* Disable the TTCM mode */ + CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM); + + /* Reset TGT bits */ + CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT); + CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT); + CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT); + } +} +/** + * @} + */ + + +/** @defgroup CAN_Group2 CAN Frames Transmission functions + * @brief CAN Frames Transmission functions + * +@verbatim + =============================================================================== + ##### CAN Frames Transmission functions ##### + =============================================================================== + [..] This section provides functions allowing to + (+) Initiate and transmit a CAN frame message (if there is an empty mailbox). + (+) Check the transmission status of a CAN Frame. + (+) Cancel a transmit request. + +@endverbatim + * @{ + */ + +/** + * @brief Initiates and transmits a CAN frame message. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data. + * @retval The number of the mailbox that is used for transmission or + * CAN_TxStatus_NoMailBox if there is no empty mailbox. + */ +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) +{ + uint8_t transmit_mailbox = 0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_IDTYPE(TxMessage->IDE)); + assert_param(IS_CAN_RTR(TxMessage->RTR)); + assert_param(IS_CAN_DLC(TxMessage->DLC)); + + /* Select one empty transmit mailbox */ + if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + { + transmit_mailbox = 0; + } + else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) + { + transmit_mailbox = 1; + } + else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) + { + transmit_mailbox = 2; + } + else + { + transmit_mailbox = CAN_TxStatus_NoMailBox; + } + + if (transmit_mailbox != CAN_TxStatus_NoMailBox) + { + /* Set up the Id */ + CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ; + if (TxMessage->IDE == CAN_Id_Standard) + { + assert_param(IS_CAN_STDID(TxMessage->StdId)); + CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \ + TxMessage->RTR); + } + else + { + assert_param(IS_CAN_EXTID(TxMessage->ExtId)); + CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \ + TxMessage->IDE | \ + TxMessage->RTR); + } + + /* Set up the DLC */ + TxMessage->DLC &= (uint8_t)0x0000000F; + CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0; + CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC; + + /* Set up the data field */ + CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | + ((uint32_t)TxMessage->Data[2] << 16) | + ((uint32_t)TxMessage->Data[1] << 8) | + ((uint32_t)TxMessage->Data[0])); + CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | + ((uint32_t)TxMessage->Data[6] << 16) | + ((uint32_t)TxMessage->Data[5] << 8) | + ((uint32_t)TxMessage->Data[4])); + /* Request transmission */ + CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ; + } + return transmit_mailbox; +} + +/** + * @brief Checks the transmission status of a CAN Frame. + * @param CANx: where x can be 1 to select the CAN peripheral. + * @param TransmitMailbox: the number of the mailbox that is used for transmission. + * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, + * CAN_TxStatus_Failed in an other case. + */ +uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) +{ + uint32_t state = 0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); + + switch (TransmitMailbox) + { + case (CAN_TXMAILBOX_0): + state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0); + break; + case (CAN_TXMAILBOX_1): + state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1); + break; + case (CAN_TXMAILBOX_2): + state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2); + break; + default: + state = CAN_TxStatus_Failed; + break; + } + switch (state) + { + /* transmit pending */ + case (0x0): state = CAN_TxStatus_Pending; + break; + /* transmit failed */ + case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed; + break; + case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed; + break; + case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed; + break; + /* transmit succeeded */ + case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok; + break; + case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok; + break; + case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok; + break; + default: state = CAN_TxStatus_Failed; + break; + } + return (uint8_t) state; +} + +/** + * @brief Cancels a transmit request. + * @param CANx: where x can be 1 to select the CAN peripheral. + * @param Mailbox: Mailbox number. + * @retval None + */ +void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); + /* abort transmission */ + switch (Mailbox) + { + case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0; + break; + case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1; + break; + case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2; + break; + default: + break; + } +} +/** + * @} + */ + + +/** @defgroup CAN_Group3 CAN Frames Reception functions + * @brief CAN Frames Reception functions + * +@verbatim + =============================================================================== + ##### CAN Frames Reception functions ##### + =============================================================================== + [..] This section provides functions allowing to + (+) Receive a correct CAN frame. + (+) Release a specified receive FIFO (2 FIFOs are available). + (+) Return the number of the pending received CAN frames. + +@endverbatim + * @{ + */ + +/** + * @brief Receives a correct CAN frame. + * @param CANx: where x can be 1 to select the CAN peripheral. + * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @param RxMessage: pointer to a structure receive frame which contains CAN Id, + * CAN DLC, CAN data and FMI number. + * @retval None + */ +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + /* Get the Id */ + RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR; + if (RxMessage->IDE == CAN_Id_Standard) + { + RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21); + } + else + { + RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3); + } + + RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR; + /* Get the DLC */ + RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR; + /* Get the FMI */ + RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8); + /* Get the data field */ + RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR; + RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8); + RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16); + RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24); + RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR; + RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8); + RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16); + RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24); + /* Release the FIFO */ + /* Release FIFO0 */ + if (FIFONumber == CAN_FIFO0) + { + CANx->RF0R |= CAN_RF0R_RFOM0; + } + /* Release FIFO1 */ + else /* FIFONumber == CAN_FIFO1 */ + { + CANx->RF1R |= CAN_RF1R_RFOM1; + } +} + +/** + * @brief Releases the specified receive FIFO. + * @param CANx: where x can be 1 to select the CAN peripheral. + * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1. + * @retval None + */ +void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + /* Release FIFO0 */ + if (FIFONumber == CAN_FIFO0) + { + CANx->RF0R |= CAN_RF0R_RFOM0; + } + /* Release FIFO1 */ + else /* FIFONumber == CAN_FIFO1 */ + { + CANx->RF1R |= CAN_RF1R_RFOM1; + } +} + +/** + * @brief Returns the number of pending received messages. + * @param CANx: where x can be 1 to select the CAN peripheral. + * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @retval NbMessage : which is the number of pending message. + */ +uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) +{ + uint8_t message_pending=0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + if (FIFONumber == CAN_FIFO0) + { + message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03); + } + else if (FIFONumber == CAN_FIFO1) + { + message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03); + } + else + { + message_pending = 0; + } + return message_pending; +} +/** + * @} + */ + + +/** @defgroup CAN_Group4 CAN Operation modes functions + * @brief CAN Operation modes functions + * +@verbatim + =============================================================================== + ##### CAN Operation modes functions ##### + =============================================================================== + [..] This section provides functions allowing to select the CAN Operation modes: + (+) sleep mode. + (+) normal mode. + (+) initialization mode. + +@endverbatim + * @{ + */ + + +/** + * @brief Selects the CAN Operation mode. + * @param CAN_OperatingMode: CAN Operating Mode. + * This parameter can be one of @ref CAN_OperatingMode_TypeDef enumeration. + * @retval status of the requested mode which can be: + * - CAN_ModeStatus_Failed: CAN failed entering the specific mode + * - CAN_ModeStatus_Success: CAN Succeed entering the specific mode + */ +uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode) +{ + uint8_t status = CAN_ModeStatus_Failed; + + /* Timeout for INAK or also for SLAK bits*/ + uint32_t timeout = INAK_TIMEOUT; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode)); + + if (CAN_OperatingMode == CAN_OperatingMode_Initialization) + { + /* Request initialisation */ + CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ); + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0)) + { + timeout--; + } + if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if (CAN_OperatingMode == CAN_OperatingMode_Normal) + { + /* Request leave initialisation and sleep mode and enter Normal mode */ + CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ)); + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0)) + { + timeout--; + } + if ((CANx->MSR & CAN_MODE_MASK) != 0) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if (CAN_OperatingMode == CAN_OperatingMode_Sleep) + { + /* Request Sleep mode */ + CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0)) + { + timeout--; + } + if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else + { + status = CAN_ModeStatus_Failed; + } + + return (uint8_t) status; +} + +/** + * @brief Enters the Sleep (low power) mode. + * @param CANx: where x can be 1 to select the CAN peripheral. + * @retval CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed otherwise. + */ +uint8_t CAN_Sleep(CAN_TypeDef* CANx) +{ + uint8_t sleepstatus = CAN_Sleep_Failed; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Request Sleep mode */ + CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); + + /* Sleep mode status */ + if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK) + { + /* Sleep mode not entered */ + sleepstatus = CAN_Sleep_Ok; + } + /* return sleep mode status */ + return (uint8_t)sleepstatus; +} + +/** + * @brief Wakes up the CAN peripheral from sleep mode . + * @param CANx: where x can be 1 to select the CAN peripheral. + * @retval CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed otherwise. + */ +uint8_t CAN_WakeUp(CAN_TypeDef* CANx) +{ + uint32_t wait_slak = SLAK_TIMEOUT; + uint8_t wakeupstatus = CAN_WakeUp_Failed; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Wake up request */ + CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP; + + /* Sleep mode status */ + while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00)) + { + wait_slak--; + } + if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK) + { + /* wake up done : Sleep mode exited */ + wakeupstatus = CAN_WakeUp_Ok; + } + /* return wakeup status */ + return (uint8_t)wakeupstatus; +} +/** + * @} + */ + + +/** @defgroup CAN_Group5 CAN Bus Error management functions + * @brief CAN Bus Error management functions + * +@verbatim + =============================================================================== + ##### CAN Bus Error management functions ##### + =============================================================================== + [..] This section provides functions allowing to + (+) Return the CANx's last error code (LEC). + (+) Return the CANx Receive Error Counter (REC). + (+) Return the LSB of the 9-bit CANx Transmit Error Counter(TEC). + [..] + (@) If TEC is greater than 255, The CAN is in bus-off state. + (@) If REC or TEC are greater than 96, an Error warning flag occurs. + (@) If REC or TEC are greater than 127, an Error Passive Flag occurs. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the CANx's last error code (LEC). + * @param CANx: where x can be 1 to select the CAN peripheral. + * @retval Error code: + * - CAN_ERRORCODE_NoErr: No Error + * - CAN_ERRORCODE_StuffErr: Stuff Error + * - CAN_ERRORCODE_FormErr: Form Error + * - CAN_ERRORCODE_ACKErr : Acknowledgment Error + * - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error + * - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error + * - CAN_ERRORCODE_CRCErr: CRC Error + * - CAN_ERRORCODE_SoftwareSetErr: Software Set Error + */ +uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx) +{ + uint8_t errorcode=0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the error code*/ + errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC); + + /* Return the error code*/ + return errorcode; +} + +/** + * @brief Returns the CANx Receive Error Counter (REC). + * @note In case of an error during reception, this counter is incremented + * by 1 or by 8 depending on the error condition as defined by the CAN + * standard. After every successful reception, the counter is + * decremented by 1 or reset to 120 if its value was higher than 128. + * When the counter value exceeds 127, the CAN controller enters the + * error passive state. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval CAN Receive Error Counter. + */ +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx) +{ + uint8_t counter=0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the Receive Error Counter*/ + counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24); + + /* Return the Receive Error Counter*/ + return counter; +} + + +/** + * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval LSB of the 9-bit CAN Transmit Error Counter. + */ +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx) +{ + uint8_t counter=0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ + counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16); + + /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ + return counter; +} +/** + * @} + */ + +/** @defgroup CAN_Group6 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + [..] This section provides functions allowing to configure the CAN Interrupts + and to get the status and clear flags and Interrupts pending bits. + [..] The CAN provides 14 Interrupts sources and 15 Flags: + + *** Flags *** + ============= + [..] The 15 flags can be divided on 4 groups: + (+) Transmit Flags: + (++) CAN_FLAG_RQCP0. + (++) CAN_FLAG_RQCP1. + (++) CAN_FLAG_RQCP2: Request completed MailBoxes 0, 1 and 2 Flags + Set when when the last request (transmit or abort) has + been performed. + (+) Receive Flags: + (++) CAN_FLAG_FMP0. + (++) CAN_FLAG_FMP1: FIFO 0 and 1 Message Pending Flags; + Set to signal that messages are pending in the receive FIFO. + These Flags are cleared only by hardware. + (++) CAN_FLAG_FF0. + (++) CAN_FLAG_FF1: FIFO 0 and 1 Full Flags; + Set when three messages are stored in the selected FIFO. + (++) CAN_FLAG_FOV0. + (++) CAN_FLAG_FOV1: FIFO 0 and 1 Overrun Flags; + Set when a new message has been received and passed the filter + while the FIFO was full. + (+) Operating Mode Flags: + (++) CAN_FLAG_WKU: Wake up Flag; + Set to signal that a SOF bit has been detected while the CAN + hardware was in Sleep mode. + (++) CAN_FLAG_SLAK: Sleep acknowledge Flag; + Set to signal that the CAN has entered Sleep Mode. + (+) Error Flags: + (++) CAN_FLAG_EWG: Error Warning Flag; + Set when the warning limit has been reached (Receive Error Counter + or Transmit Error Counter greater than 96). + This Flag is cleared only by hardware. + (++) CAN_FLAG_EPV: Error Passive Flag; + Set when the Error Passive limit has been reached (Receive Error + Counter or Transmit Error Counter greater than 127). + This Flag is cleared only by hardware. + (++) CAN_FLAG_BOF: Bus-Off Flag; + Set when CAN enters the bus-off state. The bus-off state is + entered on TEC overflow, greater than 255. + This Flag is cleared only by hardware. + (++) CAN_FLAG_LEC: Last error code Flag; + Set If a message has been transferred (reception or transmission) + with error, and the error code is hold. + + *** Interrupts *** + ================== + [..] The 14 interrupts can be divided on 4 groups: + (+) Transmit interrupt: + (++) CAN_IT_TME: Transmit mailbox empty Interrupt; + If enabled, this interrupt source is pending when no transmit + request are pending for Tx mailboxes. + (+) Receive Interrupts: + (++) CAN_IT_FMP0. + (++) CAN_IT_FMP1: FIFO 0 and FIFO1 message pending Interrupts; + If enabled, these interrupt sources are pending when messages + are pending in the receive FIFO. + The corresponding interrupt pending bits are cleared only by hardware. + (++) CAN_IT_FF0. + (++) CAN_IT_FF1: FIFO 0 and FIFO1 full Interrupts; + If enabled, these interrupt sources are pending when three messages + are stored in the selected FIFO. + (++) CAN_IT_FOV0. + (++) CAN_IT_FOV1: FIFO 0 and FIFO1 overrun Interrupts; + If enabled, these interrupt sources are pending when a new message + has been received and passed the filter while the FIFO was full. + (+) Operating Mode Interrupts: + (++) CAN_IT_WKU: Wake-up Interrupt; + If enabled, this interrupt source is pending when a SOF bit has + been detected while the CAN hardware was in Sleep mode. + (++) CAN_IT_SLK: Sleep acknowledge Interrupt: + If enabled, this interrupt source is pending when the CAN has + entered Sleep Mode. + (+) Error Interrupts: + (++) CAN_IT_EWG: Error warning Interrupt; + If enabled, this interrupt source is pending when the warning limit + has been reached (Receive Error Counter or Transmit Error Counter=96). + (++) CAN_IT_EPV: Error passive Interrupt; + If enabled, this interrupt source is pending when the Error Passive + limit has been reached (Receive Error Counter or Transmit Error Counter>127). + (++) CAN_IT_BOF: Bus-off Interrupt; + If enabled, this interrupt source is pending when CAN enters + the bus-off state. The bus-off state is entered on TEC overflow, + greater than 255. + This Flag is cleared only by hardware. + (++) CAN_IT_LEC: Last error code Interrupt; + If enabled, this interrupt source is pending when a message has + been transferred (reception or transmission) with error and the + error code is hold. + (++) CAN_IT_ERR: Error Interrupt; + If enabled, this interrupt source is pending when an error condition + is pending. + [..] Managing the CAN controller events: + The user should identify which mode will be used in his application to manage + the CAN controller events: Polling mode or Interrupt mode. + (+) In the Polling Mode it is advised to use the following functions: + (++) CAN_GetFlagStatus() : to check if flags events occur. + (++) CAN_ClearFlag() : to clear the flags events. + (+) In the Interrupt Mode it is advised to use the following functions: + (++) CAN_ITConfig() : to enable or disable the interrupt source. + (++) CAN_GetITStatus() : to check if Interrupt occurs. + (++) CAN_ClearITPendingBit() : to clear the Interrupt pending Bit + (corresponding Flag). + This function has no impact on CAN_IT_FMP0 and CAN_IT_FMP1 Interrupts + pending bits since there are cleared only by hardware. + +@endverbatim + * @{ + */ +/** + * @brief Enables or disables the specified CANx interrupts. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled. + * This parameter can be: + * @arg CAN_IT_TME: Transmit mailbox empty Interrupt + * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt + * @arg CAN_IT_FF0: FIFO 0 full Interrupt + * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt + * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt + * @arg CAN_IT_FF1: FIFO 1 full Interrupt + * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt + * @arg CAN_IT_WKU: Wake-up Interrupt + * @arg CAN_IT_SLK: Sleep acknowledge Interrupt + * @arg CAN_IT_EWG: Error warning Interrupt + * @arg CAN_IT_EPV: Error passive Interrupt + * @arg CAN_IT_BOF: Bus-off Interrupt + * @arg CAN_IT_LEC: Last error code Interrupt + * @arg CAN_IT_ERR: Error Interrupt + * @param NewState: new state of the CAN interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_IT(CAN_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected CANx interrupt */ + CANx->IER |= CAN_IT; + } + else + { + /* Disable the selected CANx interrupt */ + CANx->IER &= ~CAN_IT; + } +} +/** + * @brief Checks whether the specified CAN flag is set or not. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag + * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag + * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag + * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag + * @arg CAN_FLAG_FF0: FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag + * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag + * @arg CAN_FLAG_FF1: FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKU: Wake up Flag + * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag + * @arg CAN_FLAG_EWG: Error Warning Flag + * @arg CAN_FLAG_EPV: Error Passive Flag + * @arg CAN_FLAG_BOF: Bus-Off Flag + * @arg CAN_FLAG_LEC: Last error code Flag + * @retval The new state of CAN_FLAG (SET or RESET). + */ +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_GET_FLAG(CAN_FLAG)); + + + if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */ + { + /* Check the status of the specified CAN flag */ + if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + /* Return the CAN_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the CAN's pending flags. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_FLAG: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag + * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag + * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag + * @arg CAN_FLAG_FF0: FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag + * @arg CAN_FLAG_FF1: FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKU: Wake up Flag + * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag + * @arg CAN_FLAG_LEC: Last error code Flag + * @retval None + */ +void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + uint32_t flagtmp=0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG)); + + if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */ + { + /* Clear the selected CAN flags */ + CANx->ESR = (uint32_t)RESET; + } + else /* MSR or TSR or RF0R or RF1R */ + { + flagtmp = CAN_FLAG & 0x000FFFFF; + + if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET) + { + /* Receive Flags */ + CANx->RF0R = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET) + { + /* Receive Flags */ + CANx->RF1R = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET) + { + /* Transmit Flags */ + CANx->TSR = (uint32_t)(flagtmp); + } + else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */ + { + /* Operating mode Flags */ + CANx->MSR = (uint32_t)(flagtmp); + } + } +} + +/** + * @brief Checks whether the specified CANx interrupt has occurred or not. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the CAN interrupt source to check. + * This parameter can be one of the following values: + * @arg CAN_IT_TME: Transmit mailbox empty Interrupt + * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt + * @arg CAN_IT_FF0: FIFO 0 full Interrupt + * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt + * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt + * @arg CAN_IT_FF1: FIFO 1 full Interrupt + * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt + * @arg CAN_IT_WKU: Wake-up Interrupt + * @arg CAN_IT_SLK: Sleep acknowledge Interrupt + * @arg CAN_IT_EWG: Error warning Interrupt + * @arg CAN_IT_EPV: Error passive Interrupt + * @arg CAN_IT_BOF: Bus-off Interrupt + * @arg CAN_IT_LEC: Last error code Interrupt + * @arg CAN_IT_ERR: Error Interrupt + * @retval The current state of CAN_IT (SET or RESET). + */ +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + ITStatus itstatus = RESET; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_IT(CAN_IT)); + + /* check the interrupt enable bit */ + if((CANx->IER & CAN_IT) != RESET) + { + /* in case the Interrupt is enabled, .... */ + switch (CAN_IT) + { + case CAN_IT_TME: + /* Check CAN_TSR_RQCPx bits */ + itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2); + break; + case CAN_IT_FMP0: + /* Check CAN_RF0R_FMP0 bit */ + itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0); + break; + case CAN_IT_FF0: + /* Check CAN_RF0R_FULL0 bit */ + itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0); + break; + case CAN_IT_FOV0: + /* Check CAN_RF0R_FOVR0 bit */ + itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0); + break; + case CAN_IT_FMP1: + /* Check CAN_RF1R_FMP1 bit */ + itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1); + break; + case CAN_IT_FF1: + /* Check CAN_RF1R_FULL1 bit */ + itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1); + break; + case CAN_IT_FOV1: + /* Check CAN_RF1R_FOVR1 bit */ + itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1); + break; + case CAN_IT_WKU: + /* Check CAN_MSR_WKUI bit */ + itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI); + break; + case CAN_IT_SLK: + /* Check CAN_MSR_SLAKI bit */ + itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI); + break; + case CAN_IT_EWG: + /* Check CAN_ESR_EWGF bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF); + break; + case CAN_IT_EPV: + /* Check CAN_ESR_EPVF bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF); + break; + case CAN_IT_BOF: + /* Check CAN_ESR_BOFF bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF); + break; + case CAN_IT_LEC: + /* Check CAN_ESR_LEC bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC); + break; + case CAN_IT_ERR: + /* Check CAN_MSR_ERRI bit */ + itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI); + break; + default: + /* in case of error, return RESET */ + itstatus = RESET; + break; + } + } + else + { + /* in case the Interrupt is not enabled, return RESET */ + itstatus = RESET; + } + + /* Return the CAN_IT status */ + return itstatus; +} + +/** + * @brief Clears the CANx's interrupt pending bits. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg CAN_IT_TME: Transmit mailbox empty Interrupt + * @arg CAN_IT_FF0: FIFO 0 full Interrupt + * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt + * @arg CAN_IT_FF1: FIFO 1 full Interrupt + * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt + * @arg CAN_IT_WKU: Wake-up Interrupt + * @arg CAN_IT_SLK: Sleep acknowledge Interrupt + * @arg CAN_IT_EWG: Error warning Interrupt + * @arg CAN_IT_EPV: Error passive Interrupt + * @arg CAN_IT_BOF: Bus-off Interrupt + * @arg CAN_IT_LEC: Last error code Interrupt + * @arg CAN_IT_ERR: Error Interrupt + * @retval None + */ +void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_CLEAR_IT(CAN_IT)); + + switch (CAN_IT) + { + case CAN_IT_TME: + /* Clear CAN_TSR_RQCPx (rc_w1)*/ + CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2; + break; + case CAN_IT_FF0: + /* Clear CAN_RF0R_FULL0 (rc_w1)*/ + CANx->RF0R = CAN_RF0R_FULL0; + break; + case CAN_IT_FOV0: + /* Clear CAN_RF0R_FOVR0 (rc_w1)*/ + CANx->RF0R = CAN_RF0R_FOVR0; + break; + case CAN_IT_FF1: + /* Clear CAN_RF1R_FULL1 (rc_w1)*/ + CANx->RF1R = CAN_RF1R_FULL1; + break; + case CAN_IT_FOV1: + /* Clear CAN_RF1R_FOVR1 (rc_w1)*/ + CANx->RF1R = CAN_RF1R_FOVR1; + break; + case CAN_IT_WKU: + /* Clear CAN_MSR_WKUI (rc_w1)*/ + CANx->MSR = CAN_MSR_WKUI; + break; + case CAN_IT_SLK: + /* Clear CAN_MSR_SLAKI (rc_w1)*/ + CANx->MSR = CAN_MSR_SLAKI; + break; + case CAN_IT_EWG: + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ + break; + case CAN_IT_EPV: + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ + break; + case CAN_IT_BOF: + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ + break; + case CAN_IT_LEC: + /* Clear LEC bits */ + CANx->ESR = RESET; + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + break; + case CAN_IT_ERR: + /*Clear LEC bits */ + CANx->ESR = RESET; + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* @note BOFF, EPVF and EWGF Flags are cleared by hardware depending on the CAN Bus status*/ + break; + default: + break; + } +} + /** + * @} + */ + +/** + * @brief Checks whether the CAN interrupt has occurred or not. + * @param CAN_Reg: specifies the CAN interrupt register to check. + * @param It_Bit: specifies the interrupt source bit to check. + * @retval The new state of the CAN Interrupt (SET or RESET). + */ +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) +{ + ITStatus pendingbitstatus = RESET; + + if ((CAN_Reg & It_Bit) != (uint32_t)RESET) + { + /* CAN_IT is set */ + pendingbitstatus = SET; + } + else + { + /* CAN_IT is reset */ + pendingbitstatus = RESET; + } + return pendingbitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_cec.c b/system/src/stm32f0-stdperiph/stm32f0xx_cec.c new file mode 100644 index 0000000..fc2b33f --- /dev/null +++ b/system/src/stm32f0-stdperiph/stm32f0xx_cec.c @@ -0,0 +1,607 @@ +/** + ****************************************************************************** + * @file stm32f0xx_cec.c + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Consumer Electronics Control (CEC) peripheral + * applicable only on STM32F051, STM32F042 and STM32F072 devices: + * + Initialization and Configuration + * + Data transfers functions + * + Interrupts and flags management + * + * @verbatim + ============================================================================== + ##### CEC features ##### + ============================================================================== + [..] This device provides some features: + (#) Supports HDMI-CEC specification 1.4. + (#) Supports two source clocks(HSI/244 or LSE). + (#) Works in stop mode(without APB clock, but with CEC clock 32KHz). + It can genarate an interrupt in the CEC clock domain that the CPU + wakes up from the low power mode. + (#) Configurable Signal Free Time before of transmission start. The + number of nominal data bit periods waited before transmission can be + ruled by Hardware or Software. + (#) Configurable Peripheral Address (multi-addressing configuration). + (#) Supports listen mode.The CEC Messages addressed to different destination + can be received without interfering with CEC bus when Listen mode option is enabled. + (#) Configurable Rx-Tolerance(Standard and Extended tolerance margin). + (#) Error detection with configurable error bit generation. + (#) Arbitration lost error in the case of two CEC devices starting at the same time. + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure and program the CEC device, + follow steps below: + (#) The source clock can be configured using: + (++) RCC_CECCLKConfig(RCC_CECCLK_HSI_Div244) for HSI(Default) + (++) RCC_CECCLKConfig(RCC_CECCLK_LSE) for LSE. + (#) Enable CEC peripheral clock using RCC_APBPeriphClockCmd(RCC_APBPeriph_CEC, ENABLE). + (#) Peripherals alternate function. + (++) Connect the pin to the desired peripherals' Alternate Function (AF) using + GPIO_PinAFConfig() function. + (++) Configure the desired pin in alternate function by: + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF. + (++) Select the type open-drain and output speed via GPIO_OType + and GPIO_Speed members. + (++) Call GPIO_Init() function. + (#) Configure the Signal Free Time, Rx Tolerance, Stop reception generation + and Bit error generation using the CEC_Init() function. + The function CEC_Init() must be called when the CEC peripheral is disabled. + (#) Configure the CEC own address by calling the fuction CEC_OwnAddressConfig(). + (#) Optionally, you can configure the Listen mode using the function CEC_ListenModeCmd(). + (#) Enable the NVIC and the corresponding interrupt using the function + CEC_ITConfig() if you need to use interrupt mode. + CEC_ITConfig() must be called before enabling the CEC peripheral. + (#) Enable the CEC using the CEC_Cmd() function. + (#) Charge the first data byte in the TXDR register using CEC_SendDataByte(). + (#) Enable the transmission of the Byte of a CEC message using CEC_StartOfMessage() + (#) Transmit single data through the CEC peripheral using CEC_SendDataByte() + and Receive the last transmitted byte using CEC_ReceiveDataByte(). + (#) Enable the CEC_EndOfMessage() in order to indicate the last byte of the message. + [..] + (@) If the listen mode is enabled, Stop reception generation and Bit error generation + must be in reset state. + (@) If the CEC message consists of only 1 byte, the function CEC_EndOfMessage() + must be called before CEC_StartOfMessage(). + + @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_cec.h" +#include "stm32f0xx_rcc.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup CEC + * @brief CEC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define BROADCAST_ADDRESS ((uint32_t)0x0000F) +#define CFGR_CLEAR_MASK ((uint32_t)0x7000FE00) /* CFGR register Mask */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup CEC_Private_Functions + * @{ + */ + +/** @defgroup CEC_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to initialize: + (+) CEC own addresses + (+) CEC Signal Free Time + (+) CEC Rx Tolerance + (+) CEC Stop Reception + (+) CEC Bit Rising Error + (+) CEC Long Bit Period Error + [..] This section provides also a function to configure the CEC peripheral in Listen Mode. + Messages addressed to different destination can be received when Listen mode is + enabled without interfering with CEC bus. +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the CEC peripheral registers to their default reset values. + * @param None + * @retval None + */ +void CEC_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); +} + +/** + * @brief Initializes the CEC peripheral according to the specified parameters + * in the CEC_InitStruct. + * @note The CEC parameters must be configured before enabling the CEC peripheral. + * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that contains + * the configuration information for the specified CEC peripheral. + * @retval None + */ +void CEC_Init(CEC_InitTypeDef* CEC_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_CEC_SIGNAL_FREE_TIME(CEC_InitStruct->CEC_SignalFreeTime)); + assert_param(IS_CEC_RX_TOLERANCE(CEC_InitStruct->CEC_RxTolerance)); + assert_param(IS_CEC_STOP_RECEPTION(CEC_InitStruct->CEC_StopReception)); + assert_param(IS_CEC_BIT_RISING_ERROR(CEC_InitStruct->CEC_BitRisingError)); + assert_param(IS_CEC_LONG_BIT_PERIOD_ERROR(CEC_InitStruct->CEC_LongBitPeriodError)); + assert_param(IS_CEC_BDR_NO_GEN_ERROR(CEC_InitStruct->CEC_BRDNoGen)); + assert_param(IS_CEC_SFT_OPTION(CEC_InitStruct->CEC_SFTOption)); + + /* Get the CEC CFGR value */ + tmpreg = CEC->CFGR; + + /* Clear CFGR bits */ + tmpreg &= CFGR_CLEAR_MASK; + + /* Configure the CEC peripheral */ + tmpreg |= (CEC_InitStruct->CEC_SignalFreeTime | CEC_InitStruct->CEC_RxTolerance | + CEC_InitStruct->CEC_StopReception | CEC_InitStruct->CEC_BitRisingError | + CEC_InitStruct->CEC_LongBitPeriodError| CEC_InitStruct->CEC_BRDNoGen | + CEC_InitStruct->CEC_SFTOption); + + /* Write to CEC CFGR register */ + CEC->CFGR = tmpreg; +} + +/** + * @brief Fills each CEC_InitStruct member with its default value. + * @param CEC_InitStruct: pointer to a CEC_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void CEC_StructInit(CEC_InitTypeDef* CEC_InitStruct) +{ + CEC_InitStruct->CEC_SignalFreeTime = CEC_SignalFreeTime_Standard; + CEC_InitStruct->CEC_RxTolerance = CEC_RxTolerance_Standard; + CEC_InitStruct->CEC_StopReception = CEC_StopReception_Off; + CEC_InitStruct->CEC_BitRisingError = CEC_BitRisingError_Off; + CEC_InitStruct->CEC_LongBitPeriodError = CEC_LongBitPeriodError_Off; + CEC_InitStruct->CEC_BRDNoGen = CEC_BRDNoGen_Off; + CEC_InitStruct->CEC_SFTOption = CEC_SFTOption_Off; +} + +/** + * @brief Enables or disables the CEC peripheral. + * @param NewState: new state of the CEC peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CEC_Cmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the CEC peripheral */ + CEC->CR |= CEC_CR_CECEN; + } + else + { + /* Disable the CEC peripheral */ + CEC->CR &= ~CEC_CR_CECEN; + } +} + +/** + * @brief Enables or disables the CEC Listen Mode. + * @param NewState: new state of the Listen Mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CEC_ListenModeCmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Listen Mode */ + CEC->CFGR |= CEC_CFGR_LSTN; + } + else + { + /* Disable the Listen Mode */ + CEC->CFGR &= ~CEC_CFGR_LSTN; + } +} + +/** + * @brief Defines the Own Address of the CEC device. + * @param CEC_OwnAddress: The CEC own address. + * @retval None + */ +void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress) +{ + uint32_t tmp =0x00; + /* Check the parameters */ + assert_param(IS_CEC_ADDRESS(CEC_OwnAddress)); + tmp = 1 <<(CEC_OwnAddress + 16); + /* Set the CEC own address */ + CEC->CFGR |= tmp; +} + +/** + * @brief Clears the Own Address of the CEC device. + * @param CEC_OwnAddress: The CEC own address. + * @retval None + */ +void CEC_OwnAddressClear(void) +{ + /* Set the CEC own address */ + CEC->CFGR = 0x0; +} + +/** + * @} + */ + +/** @defgroup CEC_Group2 Data transfers functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### Data transfers functions ##### + =============================================================================== + [..] This section provides functions allowing the CEC data transfers.The read + access of the CEC_RXDR register can be done using the CEC_ReceiveData()function + and returns the Rx buffered value. Whereas a write access to the CEC_TXDR can be + done using CEC_SendData() function. +@endverbatim + * @{ + */ + +/** + * @brief Transmits single data through the CEC peripheral. + * @param Data: the data to transmit. + * @retval None + */ +void CEC_SendData(uint8_t Data) +{ + /* Transmit Data */ + CEC->TXDR = Data; +} + +/** + * @brief Returns the most recent received data by the CEC peripheral. + * @param None + * @retval The received data. + */ +uint8_t CEC_ReceiveData(void) +{ + /* Receive Data */ + return (uint8_t)(CEC->RXDR); +} + +/** + * @brief Starts a new message. + * @param None + * @retval None + */ +void CEC_StartOfMessage(void) +{ + /* Starts of new message */ + CEC->CR |= CEC_CR_TXSOM; +} + +/** + * @brief Transmits message with an EOM bit. + * @param None + * @retval None + */ +void CEC_EndOfMessage(void) +{ + /* The data byte will be transmitted with an EOM bit */ + CEC->CR |= CEC_CR_TXEOM; +} + +/** + * @} + */ + +/** @defgroup CEC_Group3 Interrupts and flags management functions + * @brief Interrupts and flags management functions +* +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + [..] This section provides functions allowing to configure the CEC Interrupts + sources and check or clear the flags or pending bits status. + [..] The user should identify which mode will be used in his application to manage + the communication: Polling mode or Interrupt mode. + + [..] In polling mode, the CEC can be managed by the following flags: + (+) CEC_FLAG_TXACKE : to indicate a missing acknowledge in transmission mode. + (+) CEC_FLAG_TXERR : to indicate an error occurs during transmission mode. + The initiator detects low impedance in the CEC line. + (+) CEC_FLAG_TXUDR : to indicate if an underrun error occurs in transmission mode. + The transmission is enabled while the software has not yet + loaded any value into the TXDR register. + (+) CEC_FLAG_TXEND : to indicate the end of successful transmission. + (+) CEC_FLAG_TXBR : to indicate the next transmission data has to be written to TXDR. + (+) CEC_FLAG_ARBLST : to indicate arbitration lost in the case of two CEC devices + starting at the same time. + (+) CEC_FLAG_RXACKE : to indicate a missing acknowledge in receive mode. + (+) CEC_FLAG_LBPE : to indicate a long bit period error generated during receive mode. + (+) CEC_FLAG_SBPE : to indicate a short bit period error generated during receive mode. + (+) CEC_FLAG_BRE : to indicate a bit rising error generated during receive mode. + (+) CEC_FLAG_RXOVR : to indicate if an overrun error occur while receiving a CEC message. + A byte is not yet received while a new byte is stored in the RXDR register. + (+) CEC_FLAG_RXEND : to indicate the end Of reception + (+) CEC_FLAG_RXBR : to indicate a new byte has been received from the CEC line and + stored into the RXDR buffer. + [..] + (@)In this Mode, it is advised to use the following functions: + FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG); + void CEC_ClearFlag(uint16_t CEC_FLAG); + + [..] In Interrupt mode, the CEC can be managed by the following interrupt sources: + (+) CEC_IT_TXACKE : to indicate a TX Missing acknowledge + (+) CEC_IT_TXACKE : to indicate a missing acknowledge in transmission mode. + (+) CEC_IT_TXERR : to indicate an error occurs during transmission mode. + The initiator detects low impedance in the CEC line. + (+) CEC_IT_TXUDR : to indicate if an underrun error occurs in transmission mode. + The transmission is enabled while the software has not yet + loaded any value into the TXDR register. + (+) CEC_IT_TXEND : to indicate the end of successful transmission. + (+) CEC_IT_TXBR : to indicate the next transmission data has to be written to TXDR register. + (+) CEC_IT_ARBLST : to indicate arbitration lost in the case of two CEC devices + starting at the same time. + (+) CEC_IT_RXACKE : to indicate a missing acknowledge in receive mode. + (+) CEC_IT_LBPE : to indicate a long bit period error generated during receive mode. + (+) CEC_IT_SBPE : to indicate a short bit period error generated during receive mode. + (+) CEC_IT_BRE : to indicate a bit rising error generated during receive mode. + (+) CEC_IT_RXOVR : to indicate if an overrun error occur while receiving a CEC message. + A byte is not yet received while a new byte is stored in the RXDR register. + (+) CEC_IT_RXEND : to indicate the end Of reception + (+) CEC_IT_RXBR : to indicate a new byte has been received from the CEC line and + stored into the RXDR buffer. + [..] + (@)In this Mode it is advised to use the following functions: + void CEC_ITConfig( uint16_t CEC_IT, FunctionalState NewState); + ITStatus CEC_GetITStatus(uint16_t CEC_IT); + void CEC_ClearITPendingBit(uint16_t CEC_IT); + + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the selected CEC interrupts. + * @param CEC_IT: specifies the CEC interrupt source to be enabled. + * This parameter can be any combination of the following values: + * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error + * @arg CEC_IT_TXERR: Tx Error. + * @arg CEC_IT_TXUDR: Tx-Buffer Underrun. + * @arg CEC_IT_TXEND: End of Transmission (successful transmission of the last byte). + * @arg CEC_IT_TXBR: Tx-Byte Request. + * @arg CEC_IT_ARBLST: Arbitration Lost + * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge + * @arg CEC_IT_LBPE: Rx Long period Error + * @arg CEC_IT_SBPE: Rx Short period Error + * @arg CEC_IT_BRE: Rx Bit Rising Error + * @arg CEC_IT_RXOVR: Rx Overrun. + * @arg CEC_IT_RXEND: End Of Reception + * @arg CEC_IT_RXBR: Rx-Byte Received + * @param NewState: new state of the selected CEC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CEC_ITConfig(uint16_t CEC_IT, FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_CEC_IT(CEC_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected CEC interrupt */ + CEC->IER |= CEC_IT; + } + else + { + CEC_IT =~CEC_IT; + /* Disable the selected CEC interrupt */ + CEC->IER &= CEC_IT; + } +} + +/** + * @brief Gets the CEC flag status. + * @param CEC_FLAG: specifies the CEC flag to check. + * This parameter can be one of the following values: + * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error + * @arg CEC_FLAG_TXERR: Tx Error. + * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun. + * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte). + * @arg CEC_FLAG_TXBR: Tx-Byte Request. + * @arg CEC_FLAG_ARBLST: Arbitration Lost + * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge + * @arg CEC_FLAG_LBPE: Rx Long period Error + * @arg CEC_FLAG_SBPE: Rx Short period Error + * @arg CEC_FLAG_BRE: Rx Bit Rissing Error + * @arg CEC_FLAG_RXOVR: Rx Overrun. + * @arg CEC_FLAG_RXEND: End Of Reception. + * @arg CEC_FLAG_RXBR: Rx-Byte Received. + * @retval The new state of CEC_FLAG (SET or RESET) + */ +FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG) +{ + FlagStatus bitstatus = RESET; + + assert_param(IS_CEC_GET_FLAG(CEC_FLAG)); + + /* Check the status of the specified CEC flag */ + if ((CEC->ISR & CEC_FLAG) != (uint16_t)RESET) + { + /* CEC flag is set */ + bitstatus = SET; + } + else + { + /* CEC flag is reset */ + bitstatus = RESET; + } + + /* Return the CEC flag status */ + return bitstatus; +} + +/** + * @brief Clears the CEC's pending flags. + * @param CEC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error + * @arg CEC_FLAG_TXERR: Tx Error + * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun + * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte). + * @arg CEC_FLAG_TXBR: Tx-Byte Request + * @arg CEC_FLAG_ARBLST: Arbitration Lost + * @arg CEC_FLAG_RXACKE: Rx Missing Acknowledge + * @arg CEC_FLAG_LBPE: Rx Long period Error + * @arg CEC_FLAG_SBPE: Rx Short period Error + * @arg CEC_FLAG_BRE: Rx Bit Rising Error + * @arg CEC_FLAG_RXOVR: Rx Overrun + * @arg CEC_FLAG_RXEND: End Of Reception + * @arg CEC_FLAG_RXBR: Rx-Byte Received + * @retval None + */ +void CEC_ClearFlag(uint32_t CEC_FLAG) +{ + assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG)); + + /* Clear the selected CEC flag */ + CEC->ISR = CEC_FLAG; +} + +/** + * @brief Checks whether the specified CEC interrupt has occurred or not. + * @param CEC_IT: specifies the CEC interrupt source to check. + * This parameter can be one of the following values: + * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error + * @arg CEC_IT_TXERR: Tx Error. + * @arg CEC_IT_TXUDR: Tx-Buffer Underrun. + * @arg CEC_IT_TXEND: End of transmission (successful transmission of the last byte). + * @arg CEC_IT_TXBR: Tx-Byte Request. + * @arg CEC_IT_ARBLST: Arbitration Lost. + * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge. + * @arg CEC_IT_LBPE: Rx Long period Error. + * @arg CEC_IT_SBPE: Rx Short period Error. + * @arg CEC_IT_BRE: Rx Bit Rising Error. + * @arg CEC_IT_RXOVR: Rx Overrun. + * @arg CEC_IT_RXEND: End Of Reception. + * @arg CEC_IT_RXBR: Rx-Byte Received + * @retval The new state of CEC_IT (SET or RESET). + */ +ITStatus CEC_GetITStatus(uint16_t CEC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_CEC_GET_IT(CEC_IT)); + + /* Get the CEC IT enable bit status */ + enablestatus = (CEC->IER & CEC_IT); + + /* Check the status of the specified CEC interrupt */ + if (((CEC->ISR & CEC_IT) != (uint32_t)RESET) && enablestatus) + { + /* CEC interrupt is set */ + bitstatus = SET; + } + else + { + /* CEC interrupt is reset */ + bitstatus = RESET; + } + + /* Return the CEC interrupt status */ + return bitstatus; +} + +/** + * @brief Clears the CEC's interrupt pending bits. + * @param CEC_IT: specifies the CEC interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error + * @arg CEC_IT_TXERR: Tx Error + * @arg CEC_IT_TXUDR: Tx-Buffer Underrun + * @arg CEC_IT_TXEND: End of Transmission + * @arg CEC_IT_TXBR: Tx-Byte Request + * @arg CEC_IT_ARBLST: Arbitration Lost + * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge + * @arg CEC_IT_LBPE: Rx Long period Error + * @arg CEC_IT_SBPE: Rx Short period Error + * @arg CEC_IT_BRE: Rx Bit Rising Error + * @arg CEC_IT_RXOVR: Rx Overrun + * @arg CEC_IT_RXEND: End Of Reception + * @arg CEC_IT_RXBR: Rx-Byte Received + * @retval None + */ +void CEC_ClearITPendingBit(uint16_t CEC_IT) +{ + assert_param(IS_CEC_IT(CEC_IT)); + + /* Clear the selected CEC interrupt pending bits */ + CEC->ISR = CEC_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_comp.c b/system/src/stm32f0-stdperiph/stm32f0xx_comp.c new file mode 100644 index 0000000..6154271 --- /dev/null +++ b/system/src/stm32f0-stdperiph/stm32f0xx_comp.c @@ -0,0 +1,408 @@ +/** + ****************************************************************************** + * @file stm32f0xx_comp.c + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the comparators (COMP1 and COMP2) peripheral + * applicable only on STM32F051 and STM32F072 devices: + * + Comparators configuration + * + Window mode control + * + * @verbatim + * + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + + The device integrates two analog comparators COMP1 and COMP2: + (+) The non inverting input is set to PA1 for COMP1 and to PA3 + for COMP2. + + (+) The inverting input can be selected among: DAC1_OUT, DAC2_OUT + 1/4 VREFINT, 1/2 VERFINT, 3/4 VREFINT, VREFINT, + I/O (PA0 for COMP1 and PA2 for COMP2) + + (+) The COMP output is internally is available using COMP_GetOutputLevel() + and can be set on GPIO pins: PA0, PA6, PA11 for COMP1 + and PA2, PA7, PA12 for COMP2 + + (+) The COMP output can be redirected to embedded timers (TIM1, TIM2 + and TIM3) + + (+) The two comparators COMP1 and COMP2 can be combined in window + mode and only COMP1 non inverting (PA1) can be used as non- + inverting input. + + (+) The two comparators COMP1 and COMP2 have interrupt capability + with wake-up from Sleep and Stop modes (through the EXTI controller). + COMP1 and COMP2 outputs are internally connected to EXTI Line 21 + and EXTI Line 22 respectively. + + + ##### How to configure the comparator ##### + =============================================================================== + [..] + This driver provides functions to configure and program the Comparators + of all STM32F0xx devices. + + [..] To use the comparator, perform the following steps: + + (#) Enable the SYSCFG APB clock to get write access to comparator + register using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); + + (#) Configure the comparator input in analog mode using GPIO_Init() + + (#) Configure the comparator output in alternate function mode + using GPIO_Init() and use GPIO_PinAFConfig() function to map the + comparator output to the GPIO pin + + (#) Configure the comparator using COMP_Init() function: + (++) Select the inverting input + (++) Select the output polarity + (++) Select the output redirection + (++) Select the hysteresis level + (++) Select the power mode + + (#) Enable the comparator using COMP_Cmd() function + + (#) If required enable the COMP interrupt by configuring and enabling + EXTI line in Interrupt mode and selecting the desired sensitivity + level using EXTI_Init() function. After that enable the comparator + interrupt vector using NVIC_Init() function. + + @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_comp.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup COMP + * @brief COMP driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* CSR register Mask */ +#define COMP_CSR_CLEAR_MASK ((uint32_t)0x00003FFE) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup COMP_Private_Functions + * @{ + */ + +/** @defgroup COMP_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes COMP peripheral registers to their default reset values. + * @note Deinitialization can't be performed if the COMP configuration is locked. + * To unlock the configuration, perform a system reset. + * @param None + * @retval None + */ +void COMP_DeInit(void) +{ + COMP->CSR = ((uint32_t)0x00000000); /*!< Set COMP_CSR register to reset value */ +} + +/** + * @brief Initializes the COMP peripheral according to the specified parameters + * in COMP_InitStruct + * @note If the selected comparator is locked, initialization can't be performed. + * To unlock the configuration, perform a system reset. + * @note By default, PA1 is selected as COMP1 non inverting input. + * To use PA4 as COMP1 non inverting input call COMP_SwitchCmd() after COMP_Init() + * @param COMP_Selection: the selected comparator. + * This parameter can be one of the following values: + * @arg COMP_Selection_COMP1: COMP1 selected + * @arg COMP_Selection_COMP2: COMP2 selected + * @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains + * the configuration information for the specified COMP peripheral. + * @retval None + */ +void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_COMP_ALL_PERIPH(COMP_Selection)); + assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_InvertingInput)); + assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_Output)); + assert_param(IS_COMP_OUTPUT_POL(COMP_InitStruct->COMP_OutputPol)); + assert_param(IS_COMP_HYSTERESIS(COMP_InitStruct->COMP_Hysteresis)); + assert_param(IS_COMP_MODE(COMP_InitStruct->COMP_Mode)); + + /*!< Get the COMP_CSR register value */ + tmpreg = COMP->CSR; + + /*!< Clear the COMP1SW1, COMPx_IN_SEL, COMPx_OUT_TIM_SEL, COMPx_POL, COMPx_HYST and COMPx_PWR_MODE bits */ + tmpreg &= (uint32_t) ~(COMP_CSR_CLEAR_MASK<COMP_InvertingInput value */ + /*!< Set COMPxOUTSEL bits according to COMP_InitStruct->COMP_Output value */ + /*!< Set COMPxPOL bit according to COMP_InitStruct->COMP_OutputPol value */ + /*!< Set COMPxHYST bits according to COMP_InitStruct->COMP_Hysteresis value */ + /*!< Set COMPxMODE bits according to COMP_InitStruct->COMP_Mode value */ + tmpreg |= (uint32_t)((COMP_InitStruct->COMP_InvertingInput | COMP_InitStruct->COMP_Output | + COMP_InitStruct->COMP_OutputPol | COMP_InitStruct->COMP_Hysteresis | + COMP_InitStruct->COMP_Mode)<CSR = tmpreg; +} + +/** + * @brief Fills each COMP_InitStruct member with its default value. + * @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct) +{ + COMP_InitStruct->COMP_InvertingInput = COMP_InvertingInput_1_4VREFINT; + COMP_InitStruct->COMP_Output = COMP_Output_None; + COMP_InitStruct->COMP_OutputPol = COMP_OutputPol_NonInverted; + COMP_InitStruct->COMP_Hysteresis = COMP_Hysteresis_No; + COMP_InitStruct->COMP_Mode = COMP_Mode_UltraLowPower; +} + +/** + * @brief Enable or disable the COMP peripheral. + * @note If the selected comparator is locked, enable/disable can't be performed. + * To unlock the configuration, perform a system reset. + * @param COMP_Selection: the selected comparator. + * This parameter can be one of the following values: + * @arg COMP_Selection_COMP1: COMP1 selected + * @arg COMP_Selection_COMP2: COMP2 selected + * @param NewState: new state of the COMP peripheral. + * This parameter can be: ENABLE or DISABLE. + * @note When enabled, the comparator compares the non inverting input with + * the inverting input and the comparison result is available on comparator output. + * @note When disabled, the comparator doesn't perform comparison and the + * output level is low. + * @retval None + */ +void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_COMP_ALL_PERIPH(COMP_Selection)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected COMP peripheral */ + COMP->CSR |= (uint32_t) (1<CSR &= (uint32_t)(~((uint32_t)1<CSR |= (uint32_t) (COMP_CSR_COMP1SW1); + } + else + { + /* Open SW1 switch */ + COMP->CSR &= (uint32_t)(~COMP_CSR_COMP1SW1); + } +} + +/** + * @brief Return the output level (high or low) of the selected comparator. + * @note The output level depends on the selected polarity. + * @note If the polarity is not inverted: + * - Comparator output is low when the non-inverting input is at a lower + * voltage than the inverting input + * - Comparator output is high when the non-inverting input is at a higher + * voltage than the inverting input + * @note If the polarity is inverted: + * - Comparator output is high when the non-inverting input is at a lower + * voltage than the inverting input + * - Comparator output is low when the non-inverting input is at a higher + * voltage than the inverting input + * @param COMP_Selection: the selected comparator. + * This parameter can be one of the following values: + * @arg COMP_Selection_COMP1: COMP1 selected + * @arg COMP_Selection_COMP2: COMP2 selected + * @retval Returns the selected comparator output level: low or high. + * + */ +uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection) +{ + uint32_t compout = 0x0; + + /* Check the parameters */ + assert_param(IS_COMP_ALL_PERIPH(COMP_Selection)); + + /* Check if selected comparator output is high */ + if ((COMP->CSR & (COMP_CSR_COMP1OUT<CSR |= (uint32_t) COMP_CSR_WNDWEN; + } + else + { + /* Disable the window mode */ + COMP->CSR &= (uint32_t)(~COMP_CSR_WNDWEN); + } +} + +/** + * @} + */ + +/** @defgroup COMP_Group3 COMP configuration locking function + * @brief COMP1 and COMP2 configuration locking function + * COMP1 and COMP2 configuration can be locked each separately. + * Unlocking is performed by system reset. + * +@verbatim + =============================================================================== + ##### Configuration Lock function ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Lock the selected comparator (COMP1/COMP2) configuration. + * @note Locking the configuration means that all control bits are read-only. + * To unlock the comparator configuration, perform a system reset. + * @param COMP_Selection: selects the comparator to be locked + * This parameter can be a value of the following values: + * @arg COMP_Selection_COMP1: COMP1 configuration is locked. + * @arg COMP_Selection_COMP2: COMP2 configuration is locked. + * @retval None + */ +void COMP_LockConfig(uint32_t COMP_Selection) +{ + /* Check the parameter */ + assert_param(IS_COMP_ALL_PERIPH(COMP_Selection)); + + /* Set the lock bit corresponding to selected comparator */ + COMP->CSR |= (uint32_t) (COMP_CSR_COMP1LOCK<
© COPYRIGHT 2014 STMicroelectronics
+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_crc.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup CRC + * @brief CRC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup CRC_Private_Functions + * @{ + */ + +/** @defgroup CRC_Group1 Configuration of the CRC computation unit functions + * @brief Configuration of the CRC computation unit functions + * +@verbatim + =============================================================================== + ##### CRC configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes CRC peripheral registers to their default reset values. + * @param None + * @retval None + */ +void CRC_DeInit(void) +{ + /* Set DR register to reset value */ + CRC->DR = 0xFFFFFFFF; + + /* Set the POL register to the reset value: 0x04C11DB7 */ + CRC->POL = 0x04C11DB7; + + /* Reset IDR register */ + CRC->IDR = 0x00; + + /* Set INIT register to reset value */ + CRC->INIT = 0xFFFFFFFF; + + /* Reset the CRC calculation unit */ + CRC->CR = CRC_CR_RESET; +} + +/** + * @brief Resets the CRC calculation unit and sets INIT register content in DR register. + * @param None + * @retval None + */ +void CRC_ResetDR(void) +{ + /* Reset CRC generator */ + CRC->CR |= CRC_CR_RESET; +} + +/** + * @brief Selects the polynomial size. This function is only applicable for + * STM32F072 devices. + * @param CRC_PolSize: Specifies the polynomial size. + * This parameter can be: + * @arg CRC_PolSize_7: 7-bit polynomial for CRC calculation + * @arg CRC_PolSize_8: 8-bit polynomial for CRC calculation + * @arg CRC_PolSize_16: 16-bit polynomial for CRC calculation + * @arg CRC_PolSize_32: 32-bit polynomial for CRC calculation + * @retval None + */ +void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize) +{ + uint32_t tmpcr = 0; + + /* Check the parameter */ + assert_param(IS_CRC_POL_SIZE(CRC_PolSize)); + + /* Get CR register value */ + tmpcr = CRC->CR; + + /* Reset POL_SIZE bits */ + tmpcr &= (uint32_t)~((uint32_t)CRC_CR_POLSIZE); + /* Set the polynomial size */ + tmpcr |= (uint32_t)CRC_PolSize; + + /* Write to CR register */ + CRC->CR = (uint32_t)tmpcr; +} + +/** + * @brief Selects the reverse operation to be performed on input data. + * @param CRC_ReverseInputData: Specifies the reverse operation on input data. + * This parameter can be: + * @arg CRC_ReverseInputData_No: No reverse operation is performed + * @arg CRC_ReverseInputData_8bits: reverse operation performed on 8 bits + * @arg CRC_ReverseInputData_16bits: reverse operation performed on 16 bits + * @arg CRC_ReverseInputData_32bits: reverse operation performed on 32 bits + * @retval None + */ +void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData) +{ + uint32_t tmpcr = 0; + + /* Check the parameter */ + assert_param(IS_CRC_REVERSE_INPUT_DATA(CRC_ReverseInputData)); + + /* Get CR register value */ + tmpcr = CRC->CR; + + /* Reset REV_IN bits */ + tmpcr &= (uint32_t)~((uint32_t)CRC_CR_REV_IN); + /* Set the reverse operation */ + tmpcr |= (uint32_t)CRC_ReverseInputData; + + /* Write to CR register */ + CRC->CR = (uint32_t)tmpcr; +} + +/** + * @brief Enables or disable the reverse operation on output data. + * The reverse operation on output data is performed on 32-bit. + * @param NewState: new state of the reverse operation on output data. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CRC_ReverseOutputDataCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable reverse operation on output data */ + CRC->CR |= CRC_CR_REV_OUT; + } + else + { + /* Disable reverse operation on output data */ + CRC->CR &= (uint32_t)~((uint32_t)CRC_CR_REV_OUT); + } +} + +/** + * @brief Initializes the INIT register. + * @note After resetting CRC calculation unit, CRC_InitValue is stored in DR register + * @param CRC_InitValue: Programmable initial CRC value + * @retval None + */ +void CRC_SetInitRegister(uint32_t CRC_InitValue) +{ + CRC->INIT = CRC_InitValue; +} + +/** + * @brief Initializes the polynomail coefficients. This function is only + * applicable for STM32F072 devices. + * @param CRC_Pol: Polynomial to be used for CRC calculation. + * @retval None + */ +void CRC_SetPolynomial(uint32_t CRC_Pol) +{ + CRC->POL = CRC_Pol; +} + +/** + * @} + */ + +/** @defgroup CRC_Group2 CRC computation of one/many 32-bit data functions + * @brief CRC computation of one/many 32-bit data functions + * +@verbatim + =============================================================================== + ##### CRC computation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Computes the 32-bit CRC of a given data word(32-bit). + * @param CRC_Data: data word(32-bit) to compute its CRC + * @retval 32-bit CRC + */ +uint32_t CRC_CalcCRC(uint32_t CRC_Data) +{ + CRC->DR = CRC_Data; + + return (CRC->DR); +} + +/** + * @brief Computes the 16-bit CRC of a given 16-bit data. This function is only + * applicable for STM32F072 devices. + * @param CRC_Data: data half-word(16-bit) to compute its CRC + * @retval 16-bit CRC + */ +uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data) +{ + *(uint16_t*)(CRC_BASE) = (uint16_t) CRC_Data; + + return (CRC->DR); +} + +/** + * @brief Computes the 8-bit CRC of a given 8-bit data. This function is only + * applicable for STM32F072 devices. + * @param CRC_Data: 8-bit data to compute its CRC + * @retval 8-bit CRC + */ +uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data) +{ + *(uint8_t*)(CRC_BASE) = (uint8_t) CRC_Data; + + return (CRC->DR); +} + +/** + * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). + * @param pBuffer: pointer to the buffer containing the data to be computed + * @param BufferLength: length of the buffer to be computed + * @retval 32-bit CRC + */ +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + for(index = 0; index < BufferLength; index++) + { + CRC->DR = pBuffer[index]; + } + return (CRC->DR); +} + +/** + * @brief Returns the current CRC value. + * @param None + * @retval 32-bit CRC + */ +uint32_t CRC_GetCRC(void) +{ + return (CRC->DR); +} + +/** + * @} + */ + +/** @defgroup CRC_Group3 CRC Independent Register (IDR) access functions + * @brief CRC Independent Register (IDR) access (write/read) functions + * +@verbatim + =============================================================================== + ##### CRC Independent Register (IDR) access functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Stores an 8-bit data in the Independent Data(ID) register. + * @param CRC_IDValue: 8-bit value to be stored in the ID register + * @retval None + */ +void CRC_SetIDRegister(uint8_t CRC_IDValue) +{ + CRC->IDR = CRC_IDValue; +} + +/** + * @brief Returns the 8-bit data stored in the Independent Data(ID) register + * @param None + * @retval 8-bit value of the ID register + */ +uint8_t CRC_GetIDRegister(void) +{ + return (CRC->IDR); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_crs.c b/system/src/stm32f0-stdperiph/stm32f0xx_crs.c new file mode 100644 index 0000000..2c21ba6 --- /dev/null +++ b/system/src/stm32f0-stdperiph/stm32f0xx_crs.c @@ -0,0 +1,466 @@ +/** + ****************************************************************************** + * @file stm32f0xx_crs.c + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of CRS peripheral applicable only on STM32F042 and + * STM32F072 devices: + * + Configuration of the CRS peripheral + * + Interrupts and flags management + * + * + * @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + + (+) Enable CRS AHB clock using RCC_APB1eriphClockCmd(RCC_APB1Periph_CRS, ENABLE) + function + + + @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_crs.h" +#include "stm32f0xx_rcc.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup CRS + * @brief CRS driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* CRS Flag Mask */ +#define FLAG_MASK ((uint32_t)0x700) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup CRS_Private_Functions + * @{ + */ + +/** @defgroup CRS_Group1 Configuration of the CRS functions + * @brief Configuration of the CRS functions + * +@verbatim + =============================================================================== + ##### CRS configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes CRS peripheral registers to their default reset values. + * @param None + * @retval None + */ +void CRS_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CRS, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CRS, DISABLE); +} + +/** + * @brief Adjusts the Internal High Speed 48 oscillator (HSI 48) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI48 RC. + * @note This function can be called only when the AUTOTRIMEN bit is reset. + * @param CRS_HSI48CalibrationValue: + * @retval None + */ +void CRS_AdjustHSI48CalibrationValue(uint8_t CRS_HSI48CalibrationValue) +{ + /* Clear TRIM[5:0] bits */ + CRS->CR &= ~CRS_CR_TRIM; + + /* Set the TRIM[5:0] bits according to CRS_HSI48CalibrationValue value */ + CRS->CR |= (uint32_t)((uint32_t)CRS_HSI48CalibrationValue << 8); + +} + +/** + * @brief Enables or disables the oscillator clock for frequency error counter. + * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. + * @param NewState: new state of the frequency error counter. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CRS_FrequencyErrorCounterCmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + CRS->CR |= CRS_CR_CEN; + } + else + { + CRS->CR &= ~CRS_CR_CEN; + } +} + +/** + * @brief Enables or disables the automatic hardware adjustement of TRIM bits. + * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. + * @param NewState: new state of the automatic trimming. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CRS_AutomaticCalibrationCmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + CRS->CR |= CRS_CR_AUTOTRIMEN; + } +else + { + CRS->CR &= ~CRS_CR_AUTOTRIMEN; + } +} + +/** + * @brief Generate the software synchronization event + * @param None + * @retval None + */ +void CRS_SoftwareSynchronizationGenerate(void) +{ + CRS->CR |= CRS_CR_SWSYNC; +} + +/** + * @brief Adjusts the Internal High Speed 48 oscillator (HSI 48) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI48 RC. + * @note This function can be called only when the CEN bit is reset. + * @param CRS_ReloadValue: specifies the HSI calibration trimming value. + * This parameter must be a number between 0 and . + * @retval None + */ +void CRS_FrequencyErrorCounterReload(uint32_t CRS_ReloadValue) +{ + + /* Clear RELOAD[15:0] bits */ + CRS->CFGR &= ~CRS_CFGR_RELOAD; + + /* Set the RELOAD[15:0] bits according to CRS_ReloadValue value */ + CRS->CFGR |= (uint32_t)CRS_ReloadValue; + +} + +/** + * @brief + * @note This function can be called only when the CEN bit is reset. + * @param CRS_ErrorLimitValue: specifies the HSI calibration trimming value. + * This parameter must be a number between 0 and . + * @retval None + */ +void CRS_FrequencyErrorLimitConfig(uint8_t CRS_ErrorLimitValue) +{ + /* Clear FELIM[7:0] bits */ + CRS->CFGR &= ~CRS_CFGR_FELIM; + + /* Set the FELIM[7:0] bits according to CRS_ErrorLimitValue value */ + CRS->CFGR |= (uint32_t)CRS_ErrorLimitValue; +} + +/** + * @brief + * @note This function can be called only when the CEN bit is reset. + * @param CRS_Prescaler: specifies the HSI calibration trimming value. + * This parameter can be one of the following values: + * @arg CRS_SYNC_Div1: + * @arg CRS_SYNC_Div2: + * @arg CRS_SYNC_Div4: + * @arg CRS_SYNC_Div8: + * @arg CRS_SYNC_Div16: + * @arg CRS_SYNC_Div32: + * @arg CRS_SYNC_Div64: + * @arg CRS_SYNC_Div128: + * @retval None + */ +void CRS_SynchronizationPrescalerConfig(uint32_t CRS_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_CRS_SYNC_DIV(CRS_Prescaler)); + + /* Clear SYNCDIV[2:0] bits */ + CRS->CFGR &= ~CRS_CFGR_SYNCDIV; + + /* Set the CRS_CFGR_SYNCDIV[2:0] bits according to CRS_Prescaler value */ + CRS->CFGR |= CRS_Prescaler; +} + +/** + * @brief + * @note This function can be called only when the CEN bit is reset. + * @param CRS_Source: . + * This parameter can be one of the following values: + * @arg CRS_SYNCSource_GPIO: + * @arg CRS_SYNCSource_LSE: + * @arg CRS_SYNCSource_USB: + * @retval None + */ +void CRS_SynchronizationSourceConfig(uint32_t CRS_Source) +{ + /* Check the parameters */ + assert_param(IS_CRS_SYNC_SOURCE(CRS_Source)); + + /* Clear SYNCSRC[1:0] bits */ + CRS->CFGR &= ~CRS_CFGR_SYNCSRC; + + /* Set the SYNCSRC[1:0] bits according to CRS_Source value */ + CRS->CFGR |= CRS_Source; +} + +/** + * @brief + * @note This function can be called only when the CEN bit is reset. + * @param CRS_Polarity: . + * This parameter can be one of the following values: + * @arg CRS_SYNCPolarity_Rising: + * @arg CRS_SYNCPolarity_Falling: + * @retval None + */ +void CRS_SynchronizationPolarityConfig(uint32_t CRS_Polarity) +{ + /* Check the parameters */ + assert_param(IS_CRS_SYNC_POLARITY(CRS_Polarity)); + + /* Clear SYNCSPOL bit */ + CRS->CFGR &= ~CRS_CFGR_SYNCPOL; + + /* Set the SYNCSPOL bits according to CRS_Polarity value */ + CRS->CFGR |= CRS_Polarity; +} + +/** + * @brief Returns the Relaod value. + * @param None + * @retval The reload value + */ +uint32_t CRS_GetReloadValue(void) +{ + return ((uint32_t)(CRS->CFGR & CRS_CFGR_RELOAD)); +} + +/** + * @brief Returns the HSI48 Calibration value. + * @param None + * @retval The reload value + */ +uint32_t CRS_GetHSI48CalibrationValue(void) +{ + return (((uint32_t)(CRS->CR & CRS_CR_TRIM)) >> 8); +} + +/** + * @brief Returns the frequency error capture. + * @param None + * @retval The frequency error capture value + */ +uint32_t CRS_GetFrequencyErrorValue(void) +{ + return ((uint32_t)(CRS->ISR & CRS_ISR_FECAP)); +} + +/** + * @brief Returns the frequency error direction. + * @param None + * @retval The frequency error direction. The returned value can be one + * of the following values: + * - 0x00: Up counting + * - 0x8000: Down counting + */ +uint32_t CRS_GetFrequencyErrorDirection(void) +{ + return ((uint32_t)(CRS->ISR & CRS_ISR_FEDIR)); +} + +/** @defgroup CRS_Group2 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== +@endverbatim + * @{ + */ +/** + * @brief Enables or disables the specified CRS interrupts. + * @param CRS_IT: specifies the RCC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CRS_IT_SYNCOK: + * @arg CRS_IT_SYNCWARN: + * @arg CRS_IT_ERR: + * @arg CRS_IT_ESYNC: + * @param NewState: new state of the specified CRS interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CRS_ITConfig(uint32_t CRS_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CRS_IT(CRS_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + CRS->CR |= CRS_IT; + } + else + { + CRS->CR &= ~CRS_IT; + } +} + +/** + * @brief Checks whether the specified CRS flag is set or not. + * @param CRS_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg CRS_FLAG_SYNCOK: + * @arg CRS_FLAG_SYNCWARN: + * @arg CRS_FLAG_ERR: + * @arg CRS_FLAG_ESYNC: + * @arg CRS_FLAG_TRIMOVF: + * @arg CRS_FLAG_SYNCERR: + * @arg CRS_FLAG_SYNCMISS: + * @retval The new state of CRS_FLAG (SET or RESET). + */ +FlagStatus CRS_GetFlagStatus(uint32_t CRS_FLAG) +{ + /* Check the parameters */ + assert_param(IS_CRS_FLAG(CRS_FLAG)); + + return ((FlagStatus)(CRS->ISR & CRS_FLAG)); +} + +/** + * @brief Clears the CRS specified FLAG. + * @param CRS_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg CRS_FLAG_SYNCOK: + * @arg CRS_FLAG_SYNCWARN: + * @arg CRS_FLAG_ERR: + * @arg CRS_FLAG_ESYNC: + * @arg CRS_FLAG_TRIMOVF: + * @arg CRS_FLAG_SYNCERR: + * @arg CRS_FLAG_SYNCMISS: + * @retval None + */ +void CRS_ClearFlag(uint32_t CRS_FLAG) +{ + /* Check the parameters */ + assert_param(IS_CRS_FLAG(CRS_FLAG)); + + if ((CRS_FLAG & FLAG_MASK)!= 0) + { + CRS->ICR |= CRS_ICR_ERRC; + } + else + { + CRS->ICR |= CRS_FLAG; + } +} + +/** + * @brief Checks whether the specified CRS IT pending bit is set or not. + * @param CRS_IT: specifies the IT pending bit to check. + * This parameter can be one of the following values: + * @arg CRS_IT_SYNCOK: + * @arg CRS_IT_SYNCWARN: + * @arg CRS_IT_ERR: + * @arg CRS_IT_ESYNC: + * @arg CRS_IT_TRIMOVF: + * @arg CRS_IT_SYNCERR: + * @arg CRS_IT_SYNCMISS: + * @retval The new state of CRS_IT (SET or RESET). + */ +ITStatus CRS_GetITStatus(uint32_t CRS_IT) +{ + /* Check the parameters */ + assert_param(IS_CRS_GET_IT(CRS_IT)); + + return ((ITStatus)(CRS->ISR & CRS_IT)); +} + +/** + * @brief Clears the CRS specified IT pending bi. + * @param CRS_FLAG: specifies the IT pending bi to clear. + * This parameter can be one of the following values: + * @arg CRS_IT_SYNCOK: + * @arg CRS_IT_SYNCWARN: + * @arg CRS_IT_ERR: + * @arg CRS_IT_ESYNC: + * @arg CRS_IT_TRIMOVF: + * @arg CRS_IT_SYNCERR: + * @arg CRS_IT_SYNCMISS: + * @retval None + */ +void CRS_ClearITPendingBit(uint32_t CRS_IT) +{ + /* Check the parameters */ + assert_param(IS_CRS_CLEAR_IT(CRS_IT)); + + if ((CRS_IT & FLAG_MASK)!= 0) + { + CRS->ICR |= CRS_ICR_ERRC; + } + else + { + CRS->ICR |= CRS_IT; + } +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_dac.c b/system/src/stm32f0-stdperiph/stm32f0xx_dac.c new file mode 100644 index 0000000..afb5b97 --- /dev/null +++ b/system/src/stm32f0-stdperiph/stm32f0xx_dac.c @@ -0,0 +1,692 @@ +/** + ****************************************************************************** + * @file stm32f0xx_dac.c + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Digital-to-Analog Converter (DAC) peripheral + * applicable only on STM32F051 and STM32F072 devices: + * + DAC channel configuration: trigger, output buffer, data format + * + DMA management + * + Interrupts and flags management + * + * @verbatim + * + =============================================================================== + ##### DAC Peripheral features ##### + =============================================================================== + [..] The device integrates two 12-bit Digital Analog Converters refered as + DAC channel1 with DAC_OUT1 (PA4) and DAC_OUT2 (PA5) as outputs. + + [..] Digital to Analog conversion can be non-triggered using DAC_Trigger_None + and DAC_OUTx is available once writing to DHRx register using + DAC_SetChannel1Data() or DAC_SetChannel2Data() + + [..] Digital to Analog conversion can be triggered by: + (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9. + The used pin (GPIOx_Pin9) must be configured in input mode. + + (#) Timers TRGO: TIM2, TIM3,TIM7, TIM6 and TIM15 + (DAC_Trigger_T2_TRGO, DAC_Trigger_T3_TRGO...) + The timer TRGO event should be selected using TIM_SelectOutputTrigger() + + (#) Software using DAC_Trigger_Software + + [..] Each DAC integrates an output buffer that can be used to + reduce the output impedance, and to drive external loads directly + without having to add an external operational amplifier. + To enable the output buffer use + DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable; + + [..] Refer to the device datasheet for more details about output impedance + value with and without output buffer. + + [..] DAC wave generation feature + Both DAC channels can be used to generate + 1- Noise wave using DAC_WaveGeneration_Noise + 2- Triangle wave using DAC_WaveGeneration_Triangle + + [..] The DAC data format can be: + (#) 8-bit right alignment using DAC_Align_8b_R + (#) 12-bit left alignment using DAC_Align_12b_L + (#) 12-bit right alignment using DAC_Align_12b_R + + [..] The analog output voltage on each DAC channel pin is determined + by the following equation: DAC_OUTx = VREF+ * DOR / 4095 + with DOR is the Data Output Register + VEF+ is the input voltage reference (refer to the device datasheet) + e.g. To set DAC_OUT1 to 0.7V, use + DAC_SetChannel1Data(DAC_Align_12b_R, 868); + Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V + + [..] A DMA1 request can be generated when an external trigger (but not + a software trigger) occurs if DMA1 requests are enabled using + DAC_DMACmd() + DMA1 requests are mapped as following: + (+) DAC channel1 is mapped on DMA1 channel3 which must be already + configured + (+) DAC channel2 is mapped on DMA1 channel4 which must be already + configured + + ##### How to use this driver ##### + =============================================================================== + [..] + (+) Enable DAC APB1 clock to get write access to DAC registers + using RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE) + + (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode + using GPIO_Init() function + + (+) Configure the DAC channel using DAC_Init() + + (+) Enable the DAC channel using DAC_Cmd() + + @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_dac.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup DAC + * @brief DAC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* CR register Mask */ +#define CR_CLEAR_MASK ((uint32_t)0x00000FFE) /* check the value of the mask */ + +/* DAC Dual Channels SWTRIG masks */ +#define DUAL_SWTRIG_SET ((uint32_t)0x00000003) /*!< Only applicable for STM32F072 devices */ +#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC) /*!< Only applicable for STM32F072 devices */ + +/* DHR registers offsets */ +#define DHR12R1_OFFSET ((uint32_t)0x00000008) +#define DHR12R2_OFFSET ((uint32_t)0x00000014) /*!< Only applicable for STM32F072 devices */ +#define DHR12RD_OFFSET ((uint32_t)0x00000020) /*!< Only applicable for STM32F072 devices */ + +/* DOR register offset */ +#define DOR_OFFSET ((uint32_t)0x0000002C) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup DAC_Private_Functions + * @{ + */ + +/** @defgroup DAC_Group1 DAC channels configuration + * @brief DAC channels configuration: trigger, output buffer, data format + * +@verbatim + =============================================================================== + ##### DAC channels configuration: trigger, output buffer, data format ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the DAC peripheral registers to their default reset values. + * @param None + * @retval None + */ +void DAC_DeInit(void) +{ + /* Enable DAC reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); + /* Release DAC from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); +} + +/** + * @brief Initializes the DAC peripheral according to the specified parameters + * in the DAC_InitStruct. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices + * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains + * the configuration information for the specified DAC channel. + * @retval None + */ +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + + /* Check the DAC parameters */ + assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); + assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); + assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); + +/*---------------------------- DAC CR Configuration --------------------------*/ + /* Get the DAC CR value */ + tmpreg1 = DAC->CR; + /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ + tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel); + /* Configure for the selected DAC channel: buffer output, trigger, + wave generation, mask/amplitude for wave generation */ + /* Set TSELx and TENx bits according to DAC_Trigger value */ + /* Set WAVEx bits according to DAC_WaveGeneration value */ + /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ + /* Set BOFFx bit according to DAC_OutputBuffer value */ + tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | \ + DAC_InitStruct->DAC_OutputBuffer); + /* Calculate CR register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << DAC_Channel; + /* Write to DAC CR */ + DAC->CR = tmpreg1; +} + +/** + * @brief Fills each DAC_InitStruct member with its default value. + * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) +{ +/*--------------- Reset DAC init structure parameters values -----------------*/ + /* Initialize the DAC_Trigger member */ + DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; + + /* Initialize the DAC_WaveGeneration member */ + DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; + + /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; + + /* Initialize the DAC_OutputBuffer member */ + DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; +} + +/** + * @brief Enables or disables the specified DAC channel. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices + * @param NewState: new state of the DAC channel. + * This parameter can be: ENABLE or DISABLE. + * @note When the DAC channel is enabled the trigger source can no more be modified. + * @retval None + */ +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DAC channel */ + DAC->CR |= (DAC_CR_EN1 << DAC_Channel); + } + else + { + /* Disable the selected DAC channel */ + DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel)); + } +} + +/** + * @brief Enables or disables the selected DAC channel software trigger. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices + * @param NewState: new state of the selected DAC channel software trigger. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable software trigger for the selected DAC channel */ + DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4); + } + else + { + /* Disable software trigger for the selected DAC channel */ + DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4)); + } +} + +/** + * @brief Enables or disables simultaneously the two DAC channels software triggers. + * This function is applicable only for STM32F072 devices. + * @param NewState: new state of the DAC channels software triggers. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable software trigger for both DAC channels */ + DAC->SWTRIGR |= DUAL_SWTRIG_SET; + } + else + { + /* Disable software trigger for both DAC channels */ + DAC->SWTRIGR &= DUAL_SWTRIG_RESET; + } +} + +/** + * @brief Enables or disables the selected DAC channel wave generation. + * This function is applicable only for STM32F072 devices. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_Wave: specifies the wave type to enable or disable. + * This parameter can be: + * @arg DAC_Wave_Noise: noise wave generation + * @arg DAC_Wave_Triangle: triangle wave generation + * @param NewState: new state of the selected DAC channel wave generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_WAVE(DAC_Wave)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected wave generation for the selected DAC channel */ + DAC->CR |= DAC_Wave << DAC_Channel; + } + else + { + /* Disable the selected wave generation for the selected DAC channel */ + DAC->CR &= ~(DAC_Wave << DAC_Channel); + } +} + +/** + * @brief Set the specified data holding register value for DAC channel1. + * @param DAC_Align: Specifies the data alignment for DAC channel1. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignment selected + * @arg DAC_Align_12b_L: 12bit left data alignment selected + * @arg DAC_Align_12b_R: 12bit right data alignment selected + * @param Data: Data to be loaded in the selected data holding register. + * @retval None + */ +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R1_OFFSET + DAC_Align; + + /* Set the DAC channel1 selected data holding register */ + *(__IO uint32_t *) tmp = Data; +} + +/** + * @brief Sets the specified data holding register value for DAC channel2. + * This function is applicable only for STM32F072 devices. + * @param DAC_Align: Specifies the data alignment for DAC channel2. + * This parameter can be: + * @arg DAC_Align_8b_R: 8bit right data alignment selected + * @arg DAC_Align_12b_L: 12bit left data alignment selected + * @arg DAC_Align_12b_R: 12bit right data alignment selected + * @param Data: Data to be loaded in the selected data holding register. + * @retval None + */ +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R2_OFFSET + DAC_Align; + + /* Set the DAC channel2 selected data holding register */ + *(__IO uint32_t *)tmp = Data; +} + +/** + * @brief Sets the specified data holding register value for dual channel DAC. + * This function is applicable only for STM32F072 devices. + * @param DAC_Align: Specifies the data alignment for dual channel DAC. + * This parameter can be: + * @arg DAC_Align_8b_R: 8bit right data alignment selected + * @arg DAC_Align_12b_L: 12bit left data alignment selected + * @arg DAC_Align_12b_R: 12bit right data alignment selected + * @param Data2: Data for DAC Channel2 to be loaded in the selected data holding register. + * @param Data1: Data for DAC Channel1 to be loaded in the selected data holding register. + * @note In dual mode, a unique register access is required to write in both + * DAC channels at the same time. + * @retval None + */ +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) +{ + uint32_t data = 0, tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data1)); + assert_param(IS_DAC_DATA(Data2)); + + /* Calculate and set dual DAC data holding register value */ + if (DAC_Align == DAC_Align_8b_R) + { + data = ((uint32_t)Data2 << 8) | Data1; + } + else + { + data = ((uint32_t)Data2 << 16) | Data1; + } + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12RD_OFFSET + DAC_Align; + + /* Set the dual DAC selected data holding register */ + *(__IO uint32_t *)tmp = data; +} + +/** + * @brief Returns the last data output value of the selected DAC channel. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices + * @retval The selected DAC channel data output value. + */ +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + + tmp = (uint32_t) DAC_BASE ; + tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); + + /* Returns the DAC channel data output register value */ + return (uint16_t) (*(__IO uint32_t*) tmp); +} + +/** + * @} + */ + +/** @defgroup DAC_Group2 DMA management functions + * @brief DMA management functions + * +@verbatim + =============================================================================== + ##### DMA management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified DAC channel DMA request. + * When enabled DMA1 is generated when an external trigger (EXTI Line9, + * TIM2, TIM3, TIM6 or TIM15 but not a software trigger) occurs + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices + * @param NewState: new state of the selected DAC channel DMA request. + * This parameter can be: ENABLE or DISABLE. + * @note The DAC channel1 is mapped on DMA1 channel3 which must be already configured. + * @note The DAC channel2 is mapped on DMA1 channel4 which must be already configured. + * @retval None + */ +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DAC channel DMA request */ + DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel); + } + else + { + /* Disable the selected DAC channel DMA request */ + DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel)); + } +} + +/** + * @} + */ + +/** @defgroup DAC_Group3 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified DAC interrupts. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices + * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @note The DMA underrun occurs when a second external trigger arrives before the + * acknowledgement for the first external trigger is received (first request). + * @param NewState: new state of the specified DAC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_DAC_IT(DAC_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected DAC interrupts */ + DAC->CR |= (DAC_IT << DAC_Channel); + } + else + { + /* Disable the selected DAC interrupts */ + DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel)); + } +} + +/** + * @brief Checks whether the specified DAC flag is set or not. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices + * @param DAC_FLAG: specifies the flag to check. + * This parameter can be only of the following value: + * @arg DAC_FLAG_DMAUDR: DMA underrun flag + * @note The DMA underrun occurs when a second external trigger arrives before the + * acknowledgement for the first external trigger is received (first request). + * @retval The new state of DAC_FLAG (SET or RESET). + */ +FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_FLAG(DAC_FLAG)); + + /* Check the status of the specified DAC flag */ + if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET) + { + /* DAC_FLAG is set */ + bitstatus = SET; + } + else + { + /* DAC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the DAC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DAC channel's pending flags. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices + * @param DAC_FLAG: specifies the flag to clear. + * This parameter can be of the following value: + * @arg DAC_FLAG_DMAUDR: DMA underrun flag + * @retval None + */ +void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_FLAG(DAC_FLAG)); + + /* Clear the selected DAC flags */ + DAC->SR = (DAC_FLAG << DAC_Channel); +} + +/** + * @brief Checks whether the specified DAC interrupt has occurred or not. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices + * @param DAC_IT: specifies the DAC interrupt source to check. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @note The DMA underrun occurs when a second external trigger arrives before the + * acknowledgement for the first external trigger is received (first request). + * @retval The new state of DAC_IT (SET or RESET). + */ +ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_IT(DAC_IT)); + + /* Get the DAC_IT enable bit status */ + enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ; + + /* Check the status of the specified DAC interrupt */ + if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus) + { + /* DAC_IT is set */ + bitstatus = SET; + } + else + { + /* DAC_IT is reset */ + bitstatus = RESET; + } + /* Return the DAC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the DAC channel's interrupt pending bits. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices + * @param DAC_IT: specifies the DAC interrupt pending bit to clear. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @retval None + */ +void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_IT(DAC_IT)); + + /* Clear the selected DAC interrupt pending bits */ + DAC->SR = (DAC_IT << DAC_Channel); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_dbgmcu.c b/system/src/stm32f0-stdperiph/stm32f0xx_dbgmcu.c new file mode 100644 index 0000000..223fdf6 --- /dev/null +++ b/system/src/stm32f0-stdperiph/stm32f0xx_dbgmcu.c @@ -0,0 +1,218 @@ +/** + ****************************************************************************** + * @file stm32f0xx_dbgmcu.c + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Debug MCU (DBGMCU) peripheral: + * + Device and Revision ID management + * + Peripherals Configuration + * @verbatim + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_dbgmcu.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup DBGMCU + * @brief DBGMCU driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup DBGMCU_Private_Functions + * @{ + */ + + +/** @defgroup DBGMCU_Group1 Device and Revision ID management functions + * @brief Device and Revision ID management functions + * +@verbatim + ============================================================================== + ##### Device and Revision ID management functions ##### + ============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Returns the device revision identifier. + * @param None + * @retval Device revision identifier + */ +uint32_t DBGMCU_GetREVID(void) +{ + return(DBGMCU->IDCODE >> 16); +} + +/** + * @brief Returns the device identifier. + * @param None + * @retval Device identifier + */ +uint32_t DBGMCU_GetDEVID(void) +{ + return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); +} + +/** + * @} + */ + +/** @defgroup DBGMCU_Group2 Peripherals Configuration functions + * @brief Peripherals Configuration + * +@verbatim + ============================================================================== + ##### Peripherals Configuration functions ##### + ============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures low power mode behavior when the MCU is in Debug mode. + * @param DBGMCU_Periph: specifies the low power mode. + * This parameter can be any combination of the following values: + * @arg DBGMCU_STOP: Keep debugger connection during STOP mode + * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode + * @param NewState: new state of the specified low power mode in Debug mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + DBGMCU->CR |= DBGMCU_Periph; + } + else + { + DBGMCU->CR &= ~DBGMCU_Periph; + } +} + + +/** + * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode. + * @param DBGMCU_Periph: specifies the APB1 peripheral. + * This parameter can be any combination of the following values: + * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted, + * not applicable for STM32F030 devices + * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted + * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted + * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted, + * applicable only for STM32F072 devices + * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted + * @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped + * when Core is halted. + * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted + * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted + * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped + * when Core is halted + * @arg DBGMCU_CAN1_STOP: Debug CAN1 stopped when Core is halted, + * applicable only for STM32F042 and STM32F072 devices + * @param NewState: new state of the specified APB1 peripheral in Debug mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + DBGMCU->APB1FZ |= DBGMCU_Periph; + } + else + { + DBGMCU->APB1FZ &= ~DBGMCU_Periph; + } +} + +/** + * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode. + * @param DBGMCU_Periph: specifies the APB2 peripheral. + * This parameter can be any combination of the following values: + * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted + * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted + * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted + * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted + * @param NewState: new state of the specified APB2 peripheral in Debug mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + DBGMCU->APB2FZ |= DBGMCU_Periph; + } + else + { + DBGMCU->APB2FZ &= ~DBGMCU_Periph; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_dma.c b/system/src/stm32f0-stdperiph/stm32f0xx_dma.c new file mode 100644 index 0000000..ef629e7 --- /dev/null +++ b/system/src/stm32f0-stdperiph/stm32f0xx_dma.c @@ -0,0 +1,891 @@ +/** + ****************************************************************************** + * @file stm32f0xx_dma.c + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access controller (DMA): + * + Initialization and Configuration + * + Data Counter + * + Interrupts and flags management + * + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable The DMA controller clock using + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) function for DMA1. + (#) Enable and configure the peripheral to be connected to the DMA channel + (except for internal SRAM / FLASH memories: no initialization is necessary). + (#) For a given Channel, program the Source and Destination addresses, + the transfer Direction, the Buffer Size, the Peripheral and Memory + Incrementation mode and Data Size, the Circular or Normal mode, + the channel transfer Priority and the Memory-to-Memory transfer + mode (if needed) using the DMA_Init() function. + (#) Enable the NVIC and the corresponding interrupt(s) using the function + DMA_ITConfig() if you need to use DMA interrupts. + (#) Enable the DMA channel using the DMA_Cmd() function. + (#) Activate the needed channel Request using PPP_DMACmd() function for + any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...) + The function allowing this operation is provided in each PPP peripheral + driver (ie. SPI_DMACmd for SPI peripheral). + (#) Optionally, you can configure the number of data to be transferred + when the channel is disabled (ie. after each Transfer Complete event + or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter(). + And you can get the number of remaining data to be transferred using + the function DMA_GetCurrDataCounter() at run time (when the DMA channel is + enabled and running). + (#) To control DMA events you can use one of the following two methods: + (##) Check on DMA channel flags using the function DMA_GetFlagStatus(). + (##) Use DMA interrupts through the function DMA_ITConfig() at initialization + phase and DMA_GetITStatus() function into interrupt routines in + communication phase. + After checking on a flag you should clear it using DMA_ClearFlag() + function. And after checking on an interrupt event you should + clear it using DMA_ClearITPendingBit() function. + @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_dma.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup DMA + * @brief DMA driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F) /* DMA Channel config registers Masks */ +#define FLAG_Mask ((uint32_t)0x10000000) /* DMA2 FLAG mask */ + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) +#define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) +#define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) +#define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) +#define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) +#define DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6)) /*!< Only applicable for STM32F072 and STM32F091 devices */ +#define DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7)) /*!< Only applicable for STM32F072 and STM32F091 devices */ + +/* DMA2 Channelx interrupt pending bit masks: Only applicable for STM32F091 devices */ +#define DMA2_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) +#define DMA2_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) +#define DMA2_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) +#define DMA2_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) +#define DMA2_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup DMA_Private_Functions + * @{ + */ + +/** @defgroup DMA_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This subsection provides functions allowing to initialize the DMA channel + source and destination addresses, incrementation and data sizes, transfer + direction, buffer size, circular/normal mode selection, memory-to-memory + mode selection and channel priority value. + [..] The DMA_Init() function follows the DMA configuration procedures as described + in reference manual (RM0091). +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the DMAy Channelx registers to their default reset + * values. + * @param DMAy_Channelx: where y can be 1 to select the DMA and + * x can be 1 to 7 for DMA1 to select the DMA Channel. + * @note Channel 6 and 7 are available only for STM32F072 devices. + * @retval None + */ +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + + /* Disable the selected DMAy Channelx */ + DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN); + + /* Reset DMAy Channelx control register */ + DMAy_Channelx->CCR = 0; + + /* Reset DMAy Channelx remaining bytes register */ + DMAy_Channelx->CNDTR = 0; + + /* Reset DMAy Channelx peripheral address register */ + DMAy_Channelx->CPAR = 0; + + /* Reset DMAy Channelx memory address register */ + DMAy_Channelx->CMAR = 0; + + if (DMAy_Channelx == DMA1_Channel1) + { + /* Reset interrupt pending bits for DMA1 Channel1 */ + DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK; + } + else if (DMAy_Channelx == DMA1_Channel2) + { + /* Reset interrupt pending bits for DMA1 Channel2 */ + DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK; + } + else if (DMAy_Channelx == DMA1_Channel3) + { + /* Reset interrupt pending bits for DMA1 Channel3 */ + DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK; + } + else if (DMAy_Channelx == DMA1_Channel4) + { + /* Reset interrupt pending bits for DMA1 Channel4 */ + DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK; + } + else if (DMAy_Channelx == DMA1_Channel5) + { + /* Reset interrupt pending bits for DMA1 Channel5 */ + DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK; + } + else if (DMAy_Channelx == DMA1_Channel6) + { + /* Reset interrupt pending bits for DMA1 Channel6 */ + DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK; + } + else if (DMAy_Channelx == DMA1_Channel7) + { + /* Reset interrupt pending bits for DMA1 Channel7 */ + DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK; + } + else if (DMAy_Channelx == DMA2_Channel1) + { + /* Reset interrupt pending bits for DMA2 Channel1 */ + DMA2->IFCR |= DMA2_CHANNEL1_IT_MASK; + } + else if (DMAy_Channelx == DMA2_Channel2) + { + /* Reset interrupt pending bits for DMA2 Channel2 */ + DMA2->IFCR |= DMA2_CHANNEL2_IT_MASK; + } + else if (DMAy_Channelx == DMA2_Channel3) + { + /* Reset interrupt pending bits for DMA2 Channel3 */ + DMA2->IFCR |= DMA2_CHANNEL3_IT_MASK; + } + else if (DMAy_Channelx == DMA2_Channel4) + { + /* Reset interrupt pending bits for DMA2 Channel4 */ + DMA2->IFCR |= DMA2_CHANNEL4_IT_MASK; + } + else + { + if (DMAy_Channelx == DMA2_Channel5) + { + /* Reset interrupt pending bits for DMA2 Channel5 */ + DMA2->IFCR |= DMA2_CHANNEL5_IT_MASK; + } + } +} + +/** + * @brief Initializes the DMAy Channelx according to the specified parameters + * in the DMA_InitStruct. + * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7 + * for DMA1 to select the DMA Channel and 1 to 5 for DMA2 to select the DMA Channel. + * @note DMA1 Channel 6 and 7 are available only for STM32F072 and STM32F091 devices. + * @note DMA2 Channel 1 to 5 are available only for STM32F091 devices. + * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); + assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); + assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); + assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); + assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); + +/*--------------------------- DMAy Channelx CCR Configuration ----------------*/ + /* Get the DMAy_Channelx CCR value */ + tmpreg = DMAy_Channelx->CCR; + + /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ + tmpreg &= CCR_CLEAR_MASK; + + /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ + /* Set DIR bit according to DMA_DIR value */ + /* Set CIRC bit according to DMA_Mode value */ + /* Set PINC bit according to DMA_PeripheralInc value */ + /* Set MINC bit according to DMA_MemoryInc value */ + /* Set PSIZE bits according to DMA_PeripheralDataSize value */ + /* Set MSIZE bits according to DMA_MemoryDataSize value */ + /* Set PL bits according to DMA_Priority value */ + /* Set the MEM2MEM bit according to DMA_M2M value */ + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + + /* Write to DMAy Channelx CCR */ + DMAy_Channelx->CCR = tmpreg; + +/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/ + /* Write to DMAy Channelx CNDTR */ + DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; + +/*--------------------------- DMAy Channelx CPAR Configuration ---------------*/ + /* Write to DMAy Channelx CPAR */ + DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; + +/*--------------------------- DMAy Channelx CMAR Configuration ---------------*/ + /* Write to DMAy Channelx CMAR */ + DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/** + * @brief Fills each DMA_InitStruct member with its default value. + * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) +{ +/*-------------- Reset DMA init structure parameters values ------------------*/ + /* Initialize the DMA_PeripheralBaseAddr member */ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + /* Initialize the DMA_MemoryBaseAddr member */ + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + /* Initialize the DMA_DIR member */ + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + /* Initialize the DMA_BufferSize member */ + DMA_InitStruct->DMA_BufferSize = 0; + /* Initialize the DMA_PeripheralInc member */ + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + /* Initialize the DMA_MemoryInc member */ + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + /* Initialize the DMA_PeripheralDataSize member */ + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + /* Initialize the DMA_MemoryDataSize member */ + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + /* Initialize the DMA_Mode member */ + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + /* Initialize the DMA_Priority member */ + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + /* Initialize the DMA_M2M member */ + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/** + * @brief Enables or disables the specified DMAy Channelx. + * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7 + * for DMA1 to select the DMA Channel and 1 to 5 for DMA2 to select the DMA Channel. + * @note DMA1 Channel 6 and 7 are available only for STM32F072 and STM32F091 devices. + * @note DMA2 Channel 1 to 5 are available only for STM32F091 devices. + * @param NewState: new state of the DMAy Channelx. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMAy Channelx */ + DMAy_Channelx->CCR |= DMA_CCR_EN; + } + else + { + /* Disable the selected DMAy Channelx */ + DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN); + } +} + +/** + * @brief Configure the DMAx channels remapping. + * @param DMAy: where x can be 1 or 2 to select the DMA peripheral. + * @param DMAy_CHx_RemapRequest: where y can be 1 or 2 to select the DMA and x can be 1 to 7 + * for DMA1 to select the DMA1 Channel and can be 1 to 5 for DMA2 to select the DMA2 Channel. + * @note This function is available only for STM32F091 devices. + * @retval None + */ +void DMA_RemapConfig(DMA_TypeDef* DMAy, uint32_t DMAx_CHy_RemapRequest) +{ + assert_param(IS_DMA_ALL_LIST(DMAy)); + + if (DMAy == DMA1) + { + assert_param(IS_DMA1_REMAP(DMAx_CHy_RemapRequest)); + } + else + { + assert_param(IS_DMA2_REMAP(DMAx_CHy_RemapRequest)); + } + + DMAy->RMPCR &= ~((uint32_t)0x0F << (uint32_t)((DMAx_CHy_RemapRequest >> 28) * 4)); + DMAy->RMPCR |= (uint32_t)(DMAx_CHy_RemapRequest & 0x0FFFFFFF); +} + +/** + * @} + */ + +/** @defgroup DMA_Group2 Data Counter functions + * @brief Data Counter functions + * +@verbatim + =============================================================================== + ##### Data Counter functions ##### + =============================================================================== + [..] This subsection provides function allowing to configure and read the buffer + size (number of data to be transferred).The DMA data counter can be written + only when the DMA channel is disabled (ie. after transfer complete event). + [..] The following function can be used to write the Channel data counter value: + (+) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t + DataNumber). + -@- It is advised to use this function rather than DMA_Init() in situations + where only the Data buffer needs to be reloaded. + [..] The DMA data counter can be read to indicate the number of remaining transfers + for the relative DMA channel. This counter is decremented at the end of each + data transfer and when the transfer is complete: + (+) If Normal mode is selected: the counter is set to 0. + (+) If Circular mode is selected: the counter is reloaded with the initial + value(configured before enabling the DMA channel). + [..] The following function can be used to read the Channel data counter value: + (+) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx). + +@endverbatim + * @{ + */ + +/** + * @brief Sets the number of data units in the current DMAy Channelx transfer. + * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7 + * for DMA1 to select the DMA Channel and 1 to 5 for DMA2 to select the DMA Channel. + * @note DMA1 Channel 6 and 7 are available only for STM32F072 and STM32F091 devices. + * @note DMA2 Channel 1 to 5 are available only for STM32F091 devices. + * @param DataNumber: The number of data units in the current DMAy Channelx + * transfer. + * @note This function can only be used when the DMAy_Channelx is disabled. + * @retval None. + */ +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + +/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/ + /* Write to DMAy Channelx CNDTR */ + DMAy_Channelx->CNDTR = DataNumber; +} + +/** + * @brief Returns the number of remaining data units in the current + * DMAy Channelx transfer. + * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7 + * for DMA1 to select the DMA Channel and 1 to 5 for DMA2 to select the DMA Channel. + * @note DMA1 Channel 6 and 7 are available only for STM32F072 and STM32F091 devices. + * @note DMA2 Channel 1 to 5 are available only for STM32F091 devices. + * @retval The number of remaining data units in the current DMAy Channelx + * transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + /* Return the number of remaining data units for DMAy Channelx */ + return ((uint16_t)(DMAy_Channelx->CNDTR)); +} + +/** + * @} + */ + +/** @defgroup DMA_Group3 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + [..] This subsection provides functions allowing to configure the DMA Interrupts + sources and check or clear the flags or pending bits status. + The user should identify which mode will be used in his application to manage + the DMA controller events: Polling mode or Interrupt mode. + *** Polling Mode *** + ==================== + [..] Each DMA channel can be managed through 4 event Flags:(y : DMA Controller + number x : DMA channel number ). + (#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred. + (#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred. + (#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred. + (#) DMAy_FLAG_GLx : to indicate that at least one of the events described + above occurred. + -@- Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the + same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx). + [..]In this Mode it is advised to use the following functions: + (+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG); + (+) void DMA_ClearFlag(uint32_t DMA_FLAG); + + *** Interrupt Mode *** + ====================== + [..] Each DMA channel can be managed through 4 Interrupts: + (+) Interrupt Source + (##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete + event. + (##) DMA_IT_HT : specifies the interrupt source for the Half-transfer Complete + event. + (##) DMA_IT_TE : specifies the interrupt source for the transfer errors event. + (##) DMA_IT_GL : to indicate that at least one of the interrupts described + above occurred. + -@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of + the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE). + [..]In this Mode it is advised to use the following functions: + (+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, + FunctionalState NewState); + (+) ITStatus DMA_GetITStatus(uint32_t DMA_IT); + (+) void DMA_ClearITPendingBit(uint32_t DMA_IT); + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified DMAy Channelx interrupts. + * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7 + * for DMA1 to select the DMA Channel and 1 to 5 for DMA2 to select the DMA Channel. + * @note DMA1 Channel 6 and 7 are available only for STM32F072 and STM32F091 devices. + * @note DMA2 Channel 1 to 5 are available only for STM32F091 devices. + * @param DMA_IT: specifies the DMA interrupts sources to be enabled + * or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @param NewState: new state of the specified DMA interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_DMA_CONFIG_IT(DMA_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA interrupts */ + DMAy_Channelx->CCR |= DMA_IT; + } + else + { + /* Disable the selected DMA interrupts */ + DMAy_Channelx->CCR &= ~DMA_IT; + } +} + +/** + * @brief Checks whether the specified DMAy Channelx flag is set or not. + * @param DMA_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. + * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. + * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. + * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. + * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. + * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. + * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. + * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. + * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. + * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. + * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. + * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. + * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. + * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. + * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. + * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. + * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. + * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. + * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. + * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. + * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag, applicable only for STM32FO91 devices. + * @note The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags + * relative to the same channel is set (Transfer Complete, Half-transfer + * Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or + * DMAy_FLAG_TEx). + * + * @retval The new state of DMA_FLAG (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_GET_FLAG(DMAy_FLAG)); + + /* Calculate the used DMAy */ + if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) + { + /* Get DMA2 ISR register value */ + tmpreg = DMA2->ISR ; + } + else + { + /* Get DMA1 ISR register value */ + tmpreg = DMA1->ISR ; + } + + /* Check the status of the specified DMAy flag */ + if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET) + { + /* DMAy_FLAG is set */ + bitstatus = SET; + } + else + { + /* DMAy_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the DMAy_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DMAy Channelx's pending flags. + * @param DMA_FLAG: specifies the flag to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. + * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. + * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. + * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. + * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. + * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. + * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. + * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. + * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. + * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. + * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. + * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. + * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. + * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. + * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. + * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. + * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. + * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. + * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. + * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. + * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag, applicable only for STM32FO91 devices. + * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag, applicable only for STM32FO91 devices. + * + * @note Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags + * relative to the same channel (Transfer Complete, Half-transfer Complete and + * Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx). + * + * @retval None + */ +void DMA_ClearFlag(uint32_t DMAy_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG)); + +/* Calculate the used DMAy */ + if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) + { + /* Clear the selected DMAy flags */ + DMA2->IFCR = DMAy_FLAG; + } + else + { + /* Clear the selected DMAy flags */ + DMA1->IFCR = DMAy_FLAG; + } +} + +/** + * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not. + * @param DMA_IT: specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. + * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. + * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. + * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. + * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. + * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. + * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. + * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. + * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. + * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. + * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. + * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. + * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. + * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. + * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. + * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. + * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. + * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. + * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. + * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. + * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt, applicable only for STM32FO91 devices. + * @note The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other + * interrupts relative to the same channel is set (Transfer Complete, + * Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx, + * DMAy_IT_HTx or DMAy_IT_TEx). + * + * @retval The new state of DMA_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(uint32_t DMAy_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_GET_IT(DMAy_IT)); + + /* Calculate the used DMA */ + if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) + { + /* Get DMA2 ISR register value */ + tmpreg = DMA2->ISR; + } + else + { + /* Get DMA1 ISR register value */ + tmpreg = DMA1->ISR; + } + + /* Check the status of the specified DMAy interrupt */ + if ((tmpreg & DMAy_IT) != (uint32_t)RESET) + { + /* DMAy_IT is set */ + bitstatus = SET; + } + else + { + /* DMAy_IT is reset */ + bitstatus = RESET; + } + /* Return the DMAy_IT status */ + return bitstatus; +} + +/** + * @brief Clears the DMAy Channelx's interrupt pending bits. + * @param DMA_IT: specifies the DMA interrupt pending bit to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. + * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. + * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. + * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. + * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. + * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. + * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. + * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. + * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. + * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. + * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. + * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. + * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. + * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. + * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. + * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. + * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. + * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. + * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. + * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. + * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt, applicable only for STM32F072 and STM32FO91 devices. + * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt, applicable only for STM32FO91 devices. + * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt, applicable only for STM32FO91 devices. + * + * @note Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other + * interrupts relative to the same channel (Transfer Complete, Half-transfer + * Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and + * DMAy_IT_TEx). + * + * @retval None + */ +void DMA_ClearITPendingBit(uint32_t DMAy_IT) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_IT(DMAy_IT)); + + /* Calculate the used DMAy */ + if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) + { + /* Clear the selected DMAy interrupt pending bits */ + DMA2->IFCR = DMAy_IT; + } + else + { + /* Clear the selected DMAy interrupt pending bits */ + DMA1->IFCR = DMAy_IT; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_exti.c b/system/src/stm32f0-stdperiph/stm32f0xx_exti.c new file mode 100644 index 0000000..16f2ea3 --- /dev/null +++ b/system/src/stm32f0-stdperiph/stm32f0xx_exti.c @@ -0,0 +1,314 @@ +/** + ****************************************************************************** + * @file stm32f0xx_exti.c + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the EXTI peripheral: + * + Initialization and Configuration + * + Interrupts and flags management + * + * @verbatim + ============================================================================== + ##### EXTI features ##### + ============================================================================== + [..] External interrupt/event lines are mapped as following: + (#) All available GPIO pins are connected to the 16 external + interrupt/event lines from EXTI0 to EXTI15. + (#) EXTI line 16 is connected to the PVD output, not applicable for STM32F030 devices. + (#) EXTI line 17 is connected to the RTC Alarm event. + (#) EXTI line 18 is connected to the RTC Alarm event, applicable only for STM32F072 devices. + (#) EXTI line 19 is connected to the RTC Tamper and TimeStamp events. + (#) EXTI line 20 is connected to the RTC wakeup event, applicable only for STM32F072 devices. + (#) EXTI line 21 is connected to the Comparator 1 wakeup event, applicable only for STM32F051 and STM32F072 devices. + (#) EXTI line 22 is connected to the Comparator 2 wakeup event, applicable only for STM32F051 and STM32F072 devices. + (#) EXTI line 23 is connected to the I2C1 wakeup event, not applicable for STM32F030 devices. + (#) EXTI line 25 is connected to the USART1 wakeup event, not applicable for STM32F030 devices. + (#) EXTI line 26 is connected to the USART2 wakeup event, applicable only for STM32F072 devices. + (#) EXTI line 27 is connected to the CEC wakeup event, applicable only for STM32F051 and STM32F072 devices. + (#) EXTI line 31 is connected to the VDD USB monitor event, applicable only for STM32F072 devices. + + ##### How to use this driver ##### + ============================================================================== + [..] In order to use an I/O pin as an external interrupt source, follow + steps below: + (#) Configure the I/O in input mode using GPIO_Init() + (#) Select the input source pin for the EXTI line using + SYSCFG_EXTILineConfig(). + (#) Select the mode(interrupt, event) and configure the trigger selection + (Rising, falling or both) using EXTI_Init(). For the internal interrupt, + the trigger selection is not needed( the active edge is always the rising one). + (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init(). + (#) Optionally, you can generate a software interrupt using the function EXTI_GenerateSWInterrupt(). + [..] + (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx + registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); + @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_exti.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup EXTI + * @brief EXTI driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup EXTI_Private_Functions + * @{ + */ + +/** @defgroup EXTI_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and Configuration functions ##### + ============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the EXTI peripheral registers to their default reset + * values. + * @param None + * @retval None + */ +void EXTI_DeInit(void) +{ + EXTI->IMR = 0x0F940000; + EXTI->EMR = 0x00000000; + EXTI->RTSR = 0x00000000; + EXTI->FTSR = 0x00000000; + EXTI->PR = 0x006BFFFF; +} + +/** + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure that + * contains the configuration information for the EXTI peripheral. + * @retval None + */ +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); + assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); + assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); + + tmp = (uint32_t)EXTI_BASE; + + if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + /* Clear EXTI line configuration */ + EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; + + tmp += EXTI_InitStruct->EXTI_Mode; + + *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; + + /* Select the trigger for the selected interrupts */ + if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + /* Rising Falling edge */ + EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + + *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + + /* Disable the selected external lines */ + *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/** + * @brief Fills each EXTI_InitStruct member with its reset value. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param EXTI_Line: specifies the EXTI line on which the software interrupt + * will be generated. + * This parameter can be any combination of EXTI_Linex where x can be (0..27). + * @retval None + */ +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->SWIER |= EXTI_Line; +} + +/** + * @} + */ + +/** @defgroup EXTI_Group2 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + ============================================================================== + ##### Interrupts and flags management functions ##### + ============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param EXTI_Line: specifies the EXTI line flag to check. + * This parameter can be EXTI_Linex where x can be (0..27). + * @retval The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTI's line pending flags. + * @param EXTI_Line: specifies the EXTI lines flags to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..27). + * @retval None + */ +void EXTI_ClearFlag(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param EXTI_Line: specifies the EXTI line to check. + * This parameter can be EXTI_Linex where x can be (0..27). + * @retval The new state of EXTI_Line (SET or RESET). + */ +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTI's line pending bits. + * @param EXTI_Line: specifies the EXTI lines to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..27). + * @retval None + */ +void EXTI_ClearITPendingBit(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_flash.c b/system/src/stm32f0-stdperiph/stm32f0xx_flash.c new file mode 100644 index 0000000..54a8833 --- /dev/null +++ b/system/src/stm32f0-stdperiph/stm32f0xx_flash.c @@ -0,0 +1,1256 @@ +/** + ****************************************************************************** + * @file stm32f0xx_flash.c + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the FLASH peripheral: + * - FLASH Interface configuration + * - FLASH Memory Programming + * - Option Bytes Programming + * - Interrupts and flags management + * + * @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] This driver provides functions to configure and program the Flash + memory of all STM32F0xx devices. These functions are split in 4 groups + (#) FLASH Interface configuration functions: this group includes the + management of following features: + (++) Set the latency + (++) Enable/Disable the prefetch buffer + + (#) FLASH Memory Programming functions: this group includes all needed + functions to erase and program the main memory: + (++) Lock and Unlock the Flash interface. + (++) Erase function: Erase Page, erase all pages. + (++) Program functions: Half Word and Word write. + + (#) FLASH Option Bytes Programming functions: this group includes all + needed functions to: + (++) Lock and Unlock the Flash Option bytes. + (++) Launch the Option Bytes loader + (++) Erase the Option Bytes + (++)Set/Reset the write protection + (++) Set the Read protection Level + (++) Program the user option Bytes + (++) Set/Reset the BOOT1 bit + (++) Enable/Disable the VDDA Analog Monitoring + (++) Get the user option bytes + (++) Get the Write protection + (++) Get the read protection status + + (#) FLASH Interrupts and flag management functions: this group includes + all needed functions to: + (++) Enable/Disable the flash interrupt sources + (++) Get flags status + (++) Clear flags + (++) Get Flash operation status + (++) Wait for last flash operation + + @endverbatim + + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_flash.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup FLASH + * @brief FLASH driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup FLASH_Private_Functions + * @{ + */ + +/** @defgroup FLASH_Group1 FLASH Interface configuration functions + * @brief FLASH Interface configuration functions + * +@verbatim + =============================================================================== + ##### FLASH Interface configuration functions ##### + =============================================================================== + + [..] FLASH_Interface configuration_Functions, includes the following functions: + (+) void FLASH_SetLatency(uint32_t FLASH_Latency): + [..] To correctly read data from Flash memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock (HCLK) + [..] + +--------------------------------------------- + + | Wait states | HCLK clock frequency (MHz) | + |---------------|------------------------------| + |0WS(1CPU cycle)| 0 < HCLK <= 24 | + |---------------|------------------------------| + |1WS(2CPU cycle)| 24 < HCLK <= 48 | + +----------------------------------------------+ + [..] + (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState); + [..] + All these functions don't need the unlock sequence. + +@endverbatim + * @{ + */ + +/** + * @brief Sets the code latency value. + * @param FLASH_Latency: specifies the FLASH Latency value. + * This parameter can be one of the following values: + * @arg FLASH_Latency_0: FLASH Zero Latency cycle + * @arg FLASH_Latency_1: FLASH One Latency cycle + * @retval None + */ +void FLASH_SetLatency(uint32_t FLASH_Latency) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_LATENCY(FLASH_Latency)); + + /* Read the ACR register */ + tmpreg = FLASH->ACR; + + /* Sets the Latency value */ + tmpreg &= (uint32_t) (~((uint32_t)FLASH_ACR_LATENCY)); + tmpreg |= FLASH_Latency; + + /* Write the ACR register */ + FLASH->ACR = tmpreg; +} + +/** + * @brief Enables or disables the Prefetch Buffer. + * @param NewState: new state of the FLASH prefetch buffer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FLASH_PrefetchBufferCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if(NewState != DISABLE) + { + FLASH->ACR |= FLASH_ACR_PRFTBE; + } + else + { + FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_PRFTBE)); + } +} + +/** + * @brief Checks whether the FLASH Prefetch Buffer status is set or not. + * @param None + * @retval FLASH Prefetch Buffer Status (SET or RESET). + */ +FlagStatus FLASH_GetPrefetchBufferStatus(void) +{ + FlagStatus bitstatus = RESET; + + if ((FLASH->ACR & FLASH_ACR_PRFTBS) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */ + return bitstatus; +} + +/** + * @} + */ + +/** @defgroup FLASH_Group2 FLASH Memory Programming functions + * @brief FLASH Memory Programming functions + * +@verbatim + =============================================================================== + ##### FLASH Memory Programming functions ##### + =============================================================================== + + [..] The FLASH Memory Programming functions, includes the following functions: + (+) void FLASH_Unlock(void); + (+) void FLASH_Lock(void); + (+) FLASH_Status FLASH_ErasePage(uint32_t Page_Address); + (+) FLASH_Status FLASH_EraseAllPages(void); + (+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); + (+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); + + [..] Any operation of erase or program should follow these steps: + + (#) Call the FLASH_Unlock() function to enable the flash control register and + program memory access + (#) Call the desired function to erase page or program data + (#) Call the FLASH_Lock() to disable the flash program memory access + (recommended to protect the FLASH memory against possible unwanted operation) + +@endverbatim + * @{ + */ + +/** + * @brief Unlocks the FLASH control register and program memory access. + * @param None + * @retval None + */ +void FLASH_Unlock(void) +{ + if((FLASH->CR & FLASH_CR_LOCK) != RESET) + { + /* Unlocking the program memory access */ + FLASH->KEYR = FLASH_FKEY1; + FLASH->KEYR = FLASH_FKEY2; + } +} + +/** + * @brief Locks the Program memory access. + * @param None + * @retval None + */ +void FLASH_Lock(void) +{ + /* Set the LOCK Bit to lock the FLASH control register and program memory access */ + FLASH->CR |= FLASH_CR_LOCK; +} + +/** + * @brief Erases a specified page in program memory. + * @note To correctly run this function, the FLASH_Unlock() function must be called before. + * @note Call the FLASH_Lock() to disable the flash memory access (recommended + * to protect the FLASH memory against possible unwanted operation) + * @param Page_Address: The page address in program memory to be erased. + * @note A Page is erased in the Program memory only if the address to load + * is the start address of a page (multiple of 1024 bytes). + * @retval FLASH Status: The returned value can be: + * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ErasePage(uint32_t Page_Address) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(Page_Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + /* If the previous operation is completed, proceed to erase the page */ + FLASH->CR |= FLASH_CR_PER; + FLASH->AR = Page_Address; + FLASH->CR |= FLASH_CR_STRT; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + /* Disable the PER Bit */ + FLASH->CR &= ~FLASH_CR_PER; + } + + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases all FLASH pages. + * @note To correctly run this function, the FLASH_Unlock() function must be called before. + * @note Call the FLASH_Lock() to disable the flash memory access (recommended + * to protect the FLASH memory against possible unwanted operation) + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllPages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR |= FLASH_CR_MER; + FLASH->CR |= FLASH_CR_STRT; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + /* Disable the MER Bit */ + FLASH->CR &= ~FLASH_CR_MER; + } + + /* Return the Erase Status */ + return status; +} + +/** + * @brief Programs a word at a specified address. + * @note To correctly run this function, the FLASH_Unlock() function must be called before. + * @note Call the FLASH_Lock() to disable the flash memory access (recommended + * to protect the FLASH memory against possible unwanted operation) + * @param Address: specifies the address to be programmed. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + /* If the previous operation is completed, proceed to program the new first + half word */ + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint16_t*)Address = (uint16_t)Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + /* If the previous operation is completed, proceed to program the new second + half word */ + tmp = Address + 2; + + *(__IO uint16_t*) tmp = Data >> 16; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + /* Disable the PG Bit */ + FLASH->CR &= ~FLASH_CR_PG; + } + else + { + /* Disable the PG Bit */ + FLASH->CR &= ~FLASH_CR_PG; + } + } + + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a half word at a specified address. + * @note To correctly run this function, the FLASH_Unlock() function must be called before. + * @note Call the FLASH_Lock() to disable the flash memory access (recommended + * to protect the FLASH memory against possible unwanted operation) + * @param Address: specifies the address to be programmed. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + /* If the previous operation is completed, proceed to program the new data */ + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint16_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + /* Disable the PG Bit */ + FLASH->CR &= ~FLASH_CR_PG; + } + + /* Return the Program Status */ + return status; +} + +/** + * @} + */ + +/** @defgroup FLASH_Group3 Option Bytes Programming functions + * @brief Option Bytes Programming functions + * +@verbatim + =============================================================================== + ##### Option Bytes Programming functions ##### + =============================================================================== + + [..] The FLASH_Option Bytes Programming_functions, includes the following functions: + (+) void FLASH_OB_Unlock(void); + (+) void FLASH_OB_Lock(void); + (+) void FLASH_OB_Launch(void); + (+) FLASH_Status FLASH_OB_Erase(void); + (+) FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState); + (+) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP); + (+) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); + (+) FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1); + (+) FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG); + (+) FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER); + (+) FLASH_OB_ProgramData(uint32_t Address, uint8_t Data); + (+) uint8_t FLASH_OB_GetUser(void); + (+) uint32_t FLASH_OB_GetWRP(void); + (+) FlagStatus FLASH_OB_GetRDP(void); + + [..] Any operation of erase or program should follow these steps: + + (#) Call the FLASH_OB_Unlock() function to enable the Option Bytes registers access + + (#) Call one or several functions to program the desired option bytes + (++) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level + (++) FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) + => to Enable/Disable the desired sector write protection + (++) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) + => to configure the user option Bytes: IWDG, STOP and the Standby. + (++) FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1) + => to set or reset BOOT1 + (++) FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG) + => to enable or disable the VDDA Analog Monitoring + (++) You can write all User Options bytes at once using a single function + by calling FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER) + (++) FLASH_OB_ProgramData(uint32_t Address, uint8_t Data) to program the + two half word in the option bytes + + (#) Once all needed option bytes to be programmed are correctly written, call the + FLASH_OB_Launch(void) function to launch the Option Bytes programming process. + + (#) Call the FLASH_OB_Lock() to disable the Option Bytes registers access (recommended + to protect the option Bytes against possible unwanted operations) + +@endverbatim + * @{ + */ + +/** + * @brief Unlocks the option bytes block access. + * @param None + * @retval None + */ +void FLASH_OB_Unlock(void) +{ + if((FLASH->CR & FLASH_CR_OPTWRE) == RESET) + { + /* Unlocking the option bytes block access */ + FLASH->OPTKEYR = FLASH_OPTKEY1; + FLASH->OPTKEYR = FLASH_OPTKEY2; + } +} + +/** + * @brief Locks the option bytes block access. + * @param None + * @retval None + */ +void FLASH_OB_Lock(void) +{ + /* Set the OPTWREN Bit to lock the option bytes block access */ + FLASH->CR &= ~FLASH_CR_OPTWRE; +} + +/** + * @brief Launch the option byte loading. + * @param None + * @retval None + */ +void FLASH_OB_Launch(void) +{ + /* Set the OBL_Launch bit to launch the option byte loading */ + FLASH->CR |= FLASH_CR_OBL_LAUNCH; +} + +/** + * @brief Erases the FLASH option bytes. + * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before. + * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option + * bytes (recommended to protect the FLASH memory against possible unwanted operation) + * @note This functions erases all option bytes except the Read protection (RDP). + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_OB_Erase(void) +{ + uint16_t rdptmp = OB_RDP_Level_0; + + FLASH_Status status = FLASH_COMPLETE; + + /* Get the actual read protection Option Byte value */ + if(FLASH_OB_GetRDP() != RESET) + { + rdptmp = 0x00; + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + /* If the previous operation is completed, proceed to erase the option bytes */ + FLASH->CR |= FLASH_CR_OPTER; + FLASH->CR |= FLASH_CR_STRT; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + /* If the erase operation is completed, disable the OPTER Bit */ + FLASH->CR &= ~FLASH_CR_OPTER; + + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= FLASH_CR_OPTPG; + + /* Restore the last read protection Option Byte value */ + OB->RDP = (uint16_t)rdptmp; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= ~FLASH_CR_OPTPG; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTPG Bit */ + FLASH->CR &= ~FLASH_CR_OPTPG; + } + } + } + /* Return the erase status */ + return status; +} + +/** + * @brief Write protects the desired pages + * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before. + * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option + * bytes (recommended to protect the FLASH memory against possible unwanted operation) + * @param OB_WRP: specifies the address of the pages to be write protected. + * This parameter can be: + * @arg OB_WRP_Pages0to3..OB_WRP_Pages60to63 + * @arg OB_WRP_AllPages + * @retval FLASH Status: The returned value can be: + * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP) +{ + uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; + + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_WRP(OB_WRP)); + + OB_WRP = (uint32_t)(~OB_WRP); + WRP0_Data = (uint16_t)(OB_WRP & OB_WRP0_WRP0); + WRP1_Data = (uint16_t)((OB_WRP >> 8) & OB_WRP0_WRP0); + WRP2_Data = (uint16_t)((OB_WRP >> 16) & OB_WRP0_WRP0) ; + WRP3_Data = (uint16_t)((OB_WRP >> 24) & OB_WRP0_WRP0) ; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + FLASH->CR |= FLASH_CR_OPTPG; + + if(WRP0_Data != 0xFF) + { + OB->WRP0 = WRP0_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + } + if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF)) + { + OB->WRP1 = WRP1_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + } + if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF)) + { + OB->WRP2 = WRP2_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + } + if((status == FLASH_COMPLETE) && (WRP3_Data != 0xFF)) + { + OB->WRP3 = WRP3_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + } + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= ~FLASH_CR_OPTPG; + } + } + /* Return the write protection operation Status */ + return status; +} + +/** + * @brief Enables or disables the read out protection. + * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before. + * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option + * bytes (recommended to protect the FLASH memory against possible unwanted operation) + * @param FLASH_ReadProtection_Level: specifies the read protection level. + * This parameter can be: + * @arg OB_RDP_Level_0: No protection + * @arg OB_RDP_Level_1: Read protection of the memory + * @arg OB_RDP_Level_2: Chip protection + * @note When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 + * @retval FLASH Status: The returned value can be: + * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_RDP(OB_RDP)); + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + FLASH->CR |= FLASH_CR_OPTER; + FLASH->CR |= FLASH_CR_STRT; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + /* If the erase operation is completed, disable the OPTER Bit */ + FLASH->CR &= ~FLASH_CR_OPTER; + + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= FLASH_CR_OPTPG; + + OB->RDP = OB_RDP; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= ~FLASH_CR_OPTPG; + } + } + else + { + if(status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CR &= ~FLASH_CR_OPTER; + } + } + } + /* Return the protection operation Status */ + return status; +} + +/** + * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before. + * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option + * bytes (recommended to protect the FLASH memory against possible unwanted operation) + * @param OB_IWDG: Selects the WDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW: Software WDG selected + * @arg OB_IWDG_HW: Hardware WDG selected + * @param OB_STOP: Reset event when entering STOP mode. + * This parameter can be one of the following values: + * @arg OB_STOP_NoRST: No reset generated when entering in STOP + * @arg OB_STOP_RST: Reset generated when entering in STOP + * @param OB_STDBY: Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY + * @arg OB_STDBY_RST: Reset generated when entering in STANDBY + * @retval FLASH Status: The returned value can be: + * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); + assert_param(IS_OB_STOP_SOURCE(OB_STOP)); + assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= FLASH_CR_OPTPG; + + OB->USER = (uint16_t)((uint16_t)(OB_IWDG | OB_STOP) | (uint16_t)(OB_STDBY | 0xF8)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status != FLASH_TIMEOUT) + { + /* If the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= ~FLASH_CR_OPTPG; + } + } + /* Return the Option Byte program Status */ + return status; +} + +/** + * @brief Sets or resets the BOOT1 option bit. + * @param OB_BOOT1: Set or Reset the BOOT1 option bit. + * This parameter can be one of the following values: + * @arg OB_BOOT1_RESET: BOOT1 option bit reset + * @arg OB_BOOT1_SET: BOOT1 option bit set + * @retval None + */ +FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_BOOT1(OB_BOOT1)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= FLASH_CR_OPTPG; + + OB->USER = OB_BOOT1 | 0xEF; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status != FLASH_TIMEOUT) + { + /* If the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= ~FLASH_CR_OPTPG; + } + } + /* Return the Option Byte program Status */ + return status; +} + +/** + * @brief Sets or resets the BOOT0 option bit. + * @note This function is applicable only for the STM32F042 devices. + * @param OB_BOOT0: Set or Reset the BOOT0 option bit. + * This parameter can be one of the following values: + * @arg OB_BOOT0_RESET: BOOT0 option bit reset + * @arg OB_BOOT0_SET: BOOT0 option bit set + * @retval None + */ +FLASH_Status FLASH_OB_BOOT0Config(uint8_t OB_BOOT0) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_BOOT0(OB_BOOT0)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= FLASH_CR_OPTPG; + + OB->USER = OB_BOOT0 | 0xF7; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status != FLASH_TIMEOUT) + { + /* If the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= ~FLASH_CR_OPTPG; + } + } + /* Return the Option Byte program Status */ + return status; +} + +/** + * @brief Sets or resets the BOOT0SW option bit. + * @note This function is applicable only for the STM32F042 devices. + * @param OB_BOOT0SW: Set or Reset the BOOT0_SW option bit. + * This parameter can be one of the following values: + * @arg OB_BOOT0_SW: BOOT0_SW option bit reset + * @arg OB_BOOT0_HW: BOOT0_SW option bit set + * @retval None + */ +FLASH_Status FLASH_OB_BOOT0SWConfig(uint8_t OB_BOOT0SW) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_BOOT0SW(OB_BOOT0SW)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= FLASH_CR_OPTPG; + + OB->USER = OB_BOOT0SW | 0x7F; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status != FLASH_TIMEOUT) + { + /* If the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= ~FLASH_CR_OPTPG; + } + } + /* Return the Option Byte program Status */ + return status; +} + +/** + * @brief Sets or resets the analogue monitoring on VDDA Power source. + * @param OB_VDDA_ANALOG: Selects the analog monitoring on VDDA Power source. + * This parameter can be one of the following values: + * @arg OB_VDDA_ANALOG_ON: Analog monitoring on VDDA Power source ON + * @arg OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source OFF + * @retval None + */ +FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_VDDA_ANALOG(OB_VDDA_ANALOG)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= FLASH_CR_OPTPG; + + OB->USER = OB_VDDA_ANALOG | 0xDF; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= ~FLASH_CR_OPTPG; + } + } + /* Return the Option Byte program Status */ + return status; +} + +/** + * @brief Sets or resets the SRAM parity. + * @param OB_SRAM_Parity: Set or Reset the SRAM parity enable bit. + * This parameter can be one of the following values: + * @arg OB_SRAM_PARITY_SET: Set SRAM parity. + * @arg OB_SRAM_PARITY_RESET: Reset SRAM parity. + * @retval None + */ +FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_SRAM_PARITY(OB_SRAM_Parity)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= FLASH_CR_OPTPG; + + OB->USER = OB_SRAM_Parity | 0xBF; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= ~FLASH_CR_OPTPG; + } + } + /* Return the Option Byte program Status */ + return status; +} + +/** + * @brief Programs the FLASH User Option Byte: IWDG_SW, RST_STOP, RST_STDBY, + * BOOT1 and VDDA ANALOG monitoring. + * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before. + * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option + * bytes (recommended to protect the FLASH memory against possible unwanted operation) + * @param OB_USER: Selects all user option bytes + * This parameter is a combination of the following values: + * @arg OB_IWDG_SW / OB_IWDG_HW: Software / Hardware WDG selected + * @arg OB_STOP_NoRST / OB_STOP_RST: No reset / Reset generated when entering in STOP + * @arg OB_STDBY_NoRST / OB_STDBY_RST: No reset / Reset generated when entering in STANDBY + * @arg OB_BOOT1_RESET / OB_BOOT1_SET: BOOT1 Reset / Set + * @arg OB_VDDA_ANALOG_ON / OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source ON / OFF + * @arg OB_SRAM_PARITY_SET / OB_SRAM_PARITY_RESET: SRAM Parity SET / RESET + * @arg OB_BOOT0_RESET / OB_BOOT0_SET: BOOT0 Reset / Set + * @arg OB_BOOT0_SW / OB_BOOT0_SW: BOOT0 pin disabled / BOOT0 pin bonded with GPIO + * @retval FLASH Status: The returned value can be: + * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= FLASH_CR_OPTPG; + + OB->USER = OB_USER; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status != FLASH_TIMEOUT) + { + /* If the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= ~FLASH_CR_OPTPG; + } + } + /* Return the Option Byte program Status */ + return status; + +} + +/** + * @brief Programs a half word at a specified Option Byte Data address. + * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before. + * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option + * bytes (recommended to protect the FLASH memory against possible unwanted operation) + * @param Address: specifies the address to be programmed. + * This parameter can be 0x1FFFF804 or 0x1FFFF806. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_OB_ProgramData(uint32_t Address, uint8_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_OB_DATA_ADDRESS(Address)); + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + /* Enables the Option Bytes Programming operation */ + FLASH->CR |= FLASH_CR_OPTPG; + *(__IO uint16_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status != FLASH_TIMEOUT) + { + /* If the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= ~FLASH_CR_OPTPG; + } + } + /* Return the Option Byte Data Program Status */ + return status; +} + +/** + * @brief Returns the FLASH User Option Bytes values. + * @param None + * @retval The FLASH User Option Bytes . + */ +uint8_t FLASH_OB_GetUser(void) +{ + /* Return the User Option Byte */ + return (uint8_t)(FLASH->OBR >> 8); +} + +/** + * @brief Returns the FLASH Write Protection Option Bytes value. + * @param None + * @retval The FLASH Write Protection Option Bytes value + */ +uint32_t FLASH_OB_GetWRP(void) +{ + /* Return the FLASH write protection Register value */ + return (uint32_t)(FLASH->WRPR); +} + +/** + * @brief Checks whether the FLASH Read out Protection Status is set or not. + * @param None + * @retval FLASH ReadOut Protection Status(SET or RESET) + */ +FlagStatus FLASH_OB_GetRDP(void) +{ + FlagStatus readstatus = RESET; + + if ((uint8_t)(FLASH->OBR & (FLASH_OBR_RDPRT1 | FLASH_OBR_RDPRT2)) != RESET) + { + readstatus = SET; + } + else + { + readstatus = RESET; + } + return readstatus; +} + +/** + * @} + */ + +/** @defgroup FLASH_Group4 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified FLASH interrupts. + * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or + * disabled. + * This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP: FLASH end of programming Interrupt + * @arg FLASH_IT_ERR: FLASH Error Interrupt + * @retval None + */ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FLASH_IT(FLASH_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if(NewState != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CR |= FLASH_IT; + } + else + { + /* Disable the interrupt sources */ + FLASH->CR &= ~(uint32_t)FLASH_IT; + } +} + +/** + * @brief Checks whether the specified FLASH flag is set or not. + * @param FLASH_FLAG: specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag + * @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_EOP: FLASH End of Programming flag + * @retval The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)); + + if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the new state of FLASH_FLAG (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Clears the FLASH's pending flags. + * @param FLASH_FLAG: specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_EOP: FLASH End of Programming flag + * @retval None + */ +void FLASH_ClearFlag(uint32_t FLASH_FLAG) +{ + /* Check the parameters */ + assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)); + + /* Clear the flags */ + FLASH->SR = FLASH_FLAG; +} + +/** + * @brief Returns the FLASH Status. + * @param None + * @retval FLASH Status: The returned value can be: + * FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetStatus(void) +{ + FLASH_Status FLASHstatus = FLASH_COMPLETE; + + if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) + { + FLASHstatus = FLASH_BUSY; + } + else + { + if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00) + { + FLASHstatus = FLASH_ERROR_WRP; + } + else + { + if((FLASH->SR & (uint32_t)(FLASH_SR_PGERR)) != (uint32_t)0x00) + { + FLASHstatus = FLASH_ERROR_PROGRAM; + } + else + { + FLASHstatus = FLASH_COMPLETE; + } + } + } + /* Return the FLASH Status */ + return FLASHstatus; +} + + +/** + * @brief Waits for a FLASH operation to complete or a TIMEOUT to occur. + * @param Timeout: FLASH programming Timeout + * @retval FLASH Status: The returned value can be: FLASH_BUSY, + * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check for the FLASH Status */ + status = FLASH_GetStatus(); + + /* Wait for a FLASH operation to complete or a TIMEOUT to occur */ + while((status == FLASH_BUSY) && (Timeout != 0x00)) + { + status = FLASH_GetStatus(); + Timeout--; + } + + if(Timeout == 0x00 ) + { + status = FLASH_TIMEOUT; + } + /* Return the operation status */ + return status; +} + +/** + * @} + */ + +/** + * @} + */ + + /** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_gpio.c b/system/src/stm32f0-stdperiph/stm32f0xx_gpio.c new file mode 100644 index 0000000..5b6eb23 --- /dev/null +++ b/system/src/stm32f0-stdperiph/stm32f0xx_gpio.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file stm32f0xx_gpio.c + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the GPIO peripheral: + * + Initialization and Configuration functions + * + GPIO Read and Write functions + * + GPIO Alternate functions configuration functions + * + * @verbatim + * + * + =========================================================================== + ##### How to use this driver ##### + =========================================================================== + [..] + (#) Enable the GPIO AHB clock using RCC_AHBPeriphClockCmd() + (#) Configure the GPIO pin(s) using GPIO_Init() + Four possible configuration are available for each pin: + (++) Input: Floating, Pull-up, Pull-down. + (++) Output: Push-Pull (Pull-up, Pull-down or no Pull) + Open Drain (Pull-up, Pull-down or no Pull). + In output mode, the speed is configurable: Low, Medium, Fast or High. + (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) + Open Drain (Pull-up, Pull-down or no Pull). + (++) Analog: required mode when a pin is to be used as ADC channel, + DAC output or comparator input. + (#) Peripherals alternate function: + (++) For ADC, DAC and comparators, configure the desired pin in analog + mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN + (++) For other peripherals (TIM, USART...): + (+++) Connect the pin to the desired peripherals' Alternate + Function (AF) using GPIO_PinAFConfig() function. For PortC, + PortD and PortF, no configuration is needed. + (+++) Configure the desired pin in alternate function mode using + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + (+++) Select the type, pull-up/pull-down and output speed via + GPIO_PuPd, GPIO_OType and GPIO_Speed members + (+++) Call GPIO_Init() function + (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit() + (#) To set/reset the level of a pin configured in output mode use + GPIO_SetBits()/GPIO_ResetBits() + (#) During and just after reset, the alternate functions are not active and + the GPIO pins are configured in input floating mode (except JTAG pins). + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as + general-purpose (PC14 and PC15, respectively) when the LSE oscillator + is off. The LSE has priority over the GPIO function. + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose + PD0 and PD1, respectively, when the HSE oscillator is off. The HSE has + priority over the GPIO function. + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_gpio.h" +#include "stm32f0xx_rcc.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup GPIO + * @brief GPIO driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup GPIO_Private_Functions + * @{ + */ + +/** @defgroup GPIO_Group1 Initialization and Configuration + * @brief Initialization and Configuration + * +@verbatim + =============================================================================== + ##### Initialization and Configuration ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the GPIOx peripheral registers to their default reset + * values. + * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. + * @note GPIOE is available only for STM32F072. + * @note GPIOD is not available for STM32F031. + * @retval None + */ +void GPIO_DeInit(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + if(GPIOx == GPIOA) + { + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE); + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE); + } + else if(GPIOx == GPIOB) + { + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE); + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE); + } + else if(GPIOx == GPIOC) + { + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE); + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE); + } + else if(GPIOx == GPIOD) + { + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE); + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE); + } + else if(GPIOx == GPIOE) + { + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE); + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE); + } + else + { + if(GPIOx == GPIOF) + { + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, ENABLE); + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, DISABLE); + } + } +} + +/** + * @brief Initializes the GPIOx peripheral according to the specified + * parameters in the GPIO_InitStruct. + * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. + * @note GPIOE is available only for STM32F072. + * @note GPIOD is not available for STM32F031. + * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); + assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); + assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); + + /*-------------------------- Configure the port pins -----------------------*/ + /*-- GPIO Mode Configuration --*/ + for (pinpos = 0x00; pinpos < 0x10; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + + /* Get the port pins position */ + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + + if (currentpin == pos) + { + if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF)) + { + /* Check Speed mode parameters */ + assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); + + /* Speed mode configuration */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2)); + GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2)); + + /* Check Output mode parameters */ + assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType)); + + /* Output mode configuration */ + GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)); + GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos)); + } + + GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2)); + + GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2)); + + /* Pull-up Pull down resistor configuration */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2)); + GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2)); + } + } +} + +/** + * @brief Fills each GPIO_InitStruct member with its default value. + * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_Level_2; + GPIO_InitStruct->GPIO_OType = GPIO_OType_PP; + GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL; +} + +/** + * @brief Locks GPIO Pins configuration registers. + * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + * @note The configuration of the locked GPIO pins can no longer be modified + * until the next device reset. + * @param GPIOx: where x can be (A or B) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = 0x00010000; + + /* Check the parameters */ + assert_param(IS_GPIO_LIST_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + tmp |= GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Reset LCKK bit */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Read LCKK bit */ + tmp = GPIOx->LCKR; + /* Read LCKK bit */ + tmp = GPIOx->LCKR; +} + +/** + * @} + */ + +/** @defgroup GPIO_Group2 GPIO Read and Write + * @brief GPIO Read and Write + * +@verbatim + =============================================================================== + ##### GPIO Read and Write ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Reads the specified input port pin. + * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. + * @note GPIOE is available only for STM32F072. + * @note GPIOD is not available for STM32F031. + * @param GPIO_Pin: specifies the port bit to read. + * @note This parameter can be GPIO_Pin_x where x can be: + * For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF. + * For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF. + * For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF. + * @retval The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified input port pin. + * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. + * @note GPIOE is available only for STM32F072. + * @note GPIOD is not available for STM32F031. + * @retval The input port pin value. + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->IDR); +} + +/** + * @brief Reads the specified output data port bit. + * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. + * @note GPIOE is available only for STM32F072. + * @note GPIOD is not available for STM32F031. + * @param GPIO_Pin: Specifies the port bit to read. + * @note This parameter can be GPIO_Pin_x where x can be: + * For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF. + * For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF. + * For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF. + * @retval The output port pin value. + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO output data port. + * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. + * @note GPIOE is available only for STM32F072. + * @note GPIOD is not available for STM32F031. + * @retval GPIO output data port value. + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->ODR); +} + +/** + * @brief Sets the selected data port bits. + * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. + * @note GPIOE is available only for STM32F072. + * @note GPIOD is not available for STM32F031. + * @param GPIO_Pin: specifies the port bits to be written. + * @note This parameter can be GPIO_Pin_x where x can be: + * For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF. + * For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF. + * For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF. + * @retval None + */ +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BSRR = GPIO_Pin; +} + +/** + * @brief Clears the selected data port bits. + * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. + * @note GPIOE is available only for STM32F072. + * @note GPIOD is not available for STM32F031. + * @param GPIO_Pin: specifies the port bits to be written. + * @note This parameter can be GPIO_Pin_x where x can be: + * For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF. + * For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF. + * For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF. + * @retval None + */ +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BRR = GPIO_Pin; +} + +/** + * @brief Sets or clears the selected data port bit. + * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. + * @note GPIOE is available only for STM32F072. + * @note GPIOD is not available for STM32F031. + * @param GPIO_Pin: specifies the port bit to be written. + * @param BitVal: specifies the value to be written to the selected bit. + * This parameter can be one of the BitAction enumeration values: + * @arg Bit_RESET: to clear the port pin + * @arg Bit_SET: to set the port pin + * @note This parameter can be GPIO_Pin_x where x can be: + * For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF. + * For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF. + * For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF. + * @retval None + */ +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_BIT_ACTION(BitVal)); + + if (BitVal != Bit_RESET) + { + GPIOx->BSRR = GPIO_Pin; + } + else + { + GPIOx->BRR = GPIO_Pin ; + } +} + +/** + * @brief Writes data to the specified GPIO data port. + * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. + * @note GPIOE is available only for STM32F072. + * @note GPIOD is not available for STM32F031. + * @param PortVal: specifies the value to be written to the port output data register. + * @retval None + */ +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + GPIOx->ODR = PortVal; +} + +/** + * @} + */ + +/** @defgroup GPIO_Group3 GPIO Alternate functions configuration functions + * @brief GPIO Alternate functions configuration functions + * +@verbatim + =============================================================================== + ##### GPIO Alternate functions configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Writes data to the specified GPIO data port. + * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. + * @note GPIOC, GPIOD, GPIOE and GPIOF are available only for STM32F072 and STM32F091. + * @param GPIO_PinSource: specifies the pin for the Alternate function. + * This parameter can be GPIO_PinSourcex where x can be (0..15) for GPIOA, GPIOB, GPIOD, GPIOE + * and (0..12) for GPIOC and (0, 2..5, 9..10) for GPIOF. + * @param GPIO_AF: selects the pin to used as Alternate function. + * This parameter can be one of the following value: + * @arg GPIO_AF_0: WKUP, EVENTOUT, TIM15, SPI1, TIM17, MCO, SWDAT, SWCLK, + * TIM14, BOOT, USART1, CEC, IR_OUT, SPI2, TIM3, USART4, + * CAN, USART2, CRS, TIM16, TIM1, TS, USART8 + * @arg GPIO_AF_1: USART2, CEC, TIM3, USART1, USART2, EVENTOUT, I2C1, + * I2C2, TIM15, SPI2, USART3, TS, SPI1, USART7, USART8 + * USART5, USART4, USART6, I2C1 + * @arg GPIO_AF_2: TIM2, TIM1, EVENTOUT, TIM16, TIM17, USB, USART6, USART5, + * USART8, USART7, USART6 + * @arg GPIO_AF_3: TS, I2C1, TIM15, EVENTOUT + * @arg GPIO_AF_4: TIM14, USART4, USART3, CRS, CAN, I2C1, USART5 + * @arg GPIO_AF_5: TIM16, TIM17, TIM15, SPI2, I2C2, USART6, MCO + * @arg GPIO_AF_6: EVENTOUT + * @arg GPIO_AF_7: COMP1 OUT, COMP2 OUT + * @note The pin should already been configured in Alternate Function mode(AF) + * using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + * @note Refer to the Alternate function mapping table in the device datasheet + * for the detailed mapping of the system and peripherals'alternate + * function I/O pins. + * @retval None + */ +void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF) +{ + uint32_t temp = 0x00; + uint32_t temp_2 = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + assert_param(IS_GPIO_AF(GPIO_AF)); + + temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)); + GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)); + temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp; + GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_i2c.c b/system/src/stm32f0-stdperiph/stm32f0xx_i2c.c new file mode 100644 index 0000000..c92c204 --- /dev/null +++ b/system/src/stm32f0-stdperiph/stm32f0xx_i2c.c @@ -0,0 +1,1585 @@ +/** + ****************************************************************************** + * @file stm32f0xx_i2c.c + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Inter-Integrated circuit (I2C): + * + Initialization and Configuration + * + Communications handling + * + SMBUS management + * + I2C registers management + * + Data transfers management + * + DMA transfers management + * + Interrupts and flags management + * + * @verbatim + ============================================================================ + ##### How to use this driver ##### + ============================================================================ + [..] + (#) Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE) + function for I2C1 or I2C2. + (#) Enable SDA, SCL and SMBA (when used) GPIO clocks using + RCC_AHBPeriphClockCmd() function. + (#) Peripherals alternate function: + (++) Connect the pin to the desired peripherals' Alternate + Function (AF) using GPIO_PinAFConfig() function. + (++) Configure the desired pin in alternate function by: + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + (++) Select the type, OpenDrain and speed via + GPIO_PuPd, GPIO_OType and GPIO_Speed members + (++) Call GPIO_Init() function. + (#) Program the Mode, Timing , Own address, Ack and Acknowledged Address + using the I2C_Init() function. + (#) Optionally you can enable/configure the following parameters without + re-initialization (i.e there is no need to call again I2C_Init() function): + (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function. + (++) Enable the dual addressing mode using I2C_DualAddressCmd() function. + (++) Enable the general call using the I2C_GeneralCallCmd() function. + (++) Enable the clock stretching using I2C_StretchClockCmd() function. + (++) Enable the PEC Calculation using I2C_CalculatePEC() function. + (++) For SMBus Mode: + (+++) Enable the SMBusAlert pin using I2C_SMBusAlertCmd() function. + (#) Enable the NVIC and the corresponding interrupt using the function + I2C_ITConfig() if you need to use interrupt mode. + (#) When using the DMA mode + (++) Configure the DMA using DMA_Init() function. + (++) Active the needed channel Request using I2C_DMACmd() function. + (#) Enable the I2C using the I2C_Cmd() function. + (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the + transfers. + [..] + (@) When using I2C in Fast Mode Plus, SCL and SDA pin 20mA current drive capability + must be enabled by setting the driving capability control bit in SYSCFG. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_i2c.h" +#include "stm32f0xx_rcc.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup I2C + * @brief I2C driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +#define CR1_CLEAR_MASK ((uint32_t)0x00CFE0FF) /*I2C_AnalogFilter)); + assert_param(IS_I2C_DIGITAL_FILTER(I2C_InitStruct->I2C_DigitalFilter)); + assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); + assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); + assert_param(IS_I2C_ACK(I2C_InitStruct->I2C_Ack)); + assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); + + /* Disable I2Cx Peripheral */ + I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE); + + /*---------------------------- I2Cx FILTERS Configuration ------------------*/ + /* Get the I2Cx CR1 value */ + tmpreg = I2Cx->CR1; + /* Clear I2Cx CR1 register */ + tmpreg &= CR1_CLEAR_MASK; + /* Configure I2Cx: analog and digital filter */ + /* Set ANFOFF bit according to I2C_AnalogFilter value */ + /* Set DFN bits according to I2C_DigitalFilter value */ + tmpreg |= (uint32_t)I2C_InitStruct->I2C_AnalogFilter |(I2C_InitStruct->I2C_DigitalFilter << 8); + + /* Write to I2Cx CR1 */ + I2Cx->CR1 = tmpreg; + + /*---------------------------- I2Cx TIMING Configuration -------------------*/ + /* Configure I2Cx: Timing */ + /* Set TIMINGR bits according to I2C_Timing */ + /* Write to I2Cx TIMING */ + I2Cx->TIMINGR = I2C_InitStruct->I2C_Timing & TIMING_CLEAR_MASK; + + /* Enable I2Cx Peripheral */ + I2Cx->CR1 |= I2C_CR1_PE; + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Clear tmpreg local variable */ + tmpreg = 0; + /* Clear OAR1 register */ + I2Cx->OAR1 = (uint32_t)tmpreg; + /* Clear OAR2 register */ + I2Cx->OAR2 = (uint32_t)tmpreg; + /* Configure I2Cx: Own Address1 and acknowledged address */ + /* Set OA1MODE bit according to I2C_AcknowledgedAddress value */ + /* Set OA1 bits according to I2C_OwnAddress1 value */ + tmpreg = (uint32_t)((uint32_t)I2C_InitStruct->I2C_AcknowledgedAddress | \ + (uint32_t)I2C_InitStruct->I2C_OwnAddress1); + /* Write to I2Cx OAR1 */ + I2Cx->OAR1 = tmpreg; + /* Enable Own Address1 acknowledgement */ + I2Cx->OAR1 |= I2C_OAR1_OA1EN; + + /*---------------------------- I2Cx MODE Configuration ---------------------*/ + /* Configure I2Cx: mode */ + /* Set SMBDEN and SMBHEN bits according to I2C_Mode value */ + tmpreg = I2C_InitStruct->I2C_Mode; + /* Write to I2Cx CR1 */ + I2Cx->CR1 |= tmpreg; + + /*---------------------------- I2Cx ACK Configuration ----------------------*/ + /* Get the I2Cx CR2 value */ + tmpreg = I2Cx->CR2; + /* Clear I2Cx CR2 register */ + tmpreg &= CR2_CLEAR_MASK; + /* Configure I2Cx: acknowledgement */ + /* Set NACK bit according to I2C_Ack value */ + tmpreg |= I2C_InitStruct->I2C_Ack; + /* Write to I2Cx CR2 */ + I2Cx->CR2 = tmpreg; +} + +/** + * @brief Fills each I2C_InitStruct member with its default value. + * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized. + * @retval None + */ +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) +{ + /*---------------- Reset I2C init structure parameters values --------------*/ + /* Initialize the I2C_Timing member */ + I2C_InitStruct->I2C_Timing = 0; + /* Initialize the I2C_AnalogFilter member */ + I2C_InitStruct->I2C_AnalogFilter = I2C_AnalogFilter_Enable; + /* Initialize the I2C_DigitalFilter member */ + I2C_InitStruct->I2C_DigitalFilter = 0; + /* Initialize the I2C_Mode member */ + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + /* Initialize the I2C_OwnAddress1 member */ + I2C_InitStruct->I2C_OwnAddress1 = 0; + /* Initialize the I2C_Ack member */ + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + /* Initialize the I2C_AcknowledgedAddress member */ + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +} + +/** + * @brief Enables or disables the specified I2C peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C peripheral */ + I2Cx->CR1 |= I2C_CR1_PE; + } + else + { + /* Disable the selected I2C peripheral */ + I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE); + } +} + +/** + * @brief Enables or disables the specified I2C software reset. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @retval None + */ +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Disable peripheral */ + I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE); + + /* Perform a dummy read to delay the disable of peripheral for minimum + 3 APB clock cycles to perform the software reset functionality */ + *(__IO uint32_t *)(uint32_t)I2Cx; + + /* Enable peripheral */ + I2Cx->CR1 |= I2C_CR1_PE; +} + +/** + * @brief Enables or disables the specified I2C interrupts. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2C_IT_ERRI: Error interrupt mask + * @arg I2C_IT_TCI: Transfer Complete interrupt mask + * @arg I2C_IT_STOPI: Stop Detection interrupt mask + * @arg I2C_IT_NACKI: Not Acknowledge received interrupt mask + * @arg I2C_IT_ADDRI: Address Match interrupt mask + * @arg I2C_IT_RXI: RX interrupt mask + * @arg I2C_IT_TXI: TX interrupt mask + * @param NewState: new state of the specified I2C interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_I2C_CONFIG_IT(I2C_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C interrupts */ + I2Cx->CR1 |= I2C_IT; + } + else + { + /* Disable the selected I2C interrupts */ + I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_IT); + } +} + +/** + * @brief Enables or disables the I2C Clock stretching. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx Clock stretching. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable clock stretching */ + I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_NOSTRETCH); + } + else + { + /* Disable clock stretching */ + I2Cx->CR1 |= I2C_CR1_NOSTRETCH; + } +} + +/** + * @brief Enables or disables I2C wakeup from stop mode. + * This function is not applicable for STM32F030 devices. + * @param I2Cx: where x can be 1 to select the I2C peripheral. + * @param NewState: new state of the I2Cx stop mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_1_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable wakeup from stop mode */ + I2Cx->CR1 |= I2C_CR1_WUPEN; + } + else + { + /* Disable wakeup from stop mode */ + I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_WUPEN); + } +} + +/** + * @brief Enables or disables the I2C own address 2. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C own address 2. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable own address 2 */ + I2Cx->OAR2 |= I2C_OAR2_OA2EN; + } + else + { + /* Disable own address 2 */ + I2Cx->OAR2 &= (uint32_t)~((uint32_t)I2C_OAR2_OA2EN); + } +} + +/** + * @brief Configures the I2C slave own address 2 and mask. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Address: specifies the slave address to be programmed. + * @param Mask: specifies own address 2 mask to be programmed. + * This parameter can be one of the following values: + * @arg I2C_OA2_NoMask: no mask. + * @arg I2C_OA2_Mask01: OA2[1] is masked and don't care. + * @arg I2C_OA2_Mask02: OA2[2:1] are masked and don't care. + * @arg I2C_OA2_Mask03: OA2[3:1] are masked and don't care. + * @arg I2C_OA2_Mask04: OA2[4:1] are masked and don't care. + * @arg I2C_OA2_Mask05: OA2[5:1] are masked and don't care. + * @arg I2C_OA2_Mask06: OA2[6:1] are masked and don't care. + * @arg I2C_OA2_Mask07: OA2[7:1] are masked and don't care. + * @retval None + */ +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_OWN_ADDRESS2(Address)); + assert_param(IS_I2C_OWN_ADDRESS2_MASK(Mask)); + + /* Get the old register value */ + tmpreg = I2Cx->OAR2; + + /* Reset I2Cx OA2 bit [7:1] and OA2MSK bit [1:0] */ + tmpreg &= (uint32_t)~((uint32_t)(I2C_OAR2_OA2 | I2C_OAR2_OA2MSK)); + + /* Set I2Cx SADD */ + tmpreg |= (uint32_t)(((uint32_t)Address & I2C_OAR2_OA2) | \ + (((uint32_t)Mask << 8) & I2C_OAR2_OA2MSK)) ; + + /* Store the new register value */ + I2Cx->OAR2 = tmpreg; +} + +/** + * @brief Enables or disables the I2C general call mode. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C general call mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable general call mode */ + I2Cx->CR1 |= I2C_CR1_GCEN; + } + else + { + /* Disable general call mode */ + I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_GCEN); + } +} + +/** + * @brief Enables or disables the I2C slave byte control. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C slave byte control. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable slave byte control */ + I2Cx->CR1 |= I2C_CR1_SBC; + } + else + { + /* Disable slave byte control */ + I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_SBC); + } +} + +/** + * @brief Configures the slave address to be transmitted after start generation. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Address: specifies the slave address to be programmed. + * @note This function should be called before generating start condition. + * @retval None + */ +void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_SLAVE_ADDRESS(Address)); + + /* Get the old register value */ + tmpreg = I2Cx->CR2; + + /* Reset I2Cx SADD bit [9:0] */ + tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_SADD); + + /* Set I2Cx SADD */ + tmpreg |= (uint32_t)((uint32_t)Address & I2C_CR2_SADD); + + /* Store the new register value */ + I2Cx->CR2 = tmpreg; +} + +/** + * @brief Enables or disables the I2C 10-bit addressing mode for the master. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C 10-bit addressing mode. + * This parameter can be: ENABLE or DISABLE. + * @note This function should be called before generating start condition. + * @retval None + */ +void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable 10-bit addressing mode */ + I2Cx->CR2 |= I2C_CR2_ADD10; + } + else + { + /* Disable 10-bit addressing mode */ + I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_ADD10); + } +} + +/** + * @} + */ + + +/** @defgroup I2C_Group2 Communications handling functions + * @brief Communications handling functions + * +@verbatim + =============================================================================== + ##### Communications handling functions ##### + =============================================================================== + [..] This section provides a set of functions that handles I2C communication. + + [..] Automatic End mode is enabled using I2C_AutoEndCmd() function. When Reload + mode is enabled via I2C_ReloadCmd() AutoEnd bit has no effect. + + [..] I2C_NumberOfBytesConfig() function set the number of bytes to be transferred, + this configuration should be done before generating start condition in master + mode. + + [..] When switching from master write operation to read operation in 10Bit addressing + mode, master can only sends the 1st 7 bits of the 10 bit address, followed by + Read direction by enabling HEADR bit using I2C_10BitAddressHeader() function. + + [..] In master mode, when transferring more than 255 bytes Reload mode should be used + to handle communication. In the first phase of transfer, Nbytes should be set to + 255. After transferring these bytes TCR flag is set and I2C_TransferHandling() + function should be called to handle remaining communication. + + [..] In master mode, when software end mode is selected when all data is transferred + TC flag is set I2C_TransferHandling() function should be called to generate STOP + or generate ReStart. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the I2C automatic end mode (stop condition is + * automatically sent when nbytes data are transferred). + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C automatic end mode. + * This parameter can be: ENABLE or DISABLE. + * @note This function has effect if Reload mode is disabled. + * @retval None + */ +void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Auto end mode */ + I2Cx->CR2 |= I2C_CR2_AUTOEND; + } + else + { + /* Disable Auto end mode */ + I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_AUTOEND); + } +} + +/** + * @brief Enables or disables the I2C nbytes reload mode. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the nbytes reload mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Auto Reload mode */ + I2Cx->CR2 |= I2C_CR2_RELOAD; + } + else + { + /* Disable Auto Reload mode */ + I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RELOAD); + } +} + +/** + * @brief Configures the number of bytes to be transmitted/received. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Number_Bytes: specifies the number of bytes to be programmed. + * @retval None + */ +void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Get the old register value */ + tmpreg = I2Cx->CR2; + + /* Reset I2Cx Nbytes bit [7:0] */ + tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_NBYTES); + + /* Set I2Cx Nbytes */ + tmpreg |= (uint32_t)(((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES); + + /* Store the new register value */ + I2Cx->CR2 = tmpreg; +} + +/** + * @brief Configures the type of transfer request for the master. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_Direction: specifies the transfer request direction to be programmed. + * This parameter can be one of the following values: + * @arg I2C_Direction_Transmitter: Master request a write transfer + * @arg I2C_Direction_Receiver: Master request a read transfer + * @retval None + */ +void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction) +{ +/* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_DIRECTION(I2C_Direction)); + + /* Test on the direction to set/reset the read/write bit */ + if (I2C_Direction == I2C_Direction_Transmitter) + { + /* Request a write Transfer */ + I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RD_WRN); + } + else + { + /* Request a read Transfer */ + I2Cx->CR2 |= I2C_CR2_RD_WRN; + } +} + +/** + * @brief Generates I2Cx communication START condition. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C START condition generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Generate a START condition */ + I2Cx->CR2 |= I2C_CR2_START; + } + else + { + /* Disable the START condition generation */ + I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_START); + } +} + +/** + * @brief Generates I2Cx communication STOP condition. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C STOP condition generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Generate a STOP condition */ + I2Cx->CR2 |= I2C_CR2_STOP; + } + else + { + /* Disable the STOP condition generation */ + I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_STOP); + } +} + +/** + * @brief Enables or disables the I2C 10-bit header only mode with read direction. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C 10-bit header only mode. + * This parameter can be: ENABLE or DISABLE. + * @note This mode can be used only when switching from master transmitter mode + * to master receiver mode. + * @retval None + */ +void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable 10-bit header only mode */ + I2Cx->CR2 |= I2C_CR2_HEAD10R; + } + else + { + /* Disable 10-bit header only mode */ + I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_HEAD10R); + } +} + +/** + * @brief Generates I2C communication Acknowledge. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the Acknowledge. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable ACK generation */ + I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_NACK); + } + else + { + /* Enable NACK generation */ + I2Cx->CR2 |= I2C_CR2_NACK; + } +} + +/** + * @brief Returns the I2C slave matched address . + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @retval The value of the slave matched address . + */ +uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Return the slave matched address in the SR1 register */ + return (uint8_t)(((uint32_t)I2Cx->ISR & I2C_ISR_ADDCODE) >> 16) ; +} + +/** + * @brief Returns the I2C slave received request. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @retval The value of the received request. + */ +uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx) +{ + uint32_t tmpreg = 0; + uint16_t direction = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Return the slave matched address in the SR1 register */ + tmpreg = (uint32_t)(I2Cx->ISR & I2C_ISR_DIR); + + /* If write transfer is requested */ + if (tmpreg == 0) + { + /* write transfer is requested */ + direction = I2C_Direction_Transmitter; + } + else + { + /* Read transfer is requested */ + direction = I2C_Direction_Receiver; + } + return direction; +} + +/** + * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Address: specifies the slave address to be programmed. + * @param Number_Bytes: specifies the number of bytes to be programmed. + * This parameter must be a value between 0 and 255. + * @param ReloadEndMode: new state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg I2C_Reload_Mode: Enable Reload mode . + * @arg I2C_AutoEnd_Mode: Enable Automatic end mode. + * @arg I2C_SoftEnd_Mode: Enable Software end mode. + * @param StartStopMode: new state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg I2C_No_StartStop: Don't Generate stop and start condition. + * @arg I2C_Generate_Stop: Generate stop condition (Number_Bytes should be set to 0). + * @arg I2C_Generate_Start_Read: Generate Restart for read request. + * @arg I2C_Generate_Start_Write: Generate Restart for write request. + * @retval None + */ +void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_SLAVE_ADDRESS(Address)); + assert_param(IS_RELOAD_END_MODE(ReloadEndMode)); + assert_param(IS_START_STOP_MODE(StartStopMode)); + + /* Get the CR2 register value */ + tmpreg = I2Cx->CR2; + + /* clear tmpreg specific bits */ + tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)); + + /* update tmpreg */ + tmpreg |= (uint32_t)(((uint32_t)Address & I2C_CR2_SADD) | (((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES) | \ + (uint32_t)ReloadEndMode | (uint32_t)StartStopMode); + + /* update CR2 register */ + I2Cx->CR2 = tmpreg; +} + +/** + * @} + */ + + +/** @defgroup I2C_Group3 SMBUS management functions + * @brief SMBUS management functions + * +@verbatim + =============================================================================== + ##### SMBUS management functions ##### + =============================================================================== + [..] This section provides a set of functions that handles SMBus communication + and timeouts detection. + + [..] The SMBus Device default address (0b1100 001) is enabled by calling I2C_Init() + function and setting I2C_Mode member of I2C_InitTypeDef() structure to + I2C_Mode_SMBusDevice. + + [..] The SMBus Host address (0b0001 000) is enabled by calling I2C_Init() + function and setting I2C_Mode member of I2C_InitTypeDef() structure to + I2C_Mode_SMBusHost. + + [..] The Alert Response Address (0b0001 100) is enabled using I2C_SMBusAlertCmd() + function. + + [..] To detect cumulative SCL stretch in master and slave mode, TIMEOUTB should be + configured (in accordance to SMBus specification) using I2C_TimeoutBConfig() + function then I2C_ExtendedClockTimeoutCmd() function should be called to enable + the detection. + + [..] SCL low timeout is detected by configuring TIMEOUTB using I2C_TimeoutBConfig() + function followed by the call of I2C_ClockTimeoutCmd(). When adding to this + procedure the call of I2C_IdleClockTimeoutCmd() function, Bus Idle condition + (both SCL and SDA high) is detected also. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables I2C SMBus alert. + * @param I2Cx: where x can be 1 to select the I2C peripheral. + * @param NewState: new state of the I2Cx SMBus alert. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_1_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable SMBus alert */ + I2Cx->CR1 |= I2C_CR1_ALERTEN; + } + else + { + /* Disable SMBus alert */ + I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_ALERTEN); + } +} + +/** + * @brief Enables or disables I2C Clock Timeout (SCL Timeout detection). + * @param I2Cx: where x can be 1 to select the I2C peripheral. + * @param NewState: new state of the I2Cx clock Timeout. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_1_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Clock Timeout */ + I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIMOUTEN; + } + else + { + /* Disable Clock Timeout */ + I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMOUTEN); + } +} + +/** + * @brief Enables or disables I2C Extended Clock Timeout (SCL cumulative Timeout detection). + * @param I2Cx: where x can be 1 to select the I2C peripheral. + * @param NewState: new state of the I2Cx Extended clock Timeout. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_1_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Clock Timeout */ + I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TEXTEN; + } + else + { + /* Disable Clock Timeout */ + I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TEXTEN); + } +} + +/** + * @brief Enables or disables I2C Idle Clock Timeout (Bus idle SCL and SDA + * high detection). + * @param I2Cx: where x can be 1 to select the I2C peripheral. + * @param NewState: new state of the I2Cx Idle clock Timeout. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_1_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Clock Timeout */ + I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIDLE; + } + else + { + /* Disable Clock Timeout */ + I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIDLE); + } +} + +/** + * @brief Configures the I2C Bus Timeout A (SCL Timeout when TIDLE = 0 or Bus + * idle SCL and SDA high when TIDLE = 1). + * @param I2Cx: where x can be 1 to select the I2C peripheral. + * @param Timeout: specifies the TimeoutA to be programmed. + * @retval None + */ +void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_1_PERIPH(I2Cx)); + assert_param(IS_I2C_TIMEOUT(Timeout)); + + /* Get the old register value */ + tmpreg = I2Cx->TIMEOUTR; + + /* Reset I2Cx TIMEOUTA bit [11:0] */ + tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTA); + + /* Set I2Cx TIMEOUTA */ + tmpreg |= (uint32_t)((uint32_t)Timeout & I2C_TIMEOUTR_TIMEOUTA) ; + + /* Store the new register value */ + I2Cx->TIMEOUTR = tmpreg; +} + +/** + * @brief Configures the I2C Bus Timeout B (SCL cumulative Timeout). + * @param I2Cx: where x can be 1 to select the I2C peripheral. + * @param Timeout: specifies the TimeoutB to be programmed. + * @retval None + */ +void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_1_PERIPH(I2Cx)); + assert_param(IS_I2C_TIMEOUT(Timeout)); + + /* Get the old register value */ + tmpreg = I2Cx->TIMEOUTR; + + /* Reset I2Cx TIMEOUTB bit [11:0] */ + tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTB); + + /* Set I2Cx TIMEOUTB */ + tmpreg |= (uint32_t)(((uint32_t)Timeout << 16) & I2C_TIMEOUTR_TIMEOUTB) ; + + /* Store the new register value */ + I2Cx->TIMEOUTR = tmpreg; +} + +/** + * @brief Enables or disables I2C PEC calculation. + * @param I2Cx: where x can be 1 to select the I2C peripheral. + * @param NewState: new state of the I2Cx PEC calculation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_1_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable PEC calculation */ + I2Cx->CR1 |= I2C_CR1_PECEN; + } + else + { + /* Disable PEC calculation */ + I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PECEN); + } +} + +/** + * @brief Enables or disables I2C PEC transmission/reception request. + * @param I2Cx: where x can be 1 to select the I2C peripheral. + * @param NewState: new state of the I2Cx PEC request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_1_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable PEC transmission/reception request */ + I2Cx->CR2 |= I2C_CR2_PECBYTE; + } + else + { + /* Disable PEC transmission/reception request */ + I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_PECBYTE); + } +} + +/** + * @brief Returns the I2C PEC. + * @param I2Cx: where x can be 1 to select the I2C peripheral. + * @retval The value of the PEC . + */ +uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_1_PERIPH(I2Cx)); + + /* Return the slave matched address in the SR1 register */ + return (uint8_t)((uint32_t)I2Cx->PECR & I2C_PECR_PEC); +} + +/** + * @} + */ + + +/** @defgroup I2C_Group4 I2C registers management functions + * @brief I2C registers management functions + * +@verbatim + =============================================================================== + ##### I2C registers management functions ##### + =============================================================================== + [..] This section provides a functions that allow user the management of + I2C registers. + +@endverbatim + * @{ + */ + + /** + * @brief Reads the specified I2C register and returns its value. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_Register: specifies the register to read. + * This parameter can be one of the following values: + * @arg I2C_Register_CR1: CR1 register. + * @arg I2C_Register_CR2: CR2 register. + * @arg I2C_Register_OAR1: OAR1 register. + * @arg I2C_Register_OAR2: OAR2 register. + * @arg I2C_Register_TIMINGR: TIMING register. + * @arg I2C_Register_TIMEOUTR: TIMEOUTR register. + * @arg I2C_Register_ISR: ISR register. + * @arg I2C_Register_ICR: ICR register. + * @arg I2C_Register_PECR: PECR register. + * @arg I2C_Register_RXDR: RXDR register. + * @arg I2C_Register_TXDR: TXDR register. + * @retval The value of the read register. + */ +uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_REGISTER(I2C_Register)); + + tmp = (uint32_t)I2Cx; + tmp += I2C_Register; + + /* Return the selected register value */ + return (*(__IO uint32_t *) tmp); +} + +/** + * @} + */ + +/** @defgroup I2C_Group5 Data transfers management functions + * @brief Data transfers management functions + * +@verbatim + =============================================================================== + ##### Data transfers management functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage + the I2C data transfers. + + [..] The read access of the I2C_RXDR register can be done using + the I2C_ReceiveData() function and returns the received value. + Whereas a write access to the I2C_TXDR can be done using I2C_SendData() + function and stores the written data into TXDR. +@endverbatim + * @{ + */ + +/** + * @brief Sends a data byte through the I2Cx peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Data: Byte to be transmitted.. + * @retval None + */ +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Write in the DR register the data to be sent */ + I2Cx->TXDR = (uint8_t)Data; +} + +/** + * @brief Returns the most recent received data by the I2Cx peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @retval The value of the received data. + */ +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Return the data in the DR register */ + return (uint8_t)I2Cx->RXDR; +} + +/** + * @} + */ + + +/** @defgroup I2C_Group6 DMA transfers management functions + * @brief DMA transfers management functions + * +@verbatim + =============================================================================== + ##### DMA transfers management functions ##### + =============================================================================== + [..] This section provides two functions that can be used only in DMA mode. + [..] In DMA Mode, the I2C communication can be managed by 2 DMA Channel + requests: + (#) I2C_DMAReq_Tx: specifies the Tx buffer DMA transfer request. + (#) I2C_DMAReq_Rx: specifies the Rx buffer DMA transfer request. + [..] In this Mode it is advised to use the following function: + (+) I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState); +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the I2C DMA interface. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_DMAReq: specifies the I2C DMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2C_DMAReq_Tx: Tx DMA transfer request + * @arg I2C_DMAReq_Rx: Rx DMA transfer request + * @param NewState: new state of the selected I2C DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_I2C_DMA_REQ(I2C_DMAReq)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C DMA requests */ + I2Cx->CR1 |= I2C_DMAReq; + } + else + { + /* Disable the selected I2C DMA requests */ + I2Cx->CR1 &= (uint32_t)~I2C_DMAReq; + } +} +/** + * @} + */ + + +/** @defgroup I2C_Group7 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + [..] This section provides functions allowing to configure the I2C Interrupts + sources and check or clear the flags or pending bits status. + The user should identify which mode will be used in his application to manage + the communication: Polling mode, Interrupt mode or DMA mode(refer I2C_Group6). + + *** Polling Mode *** + ==================== + [..] In Polling Mode, the I2C communication can be managed by 15 flags: + (#) I2C_FLAG_TXE: to indicate the status of Transmit data register empty flag. + (#) I2C_FLAG_TXIS: to indicate the status of Transmit interrupt status flag . + (#) I2C_FLAG_RXNE: to indicate the status of Receive data register not empty flag. + (#) I2C_FLAG_ADDR: to indicate the status of Address matched flag (slave mode). + (#) I2C_FLAG_NACKF: to indicate the status of NACK received flag. + (#) I2C_FLAG_STOPF: to indicate the status of STOP detection flag. + (#) I2C_FLAG_TC: to indicate the status of Transfer complete flag(master mode). + (#) I2C_FLAG_TCR: to indicate the status of Transfer complete reload flag. + (#) I2C_FLAG_BERR: to indicate the status of Bus error flag. + (#) I2C_FLAG_ARLO: to indicate the status of Arbitration lost flag. + (#) I2C_FLAG_OVR: to indicate the status of Overrun/Underrun flag. + (#) I2C_FLAG_PECERR: to indicate the status of PEC error in reception flag. + (#) I2C_FLAG_TIMEOUT: to indicate the status of Timeout or Tlow detection flag. + (#) I2C_FLAG_ALERT: to indicate the status of SMBus Alert flag. + (#) I2C_FLAG_BUSY: to indicate the status of Bus busy flag. + + [..] In this Mode it is advised to use the following functions: + (+) FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); + (+) void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); + + [..] + (@)Do not use the BUSY flag to handle each data transmission or reception.It is + better to use the TXIS and RXNE flags instead. + + *** Interrupt Mode *** + ====================== + [..] In Interrupt Mode, the I2C communication can be managed by 7 interrupt sources + and 15 pending bits: + [..] Interrupt Source: + (#) I2C_IT_ERRI: specifies the interrupt source for the Error interrupt. + (#) I2C_IT_TCI: specifies the interrupt source for the Transfer Complete interrupt. + (#) I2C_IT_STOPI: specifies the interrupt source for the Stop Detection interrupt. + (#) I2C_IT_NACKI: specifies the interrupt source for the Not Acknowledge received interrupt. + (#) I2C_IT_ADDRI: specifies the interrupt source for the Address Match interrupt. + (#) I2C_IT_RXI: specifies the interrupt source for the RX interrupt. + (#) I2C_IT_TXI: specifies the interrupt source for the TX interrupt. + + [..] Pending Bits: + (#) I2C_IT_TXIS: to indicate the status of Transmit interrupt status flag. + (#) I2C_IT_RXNE: to indicate the status of Receive data register not empty flag. + (#) I2C_IT_ADDR: to indicate the status of Address matched flag (slave mode). + (#) I2C_IT_NACKF: to indicate the status of NACK received flag. + (#) I2C_IT_STOPF: to indicate the status of STOP detection flag. + (#) I2C_IT_TC: to indicate the status of Transfer complete flag (master mode). + (#) I2C_IT_TCR: to indicate the status of Transfer complete reload flag. + (#) I2C_IT_BERR: to indicate the status of Bus error flag. + (#) I2C_IT_ARLO: to indicate the status of Arbitration lost flag. + (#) I2C_IT_OVR: to indicate the status of Overrun/Underrun flag. + (#) I2C_IT_PECERR: to indicate the status of PEC error in reception flag. + (#) I2C_IT_TIMEOUT: to indicate the status of Timeout or Tlow detection flag. + (#) I2C_IT_ALERT: to indicate the status of SMBus Alert flag. + + [..] In this Mode it is advised to use the following functions: + (+) void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); + (+) ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); + +@endverbatim + * @{ + */ + +/** + * @brief Checks whether the specified I2C flag is set or not. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_TXE: Transmit data register empty + * @arg I2C_FLAG_TXIS: Transmit interrupt status + * @arg I2C_FLAG_RXNE: Receive data register not empty + * @arg I2C_FLAG_ADDR: Address matched (slave mode) + * @arg I2C_FLAG_NACKF: NACK received flag + * @arg I2C_FLAG_STOPF: STOP detection flag + * @arg I2C_FLAG_TC: Transfer complete (master mode) + * @arg I2C_FLAG_TCR: Transfer complete reload + * @arg I2C_FLAG_BERR: Bus error + * @arg I2C_FLAG_ARLO: Arbitration lost + * @arg I2C_FLAG_OVR: Overrun/Underrun + * @arg I2C_FLAG_PECERR: PEC error in reception + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag + * @arg I2C_FLAG_ALERT: SMBus Alert + * @arg I2C_FLAG_BUSY: Bus busy + * @retval The new state of I2C_FLAG (SET or RESET). + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) +{ + uint32_t tmpreg = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); + + /* Get the ISR register value */ + tmpreg = I2Cx->ISR; + + /* Get flag status */ + tmpreg &= I2C_FLAG; + + if(tmpreg != 0) + { + /* I2C_FLAG is set */ + bitstatus = SET; + } + else + { + /* I2C_FLAG is reset */ + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the I2Cx's pending flags. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg I2C_FLAG_ADDR: Address matched (slave mode) + * @arg I2C_FLAG_NACKF: NACK received flag + * @arg I2C_FLAG_STOPF: STOP detection flag + * @arg I2C_FLAG_BERR: Bus error + * @arg I2C_FLAG_ARLO: Arbitration lost + * @arg I2C_FLAG_OVR: Overrun/Underrun + * @arg I2C_FLAG_PECERR: PEC error in reception + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag + * @arg I2C_FLAG_ALERT: SMBus Alert + * @retval The new state of I2C_FLAG (SET or RESET). + */ +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); + + /* Clear the selected flag */ + I2Cx->ICR = I2C_FLAG; + } + +/** + * @brief Checks whether the specified I2C interrupt has occurred or not. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT: specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg I2C_IT_TXIS: Transmit interrupt status + * @arg I2C_IT_RXNE: Receive data register not empty + * @arg I2C_IT_ADDR: Address matched (slave mode) + * @arg I2C_IT_NACKF: NACK received flag + * @arg I2C_IT_STOPF: STOP detection flag + * @arg I2C_IT_TC: Transfer complete (master mode) + * @arg I2C_IT_TCR: Transfer complete reload + * @arg I2C_IT_BERR: Bus error + * @arg I2C_IT_ARLO: Arbitration lost + * @arg I2C_IT_OVR: Overrun/Underrun + * @arg I2C_IT_PECERR: PEC error in reception + * @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag + * @arg I2C_IT_ALERT: SMBus Alert + * @retval The new state of I2C_IT (SET or RESET). + */ +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) +{ + uint32_t tmpreg = 0; + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_IT(I2C_IT)); + + /* Check if the interrupt source is enabled or not */ + /* If Error interrupt */ + if ((uint32_t)(I2C_IT & ERROR_IT_MASK)) + { + enablestatus = (uint32_t)((I2C_CR1_ERRIE) & (I2Cx->CR1)); + } + /* If TC interrupt */ + else if ((uint32_t)(I2C_IT & TC_IT_MASK)) + { + enablestatus = (uint32_t)((I2C_CR1_TCIE) & (I2Cx->CR1)); + } + else + { + enablestatus = (uint32_t)((I2C_IT) & (I2Cx->CR1)); + } + + /* Get the ISR register value */ + tmpreg = I2Cx->ISR; + + /* Get flag status */ + tmpreg &= I2C_IT; + + /* Check the status of the specified I2C flag */ + if((tmpreg != RESET) && enablestatus) + { + /* I2C_IT is set */ + bitstatus = SET; + } + else + { + /* I2C_IT is reset */ + bitstatus = RESET; + } + + /* Return the I2C_IT status */ + return bitstatus; +} + +/** + * @brief Clears the I2Cx's interrupt pending bits. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg I2C_IT_ADDR: Address matched (slave mode) + * @arg I2C_IT_NACKF: NACK received flag + * @arg I2C_IT_STOPF: STOP detection flag + * @arg I2C_IT_BERR: Bus error + * @arg I2C_IT_ARLO: Arbitration lost + * @arg I2C_IT_OVR: Overrun/Underrun + * @arg I2C_IT_PECERR: PEC error in reception + * @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag + * @arg I2C_IT_ALERT: SMBus Alert + * @retval The new state of I2C_IT (SET or RESET). + */ +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_IT(I2C_IT)); + + /* Clear the selected flag */ + I2Cx->ICR = I2C_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_iwdg.c b/system/src/stm32f0-stdperiph/stm32f0xx_iwdg.c new file mode 100644 index 0000000..b864cb5 --- /dev/null +++ b/system/src/stm32f0-stdperiph/stm32f0xx_iwdg.c @@ -0,0 +1,293 @@ +/** + ****************************************************************************** + * @file stm32f0xx_iwdg.c + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Independent watchdog (IWDG) peripheral: + * + Prescaler and Counter configuration + * + IWDG activation + * + Flag management + * + * @verbatim + * + ============================================================================== + ##### IWDG features ##### + ============================================================================== + [..] The IWDG can be started by either software or hardware (configurable + through option byte). + + [..] The IWDG is clocked by its own dedicated low-speed clock (LSI) and + thus stays active even if the main clock fails. + Once the IWDG is started, the LSI is forced ON and cannot be disabled + (LSI cannot be disabled too), and the counter starts counting down from + the reset value of 0xFFF. When it reaches the end of count value (0x000) + a system reset is generated. + The IWDG counter should be reloaded at regular intervals to prevent + an MCU reset. + + [..] The IWDG is implemented in the VDD voltage domain that is still functional + in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). + + [..] IWDGRST flag in RCC_CSR register can be used to inform when a IWDG + reset occurs. + + [..] Min-max timeout value @40KHz (LSI): ~0.1ms / ~28.3s + The IWDG timeout may vary due to LSI frequency dispersion. STM32F0xx + devices provide the capability to measure the LSI frequency (LSI clock + should be seleted as RTC clock which is internally connected to TIM10 CH1 + input capture). The measured value can be used to have an IWDG timeout with + an acceptable accuracy. + For more information, please refer to the STM32F0xx Reference manual. + + ##### How to use this driver ##### + ============================================================================== + [..] This driver allows to use IWDG peripheral with either window option enabled + or disabled. To do so follow one of the two procedures below. + (#) Window option is enabled: + (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used + in software mode (no need to enable the LSI, it will be enabled + by hardware). + (++) Enable write access to IWDG_PR and IWDG_RLR registers using + IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function. + (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function. + (++) Configure the IWDG counter value using IWDG_SetReload() function. + This value will be loaded in the IWDG counter each time the counter + is reloaded, then the IWDG will start counting down from this value. + (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function. + (++) Configure the IWDG refresh window using IWDG_SetWindowValue() function. + + (#) Window option is disabled: + (++) Enable write access to IWDG_PR and IWDG_RLR registers using + IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function. + (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function. + (++) Configure the IWDG counter value using IWDG_SetReload() function. + This value will be loaded in the IWDG counter each time the counter + is reloaded, then the IWDG will start counting down from this value. + (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function. + (++) reload the IWDG counter at regular intervals during normal operation + to prevent an MCU reset, using IWDG_ReloadCounter() function. + (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used + in software mode (no need to enable the LSI, it will be enabled + by hardware). + + @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_iwdg.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup IWDG + * @brief IWDG driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ---------------------- IWDG registers bit mask ----------------------------*/ +/* KR register bit mask */ +#define KR_KEY_RELOAD ((uint16_t)0xAAAA) +#define KR_KEY_ENABLE ((uint16_t)0xCCCC) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup IWDG_Private_Functions + * @{ + */ + +/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions + * @brief Prescaler and Counter configuration functions + * +@verbatim + ============================================================================== + ##### Prescaler and Counter configuration functions ##### + ============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. + * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. + * This parameter can be one of the following values: + * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers + * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers + * @retval None + */ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) +{ + /* Check the parameters */ + assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); + IWDG->KR = IWDG_WriteAccess; +} + +/** + * @brief Sets IWDG Prescaler value. + * @param IWDG_Prescaler: specifies the IWDG Prescaler value. + * This parameter can be one of the following values: + * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 + * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 + * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 + * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 + * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 + * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 + * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 + * @retval None + */ +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); + IWDG->PR = IWDG_Prescaler; +} + +/** + * @brief Sets IWDG Reload value. + * @param Reload: specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + * @retval None + */ +void IWDG_SetReload(uint16_t Reload) +{ + /* Check the parameters */ + assert_param(IS_IWDG_RELOAD(Reload)); + IWDG->RLR = Reload; +} + +/** + * @brief Reloads IWDG counter with value defined in the reload register + * (write access to IWDG_PR and IWDG_RLR registers disabled). + * @param None + * @retval None + */ +void IWDG_ReloadCounter(void) +{ + IWDG->KR = KR_KEY_RELOAD; +} + + +/** + * @brief Sets the IWDG window value. + * @param WindowValue: specifies the window value to be compared to the downcounter. + * @retval None + */ +void IWDG_SetWindowValue(uint16_t WindowValue) +{ + /* Check the parameters */ + assert_param(IS_IWDG_WINDOW_VALUE(WindowValue)); + IWDG->WINR = WindowValue; +} + +/** + * @} + */ + +/** @defgroup IWDG_Group2 IWDG activation function + * @brief IWDG activation function + * +@verbatim + ============================================================================== + ##### IWDG activation function ##### + ============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). + * @param None + * @retval None + */ +void IWDG_Enable(void) +{ + IWDG->KR = KR_KEY_ENABLE; +} + +/** + * @} + */ + +/** @defgroup IWDG_Group3 Flag management function + * @brief Flag management function + * +@verbatim + =============================================================================== + ##### Flag management function ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Checks whether the specified IWDG flag is set or not. + * @param IWDG_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg IWDG_FLAG_PVU: Prescaler Value Update on going + * @arg IWDG_FLAG_RVU: Reload Value Update on going + * @arg IWDG_FLAG_WVU: Counter Window Value Update on going + * @retval The new state of IWDG_FLAG (SET or RESET). + */ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_IWDG_FLAG(IWDG_FLAG)); + if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_misc.c b/system/src/stm32f0-stdperiph/stm32f0xx_misc.c new file mode 100644 index 0000000..d44d7fe --- /dev/null +++ b/system/src/stm32f0-stdperiph/stm32f0xx_misc.c @@ -0,0 +1,167 @@ +/** + ****************************************************************************** + * @file stm32f0xx_misc.c + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file provides all the miscellaneous firmware functions (add-on + * to CMSIS functions). + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_misc.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup MISC + * @brief MISC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup MISC_Private_Functions + * @{ + */ +/** + * +@verbatim + ******************************************************************************* + ##### Interrupts configuration functions ##### + ******************************************************************************* + [..] This section provide functions allowing to configure the NVIC interrupts + (IRQ). The Cortex-M0 exceptions are managed by CMSIS functions. + (#) Enable and Configure the priority of the selected IRQ Channels. + The priority can be 0..3. + + -@- Lower priority values gives higher priority. + -@- Priority Order: + (#@) Lowest priority. + (#@) Lowest hardware priority (IRQn position). + +@endverbatim +*/ + +/** + * @brief Initializes the NVIC peripheral according to the specified + * parameters in the NVIC_InitStruct. + * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains + * the configuration information for the specified NVIC peripheral. + * @retval None + */ +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) +{ + uint32_t tmppriority = 0x00; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); + assert_param(IS_NVIC_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPriority)); + + if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + /* Compute the Corresponding IRQ Priority --------------------------------*/ + tmppriority = NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel >> 0x02]; + tmppriority &= (uint32_t)(~(((uint32_t)0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8))); + tmppriority |= (uint32_t)((((uint32_t)NVIC_InitStruct->NVIC_IRQChannelPriority << 6) & 0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8)); + + NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel >> 0x02] = tmppriority; + + /* Enable the Selected IRQ Channels --------------------------------------*/ + NVIC->ISER[0] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } + else + { + /* Disable the Selected IRQ Channels -------------------------------------*/ + NVIC->ICER[0] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } +} + +/** + * @brief Selects the condition for the system to enter low power mode. + * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. + * This parameter can be one of the following values: + * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend. + * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request. + * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit. + * @param NewState: new state of LP condition. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_NVIC_LP(LowPowerMode)); + + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + SCB->SCR |= LowPowerMode; + } + else + { + SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); + } +} + +/** + * @brief Configures the SysTick clock source. + * @param SysTick_CLKSource: specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); + + if (SysTick_CLKSource == SysTick_CLKSource_HCLK) + { + SysTick->CTRL |= SysTick_CLKSource_HCLK; + } + else + { + SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_pwr.c b/system/src/stm32f0-stdperiph/stm32f0xx_pwr.c new file mode 100644 index 0000000..e5779c6 --- /dev/null +++ b/system/src/stm32f0-stdperiph/stm32f0xx_pwr.c @@ -0,0 +1,566 @@ +/** + ****************************************************************************** + * @file stm32f0xx_pwr.c + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Backup Domain Access + * + PVD configuration + * + WakeUp pins configuration + * + Low Power modes configuration + * + Flags management + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_pwr.h" +#include "stm32f0xx_rcc.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup PWR + * @brief PWR driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* ------------------ PWR registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_DS_MASK ((uint32_t)0xFFFFFFFC) +#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup PWR_Private_Functions + * @{ + */ + +/** @defgroup PWR_Group1 Backup Domain Access function + * @brief Backup Domain Access function + * +@verbatim + ============================================================================== + ##### Backup Domain Access function ##### + ============================================================================== + + [..] After reset, the Backup Domain Registers (RCC BDCR Register, RTC registers + and RTC backup registers) are protected against possible stray write accesses. + [..] To enable access to Backup domain use the PWR_BackupAccessCmd(ENABLE) function. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the PWR peripheral registers to their default reset values. + * @param None + * @retval None + */ +void PWR_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); +} + +/** + * @brief Enables or disables access to the Backup domain registers. + * @note If the HSE divided by 32 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @param NewState: new state of the access to the Backup domain registers. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_BackupAccessCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Backup Domain Access */ + PWR->CR |= PWR_CR_DBP; + } + else + { + /* Disable the Backup Domain Access */ + PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_DBP); + } +} + +/** + * @} + */ + +/** @defgroup PWR_Group2 PVD configuration functions + * @brief PVD configuration functions + * +@verbatim + ============================================================================== + ##### PVD configuration functions ##### + ============================================================================== + [..] + (+) The PVD is used to monitor the VDD power supply by comparing it to a threshold + selected by the PVD Level (PLS[2:0] bits in the PWR_CR). + (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the + PVD threshold. This event is internally connected to the EXTI line16 + and can generate an interrupt if enabled through the EXTI registers. + (+) The PVD is stopped in Standby mode. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @note This function is not applicable for STM32F030 devices. + * @param PWR_PVDLevel: specifies the PVD detection level + * This parameter can be one of the following values: + * @arg PWR_PVDLevel_0 + * @arg PWR_PVDLevel_1 + * @arg PWR_PVDLevel_2 + * @arg PWR_PVDLevel_3 + * @arg PWR_PVDLevel_4 + * @arg PWR_PVDLevel_5 + * @arg PWR_PVDLevel_6 + * @arg PWR_PVDLevel_7 + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @retval None + */ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); + + tmpreg = PWR->CR; + + /* Clear PLS[7:5] bits */ + tmpreg &= CR_PLS_MASK; + + /* Set PLS[7:5] bits according to PWR_PVDLevel value */ + tmpreg |= PWR_PVDLevel; + + /* Store the new value */ + PWR->CR = tmpreg; +} + +/** + * @brief Enables or disables the Power Voltage Detector(PVD). + * @note This function is not applicable for STM32F030 devices. + * @param NewState: new state of the PVD. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_PVDCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the PVD */ + PWR->CR |= PWR_CR_PVDE; + } + else + { + /* Disable the PVD */ + PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_PVDE); + } +} + +/** + * @} + */ + +/** @defgroup PWR_Group3 WakeUp pins configuration functions + * @brief WakeUp pins configuration functions + * +@verbatim + ============================================================================== + ##### WakeUp pin configuration functions ##### + ============================================================================== + + (+) WakeUp pins are used to wakeup the system from Standby mode. These pins are + forced in input pull down configuration and are active on rising edges. + (+) There are eight WakeUp pins: WakeUp Pin 1 on PA.00 and WakeUp Pin 2 on PC.13. + The following WakeUp pins are only applicable for STM32F072 dvices: + WakeUp Pin 3 on PE.06, WakeUp Pin 4 on PA.02, WakeUp Pin 5 on PC.05, + WakeUp Pin 6 on PB.05, WakeUp Pin 7 on PB.15 and WakeUp Pin 8 on PF.02. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the WakeUp Pin functionality. + * @param PWR_WakeUpPin: specifies the WakeUpPin. + * This parameter can be one of the following values + * @arg PWR_WakeUpPin_1 + * @arg PWR_WakeUpPin_2 + * @arg PWR_WakeUpPin_3, only applicable for STM32F072 devices + * @arg PWR_WakeUpPin_4, only applicable for STM32F072 devices + * @arg PWR_WakeUpPin_5, only applicable for STM32F072 devices + * @arg PWR_WakeUpPin_6, only applicable for STM32F072 devices + * @arg PWR_WakeUpPin_7, only applicable for STM32F072 devices + * @arg PWR_WakeUpPin_8, only applicable for STM32F072 devices + * @param NewState: new state of the WakeUp Pin functionality. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the EWUPx pin */ + PWR->CSR |= PWR_WakeUpPin; + } + else + { + /* Disable the EWUPx pin */ + PWR->CSR &= ~PWR_WakeUpPin; + } +} + +/** + * @} + */ + + +/** @defgroup PWR_Group4 Low Power modes configuration functions + * @brief Low Power modes configuration functions + * +@verbatim + ============================================================================== + ##### Low Power modes configuration functions ##### + ============================================================================== + + [..] The devices feature three low-power modes: + (+) Sleep mode: Cortex-M0 core stopped, peripherals kept running. + (+) Stop mode: all clocks are stopped, regulator running, regulator in low power mode + (+) Standby mode: VCORE domain powered off + + *** Sleep mode *** + ================== + [..] + (+) Entry: + (++) The Sleep mode is entered by executing the WFE() or WFI() instructions. + (+) Exit: + (++) Any peripheral interrupt acknowledged by the nested vectored interrupt + controller (NVIC) can wake up the device from Sleep mode. + + *** Stop mode *** + ================= + [..] In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the HSI, + the HSI14 and the HSE RC oscillators are disabled. Internal SRAM and register + contents are preserved. + The voltage regulator can be configured either in normal or low-power mode. + + (+) Entry: + (++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,) + function with regulator in LowPower or with Regulator ON. + (+) Exit: + (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode + or any internal IPs (I2C, UASRT or CEC) wakeup event. + + *** Standby mode *** + ==================== + [..] The Standby mode allows to achieve the lowest power consumption. It is based + on the Cortex-M0 deepsleep mode, with the voltage regulator disabled. + The VCORE domain is consequently powered off. The PLL, the HSI, the HSI14 + oscillator and the HSE oscillator are also switched off. SRAM and register + contents are lost except for the Backup domain (RTC registers, RTC backup + registers and Standby circuitry). + + [..] The voltage regulator is OFF. + + (+) Entry: + (++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function. + (+) Exit: + (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, + tamper event, time-stamp event, external reset in NRST pin, IWDG reset. + + *** Auto-wakeup (AWU) from low-power mode *** + ============================================= + [..] The MCU can be woken up from low-power mode by an RTC Alarm event, a tamper + event, a time-stamp event, or a comparator event, without depending on an + external interrupt (Auto-wakeup mode). + + (+) RTC auto-wakeup (AWU) from the Stop mode + (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to: + (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt + or Event modes) using the EXTI_Init() function. + (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function + (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() + and RTC_AlarmCmd() functions. + (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it + is necessary to: + (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt + or Event modes) using the EXTI_Init() function. + (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() + function. + (+++) Configure the RTC to detect the tamper or time stamp event using the + RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() + functions. + + (+) RTC auto-wakeup (AWU) from the Standby mode + (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to: + (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function. + (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() + and RTC_AlarmCmd() functions. + (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it + is necessary to: + (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() + function. + (+++) Configure the RTC to detect the tamper or time stamp event using the + RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() + functions. + + (+) Comparator auto-wakeup (AWU) from the Stop mode + (++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup + event, it is necessary to: + (+++) Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2 + to be sensitive to to the selected edges (falling, rising or falling + and rising) (Interrupt or Event modes) using the EXTI_Init() function. + (+++) Configure the comparator to generate the event. + +@endverbatim + * @{ + */ + +/** + * @brief Enters Sleep mode. + * @note In Sleep mode, all I/O pins keep the same state as in Run mode. + * @param PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction + * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction + * @retval None + */ +void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry)); + + /* Clear SLEEPDEEP bit of Cortex-M0 System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + + /* Select SLEEP mode entry -------------------------------------------------*/ + if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } +} + +/** + * @brief Enters STOP mode. + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * @note When exiting Stop mode by issuing an interrupt or a wakeup event, + * the HSI RC oscillator is selected as system clock. + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * @param PWR_Regulator: specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_Regulator_ON: STOP mode with regulator ON + * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode + * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction + * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction + @arg PWR_STOPEntry_SLEEPONEXIT: enter STOP mode with SLEEPONEXIT instruction + * @retval None + */ +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(PWR_Regulator)); + assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); + + /* Select the regulator state in STOP mode ---------------------------------*/ + tmpreg = PWR->CR; + /* Clear PDDS and LPDSR bits */ + tmpreg &= CR_DS_MASK; + + /* Set LPDSR bit according to PWR_Regulator value */ + tmpreg |= PWR_Regulator; + + /* Store the new value */ + PWR->CR = tmpreg; + + /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Select STOP mode entry --------------------------------------------------*/ + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + } + else if (PWR_STOPEntry == PWR_STOPEntry_WFE) + { + /* Request Wait For Event */ + __WFE(); + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + } + else + { + /* Set SLEEP on exit bit of Cortex-M0 System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk; + } +} + +/** + * @brief Enters STANDBY mode. + * @note In Standby mode, all I/O pins are high impedance except for: + * - Reset pad (still available) + * - RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper, + * time-stamp, RTC Alarm out, or RTC clock calibration out. + * - WKUP pin 1 (PA0) if enabled. + * @note The Wakeup flag (WUF) need to be cleared at application level before to call this function + * @param None + * @retval None + */ +void PWR_EnterSTANDBYMode(void) +{ + /* Select STANDBY mode */ + PWR->CR |= PWR_CR_PDDS; + + /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @} + */ + +/** @defgroup PWR_Group5 Flags management functions + * @brief Flags management functions + * +@verbatim + ============================================================================== + ##### Flags management functions ##### + ============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Checks whether the specified PWR flag is set or not. + * @param PWR_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup + * event was received from the WKUP pin or from the RTC alarm + * (Alarm A or Alarm B), RTC Tamper event or RTC TimeStamp event. + * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the + * system was resumed from StandBy mode. + * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD + * is enabled by the PWR_PVDCmd() function. + * @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag. + * This flag indicates the state of the internal voltage + * reference, VREFINT. + * @retval The new state of PWR_FLAG (SET or RESET). + */ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); + + if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the PWR's pending flags. + * @param PWR_FLAG: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + * @retval None + */ +void PWR_ClearFlag(uint32_t PWR_FLAG) +{ + /* Check the parameters */ + assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); + + PWR->CR |= PWR_FLAG << 2; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_rcc.c b/system/src/stm32f0-stdperiph/stm32f0xx_rcc.c new file mode 100644 index 0000000..5b8af2c --- /dev/null +++ b/system/src/stm32f0-stdperiph/stm32f0xx_rcc.c @@ -0,0 +1,1781 @@ +/** + ****************************************************************************** + * @file stm32f0xx_rcc.c + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Reset and clock control (RCC) peripheral: + * + Internal/external clocks, PLL, CSS and MCO configuration + * + System, AHB and APB busses clocks configuration + * + Peripheral clocks configuration + * + Interrupts and flags management + * + @verbatim + + =============================================================================== + ##### RCC specific features ##### + =============================================================================== + [..] After reset the device is running from HSI (8 MHz) with Flash 0 WS, + all peripherals are off except internal SRAM, Flash and SWD. + (#) There is no prescaler on High speed (AHB) and Low speed (APB) busses; + all peripherals mapped on these busses are running at HSI speed. + (#) The clock for all peripherals is switched off, except the SRAM and FLASH. + (#) All GPIOs are in input floating state, except the SWD pins which + are assigned to be used for debug purpose. + [..] Once the device started from reset, the user application has to: + (#) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (#) Configure the System clock frequency and Flash settings + (#) Configure the AHB and APB busses prescalers + (#) Enable the clock for the peripheral(s) to be used + (#) Configure the clock source(s) for peripherals which clocks are not + derived from the System clock (ADC, CEC, I2C, USART, RTC and IWDG) + + @endverbatim + + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_rcc.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup RCC + * @brief RCC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* ---------------------- RCC registers mask -------------------------------- */ +/* RCC Flag Mask */ +#define FLAG_MASK ((uint8_t)0x1F) + +/* CR register byte 2 (Bits[23:16]) base address */ +#define CR_BYTE2_ADDRESS ((uint32_t)0x40021002) + +/* CFGR register byte 3 (Bits[31:23]) base address */ +#define CFGR_BYTE3_ADDRESS ((uint32_t)0x40021007) + +/* CIR register byte 1 (Bits[15:8]) base address */ +#define CIR_BYTE1_ADDRESS ((uint32_t)0x40021009) + +/* CIR register byte 2 (Bits[23:16]) base address */ +#define CIR_BYTE2_ADDRESS ((uint32_t)0x4002100A) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RCC_Private_Functions + * @{ + */ + +/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions + * @brief Internal and external clocks, PLL, CSS and MCO configuration functions + * +@verbatim + =============================================================================== + ##### Internal-external clocks, PLL, CSS and MCO configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to configure the internal/external clocks, + PLL, CSS and MCO. + (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly + or through the PLL as System clock source. + The HSI clock can be used also to clock the USART, I2C and CEC peripherals. + (#) HSI14 (high-speed internal for ADC), 14 MHz factory-trimmed RC used to clock + the ADC peripheral. + (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC + clock source. + (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also as RTC clock source. + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + LSE can be used also to clock the USART and CEC peripherals. + (#) PLL (clocked by HSI or HSE), for System clock. + (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs + (HSE used directly or through PLL as System clock source), the System clock + is automatically switched to HSI and an interrupt is generated if enabled. + The interrupt is linked to the Cortex-M0 NMI (Non-Maskable Interrupt) + exception vector. + (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSI14, LSI, + HSE, LSE or PLL (divided by 2) clock on PA8 pin. + +@endverbatim + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * @note HSI ON and used as system clock source + * @note HSI14, HSE and PLL OFF + * @note AHB, APB prescaler set to 1. + * @note CSS and MCO OFF + * @note All interrupts disabled + * @note However, this function doesn't modify the configuration of the + * @note Peripheral clocks + * @note LSI, LSE and RTC clocks + * @param None + * @retval None + */ +void RCC_DeInit(void) +{ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + +#if defined (STM32F051) + /* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */ + RCC->CFGR &= (uint32_t)0xF8FFB80C; +#else + /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */ + RCC->CFGR &= (uint32_t)0x08FFB80C; +#endif /* STM32F051 */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ + RCC->CFGR &= (uint32_t)0xFFC0FFFF; + + /* Reset PREDIV1[3:0] bits */ + RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; + + /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFF0FEAC; + + /* Reset HSI14 bit */ + RCC->CR2 &= (uint32_t)0xFFFFFFFE; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; +} + +/** + * @brief Configures the External High Speed oscillator (HSE). + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function resets the CSSON bit, so if the Clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param RCC_HSE: specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg RCC_HSE_ON: turn ON the HSE oscillator + * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock + * @retval None + */ +void RCC_HSEConfig(uint8_t RCC_HSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_HSE)); + + /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ + *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE_OFF; + + /* Set the new HSE configuration -------------------------------------------*/ + *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE; + +} + +/** + * @brief Waits for HSE start-up. + * @note This function waits on HSERDY flag to be set and return SUCCESS if + * this flag is set, otherwise returns ERROR if the timeout is reached + * and this flag is not set. The timeout value is defined by the constant + * HSE_STARTUP_TIMEOUT in stm32f0xx.h file. You can tailor it depending + * on the HSE crystal used in your application. + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: HSE oscillator is stable and ready to use + * - ERROR: HSE oscillator not yet ready + */ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + ErrorStatus status = ERROR; + FlagStatus HSEStatus = RESET; + + /* Wait till HSE is ready and if timeout is reached exit */ + do + { + HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + StartUpCounter++; + } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); + + if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * Refer to the Application Note AN4067 for more details on how to + * calibrate the HSI. + * @param HSICalibrationValue: specifies the HSI calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * @retval None + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue)); + + tmpreg = RCC->CR; + + /* Clear HSITRIM[4:0] bits */ + tmpreg &= ~RCC_CR_HSITRIM; + + /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ + tmpreg |= (uint32_t)HSICalibrationValue << 3; + + /* Store the new value */ + RCC->CR = tmpreg; +} + +/** + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * @note After enabling the HSI, the application software should wait on + * HSIRDY flag to be set indicating that HSI clock is stable and can + * be used to clock the PLL and/or system clock. + * @note HSI can not be stopped if it is used directly or through the PLL + * as system clock. In this case, you have to select another source + * of the system clock then stop the HSI. + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * @param NewState: new state of the HSI. + * This parameter can be: ENABLE or DISABLE. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + * @retval None + */ +void RCC_HSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->CR |= RCC_CR_HSION; + } + else + { + RCC->CR &= ~RCC_CR_HSION; + } +} + +/** + * @brief Adjusts the Internal High Speed oscillator for ADC (HSI14) + * calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * Refer to the Application Note AN4067 for more details on how to + * calibrate the HSI14. + * @param HSI14CalibrationValue: specifies the HSI14 calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * @retval None + */ +void RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_HSI14_CALIBRATION_VALUE(HSI14CalibrationValue)); + + tmpreg = RCC->CR2; + + /* Clear HSI14TRIM[4:0] bits */ + tmpreg &= ~RCC_CR2_HSI14TRIM; + + /* Set the HSITRIM14[4:0] bits according to HSI14CalibrationValue value */ + tmpreg |= (uint32_t)HSI14CalibrationValue << 3; + + /* Store the new value */ + RCC->CR2 = tmpreg; +} + +/** + * @brief Enables or disables the Internal High Speed oscillator for ADC (HSI14). + * @note After enabling the HSI14, the application software should wait on + * HSIRDY flag to be set indicating that HSI clock is stable and can + * be used to clock the ADC. + * @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes. + * @param NewState: new state of the HSI14. + * This parameter can be: ENABLE or DISABLE. + * @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator + * clock cycles. + * @retval None + */ +void RCC_HSI14Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->CR2 |= RCC_CR2_HSI14ON; + } + else + { + RCC->CR2 &= ~RCC_CR2_HSI14ON; + } +} + +/** + * @brief Enables or disables the Internal High Speed oscillator request from ADC. + * @param NewState: new state of the HSI14 ADC request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_HSI14ADCRequestCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->CR2 &= ~RCC_CR2_HSI14DIS; + } + else + { + RCC->CR2 |= RCC_CR2_HSI14DIS; + } +} + +/** + * @brief Configures the External Low Speed oscillator (LSE). + * @note As the LSE is in the Backup domain and write access is denied to this + * domain after reset, you have to enable write access using + * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param RCC_LSE: specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg RCC_LSE_ON: turn ON the LSE oscillator + * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock + * @retval None + */ +void RCC_LSEConfig(uint32_t RCC_LSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_LSE)); + + /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ + /* Reset LSEON bit */ + RCC->BDCR &= ~(RCC_BDCR_LSEON); + + /* Reset LSEBYP bit */ + RCC->BDCR &= ~(RCC_BDCR_LSEBYP); + + /* Configure LSE */ + RCC->BDCR |= RCC_LSE; +} + +/** + * @brief Configures the External Low Speed oscillator (LSE) drive capability. + * @param RCC_LSEDrive: specifies the new state of the LSE drive capability. + * This parameter can be one of the following values: + * @arg RCC_LSEDrive_Low: LSE oscillator low drive capability. + * @arg RCC_LSEDrive_MediumLow: LSE oscillator medium low drive capability. + * @arg RCC_LSEDrive_MediumHigh: LSE oscillator medium high drive capability. + * @arg RCC_LSEDrive_High: LSE oscillator high drive capability. + * @retval None + */ +void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSE_DRIVE(RCC_LSEDrive)); + + /* Clear LSEDRV[1:0] bits */ + RCC->BDCR &= ~(RCC_BDCR_LSEDRV); + + /* Set the LSE Drive */ + RCC->BDCR |= RCC_LSEDrive; +} + +/** + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + * @note LSI can not be disabled if the IWDG is running. + * @param NewState: new state of the LSI. + * This parameter can be: ENABLE or DISABLE. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + * @retval None + */ +void RCC_LSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->CSR |= RCC_CSR_LSION; + } + else + { + RCC->CSR &= ~RCC_CSR_LSION; + } +} + +/** + * @brief Configures the PLL clock source and multiplication factor. + * @note This function must be used only when the PLL is disabled. + * + * @param RCC_PLLSource: specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock selected as PLL clock source + * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry + * @arg RCC_PLLSource_HSI48 HSI48 oscillator clock selected as PLL clock source, applicable only for STM32F072 devices + * @arg RCC_PLLSource_HSI: HSI clock selected as PLL clock entry, applicable only for STM32F072 devices + * @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as + * PLL source). + * + * @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock + * This parameter can be RCC_PLLMul_x where x:[2,16] + * + * @retval None + */ +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); + + /* Clear PLL Source [16] and Multiplier [21:18] bits */ + RCC->CFGR &= ~(RCC_CFGR_PLLMULL | RCC_CFGR_PLLSRC); + + /* Set the PLL Source and Multiplier */ + RCC->CFGR |= (uint32_t)(RCC_PLLSource | RCC_PLLMul); +} + +/** + * @brief Enables or disables the PLL. + * @note After enabling the PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The PLL can not be disabled if it is used as system clock source + * @note The PLL is disabled by hardware when entering STOP and STANDBY modes. + * @param NewState: new state of the PLL. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLLCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->CR |= RCC_CR_PLLON; + } + else + { + RCC->CR &= ~RCC_CR_PLLON; + } +} + +/** + * @brief Enables or disables the Internal High Speed oscillator for USB (HSI48). + * This function is only applicable for STM32F072 devices. + * @note After enabling the HSI48, the application software should wait on + * HSI48RDY flag to be set indicating that HSI48 clock is stable and can + * be used to clock the USB. + * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. + * @param NewState: new state of the HSI48. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_HSI48Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->CR2 |= RCC_CR2_HSI48ON; + } + else + { + RCC->CR2 &= ~RCC_CR2_HSI48ON; + } +} + +/** + * @brief Configures the PREDIV1 division factor. + * @note This function must be used only when the PLL is disabled. + * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor. + * This parameter can be RCC_PREDIV1_Divx where x:[1,16] + * @retval None + */ +void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div)); + + tmpreg = RCC->CFGR2; + /* Clear PREDIV1[3:0] bits */ + tmpreg &= ~(RCC_CFGR2_PREDIV1); + /* Set the PREDIV1 division factor */ + tmpreg |= RCC_PREDIV1_Div; + /* Store the new value */ + RCC->CFGR2 = tmpreg; +} + +/** + * @brief Enables or disables the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector. + * @param NewState: new state of the Clock Security System. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->CR |= RCC_CR_CSSON; + } + else + { + RCC->CR &= ~RCC_CR_CSSON; + } +} + +#ifdef STM32F051 +/** + * @brief Selects the clock source to output on MCO pin (PA8). + * @note PA8 should be configured in alternate function mode. + * @param RCC_MCOSource: specifies the clock source to output. + * This parameter can be one of the following values: + * @arg RCC_MCOSource_NoClock: No clock selected. + * @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected. + * @arg RCC_MCOSource_LSI: LSI oscillator clock selected. + * @arg RCC_MCOSource_LSE: LSE oscillator clock selected. + * @arg RCC_MCOSource_SYSCLK: System clock selected. + * @arg RCC_MCOSource_HSI: HSI oscillator clock selected. + * @arg RCC_MCOSource_HSE: HSE oscillator clock selected. + * @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected. + * @retval None + */ +void RCC_MCOConfig(uint8_t RCC_MCOSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource)); + + /* Select MCO clock source and prescaler */ + *(__IO uint8_t *) CFGR_BYTE3_ADDRESS = RCC_MCOSource; +} +#else + +/** + * @brief Selects the clock source to output on MCO pin (PA8) and the corresponding + * prescsaler. + * @note PA8 should be configured in alternate function mode. + * @param RCC_MCOSource: specifies the clock source to output. + * This parameter can be one of the following values: + * @arg RCC_MCOSource_NoClock: No clock selected. + * @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected. + * @arg RCC_MCOSource_LSI: LSI oscillator clock selected. + * @arg RCC_MCOSource_LSE: LSE oscillator clock selected. + * @arg RCC_MCOSource_SYSCLK: System clock selected. + * @arg RCC_MCOSource_HSI: HSI oscillator clock selected. + * @arg RCC_MCOSource_HSE: HSE oscillator clock selected. + * @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected. + * @arg RCC_MCOSource_PLLCLK: PLL clock selected. + * @arg RCC_MCOSource_HSI48: HSI48 clock selected. + * @param RCC_MCOPrescaler: specifies the prescaler on MCO pin. + * This parameter can be one of the following values: + * @arg RCC_MCOPrescaler_1: MCO clock is divided by 1. + * @arg RCC_MCOPrescaler_2: MCO clock is divided by 2. + * @arg RCC_MCOPrescaler_4: MCO clock is divided by 4. + * @arg RCC_MCOPrescaler_8: MCO clock is divided by 8. + * @arg RCC_MCOPrescaler_16: MCO clock is divided by 16. + * @arg RCC_MCOPrescaler_32: MCO clock is divided by 32. + * @arg RCC_MCOPrescaler_64: MCO clock is divided by 64. + * @arg RCC_MCOPrescaler_128: MCO clock is divided by 128. + * @retval None + */ +void RCC_MCOConfig(uint8_t RCC_MCOSource, uint32_t RCC_MCOPrescaler) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource)); + assert_param(IS_RCC_MCO_PRESCALER(RCC_MCOPrescaler)); + + /* Get CFGR value */ + tmpreg = RCC->CFGR; + /* Clear MCOPRE[2:0] bits */ + tmpreg &= ~(RCC_CFGR_MCO_PRE | RCC_CFGR_MCO | RCC_CFGR_PLLNODIV); + /* Set the RCC_MCOSource and RCC_MCOPrescaler */ + tmpreg |= (RCC_MCOPrescaler | ((uint32_t)RCC_MCOSource<<24)); + /* Store the new value */ + RCC->CFGR = tmpreg; +} +#endif /* STM32F072 */ + +/** + * @} + */ + +/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions + * @brief System, AHB and APB busses clocks configuration functions + * +@verbatim + =============================================================================== + ##### System, AHB and APB busses clocks configuration functions ##### + =============================================================================== + + [..] This section provide functions allowing to configure the System, AHB and + APB busses clocks. + (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, + HSE and PLL. + The AHB clock (HCLK) is derived from System clock through configurable prescaler + and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA and GPIO). + and APB (PCLK) clocks are derived from AHB clock through + configurable prescalers and used to clock the peripherals mapped on these busses. + You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks. + + -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: + (+@) The ADC clock which is derived from HSI14 or APB (APB divided by a + programmable prescaler: 2 or 4). + (+@) The CEC clock which is derived from LSE or HSI divided by 244. + (+@) The I2C clock which is derived from HSI or system clock (SYSCLK). + (+@) The USART clock which is derived from HSI, system clock (SYSCLK), APB or LSE. + (+@) The RTC/LCD clock which is derived from the LSE, LSI or 2 MHz HSE_RTC (HSE + divided by a programmable prescaler). + The System clock (SYSCLK) frequency must be higher or equal to the RTC/LCD + clock frequency. + (+@) IWDG clock which is always the LSI clock. + + (#) The maximum frequency of the SYSCLK, HCLK and PCLK is 48 MHz. + Depending on the maximum frequency, the FLASH wait states (WS) should be + adapted accordingly: + +--------------------------------------------- + + | Wait states | HCLK clock frequency (MHz) | + |---------------|------------------------------| + |0WS(1CPU cycle)| 0 < HCLK <= 24 | + |---------------|------------------------------| + |1WS(2CPU cycle)| 24 < HCLK <= 48 | + +----------------------------------------------+ + + (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and + prefetch is disabled. + + [..] It is recommended to use the following software sequences to tune the number + of wait states needed to access the Flash memory with the CPU frequency (HCLK). + (+) Increasing the CPU frequency + (++) Program the Flash Prefetch buffer, using "FLASH_PrefetchBufferCmd(ENABLE)" + function + (++) Check that Flash Prefetch buffer activation is taken into account by + reading FLASH_ACR using the FLASH_GetPrefetchBufferStatus() function + (++) Program Flash WS to 1, using "FLASH_SetLatency(FLASH_Latency_1)" function + (++) Check that the new number of WS is taken into account by reading FLASH_ACR + (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function + (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function + (++) Check that the new CPU clock source is taken into account by reading + the clock source status, using "RCC_GetSYSCLKSource()" function + (+) Decreasing the CPU frequency + (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function + (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function + (++) Check that the new CPU clock source is taken into account by reading + the clock source status, using "RCC_GetSYSCLKSource()" function + (++) Program the new number of WS, using "FLASH_SetLatency()" function + (++) Check that the new number of WS is taken into account by reading FLASH_ACR + (++) Disable the Flash Prefetch buffer using "FLASH_PrefetchBufferCmd(DISABLE)" + function + (++) Check that Flash Prefetch buffer deactivation is taken into account by reading FLASH_ACR + using the FLASH_GetPrefetchBufferStatus() function. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the system clock (SYSCLK). + * @note The HSI is used (enabled by hardware) as system clock source after + * startup from Reset, wake-up from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after startup delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source will be ready. + * You can use RCC_GetSYSCLKSource() function to know which clock is + * currently used as system clock source. + * @param RCC_SYSCLKSource: specifies the clock source used as system clock source + * This parameter can be one of the following values: + * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source + * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source + * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source + * @arg RCC_SYSCLKSource_HSI48: HSI48 selected as system clock source, applicable only for STM32F072 devices + * @retval None + */ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); + + tmpreg = RCC->CFGR; + + /* Clear SW[1:0] bits */ + tmpreg &= ~RCC_CFGR_SW; + + /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ + tmpreg |= RCC_SYSCLKSource; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Returns the clock source used as system clock. + * @param None + * @retval The clock source used as system clock. The returned value can be one + * of the following values: + * - 0x00: HSI used as system clock + * - 0x04: HSE used as system clock + * - 0x08: PLL used as system clock + * - 0x0C: HSI48 used as system clock, applicable only for STM32F072 devices + */ +uint8_t RCC_GetSYSCLKSource(void) +{ + return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS)); +} + +/** + * @brief Configures the AHB clock (HCLK). + * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * This parameter can be one of the following values: + * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK + * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 + * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 + * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 + * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 + * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 + * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 + * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 + * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 + * @retval None + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_HCLK(RCC_SYSCLK)); + + tmpreg = RCC->CFGR; + + /* Clear HPRE[3:0] bits */ + tmpreg &= ~RCC_CFGR_HPRE; + + /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ + tmpreg |= RCC_SYSCLK; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Configures the APB clock (PCLK). + * @param RCC_HCLK: defines the APB clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_Div1: APB clock = HCLK + * @arg RCC_HCLK_Div2: APB clock = HCLK/2 + * @arg RCC_HCLK_Div4: APB clock = HCLK/4 + * @arg RCC_HCLK_Div8: APB clock = HCLK/8 + * @arg RCC_HCLK_Div16: APB clock = HCLK/16 + * @retval None + */ +void RCC_PCLKConfig(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + + tmpreg = RCC->CFGR; + + /* Clear PPRE[2:0] bits */ + tmpreg &= ~RCC_CFGR_PPRE; + + /* Set PPRE[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Configures the ADC clock (ADCCLK). + * @note This function is obsolete. + * For proper ADC clock selection, refer to ADC_ClockModeConfig() in the ADC driver + * @param RCC_ADCCLK: defines the ADC clock source. This clock is derived + * from the HSI14 or APB clock (PCLK). + * This parameter can be one of the following values: + * @arg RCC_ADCCLK_HSI14: ADC clock = HSI14 (14MHz) + * @arg RCC_ADCCLK_PCLK_Div2: ADC clock = PCLK/2 + * @arg RCC_ADCCLK_PCLK_Div4: ADC clock = PCLK/4 + * @retval None + */ +void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK) +{ + /* Check the parameters */ + assert_param(IS_RCC_ADCCLK(RCC_ADCCLK)); + + /* Clear ADCPRE bit */ + RCC->CFGR &= ~RCC_CFGR_ADCPRE; + /* Set ADCPRE bits according to RCC_PCLK value */ + RCC->CFGR |= RCC_ADCCLK & 0xFFFF; + + /* Clear ADCSW bit */ + RCC->CFGR3 &= ~RCC_CFGR3_ADCSW; + /* Set ADCSW bits according to RCC_ADCCLK value */ + RCC->CFGR3 |= RCC_ADCCLK >> 16; +} + +/** + * @brief Configures the CEC clock (CECCLK). + * @param RCC_CECCLK: defines the CEC clock source. This clock is derived + * from the HSI or LSE clock. + * This parameter can be one of the following values: + * @arg RCC_CECCLK_HSI_Div244: CEC clock = HSI/244 (32768Hz) + * @arg RCC_CECCLK_LSE: CEC clock = LSE + * @retval None + */ +void RCC_CECCLKConfig(uint32_t RCC_CECCLK) +{ + /* Check the parameters */ + assert_param(IS_RCC_CECCLK(RCC_CECCLK)); + + /* Clear CECSW bit */ + RCC->CFGR3 &= ~RCC_CFGR3_CECSW; + /* Set CECSW bits according to RCC_CECCLK value */ + RCC->CFGR3 |= RCC_CECCLK; +} + +/** + * @brief Configures the I2C1 clock (I2C1CLK). + * @param RCC_I2CCLK: defines the I2C1 clock source. This clock is derived + * from the HSI or System clock. + * This parameter can be one of the following values: + * @arg RCC_I2C1CLK_HSI: I2C1 clock = HSI + * @arg RCC_I2C1CLK_SYSCLK: I2C1 clock = System Clock + * @retval None + */ +void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK) +{ + /* Check the parameters */ + assert_param(IS_RCC_I2CCLK(RCC_I2CCLK)); + + /* Clear I2CSW bit */ + RCC->CFGR3 &= ~RCC_CFGR3_I2C1SW; + /* Set I2CSW bits according to RCC_I2CCLK value */ + RCC->CFGR3 |= RCC_I2CCLK; +} + +/** + * @brief Configures the USART1 clock (USART1CLK). + * @param RCC_USARTCLK: defines the USART clock source. This clock is derived + * from the HSI or System clock. + * This parameter can be one of the following values: + * @arg RCC_USART1CLK_PCLK: USART1 clock = APB Clock (PCLK) + * @arg RCC_USART1CLK_SYSCLK: USART1 clock = System Clock + * @arg RCC_USART1CLK_LSE: USART1 clock = LSE Clock + * @arg RCC_USART1CLK_HSI: USART1 clock = HSI Clock + * @arg RCC_USART2CLK_PCLK: USART2 clock = APB Clock (PCLK), applicable only for STM32F072 and STM32F091 devices + * @arg RCC_USART2CLK_SYSCLK: USART2 clock = System Clock, applicable only for STM32F072 and STM32F091 devices + * @arg RCC_USART2CLK_LSE: USART2 clock = LSE Clock, applicable only for STM32F072 and STM32F091 devices + * @arg RCC_USART2CLK_HSI: USART2 clock = HSI Clock, applicable only for STM32F072 and STM32F091 devices + * @arg RCC_USART3CLK_PCLK: USART3 clock = APB Clock (PCLK), applicable only for STM32F091 devices + * @arg RCC_USART3CLK_SYSCLK: USART3 clock = System Clock, applicable only for STM32F091 devices + * @arg RCC_USART3CLK_LSE: USART3 clock = LSE Clock, applicable only for STM32F091 devices + * @arg RCC_USART3CLK_HSI: USART3 clock = HSI Clock, applicable only for STM32F091 devices + * @retval None + */ +void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_RCC_USARTCLK(RCC_USARTCLK)); + + /* Get USART index */ + tmp = (RCC_USARTCLK >> 28); + + /* Clear USARTSW[1:0] bit */ + if (tmp == (uint32_t)0x00000001) + { + /* Clear USART1SW[1:0] bit */ + RCC->CFGR3 &= ~RCC_CFGR3_USART1SW; + } + else if (tmp == (uint32_t)0x00000002) + { + /* Clear USART2SW[1:0] bit */ + RCC->CFGR3 &= ~RCC_CFGR3_USART2SW; + } + else + { + /* Clear USART3SW[1:0] bit */ + RCC->CFGR3 &= ~RCC_CFGR3_USART3SW; + } + + /* Set USARTxSW bits according to RCC_USARTCLK value */ + RCC->CFGR3 |= RCC_USARTCLK; +} + +/** + * @brief Configures the USB clock (USBCLK). + * This function is only applicable for STM32F072 devices. + * @param RCC_USBCLK: defines the USB clock source. This clock is derived + * from the HSI48 or system clock. + * This parameter can be one of the following values: + * @arg RCC_USBCLK_HSI48: USB clock = HSI48 + * @arg RCC_USBCLK_PLLCLK: USB clock = PLL clock + * @retval None + */ +void RCC_USBCLKConfig(uint32_t RCC_USBCLK) +{ + /* Check the parameters */ + assert_param(IS_RCC_USBCLK(RCC_USBCLK)); + + /* Clear USBSW bit */ + RCC->CFGR3 &= ~RCC_CFGR3_USBSW; + /* Set USBSW bits according to RCC_USBCLK value */ + RCC->CFGR3 |= RCC_USBCLK; +} + +/** + * @brief Returns the frequencies of the System, AHB and APB busses clocks. + * @note The frequency returned by this function is not the real frequency + * in the chip. It is calculated based on the predefined constant and + * the source selected by RCC_SYSCLKConfig(): + * + * @note If SYSCLK source is HSI, function returns constant HSI_VALUE(*) + * + * @note If SYSCLK source is HSE, function returns constant HSE_VALUE(**) + * + * @note If SYSCLK source is PLL, function returns constant HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * @note If SYSCLK source is HSI48, function returns constant HSI48_VALUE(***) + * + * @note (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature, refer to RCC_AdjustHSICalibrationValue(). + * + * @note (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * return wrong result. + * + * @note (***) HSI48_VALUE is a constant defined in stm32f0xx.h file (default value + * 48 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * + * @note This function can be used by the user application to compute the + * baudrate for the communication peripherals or configure other parameters. + * @note Each time SYSCLK, HCLK and/or PCLK clock changes, this function + * must be called to update the structure's field. Otherwise, any + * configuration based on this function will be incorrect. + * + * @retval None + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0, presc = 0, pllclk = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + pllclk = (HSI_VALUE >> 1) * pllmull; + } + else + { + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + pllclk = (HSE_VALUE / prediv1factor) * pllmull; + } + RCC_Clocks->SYSCLK_Frequency = pllclk; + break; + case 0x0C: /* HSI48 used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSI48_VALUE; + break; + default: /* HSI used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + } + /* Compute HCLK, PCLK clocks frequencies -----------------------------------*/ + /* Get HCLK prescaler */ + tmp = RCC->CFGR & RCC_CFGR_HPRE; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + + /* Get PCLK prescaler */ + tmp = RCC->CFGR & RCC_CFGR_PPRE; + tmp = tmp >> 8; + presc = APBAHBPrescTable[tmp]; + /* PCLK clock frequency */ + RCC_Clocks->PCLK_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + + /* ADCCLK clock frequency */ + if((RCC->CFGR3 & RCC_CFGR3_ADCSW) != RCC_CFGR3_ADCSW) + { + /* ADC Clock is HSI14 Osc. */ + RCC_Clocks->ADCCLK_Frequency = HSI14_VALUE; + } + else + { + if((RCC->CFGR & RCC_CFGR_ADCPRE) != RCC_CFGR_ADCPRE) + { + /* ADC Clock is derived from PCLK/2 */ + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK_Frequency >> 1; + } + else + { + /* ADC Clock is derived from PCLK/4 */ + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK_Frequency >> 2; + } + + } + + /* CECCLK clock frequency */ + if((RCC->CFGR3 & RCC_CFGR3_CECSW) != RCC_CFGR3_CECSW) + { + /* CEC Clock is HSI/244 */ + RCC_Clocks->CECCLK_Frequency = HSI_VALUE / 244; + } + else + { + /* CECC Clock is LSE Osc. */ + RCC_Clocks->CECCLK_Frequency = LSE_VALUE; + } + + /* I2C1CLK clock frequency */ + if((RCC->CFGR3 & RCC_CFGR3_I2C1SW) != RCC_CFGR3_I2C1SW) + { + /* I2C1 Clock is HSI Osc. */ + RCC_Clocks->I2C1CLK_Frequency = HSI_VALUE; + } + else + { + /* I2C1 Clock is System Clock */ + RCC_Clocks->I2C1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency; + } + + /* USART1CLK clock frequency */ + if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == 0x0) + { + /* USART1 Clock is PCLK */ + RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->PCLK_Frequency; + } + else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_0) + { + /* USART1 Clock is System Clock */ + RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency; + } + else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_1) + { + /* USART1 Clock is LSE Osc. */ + RCC_Clocks->USART1CLK_Frequency = LSE_VALUE; + } + else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW) + { + /* USART1 Clock is HSI Osc. */ + RCC_Clocks->USART1CLK_Frequency = HSI_VALUE; + } + + /* USART2CLK clock frequency */ + if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == 0x0) + { + /* USART Clock is PCLK */ + RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->PCLK_Frequency; + } + else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_0) + { + /* USART Clock is System Clock */ + RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->SYSCLK_Frequency; + } + else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_1) + { + /* USART Clock is LSE Osc. */ + RCC_Clocks->USART2CLK_Frequency = LSE_VALUE; + } + else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW) + { + /* USART Clock is HSI Osc. */ + RCC_Clocks->USART2CLK_Frequency = HSI_VALUE; + } + + /* USART3CLK clock frequency */ + if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == 0x0) + { + /* USART Clock is PCLK */ + RCC_Clocks->USART3CLK_Frequency = RCC_Clocks->PCLK_Frequency; + } + else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW_0) + { + /* USART Clock is System Clock */ + RCC_Clocks->USART3CLK_Frequency = RCC_Clocks->SYSCLK_Frequency; + } + else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW_1) + { + /* USART Clock is LSE Osc. */ + RCC_Clocks->USART3CLK_Frequency = LSE_VALUE; + } + else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW) + { + /* USART Clock is HSI Osc. */ + RCC_Clocks->USART3CLK_Frequency = HSI_VALUE; + } + + /* USBCLK clock frequency */ + if((RCC->CFGR3 & RCC_CFGR3_USBSW) != RCC_CFGR3_USBSW) + { + /* USB Clock is HSI48 */ + RCC_Clocks->USBCLK_Frequency = HSI48_VALUE; + } + else + { + /* USB Clock is PLL clock */ + RCC_Clocks->USBCLK_Frequency = pllclk; + } +} + +/** + * @} + */ + +/** @defgroup RCC_Group3 Peripheral clocks configuration functions + * @brief Peripheral clocks configuration functions + * +@verbatim + =============================================================================== + #####Peripheral clocks configuration functions ##### + =============================================================================== + + [..] This section provide functions allowing to configure the Peripheral clocks. + (#) The RTC clock which is derived from the LSE, LSI or HSE_Div32 (HSE + divided by 32). + (#) After restart from Reset or wakeup from STANDBY, all peripherals are off + except internal SRAM, Flash and SWD. Before to start using a peripheral you + have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd(), + RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions. + (#) To reset the peripherals configuration (to the default state after device reset) + you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and + RCC_APB1PeriphResetCmd() functions. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using PWR_BackupAccessCmd(ENABLE) function before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it can't be changed unless the RTC + * is reset using RCC_BackupResetCmd function, or by a Power On Reset (POR) + * + * @param RCC_RTCCLKSource: specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock + * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock + * @arg RCC_RTCCLKSource_HSE_Div32: HSE divided by 32 selected as RTC clock + * + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * + * @note The maximum input clock frequency for RTC is 2MHz (when using HSE as + * RTC clock source). + * + * @retval None + */ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); + + /* Select the RTC clock source */ + RCC->BDCR |= RCC_RTCCLKSource; +} + +/** + * @brief Enables or disables the RTC clock. + * @note This function must be used only after the RTC clock source was selected + * using the RCC_RTCCLKConfig function. + * @param NewState: new state of the RTC clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->BDCR |= RCC_BDCR_RTCEN; + } + else + { + RCC->BDCR &= ~RCC_BDCR_RTCEN; + } +} + +/** + * @brief Forces or releases the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_BDCR register. + * @param NewState: new state of the Backup domain reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_BackupResetCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->BDCR |= RCC_BDCR_BDRST; + } + else + { + RCC->BDCR &= ~RCC_BDCR_BDRST; + } +} + +/** + * @brief Enables or disables the AHB peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_AHBPeriph_GPIOA: GPIOA clock + * @arg RCC_AHBPeriph_GPIOB: GPIOB clock + * @arg RCC_AHBPeriph_GPIOC: GPIOC clock + * @arg RCC_AHBPeriph_GPIOD: GPIOD clock + * @arg RCC_AHBPeriph_GPIOE: GPIOE clock, applicable only for STM32F072 devices + * @arg RCC_AHBPeriph_GPIOF: GPIOF clock + * @arg RCC_AHBPeriph_TS: TS clock + * @arg RCC_AHBPeriph_CRC: CRC clock + * @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode) + * @arg RCC_AHBPeriph_SRAM: SRAM clock + * @arg RCC_AHBPeriph_DMA1: DMA1 clock + * @arg RCC_AHBPeriph_DMA2: DMA2 clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHBENR |= RCC_AHBPeriph; + } + else + { + RCC->AHBENR &= ~RCC_AHBPeriph; + } +} + +/** + * @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock + * @arg RCC_APB2Periph_USART6: USART6 clock + * @arg RCC_APB2Periph_USART7: USART7 clock + * @arg RCC_APB2Periph_USART8: USART8 clock + * @arg RCC_APB2Periph_ADC1: ADC1 clock + * @arg RCC_APB2Periph_TIM1: TIM1 clock + * @arg RCC_APB2Periph_SPI1: SPI1 clock + * @arg RCC_APB2Periph_USART1: USART1 clock + * @arg RCC_APB2Periph_TIM15: TIM15 clock + * @arg RCC_APB2Periph_TIM16: TIM16 clock + * @arg RCC_APB2Periph_TIM17: TIM17 clock + * @arg RCC_APB2Periph_DBGMCU: DBGMCU clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB2ENR |= RCC_APB2Periph; + } + else + { + RCC->APB2ENR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2: TIM2 clock, applicable only for STM32F051 and STM32F072 devices + * @arg RCC_APB1Periph_TIM3: TIM3 clock + * @arg RCC_APB1Periph_TIM6: TIM6 clock + * @arg RCC_APB1Periph_TIM7: TIM7 clock, applicable only for STM32F072 devices + * @arg RCC_APB1Periph_TIM14: TIM14 clock + * @arg RCC_APB1Periph_WWDG: WWDG clock + * @arg RCC_APB1Periph_SPI2: SPI2 clock + * @arg RCC_APB1Periph_USART2: USART2 clock + * @arg RCC_APB1Periph_USART3: USART3 clock, applicable only for STM32F072 and STM32F091 devices + * @arg RCC_APB1Periph_USART4: USART4 clock, applicable only for STM32F072 and STM32F091 devices + * @arg RCC_APB1Periph_USART5: USART5 clock, applicable only for STM32F091 devices + * @arg RCC_APB1Periph_I2C1: I2C1 clock + * @arg RCC_APB1Periph_I2C2: I2C2 clock + * @arg RCC_APB1Periph_USB: USB clock, applicable only for STM32F042 and STM32F072 devices + * @arg RCC_APB1Periph_CAN: CAN clock, applicable only for STM32F042 and STM32F072 devices + * @arg RCC_APB1Periph_CRS: CRS clock , applicable only for STM32F042 and STM32F072 devices + * @arg RCC_APB1Periph_PWR: PWR clock + * @arg RCC_APB1Periph_DAC: DAC clock, applicable only for STM32F051 and STM32F072 devices + * @arg RCC_APB1Periph_CEC: CEC clock, applicable only for STM32F051, STM32F042 and STM32F072 devices + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB1ENR |= RCC_APB1Periph; + } + else + { + RCC->APB1ENR &= ~RCC_APB1Periph; + } +} + +/** + * @brief Forces or releases AHB peripheral reset. + * @param RCC_AHBPeriph: specifies the AHB peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_AHBPeriph_GPIOA: GPIOA clock + * @arg RCC_AHBPeriph_GPIOB: GPIOB clock + * @arg RCC_AHBPeriph_GPIOC: GPIOC clock + * @arg RCC_AHBPeriph_GPIOD: GPIOD clock + * @arg RCC_AHBPeriph_GPIOE: GPIOE clock, applicable only for STM32F072 devices + * @arg RCC_AHBPeriph_GPIOF: GPIOF clock + * @arg RCC_AHBPeriph_TS: TS clock + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_RST_PERIPH(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHBRSTR |= RCC_AHBPeriph; + } + else + { + RCC->AHBRSTR &= ~RCC_AHBPeriph; + } +} + +/** + * @brief Forces or releases High Speed APB (APB2) peripheral reset. + * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock + * @arg RCC_APB2Periph_USART6: USART6 clock + * @arg RCC_APB2Periph_USART7: USART7 clock + * @arg RCC_APB2Periph_USART8: USART8 clock + * @arg RCC_APB2Periph_ADC1: ADC1 clock + * @arg RCC_APB2Periph_TIM1: TIM1 clock + * @arg RCC_APB2Periph_SPI1: SPI1 clock + * @arg RCC_APB2Periph_USART1: USART1 clock + * @arg RCC_APB2Periph_TIM15: TIM15 clock + * @arg RCC_APB2Periph_TIM16: TIM16 clock + * @arg RCC_APB2Periph_TIM17: TIM17 clock + * @arg RCC_APB2Periph_DBGMCU: DBGMCU clock + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB2RSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2RSTR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Forces or releases Low Speed APB (APB1) peripheral reset. + * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2: TIM2 clock, applicable only for STM32F051 and STM32F072 devices + * @arg RCC_APB1Periph_TIM3: TIM3 clock + * @arg RCC_APB1Periph_TIM6: TIM6 clock + * @arg RCC_APB1Periph_TIM7: TIM7 clock, applicable only for STM32F072 devices + * @arg RCC_APB1Periph_TIM14: TIM14 clock + * @arg RCC_APB1Periph_WWDG: WWDG clock + * @arg RCC_APB1Periph_SPI2: SPI2 clock + * @arg RCC_APB1Periph_USART2: USART2 clock + * @arg RCC_APB1Periph_USART3: USART3 clock, applicable only for STM32F072 and STM32F091 devices + * @arg RCC_APB1Periph_USART4: USART4 clock, applicable only for STM32F072 and STM32F091 devices + * @arg RCC_APB1Periph_USART5: USART5 clock, applicable only for STM32F091 devices + * @arg RCC_APB1Periph_I2C1: I2C1 clock + * @arg RCC_APB1Periph_I2C2: I2C2 clock + * @arg RCC_APB1Periph_USB: USB clock, applicable only for STM32F042 and STM32F072 devices + * @arg RCC_APB1Periph_CAN: CAN clock, applicable only for STM32F042 and STM32F072 devices + * @arg RCC_APB1Periph_CRS: CRS clock , applicable only for STM32F042 and STM32F072 devices + * @arg RCC_APB1Periph_PWR: PWR clock + * @arg RCC_APB1Periph_DAC: DAC clock, applicable only for STM32F051 and STM32F072 devices + * @arg RCC_APB1Periph_CEC: CEC clock, applicable only for STM32F051, STM32F042 and STM32F072 devices + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB1RSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1RSTR &= ~RCC_APB1Periph; + } +} + +/** + * @} + */ + +/** @defgroup RCC_Group4 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified RCC interrupts. + * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled + * and if the HSE clock fails, the CSS interrupt occurs and an NMI is + * automatically generated. The NMI will be executed indefinitely, and + * since NMI has higher priority than any other IRQ (and main program) + * the application will be stacked in the NMI ISR unless the CSS interrupt + * pending bit is cleared. + * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt + * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt, applicable only for STM32F072 devices + * @param NewState: new state of the specified RCC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_IT(RCC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Perform Byte access to RCC_CIR[13:8] bits to enable the selected interrupts */ + *(__IO uint8_t *) CIR_BYTE1_ADDRESS |= RCC_IT; + } + else + { + /* Perform Byte access to RCC_CIR[13:8] bits to disable the selected interrupts */ + *(__IO uint8_t *) CIR_BYTE1_ADDRESS &= (uint8_t)~RCC_IT; + } +} + +/** + * @brief Checks whether the specified RCC flag is set or not. + * @param RCC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCC_FLAG_PLLRDY: PLL clock ready + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset + * @arg RCC_FLAG_PINRST: Pin reset + * @arg RCC_FLAG_V18PWRRSTF: V1.8 power domain reset + * @arg RCC_FLAG_PORRST: POR/PDR reset + * @arg RCC_FLAG_SFTRST: Software reset + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset + * @arg RCC_FLAG_LPWRRST: Low Power reset + * @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready + * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready, applicable only for STM32F072 devices + * @retval The new state of RCC_FLAG (SET or RESET). + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_FLAG(RCC_FLAG)); + + /* Get the RCC register index */ + tmp = RCC_FLAG >> 5; + + if (tmp == 0) /* The flag to check is in CR register */ + { + statusreg = RCC->CR; + } + else if (tmp == 1) /* The flag to check is in BDCR register */ + { + statusreg = RCC->BDCR; + } + else if (tmp == 2) /* The flag to check is in CSR register */ + { + statusreg = RCC->CSR; + } + else /* The flag to check is in CR2 register */ + { + statusreg = RCC->CR2; + } + + /* Get the flag position */ + tmp = RCC_FLAG & FLAG_MASK; + + if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the RCC reset flags. + * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_V18PWRRSTF, + * RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, + * RCC_FLAG_LPWRRST. + * @param None + * @retval None + */ +void RCC_ClearFlag(void) +{ + /* Set RMVF bit to clear the reset flags */ + RCC->CSR |= RCC_CSR_RMVF; +} + +/** + * @brief Checks whether the specified RCC interrupt has occurred or not. + * @param RCC_IT: specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt + * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt, applicable only for STM32F072 devices + * @arg RCC_IT_CSS: Clock Security System interrupt + * @retval The new state of RCC_IT (SET or RESET). + */ +ITStatus RCC_GetITStatus(uint8_t RCC_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_GET_IT(RCC_IT)); + + /* Check the status of the specified RCC interrupt */ + if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the RCC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the RCC's interrupt pending bits. + * @param RCC_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt, applicable only for STM32F072 devices + * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * @retval None + */ +void RCC_ClearITPendingBit(uint8_t RCC_IT) +{ + /* Check the parameters */ + assert_param(IS_RCC_CLEAR_IT(RCC_IT)); + + /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt + pending bits */ + *(__IO uint8_t *) CIR_BYTE2_ADDRESS = RCC_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_rtc.c b/system/src/stm32f0-stdperiph/stm32f0xx_rtc.c new file mode 100644 index 0000000..1ca2c91 --- /dev/null +++ b/system/src/stm32f0-stdperiph/stm32f0xx_rtc.c @@ -0,0 +1,2518 @@ +/** + ****************************************************************************** + * @file stm32f0xx_rtc.c + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Real-Time Clock (RTC) peripheral: + * + Initialization + * + Calendar (Time and Date) configuration + * + Alarms (Alarm A) configuration + * + Daylight Saving configuration + * + Output pin Configuration + * + Digital Calibration configuration + * + TimeStamp configuration + * + Tampers configuration + * + Backup Data Registers configuration + * + Output Type Config configuration + * + Shift control synchronisation + * + Interrupts and flags management + * + @verbatim + =============================================================================== + ##### Backup Domain Operating Condition ##### + =============================================================================== + [..] The real-time clock (RTC) and the RTC backup registers can be powered + from the VBAT voltage when the main VDD supply is powered off. + To retain the content of the RTC backup registers and supply the RTC + when VDD is turned off, VBAT pin can be connected to an optional + standby voltage supplied by a battery or by another source. + + [..] To allow the RTC to operate even when the main digital supply (VDD) + is turned off, the VBAT pin powers the following blocks: + (#) The RTC + (#) The LSE oscillator + (#) PC13 to PC15 I/Os I/Os (when available) + + [..] When the backup domain is supplied by VDD (analog switch connected + to VDD), the following functions are available: + (#) PC14 and PC15 can be used as either GPIO or LSE pins + (#) PC13 can be used as a GPIO or as the RTC_AF1 pin + + [..] When the backup domain is supplied by VBAT (analog switch connected + to VBAT because VDD is not present), the following functions are available: + (#) PC14 and PC15 can be used as LSE pins only + (#) PC13 can be used as the RTC_AF1 pin + + ##### Backup Domain Reset ##### + =============================================================================== + [..] The backup domain reset sets all RTC registers and the RCC_BDCR + register to their reset values. + A backup domain reset is generated when one of the following events + occurs: + (#) Software reset, triggered by setting the BDRST bit in the + RCC Backup domain control register (RCC_BDCR). You can use the + RCC_BackupResetCmd(). + (#) VDD or VBAT power on, if both supplies have previously been + powered off. + + ##### Backup Domain Access ##### + =============================================================================== + [..] After reset, the backup domain (RTC registers and RTC backup data + registers) is protected against possible unwanted write accesses. + [..] To enable access to the Backup Domain and RTC registers, proceed as follows: + (#) Enable the Power Controller (PWR) APB1 interface clock using the + RCC_APB1PeriphClockCmd() function. + (#) Enable access to Backup domain using the PWR_BackupAccessCmd() function. + (#) Select the RTC clock source using the RCC_RTCCLKConfig() function. + (#) Enable RTC Clock using the RCC_RTCCLKCmd() function. + + + ##### How to use this driver ##### + =============================================================================== + [..] + (+) Enable the backup domain access (see description in the section above) + (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and + RTC hour format using the RTC_Init() function. + + ***Time and Date configuration *** + ================================== + [..] + (+) To configure the RTC Calendar (Time and Date) use the RTC_SetTime() + and RTC_SetDate() functions. + (+) To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate() + functions. + (+) To read the RTC subsecond, use the RTC_GetSubSecond() function. + (+) Use the RTC_DayLightSavingConfig() function to add or sub one + hour to the RTC Calendar. + + ***Alarm configuration *** + ========================== + [..] + (+) To configure the RTC Alarm use the RTC_SetAlarm() function. + (+) Enable the selected RTC Alarm using the RTC_AlarmCmd() function + (+) To read the RTC Alarm, use the RTC_GetAlarm() function. + (+) To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function. + + ***RTC Wakeup configuration*** + ========================== + [..] + (+) Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig() + function. + (+) Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() + function + (+) Enable the RTC WakeUp using the RTC_WakeUpCmd() function + (+) To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter() + function. + + ***Outputs configuration *** + ============================ + [..] The RTC has 2 different outputs: + (+) AFO_ALARM: this output is used to manage the RTC Alarm A. + To output the selected RTC signal on RTC_AF1 pin, use the + RTC_OutputConfig() function. + (+) AFO_CALIB: this output is 512Hz signal or 1Hz . + To output the RTC Clock on RTC_AF1 pin, use the RTC_CalibOutputCmd() + function. + + ***Original Digital Calibration configuration *** + ================================= + [..] Configure the RTC Original Digital Calibration Value and the corresponding + calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig() + function. + + ***TimeStamp configuration *** + ============================== + [..] + (+) Configure the RTC_AF1 trigger and enables the RTC TimeStamp + using the RTC_TimeStampCmd() function. + (+) To read the RTC TimeStamp Time and Date register, use the + RTC_GetTimeStamp() function. + (+) To read the RTC TimeStamp SubSecond register, use the + RTC_GetTimeStampSubSecond() function. + + ***Tamper configuration *** + =========================== + [..] + (+) Configure the Tamper filter count using RTC_TamperFilterConfig() + function. + (+) Configure the RTC Tamper trigger Edge or Level according to the Tamper + filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig() function + (+) Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig() + function. + (+) Configure the Tamper precharge or discharge duration using + RTC_TamperPinsPrechargeDuration() function. + (+) Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function. + (+) Enable the RTC Tamper using the RTC_TamperCmd() function. + (+) Enable the Time stamp on Tamper detection event using + RTC_TSOnTamperDetecCmd() function. + + ***Backup Data Registers configuration *** + ========================================== + [..] + (+) To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister() + function. + (+) To read the RTC Backup Data registers, use the RTC_ReadBackupRegister() + function. + + ##### RTC and low power modes ##### + =============================================================================== + [..] The MCU can be woken up from a low power mode by an RTC alternate + function. + [..] The RTC alternate functions are the RTC alarm (Alarm A), RTC tamper + event detection and RTC time stamp event detection. + These RTC alternate functions can wake up the system from the Stop + and Standby lowpower modes. + The system can also wake up from low power modes without depending + on an external interrupt (Auto-wakeup mode), by using the RTC alarm events. + [..] The RTC provides a programmable time base for waking up from the + Stop or Standby mode at regular intervals. + Wakeup from STOP and Standby modes is possible only when the RTC + clock source is LSE or LSI. + + ##### Selection of RTC_AF1 alternate functions ##### + =============================================================================== + [..] The RTC_AF1 pin (PC13) can be used for the following purposes: + (+) AFO_ALARM output + (+) AFO_CALIB output + (+) AFI_TAMPER + (+) AFI_TIMESTAMP + + +------------------------------------------------------------------------------------------+ + | Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | WKUP2 |ALARMOUTTYPE | + | configuration | ENABLED | ENABLED | ENABLED | ENABLED |ENABLED | AFO_ALARM | + | and function | | | | | |Configuration | + |-----------------|----------|----------|-----------|--------------|--------|--------------| + | Alarm out | | | | | Don't | | + | output OD | 1 | 0 |Don't care | Don't care | care | 0 | + |-----------------|----------|----------|-----------|--------------|--------|--------------| + | Alarm out | | | | | Don't | | + | output PP | 1 | 0 |Don't care | Don't care | care | 1 | + |-----------------|----------|----------|-----------|--------------|--------|--------------| + | Calibration out | | | | | Don't | | + | output PP | 0 | 1 |Don't care | Don't care | care | Don't care | + |-----------------|----------|----------|-----------|--------------|--------|--------------| + | TAMPER input | | | | | Don't | | + | floating | 0 | 0 | 1 | 0 | care | Don't care | + |-----------------|----------|----------|-----------|--------------|--------|--------------| + | TIMESTAMP and | | | | | Don't | | + | TAMPER input | 0 | 0 | 1 | 1 | care | Don't care | + | floating | | | | | | | + |-----------------|----------|----------|-----------|--------------|--------|--------------| + | TIMESTAMP input | | | | | Don't | | + | floating | 0 | 0 | 0 | 1 | care | Don't care | + |-----------------|----------|----------|-----------|--------------|--------|--------------| + | Wakeup Pin 2 | 0 | 0 | 0 | 0 | 1 | Don't care | + |-----------------|----------|----------|-----------|--------------|--------|--------------| + | Standard GPIO | 0 | 0 | 0 | 0 | 0 | Don't care | + +------------------------------------------------------------------------------------------+ + + @endverbatim + + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_rtc.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup RTC + * @brief RTC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* Masks Definition */ +#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) +#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) +#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) +#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F) +#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_ALRAF | \ + RTC_FLAG_RSF | RTC_FLAG_INITS |RTC_FLAG_INITF | \ + RTC_FLAG_TAMP1F | RTC_FLAG_TAMP2F | RTC_FLAG_RECALPF | \ + RTC_FLAG_SHPF)) + +#define INITMODE_TIMEOUT ((uint32_t) 0x00004000) +#define SYNCHRO_TIMEOUT ((uint32_t) 0x00008000) +#define RECALPF_TIMEOUT ((uint32_t) 0x00001000) +#define SHPF_TIMEOUT ((uint32_t) 0x00001000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static uint8_t RTC_ByteToBcd2(uint8_t Value); +static uint8_t RTC_Bcd2ToByte(uint8_t Value); + +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RTC_Private_Functions + * @{ + */ + +/** @defgroup RTC_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + + [..] This section provide functions allowing to initialize and configure the RTC + Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers + Write protection, enter and exit the RTC initialization mode, RTC registers + synchronization check and reference clock detection enable. + + (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. + It is split into 2 programmable prescalers to minimize power consumption. + (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler. + (++) When both prescalers are used, it is recommended to configure the + asynchronous prescaler to a high value to minimize consumption. + (#) All RTC registers are Write protected. Writing to the RTC registers + is enabled by writing a key into the Write Protection register, RTC_WPR. + (#) To Configure the RTC Calendar, user application should enter + initialization mode. In this mode, the calendar counter is stopped + and its value can be updated. When the initialization sequence is + complete, the calendar restarts counting after 4 RTCCLK cycles. + (#) To read the calendar through the shadow registers after Calendar + initialization, calendar update or after wakeup from low power modes + the software must first clear the RSF flag. The software must then + wait until it is set again before reading the calendar, which means + that the calendar registers have been correctly copied into the + RTC_TR and RTC_DR shadow registers.The RTC_WaitForSynchro() function + implements the above software sequence (RSF clear and RSF check). + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the RTC registers to their default reset values. + * @note This function doesn't reset the RTC Clock source and RTC Backup Data + * registers. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are deinitialized + * - ERROR: RTC registers are not deinitialized + */ +ErrorStatus RTC_DeInit(void) +{ + ErrorStatus status = ERROR; + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Reset TR, DR and CR registers */ + RTC->TR = (uint32_t)0x00000000; + RTC->WUTR = (uint32_t)0x0000FFFF; + RTC->DR = (uint32_t)0x00002101; + RTC->CR &= (uint32_t)0x00000000; + RTC->PRER = (uint32_t)0x007F00FF; + RTC->ALRMAR = (uint32_t)0x00000000; + RTC->SHIFTR = (uint32_t)0x00000000; + RTC->CALR = (uint32_t)0x00000000; + RTC->ALRMASSR = (uint32_t)0x00000000; + + /* Reset ISR register and exit initialization mode */ + RTC->ISR = (uint32_t)0x00000000; + + /* Reset Tamper and alternate functions configuration register */ + RTC->TAFCR = 0x00000000; + + /* Wait till the RTC RSF flag is set */ + if (RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Initializes the RTC registers according to the specified parameters + * in RTC_InitStruct. + * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains + * the configuration information for the RTC peripheral. + * @note The RTC Prescaler register is write protected and can be written in + * initialization mode only. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are initialized + * - ERROR: RTC registers are not initialized + */ +ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat)); + assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv)); + assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Clear RTC CR FMT Bit */ + RTC->CR &= ((uint32_t)~(RTC_CR_FMT)); + /* Set RTC_CR register */ + RTC->CR |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat)); + + /* Configure the RTC PRER */ + RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv); + RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16); + + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + status = SUCCESS; + } + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Fills each RTC_InitStruct member with its default value. + * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be + * initialized. + * @retval None + */ +void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct) +{ + /* Initialize the RTC_HourFormat member */ + RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24; + + /* Initialize the RTC_AsynchPrediv member */ + RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F; + + /* Initialize the RTC_SynchPrediv member */ + RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; +} + +/** + * @brief Enables or disables the RTC registers write protection. + * @note All the RTC registers are write protected except for RTC_ISR[13:8], + * RTC_TAFCR and RTC_BKPxR. + * @note Writing a wrong key reactivates the write protection. + * @note The protection mechanism is not affected by system reset. + * @param NewState: new state of the write protection. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_WriteProtectionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + } + else + { + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + } +} + +/** + * @brief Enters the RTC Initialization mode. + * @note The RTC Initialization mode is write protected, use the + * RTC_WriteProtectionCmd(DISABLE) before calling this function. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC is in Init mode + * - ERROR: RTC is not in Init mode + */ +ErrorStatus RTC_EnterInitMode(void) +{ + __IO uint32_t initcounter = 0x00; + ErrorStatus status = ERROR; + uint32_t initstatus = 0x00; + + /* Check if the Initialization mode is set */ + if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET) + { + /* Set the Initialization mode */ + RTC->ISR = (uint32_t)RTC_INIT_MASK; + + /* Wait till RTC is in INIT state and if Time out is reached exit */ + do + { + initstatus = RTC->ISR & RTC_ISR_INITF; + initcounter++; + } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00)); + + if ((RTC->ISR & RTC_ISR_INITF) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + } + else + { + status = SUCCESS; + } + + return (status); +} + +/** + * @brief Exits the RTC Initialization mode. + * @note When the initialization sequence is complete, the calendar restarts + * counting after 4 RTCCLK cycles. + * @note The RTC Initialization mode is write protected, use the + * RTC_WriteProtectionCmd(DISABLE) before calling this function. + * @param None + * @retval None + */ +void RTC_ExitInitMode(void) +{ + /* Exit Initialization mode */ + RTC->ISR &= (uint32_t)~RTC_ISR_INIT; +} + +/** + * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are + * synchronized with RTC APB clock. + * @note The RTC Resynchronization mode is write protected, use the + * RTC_WriteProtectionCmd(DISABLE) before calling this function. + * @note To read the calendar through the shadow registers after Calendar + * initialization, calendar update or after wakeup from low power modes + * the software must first clear the RSF flag. + * The software must then wait until it is set again before reading + * the calendar, which means that the calendar registers have been + * correctly copied into the RTC_TR and RTC_DR shadow registers. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are synchronised + * - ERROR: RTC registers are not synchronised + */ +ErrorStatus RTC_WaitForSynchro(void) +{ + __IO uint32_t synchrocounter = 0; + ErrorStatus status = ERROR; + uint32_t synchrostatus = 0x00; + + if ((RTC->CR & RTC_CR_BYPSHAD) != RESET) + { + /* Bypass shadow mode */ + status = SUCCESS; + } + else + { + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Clear RSF flag */ + RTC->ISR &= (uint32_t)RTC_RSF_MASK; + + /* Wait the registers to be synchronised */ + do + { + synchrostatus = RTC->ISR & RTC_ISR_RSF; + synchrocounter++; + } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00)); + + if ((RTC->ISR & RTC_ISR_RSF) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + } + + return (status); +} + +/** + * @brief Enables or disables the RTC reference clock detection. + * @param NewState: new state of the RTC reference clock. + * This parameter can be: ENABLE or DISABLE. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC reference clock detection is enabled + * - ERROR: RTC reference clock detection is disabled + */ +ErrorStatus RTC_RefClockCmd(FunctionalState NewState) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + if (NewState != DISABLE) + { + /* Enable the RTC reference clock detection */ + RTC->CR |= RTC_CR_REFCKON; + } + else + { + /* Disable the RTC reference clock detection */ + RTC->CR &= ~RTC_CR_REFCKON; + } + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + status = SUCCESS; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Enables or Disables the Bypass Shadow feature. + * @note When the Bypass Shadow is enabled the calendar value are taken + * directly from the Calendar counter. + * @param NewState: new state of the Bypass Shadow feature. + * This parameter can be: ENABLE or DISABLE. + * @retval None +*/ +void RTC_BypassShadowCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + if (NewState != DISABLE) + { + /* Set the BYPSHAD bit */ + RTC->CR |= (uint8_t)RTC_CR_BYPSHAD; + } + else + { + /* Reset the BYPSHAD bit */ + RTC->CR &= (uint8_t)~RTC_CR_BYPSHAD; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @} + */ + +/** @defgroup RTC_Group2 Time and Date configuration functions + * @brief Time and Date configuration functions + * +@verbatim + =============================================================================== + ##### Time and Date configuration functions ##### + =============================================================================== + [..] This section provide functions allowing to program and read the RTC + Calendar (Time and Date). + +@endverbatim + * @{ + */ + +/** + * @brief Set the RTC current time. + * @param RTC_Format: specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains + * the time configuration information for the RTC. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Time register is configured + * - ERROR: RTC Time register is not configured + */ +ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) +{ + uint32_t tmpreg = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + if (RTC_Format == RTC_Format_BIN) + { + if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours)); + assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); + } + else + { + RTC_TimeStruct->RTC_H12 = 0x00; + assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours)); + } + assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes)); + assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds)); + } + else + { + if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); + assert_param(IS_RTC_HOUR12(tmpreg)); + assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); + } + else + { + RTC_TimeStruct->RTC_H12 = 0x00; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours))); + } + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds))); + } + + /* Check the input parameters format */ + if (RTC_Format != RTC_Format_BIN) + { + tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \ + ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \ + ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \ + ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16)); + } + else + { + tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \ + (((uint32_t)RTC_TimeStruct->RTC_H12) << 16)); + } + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Set the RTC_TR register */ + RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); + + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if ((RTC->CR & RTC_CR_BYPSHAD) == RESET) + { + if (RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + else + { + status = SUCCESS; + } + + } + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Fills each RTC_TimeStruct member with its default value + * (Time = 00h:00min:00sec). + * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be + * initialized. + * @retval None + */ +void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct) +{ + /* Time = 00h:00min:00sec */ + RTC_TimeStruct->RTC_H12 = RTC_H12_AM; + RTC_TimeStruct->RTC_Hours = 0; + RTC_TimeStruct->RTC_Minutes = 0; + RTC_TimeStruct->RTC_Seconds = 0; +} + +/** + * @brief Get the RTC current Time. + * @param RTC_Format: specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will + * contain the returned current time configuration. + * @retval None + */ +void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + /* Get the RTC_TR register */ + tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16); + RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8); + RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); + RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); + + /* Check the input parameters format */ + if (RTC_Format == RTC_Format_BIN) + { + /* Convert the structure parameters to Binary format */ + RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); + RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes); + RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds); + } +} + +/** + * @brief Gets the RTC current Calendar Subseconds value. + * @note This function freeze the Time and Date registers after reading the + * SSR register. + * @param None + * @retval RTC current Calendar Subseconds value. + */ +uint32_t RTC_GetSubSecond(void) +{ + uint32_t tmpreg = 0; + + /* Get subseconds values from the correspondent registers*/ + tmpreg = (uint32_t)(RTC->SSR); + + /* Read DR register to unfroze calendar registers */ + (void) (RTC->DR); + + return (tmpreg); +} + +/** + * @brief Set the RTC current date. + * @param RTC_Format: specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains + * the date configuration information for the RTC. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Date register is configured + * - ERROR: RTC Date register is not configured + */ +ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) +{ + uint32_t tmpreg = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10)) + { + RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A; + } + if (RTC_Format == RTC_Format_BIN) + { + assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year)); + assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month)); + assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date)); + } + else + { + assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year))); + tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); + assert_param(IS_RTC_MONTH(tmpreg)); + tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); + assert_param(IS_RTC_DATE(tmpreg)); + } + assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay)); + + /* Check the input parameters format */ + if (RTC_Format != RTC_Format_BIN) + { + tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \ + (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \ + ((uint32_t)RTC_DateStruct->RTC_Date) | \ + (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); + } + else + { + tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \ + ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13)); + } + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Set the RTC_DR register */ + RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK); + + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if ((RTC->CR & RTC_CR_BYPSHAD) == RESET) + { + if (RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + else + { + status = SUCCESS; + } + } + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Fills each RTC_DateStruct member with its default value + * (Monday, January 01 xx00). + * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be + * initialized. + * @retval None + */ +void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct) +{ + /* Monday, January 01 xx00 */ + RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday; + RTC_DateStruct->RTC_Date = 1; + RTC_DateStruct->RTC_Month = RTC_Month_January; + RTC_DateStruct->RTC_Year = 0; +} + +/** + * @brief Get the RTC current date. + * @param RTC_Format: specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will + * contain the returned current date configuration. + * @retval None + */ +void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + /* Get the RTC_TR register */ + tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16); + RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8); + RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU)); + RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13); + + /* Check the input parameters format */ + if (RTC_Format == RTC_Format_BIN) + { + /* Convert the structure parameters to Binary format */ + RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year); + RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); + RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); + RTC_DateStruct->RTC_WeekDay = (uint8_t)(RTC_DateStruct->RTC_WeekDay); + } +} + +/** + * @} + */ + +/** @defgroup RTC_Group3 Alarms configuration functions + * @brief Alarms (Alarm A) configuration functions + * +@verbatim + =============================================================================== + ##### Alarms (Alarm A and Alarm B) configuration functions ##### + =============================================================================== + [..] This section provide functions allowing to program and read the RTC + Alarms. + +@endverbatim + * @{ + */ + +/** + * @brief Set the specified RTC Alarm. + * @note The Alarm register can only be written when the corresponding Alarm + * is disabled (Use the RTC_AlarmCmd(DISABLE)). + * @param RTC_Format: specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_Alarm: specifies the alarm to be configured. + * This parameter can be one of the following values: + * @arg RTC_Alarm_A: to select Alarm A + * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that + * contains the alarm configuration parameters. + * @retval None + */ +void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + assert_param(IS_RTC_ALARM(RTC_Alarm)); + assert_param(IS_RTC_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask)); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel)); + + if (RTC_Format == RTC_Format_BIN) + { + if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); + assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); + } + else + { + RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; + assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); + } + assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)); + assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)); + + if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); + } + } + else + { + if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours); + assert_param(IS_RTC_HOUR12(tmpreg)); + assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); + } + else + { + RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours))); + } + + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds))); + + if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) + { + tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); + } + else + { + tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); + } + } + + /* Check the input parameters format */ + if (RTC_Format != RTC_Format_BIN) + { + tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ + ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ + ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \ + ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ + ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ + ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ + ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); + } + else + { + tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \ + ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ + ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ + ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); + } + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Configure the Alarm register */ + RTC->ALRMAR = (uint32_t)tmpreg; + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Fills each RTC_AlarmStruct member with its default value + * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = + * all fields are masked). + * @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which + * will be initialized. + * @retval None + */ +void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct) +{ + /* Alarm Time Settings : Time = 00h:00mn:00sec */ + RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM; + RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0; + RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0; + RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0; + + /* Alarm Date Settings : Date = 1st day of the month */ + RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date; + RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1; + + /* Alarm Masks Settings : Mask = all fields are not masked */ + RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None; +} + +/** + * @brief Get the RTC Alarm value and masks. + * @param RTC_Format: specifies the format of the output parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_Alarm: specifies the alarm to be read. + * This parameter can be one of the following values: + * @arg RTC_Alarm_A: to select Alarm A + * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will + * contains the output alarm configuration values. + * @retval None + */ +void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + assert_param(IS_RTC_ALARM(RTC_Alarm)); + + /* Get the RTC_ALRMAR register */ + tmpreg = (uint32_t)(RTC->ALRMAR); + + /* Fill the structure with the read parameters */ + RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \ + RTC_ALRMAR_HU)) >> 16); + RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \ + RTC_ALRMAR_MNU)) >> 8); + RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \ + RTC_ALRMAR_SU)); + RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16); + RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); + RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); + RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All); + + if (RTC_Format == RTC_Format_BIN) + { + RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ + RTC_AlarmTime.RTC_Hours); + RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ + RTC_AlarmTime.RTC_Minutes); + RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ + RTC_AlarmTime.RTC_Seconds); + RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); + } +} + +/** + * @brief Enables or disables the specified RTC Alarm. + * @param RTC_Alarm: specifies the alarm to be configured. + * This parameter can be any combination of the following values: + * @arg RTC_Alarm_A: to select Alarm A + * @param NewState: new state of the specified alarm. + * This parameter can be: ENABLE or DISABLE. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Alarm is enabled/disabled + * - ERROR: RTC Alarm is not enabled/disabled + */ +ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState) +{ + __IO uint32_t alarmcounter = 0x00; + uint32_t alarmstatus = 0x00; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_CMD_ALARM(RTC_Alarm)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Configure the Alarm state */ + if (NewState != DISABLE) + { + RTC->CR |= (uint32_t)RTC_Alarm; + + status = SUCCESS; + } + else + { + /* Disable the Alarm in RTC_CR register */ + RTC->CR &= (uint32_t)~RTC_Alarm; + + /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ + do + { + alarmstatus = RTC->ISR & (RTC_Alarm >> 8); + alarmcounter++; + } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00)); + + if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Configure the RTC AlarmA/B Subseconds value and mask. + * @note This function is performed only when the Alarm is disabled. + * @param RTC_Alarm: specifies the alarm to be configured. + * This parameter can be one of the following values: + * @arg RTC_Alarm_A: to select Alarm A + * @param RTC_AlarmSubSecondValue: specifies the Subseconds value. + * This parameter can be a value from 0 to 0x00007FFF. + * @param RTC_AlarmSubSecondMask: specifies the Subseconds Mask. + * This parameter can be any combination of the following values: + * @arg RTC_AlarmSubSecondMask_All: All Alarm SS fields are masked. + * There is no comparison on sub seconds for Alarm. + * @arg RTC_AlarmSubSecondMask_SS14_1: SS[14:1] are don't care in Alarm comparison. + * Only SS[0] is compared + * @arg RTC_AlarmSubSecondMask_SS14_2: SS[14:2] are don't care in Alarm comparison. + * Only SS[1:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_3: SS[14:3] are don't care in Alarm comparison. + * Only SS[2:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_4: SS[14:4] are don't care in Alarm comparison. + * Only SS[3:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_5: SS[14:5] are don't care in Alarm comparison. + * Only SS[4:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_6: SS[14:6] are don't care in Alarm comparison. + * Only SS[5:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_7: SS[14:7] are don't care in Alarm comparison. + * Only SS[6:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_8: SS[14:8] are don't care in Alarm comparison. + * Only SS[7:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_9: SS[14:9] are don't care in Alarm comparison. + * Only SS[8:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison. + * Only SS[9:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison. + * Only SS[10:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison. + * Only SS[11:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison. + * Only SS[12:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14: SS[14] is don't care in Alarm comparison. + * Only SS[13:0] are compared + * @arg RTC_AlarmSubSecondMask_None: SS[14:0] are compared and must match to activate alarm + * @retval None + */ +void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint8_t RTC_AlarmSubSecondMask) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_ALARM(RTC_Alarm)); + assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue)); + assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Configure the Alarm A or Alarm B SubSecond registers */ + tmpreg = (uint32_t) (((uint32_t)(RTC_AlarmSubSecondValue)) | ((uint32_t)(RTC_AlarmSubSecondMask) << 24)); + + /* Configure the AlarmA SubSecond register */ + RTC->ALRMASSR = tmpreg; + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + +} + +/** + * @brief Gets the RTC Alarm Subseconds value. + * @param RTC_Alarm: specifies the alarm to be read. + * This parameter can be one of the following values: + * @arg RTC_Alarm_A: to select Alarm A + * @param None + * @retval RTC Alarm Subseconds value. + */ +uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm) +{ + uint32_t tmpreg = 0; + + /* Get the RTC_ALRMAR register */ + tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS); + + return (tmpreg); +} + +/** + * @} + */ + +/** @defgroup RTC_Group4 WakeUp Timer configuration functions + * @brief WakeUp Timer configuration functions + * +@verbatim + =============================================================================== + ##### WakeUp Timer configuration functions ##### + =============================================================================== + + [..] This section provide functions allowing to program and read the RTC WakeUp. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the RTC Wakeup clock source. + * This function is available for STM32F072 devices. + * @note The WakeUp Clock source can only be changed when the RTC WakeUp + * is disabled (Use the RTC_WakeUpCmd(DISABLE)). + * @param RTC_WakeUpClock: Wakeup Clock source. + * This parameter can be one of the following values: + * @arg RTC_WakeUpClock_RTCCLK_Div16 + * @arg RTC_WakeUpClock_RTCCLK_Div8 + * @arg RTC_WakeUpClock_RTCCLK_Div4 + * @arg RTC_WakeUpClock_RTCCLK_Div2 + * @arg RTC_WakeUpClock_CK_SPRE_16bits + * @arg RTC_WakeUpClock_CK_SPRE_17bits + * @retval None + */ +void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock) +{ + /* Check the parameters */ + assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Clear the Wakeup Timer clock source bits in CR register */ + RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL; + + /* Configure the clock source */ + RTC->CR |= (uint32_t)RTC_WakeUpClock; + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Configures the RTC Wakeup counter. + * This function is available for STM32F072 devices. + * @note The RTC WakeUp counter can only be written when the RTC WakeUp + * is disabled (Use the RTC_WakeUpCmd(DISABLE)). + * @param RTC_WakeUpCounter: specifies the WakeUp counter. + * This parameter can be a value from 0x0000 to 0xFFFF. + * @retval None + */ +void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter) +{ + /* Check the parameters */ + assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Configure the Wakeup Timer counter */ + RTC->WUTR = (uint32_t)RTC_WakeUpCounter; + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Returns the RTC WakeUp timer counter value. + * This function is available for STM32F072 devices. + * @param None + * @retval The RTC WakeUp Counter value. + */ +uint32_t RTC_GetWakeUpCounter(void) +{ + /* Get the counter value */ + return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT)); +} + +/** + * @brief Enables or Disables the RTC WakeUp timer. + * This function is available for STM32F072 devices. + * @param NewState: new state of the WakeUp timer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +ErrorStatus RTC_WakeUpCmd(FunctionalState NewState) +{ + __IO uint32_t wutcounter = 0x00; + uint32_t wutwfstatus = 0x00; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + if (NewState != DISABLE) + { + /* Enable the Wakeup Timer */ + RTC->CR |= (uint32_t)RTC_CR_WUTE; + status = SUCCESS; + } + else + { + /* Disable the Wakeup Timer */ + RTC->CR &= (uint32_t)~RTC_CR_WUTE; + /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ + do + { + wutwfstatus = RTC->ISR & RTC_ISR_WUTWF; + wutcounter++; + } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); + + if ((RTC->ISR & RTC_ISR_WUTWF) == RESET) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @} + */ + +/** @defgroup RTC_Group5 Daylight Saving configuration functions + * @brief Daylight Saving configuration functions + * +@verbatim + =============================================================================== + ##### WakeUp Timer configuration functions ##### + =============================================================================== + [..] This section provide functions allowing to program and read the RTC WakeUp. + + This section provide functions allowing to configure the RTC DayLight Saving. + +@endverbatim + * @{ + */ + +/** + * @brief Adds or substract one hour from the current time. + * @param RTC_DayLightSaveOperation: the value of hour adjustment. + * This parameter can be one of the following values: + * @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time) + * @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time) + * @param RTC_StoreOperation: Specifies the value to be written in the BCK bit + * in CR register to store the operation. + * This parameter can be one of the following values: + * @arg RTC_StoreOperation_Reset: BCK Bit Reset + * @arg RTC_StoreOperation_Set: BCK Bit Set + * @retval None + */ +void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation) +{ + /* Check the parameters */ + assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving)); + assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Clear the bits to be configured */ + RTC->CR &= (uint32_t)~(RTC_CR_BCK); + + /* Configure the RTC_CR register */ + RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation); + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Returns the RTC Day Light Saving stored operation. + * @param None + * @retval RTC Day Light Saving stored operation. + * - RTC_StoreOperation_Reset + * - RTC_StoreOperation_Set + */ +uint32_t RTC_GetStoreOperation(void) +{ + return (RTC->CR & RTC_CR_BCK); +} + +/** + * @} + */ + +/** @defgroup RTC_Group6 Output pin Configuration function + * @brief Output pin Configuration function + * +@verbatim + =============================================================================== + ##### Output pin Configuration function ##### + =============================================================================== + [..] This section provide functions allowing to configure the RTC Output source. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the RTC output source (AFO_ALARM). + * @param RTC_Output: Specifies which signal will be routed to the RTC output. + * This parameter can be one of the following values: + * @arg RTC_Output_Disable: No output selected + * @arg RTC_Output_AlarmA: signal of AlarmA mapped to output + * @arg RTC_Output_WakeUp: signal of WakeUp mapped to output, available only for STM32F072 devices + * @param RTC_OutputPolarity: Specifies the polarity of the output signal. + * This parameter can be one of the following: + * @arg RTC_OutputPolarity_High: The output pin is high when the + * ALRAF is high (depending on OSEL) + * @arg RTC_OutputPolarity_Low: The output pin is low when the + * ALRAF is high (depending on OSEL) + * @retval None + */ +void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity) +{ + /* Check the parameters */ + assert_param(IS_RTC_OUTPUT(RTC_Output)); + assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Clear the bits to be configured */ + RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL); + + /* Configure the output selection and polarity */ + RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity); + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @} + */ + +/** @defgroup RTC_Group7 Digital Calibration configuration functions + * @brief Digital Calibration configuration functions + * +@verbatim + =============================================================================== + ##### Digital Calibration configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the RTC clock to be output through the relative pin. + * @param NewState: new state of the digital calibration Output. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_CalibOutputCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + if (NewState != DISABLE) + { + /* Enable the RTC clock output */ + RTC->CR |= (uint32_t)RTC_CR_COE; + } + else + { + /* Disable the RTC clock output */ + RTC->CR &= (uint32_t)~RTC_CR_COE; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + * @param RTC_CalibOutput: Select the Calibration output Selection . + * This parameter can be one of the following values: + * @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz. + * @arg RTC_CalibOutput_1Hz: A signal has a regular waveform at 1Hz. + * @retval None +*/ +void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput) +{ + /* Check the parameters */ + assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /*clear flags before config*/ + RTC->CR &= (uint32_t)~(RTC_CR_CALSEL); + + /* Configure the RTC_CR register */ + RTC->CR |= (uint32_t)RTC_CalibOutput; + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Configures the Smooth Calibration Settings. + * @param RTC_SmoothCalibPeriod: Select the Smooth Calibration Period. + * This parameter can be can be one of the following values: + * @arg RTC_SmoothCalibPeriod_32sec: The smooth calibration periode is 32s. + * @arg RTC_SmoothCalibPeriod_16sec: The smooth calibration periode is 16s. + * @arg RTC_SmoothCalibPeriod_8sec: The smooth calibartion periode is 8s. + * @param RTC_SmoothCalibPlusPulses: Select to Set or reset the CALP bit. + * This parameter can be one of the following values: + * @arg RTC_SmoothCalibPlusPulses_Set: Add one RTCCLK puls every 2**11 pulses. + * @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added. + * @param RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits. + * This parameter can be one any value from 0 to 0x000001FF. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Calib registers are configured + * - ERROR: RTC Calib registers are not configured +*/ +ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, + uint32_t RTC_SmoothCalibPlusPulses, + uint32_t RTC_SmouthCalibMinusPulsesValue) +{ + ErrorStatus status = ERROR; + uint32_t recalpfcount = 0; + + /* Check the parameters */ + assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod)); + assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses)); + assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* check if a calibration is pending*/ + if ((RTC->ISR & RTC_ISR_RECALPF) != RESET) + { + /* wait until the Calibration is completed*/ + while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT)) + { + recalpfcount++; + } + } + + /* check if the calibration pending is completed or if there is no calibration operation at all*/ + if ((RTC->ISR & RTC_ISR_RECALPF) == RESET) + { + /* Configure the Smooth calibration settings */ + RTC->CALR = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses | (uint32_t)RTC_SmouthCalibMinusPulsesValue); + + status = SUCCESS; + } + else + { + status = ERROR; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return (ErrorStatus)(status); +} + +/** + * @} + */ + + +/** @defgroup RTC_Group8 TimeStamp configuration functions + * @brief TimeStamp configuration functions + * +@verbatim + =============================================================================== + ##### TimeStamp configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or Disables the RTC TimeStamp functionality with the + * specified time stamp pin stimulating edge. + * @param RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is + * activated. + * This parameter can be one of the following: + * @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising + * edge of the related pin. + * @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the + * falling edge of the related pin. + * @param NewState: new state of the TimeStamp. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Get the RTC_CR register and clear the bits to be configured */ + tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); + + /* Get the new configuration */ + if (NewState != DISABLE) + { + tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE); + } + else + { + tmpreg |= (uint32_t)(RTC_TimeStampEdge); + } + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Configure the Time Stamp TSEDGE and Enable bits */ + RTC->CR = (uint32_t)tmpreg; + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Get the RTC TimeStamp value and masks. + * @param RTC_Format: specifies the format of the output parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will + * contains the TimeStamp time values. + * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will + * contains the TimeStamp date values. + * @retval None + */ +void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, + RTC_DateTypeDef* RTC_StampDateStruct) +{ + uint32_t tmptime = 0, tmpdate = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + /* Get the TimeStamp time and date registers values */ + tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK); + tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK); + + /* Fill the Time structure fields with the read parameters */ + RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16); + RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8); + RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); + RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); + + /* Fill the Date structure fields with the read parameters */ + RTC_StampDateStruct->RTC_Year = 0; + RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8); + RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); + RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); + + /* Check the input parameters format */ + if (RTC_Format == RTC_Format_BIN) + { + /* Convert the Time structure parameters to Binary format */ + RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours); + RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes); + RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds); + + /* Convert the Date structure parameters to Binary format */ + RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month); + RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date); + RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay); + } +} + +/** + * @brief Get the RTC timestamp Subseconds value. + * @param None + * @retval RTC current timestamp Subseconds value. + */ +uint32_t RTC_GetTimeStampSubSecond(void) +{ + /* Get timestamp subseconds values from the correspondent registers */ + return (uint32_t)(RTC->TSSSR); +} + +/** + * @} + */ + +/** @defgroup RTC_Group9 Tampers configuration functions + * @brief Tampers configuration functions + * +@verbatim + =============================================================================== + ##### Tampers configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the select Tamper pin edge. + * @param RTC_Tamper: Selected tamper pin. + * This parameter can be any combination of the following values: + * @arg RTC_Tamper_1: Select Tamper 1. + * @arg RTC_Tamper_2: Select Tamper 2. + * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that + * stimulates tamper event. + * This parameter can be one of the following values: + * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event. + * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event. + * @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event. + * @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event. + * @retval None + */ +void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(RTC_Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger)); + + if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge) + { + /* Configure the RTC_TAFCR register */ + RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1)); + } + else + { + /* Configure the RTC_TAFCR register */ + RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1); + } +} + +/** + * @brief Enables or Disables the Tamper detection. + * @param RTC_Tamper: Selected tamper pin. + * This parameter can be any combination of the following values: + * @arg RTC_Tamper_1: Select Tamper 1. + * @arg RTC_Tamper_2: Select Tamper 2. + * @param NewState: new state of the tamper pin. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(RTC_Tamper)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected Tamper pin */ + RTC->TAFCR |= (uint32_t)RTC_Tamper; + } + else + { + /* Disable the selected Tamper pin */ + RTC->TAFCR &= (uint32_t)~RTC_Tamper; + } +} + +/** + * @brief Configures the Tampers Filter. + * @param RTC_TamperFilter: Specifies the tampers filter. + * This parameter can be one of the following values: + * @arg RTC_TamperFilter_Disable: Tamper filter is disabled. + * @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive + * samples at the active level + * @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive + * samples at the active level + * @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive + * samples at the active level + * @retval None + */ +void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter)); + + /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */ + RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT); + + /* Configure the RTC_TAFCR register */ + RTC->TAFCR |= (uint32_t)RTC_TamperFilter; +} + +/** + * @brief Configures the Tampers Sampling Frequency. + * @param RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency. + * This parameter can be one of the following values: + * @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 32768 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 16384 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 8192 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 4096 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 2048 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 1024 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 512 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 256 + * @retval None + */ +void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq)); + + /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */ + RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ); + + /* Configure the RTC_TAFCR register */ + RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq; +} + +/** + * @brief Configures the Tampers Pins input Precharge Duration. + * @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input + * Precharge Duration. + * This parameter can be one of the following values: + * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle + * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle + * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle + * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle + * @retval None + */ +void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration)); + + /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */ + RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH); + + /* Configure the RTC_TAFCR register */ + RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration; +} + +/** + * @brief Enables or Disables the TimeStamp on Tamper Detection Event. + * @note The timestamp is valid even the TSE bit in tamper control register + * is reset. + * @param NewState: new state of the timestamp on tamper event. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Save timestamp on tamper detection event */ + RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS; + } + else + { + /* Tamper detection does not cause a timestamp to be saved */ + RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS; + } +} + +/** + * @brief Enables or Disables the Precharge of Tamper pin. + * @param NewState: new state of tamper pull up. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TamperPullUpCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable precharge of the selected Tamper pin */ + RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS; + } + else + { + /* Disable precharge of the selected Tamper pin */ + RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS; + } +} + +/** + * @} + */ + +/** @defgroup RTC_Group10 Backup Data Registers configuration functions + * @brief Backup Data Registers configuration functions + * +@verbatim + =============================================================================== + ##### Backup Data Registers configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Writes a data in a specified RTC Backup data register. + * @param RTC_BKP_DR: RTC Backup data Register number. + * This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 to + * specify the register. + * @param Data: Data to be written in the specified RTC Backup data register. + * @retval None + */ +void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_RTC_BKP(RTC_BKP_DR)); + + tmp = RTC_BASE + 0x50; + tmp += (RTC_BKP_DR * 4); + + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; +} + +/** + * @brief Reads data from the specified RTC Backup data Register. + * @param RTC_BKP_DR: RTC Backup data Register number. + * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to + * specify the register. + * @retval None + */ +uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_RTC_BKP(RTC_BKP_DR)); + + tmp = RTC_BASE + 0x50; + tmp += (RTC_BKP_DR * 4); + + /* Read the specified register */ + return (*(__IO uint32_t *)tmp); +} + +/** + * @} + */ + +/** @defgroup RTC_Group11 Output Type Config configuration functions + * @brief Output Type Config configuration functions + * +@verbatim + =============================================================================== + ##### Output Type Config configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the RTC Output Pin mode. + * @param RTC_OutputType: specifies the RTC Output (PC13) pin mode. + * This parameter can be one of the following values: + * @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in + * Open Drain mode. + * @arg RTC_OutputType_PushPull: RTC Output (PC13) is configured in + * Push Pull mode. + * @retval None + */ +void RTC_OutputTypeConfig(uint32_t RTC_OutputType) +{ + /* Check the parameters */ + assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType)); + + RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE); + RTC->TAFCR |= (uint32_t)(RTC_OutputType); +} + +/** + * @} + */ + +/** @defgroup RTC_Group12 Shift control synchronisation functions + * @brief Shift control synchronisation functions + * +@verbatim + =============================================================================== + ##### Shift control synchronisation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the Synchronization Shift Control Settings. + * @note When REFCKON is set, firmware must not write to Shift control register + * @param RTC_ShiftAdd1S: Select to add or not 1 second to the time Calendar. + * This parameter can be one of the following values : + * @arg RTC_ShiftAdd1S_Set: Add one second to the clock calendar. + * @arg RTC_ShiftAdd1S_Reset: No effect. + * @param RTC_ShiftSubFS: Select the number of Second Fractions to Substitute. + * This parameter can be one any value from 0 to 0x7FFF. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Shift registers are configured + * - ERROR: RTC Shift registers are not configured +*/ +ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS) +{ + ErrorStatus status = ERROR; + uint32_t shpfcount = 0; + + /* Check the parameters */ + assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S)); + assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Check if a Shift is pending*/ + if ((RTC->ISR & RTC_ISR_SHPF) != RESET) + { + /* Wait until the shift is completed*/ + while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT)) + { + shpfcount++; + } + } + + /* Check if the Shift pending is completed or if there is no Shift operation at all*/ + if ((RTC->ISR & RTC_ISR_SHPF) == RESET) + { + /* check if the reference clock detection is disabled */ + if((RTC->CR & RTC_CR_REFCKON) == RESET) + { + /* Configure the Shift settings */ + RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S); + + if(RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + else + { + status = ERROR; + } + } + else + { + status = ERROR; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return (ErrorStatus)(status); +} + +/** + * @} + */ + +/** @defgroup RTC_Group13 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + [..] All RTC interrupts are connected to the EXTI controller. + + (+) To enable the RTC Alarm interrupt, the following sequence is required: + (++) Configure and enable the EXTI Line 17 in interrupt mode and select the rising + edge sensitivity using the EXTI_Init() function. + (++) Configure and enable the RTC_Alarm IRQ channel in the NVIC using the NVIC_Init() + function. + (++) Configure the RTC to generate RTC alarms (Alarm A) using + the RTC_SetAlarm() and RTC_AlarmCmd() functions. + + (+) To enable the RTC Tamper interrupt, the following sequence is required: + (++) Configure and enable the EXTI Line 19 in interrupt mode and select the rising + edge sensitivity using the EXTI_Init() function. + (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init() + function. + (++) Configure the RTC to detect the RTC tamper event using the + RTC_TamperTriggerConfig() and RTC_TamperCmd() functions. + + (+) To enable the RTC TimeStamp interrupt, the following sequence is required: + (++) Configure and enable the EXTI Line 19 in interrupt mode and select the rising + edge sensitivity using the EXTI_Init() function. + (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init() + function. + (++) Configure the RTC to detect the RTC time-stamp event using the + RTC_TimeStampCmd() functions. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified RTC interrupts. + * @param RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TS: Time Stamp interrupt mask + * @arg RTC_IT_WUT: WakeUp Timer interrupt mask, available only for STM32F072 devices + * @arg RTC_IT_ALRA: Alarm A interrupt mask + * @arg RTC_IT_TAMP: Tamper event interrupt mask + * @param NewState: new state of the specified RTC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RTC_CONFIG_IT(RTC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + if (NewState != DISABLE) + { + /* Configure the Interrupts in the RTC_CR register */ + RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE); + /* Configure the Tamper Interrupt in the RTC_TAFCR */ + RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE); + } + else + { + /* Configure the Interrupts in the RTC_CR register */ + RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE); + /* Configure the Tamper Interrupt in the RTC_TAFCR */ + RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE); + } + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Checks whether the specified RTC flag is set or not. + * @param RTC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg RTC_FLAG_RECALPF: RECALPF event flag + * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag + * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag + * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag + * @arg RTC_FLAG_TSF: Time Stamp event flag + * @arg RTC_FLAG_WUTF: WakeUp Timer flag, available only for STM32F072 devices + * @arg RTC_FLAG_ALRAF: Alarm A flag + * @arg RTC_FLAG_INITF: Initialization mode flag + * @arg RTC_FLAG_RSF: Registers Synchronized flag + * @arg RTC_FLAG_INITS: Registers Configured flag + * @retval The new state of RTC_FLAG (SET or RESET). + */ +FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); + + /* Get all the flags */ + tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK); + + /* Return the status of the flag */ + if ((tmpreg & RTC_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTC's pending flags. + * @param RTC_FLAG: specifies the RTC flag to clear. + * This parameter can be any combination of the following values: + * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag + * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag + * @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag + * @arg RTC_FLAG_TSF: Time Stamp event flag + * @arg RTC_FLAG_WUTF: WakeUp Timer flag, available only for STM32F072 devices + * @arg RTC_FLAG_ALRAF: Alarm A flag + * @arg RTC_FLAG_RSF: Registers Synchronized flag + * @retval None + */ +void RTC_ClearFlag(uint32_t RTC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); + + /* Clear the Flags in the RTC_ISR register */ + RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0001FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); +} + +/** + * @brief Checks whether the specified RTC interrupt has occurred or not. + * @param RTC_IT: specifies the RTC interrupt source to check. + * This parameter can be one of the following values: + * @arg RTC_IT_TS: Time Stamp interrupt + * @arg RTC_IT_WUT: WakeUp Timer interrupt, available only for STM32F072 devices + * @arg RTC_IT_ALRA: Alarm A interrupt + * @arg RTC_IT_TAMP1: Tamper1 event interrupt + * @arg RTC_IT_TAMP2: Tamper2 event interrupt + * @retval The new state of RTC_IT (SET or RESET). + */ +ITStatus RTC_GetITStatus(uint32_t RTC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_RTC_GET_IT(RTC_IT)); + + /* Get the TAMPER Interrupt enable bit and pending bit */ + tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE)); + + /* Get the Interrupt enable Status */ + enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & ((RTC_IT >> (RTC_IT >> 18)) >> 15))); + + /* Get the Interrupt pending bit */ + tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4))); + + /* Get the status of the Interrupt */ + if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTC's interrupt pending bits. + * @param RTC_IT: specifies the RTC interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TS: Time Stamp interrupt + * @arg RTC_IT_WUT: WakeUp Timer interrupt, available only for STM32F072 devices + * @arg RTC_IT_ALRA: Alarm A interrupt + * @arg RTC_IT_TAMP1: Tamper1 event interrupt + * @arg RTC_IT_TAMP2: Tamper2 event interrupt + * @retval None + */ +void RTC_ClearITPendingBit(uint32_t RTC_IT) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_CLEAR_IT(RTC_IT)); + + /* Get the RTC_ISR Interrupt pending bits mask */ + tmpreg = (uint32_t)(RTC_IT >> 4); + + /* Clear the interrupt pending bits in the RTC_ISR register */ + RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); +} + +/** + * @} + */ + +/** + * @brief Converts a 2 digit decimal to BCD format. + * @param Value: Byte to be converted. + * @retval Converted byte + */ +static uint8_t RTC_ByteToBcd2(uint8_t Value) +{ + uint8_t bcdhigh = 0; + + while (Value >= 10) + { + bcdhigh++; + Value -= 10; + } + + return ((uint8_t)(bcdhigh << 4) | Value); +} + +/** + * @brief Convert from 2 digit BCD to Binary. + * @param Value: BCD value to be converted. + * @retval Converted word + */ +static uint8_t RTC_Bcd2ToByte(uint8_t Value) +{ + uint8_t tmp = 0; + tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; + return (tmp + (Value & (uint8_t)0x0F)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_spi.c b/system/src/stm32f0-stdperiph/stm32f0xx_spi.c new file mode 100644 index 0000000..949ef57 --- /dev/null +++ b/system/src/stm32f0-stdperiph/stm32f0xx_spi.c @@ -0,0 +1,1334 @@ +/** + ****************************************************************************** + * @file stm32f0xx_spi.c + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Serial peripheral interface (SPI): + * + Initialization and Configuration + * + Data transfers functions + * + Hardware CRC Calculation + * + DMA transfers management + * + Interrupts and flags management + * + * @verbatim + + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) + function for SPI1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) + function for SPI2. + + (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using + RCC_AHBPeriphClockCmd() function. + + (#) Peripherals alternate function: + (++) Connect the pin to the desired peripherals' Alternate + Function (AF) using GPIO_PinAFConfig() function. + (++) Configure the desired pin in alternate function by: + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF. + (++) Select the type, pull-up/pull-down and output speed via + GPIO_PuPd, GPIO_OType and GPIO_Speed members. + (++) Call GPIO_Init() function. + + (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave + Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() + function.In I2S mode, program the Mode, Standard, Data Format, MCLK + Output, Audio frequency and Polarity using I2S_Init() function. + + (#) Configure the FIFO threshold using SPI_RxFIFOThresholdConfig() to select + at which threshold the RXNE event is generated. + + (#) Enable the NVIC and the corresponding interrupt using the function + SPI_ITConfig() if you need to use interrupt mode. + + (#) When using the DMA mode + (++) Configure the DMA using DMA_Init() function. + (++) Active the needed channel Request using SPI_I2S_DMACmd() function. + + (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using + I2S_Cmd(). + + (#) Enable the DMA using the DMA_Cmd() function when using DMA mode. + + (#) Optionally, you can enable/configure the following parameters without + re-initialization (i.e there is no need to call again SPI_Init() function): + (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx) + is programmed as Data direction parameter using the SPI_Init() + function it can be possible to switch between SPI_Direction_Tx + or SPI_Direction_Rx using the SPI_BiDirectionalLineConfig() function. + (++) When SPI_NSS_Soft is selected as Slave Select Management parameter + using the SPI_Init() function it can be possible to manage the + NSS internal signal using the SPI_NSSInternalSoftwareConfig() function. + (++) Reconfigure the data size using the SPI_DataSizeConfig() function. + (++) Enable or disable the SS output using the SPI_SSOutputCmd() function. + + (#) To use the CRC Hardware calculation feature refer to the Peripheral + CRC hardware Calculation subsection. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_spi.h" +#include "stm32f0xx_rcc.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup SPI + * @brief SPI driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* SPI registers Masks */ +#define CR1_CLEAR_MASK ((uint16_t)0x3040) +#define CR1_CLEAR_MASK2 ((uint16_t)0xFFFB) +#define CR2_LDMA_MASK ((uint16_t)0x9FFF) + +#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup SPI_Private_Functions + * @{ + */ + +/** @defgroup SPI_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides a set of functions allowing to initialize the SPI Direction, + SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud + Rate Prescaler, SPI First Bit and SPI CRC Polynomial. + + [..] The SPI_Init() function follows the SPI configuration procedures for Master mode + and Slave mode (details for these procedures are available in reference manual). + + [..] When the Software NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Soft) is selected, + use the following function to manage the NSS bit: + void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); + + [..] In Master mode, when the Hardware NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Hard) + is selected, use the follwoing function to enable the NSS output feature. + void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); + + [..] The NSS pulse mode can be managed by the SPI TI mode when enabling it using the following function: + void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); + And it can be managed by software in the SPI Motorola mode using this function: + void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); + + [..] This section provides also functions to initialize the I2S Mode, Standard, + Data Format, MCLK Output, Audio frequency and Polarity. + + [..] The I2S_Init() function follows the I2S configuration procedures for Master mode + and Slave mode. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the SPIx peripheral registers to their default + * reset values. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @note SPI2 is not available for STM32F031 devices. + * I2S mode is not supported for STM32F030 devices. + * @retval None + */ +void SPI_I2S_DeInit(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + if (SPIx == SPI1) + { + /* Enable SPI1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); + /* Release SPI1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); + } + else + { + if (SPIx == SPI2) + { + /* Enable SPI2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); + /* Release SPI2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); + } + } +} + +/** + * @brief Fills each SPI_InitStruct member with its default value. + * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized. + * @retval None + */ +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) +{ +/*--------------- Reset SPI init structure parameters values -----------------*/ + /* Initialize the SPI_Direction member */ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + /* Initialize the SPI_Mode member */ + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + /* Initialize the SPI_DataSize member */ + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + /* Initialize the SPI_CPOL member */ + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + /* Initialize the SPI_CPHA member */ + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + /* Initialize the SPI_NSS member */ + SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; + /* Initialize the SPI_BaudRatePrescaler member */ + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + /* Initialize the SPI_FirstBit member */ + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + /* Initialize the SPI_CRCPolynomial member */ + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @note SPI2 is not available for STM32F031 devices. + * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral. + * @retval None + */ +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) +{ + uint16_t tmpreg = 0; + + /* check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Check the SPI parameters */ + assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); + assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); + assert_param(IS_SPI_DATA_SIZE(SPI_InitStruct->SPI_DataSize)); + assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); + assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); + assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); + assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); + + /*---------------------------- SPIx CR1 Configuration ------------------------*/ + /* Get the SPIx CR1 value */ + tmpreg = SPIx->CR1; + /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, CPOL and CPHA bits */ + tmpreg &= CR1_CLEAR_MASK; + /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler + master/slave mode, CPOL and CPHA */ + /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ + /* Set SSM, SSI bit according to SPI_NSS values */ + /* Set LSBFirst bit according to SPI_FirstBit value */ + /* Set BR bits according to SPI_BaudRatePrescaler value */ + /* Set CPOL bit according to SPI_CPOL value */ + /* Set CPHA bit according to SPI_CPHA value */ + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_FirstBit | + SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA | + SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler); + /* Write to SPIx CR1 */ + SPIx->CR1 = tmpreg; + /*-------------------------Data Size Configuration -----------------------*/ + /* Get the SPIx CR2 value */ + tmpreg = SPIx->CR2; + /* Clear DS[3:0] bits */ + tmpreg &=(uint16_t)~SPI_CR2_DS; + /* Configure SPIx: Data Size */ + tmpreg |= (uint16_t)(SPI_InitStruct->SPI_DataSize); + /* Write to SPIx CR2 */ + SPIx->CR2 = tmpreg; + + /*---------------------------- SPIx CRCPOLY Configuration --------------------*/ + /* Write to SPIx CRCPOLY */ + SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; + + /*---------------------------- SPIx CR1 Configuration ------------------------*/ + /* Get the SPIx CR1 value */ + tmpreg = SPIx->CR1; + /* Clear MSTR bit */ + tmpreg &= CR1_CLEAR_MASK2; + /* Configure SPIx: master/slave mode */ + /* Set MSTR bit according to SPI_Mode */ + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Mode); + /* Write to SPIx CR1 */ + SPIx->CR1 = tmpreg; + + /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ + SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD); +} + +/** + * @brief Fills each I2S_InitStruct member with its default value. + * @note This mode is not supported for STM32F030 devices. + * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized. + * @retval None + */ +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) +{ +/*--------------- Reset I2S init structure parameters values -----------------*/ + /* Initialize the I2S_Mode member */ + I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; + + /* Initialize the I2S_Standard member */ + I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; + + /* Initialize the I2S_DataFormat member */ + I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; + + /* Initialize the I2S_MCLKOutput member */ + I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; + + /* Initialize the I2S_AudioFreq member */ + I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; + + /* Initialize the I2S_CPOL member */ + I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the I2S_InitStruct. + * @note This mode is not supported for STM32F030 devices. + * @param SPIx: where x can be 1 to select the SPI peripheral (configured in I2S mode). + * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral + * configured in I2S mode. + * @note This function calculates the optimal prescaler needed to obtain the most + * accurate audio frequency (depending on the I2S clock source, the PLL values + * and the product configuration). But in case the prescaler value is greater + * than 511, the default value (0x02) will be configured instead. + * @retval None + */ +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) +{ + uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; + uint32_t tmp = 0; + RCC_ClocksTypeDef RCC_Clocks; + uint32_t sourceclock = 0; + + /* Check the I2S parameters */ + assert_param(IS_SPI_1_PERIPH(SPIx)); + assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); + assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); + assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); + assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); + assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); + assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); + +/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; + SPIx->I2SPR = 0x0002; + + /* Get the I2SCFGR register value */ + tmpreg = SPIx->I2SCFGR; + + /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ + if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) + { + i2sodd = (uint16_t)0; + i2sdiv = (uint16_t)2; + } + /* If the requested audio frequency is not the default, compute the prescaler */ + else + { + /* Check the frame length (For the Prescaler computing) */ + if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) + { + /* Packet length is 16 bits */ + packetlength = 1; + } + else + { + /* Packet length is 32 bits */ + packetlength = 2; + } + + /* I2S Clock source is System clock: Get System Clock frequency */ + RCC_GetClocksFreq(&RCC_Clocks); + + /* Get the source clock value: based on System Clock value */ + sourceclock = RCC_Clocks.SYSCLK_Frequency; + + /* Compute the Real divider depending on the MCLK output state with a floating point */ + if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) + { + /* MCLK output is enabled */ + tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + else + { + /* MCLK output is disabled */ + tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + + /* Remove the floating point */ + tmp = tmp / 10; + + /* Check the parity of the divider */ + i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); + + /* Compute the i2sdiv prescaler */ + i2sdiv = (uint16_t)((tmp - i2sodd) / 2); + + /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ + i2sodd = (uint16_t) (i2sodd << 8); + } + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2) || (i2sdiv > 0xFF)) + { + /* Set the default values */ + i2sdiv = 2; + i2sodd = 0; + } + + /* Write to SPIx I2SPR register the computed value */ + SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); + + /* Configure the I2S with the SPI_InitStruct values */ + tmpreg |= (uint16_t)(SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \ + (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ + (uint16_t)I2S_InitStruct->I2S_CPOL)))); + + /* Write to SPIx I2SCFGR */ + SPIx->I2SCFGR = tmpreg; +} + +/** + * @brief Enables or disables the specified SPI peripheral. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @note SPI2 is not available for STM32F031 devices. + * @param NewState: new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral */ + SPIx->CR1 |= SPI_CR1_SPE; + } + else + { + /* Disable the selected SPI peripheral */ + SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE); + } +} + +/** + * @brief Enables or disables the TI Mode. + * + * @note This function can be called only after the SPI_Init() function has + * been called. + * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA + * are not taken into consideration and are configured by hardware + * respectively to the TI mode requirements. + * + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @note SPI2 is not available for STM32F031 devices. + * @param NewState: new state of the selected SPI TI communication mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TI mode for the selected SPI peripheral */ + SPIx->CR2 |= SPI_CR2_FRF; + } + else + { + /* Disable the TI mode for the selected SPI peripheral */ + SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRF); + } +} + +/** + * @brief Enables or disables the specified SPI peripheral (in I2S mode). + * @note This mode is not supported for STM32F030 devices. + * @param SPIx: where x can be 1 to select the SPI peripheral. + * @param NewState: new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_1_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral in I2S mode */ + SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE; + } + else + { + /* Disable the selected SPI peripheral in I2S mode */ + SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE); + } +} + +/** + * @brief Configures the data size for the selected SPI. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @note SPI2 is not available for STM32F031 devices. + * @param SPI_DataSize: specifies the SPI data size. + * For the SPIx peripheral this parameter can be one of the following values: + * @arg SPI_DataSize_4b: Set data size to 4 bits + * @arg SPI_DataSize_5b: Set data size to 5 bits + * @arg SPI_DataSize_6b: Set data size to 6 bits + * @arg SPI_DataSize_7b: Set data size to 7 bits + * @arg SPI_DataSize_8b: Set data size to 8 bits + * @arg SPI_DataSize_9b: Set data size to 9 bits + * @arg SPI_DataSize_10b: Set data size to 10 bits + * @arg SPI_DataSize_11b: Set data size to 11 bits + * @arg SPI_DataSize_12b: Set data size to 12 bits + * @arg SPI_DataSize_13b: Set data size to 13 bits + * @arg SPI_DataSize_14b: Set data size to 14 bits + * @arg SPI_DataSize_15b: Set data size to 15 bits + * @arg SPI_DataSize_16b: Set data size to 16 bits + * @retval None + */ +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) +{ + uint16_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DATA_SIZE(SPI_DataSize)); + /* Read the CR2 register */ + tmpreg = SPIx->CR2; + /* Clear DS[3:0] bits */ + tmpreg &= (uint16_t)~SPI_CR2_DS; + /* Set new DS[3:0] bits value */ + tmpreg |= SPI_DataSize; + SPIx->CR2 = tmpreg; +} + +/** + * @brief Configures the FIFO reception threshold for the selected SPI. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @note SPI2 is not available for STM32F031 devices. + * @param SPI_RxFIFOThreshold: specifies the FIFO reception threshold. + * This parameter can be one of the following values: + * @arg SPI_RxFIFOThreshold_HF: RXNE event is generated if the FIFO + * level is greater or equal to 1/2. + * @arg SPI_RxFIFOThreshold_QF: RXNE event is generated if the FIFO + * level is greater or equal to 1/4. + * @retval None + */ +void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_RX_FIFO_THRESHOLD(SPI_RxFIFOThreshold)); + + /* Clear FRXTH bit */ + SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRXTH); + + /* Set new FRXTH bit value */ + SPIx->CR2 |= SPI_RxFIFOThreshold; +} + +/** + * @brief Selects the data transfer direction in bidirectional mode for the specified SPI. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @note SPI2 is not available for STM32F031 devices. + * @param SPI_Direction: specifies the data transfer direction in bidirectional mode. + * This parameter can be one of the following values: + * @arg SPI_Direction_Tx: Selects Tx transmission direction + * @arg SPI_Direction_Rx: Selects Rx receive direction + * @retval None + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DIRECTION(SPI_Direction)); + if (SPI_Direction == SPI_Direction_Tx) + { + /* Set the Tx only mode */ + SPIx->CR1 |= SPI_Direction_Tx; + } + else + { + /* Set the Rx only mode */ + SPIx->CR1 &= SPI_Direction_Rx; + } +} + +/** + * @brief Configures internally by software the NSS pin for the selected SPI. + * @note This function can be called only after the SPI_Init() function has + * been called. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @note SPI2 is not available for STM32F031 devices. + * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. + * This parameter can be one of the following values: + * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally + * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally + * @retval None + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); + + if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + /* Set NSS pin internally by software */ + SPIx->CR1 |= SPI_NSSInternalSoft_Set; + } + else + { + /* Reset NSS pin internally by software */ + SPIx->CR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/** + * @brief Enables or disables the SS output for the selected SPI. + * @note This function can be called only after the SPI_Init() function has + * been called and the NSS hardware management mode is selected. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @note SPI2 is not available for STM32F031 devices. + * @param NewState: new state of the SPIx SS output. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI SS output */ + SPIx->CR2 |= SPI_CR2_SSOE; + } + else + { + /* Disable the selected SPI SS output */ + SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE); + } +} + +/** + * @brief Enables or disables the NSS pulse management mode. + * @note This function can be called only after the SPI_Init() function has + * been called. + * @note When TI mode is selected, the control bits NSSP is not taken into + * consideration and are configured by hardware respectively to the + * TI mode requirements. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @note SPI2 is not available for STM32F031 devices. + * @param NewState: new state of the NSS pulse management mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the NSS pulse management mode */ + SPIx->CR2 |= SPI_CR2_NSSP; + } + else + { + /* Disable the NSS pulse management mode */ + SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_NSSP); + } +} + +/** + * @} + */ + +/** @defgroup SPI_Group2 Data transfers functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### Data transfers functions ##### + =============================================================================== + [..] This section provides a set of functions allowing to manage the SPI or I2S + data transfers. + + [..] In reception, data are received and then stored into an internal Rx buffer while + In transmission, data are first stored into an internal Tx buffer before being + transmitted. + + [..] The read access of the SPI_DR register can be done using + SPI_ReceiveData8() (when data size is equal or inferior than 8bits) and. + SPI_I2S_ReceiveData16() (when data size is superior than 8bits)function + and returns the Rx buffered value. Whereas a write access to the SPI_DR + can be done using SPI_SendData8() (when data size is equal or inferior than 8bits) + and SPI_I2S_SendData16() (when data size is superior than 8bits) function + and stores the written data into Tx buffer. + +@endverbatim + * @{ + */ + +/** + * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * @param SPIx: where x can be 1 or 2 in SPI mode to select the SPI peripheral. + * @note SPI2 is not available for STM32F031 devices. + * @param Data: Data to be transmitted. + * @retval None + */ +void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data) +{ + uint32_t spixbase = 0x00; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + spixbase = (uint32_t)SPIx; + spixbase += 0x0C; + + *(__IO uint8_t *) spixbase = Data; +} + +/** + * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select + * the SPI peripheral. + * @note SPI2 is not available for STM32F031 devices. + * @param Data: Data to be transmitted. + * @retval None + */ +void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + SPIx->DR = (uint16_t)Data; +} + +/** + * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. + * @param SPIx: where x can be 1 or 2 in SPI mode to select the SPI peripheral. + * @note SPI2 is not available for STM32F031 devices. + * @retval The value of the received data. + */ +uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx) +{ + uint32_t spixbase = 0x00; + + spixbase = (uint32_t)SPIx; + spixbase += 0x0C; + + return *(__IO uint8_t *) spixbase; +} + +/** + * @brief Returns the most recent received data by the SPIx peripheral. + * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select + * @note SPI2 is not available for STM32F031 devices. + * the SPI peripheral. + * @retval The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx) +{ + return SPIx->DR; +} +/** + * @} + */ + +/** @defgroup SPI_Group3 Hardware CRC Calculation functions + * @brief Hardware CRC Calculation functions + * +@verbatim + =============================================================================== + ##### Hardware CRC Calculation functions ##### + =============================================================================== + [..] This section provides a set of functions allowing to manage the SPI CRC hardware + calculation.SPI communication using CRC is possible through the following procedure: + + (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, + Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() + function. + (#) Enable the CRC calculation using the SPI_CalculateCRC() function. + (#) Enable the SPI using the SPI_Cmd() function + (#) Before writing the last data to the TX buffer, set the CRCNext bit using the + SPI_TransmitCRC() function to indicate that after transmission of the last + data, the CRC should be transmitted. + (#) After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT + bit is reset. The CRC is also received and compared against the SPI_RXCRCR + value. + If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt + can be generated when the SPI_I2S_IT_ERR interrupt is enabled. + + -@- + (+@) It is advised to don't read the calculate CRC values during the communication. + (+@) When the SPI is in slave mode, be careful to enable CRC calculation only + when the clock is stable, that is, when the clock is in the steady state. + If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive + to the SCK slave input clock as soon as CRCEN is set, and this, whatever + the value of the SPE bit. + (+@) With high bitrate frequencies, be careful when transmitting the CRC. + As the number of used CPU cycles has to be as low as possible in the CRC + transfer phase, it is forbidden to call software functions in the CRC + transmission sequence to avoid errors in the last data and CRC reception. + In fact, CRCNEXT bit has to be written before the end of the transmission/reception + of the last data. + (+@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the + degradation of the SPI speed performance due to CPU accesses impacting the + SPI bandwidth. + (+@) When the STM32F0xx are configured as slaves and the NSS hardware mode is + used, the NSS pin needs to be kept low between the data phase and the CRC + phase. + (+@) When the SPI is configured in slave mode with the CRC feature enabled, CRC + calculation takes place even if a high level is applied on the NSS pin. + This may happen for example in case of a multislave environment where the + communication master addresses slaves alternately. + (+@) Between a slave deselection (high level on NSS) and a new slave selection + (low level on NSS), the CRC value should be cleared on both master and slave + sides in order to resynchronize the master and slave for their respective + CRC calculation. + + -@- To clear the CRC, follow the procedure below: + (#@) Disable SPI using the SPI_Cmd() function + (#@) Disable the CRC calculation using the SPI_CalculateCRC() function. + (#@) Enable the CRC calculation using the SPI_CalculateCRC() function. + (#@) Enable SPI using the SPI_Cmd() function. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the CRC calculation length for the selected SPI. + * @note This function can be called only after the SPI_Init() function has + * been called. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @note SPI2 is not available for STM32F031 devices. + * @param SPI_CRCLength: specifies the SPI CRC calculation length. + * This parameter can be one of the following values: + * @arg SPI_CRCLength_8b: Set CRC Calculation to 8 bits + * @arg SPI_CRCLength_16b: Set CRC Calculation to 16 bits + * @retval None + */ +void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CRC_LENGTH(SPI_CRCLength)); + + /* Clear CRCL bit */ + SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCL); + + /* Set new CRCL bit value */ + SPIx->CR1 |= SPI_CRCLength; +} + +/** + * @brief Enables or disables the CRC value calculation of the transferred bytes. + * @note This function can be called only after the SPI_Init() function has + * been called. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @note SPI2 is not available for STM32F031 devices. + * @param NewState: new state of the SPIx CRC value calculation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI CRC calculation */ + SPIx->CR1 |= SPI_CR1_CRCEN; + } + else + { + /* Disable the selected SPI CRC calculation */ + SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN); + } +} + +/** + * @brief Transmit the SPIx CRC value. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @note SPI2 is not available for STM32F031 devices. + * @retval None + */ +void SPI_TransmitCRC(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Enable the selected SPI CRC transmission */ + SPIx->CR1 |= SPI_CR1_CRCNEXT; +} + +/** + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @note SPI2 is not available for STM32F031 devices. + * @param SPI_CRC: specifies the CRC register to be read. + * This parameter can be one of the following values: + * @arg SPI_CRC_Tx: Selects Tx CRC register + * @arg SPI_CRC_Rx: Selects Rx CRC register + * @retval The selected CRC register value.. + */ +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CRC(SPI_CRC)); + + if (SPI_CRC != SPI_CRC_Rx) + { + /* Get the Tx CRC register */ + crcreg = SPIx->TXCRCR; + } + else + { + /* Get the Rx CRC register */ + crcreg = SPIx->RXCRCR; + } + /* Return the selected CRC register */ + return crcreg; +} + +/** + * @brief Returns the CRC Polynomial register value for the specified SPI. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @note SPI2 is not available for STM32F031 devices. + * @retval The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Return the CRC polynomial register */ + return SPIx->CRCPR; +} + +/** + * @} + */ + +/** @defgroup SPI_Group4 DMA transfers management functions + * @brief DMA transfers management functions + * +@verbatim + =============================================================================== + ##### DMA transfers management functions ##### + =============================================================================== + [..] This section provides two functions that can be used only in DMA mode. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the SPIx/I2Sx DMA interface. + * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select + * the SPI peripheral. + * @note SPI2 is not available for STM32F031 devices. + * I2S mode is not supported for STM32F030 devices. + * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request + * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request + * @param NewState: new state of the selected SPI DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_I2S_DMA_REQ(SPI_I2S_DMAReq)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI DMA requests */ + SPIx->CR2 |= SPI_I2S_DMAReq; + } + else + { + /* Disable the selected SPI DMA requests */ + SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/** + * @brief Configures the number of data to transfer type(Even/Odd) for the DMA + * last transfers and for the selected SPI. + * @note This function have a meaning only if DMA mode is selected and if + * the packing mode is used (data length <= 8 and DMA transfer size halfword) + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @note SPI2 is not available for STM32F031 devices. + * @param SPI_LastDMATransfer: specifies the SPI last DMA transfers state. + * This parameter can be one of the following values: + * @arg SPI_LastDMATransfer_TxEvenRxEven: Number of data for transmission Even + * and number of data for reception Even. + * @arg SPI_LastDMATransfer_TxOddRxEven: Number of data for transmission Odd + * and number of data for reception Even. + * @arg SPI_LastDMATransfer_TxEvenRxOdd: Number of data for transmission Even + * and number of data for reception Odd. + * @arg SPI_LastDMATransfer_TxOddRxOdd: Number of data for transmission Odd + * and number of data for reception Odd. + * @retval None + */ +void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_LAST_DMA_TRANSFER(SPI_LastDMATransfer)); + + /* Clear LDMA_TX and LDMA_RX bits */ + SPIx->CR2 &= CR2_LDMA_MASK; + + /* Set new LDMA_TX and LDMA_RX bits value */ + SPIx->CR2 |= SPI_LastDMATransfer; +} + +/** + * @} + */ + +/** @defgroup SPI_Group5 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + [..] This section provides a set of functions allowing to configure the SPI/I2S Interrupts + sources and check or clear the flags or pending bits status. + The user should identify which mode will be used in his application to manage + the communication: Polling mode, Interrupt mode or DMA mode. + + *** Polling Mode *** + ==================== + [..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags: + (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register + (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register + (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI. + (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur + (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur + (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur + (#) SPI_I2S_FLAG_FRE: to indicate a Frame Format error occurs. + (#) I2S_FLAG_UDR: to indicate an Underrun error occurs. + (#) I2S_FLAG_CHSIDE: to indicate Channel Side. + + [..] + (@)Do not use the BSY flag to handle each data transmission or reception. It is better + to use the TXE and RXNE flags instead. + + [..] In this Mode it is advised to use the following functions: + (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); + (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); + + *** Interrupt Mode *** + ====================== + [..] In Interrupt Mode, the SPI/I2S communication can be managed by 3 interrupt sources + and 5 pending bits: + [..] Pending Bits: + (#) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register + (#) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register + (#) SPI_I2S_IT_OVR : to indicate if an Overrun error occur + (#) I2S_IT_UDR : to indicate an Underrun Error occurs. + (#) SPI_I2S_FLAG_FRE : to indicate a Frame Format error occurs. + + [..] Interrupt Source: + (#) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty + interrupt. + (#) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not + empty interrupt. + (#) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt. + + [..] In this Mode it is advised to use the following functions: + (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); + (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); + + *** FIFO Status *** + =================== + [..] It is possible to monitor the FIFO status when a transfer is ongoing using the + following function: + (+) uint32_t SPI_GetFIFOStatus(uint8_t SPI_FIFO_Direction); + + *** DMA Mode *** + ================ + [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel + requests: + (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request. + (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request. + + [..] In this Mode it is advised to use the following function: + (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState). + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified SPI/I2S interrupts. + * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select + * the SPI peripheral. + * @note SPI2 is not available for STM32F031 devices. + * I2S mode is not supported for STM32F030 devices. + * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. + * This parameter can be one of the following values: + * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask + * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask + * @arg SPI_I2S_IT_ERR: Error interrupt mask + * @param NewState: new state of the specified SPI interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) +{ + uint16_t itpos = 0, itmask = 0 ; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); + + /* Get the SPI IT index */ + itpos = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = (uint16_t)1 << (uint16_t)itpos; + + if (NewState != DISABLE) + { + /* Enable the selected SPI interrupt */ + SPIx->CR2 |= itmask; + } + else + { + /* Disable the selected SPI interrupt */ + SPIx->CR2 &= (uint16_t)~itmask; + } +} + +/** + * @brief Returns the current SPIx Transmission FIFO filled level. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @note SPI2 is not available for STM32F031 devices. + * @retval The Transmission FIFO filling state. + * - SPI_TransmissionFIFOStatus_Empty: when FIFO is empty + * - SPI_TransmissionFIFOStatus_1QuarterFull: if more than 1 quarter-full. + * - SPI_TransmissionFIFOStatus_HalfFull: if more than 1 half-full. + * - SPI_TransmissionFIFOStatus_Full: when FIFO is full. + */ +uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx) +{ + /* Get the SPIx Transmission FIFO level bits */ + return (uint16_t)((SPIx->SR & SPI_SR_FTLVL)); +} + +/** + * @brief Returns the current SPIx Reception FIFO filled level. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @note SPI2 is not available for STM32F031 devices. + * @retval The Reception FIFO filling state. + * - SPI_ReceptionFIFOStatus_Empty: when FIFO is empty + * - SPI_ReceptionFIFOStatus_1QuarterFull: if more than 1 quarter-full. + * - SPI_ReceptionFIFOStatus_HalfFull: if more than 1 half-full. + * - SPI_ReceptionFIFOStatus_Full: when FIFO is full. + */ +uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx) +{ + /* Get the SPIx Reception FIFO level bits */ + return (uint16_t)((SPIx->SR & SPI_SR_FRLVL)); +} + +/** + * @brief Checks whether the specified SPI flag is set or not. + * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select + * the SPI peripheral. + * @note SPI2 is not available for STM32F031 devices. + * I2S mode is not supported for STM32F030 devices. + * @param SPI_I2S_FLAG: specifies the SPI flag to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. + * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. + * @arg SPI_I2S_FLAG_BSY: Busy flag. + * @arg SPI_I2S_FLAG_OVR: Overrun flag. + * @arg SPI_FLAG_MODF: Mode Fault flag. + * @arg SPI_FLAG_CRCERR: CRC Error flag. + * @arg SPI_I2S_FLAG_FRE: TI frame format error flag. + * @arg I2S_FLAG_UDR: Underrun Error flag. + * @arg I2S_FLAG_CHSIDE: Channel Side flag. + * @retval The new state of SPI_I2S_FLAG (SET or RESET). + */ +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); + + /* Check the status of the specified SPI flag */ + if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) + { + /* SPI_I2S_FLAG is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_FLAG is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @note SPI2 is not available for STM32F031 devices. + * I2S mode is not supported for STM32F030 devices. + * @param SPI_I2S_FLAG: specifies the SPI flag to clear. + * This function clears only CRCERR flag. + * @note OVR (OverRun error) flag is cleared by software sequence: a read + * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by + * a read operation to SPI_SR register (SPI_I2S_GetFlagStatus()). + * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write + * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by + * a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). + * @retval None + */ +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CLEAR_FLAG(SPI_I2S_FLAG)); + + /* Clear the selected SPI CRC Error (CRCERR) flag */ + SPIx->SR = (uint16_t)~SPI_I2S_FLAG; +} + +/** + * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. + * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select + * the SPI peripheral. + * @param SPI_I2S_IT: specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. + * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. + * @arg SPI_IT_MODF: Mode Fault interrupt. + * @arg SPI_I2S_IT_OVR: Overrun interrupt. + * @arg I2S_IT_UDR: Underrun interrupt. + * @arg SPI_I2S_IT_FRE: Format Error interrupt. + * @retval The new state of SPI_I2S_IT (SET or RESET). + */ +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); + + /* Get the SPI_I2S_IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Get the SPI_I2S_IT IT mask */ + itmask = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = 0x01 << itmask; + + /* Get the SPI_I2S_IT enable bit status */ + enablestatus = (SPIx->CR2 & itmask) ; + + /* Check the status of the specified SPI interrupt */ + if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) + { + /* SPI_I2S_IT is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_IT is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_IT status */ + return bitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_syscfg.c b/system/src/stm32f0-stdperiph/stm32f0xx_syscfg.c new file mode 100644 index 0000000..5c7cdd3 --- /dev/null +++ b/system/src/stm32f0-stdperiph/stm32f0xx_syscfg.c @@ -0,0 +1,420 @@ +/** + ****************************************************************************** + * @file stm32f0xx_syscfg.c + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the SYSCFG peripheral: + * + Remapping the memory mapped at 0x00000000 + * + Remapping the DMA channels + * + Enabling I2C fast mode plus driving capability for I2C pins + * + Configuring the EXTI lines connection to the GPIO port + * + Configuring the CFGR2 features (Connecting some internal signal + * to the break input of TIM1) + * + * @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The SYSCFG registers can be accessed only when the SYSCFG + interface APB clock is enabled. + To enable SYSCFG APB clock use: + RCC_APBPeriphClockCmd(RCC_APBPeriph_SYSCFG, ENABLE). + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_syscfg.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup SYSCFG + * @brief SYSCFG driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup SYSCFG_Private_Functions + * @{ + */ + +/** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions + * @brief SYSCFG Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### SYSCFG Initialization and Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the SYSCFG registers to their default reset values. + * @param None + * @retval None + * @note MEM_MODE bits are not affected by APB reset. + * @note MEM_MODE bits took the value from the user option bytes. + * @note CFGR2 register is not affected by APB reset. + * @note CLABBB configuration bits are locked when set. + * @note To unlock the configuration, perform a system reset. + */ +void SYSCFG_DeInit(void) +{ + /* Set SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */ + SYSCFG->CFGR1 &= SYSCFG_CFGR1_MEM_MODE; + /* Set EXTICRx registers to reset value */ + SYSCFG->EXTICR[0] = 0; + SYSCFG->EXTICR[1] = 0; + SYSCFG->EXTICR[2] = 0; + SYSCFG->EXTICR[3] = 0; + /* Set CFGR2 register to reset value: clear SRAM parity error flag */ + SYSCFG->CFGR2 |= (uint32_t) SYSCFG_CFGR2_SRAM_PE; +} + +/** + * @brief Configures the memory mapping at address 0x00000000. + * @param SYSCFG_MemoryRemap: selects the memory remapping. + * This parameter can be one of the following values: + * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 + * @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000 + * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000 + * @retval None + */ +void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap) +{ + uint32_t tmpctrl = 0; + + /* Check the parameter */ + assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap)); + + /* Get CFGR1 register value */ + tmpctrl = SYSCFG->CFGR1; + + /* Clear MEM_MODE bits */ + tmpctrl &= (uint32_t) (~SYSCFG_CFGR1_MEM_MODE); + + /* Set the new MEM_MODE bits value */ + tmpctrl |= (uint32_t) SYSCFG_MemoryRemap; + + /* Set CFGR1 register with the new memory remap configuration */ + SYSCFG->CFGR1 = tmpctrl; +} + +/** + * @brief Configure the DMA channels remapping. + * @param SYSCFG_DMARemap: selects the DMA channels remap. + * This parameter can be one of the following values: + * @arg SYSCFG_DMARemap_TIM17: Remap TIM17 DMA requests from channel1 to channel2 + * @arg SYSCFG_DMARemap_TIM16: Remap TIM16 DMA requests from channel3 to channel4 + * @arg SYSCFG_DMARemap_USART1Rx: Remap USART1 Rx DMA requests from channel3 to channel5 + * @arg SYSCFG_DMARemap_USART1Tx: Remap USART1 Tx DMA requests from channel2 to channel4 + * @arg SYSCFG_DMARemap_ADC1: Remap ADC1 DMA requests from channel1 to channel2 + * @param NewState: new state of the DMA channel remapping. + * This parameter can be: ENABLE or DISABLE. + * @note When enabled, DMA channel of the selected peripheral is remapped + * @note When disabled, Default DMA channel is mapped to the selected peripheral + * @note By default TIM17 DMA requests is mapped to channel 1, + * use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable) to remap + * TIM17 DMA requests to channel 2 and use + * SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable) to map + * TIM17 DMA requests to channel 1 (default mapping) + * @note This function is only used for STM32F030, STM32F031, STM32F042, STM32F072 and STM32F051 devices. + * @retval None + */ +void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Remap the DMA channel */ + SYSCFG->CFGR1 |= (uint32_t)SYSCFG_DMARemap; + } + else + { + /* use the default DMA channel mapping */ + SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_DMARemap); + } +} + +/** + * @brief Configure the I2C fast mode plus driving capability. + * @param SYSCFG_I2CFastModePlus: selects the pin. + * This parameter can be one of the following values: + * @arg SYSCFG_I2CFastModePlus_PB6: Configure fast mode plus driving capability for PB6 + * @arg SYSCFG_I2CFastModePlus_PB7: Configure fast mode plus driving capability for PB7 + * @arg SYSCFG_I2CFastModePlus_PB8: Configure fast mode plus driving capability for PB8 + * @arg SYSCFG_I2CFastModePlus_PB9: Configure fast mode plus driving capability for PB9 + * @arg SYSCFG_I2CFastModePlus_PA9: Configure fast mode plus driving capability for PA9 (only for STM32F031 and STM32F030 devices) + * @arg SYSCFG_I2CFastModePlus_PA10: Configure fast mode plus driving capability for PA10 (only for STM32F031 and STM32F030 devices) + * @arg SYSCFG_I2CFastModePlus_I2C1: Configure fast mode plus driving capability for PB10, PB11, PF6 and PF7(only for STM32F031 and STM32F030 devices) + * @arg SYSCFG_I2CFastModePlus_I2C2: Configure fast mode plus driving capability for I2C2 pins, available only for STM32F072 devices + * + * @param NewState: new state of the DMA channel remapping. + * This parameter can be: ENABLE or DISABLE. + * @note ENABLE: Enable fast mode plus driving capability for selected I2C pin + * @note DISABLE: Disable fast mode plus driving capability for selected I2C pin + * @note For I2C1, fast mode plus driving capability can be enabled on all selected + * I2C1 pins using SYSCFG_I2CFastModePlus_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be enabled only by using SYSCFG_I2CFastModePlus_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be enabled + * only by using SYSCFG_I2CFastModePlus_I2C2 parameter. + * @retval None + */ +void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_I2C_FMP(SYSCFG_I2CFastModePlus)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable fast mode plus driving capability for selected pin */ + SYSCFG->CFGR1 |= (uint32_t)SYSCFG_I2CFastModePlus; + } + else + { + /* Disable fast mode plus driving capability for selected pin */ + SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_I2CFastModePlus); + } +} + +/** @brief select the modulation envelope source + * @param SYSCFG_IRDAEnv: select the envelope source. + * This parameter can be a value + * @arg SYSCFG_IRDA_ENV_SEL_TIM16 + * @arg SYSCFG_IRDA_ENV_SEL_USART1 + * @arg SYSCFG_IRDA_ENV_SEL_USART4 + * @retval None + */ +void SYSCFG_IRDAEnvSelection(uint32_t SYSCFG_IRDAEnv) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_IRDA_ENV(SYSCFG_IRDAEnv)); + + SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_IRDA_ENV_SEL); + SYSCFG->CFGR1 |= (SYSCFG_IRDAEnv); +} + +/** + * @brief Selects the GPIO pin used as EXTI Line. + * @param EXTI_PortSourceGPIOx: selects the GPIO port to be used as source + * for EXTI lines where x can be (A, B, C, D, E or F). + * @note GPIOE is available only for STM32F072. + * @note GPIOD is not available for STM32F031. + * @param EXTI_PinSourcex: specifies the EXTI line to be configured. + * @note This parameter can be EXTI_PinSourcex where x can be: + * For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF. + * For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF. + * For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF. + * @retval None + */ +void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex) +{ + uint32_t tmp = 0x00; + + /* Check the parameters */ + assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx)); + assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex)); + + tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)); + SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp; + SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03))); +} + +/** + * @brief check ISR wrapper: Allow to determine interrupt source per line . + * @param IT_Source: specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg ITLINE_EWDG EWDG has expired + * @arg ITLINE_PVDOUT Power voltage detection Interrupt + * @arg ITLINE_VDDIO2 VDDIO2 Interrupt + * @arg ITLINE_RTC_WAKEUP RTC WAKEUP -> exti[20] Interrupt + * @arg ITLINE_RTC_TSTAMP RTC Time Stamp -> exti[19] interrupt + * @arg ITLINE_RTC_ALRA RTC Alarm -> exti[17] interrupt + * @arg ITLINE_FLASH_ITF Flash ITF Interrupt + * @arg ITLINE_CRS CRS Interrupt + * @arg ITLINE_CLK_CTRL CLK Control Interrupt + * @arg ITLINE_EXTI0 External Interrupt 0 + * @arg ITLINE_EXTI1 External Interrupt 1 + * @arg ITLINE_EXTI2 External Interrupt 2 + * @arg ITLINE_EXTI3 External Interrupt 3 + * @arg ITLINE_EXTI4 External Interrupt 4 + * @arg ITLINE_EXTI5 External Interrupt 5 + * @arg ITLINE_EXTI6 External Interrupt 6 + * @arg ITLINE_EXTI7 External Interrupt 7 + * @arg ITLINE_EXTI8 External Interrupt 8 + * @arg ITLINE_EXTI9 External Interrupt 9 + * @arg ITLINE_EXTI10 External Interrupt 10 + * @arg ITLINE_EXTI11 External Interrupt 11 + * @arg ITLINE_EXTI12 External Interrupt 12 + * @arg ITLINE_EXTI13 External Interrupt 13 + * @arg ITLINE_EXTI14 External Interrupt 14 + * @arg ITLINE_EXTI15 External Interrupt 15 + * @arg ITLINE_TSC_EOA Touch control EOA Interrupt + * @arg ITLINE_TSC_MCE Touch control MCE Interrupt + * @arg ITLINE_DMA1_CH1 DMA1 Channel 1 Interrupt + * @arg ITLINE_DMA1_CH2 DMA1 Channel 2 Interrupt + * @arg ITLINE_DMA1_CH3 DMA1 Channel 3 Interrupt + * @arg ITLINE_DMA2_CH1 DMA2 Channel 1 Interrupt + * @arg ITLINE_DMA2_CH2 DMA2 Channel 2 Interrupt + * @arg ITLINE_DMA1_CH4 DMA1 Channel 4 Interrupt + * @arg ITLINE_DMA1_CH5 DMA1 Channel 5 Interrupt + * @arg ITLINE_DMA1_CH6 DMA1 Channel 6 Interrupt + * @arg ITLINE_DMA1_CH7 DMA1 Channel 7 Interrupt + * @arg ITLINE_DMA2_CH3 DMA2 Channel 3 Interrupt + * @arg ITLINE_DMA2_CH4 DMA2 Channel 4 Interrupt + * @arg ITLINE_DMA2_CH5 DMA2 Channel 5 Interrupt + * @arg ITLINE_ADC ADC Interrupt + * @arg ITLINE_COMP1 COMP1 Interrupt -> exti[21] + * @arg ITLINE_COMP2 COMP2 Interrupt -> exti[21] + * @arg ITLINE_TIM1_BRK TIM1 BRK Interrupt + * @arg ITLINE_TIM1_UPD TIM1 UPD Interrupt + * @arg ITLINE_TIM1_TRG TIM1 TRG Interrupt + * @arg ITLINE_TIM1_CCU TIM1 CCU Interrupt + * @arg ITLINE_TIM1_CC TIM1 CC Interrupt + * @arg ITLINE_TIM2 TIM2 Interrupt + * @arg ITLINE_TIM3 TIM3 Interrupt + * @arg ITLINE_DAC DAC Interrupt + * @arg ITLINE_TIM6 TIM6 Interrupt + * @arg ITLINE_TIM7 TIM7 Interrupt + * @arg ITLINE_TIM14 TIM14 Interrupt + * @arg ITLINE_TIM15 TIM15 Interrupt + * @arg ITLINE_TIM16 TIM16 Interrupt + * @arg ITLINE_TIM17 TIM17 Interrupt + * @arg ITLINE_I2C1 I2C1 Interrupt -> exti[23] + * @arg ITLINE_I2C2 I2C2 Interrupt + * @arg ITLINE_SPI1 I2C1 Interrupt -> exti[23] + * @arg ITLINE_SPI2 SPI1 Interrupt + * @arg ITLINE_USART1 USART1 GLB Interrupt -> exti[25] + * @arg ITLINE_USART2 USART2 GLB Interrupt -> exti[26] + * @arg ITLINE_USART3 USART3 Interrupt + * @arg ITLINE_USART4 USART4 Interrupt + * @arg ITLINE_USART5 USART5 Interrupt + * @arg ITLINE_USART6 USART6 Interrupt + * @arg ITLINE_USART7 USART7 Interrupt + * @arg ITLINE_USART8 USART8 Interrupt + * @arg ITLINE_CAN CAN Interrupt + * @arg ITLINE_CEC CEC Interrupt + * @retval The new state of IT_LINE_SR. + */ +uint32_t SYSCFG_GetPendingIT(uint32_t ITSourceLine) +{ + assert_param(IS_SYSCFG_ITLINE(ITSourceLine)); + return(SYSCFG->IT_LINE_SR[(ITSourceLine >> 0x18)] & (ITSourceLine & 0x00FFFFFF)); +} + +/** + * @brief Connect the selected parameter to the break input of TIM1. + * @note The selected configuration is locked and can be unlocked by system reset + * @param SYSCFG_Break: selects the configuration to be connected to break + * input of TIM1 + * This parameter can be any combination of the following values: + * @arg SYSCFG_Break_PVD: Connects the PVD event to the Break Input of TIM1,, not available for STM32F030 devices. + * @arg SYSCFG_Break_SRAMParity: Connects the SRAM_PARITY error signal to the Break Input of TIM1 . + * @arg SYSCFG_Break_Lockup: Connects Lockup output of CortexM0 to the break input of TIM1. + * @retval None + */ +void SYSCFG_BreakConfig(uint32_t SYSCFG_Break) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break)); + + SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break; +} + +/** + * @brief Checks whether the specified SYSCFG flag is set or not. + * @param SYSCFG_Flag: specifies the SYSCFG flag to check. + * This parameter can be one of the following values: + * @arg SYSCFG_FLAG_PE: SRAM parity error flag. + * @retval The new state of SYSCFG_Flag (SET or RESET). + */ +FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameter */ + assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag)); + + /* Check the status of the specified SPI flag */ + if ((SYSCFG->CFGR2 & SYSCFG_CFGR2_SRAM_PE) != (uint32_t)RESET) + { + /* SYSCFG_Flag is set */ + bitstatus = SET; + } + else + { + /* SYSCFG_Flag is reset */ + bitstatus = RESET; + } + /* Return the SYSCFG_Flag status */ + return bitstatus; +} + +/** + * @brief Clear the selected SYSCFG flag. + * @param SYSCFG_Flag: selects the flag to be cleared. + * This parameter can be any combination of the following values: + * @arg SYSCFG_FLAG_PE: SRAM parity error flag. + * @retval None + */ +void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag)); + + SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Flag; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_tim.c b/system/src/stm32f0-stdperiph/stm32f0xx_tim.c new file mode 100644 index 0000000..ddaab12 --- /dev/null +++ b/system/src/stm32f0-stdperiph/stm32f0xx_tim.c @@ -0,0 +1,3349 @@ +/** + ****************************************************************************** + * @file stm32f0xx_tim.c + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the TIM peripheral: + * + TimeBase management + * + Output Compare management + * + Input Capture management + * + Interrupts, DMA and flags management + * + Clocks management + * + Synchronization management + * + Specific interface management + * + Specific remapping management + * + * @verbatim + + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] This driver provides functions to configure and program the TIM + of all STM32F0xx devices These functions are split in 8 groups: + (#) TIM TimeBase management: this group includes all needed functions + to configure the TM Timebase unit: + (++) Set/Get Prescaler. + (++) Set/Get Autoreload. + (++) Counter modes configuration. + (++) Set Clock division. + (++) Select the One Pulse mode. + (++) Update Request Configuration. + (++) Update Disable Configuration. + (++) Auto-Preload Configuration. + (++) Enable/Disable the counter. + + (#) TIM Output Compare management: this group includes all needed + functions to configure the Capture/Compare unit used in Output + compare mode: + (++) Configure each channel, independently, in Output Compare mode. + (++) Select the output compare modes. + (++) Select the Polarities of each channel. + (++) Set/Get the Capture/Compare register values. + (++) Select the Output Compare Fast mode. + (++) Select the Output Compare Forced mode. + (++) Output Compare-Preload Configuration. + (++) Clear Output Compare Reference. + (++) Select the OCREF Clear signal. + (++) Enable/Disable the Capture/Compare Channels. + + (#) TIM Input Capture management: this group includes all needed + functions to configure the Capture/Compare unit used in + Input Capture mode: + (++) Configure each channel in input capture mode. + (++) Configure Channel1/2 in PWM Input mode. + (++) Set the Input Capture Prescaler. + (++) Get the Capture/Compare values. + + (#) Advanced-control timers (TIM1) specific features + (++) Configures the Break input, dead time, Lock level, the OSSI, + the OSSR State and the AOE(automatic output enable) + (++) Enable/Disable the TIM peripheral Main Outputs + (++) Select the Commutation event + (++) Set/Reset the Capture Compare Preload Control bit + + (#) TIM interrupts, DMA and flags management. + (++) Enable/Disable interrupt sources. + (++) Get flags status. + (++) Clear flags/ Pending bits. + (++) Enable/Disable DMA requests. + (++) Configure DMA burst mode. + (++) Select CaptureCompare DMA request. + + (#) TIM clocks management: this group includes all needed functions + to configure the clock controller unit: + (++) Select internal/External clock. + (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx. + + (#) TIM synchronization management: this group includes all needed. + functions to configure the Synchronization unit: + (++) Select Input Trigger. + (++) Select Output Trigger. + (++) Select Master Slave Mode. + (++) ETR Configuration when used as external trigger. + + (#) TIM specific interface management, this group includes all + needed functions to use the specific TIM interface: + (++) Encoder Interface Configuration. + (++) Select Hall Sensor. + + (#) TIM specific remapping management includes the Remapping + configuration of specific timers + +@endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_tim.h" +#include "stm32f0xx_rcc.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup TIM + * @brief TIM driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* ---------------------- TIM registers bit mask ------------------------ */ +#define SMCR_ETR_MASK ((uint16_t)0x00FF) +#define CCMR_OFFSET ((uint16_t)0x0018) +#define CCER_CCE_SET ((uint16_t)0x0001) +#define CCER_CCNE_SET ((uint16_t)0x0004) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup TIM_Private_Functions + * @{ + */ + +/** @defgroup TIM_Group1 TimeBase management functions + * @brief TimeBase management functions + * +@verbatim + =============================================================================== + ##### TimeBase management functions ##### + =============================================================================== + + *** TIM Driver: how to use it in Timing(Time base) Mode *** + =============================================================================== + [..] To use the Timer in Timing(Time base) mode, the following steps are + mandatory: + (#) Enable TIM clock using + RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function. + (#) Fill the TIM_TimeBaseInitStruct with the desired parameters. + (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure + the Time Base unit with the corresponding configuration. + (#) Enable the NVIC if you need to generate the update interrupt. + (#) Enable the corresponding interrupt using the function + TIM_ITConfig(TIMx, TIM_IT_Update). + (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. + [..] + (@) All other functions can be used seperatly to modify, if needed, + a specific feature of the Timer. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the TIMx peripheral registers to their default reset values. + * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM peripheral. + * @note TIM7 is applicable only for STM32F072 devices + * @note TIM6 is not applivable for STM32F031 devices. + * @note TIM2 is not applicable for STM32F030 devices. + * @retval None + * + */ +void TIM_DeInit(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + if (TIMx == TIM1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); + } + else if (TIMx == TIM2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); + } + else if (TIMx == TIM3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); + } + else if (TIMx == TIM6) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); + } + else if (TIMx == TIM7) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); + } + else if (TIMx == TIM14) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); + } + else if (TIMx == TIM15) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE); + } + else if (TIMx == TIM16) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE); + } + else + { + if (TIMx == TIM17) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE); + } + } + +} + +/** + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM + * peripheral. + * @note TIM7 is applicable only for STM32F072 devices + * @note TIM6 is not applivable for STM32F031 devices. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef + * structure that contains the configuration information for + * the specified TIM peripheral. + * @retval None + */ +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + uint16_t tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); + assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); + + tmpcr1 = TIMx->CR1; + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3)) + { + /* Select the Counter Mode */ + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; + } + + if(TIMx != TIM6) + { + /* Set the clock division */ + tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; + } + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; + + /* Set the Prescaler value */ + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if ((TIMx == TIM1) || (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler and the Repetition counter + values immediately */ + TIMx->EGR = TIM_PSCReloadMode_Immediate; +} + +/** + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure + * which will be initialized. + * @retval None + */ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + /* Set the default configuration */ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/** + * @brief Configures the TIMx Prescaler. + * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM peripheral. + * @note TIM7 is applicable only for STM32F072 devices + * @note TIM6 is not applivable for STM32F031 devices. + * @note TIM2 is not applicable for STM32F030 devices. + * @param Prescaler: specifies the Prescaler Register value + * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode + * This parameter can be one of the following values: + * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. + * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly. + * @retval None + */ +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); + + /* Set the Prescaler value */ + TIMx->PSC = Prescaler; + /* Set or reset the UG Bit */ + TIMx->EGR = TIM_PSCReloadMode; +} + +/** + * @brief Specifies the TIMx Counter Mode to be used. + * @param TIMx: where x can be 1, 2, or 3 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_CounterMode: specifies the Counter Mode to be used + * This parameter can be one of the following values: + * @arg TIM_CounterMode_Up: TIM Up Counting Mode + * @arg TIM_CounterMode_Down: TIM Down Counting Mode + * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 + * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 + * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 + * @retval None + */ +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) +{ + uint16_t tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); + + tmpcr1 = TIMx->CR1; + /* Reset the CMS and DIR Bits */ + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); + /* Set the Counter Mode */ + tmpcr1 |= TIM_CounterMode; + /* Write to TIMx CR1 register */ + TIMx->CR1 = tmpcr1; +} + +/** + * @brief Sets the TIMx Counter Register value + * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM + * peripheral. + * @note TIM7 is applicable only for STM32F072 devices + * @note TIM6 is not applivable for STM32F031 devices. + * @note TIM2 is not applicable for STM32F030 devices. + * @param Counter: specifies the Counter register new value. + * @retval None + */ +void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Set the Counter Register value */ + TIMx->CNT = Counter; +} + +/** + * @brief Sets the TIMx Autoreload Register value + * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM peripheral. + * @note TIM7 is applicable only for STM32F072 devices + * @note TIM6 is not applivable for STM32F031 devices. + * @note TIM2 is not applicable for STM32F030 devices. + * @param Autoreload: specifies the Autoreload register new value. + * @retval None + */ +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Set the Autoreload Register value */ + TIMx->ARR = Autoreload; +} + +/** + * @brief Gets the TIMx Counter value. + * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM + * peripheral. + * @note TIM7 is applicable only for STM32F072 devices + * @note TIM6 is not applivable for STM32F031 devices. + * @note TIM2 is not applicable for STM32F030 devices. + * @retval Counter Register value. + */ +uint32_t TIM_GetCounter(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Get the Counter Register value */ + return TIMx->CNT; +} + +/** + * @brief Gets the TIMx Prescaler value. + * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM + * peripheral. + * @note TIM7 is applicable only for STM32F072 devices + * @note TIM6 is not applivable for STM32F031 devices. + * @note TIM2 is not applicable for STM32F030 devices. + * @retval Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Get the Prescaler Register value */ + return TIMx->PSC; +} + +/** + * @brief Enables or Disables the TIMx Update event. + * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM + * peripheral. + * @note TIM7 is applicable only for STM32F072 devices + * @note TIM6 is not applivable for STM32F031 devices. + * @note TIM2 is not applicable for STM32F030 devices. + * @param NewState: new state of the TIMx UDIS bit + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the Update Disable Bit */ + TIMx->CR1 |= TIM_CR1_UDIS; + } + else + { + /* Reset the Update Disable Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS); + } +} + +/** + * @brief Configures the TIMx Update Request Interrupt source. + * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM + * peripheral. + * @note TIM7 is applicable only for STM32F072 devices + * @note TIM6 is not applivable for STM32F031 devices. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_UpdateSource: specifies the Update source. + * This parameter can be one of the following values: + * @arg TIM_UpdateSource_Regular: Source of update is the counter + * overflow/underflow or the setting of UG bit, or an update + * generation through the slave mode controller. + * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow. + * @retval None + */ +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); + + if (TIM_UpdateSource != TIM_UpdateSource_Global) + { + /* Set the URS Bit */ + TIMx->CR1 |= TIM_CR1_URS; + } + else + { + /* Reset the URS Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS); + } +} + +/** + * @brief Enables or disables TIMx peripheral Preload register on ARR. + * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM + * peripheral. + * @note TIM7 is applicable only for STM32F072 devices + * @note TIM6 is not applivable for STM32F031 devices. + * @note TIM2 is not applicable for STM32F030 devices. + * @param NewState: new state of the TIMx peripheral Preload register + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the ARR Preload Bit */ + TIMx->CR1 |= TIM_CR1_ARPE; + } + else + { + /* Reset the ARR Preload Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE); + } +} + +/** + * @brief Selects the TIMx's One Pulse Mode. + * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM + * peripheral. + * @note TIM7 is applicable only for STM32F072 devices + * @note TIM6 is not applivable for STM32F031 devices. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_OPMode: specifies the OPM Mode to be used. + * This parameter can be one of the following values: + * @arg TIM_OPMode_Single + * @arg TIM_OPMode_Repetitive + * @retval None + */ +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); + + /* Reset the OPM Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM); + /* Configure the OPM Mode */ + TIMx->CR1 |= TIM_OPMode; +} + +/** + * @brief Sets the TIMx Clock Division value. + * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_CKD: specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CKD_DIV1: TDTS = Tck_tim + * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim + * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim + * @retval None + */ +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_CKD_DIV(TIM_CKD)); + + /* Reset the CKD Bits */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD); + /* Set the CKD value */ + TIMx->CR1 |= TIM_CKD; +} + +/** + * @brief Enables or disables the specified TIM peripheral. + * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17to select the TIMx + * peripheral. + * @note TIM7 is applicable only for STM32F072 devices + * @note TIM6 is not applivable for STM32F031 devices. + * @note TIM2 is not applicable for STM32F030 devices. + * @param NewState: new state of the TIMx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TIM Counter */ + TIMx->CR1 |= TIM_CR1_CEN; + } + else + { + /* Disable the TIM Counter */ + TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN)); + } +} + +/** + * @} + */ + +/** @defgroup TIM_Group2 Advanced-control timers (TIM1) specific features + * @brief Advanced-control timers (TIM1) specific features + * +@verbatim + =============================================================================== + ##### Advanced-control timers (TIM1) specific features ##### + =============================================================================== + + =================================================================== + *** TIM Driver: how to use the Break feature *** + =================================================================== + [..] After configuring the Timer channel(s) in the appropriate Output Compare mode: + + (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer + Break Polarity, dead time, Lock level, the OSSI/OSSR State and the + AOE(automatic output enable). + + (#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer + + (#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) + + (#) Once the break even occurs, the Timer's output signals are put in reset + state or in a known state (according to the configuration made in + TIM_BDTRConfig() function). + +@endverbatim + * @{ + */ +/** + * @brief Configures the: Break feature, dead time, Lock level, OSSI/OSSR State + * and the AOE(automatic output enable). + * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM + * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @retval None + */ +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); + assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); + assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); + assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); + assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); + /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; +} + +/** + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which + * will be initialized. + * @retval None + */ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/** + * @brief Enables or disables the TIM peripheral Main Outputs. + * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIMx peripheral. + * @param NewState: new state of the TIM peripheral Main Outputs. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the TIM Main Output */ + TIMx->BDTR |= TIM_BDTR_MOE; + } + else + { + /* Disable the TIM Main Output */ + TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE)); + } +} + +/** + * @} + */ + +/** @defgroup TIM_Group3 Output Compare management functions + * @brief Output Compare management functions + * +@verbatim + =============================================================================== + ##### Output Compare management functions ##### + =============================================================================== + *** TIM Driver: how to use it in Output Compare Mode *** + =============================================================================== + [..] To use the Timer in Output Compare mode, the following steps are mandatory: + (#) Enable TIM clock using + RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function. + (#) Configure the TIM pins by configuring the corresponding GPIO pins + (#) Configure the Time base unit as described in the first part of this + driver, if needed, else the Timer will run with the default + configuration: + (++) Autoreload value = 0xFFFF. + (++) Prescaler value = 0x0000. + (++) Counter mode = Up counting. + (++) Clock Division = TIM_CKD_DIV1. + (#) Fill the TIM_OCInitStruct with the desired parameters including: + (++) The TIM Output Compare mode: TIM_OCMode. + (++) TIM Output State: TIM_OutputState. + (++) TIM Pulse value: TIM_Pulse. + (++) TIM Output Compare Polarity : TIM_OCPolarity. + (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired + channel with the corresponding configuration. + (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. + [..] + (@) All other functions can be used separately to modify, if needed, + a specific feature of the Timer. + (@) In case of PWM mode, this function is mandatory: + TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE). + (@) If the corresponding interrupt or DMA request are needed, the user should: + (#@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). + (#@) Enable the corresponding interrupt (or DMA request) using the function + TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)). + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIMx Channel1 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM + * peripheral. + * @retval None + */ +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E); + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S)); + + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P)); + /* Set the Output Compare Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + + /* Set the Output State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + if((TIMx == TIM1) || (TIMx == TIM15) || (TIMx == TIM16) || (TIMx == TIM17)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP)); + /* Set the Output N Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + + /* Reset the Output N State */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE)); + /* Set the Output N State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + + /* Reset the Ouput Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N)); + + /* Set the Output Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel2 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM + * peripheral. + * @retval None + */ +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + if((TIMx == TIM1) || (TIMx == TIM15)) + { + /* Check the parameters */ + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Ouput Compare State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2)); + + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + + if (TIMx == TIM1) + { + /* Check the parameters */ + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP)); + /* Set the Output N Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + + /* Reset the Output N State */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE)); + /* Set the Output N State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + + /* Reset the Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N)); + + /* Set the Output N Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel3 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM + * peripheral. + * @retval None + */ +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S)); + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + if(TIMx == TIM1) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP)); + /* Set the Output N Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + /* Reset the Output N State */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE)); + + /* Set the Output N State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + /* Reset the Ouput Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N)); + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + /* Set the Output N Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel4 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM + * peripheral. + * @retval None + */ +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC4E Bit */ + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + if(TIMx == TIM1) + { + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + /* Reset the Ouput Compare IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4)); + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Fills each TIM_OCInitStruct member with its default value. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will + * be initialized. + * @retval None + */ +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + /* Set the default configuration */ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x0000000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/** + * @brief Selects the TIM Output Compare Mode. + * @note This function disables the selected channel before changing the Output + * Compare Mode. + * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions. + * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_Channel_4: TIM Channel 4 + * @param TIM_OCMode: specifies the TIM Output Compare Mode. + * This parameter can be one of the following values: + * @arg TIM_OCMode_Timing + * @arg TIM_OCMode_Active + * @arg TIM_OCMode_Toggle + * @arg TIM_OCMode_PWM1 + * @arg TIM_OCMode_PWM2 + * @arg TIM_ForcedAction_Active + * @arg TIM_ForcedAction_InActive + * @retval None + */ +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OCM(TIM_OCMode)); + + tmp = (uint32_t) TIMx; + tmp += CCMR_OFFSET; + + tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel; + + /* Disable the Channel: Reset the CCxE Bit */ + TIMx->CCER &= (uint16_t) ~tmp1; + + if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) + { + tmp += (TIM_Channel>>1); + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M); + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp |= TIM_OCMode; + } + else + { + tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M); + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); + } +} + +/** + * @brief Sets the TIMx Capture Compare1 Register value + * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param Compare1: specifies the Capture Compare1 register new value. + * @retval None + */ +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + + /* Set the Capture Compare1 Register value */ + TIMx->CCR1 = Compare1; +} + +/** + * @brief Sets the TIMx Capture Compare2 Register value + * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param Compare2: specifies the Capture Compare2 register new value. + * @retval None + */ +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + + /* Set the Capture Compare2 Register value */ + TIMx->CCR2 = Compare2; +} + +/** + * @brief Sets the TIMx Capture Compare3 Register value + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @param Compare3: specifies the Capture Compare3 register new value. + * @retval None + */ +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Set the Capture Compare3 Register value */ + TIMx->CCR3 = Compare3; +} + +/** + * @brief Sets the TIMx Capture Compare4 Register value + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param Compare4: specifies the Capture Compare4 register new value. + * @retval None + */ +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Set the Capture Compare4 Register value */ + TIMx->CCR4 = Compare4; +} + +/** + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC1REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. + * @retval None + */ +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1M Bits */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M); + /* Configure The Forced output Mode */ + tmpccmr1 |= TIM_ForcedAction; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC2REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. + * @retval None + */ +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2M Bits */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M); + /* Configure The Forced output Mode */ + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC3REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. + * @retval None + */ +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC1M Bits */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M); + /* Configure The Forced output Mode */ + tmpccmr2 |= TIM_ForcedAction; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC4REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. + * @retval None + */ +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC2M Bits */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M); + /* Configure The Forced output Mode */ + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. + * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIMx peripheral + * @note TIM2 is not applicable for STM32F030 devices. + * @param NewState: new state of the Capture Compare Preload Control bit + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the CCPC Bit */ + TIMx->CR2 |= TIM_CR2_CCPC; + } + else + { + /* Reset the CCPC Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC); + } +} + + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR1. + * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1PE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= TIM_OCPreload; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR2. + * @param TIMx: where x can be 1, 2, 3 and 15 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2PE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR3. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3PE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= TIM_OCPreload; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR4. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4PE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 1 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1FE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= TIM_OCFast; + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 2 Fast feature. + * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2FE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 3 Fast feature. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3FE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= TIM_OCFast; + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 4 Fast feature. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4FE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF1 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1CE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= TIM_OCClear; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF2 signal on an external event + * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2CE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF3 signal on an external event + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3CE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= TIM_OCClear; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF4 signal on an external event + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4CE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx channel 1 polarity. + * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_OCPolarity: specifies the OC1 Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC1P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P); + tmpccer |= TIM_OCPolarity; + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 1N polarity. + * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC1N Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC1NP Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP); + tmpccer |= TIM_OCNPolarity; + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 2 polarity. + * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_OCPolarity: specifies the OC2 Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC2P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 4); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 2N polarity. + * @param TIMx: where x can be 1 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC2N Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC2NP Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 3 polarity. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_OCPolarity: specifies the OC3 Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC3P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 8); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 3N polarity. + * @param TIMx: where x can be 1 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC3N Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC3NP Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 4 polarity. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_OCPolarity: specifies the OC4 Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC4P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 12); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Selects the OCReference Clear source. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_OCReferenceClear: specifies the OCReference Clear source. + * This parameter can be one of the following values: + * @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF. + * @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input. + * @retval None + */ +void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear)); + + /* Set the TIM_OCReferenceClear source */ + TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS); + TIMx->SMCR |= TIM_OCReferenceClear; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_Channel_4: TIM Channel 4 + * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. + * @retval None + */ +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_CCX(TIM_CCx)); + + tmp = CCER_CCE_SET << TIM_Channel; + + /* Reset the CCxE Bit */ + TIMx->CCER &= (uint16_t)~ tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parmeter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. + * @retval None + */ +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_CCXN(TIM_CCxN)); + + tmp = CCER_CCNE_SET << TIM_Channel; + + /* Reset the CCxNE Bit */ + TIMx->CCER &= (uint16_t) ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +} + +/** + * @brief Selects the TIM peripheral Commutation event. + * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIMx peripheral + * @param NewState: new state of the Commutation event. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the COM Bit */ + TIMx->CR2 |= TIM_CR2_CCUS; + } + else + { + /* Reset the COM Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS); + } +} + +/** + * @} + */ + +/** @defgroup TIM_Group4 Input Capture management functions + * @brief Input Capture management functions + * +@verbatim + =============================================================================== + ##### Input Capture management functions ##### + =============================================================================== + + *** TIM Driver: how to use it in Input Capture Mode *** + =============================================================================== + [..] To use the Timer in Input Capture mode, the following steps are mandatory: + (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) + function. + (#) Configure the TIM pins by configuring the corresponding GPIO pins. + (#) Configure the Time base unit as described in the first part of this + driver, if needed, else the Timer will run with the default configuration: + (++) Autoreload value = 0xFFFF. + (++) Prescaler value = 0x0000. + (++) Counter mode = Up counting. + (++) Clock Division = TIM_CKD_DIV1. + (#) Fill the TIM_ICInitStruct with the desired parameters including: + (++) TIM Channel: TIM_Channel. + (++) TIM Input Capture polarity: TIM_ICPolarity. + (++) TIM Input Capture selection: TIM_ICSelection. + (++) TIM Input Capture Prescaler: TIM_ICPrescaler. + (++) TIM Input CApture filter value: TIM_ICFilter. + (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired + channel with the corresponding configuration and to measure only + frequency or duty cycle of the input signal,or, Call + TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired + channels with the corresponding configuration and to measure the + frequency and the duty cycle of the input signal. + (#) Enable the NVIC or the DMA to read the measured frequency. + (#) Enable the corresponding interrupt (or DMA request) to read + the Captured value, using the function TIM_ITConfig(TIMx, TIM_IT_CCx) + (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)). + (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. + (#) Use TIM_GetCapturex(TIMx); to read the captured value. + [..] + (@) All other functions can be used separately to modify, if needed, + a specific feature of the Timer. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct. + * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure + * that contains the configuration information for the specified TIM + * peripheral. + * @retval None + */ +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); + assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); + assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); + + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* TI3 Configuration */ + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* TI4 Configuration */ + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** + * @brief Fills each TIM_ICInitStruct member with its default value. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will + * be initialized. + * @retval None + */ +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/** + * @brief Configures the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct to measure an external PWM signal. + * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure + * that contains the configuration information for the specified TIM + * peripheral. + * @retval None + */ +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_ICPolarity_Rising; + uint16_t icoppositeselection = TIM_ICSelection_DirectTI; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* Select the Opposite Input Polarity */ + if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + /* Select the Opposite Input */ + if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI2 Configuration */ + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI1 Configuration */ + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** + * @brief Gets the TIMx Input Capture 1 value. + * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @retval Capture Compare 1 Register value. + */ +uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + + /* Get the Capture 1 Register value */ + return TIMx->CCR1; +} + +/** + * @brief Gets the TIMx Input Capture 2 value. + * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. + * @retval Capture Compare 2 Register value. + */ +uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + + /* Get the Capture 2 Register value */ + return TIMx->CCR2; +} + +/** + * @brief Gets the TIMx Input Capture 3 value. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @retval Capture Compare 3 Register value. + */ +uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Get the Capture 3 Register value */ + return TIMx->CCR3; +} + +/** + * @brief Gets the TIMx Input Capture 4 value. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @retval Capture Compare 4 Register value. + */ +uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Get the Capture 4 Register value */ + return TIMx->CCR4; +} + +/** + * @brief Sets the TIMx Input Capture 1 prescaler. + * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC1PSC Bits */ + TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC); + /* Set the IC1PSC value */ + TIMx->CCMR1 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 2 prescaler. + * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC2PSC Bits */ + TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC); + /* Set the IC2PSC value */ + TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** + * @brief Sets the TIMx Input Capture 3 prescaler. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC3PSC Bits */ + TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC); + /* Set the IC3PSC value */ + TIMx->CCMR2 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 4 prescaler. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC4PSC Bits */ + TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC); + /* Set the IC4PSC value */ + TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** + * @} + */ + +/** @defgroup TIM_Group5 Interrupts DMA and flags management functions + * @brief Interrupts, DMA and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts, DMA and flags management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified TIM interrupts. + * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIMx peripheral. + * @note TIM7 is applicable only for STM32F072 devices + * @note TIM6 is not applivable for STM32F031 devices. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg TIM_IT_Update: TIM update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * + * @note TIM6 and TIM7 can only generate an update interrupt. + * @note TIM15 can have only TIM_IT_Update, TIM_IT_CC1,TIM_IT_CC2 or TIM_IT_Trigger. + * @note TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. + * @note TIM_IT_Break is used only with TIM1 and TIM15. + * @note TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17. + * + * @param NewState: new state of the TIM interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_IT(TIM_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Interrupt sources */ + TIMx->DIER |= TIM_IT; + } + else + { + /* Disable the Interrupt sources */ + TIMx->DIER &= (uint16_t)~TIM_IT; + } +} + +/** + * @brief Configures the TIMx event to be generate by software. + * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the + * TIM peripheral. + * @note TIM7 is applicable only for STM32F072 devices + * @note TIM6 is not applivable for STM32F031 devices. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_EventSource: specifies the event source. + * This parameter can be one or more of the following values: + * @arg TIM_EventSource_Update: Timer update Event source + * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EventSource_COM: Timer COM event source + * @arg TIM_EventSource_Trigger: Timer Trigger Event source + * @arg TIM_EventSource_Break: Timer Break event source + * + * @note TIM6 and TIM7 can only generate an update event. + * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1. + * + * @retval None + */ +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); + /* Set the event sources */ + TIMx->EGR = TIM_EventSource; +} + +/** + * @brief Checks whether the specified TIM flag is set or not. + * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral. + * @note TIM7 is applicable only for STM32F072 devices + * @note TIM6 is not applivable for STM32F031 devices. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_Update: TIM update Flag + * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM: TIM Commutation Flag + * @arg TIM_FLAG_Trigger: TIM Trigger Flag + * @arg TIM_FLAG_Break: TIM Break Flag + * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag + * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag + * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag + * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag + * + * @note TIM6 and TIM7 can have only one update flag. + * @note TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, TIM_FLAG_CC2 or TIM_FLAG_Trigger. + * @note TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. + * @note TIM_FLAG_Break is used only with TIM1 and TIM15. + * @note TIM_FLAG_COM is used only with TIM1 TIM15, TIM16 and TIM17. + * + * @retval The new state of TIM_FLAG (SET or RESET). + */ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); + + if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's pending flags. + * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral. + * @note TIM7 is applicable only for STM32F072 devices + * @note TIM6 is not applivable for STM32F031 devices. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_FLAG: specifies the flag bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_FLAG_Update: TIM update Flag + * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM: TIM Commutation Flag + * @arg TIM_FLAG_Trigger: TIM Trigger Flag + * @arg TIM_FLAG_Break: TIM Break Flag + * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag + * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag + * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag + * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag + * + * @note TIM6 and TIM7 can have only one update flag. + * @note TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,TIM_FLAG_CC2 or + * TIM_FLAG_Trigger. + * @note TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. + * @note TIM_FLAG_Break is used only with TIM1 and TIM15. + * @note TIM_FLAG_COM is used only with TIM1, TIM15, TIM16 and TIM17. + * + * @retval None + */ +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG)); + + /* Clear the flags */ + TIMx->SR = (uint16_t)~TIM_FLAG; +} + +/** + * @brief Checks whether the TIM interrupt has occurred or not. + * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral. + * @note TIM7 is applicable only for STM32F072 devices + * @note TIM6 is not applivable for STM32F031 devices. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_IT: specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_Update: TIM update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * + * @note TIM6 and TIM7 can generate only an update interrupt. + * @note TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. + * @note TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. + * @note TIM_IT_Break is used only with TIM1 and TIM15. + * @note TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17. + * + * @retval The new state of the TIM_IT(SET or RESET). + */ +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itstatus = 0x0, itenable = 0x0; + + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_IT(TIM_IT)); + + itstatus = TIMx->SR & TIM_IT; + + itenable = TIMx->DIER & TIM_IT; + if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's interrupt pending bits. + * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral. + * @note TIM7 is applicable only for STM32F072 devices + * @note TIM6 is not applivable for STM32F031 devices. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_IT: specifies the pending bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_IT_Update: TIM1 update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * + * @note TIM6 and TIM7 can generate only an update interrupt. + * @note TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. + * @note TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. + * @note TIM_IT_Break is used only with TIM1 and TIM15. + * @note TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17. + * + * @retval None + */ +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_IT(TIM_IT)); + + /* Clear the IT pending Bit */ + TIMx->SR = (uint16_t)~TIM_IT; +} + +/** + * @brief Configures the TIMx's DMA interface. + * @param TIMx: where x can be 1, 2, 3, 15, 16 or 17 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_DMABase: DMA Base address. + * This parameter can be one of the following values: + * @arg TIM_DMABase_CR1 + * @arg TIM_DMABase_CR2 + * @arg TIM_DMABase_SMCR + * @arg TIM_DMABase_DIER + * @arg TIM_DMABase_SR + * @arg TIM_DMABase_EGR + * @arg TIM_DMABase_CCMR1 + * @arg TIM_DMABase_CCMR2 + * @arg TIM_DMABase_CCER + * @arg TIM_DMABase_CNT + * @arg TIM_DMABase_PSC + * @arg TIM_DMABase_ARR + * @arg TIM_DMABase_CCR1 + * @arg TIM_DMABase_CCR2 + * @arg TIM_DMABase_CCR3 + * @arg TIM_DMABase_CCR4 + * @arg TIM_DMABase_DCR + * @arg TIM_DMABase_OR + * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value + * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. + * @retval None + */ +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); + assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); + /* Set the DMA Base and the DMA Burst Length */ + TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; +} + +/** + * @brief Enables or disables the TIMx's DMA Requests. + * @param TIMx: where x can be 1, 2, 3, 6, 7, 15, 16 or 17 to select the TIM peripheral. + * @note TIM7 is applicable only for STM32F072 devices + * @note TIM6 is not applivable for STM32F031 devices. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_DMASource: specifies the DMA Request sources. + * This parameter can be any combination of the following values: + * @arg TIM_DMA_Update: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_Trigger: TIM Trigger DMA source + * @param NewState: new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST10_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA sources */ + TIMx->DIER |= TIM_DMASource; + } + else + { + /* Disable the DMA sources */ + TIMx->DIER &= (uint16_t)~TIM_DMASource; + } +} + +/** + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * @param TIMx: where x can be 1, 2, 3, 15, 16 or 17 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param NewState: new state of the Capture Compare DMA source + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the CCDS Bit */ + TIMx->CR2 |= TIM_CR2_CCDS; + } + else + { + /* Reset the CCDS Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS); + } +} + +/** + * @} + */ + +/** @defgroup TIM_Group6 Clocks management functions + * @brief Clocks management functions + * +@verbatim + =============================================================================== + ##### Clocks management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the TIMx internal Clock + * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @retval None + */ +void TIM_InternalClockConfig(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); +} + +/** + * @brief Configures the TIMx Internal Trigger as External Clock + * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_ITRSource: Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @retval None + */ +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); + /* Select the Internal Trigger */ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** + * @brief Configures the TIMx Trigger as External Clock + * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_TIxExternalCLKSource: Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector + * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 + * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 + * @param TIM_ICPolarity: specifies the TIx Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param ICFilter: specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + * @retval None + */ +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); + assert_param(IS_TIM_IC_FILTER(ICFilter)); + + /* Configure the Timer Input Clock Source */ + if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + /* Select the Trigger source */ + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** + * @brief Configures the External clock Mode1 + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the SMS Bits */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); + /* Select the External clock mode1 */ + tmpsmcr |= TIM_SlaveMode_External1; + /* Select the Trigger selection : ETRF */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); + tmpsmcr |= TIM_TS_ETRF; + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Configures the External clock Mode2 + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + /* Enable the External clock mode2 */ + TIMx->SMCR |= TIM_SMCR_ECE; +} + +/** + * @} + */ + +/** @defgroup TIM_Group7 Synchronization management functions + * @brief Synchronization management functions + * +@verbatim + =============================================================================== + ##### Synchronization management functions ##### + =============================================================================== + *** TIM Driver: how to use it in synchronization Mode *** + =============================================================================== + [..] Case of two/several Timers + (#) Configure the Master Timers using the following functions: + (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, + uint16_t TIM_TRGOSource). + (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, + uint16_t TIM_MasterSlaveMode); + (#) Configure the Slave Timers using the following functions: + (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, + uint16_t TIM_InputTriggerSource); + (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); + [..] Case of Timers and external trigger(ETR pin) + (#) Configure the Etrenal trigger using this function: + (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); + (#) Configure the Slave Timers using the following functions: + (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, + uint16_t TIM_InputTriggerSource); + (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); + +@endverbatim + * @{ + */ +/** + * @brief Selects the Input Trigger source + * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_InputTriggerSource: The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); + /* Set the Input Trigger source */ + tmpsmcr |= TIM_InputTriggerSource; + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Selects the TIMx Trigger Output Mode. + * @param TIMx: where x can be 1, 2, 3, 6, 7, or 15 to select the TIM peripheral. + * @note TIM7 is applicable only for STM32F072 devices + * @note TIM6 is not applivable for STM32F031 devices. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_TRGOSource: specifies the Trigger Output source. + * This parameter can be one of the following values: + * + * - For all TIMx + * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO). + * + * - For all TIMx except TIM6 and TIM7 + * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag + * is to be set, as soon as a capture or compare match occurs (TRGO). + * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO). + * + * @retval None + */ +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST9_PERIPH(TIMx)); + assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); + + /* Reset the MMS Bits */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS); + /* Select the TRGO source */ + TIMx->CR2 |= TIM_TRGOSource; +} + +/** + * @brief Selects the TIMx Slave Mode. + * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_SlaveMode: specifies the Timer Slave Mode. + * This parameter can be one of the following values: + * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes + * the counter and triggers an update of the registers. + * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high. + * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI. + * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter. + * @retval None + */ +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); + + /* Reset the SMS Bits */ + TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS); + /* Select the Slave Mode */ + TIMx->SMCR |= TIM_SlaveMode; +} + +/** + * @brief Sets or Resets the TIMx Master/Slave Mode. + * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. + * This parameter can be one of the following values: + * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer + * and its slaves (through TRGO). + * @arg TIM_MasterSlaveMode_Disable: No action + * @retval None + */ +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); + + /* Reset the MSM Bit */ + TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM); + + /* Set or Reset the MSM Bit */ + TIMx->SMCR |= TIM_MasterSlaveMode; +} + +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + + tmpsmcr = TIMx->SMCR; + /* Reset the ETR Bits */ + tmpsmcr &= SMCR_ETR_MASK; + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @} + */ + +/** @defgroup TIM_Group8 Specific interface management functions + * @brief Specific interface management functions + * +@verbatim + =============================================================================== + ##### Specific interface management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the TIMx Encoder Interface. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. + * This parameter can be one of the following values: + * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. + * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. + * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending + * on the level of the other input. + * @param TIM_IC1Polarity: specifies the IC1 Polarity + * This parmeter can be one of the following values: + * @arg TIM_ICPolarity_Falling: IC Falling edge. + * @arg TIM_ICPolarity_Rising: IC Rising edge. + * @param TIM_IC2Polarity: specifies the IC2 Polarity + * This parmeter can be one of the following values: + * @arg TIM_ICPolarity_Falling: IC Falling edge. + * @arg TIM_ICPolarity_Rising: IC Rising edge. + * @retval None + */ +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Set the encoder Mode */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); + tmpsmcr |= TIM_EncoderMode; + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S))); + tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)) & (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP)); + tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Enables or disables the TIMx's Hall sensor interface. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param NewState: new state of the TIMx Hall sensor interface. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the TI1S Bit */ + TIMx->CR2 |= TIM_CR2_TI1S; + } + else + { + /* Reset the TI1S Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S); + } +} + +/** + * @} + */ + +/** @defgroup TIM_Group9 Specific remapping management function + * @brief Specific remapping management function + * +@verbatim + =============================================================================== + ##### Specific remapping management function ##### + =============================================================================== + +@endverbatim + * @{ + */ +/** + * @brief Configures the TIM14 Remapping input Capabilities. + * @param TIMx: where x can be 14 to select the TIM peripheral. + * @param TIM_Remap: specifies the TIM input reampping source. + * This parameter can be one of the following values: + * @arg TIM14_GPIO: TIM14 Channel 1 is connected to GPIO. + * @arg TIM14_RTC_CLK: TIM14 Channel 1 is connected to RTC input clock. + * RTC input clock can be LSE, LSI or HSE/div128. + * @arg TIM14_HSE_DIV32: TIM14 Channel 1 is connected to HSE/32 clock. + * @arg TIM14_MCO: TIM14 Channel 1 is connected to MCO clock. + * MCO clock can be HSI14, SYSCLK, HSI, HSE or PLL/2. + * @retval None + */ +void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST11_PERIPH(TIMx)); + assert_param(IS_TIM_REMAP(TIM_Remap)); + + /* Set the Timer remapping configuration */ + TIMx->OR = TIM_Remap; +} + +/** + * @} + */ + +/** + * @brief Configure the TI1 as Input. + * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_ICPolarity: The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0; + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E); + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + /* Select the Input and set the filter */ + tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F))); + tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_ICPolarity: The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E); + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 4); + /* Select the Input and set the filter */ + tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F))); + tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); + tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_ICPolarity: The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E); + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 8); + /* Select the Input and set the filter */ + tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @note TIM2 is not applicable for STM32F030 devices. + * @param TIM_ICPolarity: The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E); + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 12); + /* Select the Input and set the filter */ + tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P | TIM_CCER_CC4NP)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_usart.c b/system/src/stm32f0-stdperiph/stm32f0xx_usart.c new file mode 100644 index 0000000..5c05899 --- /dev/null +++ b/system/src/stm32f0-stdperiph/stm32f0xx_usart.c @@ -0,0 +1,2168 @@ +/** + ****************************************************************************** + * @file stm32f0xx_usart.c + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Universal synchronous asynchronous receiver + * transmitter (USART): + * + Initialization and Configuration + * + STOP Mode + * + AutoBaudRate + * + Data transfers + * + Multi-Processor Communication + * + LIN mode + * + Half-duplex mode + * + Smartcard mode + * + IrDA mode + * + RS485 mode + * + DMA transfers management + * + Interrupts and flags management + * + * @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE) + function for USART1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE) + function for USART2 and USART3. + (#) According to the USART mode, enable the GPIO clocks using + RCC_AHBPeriphClockCmd() function. (The I/O can be TX, RX, CTS, + or and SCLK). + (#) Peripheral's alternate function: + (++) Connect the pin to the desired peripherals' Alternate + Function (AF) using GPIO_PinAFConfig() function. + (++) Configure the desired pin in alternate function by: + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF. + (++) Select the type, pull-up/pull-down and output speed via + GPIO_PuPd, GPIO_OType and GPIO_Speed members. + (++) Call GPIO_Init() function. + (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware + flow control and Mode(Receiver/Transmitter) using the SPI_Init() + function. + (#) For synchronous mode, enable the clock and program the polarity, + phase and last bit using the USART_ClockInit() function. + (#) Enable the NVIC and the corresponding interrupt using the function + USART_ITConfig() if you need to use interrupt mode. + (#) When using the DMA mode: + (++) Configure the DMA using DMA_Init() function. + (++) Active the needed channel Request using USART_DMACmd() function. + (#) Enable the USART using the USART_Cmd() function. + (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode. + [..] + Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections + for more details. + +@endverbatim + + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_usart.h" +#include "stm32f0xx_rcc.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup USART + * @brief USART driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/*!< USART CR1 register clear Mask ((~(uint32_t)0xFFFFE6F3)) */ +#define CR1_CLEAR_MASK ((uint32_t)(USART_CR1_M | USART_CR1_PCE | \ + USART_CR1_PS | USART_CR1_TE | \ + USART_CR1_RE)) + +/*!< USART CR2 register clock bits clear Mask ((~(uint32_t)0xFFFFF0FF)) */ +#define CR2_CLOCK_CLEAR_MASK ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \ + USART_CR2_CPHA | USART_CR2_LBCL)) + +/*!< USART CR3 register clear Mask ((~(uint32_t)0xFFFFFCFF)) */ +#define CR3_CLEAR_MASK ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) + +/*!< USART Interrupts mask */ +#define IT_MASK ((uint32_t)0x000000FF) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup USART_Private_Functions + * @{ + */ + +/** @defgroup USART_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USART + in asynchronous and in synchronous modes. + (+) For the asynchronous mode only these parameters can be configured: + (++) Baud Rate. + (++) Word Length. + (++) Stop Bit. + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + the possible USART frame formats are as listed in the following table: + + +-------------------------------------------------------------+ + | M bit | PCE bit | USART frame | + |---------------------|---------------------------------------| + | 0 | 0 | | SB | 8 bit data | STB | | + |---------|-----------|---------------------------------------| + | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|-----------|---------------------------------------| + | 1 | 0 | | SB | 9 bit data | STB | | + |---------|-----------|---------------------------------------| + | 1 | 1 | | SB | 8 bit data | PB | STB | | + +-------------------------------------------------------------+ + + (++) Hardware flow control. + (++) Receiver/transmitter modes. + [..] The USART_Init() function follows the USART asynchronous configuration + procedure(details for the procedure are available in reference manual. + (+) For the synchronous mode in addition to the asynchronous mode parameters + these parameters should be also configured: + (++) USART Clock Enabled. + (++) USART polarity. + (++) USART phase. + (++) USART LastBit. + [..] These parameters can be configured using the USART_ClockInit() function. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the USARTx peripheral registers to their default reset values. + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @retval None + */ +void USART_DeInit(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + if (USARTx == USART1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); + } + else if (USARTx == USART2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); + } + else if (USARTx == USART3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); + } + else if (USARTx == USART4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART4, DISABLE); + } + else if (USARTx == USART5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART5, DISABLE); + } + else if (USARTx == USART6) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE); + } + else if (USARTx == USART7) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART7, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART7, DISABLE); + } + else + { + if (USARTx == USART8) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART8, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART8, DISABLE); + } + } +} + +/** + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct . + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that contains + * the configuration information for the specified USART peripheral. + * @retval None + */ +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) +{ + uint32_t divider = 0, apbclock = 0, tmpreg = 0; + RCC_ClocksTypeDef RCC_ClocksStatus; + + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); + assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); + assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); + assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); + assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); + assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); + + /* Disable USART */ + USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UE); + + /*---------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = USARTx->CR2; + /* Clear STOP[13:12] bits */ + tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP); + + /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/ + /* Set STOP[13:12] bits according to USART_StopBits value */ + tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; + + /* Write to USART CR2 */ + USARTx->CR2 = tmpreg; + + /*---------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = USARTx->CR1; + /* Clear M, PCE, PS, TE and RE bits */ + tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK); + + /* Configure the USART Word Length, Parity and mode ----------------------- */ + /* Set the M bits according to USART_WordLength value */ + /* Set PCE and PS bits according to USART_Parity value */ + /* Set TE and RE bits according to USART_Mode value */ + tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + + /* Write to USART CR1 */ + USARTx->CR1 = tmpreg; + + /*---------------------------- USART CR3 Configuration -----------------------*/ + tmpreg = USARTx->CR3; + /* Clear CTSE and RTSE bits */ + tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK); + + /* Configure the USART HFC -------------------------------------------------*/ + /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + + /* Write to USART CR3 */ + USARTx->CR3 = tmpreg; + + /*---------------------------- USART BRR Configuration -----------------------*/ + /* Configure the USART Baud Rate -------------------------------------------*/ + RCC_GetClocksFreq(&RCC_ClocksStatus); + + if (USARTx == USART1) + { + apbclock = RCC_ClocksStatus.USART1CLK_Frequency; + } + else if (USARTx == USART2) + { + apbclock = RCC_ClocksStatus.USART2CLK_Frequency; + } + else if (USARTx == USART3) + { + apbclock = RCC_ClocksStatus.USART3CLK_Frequency; + } + else + { + apbclock = RCC_ClocksStatus.PCLK_Frequency; + } + + /* Determine the integer part */ + if ((USARTx->CR1 & USART_CR1_OVER8) != 0) + { + /* (divider * 10) computing in case Oversampling mode is 8 Samples */ + divider = (uint32_t)((2 * apbclock) / (USART_InitStruct->USART_BaudRate)); + tmpreg = (uint32_t)((2 * apbclock) % (USART_InitStruct->USART_BaudRate)); + } + else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ + { + /* (divider * 10) computing in case Oversampling mode is 16 Samples */ + divider = (uint32_t)((apbclock) / (USART_InitStruct->USART_BaudRate)); + tmpreg = (uint32_t)((apbclock) % (USART_InitStruct->USART_BaudRate)); + } + + /* round the divider : if fractional part i greater than 0.5 increment divider */ + if (tmpreg >= (USART_InitStruct->USART_BaudRate) / 2) + { + divider++; + } + + /* Implement the divider in case Oversampling mode is 8 Samples */ + if ((USARTx->CR1 & USART_CR1_OVER8) != 0) + { + /* get the LSB of divider and shift it to the right by 1 bit */ + tmpreg = (divider & (uint16_t)0x000F) >> 1; + + /* update the divider value */ + divider = (divider & (uint16_t)0xFFF0) | tmpreg; + } + + /* Write to USART BRR */ + USARTx->BRR = (uint16_t)divider; +} + +/** + * @brief Fills each USART_InitStruct member with its default value. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * which will be initialized. + * @retval None + */ +void USART_StructInit(USART_InitTypeDef* USART_InitStruct) +{ + /* USART_InitStruct members default value */ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No ; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/** + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct. + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef + * structure that contains the configuration information for the specified + * USART peripheral. + * @retval None + */ +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); + assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); + assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); + assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); +/*---------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = USARTx->CR2; + /* Clear CLKEN, CPOL, CPHA, LBCL and SSM bits */ + tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK); + /* Configure the USART Clock, CPOL, CPHA, LastBit and SSM ------------*/ + /* Set CLKEN bit according to USART_Clock value */ + /* Set CPOL bit according to USART_CPOL value */ + /* Set CPHA bit according to USART_CPHA value */ + /* Set LBCL bit according to USART_LastBit value */ + tmpreg |= (uint32_t)(USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | + USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit); + /* Write to USART CR2 */ + USARTx->CR2 = tmpreg; +} + +/** + * @brief Fills each USART_ClockInitStruct member with its default value. + * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef + * structure which will be initialized. + * @retval None + */ +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) +{ + /* USART_ClockInitStruct members default value */ + USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; + USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; + USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; + USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; +} + +/** + * @brief Enables or disables the specified USART peripheral. + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @param NewState: new state of the USARTx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected USART by setting the UE bit in the CR1 register */ + USARTx->CR1 |= USART_CR1_UE; + } + else + { + /* Disable the selected USART by clearing the UE bit in the CR1 register */ + USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UE); + } +} + +/** + * @brief Enables or disables the USART's transmitter or receiver. + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @param USART_Direction: specifies the USART direction. + * This parameter can be any combination of the following values: + * @arg USART_Mode_Tx: USART Transmitter + * @arg USART_Mode_Rx: USART Receiver + * @param NewState: new state of the USART transfer direction. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_MODE(USART_DirectionMode)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the USART's transfer interface by setting the TE and/or RE bits + in the USART CR1 register */ + USARTx->CR1 |= USART_DirectionMode; + } + else + { + /* Disable the USART's transfer interface by clearing the TE and/or RE bits + in the USART CR3 register */ + USARTx->CR1 &= (uint32_t)~USART_DirectionMode; + } +} + +/** + * @brief Enables or disables the USART's 8x oversampling mode. + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @param NewState: new state of the USART 8x oversampling mode. + * This parameter can be: ENABLE or DISABLE. + * @note This function has to be called before calling USART_Init() function + * in order to have correct baudrate Divider value. + * @retval None + */ +void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ + USARTx->CR1 |= USART_CR1_OVER8; + } + else + { + /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ + USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_OVER8); + } +} + +/** + * @brief Enables or disables the USART's one bit sampling method. + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @param NewState: new state of the USART one bit sampling method. + * This parameter can be: ENABLE or DISABLE. + * @note This function has to be called before calling USART_Cmd() function. + * @retval None + */ +void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_ONEBIT; + } + else + { + /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */ + USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT); + } +} + +/** + * @brief Enables or disables the USART's most significant bit first + * transmitted/received following the start bit. + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @param NewState: new state of the USART most significant bit first + * transmitted/received following the start bit. + * This parameter can be: ENABLE or DISABLE. + * @note This function has to be called before calling USART_Cmd() function. + * @retval None + */ +void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the most significant bit first transmitted/received following the + start bit by setting the MSBFIRST bit in the CR2 register */ + USARTx->CR2 |= USART_CR2_MSBFIRST; + } + else + { + /* Disable the most significant bit first transmitted/received following the + start bit by clearing the MSBFIRST bit in the CR2 register */ + USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_MSBFIRST); + } +} + +/** + * @brief Enables or disables the binary data inversion. + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @param NewState: new defined levels for the USART data. + * This parameter can be: + * @arg ENABLE: Logical data from the data register are send/received in negative + * logic (1=L, 0=H). The parity bit is also inverted. + * @arg DISABLE: Logical data from the data register are send/received in positive + * logic (1=H, 0=L) + * @note This function has to be called before calling USART_Cmd() function. + * @retval None + */ +void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the binary data inversion feature by setting the DATAINV bit in + the CR2 register */ + USARTx->CR2 |= USART_CR2_DATAINV; + } + else + { + /* Disable the binary data inversion feature by clearing the DATAINV bit in + the CR2 register */ + USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_DATAINV); + } +} + +/** + * @brief Enables or disables the Pin(s) active level inversion. + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @param USART_InvPin: specifies the USART pin(s) to invert. + * This parameter can be any combination of the following values: + * @arg USART_InvPin_Tx: USART Tx pin active level inversion. + * @arg USART_InvPin_Rx: USART Rx pin active level inversion. + * @param NewState: new active level status for the USART pin(s). + * This parameter can be: + * @arg ENABLE: pin(s) signal values are inverted (Vdd =0, Gnd =1). + * @arg DISABLE: pin(s) signal works using the standard logic levels (Vdd =1, Gnd =0). + * @note This function has to be called before calling USART_Cmd() function. + * @retval None + */ +void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_INVERSTION_PIN(USART_InvPin)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the active level inversion for selected pins by setting the TXINV + and/or RXINV bits in the USART CR2 register */ + USARTx->CR2 |= USART_InvPin; + } + else + { + /* Disable the active level inversion for selected requests by clearing the + TXINV and/or RXINV bits in the USART CR2 register */ + USARTx->CR2 &= (uint32_t)~USART_InvPin; + } +} + +/** + * @brief Enables or disables the swap Tx/Rx pins. + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @param NewState: new state of the USARTx TX/RX pins pinout. + * This parameter can be: + * @arg ENABLE: The TX and RX pins functions are swapped. + * @arg DISABLE: TX/RX pins are used as defined in standard pinout + * @note This function has to be called before calling USART_Cmd() function. + * @retval None + */ +void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the SWAP feature by setting the SWAP bit in the CR2 register */ + USARTx->CR2 |= USART_CR2_SWAP; + } + else + { + /* Disable the SWAP feature by clearing the SWAP bit in the CR2 register */ + USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_SWAP); + } +} + +/** + * @brief Enables or disables the receiver Time Out feature. + * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. + * @note USART2 is available only for STM32F072 and STM32F091 devices. + * @note USART3 is available only for STM32F091 devices. + * @param NewState: new state of the USARTx receiver Time Out. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the receiver time out feature by setting the RTOEN bit in the CR2 + register */ + USARTx->CR2 |= USART_CR2_RTOEN; + } + else + { + /* Disable the receiver time out feature by clearing the RTOEN bit in the CR2 + register */ + USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_RTOEN); + } +} + +/** + * @brief Sets the receiver Time Out value. + * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. + * @note USART2 is available only for STM32F072 and STM32F091 devices. + * @note USART3 is available only for STM32F091 devices. + * @param USART_ReceiverTimeOut: specifies the Receiver Time Out value. + * @retval None + */ +void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_USART_TIMEOUT(USART_ReceiverTimeOut)); + + /* Clear the receiver Time Out value by clearing the RTO[23:0] bits in the RTOR + register */ + USARTx->RTOR &= (uint32_t)~((uint32_t)USART_RTOR_RTO); + /* Set the receiver Time Out value by setting the RTO[23:0] bits in the RTOR + register */ + USARTx->RTOR |= USART_ReceiverTimeOut; +} + +/** + * @brief Sets the system clock prescaler. + * @note This function is not available for STM32F030 devices. + * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. + * @note USART2 is available only for STM32F072 and STM32F091 devices. + * @note USART3 is available only for STM32F091 devices. + * @param USART_Prescaler: specifies the prescaler clock. + * @note This function has to be called before calling USART_Cmd() function. + * @retval None + */ +void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + + /* Clear the USART prescaler */ + USARTx->GTPR &= USART_GTPR_GT; + /* Set the USART prescaler */ + USARTx->GTPR |= USART_Prescaler; +} + +/** + * @} + */ + + +/** @defgroup USART_Group2 STOP Mode functions + * @brief STOP Mode functions + * +@verbatim + =============================================================================== + ##### STOP Mode functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage + WakeUp from STOP mode. + + [..] The USART is able to WakeUp from Stop Mode if USART clock is set to HSI + or LSI. + + [..] The WakeUp source is configured by calling USART_StopModeWakeUpSourceConfig() + function. + + [..] After configuring the source of WakeUp and before entering in Stop Mode + USART_STOPModeCmd() function should be called to allow USART WakeUp. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified USART peripheral in STOP Mode. + * @param USARTx: where x can be 1 or 2 or 3 to select the USART peripheral. + * @note USART2 is available only for STM32F072 and STM32F091 devices. + * @note USART3 is available only for STM32F091 devices. + * @param NewState: new state of the USARTx peripheral state in stop mode. + * This parameter can be: ENABLE or DISABLE. + * @note This function has to be called when USART clock is set to HSI or LSE. + * @retval None + */ +void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected USART in STOP mode by setting the UESM bit in the CR1 + register */ + USARTx->CR1 |= USART_CR1_UESM; + } + else + { + /* Disable the selected USART in STOP mode by clearing the UE bit in the CR1 + register */ + USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UESM); + } +} + +/** + * @brief Selects the USART WakeUp method form stop mode. + * @note This function is not available for STM32F030 devices. + * @param USARTx: where x can be 1 or 2 or 3 to select the USART peripheral. + * @note USART2 is available only for STM32F072 and STM32F091 devices. + * @note USART3 is available only for STM32F091 devices. + * @param USART_WakeUp: specifies the selected USART wakeup method. + * This parameter can be one of the following values: + * @arg USART_WakeUpSource_AddressMatch: WUF active on address match. + * @arg USART_WakeUpSource_StartBit: WUF active on Start bit detection. + * @arg USART_WakeUpSource_RXNE: WUF active on RXNE. + * @note This function has to be called before calling USART_Cmd() function. + * @retval None + */ +void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_USART_STOPMODE_WAKEUPSOURCE(USART_WakeUpSource)); + + USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_WUS); + USARTx->CR3 |= USART_WakeUpSource; +} + +/** + * @} + */ + + +/** @defgroup USART_Group3 AutoBaudRate functions + * @brief AutoBaudRate functions + * +@verbatim + =============================================================================== + ##### AutoBaudRate functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage + the AutoBaudRate detections. + + [..] Before Enabling AutoBaudRate detection using USART_AutoBaudRateCmd () + The character patterns used to calculate baudrate must be chosen by calling + USART_AutoBaudRateConfig() function. These function take as parameter : + (#)USART_AutoBaudRate_StartBit : any character starting with a bit 1. + (#)USART_AutoBaudRate_FallingEdge : any character starting with a 10xx bit pattern. + + [..] At any later time, another request for AutoBaudRate detection can be performed + using USART_RequestCmd() function. + + [..] The AutoBaudRate detection is monitored by the status of ABRF flag which indicate + that the AutoBaudRate detection is completed. In addition to ABRF flag, the ABRE flag + indicate that this procedure is completed without success. USART_GetFlagStatus () + function should be used to monitor the status of these flags. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the Auto Baud Rate. + * @param USARTx: where x can be 1or 2 to select the USART peripheral. + * @note USART2 is available only for STM32F072 and STM32F091 devices. + * @note USART3 is available only for STM32F091 devices. + * @param NewState: new state of the USARTx auto baud rate. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the auto baud rate feature by setting the ABREN bit in the CR2 + register */ + USARTx->CR2 |= USART_CR2_ABREN; + } + else + { + /* Disable the auto baud rate feature by clearing the ABREN bit in the CR2 + register */ + USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ABREN); + } +} + +/** + * @brief Selects the USART auto baud rate method. + * @param USARTx: where x can be 1or 2 to select the USART peripheral. + * @note USART2 is available only for STM32F072 and STM32F091 devices. + * @note USART3 is available only for STM32F091 devices. + * @param USART_AutoBaudRate: specifies the selected USART auto baud rate method. + * This parameter can be one of the following values: + * @arg USART_AutoBaudRate_StartBit: Start Bit duration measurement. + * @arg USART_AutoBaudRate_FallingEdge: Falling edge to falling edge measurement. + * @note This function has to be called before calling USART_Cmd() function. + * @retval None + */ +void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_USART_AUTOBAUDRATE_MODE(USART_AutoBaudRate)); + + USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ABRMODE); + USARTx->CR2 |= USART_AutoBaudRate; +} + +/** + * @} + */ + + +/** @defgroup USART_Group4 Data transfers functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### Data transfers functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage + the USART data transfers. + [..] During an USART reception, data shifts in least significant bit first + through the RX pin. When a transmission is taking place, a write instruction to + the USART_TDR register stores the data in the shift register. + [..] The read access of the USART_RDR register can be done using + the USART_ReceiveData() function and returns the RDR value. + Whereas a write access to the USART_TDR can be done using USART_SendData() + function and stores the written data into TDR. + +@endverbatim + * @{ + */ + +/** + * @brief Transmits single data through the USARTx peripheral. + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @param Data: the data to transmit. + * @retval None + */ +void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DATA(Data)); + + /* Transmit Data */ + USARTx->TDR = (Data & (uint16_t)0x01FF); +} + +/** + * @brief Returns the most recent received data by the USARTx peripheral. + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @retval The received data. + */ +uint16_t USART_ReceiveData(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Receive Data */ + return (uint16_t)(USARTx->RDR & (uint16_t)0x01FF); +} + +/** + * @} + */ + +/** @defgroup USART_Group5 MultiProcessor Communication functions + * @brief Multi-Processor Communication functions + * +@verbatim + =============================================================================== + ##### Multi-Processor Communication functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage the USART + multiprocessor communication. + [..] For instance one of the USARTs can be the master, its TX output is + connected to the RX input of the other USART. The others are slaves, + their respective TX outputs are logically ANDed together and connected + to the RX input of the master. USART multiprocessor communication is + possible through the following procedure: + (#) Program the Baud rate, Word length = 9 bits, Stop bits, Parity, + Mode transmitter or Mode receiver and hardware flow control values + using the USART_Init() function. + (#) Configures the USART address using the USART_SetAddress() function. + (#) Configures the wake up methode (USART_WakeUp_IdleLine or + USART_WakeUp_AddressMark) using USART_WakeUpConfig() function only + for the slaves. + (#) Enable the USART using the USART_Cmd() function. + (#) Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() + function. + [..] The USART Slave exit from mute mode when receive the wake up condition. + +@endverbatim + * @{ + */ + +/** + * @brief Sets the address of the USART node. + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @param USART_Address: Indicates the address of the USART node. + * @retval None + */ +void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Clear the USART address */ + USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ADD); + /* Set the USART address node */ + USARTx->CR2 |=((uint32_t)USART_Address << (uint32_t)0x18); +} + +/** + * @brief Enables or disables the USART's mute mode. + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @param NewState: new state of the USART mute mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the USART mute mode by setting the MME bit in the CR1 register */ + USARTx->CR1 |= USART_CR1_MME; + } + else + { + /* Disable the USART mute mode by clearing the MME bit in the CR1 register */ + USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_MME); + } +} + +/** + * @brief Selects the USART WakeUp method from mute mode. + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @param USART_WakeUp: specifies the USART wakeup method. + * This parameter can be one of the following values: + * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection + * @arg USART_WakeUp_AddressMark: WakeUp by an address mark + * @retval None + */ +void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_MUTEMODE_WAKEUP(USART_WakeUp)); + + USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_WAKE); + USARTx->CR1 |= USART_WakeUp; +} + +/** + * @brief Configure the the USART Address detection length. + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @param USART_AddressLength: specifies the USART address length detection. + * This parameter can be one of the following values: + * @arg USART_AddressLength_4b: 4-bit address length detection + * @arg USART_AddressLength_7b: 7-bit address length detection + * @retval None + */ +void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_ADDRESS_DETECTION(USART_AddressLength)); + + USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ADDM7); + USARTx->CR2 |= USART_AddressLength; +} + +/** + * @} + */ + +/** @defgroup USART_Group6 LIN mode functions + * @brief LIN mode functions + * +@verbatim + =============================================================================== + ##### LIN mode functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage the USART + LIN Mode communication. + [..] In LIN mode, 8-bit data format with 1 stop bit is required in accordance + with the LIN standard. + [..] Only this LIN Feature is supported by the USART IP: + (+) LIN Master Synchronous Break send capability and LIN slave break + detection capability : 13-bit break generation and 10/11 bit break + detection. + [..] USART LIN Master transmitter communication is possible through the + following procedure: + (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, + Mode transmitter or Mode receiver and hardware flow control values + using the USART_Init() function. + (#) Enable the LIN mode using the USART_LINCmd() function. + (#) Enable the USART using the USART_Cmd() function. + (#) Send the break character using USART_SendBreak() function. + [..] USART LIN Master receiver communication is possible through the + following procedure: + (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, + Mode transmitter or Mode receiver and hardware flow control values + using the USART_Init() function. + (#) Configures the break detection length + using the USART_LINBreakDetectLengthConfig() function. + (#) Enable the LIN mode using the USART_LINCmd() function. + -@- In LIN mode, the following bits must be kept cleared: + (+@) CLKEN in the USART_CR2 register. + (+@) STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register. + (#) Enable the USART using the USART_Cmd() function. + +@endverbatim + * @{ + */ + +/** + * @brief Sets the USART LIN Break detection length. + * @note This function is not available for STM32F030 devices. + * @param USARTx: where x can be 1or 2 to select the USART peripheral. + * @note USART2 is available only for STM32F072 and STM32F091 devices. + * @note USART3 is available only for STM32F091 devices. + * @param USART_LINBreakDetectLength: specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg USART_LINBreakDetectLength_10b: 10-bit break detection + * @arg USART_LINBreakDetectLength_11b: 11-bit break detection + * @retval None + */ +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); + + USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_LBDL); + USARTx->CR2 |= USART_LINBreakDetectLength; +} + +/** + * @brief Enables or disables the USART's LIN mode. + * @note This function is not available for STM32F030 devices. + * @param USARTx: where x can be 1or 2 to select the USART peripheral. + * @note USART2 is available only for STM32F072 and STM32F091 devices. + * @note USART3 is available only for STM32F091 devices. + * @param NewState: new state of the USART LIN mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + USARTx->CR2 |= USART_CR2_LINEN; + } + else + { + /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ + USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_LINEN); + } +} + +/** + * @} + */ + +/** @defgroup USART_Group7 Halfduplex mode function + * @brief Half-duplex mode function + * +@verbatim + =============================================================================== + ##### Half-duplex mode function ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage the USART + Half-duplex communication. + [..] The USART can be configured to follow a single-wire half-duplex protocol + where the TX and RX lines are internally connected. + [..] USART Half duplex communication is possible through the following procedure: + (#) Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter + or Mode receiver and hardware flow control values using the USART_Init() + function. + (#) Configures the USART address using the USART_SetAddress() function. + (#) Enable the half duplex mode using USART_HalfDuplexCmd() function. + (#) Enable the USART using the USART_Cmd() function. + -@- The RX pin is no longer used. + -@- In Half-duplex mode the following bits must be kept cleared: + (+@) LINEN and CLKEN bits in the USART_CR2 register. + (+@) SCEN and IREN bits in the USART_CR3 register. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the USART's Half Duplex communication. + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @param NewState: new state of the USART Communication. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_HDSEL; + } + else + { + /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ + USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_HDSEL); + } +} + +/** + * @} + */ + + +/** @defgroup USART_Group8 Smartcard mode functions + * @brief Smartcard mode functions + * +@verbatim + =============================================================================== + ##### Smartcard mode functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage the USART + Smartcard communication. + [..] The Smartcard interface is designed to support asynchronous protocol + Smartcards as defined in the ISO 7816-3 standard. The USART can provide + a clock to the smartcard through the SCLK output. In smartcard mode, + SCLK is not associated to the communication but is simply derived from + the internal peripheral input clock through a 5-bit prescaler. + [..] Smartcard communication is possible through the following procedure: + (#) Configures the Smartcard Prsecaler using the USART_SetPrescaler() + function. + (#) Configures the Smartcard Guard Time using the USART_SetGuardTime() + function. + (#) Program the USART clock using the USART_ClockInit() function as following: + (++) USART Clock enabled. + (++) USART CPOL Low. + (++) USART CPHA on first edge. + (++) USART Last Bit Clock Enabled. + (#) Program the Smartcard interface using the USART_Init() function as + following: + (++) Word Length = 9 Bits. + (++) 1.5 Stop Bit. + (++) Even parity. + (++) BaudRate = 12096 baud. + (++) Hardware flow control disabled (RTS and CTS signals). + (++) Tx and Rx enabled + (#) Optionally you can enable the parity error interrupt using + the USART_ITConfig() function. + (#) Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function. + (#) Enable the Smartcard interface using the USART_SmartCardCmd() function. + (#) Enable the USART using the USART_Cmd() function. + [..] + Please refer to the ISO 7816-3 specification for more details. + [..] + (@) It is also possible to choose 0.5 stop bit for receiving but it is + recommended to use 1.5 stop bits for both transmitting and receiving + to avoid switching between the two configurations. + (@) In smartcard mode, the following bits must be kept cleared: + (+@) LINEN bit in the USART_CR2 register. + (+@) HDSEL and IREN bits in the USART_CR3 register. + +@endverbatim + * @{ + */ + +/** + * @brief Sets the specified USART guard time. + * @note This function is not available for STM32F030 devices. + * @param USARTx: where x can be 1or 2 to select the USART peripheral. + * @note USART2 is available only for STM32F072 and STM32F091 devices. + * @note USART3 is available only for STM32F091 devices. + * @param USART_GuardTime: specifies the guard time. + * @retval None + */ +void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + + /* Clear the USART Guard time */ + USARTx->GTPR &= USART_GTPR_PSC; + /* Set the USART guard time */ + USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/** + * @brief Enables or disables the USART's Smart Card mode. + * @note This function is not available for STM32F030 devices. + * @param USARTx: where x can be 1or 2 to select the USART peripheral. + * @note USART2 is available only for STM32F072 and STM32F091 devices. + * @note USART3 is available only for STM32F091 devices. + * @param NewState: new state of the Smart Card mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the SC mode by setting the SCEN bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_SCEN; + } + else + { + /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ + USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_SCEN); + } +} + +/** + * @brief Enables or disables NACK transmission. + * @note This function is not available for STM32F030 devices. + * @param USARTx: where x can be 1or 2 to select the USART peripheral. + * @note USART2 is available only for STM32F072 and STM32F091 devices. + * @note USART3 is available only for STM32F091 devices. + * @param NewState: new state of the NACK transmission. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_NACK; + } + else + { + /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ + USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_NACK); + } +} + +/** + * @brief Sets the Smart Card number of retries in transmit and receive. + * @note This function is not available for STM32F030 devices. + * @param USARTx: where x can be 1or 3 to select the USART peripheral. + * @note USART2 is available only for STM32F072 and STM32F091 devices. + * @note USART3 is available only for STM32F091 devices. + * @param USART_AutoCount: specifies the Smart Card auto retry count. + * @retval None + */ +void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_USART_AUTO_RETRY_COUNTER(USART_AutoCount)); + /* Clear the USART auto retry count */ + USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_SCARCNT); + /* Set the USART auto retry count*/ + USARTx->CR3 |= (uint32_t)((uint32_t)USART_AutoCount << 0x11); +} + +/** + * @brief Sets the Smart Card Block length. + * @note This function is not available for STM32F030 devices. + * @param USARTx: where x can be 1or 3 to select the USART peripheral. + * @note USART2 is available only for STM32F072 and STM32F091 devices. + * @note USART3 is available only for STM32F091 devices. + * @param USART_BlockLength: specifies the Smart Card block length. + * @retval None + */ +void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + + /* Clear the Smart card block length */ + USARTx->RTOR &= (uint32_t)~((uint32_t)USART_RTOR_BLEN); + /* Set the Smart Card block length */ + USARTx->RTOR |= (uint32_t)((uint32_t)USART_BlockLength << 0x18); +} + +/** + * @} + */ + +/** @defgroup USART_Group9 IrDA mode functions + * @brief IrDA mode functions + * +@verbatim + =============================================================================== + ##### IrDA mode functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage the USART + IrDA communication. + [..] IrDA is a half duplex communication protocol. If the Transmitter is busy, + any data on the IrDA receive line will be ignored by the IrDA decoder + and if the Receiver is busy, data on the TX from the USART to IrDA will + not be encoded by IrDA. While receiving data, transmission should be + avoided as the data to be transmitted could be corrupted. + [..] IrDA communication is possible through the following procedure: + (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, + Transmitter/Receiver modes and hardware flow control values using + the USART_Init() function. + (#) Configures the IrDA pulse width by configuring the prescaler using + the USART_SetPrescaler() function. + (#) Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal + mode using the USART_IrDAConfig() function. + (#) Enable the IrDA using the USART_IrDACmd() function. + (#) Enable the USART using the USART_Cmd() function. + [..] + (@) A pulse of width less than two and greater than one PSC period(s) may or + may not be rejected. + (@) The receiver set up time should be managed by software. The IrDA physical + layer specification specifies a minimum of 10 ms delay between + transmission and reception (IrDA is a half duplex protocol). + (@) In IrDA mode, the following bits must be kept cleared: + (+@) LINEN, STOP and CLKEN bits in the USART_CR2 register. + (+@) SCEN and HDSEL bits in the USART_CR3 register. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the USART's IrDA interface. + * @note This function is not available for STM32F030 devices. + * @param USARTx: where x can be 1or 2 to select the USART peripheral. + * @note USART2 is available only for STM32F072 and STM32F091 devices. + * @note USART3 is available only for STM32F091 devices. + * @param USART_IrDAMode: specifies the IrDA mode. + * This parameter can be one of the following values: + * @arg USART_IrDAMode_LowPower + * @arg USART_IrDAMode_Normal + * @retval None + */ +void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); + + USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_IRLP); + USARTx->CR3 |= USART_IrDAMode; +} + +/** + * @brief Enables or disables the USART's IrDA interface. + * @note This function is not available for STM32F030 devices. + * @param USARTx: where x can be 1or 2 to select the USART peripheral. + * @note USART2 is available only for STM32F072 and STM32F091 devices. + * @note USART3 is available only for STM32F091 devices. + * @param NewState: new state of the IrDA mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_IREN; + } + else + { + /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ + USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_IREN); + } +} +/** + * @} + */ + +/** @defgroup USART_Group10 RS485 mode function + * @brief RS485 mode function + * +@verbatim + =============================================================================== + ##### RS485 mode functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage the USART + RS485 flow control. + [..] RS485 flow control (Driver enable feature) handling is possible through + the following procedure: + (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, + Transmitter/Receiver modes and hardware flow control values using + the USART_Init() function. + (#) Enable the Driver Enable using the USART_DECmd() function. + (#) Configures the Driver Enable polarity using the USART_DEPolarityConfig() + function. + (#) Configures the Driver Enable assertion time using USART_SetDEAssertionTime() + function and deassertion time using the USART_SetDEDeassertionTime() + function. + (#) Enable the USART using the USART_Cmd() function. + -@- + (+@) The assertion and dessertion times are expressed in sample time units (1/8 or + 1/16 bit time, depending on the oversampling rate). + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the USART's DE functionality. + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @param NewState: new state of the driver enable mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the DE functionality by setting the DEM bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_DEM; + } + else + { + /* Disable the DE functionality by clearing the DEM bit in the CR3 register */ + USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DEM); + } +} + +/** + * @brief Configures the USART's DE polarity + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @param USART_DEPolarity: specifies the DE polarity. + * This parameter can be one of the following values: + * @arg USART_DEPolarity_Low + * @arg USART_DEPolarity_High + * @retval None + */ +void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DE_POLARITY(USART_DEPolarity)); + + USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DEP); + USARTx->CR3 |= USART_DEPolarity; +} + +/** + * @brief Sets the specified RS485 DE assertion time + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @param USART_DEAssertionTime: specifies the time between the activation of + * the DE signal and the beginning of the start bit + * @retval None + */ +void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DE_ASSERTION_DEASSERTION_TIME(USART_DEAssertionTime)); + + /* Clear the DE assertion time */ + USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_DEAT); + /* Set the new value for the DE assertion time */ + USARTx->CR1 |=((uint32_t)USART_DEAssertionTime << (uint32_t)0x15); +} + +/** + * @brief Sets the specified RS485 DE deassertion time + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @param USART_DeassertionTime: specifies the time between the middle of the last + * stop bit in a transmitted message and the de-activation of the DE signal + * @retval None + */ +void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DE_ASSERTION_DEASSERTION_TIME(USART_DEDeassertionTime)); + + /* Clear the DE deassertion time */ + USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_DEDT); + /* Set the new value for the DE deassertion time */ + USARTx->CR1 |=((uint32_t)USART_DEDeassertionTime << (uint32_t)0x10); +} + +/** + * @} + */ + +/** @defgroup USART_Group11 DMA transfers management functions + * @brief DMA transfers management functions + * +@verbatim + =============================================================================== + ##### DMA transfers management functions ##### + =============================================================================== + [..] This section provides two functions that can be used only in DMA mode. + [..] In DMA Mode, the USART communication can be managed by 2 DMA Channel + requests: + (#) USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request. + (#) USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request. + [..] In this Mode it is advised to use the following function: + (+) void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, + FunctionalState NewState). +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the USART's DMA interface. + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @param USART_DMAReq: specifies the DMA request. + * This parameter can be any combination of the following values: + * @arg USART_DMAReq_Tx: USART DMA transmit request + * @arg USART_DMAReq_Rx: USART DMA receive request + * @param NewState: new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DMAREQ(USART_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA transfer for selected requests by setting the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 |= USART_DMAReq; + } + else + { + /* Disable the DMA transfer for selected requests by clearing the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 &= (uint32_t)~USART_DMAReq; + } +} + +/** + * @brief Enables or disables the USART's DMA interface when reception error occurs. + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @param USART_DMAOnError: specifies the DMA status in case of reception error. + * This parameter can be any combination of the following values: + * @arg USART_DMAOnError_Enable: DMA receive request enabled when the USART DMA + * reception error is asserted. + * @arg USART_DMAOnError_Disable: DMA receive request disabled when the USART DMA + * reception error is asserted. + * @retval None + */ +void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DMAONERROR(USART_DMAOnError)); + + /* Clear the DMA Reception error detection bit */ + USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DDRE); + /* Set the new value for the DMA Reception error detection bit */ + USARTx->CR3 |= USART_DMAOnError; +} + +/** + * @} + */ + +/** @defgroup USART_Group12 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to configure the + USART Interrupts sources, Requests and check or clear the flags or pending bits status. + The user should identify which mode will be used in his application to + manage the communication: Polling mode, Interrupt mode. + + *** Polling Mode *** + ==================== + [..] In Polling Mode, the SPI communication can be managed by these flags: + (#) USART_FLAG_REACK: to indicate the status of the Receive Enable + acknowledge flag + (#) USART_FLAG_TEACK: to indicate the status of the Transmit Enable + acknowledge flag. + (#) USART_FLAG_WU: to indicate the status of the Wake up flag. + (#) USART_FLAG_RWU: to indicate the status of the Receive Wake up flag. + (#) USART_FLAG_SBK: to indicate the status of the Send Break flag. + (#) USART_FLAG_CM: to indicate the status of the Character match flag. + (#) USART_FLAG_BUSY: to indicate the status of the Busy flag. + (#) USART_FLAG_ABRF: to indicate the status of the Auto baud rate flag. + (#) USART_FLAG_ABRE: to indicate the status of the Auto baud rate error flag. + (#) USART_FLAG_EOB: to indicate the status of the End of block flag. + (#) USART_FLAG_RTO: to indicate the status of the Receive time out flag. + (#) USART_FLAG_nCTSS: to indicate the status of the Inverted nCTS input + bit status. + (#) USART_FLAG_TXE: to indicate the status of the transmit buffer register. + (#) USART_FLAG_RXNE: to indicate the status of the receive buffer register. + (#) USART_FLAG_TC: to indicate the status of the transmit operation. + (#) USART_FLAG_IDLE: to indicate the status of the Idle Line. + (#) USART_FLAG_CTS: to indicate the status of the nCTS input. + (#) USART_FLAG_LBD: to indicate the status of the LIN break detection. + (#) USART_FLAG_NE: to indicate if a noise error occur. + (#) USART_FLAG_FE: to indicate if a frame error occur. + (#) USART_FLAG_PE: to indicate if a parity error occur. + (#) USART_FLAG_ORE: to indicate if an Overrun error occur. + [..] In this Mode it is advised to use the following functions: + (+) FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG). + (+) void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG). + + *** Interrupt Mode *** + ====================== + [..] In Interrupt Mode, the USART communication can be managed by 8 interrupt + sources and 10 pending bits: + (+) Pending Bits: + (##) USART_IT_WU: to indicate the status of the Wake up interrupt. + (##) USART_IT_CM: to indicate the status of Character match interrupt. + (##) USART_IT_EOB: to indicate the status of End of block interrupt. + (##) USART_IT_RTO: to indicate the status of Receive time out interrupt. + (##) USART_IT_CTS: to indicate the status of CTS change interrupt. + (##) USART_IT_LBD: to indicate the status of LIN Break detection interrupt. + (##) USART_IT_TC: to indicate the status of Transmission complete interrupt. + (##) USART_IT_IDLE: to indicate the status of IDLE line detected interrupt. + (##) USART_IT_ORE: to indicate the status of OverRun Error interrupt. + (##) USART_IT_NE: to indicate the status of Noise Error interrupt. + (##) USART_IT_FE: to indicate the status of Framing Error interrupt. + (##) USART_IT_PE: to indicate the status of Parity Error interrupt. + + (+) Interrupt Source: + (##) USART_IT_WU: specifies the interrupt source for Wake up interrupt. + (##) USART_IT_CM: specifies the interrupt source for Character match + interrupt. + (##) USART_IT_EOB: specifies the interrupt source for End of block + interrupt. + (##) USART_IT_RTO: specifies the interrupt source for Receive time-out + interrupt. + (##) USART_IT_CTS: specifies the interrupt source for CTS change interrupt. + (##) USART_IT_LBD: specifies the interrupt source for LIN Break + detection interrupt. + (##) USART_IT_TXE: specifies the interrupt source for Tansmit Data + Register empty interrupt. + (##) USART_IT_TC: specifies the interrupt source for Transmission + complete interrupt. + (##) USART_IT_RXNE: specifies the interrupt source for Receive Data + register not empty interrupt. + (##) USART_IT_IDLE: specifies the interrupt source for Idle line + detection interrupt. + (##) USART_IT_PE: specifies the interrupt source for Parity Error interrupt. + (##) USART_IT_ERR: specifies the interrupt source for Error interrupt + (Frame error, noise error, overrun error) + -@@- Some parameters are coded in order to use them as interrupt + source or as pending bits. + [..] In this Mode it is advised to use the following functions: + (+) void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState). + (+) ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT). + (+) void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT). + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified USART interrupts. + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg USART_IT_WU: Wake up interrupt, not available for STM32F030 devices. + * @arg USART_IT_CM: Character match interrupt. + * @arg USART_IT_EOB: End of block interrupt, not available for STM32F030 devices. + * @arg USART_IT_RTO: Receive time out interrupt. + * @arg USART_IT_CTS: CTS change interrupt. + * @arg USART_IT_LBD: LIN Break detection interrupt, not available for STM32F030 devices. + * @arg USART_IT_TXE: Tansmit Data Register empty interrupt. + * @arg USART_IT_TC: Transmission complete interrupt. + * @arg USART_IT_RXNE: Receive Data register not empty interrupt. + * @arg USART_IT_IDLE: Idle line detection interrupt. + * @arg USART_IT_PE: Parity Error interrupt. + * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @param NewState: new state of the specified USARTx interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState) +{ + uint32_t usartreg = 0, itpos = 0, itmask = 0; + uint32_t usartxbase = 0; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CONFIG_IT(USART_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + usartxbase = (uint32_t)USARTx; + + /* Get the USART register index */ + usartreg = (((uint16_t)USART_IT) >> 0x08); + + /* Get the interrupt position */ + itpos = USART_IT & IT_MASK; + itmask = (((uint32_t)0x01) << itpos); + + if (usartreg == 0x02) /* The IT is in CR2 register */ + { + usartxbase += 0x04; + } + else if (usartreg == 0x03) /* The IT is in CR3 register */ + { + usartxbase += 0x08; + } + else /* The IT is in CR1 register */ + { + } + if (NewState != DISABLE) + { + *(__IO uint32_t*)usartxbase |= itmask; + } + else + { + *(__IO uint32_t*)usartxbase &= ~itmask; + } +} + +/** + * @brief Enables the specified USART's Request. + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @param USART_Request: specifies the USART request. + * This parameter can be any combination of the following values: + * @arg USART_Request_TXFRQ: Transmit data flush ReQuest + * @arg USART_Request_RXFRQ: Receive data flush ReQuest + * @arg USART_Request_MMRQ: Mute Mode ReQuest + * @arg USART_Request_SBKRQ: Send Break ReQuest + * @arg USART_Request_ABRRQ: Auto Baud Rate ReQuest + * @param NewState: new state of the DMA interface when reception error occurs. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_REQUEST(USART_Request)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the USART ReQuest by setting the dedicated request bit in the RQR + register.*/ + USARTx->RQR |= USART_Request; + } + else + { + /* Disable the USART ReQuest by clearing the dedicated request bit in the RQR + register.*/ + USARTx->RQR &= (uint32_t)~USART_Request; + } +} + +/** + * @brief Enables or disables the USART's Overrun detection. + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @param USART_OVRDetection: specifies the OVR detection status in case of OVR error. + * This parameter can be any combination of the following values: + * @arg USART_OVRDetection_Enable: OVR error detection enabled when + * the USART OVR error is asserted. + * @arg USART_OVRDetection_Disable: OVR error detection disabled when + * the USART OVR error is asserted. + * @retval None + */ +void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_OVRDETECTION(USART_OVRDetection)); + + /* Clear the OVR detection bit */ + USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_OVRDIS); + /* Set the new value for the OVR detection bit */ + USARTx->CR3 |= USART_OVRDetection; +} + +/** + * @brief Checks whether the specified USART flag is set or not. + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @param USART_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg USART_FLAG_REACK: Receive Enable acknowledge flag. + * @arg USART_FLAG_TEACK: Transmit Enable acknowledge flag. + * @arg USART_FLAG_WU: Wake up flag, not available for STM32F030 devices. + * @arg USART_FLAG_RWU: Receive Wake up flag, not available for STM32F030 devices. + * @arg USART_FLAG_SBK: Send Break flag. + * @arg USART_FLAG_CM: Character match flag. + * @arg USART_FLAG_BUSY: Busy flag. + * @arg USART_FLAG_ABRF: Auto baud rate flag. + * @arg USART_FLAG_ABRE: Auto baud rate error flag. + * @arg USART_FLAG_EOB: End of block flag, not available for STM32F030 devices. + * @arg USART_FLAG_RTO: Receive time out flag. + * @arg USART_FLAG_nCTSS: Inverted nCTS input bit status. + * @arg USART_FLAG_CTS: CTS Change flag. + * @arg USART_FLAG_LBD: LIN Break detection flag, not available for STM32F030 devices. + * @arg USART_FLAG_TXE: Transmit data register empty flag. + * @arg USART_FLAG_TC: Transmission Complete flag. + * @arg USART_FLAG_RXNE: Receive data register not empty flag. + * @arg USART_FLAG_IDLE: Idle Line detection flag. + * @arg USART_FLAG_ORE: OverRun Error flag. + * @arg USART_FLAG_NE: Noise Error flag. + * @arg USART_FLAG_FE: Framing Error flag. + * @arg USART_FLAG_PE: Parity Error flag. + * @retval The new state of USART_FLAG (SET or RESET). + */ +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_FLAG(USART_FLAG)); + + if ((USARTx->ISR & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the USARTx's pending flags. + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @param USART_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg USART_FLAG_WU: Wake up flag, not available for STM32F030 devices. + * @arg USART_FLAG_CM: Character match flag. + * @arg USART_FLAG_EOB: End of block flag, not available for STM32F030 devices. + * @arg USART_FLAG_RTO: Receive time out flag. + * @arg USART_FLAG_CTS: CTS Change flag. + * @arg USART_FLAG_LBD: LIN Break detection flag, not available for STM32F030 devices. + * @arg USART_FLAG_TC: Transmission Complete flag. + * @arg USART_FLAG_IDLE: IDLE line detected flag. + * @arg USART_FLAG_ORE: OverRun Error flag. + * @arg USART_FLAG_NE: Noise Error flag. + * @arg USART_FLAG_FE: Framing Error flag. + * @arg USART_FLAG_PE: Parity Errorflag. + * + * @note RXNE pending bit is cleared by a read to the USART_RDR register + * (USART_ReceiveData()) or by writing 1 to the RXFRQ in the register + * USART_RQR (USART_RequestCmd()). + * @note TC flag can be also cleared by software sequence: a read operation + * to USART_SR register (USART_GetFlagStatus()) followed by a write + * operation to USART_TDR register (USART_SendData()). + * @note TXE flag is cleared by a write to the USART_TDR register (USART_SendData()) + * or by writing 1 to the TXFRQ in the register USART_RQR (USART_RequestCmd()). + * @note SBKF flag is cleared by 1 to the SBKRQ in the register USART_RQR + * (USART_RequestCmd()). + * @retval None + */ +void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); + + USARTx->ICR = USART_FLAG; +} + +/** + * @brief Checks whether the specified USART interrupt has occurred or not. + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @param USART_IT: specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg USART_IT_WU: Wake up interrupt, not available for STM32F030 devices. + * @arg USART_IT_CM: Character match interrupt. + * @arg USART_IT_EOB: End of block interrupt, not available for STM32F030 devices. + * @arg USART_IT_RTO: Receive time out interrupt. + * @arg USART_IT_CTS: CTS change interrupt. + * @arg USART_IT_LBD: LIN Break detection interrupt, not available for STM32F030 devices. + * @arg USART_IT_TXE: Tansmit Data Register empty interrupt. + * @arg USART_IT_TC: Transmission complete interrupt. + * @arg USART_IT_RXNE: Receive Data register not empty interrupt. + * @arg USART_IT_IDLE: Idle line detection interrupt. + * @arg USART_IT_ORE: OverRun Error interrupt. + * @arg USART_IT_NE: Noise Error interrupt. + * @arg USART_IT_FE: Framing Error interrupt. + * @arg USART_IT_PE: Parity Error interrupt. + * @retval The new state of USART_IT (SET or RESET). + */ +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT) +{ + uint32_t bitpos = 0, itmask = 0, usartreg = 0; + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_GET_IT(USART_IT)); + + /* Get the USART register index */ + usartreg = (((uint16_t)USART_IT) >> 0x08); + /* Get the interrupt position */ + itmask = USART_IT & IT_MASK; + itmask = (uint32_t)0x01 << itmask; + + if (usartreg == 0x01) /* The IT is in CR1 register */ + { + itmask &= USARTx->CR1; + } + else if (usartreg == 0x02) /* The IT is in CR2 register */ + { + itmask &= USARTx->CR2; + } + else /* The IT is in CR3 register */ + { + itmask &= USARTx->CR3; + } + + bitpos = USART_IT >> 0x10; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->ISR; + if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** + * @brief Clears the USARTx's interrupt pending bits. + * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. + * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. + * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. + * @note USART2 is not available for STM32F031 devices. + * @param USART_IT: specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg USART_IT_WU: Wake up interrupt, not available for STM32F030 devices. + * @arg USART_IT_CM: Character match interrupt. + * @arg USART_IT_EOB: End of block interrupt, not available for STM32F030 devices. + * @arg USART_IT_RTO: Receive time out interrupt. + * @arg USART_IT_CTS: CTS change interrupt. + * @arg USART_IT_LBD: LIN Break detection interrupt, not available for STM32F030 devices. + * @arg USART_IT_TC: Transmission complete interrupt. + * @arg USART_IT_IDLE: IDLE line detected interrupt. + * @arg USART_IT_ORE: OverRun Error interrupt. + * @arg USART_IT_NE: Noise Error interrupt. + * @arg USART_IT_FE: Framing Error interrupt. + * @arg USART_IT_PE: Parity Error interrupt. + * + * @note RXNE pending bit is cleared by a read to the USART_RDR register + * (USART_ReceiveData()) or by writing 1 to the RXFRQ in the register + * USART_RQR (USART_RequestCmd()). + * @note TC pending bit can be also cleared by software sequence: a read + * operation to USART_SR register (USART_GetITStatus()) followed by + * a write operation to USART_TDR register (USART_SendData()). + * @note TXE pending bit is cleared by a write to the USART_TDR register + * (USART_SendData()) or by writing 1 to the TXFRQ in the register + * USART_RQR (USART_RequestCmd()). + * @retval None + */ +void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT) +{ + uint32_t bitpos = 0, itmask = 0; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_IT(USART_IT)); + + bitpos = USART_IT >> 0x10; + itmask = ((uint32_t)0x01 << (uint32_t)bitpos); + USARTx->ICR = (uint32_t)itmask; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/src/stm32f0-stdperiph/stm32f0xx_wwdg.c b/system/src/stm32f0-stdperiph/stm32f0xx_wwdg.c new file mode 100644 index 0000000..3b04fb4 --- /dev/null +++ b/system/src/stm32f0-stdperiph/stm32f0xx_wwdg.c @@ -0,0 +1,303 @@ +/** + ****************************************************************************** + * @file stm32f0xx_wwdg.c + * @author MCD Application Team + * @version V1.5.0 + * @date 05-December-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Window watchdog (WWDG) peripheral: + * + Prescaler, Refresh window and Counter configuration + * + WWDG activation + * + Interrupts and flags management + * + * @verbatim + * + ============================================================================== + ##### WWDG features ##### + ============================================================================== + [..] Once enabled the WWDG generates a system reset on expiry of a programmed + time period, unless the program refreshes the counter (downcounter) + before to reach 0x3F value (i.e. a reset is generated when the counter + value rolls over from 0x40 to 0x3F). + [..] An MCU reset is also generated if the counter value is refreshed + before the counter has reached the refresh window value. This + implies that the counter must be refreshed in a limited window. + + [..] Once enabled the WWDG cannot be disabled except by a system reset. + + [..] WWDGRST flag in RCC_CSR register can be used to inform when a WWDG + reset occurs. + + [..] The WWDG counter input clock is derived from the APB clock divided + by a programmable prescaler. + + [..] WWDG counter clock = PCLK1 / Prescaler. + [..] WWDG timeout = (WWDG counter clock) * (counter value). + + [..] Min-max timeout value @32MHz (PCLK1): ~85us / ~43ms. + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) + function. + + (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function. + + (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function. + + (#) Set the WWDG counter value and start it using WWDG_Enable() function. + When the WWDG is enabled the counter value should be configured to + a value greater than 0x40 to prevent generating an immediate reset. + + (#) Optionally you can enable the Early wakeup interrupt which is + generated when the counter reach 0x40. + Once enabled this interrupt cannot be disabled except by a system reset. + + (#) Then the application program must refresh the WWDG counter at regular + intervals during normal operation to prevent an MCU reset, using + WWDG_SetCounter() function. This operation must occur only when + the counter value is lower than the refresh window value, + programmed using WWDG_SetWindowValue(). + + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_wwdg.h" +#include "stm32f0xx_rcc.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup WWDG + * @brief WWDG driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* --------------------- WWDG registers bit mask ---------------------------- */ +/* CFR register bit mask */ +#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F) +#define CFR_W_MASK ((uint32_t)0xFFFFFF80) +#define BIT_MASK ((uint8_t)0x7F) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup WWDG_Private_Functions + * @{ + */ + +/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions + * @brief Prescaler, Refresh window and Counter configuration functions + * +@verbatim + ============================================================================== + ##### Prescaler, Refresh window and Counter configuration functions ##### + ============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the WWDG peripheral registers to their default reset values. + * @param None + * @retval None + */ +void WWDG_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); +} + +/** + * @brief Sets the WWDG Prescaler. + * @param WWDG_Prescaler: specifies the WWDG Prescaler. + * This parameter can be one of the following values: + * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 + * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 + * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 + * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 + * @retval None + */ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); + /* Clear WDGTB[1:0] bits */ + tmpreg = WWDG->CFR & CFR_WDGTB_MASK; + /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ + tmpreg |= WWDG_Prescaler; + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/** + * @brief Sets the WWDG window value. + * @param WindowValue: specifies the window value to be compared to the downcounter. + * This parameter value must be lower than 0x80. + * @retval None + */ +void WWDG_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); + /* Clear W[6:0] bits */ + + tmpreg = WWDG->CFR & CFR_W_MASK; + + /* Set W[6:0] bits according to WindowValue value */ + tmpreg |= WindowValue & (uint32_t) BIT_MASK; + + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/** + * @brief Enables the WWDG Early Wakeup interrupt(EWI). + * @note Once enabled this interrupt cannot be disabled except by a system reset. + * @param None + * @retval None + */ +void WWDG_EnableIT(void) +{ + WWDG->CFR |= WWDG_CFR_EWI; +} + +/** + * @brief Sets the WWDG counter value. + * @param Counter: specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F (to prevent + * generating an immediate reset). + * @retval None + */ +void WWDG_SetCounter(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + /* Write to T[6:0] bits to configure the counter value, no need to do + a read-modify-write; writing a 0 to WDGA bit does nothing */ + WWDG->CR = Counter & BIT_MASK; +} + +/** + * @} + */ + +/** @defgroup WWDG_Group2 WWDG activation functions + * @brief WWDG activation functions + * +@verbatim + ============================================================================== + ##### WWDG activation function ##### + ============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables WWDG and load the counter value. + * @param Counter: specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F (to prevent + * generating an immediate reset). + * @retval None + */ +void WWDG_Enable(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + WWDG->CR = WWDG_CR_WDGA | Counter; +} + +/** + * @} + */ + +/** @defgroup WWDG_Group3 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + ============================================================================== + ##### Interrupts and flags management functions ##### + ============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Checks whether the Early Wakeup interrupt flag is set or not. + * @param None + * @retval The new state of the Early Wakeup interrupt flag (SET or RESET). + */ +FlagStatus WWDG_GetFlagStatus(void) +{ + FlagStatus bitstatus = RESET; + + if ((WWDG->SR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears Early Wakeup interrupt flag. + * @param None + * @retval None + */ +void WWDG_ClearFlag(void) +{ + WWDG->SR = (uint32_t)RESET; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -- 2.39.5